[deliverable/linux.git] / drivers / thermal / tegra / soctherm.c

/*
 * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
 *
 * Author:
 *	Mikko Perttunen <mperttunen@nvidia.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/debugfs.h>
#include <linux/bitops.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/thermal.h>

#include <dt-bindings/thermal/tegra124-soctherm.h>

#include "soctherm.h"

#define SENSOR_CONFIG0				0
#define SENSOR_CONFIG0_STOP			BIT(0)
#define SENSOR_CONFIG0_CPTR_OVER		BIT(2)
#define SENSOR_CONFIG0_OVER			BIT(3)
#define SENSOR_CONFIG0_TCALC_OVER		BIT(4)
#define SENSOR_CONFIG0_TALL_MASK		(0xfffff << 8)
#define SENSOR_CONFIG0_TALL_SHIFT		8

#define SENSOR_CONFIG1				4
#define SENSOR_CONFIG1_TSAMPLE_MASK		0x3ff
#define SENSOR_CONFIG1_TSAMPLE_SHIFT		0
#define SENSOR_CONFIG1_TIDDQ_EN_MASK		(0x3f << 15)
#define SENSOR_CONFIG1_TIDDQ_EN_SHIFT		15
#define SENSOR_CONFIG1_TEN_COUNT_MASK		(0x3f << 24)
#define SENSOR_CONFIG1_TEN_COUNT_SHIFT		24
#define SENSOR_CONFIG1_TEMP_ENABLE		BIT(31)

/*
 * SENSOR_CONFIG2 is defined in soctherm.h
 * because, it will be used by tegra_soctherm_fuse.c
 */

#define SENSOR_STATUS0				0xc
#define SENSOR_STATUS0_VALID_MASK		BIT(31)
#define SENSOR_STATUS0_CAPTURE_MASK		0xffff

#define SENSOR_STATUS1				0x10
#define SENSOR_STATUS1_TEMP_VALID_MASK		BIT(31)
#define SENSOR_STATUS1_TEMP_MASK		0xffff

#define READBACK_VALUE_MASK			0xff00
#define READBACK_VALUE_SHIFT			8
#define READBACK_ADD_HALF			BIT(7)
#define READBACK_NEGATE				BIT(0)

/* get val from register(r) mask bits(m) */
#define REG_GET_MASK(r, m)	(((r) & (m)) >> (ffs(m) - 1))
/* set val(v) to mask bits(m) of register(r) */
#define REG_SET_MASK(r, m, v)	(((r) & ~(m)) | \
				 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))

struct tegra_thermctl_zone {
	void __iomem *reg;
	u32 mask;
};

struct tegra_soctherm {
	struct reset_control *reset;
	struct clk *clock_tsensor;
	struct clk *clock_soctherm;
	void __iomem *regs;

	u32 *calib;
	struct tegra_soctherm_soc *soc;

	struct dentry *debugfs_dir;
};

static int enable_tsensor(struct tegra_soctherm *tegra,
			  unsigned int i,
			  const struct tsensor_shared_calib *shared)
{
	const struct tegra_tsensor *sensor = &tegra->soc->tsensors[i];
	void __iomem *base = tegra->regs + sensor->base;
	u32 *calib = &tegra->calib[i];
	unsigned int val;
	int err;

	err = tegra_calc_tsensor_calib(sensor, shared, calib);
	if (err)
		return err;

	val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT;
	writel(val, base + SENSOR_CONFIG0);

	val  = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT;
	val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
	val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
	val |= SENSOR_CONFIG1_TEMP_ENABLE;
	writel(val, base + SENSOR_CONFIG1);

	writel(*calib, base + SENSOR_CONFIG2);

	return 0;
}

/*
 * Translate from soctherm readback format to millicelsius.
 * The soctherm readback format in bits is as follows:
 *   TTTTTTTT H______N
 * where T's contain the temperature in Celsius,
 * H denotes an addition of 0.5 Celsius and N denotes negation
 * of the final value.
 */
static int translate_temp(u16 val)
{
	int t;

	t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
	if (val & READBACK_ADD_HALF)
		t += 500;
	if (val & READBACK_NEGATE)
		t *= -1;

	return t;
}

static int tegra_thermctl_get_temp(void *data, int *out_temp)
{
	struct tegra_thermctl_zone *zone = data;
	u32 val;

	val = readl(zone->reg);
	val = REG_GET_MASK(val, zone->mask);
	*out_temp = translate_temp(val);

	return 0;
}

static const struct thermal_zone_of_device_ops tegra_of_thermal_ops = {
	.get_temp = tegra_thermctl_get_temp,
};

#ifdef CONFIG_DEBUG_FS
static int regs_show(struct seq_file *s, void *data)
{
	struct platform_device *pdev = s->private;
	struct tegra_soctherm *ts = platform_get_drvdata(pdev);
	const struct tegra_tsensor *tsensors = ts->soc->tsensors;
	u32 r, state;
	int i;

	seq_puts(s, "-----TSENSE (convert HW)-----\n");

	for (i = 0; i < ts->soc->num_tsensors; i++) {
		r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG1);
		state = REG_GET_MASK(r, SENSOR_CONFIG1_TEMP_ENABLE);

		seq_printf(s, "%s: ", tsensors[i].name);
		seq_printf(s, "En(%d) ", state);

		if (!state) {
			seq_puts(s, "\n");
			continue;
		}

		state = REG_GET_MASK(r, SENSOR_CONFIG1_TIDDQ_EN_MASK);
		seq_printf(s, "tiddq(%d) ", state);
		state = REG_GET_MASK(r, SENSOR_CONFIG1_TEN_COUNT_MASK);
		seq_printf(s, "ten_count(%d) ", state);
		state = REG_GET_MASK(r, SENSOR_CONFIG1_TSAMPLE_MASK);
		seq_printf(s, "tsample(%d) ", state + 1);

		r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS1);
		state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_VALID_MASK);
		seq_printf(s, "Temp(%d/", state);
		state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_MASK);
		seq_printf(s, "%d) ", translate_temp(state));

		r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS0);
		state = REG_GET_MASK(r, SENSOR_STATUS0_VALID_MASK);
		seq_printf(s, "Capture(%d/", state);
		state = REG_GET_MASK(r, SENSOR_STATUS0_CAPTURE_MASK);
		seq_printf(s, "%d) ", state);

		r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG0);
		state = REG_GET_MASK(r, SENSOR_CONFIG0_STOP);
		seq_printf(s, "Stop(%d) ", state);
		state = REG_GET_MASK(r, SENSOR_CONFIG0_TALL_MASK);
		seq_printf(s, "Tall(%d) ", state);
		state = REG_GET_MASK(r, SENSOR_CONFIG0_TCALC_OVER);
		seq_printf(s, "Over(%d/", state);
		state = REG_GET_MASK(r, SENSOR_CONFIG0_OVER);
		seq_printf(s, "%d/", state);
		state = REG_GET_MASK(r, SENSOR_CONFIG0_CPTR_OVER);
		seq_printf(s, "%d) ", state);

		r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG2);
		state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMA_MASK);
		seq_printf(s, "Therm_A/B(%d/", state);
		state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMB_MASK);
		seq_printf(s, "%d)\n", (s16)state);
	}

	r = readl(ts->regs + SENSOR_PDIV);
	seq_printf(s, "PDIV: 0x%x\n", r);

	r = readl(ts->regs + SENSOR_HOTSPOT_OFF);
	seq_printf(s, "HOTSPOT: 0x%x\n", r);

	seq_puts(s, "\n");
	seq_puts(s, "-----SOC_THERM-----\n");

	r = readl(ts->regs + SENSOR_TEMP1);
	state = REG_GET_MASK(r, SENSOR_TEMP1_CPU_TEMP_MASK);
	seq_printf(s, "Temperatures: CPU(%d) ", translate_temp(state));
	state = REG_GET_MASK(r, SENSOR_TEMP1_GPU_TEMP_MASK);
	seq_printf(s, " GPU(%d) ", translate_temp(state));
	r = readl(ts->regs + SENSOR_TEMP2);
	state = REG_GET_MASK(r, SENSOR_TEMP2_PLLX_TEMP_MASK);
	seq_printf(s, " PLLX(%d) ", translate_temp(state));
	state = REG_GET_MASK(r, SENSOR_TEMP2_MEM_TEMP_MASK);
	seq_printf(s, " MEM(%d)\n", translate_temp(state));

	return 0;
}

static int regs_open(struct inode *inode, struct file *file)
{
	return single_open(file, regs_show, inode->i_private);
}

static const struct file_operations regs_fops = {
	.open		= regs_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static void soctherm_debug_init(struct platform_device *pdev)
{
	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
	struct dentry *root, *file;

	root = debugfs_create_dir("soctherm", NULL);
	if (!root) {
		dev_err(&pdev->dev, "failed to create debugfs directory\n");
		return;
	}

	tegra->debugfs_dir = root;

	file = debugfs_create_file("reg_contents", 0644, root,
				   pdev, &regs_fops);
	if (!file) {
		dev_err(&pdev->dev, "failed to create debugfs file\n");
		debugfs_remove_recursive(tegra->debugfs_dir);
		tegra->debugfs_dir = NULL;
	}
}
#else
static inline void soctherm_debug_init(struct platform_device *pdev) {}
#endif

static const struct of_device_id tegra_soctherm_of_match[] = {
#ifdef CONFIG_ARCH_TEGRA_124_SOC
	{
		.compatible = "nvidia,tegra124-soctherm",
		.data = &tegra124_soctherm,
	},
#endif
#ifdef CONFIG_ARCH_TEGRA_210_SOC
	{
		.compatible = "nvidia,tegra210-soctherm",
		.data = &tegra210_soctherm,
	},
#endif
	{ },
};
MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);

static int tegra_soctherm_probe(struct platform_device *pdev)
{
	const struct of_device_id *match;
	struct tegra_soctherm *tegra;
	struct thermal_zone_device *z;
	struct tsensor_shared_calib shared_calib;
	struct resource *res;
	struct tegra_soctherm_soc *soc;
	unsigned int i;
	int err;
	u32 pdiv, hotspot;

	match = of_match_node(tegra_soctherm_of_match, pdev->dev.of_node);
	if (!match)
		return -ENODEV;

	soc = (struct tegra_soctherm_soc *)match->data;
	if (soc->num_ttgs > TEGRA124_SOCTHERM_SENSOR_NUM)
		return -EINVAL;

	tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
	if (!tegra)
		return -ENOMEM;

	dev_set_drvdata(&pdev->dev, tegra);

	tegra->soc = soc;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	tegra->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(tegra->regs))
		return PTR_ERR(tegra->regs);

	tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
	if (IS_ERR(tegra->reset)) {
		dev_err(&pdev->dev, "can't get soctherm reset\n");
		return PTR_ERR(tegra->reset);
	}

	tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");
	if (IS_ERR(tegra->clock_tsensor)) {
		dev_err(&pdev->dev, "can't get tsensor clock\n");
		return PTR_ERR(tegra->clock_tsensor);
	}

	tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");
	if (IS_ERR(tegra->clock_soctherm)) {
		dev_err(&pdev->dev, "can't get soctherm clock\n");
		return PTR_ERR(tegra->clock_soctherm);
	}

	reset_control_assert(tegra->reset);

	err = clk_prepare_enable(tegra->clock_soctherm);
	if (err)
		return err;

	err = clk_prepare_enable(tegra->clock_tsensor);
	if (err) {
		clk_disable_unprepare(tegra->clock_soctherm);
		return err;
	}

	reset_control_deassert(tegra->reset);

	/* Initialize raw sensors */

	tegra->calib = devm_kzalloc(&pdev->dev,
				    sizeof(u32) * soc->num_tsensors,
				    GFP_KERNEL);
	if (!tegra->calib) {
		err = -ENOMEM;
		goto disable_clocks;
	}

	err = tegra_calc_shared_calib(soc->tfuse, &shared_calib);
	if (err)
		goto disable_clocks;

	for (i = 0; i < soc->num_tsensors; ++i) {
		err = enable_tsensor(tegra, i, &shared_calib);
		if (err)
			goto disable_clocks;
	}

	/* Program pdiv and hotspot offsets per THERM */
	pdiv = readl(tegra->regs + SENSOR_PDIV);
	hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
	for (i = 0; i < soc->num_ttgs; ++i) {
		pdiv = REG_SET_MASK(pdiv, soc->ttgs[i]->pdiv_mask,
				    soc->ttgs[i]->pdiv);
		/* hotspot offset from PLLX, doesn't need to configure PLLX */
		if (soc->ttgs[i]->id == TEGRA124_SOCTHERM_SENSOR_PLLX)
			continue;
		hotspot =  REG_SET_MASK(hotspot,
					soc->ttgs[i]->pllx_hotspot_mask,
					soc->ttgs[i]->pllx_hotspot_diff);
	}
	writel(pdiv, tegra->regs + SENSOR_PDIV);
	writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);

	/* Initialize thermctl sensors */

	for (i = 0; i < soc->num_ttgs; ++i) {
		struct tegra_thermctl_zone *zone =
			devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
		if (!zone) {
			err = -ENOMEM;
			goto disable_clocks;
		}

		zone->reg = tegra->regs + soc->ttgs[i]->sensor_temp_offset;
		zone->mask = soc->ttgs[i]->sensor_temp_mask;

		z = devm_thermal_zone_of_sensor_register(&pdev->dev,
							 soc->ttgs[i]->id, zone,
							 &tegra_of_thermal_ops);
		if (IS_ERR(z)) {
			err = PTR_ERR(z);
			dev_err(&pdev->dev, "failed to register sensor: %d\n",
				err);
			goto disable_clocks;
		}
	}

	soctherm_debug_init(pdev);

	return 0;

disable_clocks:
	clk_disable_unprepare(tegra->clock_tsensor);
	clk_disable_unprepare(tegra->clock_soctherm);

	return err;
}

static int tegra_soctherm_remove(struct platform_device *pdev)
{
	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);

	debugfs_remove_recursive(tegra->debugfs_dir);

	clk_disable_unprepare(tegra->clock_tsensor);
	clk_disable_unprepare(tegra->clock_soctherm);

	return 0;
}

static struct platform_driver tegra_soctherm_driver = {
	.probe = tegra_soctherm_probe,
	.remove = tegra_soctherm_remove,
	.driver = {
		.name = "tegra_soctherm",
		.of_match_table = tegra_soctherm_of_match,
	},
};
module_platform_driver(tegra_soctherm_driver);

MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
MODULE_DESCRIPTION("NVIDIA Tegra SOCTHERM thermal management driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
65b6d57c WN	1	/*
	2	* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
	3	*
	4	* Author:
	5	* Mikko Perttunen <mperttunen@nvidia.com>
	6	*
	7	* This software is licensed under the terms of the GNU General Public
	8	* License version 2, as published by the Free Software Foundation, and
	9	* may be copied, distributed, and modified under those terms.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	*/
	17
d753b22d	18	#include <linux/debugfs.h>
65b6d57c WN	19	#include <linux/bitops.h>
	20	#include <linux/clk.h>
	21	#include <linux/delay.h>
	22	#include <linux/err.h>
	23	#include <linux/interrupt.h>
	24	#include <linux/io.h>
	25	#include <linux/module.h>
	26	#include <linux/of.h>
	27	#include <linux/platform_device.h>
	28	#include <linux/reset.h>
	29	#include <linux/thermal.h>
	30
	31	#include <dt-bindings/thermal/tegra124-soctherm.h>
	32
	33	#include "soctherm.h"
	34
	35	#define SENSOR_CONFIG0 0
	36	#define SENSOR_CONFIG0_STOP BIT(0)
65b6d57c	37	#define SENSOR_CONFIG0_CPTR_OVER BIT(2)
d753b22d WN	38	#define SENSOR_CONFIG0_OVER BIT(3)
	39	#define SENSOR_CONFIG0_TCALC_OVER BIT(4)
	40	#define SENSOR_CONFIG0_TALL_MASK (0xfffff << 8)
	41	#define SENSOR_CONFIG0_TALL_SHIFT 8
65b6d57c WN	42
65b6d57c WN	43	#define SENSOR_CONFIG1 4
d753b22d	44	#define SENSOR_CONFIG1_TSAMPLE_MASK 0x3ff
65b6d57c	45	#define SENSOR_CONFIG1_TSAMPLE_SHIFT 0
d753b22d	46	#define SENSOR_CONFIG1_TIDDQ_EN_MASK (0x3f << 15)
65b6d57c	47	#define SENSOR_CONFIG1_TIDDQ_EN_SHIFT 15
d753b22d	48	#define SENSOR_CONFIG1_TEN_COUNT_MASK (0x3f << 24)
65b6d57c WN	49	#define SENSOR_CONFIG1_TEN_COUNT_SHIFT 24
	50	#define SENSOR_CONFIG1_TEMP_ENABLE BIT(31)
	51
	52	/*
	53	* SENSOR_CONFIG2 is defined in soctherm.h
	54	* because, it will be used by tegra_soctherm_fuse.c
	55	*/
	56
d753b22d WN	57	#define SENSOR_STATUS0 0xc
	58	#define SENSOR_STATUS0_VALID_MASK BIT(31)
	59	#define SENSOR_STATUS0_CAPTURE_MASK 0xffff
	60
	61	#define SENSOR_STATUS1 0x10
	62	#define SENSOR_STATUS1_TEMP_VALID_MASK BIT(31)
	63	#define SENSOR_STATUS1_TEMP_MASK 0xffff
	64
65b6d57c WN	65	#define READBACK_VALUE_MASK 0xff00
	66	#define READBACK_VALUE_SHIFT 8
	67	#define READBACK_ADD_HALF BIT(7)
	68	#define READBACK_NEGATE BIT(0)
	69
	70	/* get val from register(r) mask bits(m) */
	71	#define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
	72	/* set val(v) to mask bits(m) of register(r) */
	73	#define REG_SET_MASK(r, m, v) (((r) & ~(m)) \| \
	74	(((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
	75
	76	struct tegra_thermctl_zone {
	77	void __iomem *reg;
	78	u32 mask;
	79	};
	80
	81	struct tegra_soctherm {
	82	struct reset_control *reset;
	83	struct clk *clock_tsensor;
	84	struct clk *clock_soctherm;
	85	void __iomem *regs;
	86
	87	u32 *calib;
	88	struct tegra_soctherm_soc *soc;
d753b22d WN	89
d753b22d WN	90	struct dentry *debugfs_dir;
65b6d57c WN	91	};
	92
	93	static int enable_tsensor(struct tegra_soctherm *tegra,
	94	unsigned int i,
	95	const struct tsensor_shared_calib *shared)
	96	{
	97	const struct tegra_tsensor *sensor = &tegra->soc->tsensors[i];
	98	void __iomem *base = tegra->regs + sensor->base;
	99	u32 *calib = &tegra->calib[i];
	100	unsigned int val;
	101	int err;
	102
	103	err = tegra_calc_tsensor_calib(sensor, shared, calib);
	104	if (err)
	105	return err;
	106
	107	val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT;
	108	writel(val, base + SENSOR_CONFIG0);
	109
	110	val = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT;
	111	val \|= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
	112	val \|= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
	113	val \|= SENSOR_CONFIG1_TEMP_ENABLE;
	114	writel(val, base + SENSOR_CONFIG1);
	115
	116	writel(*calib, base + SENSOR_CONFIG2);
	117
	118	return 0;
	119	}
	120
	121	/*
	122	* Translate from soctherm readback format to millicelsius.
	123	* The soctherm readback format in bits is as follows:
	124	* TTTTTTTT H______N
	125	* where T's contain the temperature in Celsius,
	126	* H denotes an addition of 0.5 Celsius and N denotes negation
	127	* of the final value.
	128	*/
	129	static int translate_temp(u16 val)
	130	{
	131	int t;
	132
	133	t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
	134	if (val & READBACK_ADD_HALF)
	135	t += 500;
	136	if (val & READBACK_NEGATE)
	137	t *= -1;
	138
	139	return t;
	140	}
	141
	142	static int tegra_thermctl_get_temp(void data, int out_temp)
	143	{
	144	struct tegra_thermctl_zone *zone = data;
	145	u32 val;
	146
	147	val = readl(zone->reg);
	148	val = REG_GET_MASK(val, zone->mask);
	149	*out_temp = translate_temp(val);
	150
	151	return 0;
	152	}
	153
	154	static const struct thermal_zone_of_device_ops tegra_of_thermal_ops = {
155	.get_temp = tegra_thermctl_get_temp,
156	};
157
d753b22d WN	158	#ifdef CONFIG_DEBUG_FS
	159	static int regs_show(struct seq_file s, void data)
	160	{
	161	struct platform_device *pdev = s->private;
	162	struct tegra_soctherm *ts = platform_get_drvdata(pdev);
	163	const struct tegra_tsensor *tsensors = ts->soc->tsensors;
	164	u32 r, state;
	165	int i;
	166
	167	seq_puts(s, "-----TSENSE (convert HW)-----\n");
	168
	169	for (i = 0; i < ts->soc->num_tsensors; i++) {
	170	r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG1);
	171	state = REG_GET_MASK(r, SENSOR_CONFIG1_TEMP_ENABLE);
	172
	173	seq_printf(s, "%s: ", tsensors[i].name);
	174	seq_printf(s, "En(%d) ", state);
	175
	176	if (!state) {
	177	seq_puts(s, "\n");
	178	continue;
	179	}
	180
	181	state = REG_GET_MASK(r, SENSOR_CONFIG1_TIDDQ_EN_MASK);
	182	seq_printf(s, "tiddq(%d) ", state);
	183	state = REG_GET_MASK(r, SENSOR_CONFIG1_TEN_COUNT_MASK);
	184	seq_printf(s, "ten_count(%d) ", state);
	185	state = REG_GET_MASK(r, SENSOR_CONFIG1_TSAMPLE_MASK);
	186	seq_printf(s, "tsample(%d) ", state + 1);
	187
	188	r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS1);
	189	state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_VALID_MASK);
	190	seq_printf(s, "Temp(%d/", state);
	191	state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_MASK);
	192	seq_printf(s, "%d) ", translate_temp(state));
	193
	194	r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS0);
	195	state = REG_GET_MASK(r, SENSOR_STATUS0_VALID_MASK);
	196	seq_printf(s, "Capture(%d/", state);
	197	state = REG_GET_MASK(r, SENSOR_STATUS0_CAPTURE_MASK);
	198	seq_printf(s, "%d) ", state);
	199
	200	r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG0);
	201	state = REG_GET_MASK(r, SENSOR_CONFIG0_STOP);
	202	seq_printf(s, "Stop(%d) ", state);
	203	state = REG_GET_MASK(r, SENSOR_CONFIG0_TALL_MASK);
	204	seq_printf(s, "Tall(%d) ", state);
	205	state = REG_GET_MASK(r, SENSOR_CONFIG0_TCALC_OVER);
	206	seq_printf(s, "Over(%d/", state);
	207	state = REG_GET_MASK(r, SENSOR_CONFIG0_OVER);
	208	seq_printf(s, "%d/", state);
	209	state = REG_GET_MASK(r, SENSOR_CONFIG0_CPTR_OVER);
	210	seq_printf(s, "%d) ", state);
	211
	212	r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG2);
	213	state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMA_MASK);
	214	seq_printf(s, "Therm_A/B(%d/", state);
	215	state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMB_MASK);
	216	seq_printf(s, "%d)\n", (s16)state);
	217	}
	218
	219	r = readl(ts->regs + SENSOR_PDIV);
	220	seq_printf(s, "PDIV: 0x%x\n", r);
	221
222	r = readl(ts->regs + SENSOR_HOTSPOT_OFF);
223	seq_printf(s, "HOTSPOT: 0x%x\n", r);
224
225	seq_puts(s, "\n");
226	seq_puts(s, "-----SOC_THERM-----\n");
227
228	r = readl(ts->regs + SENSOR_TEMP1);
229	state = REG_GET_MASK(r, SENSOR_TEMP1_CPU_TEMP_MASK);
230	seq_printf(s, "Temperatures: CPU(%d) ", translate_temp(state));
231	state = REG_GET_MASK(r, SENSOR_TEMP1_GPU_TEMP_MASK);
232	seq_printf(s, " GPU(%d) ", translate_temp(state));
233	r = readl(ts->regs + SENSOR_TEMP2);
234	state = REG_GET_MASK(r, SENSOR_TEMP2_PLLX_TEMP_MASK);
235	seq_printf(s, " PLLX(%d) ", translate_temp(state));
236	state = REG_GET_MASK(r, SENSOR_TEMP2_MEM_TEMP_MASK);
237	seq_printf(s, " MEM(%d)\n", translate_temp(state));
238
239	return 0;
240	}
241
242	static int regs_open(struct inode inode, struct file file)
243	{
244	return single_open(file, regs_show, inode->i_private);
245	}
246
247	static const struct file_operations regs_fops = {
248	.open = regs_open,
249	.read = seq_read,
250	.llseek = seq_lseek,
251	.release = single_release,
252	};
253
254	static void soctherm_debug_init(struct platform_device *pdev)
255	{
256	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
257	struct dentry root, file;
258
259	root = debugfs_create_dir("soctherm", NULL);
260	if (!root) {
261	dev_err(&pdev->dev, "failed to create debugfs directory\n");
262	return;
263	}
264
265	tegra->debugfs_dir = root;
266
267	file = debugfs_create_file("reg_contents", 0644, root,
268	pdev, &regs_fops);
269	if (!file) {
270	dev_err(&pdev->dev, "failed to create debugfs file\n");
271	debugfs_remove_recursive(tegra->debugfs_dir);
272	tegra->debugfs_dir = NULL;
273	}
274	}
275	#else
276	static inline void soctherm_debug_init(struct platform_device *pdev) {}
277	#endif
278
65b6d57c WN	279	static const struct of_device_id tegra_soctherm_of_match[] = {
	280	#ifdef CONFIG_ARCH_TEGRA_124_SOC
	281	{
	282	.compatible = "nvidia,tegra124-soctherm",
	283	.data = &tegra124_soctherm,
	284	},
8204104f WN	285	#endif
	286	#ifdef CONFIG_ARCH_TEGRA_210_SOC
	287	{
	288	.compatible = "nvidia,tegra210-soctherm",
	289	.data = &tegra210_soctherm,
	290	},
65b6d57c WN	291	#endif
	292	{ },
	293	};
	294	MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
	295
	296	static int tegra_soctherm_probe(struct platform_device *pdev)
	297	{
	298	const struct of_device_id *match;
	299	struct tegra_soctherm *tegra;
	300	struct thermal_zone_device *z;
	301	struct tsensor_shared_calib shared_calib;
	302	struct resource *res;
	303	struct tegra_soctherm_soc *soc;
	304	unsigned int i;
	305	int err;
	306	u32 pdiv, hotspot;
	307
	308	match = of_match_node(tegra_soctherm_of_match, pdev->dev.of_node);
	309	if (!match)
	310	return -ENODEV;
	311
	312	soc = (struct tegra_soctherm_soc *)match->data;
	313	if (soc->num_ttgs > TEGRA124_SOCTHERM_SENSOR_NUM)
	314	return -EINVAL;
	315
	316	tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
	317	if (!tegra)
	318	return -ENOMEM;
	319
	320	dev_set_drvdata(&pdev->dev, tegra);
	321
	322	tegra->soc = soc;
	323
	324	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	325	tegra->regs = devm_ioremap_resource(&pdev->dev, res);
	326	if (IS_ERR(tegra->regs))
	327	return PTR_ERR(tegra->regs);
	328
	329	tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
	330	if (IS_ERR(tegra->reset)) {
	331	dev_err(&pdev->dev, "can't get soctherm reset\n");
	332	return PTR_ERR(tegra->reset);
	333	}
	334
	335	tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");
	336	if (IS_ERR(tegra->clock_tsensor)) {
	337	dev_err(&pdev->dev, "can't get tsensor clock\n");
	338	return PTR_ERR(tegra->clock_tsensor);
	339	}
	340
	341	tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");
	342	if (IS_ERR(tegra->clock_soctherm)) {
	343	dev_err(&pdev->dev, "can't get soctherm clock\n");
	344	return PTR_ERR(tegra->clock_soctherm);
	345	}
	346
	347	reset_control_assert(tegra->reset);
	348
	349	err = clk_prepare_enable(tegra->clock_soctherm);
	350	if (err)
	351	return err;
	352
	353	err = clk_prepare_enable(tegra->clock_tsensor);
	354	if (err) {
355	clk_disable_unprepare(tegra->clock_soctherm);
356	return err;
357	}
358
359	reset_control_deassert(tegra->reset);
360
361	/* Initialize raw sensors */
362
363	tegra->calib = devm_kzalloc(&pdev->dev,
364	sizeof(u32) * soc->num_tsensors,
365	GFP_KERNEL);
366	if (!tegra->calib) {
367	err = -ENOMEM;
368	goto disable_clocks;
369	}
370
371	err = tegra_calc_shared_calib(soc->tfuse, &shared_calib);
372	if (err)
373	goto disable_clocks;
374
375	for (i = 0; i < soc->num_tsensors; ++i) {
376	err = enable_tsensor(tegra, i, &shared_calib);
377	if (err)
378	goto disable_clocks;
379	}
380
381	/* Program pdiv and hotspot offsets per THERM */
382	pdiv = readl(tegra->regs + SENSOR_PDIV);
383	hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
384	for (i = 0; i < soc->num_ttgs; ++i) {
385	pdiv = REG_SET_MASK(pdiv, soc->ttgs[i]->pdiv_mask,
386	soc->ttgs[i]->pdiv);
387	/* hotspot offset from PLLX, doesn't need to configure PLLX */
388	if (soc->ttgs[i]->id == TEGRA124_SOCTHERM_SENSOR_PLLX)
389	continue;
390	hotspot = REG_SET_MASK(hotspot,
391	soc->ttgs[i]->pllx_hotspot_mask,
392	soc->ttgs[i]->pllx_hotspot_diff);
393	}
394	writel(pdiv, tegra->regs + SENSOR_PDIV);
395	writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
396
397	/* Initialize thermctl sensors */
398
399	for (i = 0; i < soc->num_ttgs; ++i) {
400	struct tegra_thermctl_zone *zone =
401	devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
402	if (!zone) {
403	err = -ENOMEM;
404	goto disable_clocks;
405	}
406
407	zone->reg = tegra->regs + soc->ttgs[i]->sensor_temp_offset;
408	zone->mask = soc->ttgs[i]->sensor_temp_mask;
409
410	z = devm_thermal_zone_of_sensor_register(&pdev->dev,
411	soc->ttgs[i]->id, zone,
412	&tegra_of_thermal_ops);
413	if (IS_ERR(z)) {
414	err = PTR_ERR(z);
415	dev_err(&pdev->dev, "failed to register sensor: %d\n",
416	err);
417	goto disable_clocks;
418	}
419	}
420
d753b22d WN	421	soctherm_debug_init(pdev);
d753b22d WN	422
65b6d57c WN	423	return 0;
	424
	425	disable_clocks:
	426	clk_disable_unprepare(tegra->clock_tsensor);
	427	clk_disable_unprepare(tegra->clock_soctherm);
	428
	429	return err;
	430	}
	431
	432	static int tegra_soctherm_remove(struct platform_device *pdev)
	433	{
	434	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
	435
d753b22d WN	436	debugfs_remove_recursive(tegra->debugfs_dir);
d753b22d WN	437
65b6d57c WN	438	clk_disable_unprepare(tegra->clock_tsensor);
	439	clk_disable_unprepare(tegra->clock_soctherm);
	440
	441	return 0;
	442	}
	443
	444	static struct platform_driver tegra_soctherm_driver = {
	445	.probe = tegra_soctherm_probe,
	446	.remove = tegra_soctherm_remove,
	447	.driver = {
	448	.name = "tegra_soctherm",
	449	.of_match_table = tegra_soctherm_of_match,
	450	},
	451	};
	452	module_platform_driver(tegra_soctherm_driver);
	453
	454	MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
	455	MODULE_DESCRIPTION("NVIDIA Tegra SOCTHERM thermal management driver");
	456	MODULE_LICENSE("GPL v2");