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1 | /* |
2 | * DRA752 bandgap registers, bitfields and temperature definitions | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * Contact: | |
6 | * Eduardo Valentin <eduardo.valentin@ti.com> | |
7 | * Tero Kristo <t-kristo@ti.com> | |
8 | * | |
9 | * This is an auto generated file. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * version 2 as published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, but | |
16 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
23 | * 02110-1301 USA | |
24 | * | |
25 | */ | |
26 | #ifndef __DRA752_BANDGAP_H | |
27 | #define __DRA752_BANDGAP_H | |
28 | ||
29 | /** | |
30 | * *** DRA752 *** | |
31 | * | |
32 | * Below, in sequence, are the Register definitions, | |
33 | * the bitfields and the temperature definitions for DRA752. | |
34 | */ | |
35 | ||
36 | /** | |
37 | * DRA752 register definitions | |
38 | * | |
39 | * Registers are defined as offsets. The offsets are | |
40 | * relative to FUSE_OPP_BGAP_GPU on DRA752. | |
41 | * DRA752_BANDGAP_BASE 0x4a0021e0 | |
42 | * | |
43 | * Register below are grouped by domain (not necessarily in offset order) | |
44 | */ | |
45 | ||
46 | ||
47 | /* DRA752.common register offsets */ | |
48 | #define DRA752_BANDGAP_CTRL_1_OFFSET 0x1a0 | |
49 | #define DRA752_BANDGAP_STATUS_1_OFFSET 0x1c8 | |
50 | #define DRA752_BANDGAP_CTRL_2_OFFSET 0x39c | |
51 | #define DRA752_BANDGAP_STATUS_2_OFFSET 0x3b8 | |
52 | ||
53 | /* DRA752.core register offsets */ | |
54 | #define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8 | |
55 | #define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154 | |
56 | #define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac | |
57 | #define DRA752_BANDGAP_TSHUT_CORE_OFFSET 0x1b8 | |
58 | #define DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET 0x1c4 | |
59 | #define DRA752_DTEMP_CORE_0_OFFSET 0x208 | |
60 | #define DRA752_DTEMP_CORE_1_OFFSET 0x20c | |
61 | #define DRA752_DTEMP_CORE_2_OFFSET 0x210 | |
62 | #define DRA752_DTEMP_CORE_3_OFFSET 0x214 | |
63 | #define DRA752_DTEMP_CORE_4_OFFSET 0x218 | |
64 | ||
65 | /* DRA752.iva register offsets */ | |
66 | #define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET 0x388 | |
67 | #define DRA752_TEMP_SENSOR_IVA_OFFSET 0x398 | |
68 | #define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET 0x3a4 | |
69 | #define DRA752_BANDGAP_TSHUT_IVA_OFFSET 0x3ac | |
70 | #define DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET 0x3b4 | |
71 | #define DRA752_DTEMP_IVA_0_OFFSET 0x3d0 | |
72 | #define DRA752_DTEMP_IVA_1_OFFSET 0x3d4 | |
73 | #define DRA752_DTEMP_IVA_2_OFFSET 0x3d8 | |
74 | #define DRA752_DTEMP_IVA_3_OFFSET 0x3dc | |
75 | #define DRA752_DTEMP_IVA_4_OFFSET 0x3e0 | |
76 | ||
77 | /* DRA752.mpu register offsets */ | |
78 | #define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET 0x4 | |
79 | #define DRA752_TEMP_SENSOR_MPU_OFFSET 0x14c | |
80 | #define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET 0x1a4 | |
81 | #define DRA752_BANDGAP_TSHUT_MPU_OFFSET 0x1b0 | |
82 | #define DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET 0x1bc | |
83 | #define DRA752_DTEMP_MPU_0_OFFSET 0x1e0 | |
84 | #define DRA752_DTEMP_MPU_1_OFFSET 0x1e4 | |
85 | #define DRA752_DTEMP_MPU_2_OFFSET 0x1e8 | |
86 | #define DRA752_DTEMP_MPU_3_OFFSET 0x1ec | |
87 | #define DRA752_DTEMP_MPU_4_OFFSET 0x1f0 | |
88 | ||
89 | /* DRA752.dspeve register offsets */ | |
90 | #define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET 0x384 | |
91 | #define DRA752_TEMP_SENSOR_DSPEVE_OFFSET 0x394 | |
92 | #define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET 0x3a0 | |
93 | #define DRA752_BANDGAP_TSHUT_DSPEVE_OFFSET 0x3a8 | |
94 | #define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET 0x3b0 | |
95 | #define DRA752_DTEMP_DSPEVE_0_OFFSET 0x3bc | |
96 | #define DRA752_DTEMP_DSPEVE_1_OFFSET 0x3c0 | |
97 | #define DRA752_DTEMP_DSPEVE_2_OFFSET 0x3c4 | |
98 | #define DRA752_DTEMP_DSPEVE_3_OFFSET 0x3c8 | |
99 | #define DRA752_DTEMP_DSPEVE_4_OFFSET 0x3cc | |
100 | ||
101 | /* DRA752.gpu register offsets */ | |
102 | #define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET 0x0 | |
103 | #define DRA752_TEMP_SENSOR_GPU_OFFSET 0x150 | |
104 | #define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET 0x1a8 | |
105 | #define DRA752_BANDGAP_TSHUT_GPU_OFFSET 0x1b4 | |
106 | #define DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET 0x1c0 | |
107 | #define DRA752_DTEMP_GPU_0_OFFSET 0x1f4 | |
108 | #define DRA752_DTEMP_GPU_1_OFFSET 0x1f8 | |
109 | #define DRA752_DTEMP_GPU_2_OFFSET 0x1fc | |
110 | #define DRA752_DTEMP_GPU_3_OFFSET 0x200 | |
111 | #define DRA752_DTEMP_GPU_4_OFFSET 0x204 | |
112 | ||
113 | /** | |
114 | * Register bitfields for DRA752 | |
115 | * | |
116 | * All the macros bellow define the required bits for | |
117 | * controlling temperature on DRA752. Bit defines are | |
118 | * grouped by register. | |
119 | */ | |
120 | ||
121 | /* DRA752.BANDGAP_STATUS_1 */ | |
122 | #define DRA752_BANDGAP_STATUS_1_ALERT_MASK BIT(31) | |
123 | #define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK BIT(5) | |
124 | #define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK BIT(4) | |
125 | #define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK BIT(3) | |
126 | #define DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK BIT(2) | |
127 | #define DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK BIT(1) | |
128 | #define DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK BIT(0) | |
129 | ||
130 | /* DRA752.BANDGAP_CTRL_2 */ | |
131 | #define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK BIT(22) | |
132 | #define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK BIT(21) | |
133 | #define DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK BIT(19) | |
134 | #define DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK BIT(18) | |
135 | #define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK BIT(16) | |
136 | #define DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK BIT(15) | |
137 | #define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK BIT(3) | |
138 | #define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK BIT(2) | |
139 | #define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK BIT(1) | |
140 | #define DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK BIT(0) | |
141 | ||
142 | /* DRA752.BANDGAP_STATUS_2 */ | |
143 | #define DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK BIT(3) | |
144 | #define DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK BIT(2) | |
145 | #define DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK BIT(1) | |
146 | #define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK BIT(0) | |
147 | ||
148 | /* DRA752.BANDGAP_CTRL_1 */ | |
149 | #define DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK (0x3 << 30) | |
150 | #define DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK (0x7 << 27) | |
151 | #define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK BIT(23) | |
152 | #define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK BIT(22) | |
153 | #define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK BIT(21) | |
154 | #define DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK BIT(20) | |
155 | #define DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK BIT(19) | |
156 | #define DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK BIT(18) | |
157 | #define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK BIT(17) | |
158 | #define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK BIT(16) | |
159 | #define DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK BIT(15) | |
160 | #define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK BIT(5) | |
161 | #define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK BIT(4) | |
162 | #define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK BIT(3) | |
163 | #define DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK BIT(2) | |
164 | #define DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK BIT(1) | |
165 | #define DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK BIT(0) | |
166 | ||
167 | /* DRA752.TEMP_SENSOR */ | |
168 | #define DRA752_TEMP_SENSOR_TMPSOFF_MASK BIT(11) | |
169 | #define DRA752_TEMP_SENSOR_EOCZ_MASK BIT(10) | |
170 | #define DRA752_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0) | |
171 | ||
172 | /* DRA752.BANDGAP_THRESHOLD */ | |
173 | #define DRA752_BANDGAP_THRESHOLD_HOT_MASK (0x3ff << 16) | |
174 | #define DRA752_BANDGAP_THRESHOLD_COLD_MASK (0x3ff << 0) | |
175 | ||
176 | /* DRA752.TSHUT_THRESHOLD */ | |
177 | #define DRA752_TSHUT_THRESHOLD_MUXCTRL_MASK BIT(31) | |
178 | #define DRA752_TSHUT_THRESHOLD_HOT_MASK (0x3ff << 16) | |
179 | #define DRA752_TSHUT_THRESHOLD_COLD_MASK (0x3ff << 0) | |
180 | ||
181 | /* DRA752.BANDGAP_CUMUL_DTEMP_CORE */ | |
182 | #define DRA752_BANDGAP_CUMUL_DTEMP_CORE_MASK (0xffffffff << 0) | |
183 | ||
184 | /* DRA752.BANDGAP_CUMUL_DTEMP_IVA */ | |
185 | #define DRA752_BANDGAP_CUMUL_DTEMP_IVA_MASK (0xffffffff << 0) | |
186 | ||
187 | /* DRA752.BANDGAP_CUMUL_DTEMP_MPU */ | |
188 | #define DRA752_BANDGAP_CUMUL_DTEMP_MPU_MASK (0xffffffff << 0) | |
189 | ||
190 | /* DRA752.BANDGAP_CUMUL_DTEMP_DSPEVE */ | |
191 | #define DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_MASK (0xffffffff << 0) | |
192 | ||
193 | /* DRA752.BANDGAP_CUMUL_DTEMP_GPU */ | |
194 | #define DRA752_BANDGAP_CUMUL_DTEMP_GPU_MASK (0xffffffff << 0) | |
195 | ||
196 | /** | |
197 | * Temperature limits and thresholds for DRA752 | |
198 | * | |
199 | * All the macros bellow are definitions for handling the | |
200 | * ADC conversions and representation of temperature limits | |
201 | * and thresholds for DRA752. Definitions are grouped | |
202 | * by temperature domain. | |
203 | */ | |
204 | ||
205 | /* DRA752.common temperature definitions */ | |
206 | /* ADC conversion table limits */ | |
207 | #define DRA752_ADC_START_VALUE 540 | |
208 | #define DRA752_ADC_END_VALUE 945 | |
209 | ||
210 | /* DRA752.GPU temperature definitions */ | |
211 | /* bandgap clock limits */ | |
212 | #define DRA752_GPU_MAX_FREQ 1500000 | |
213 | #define DRA752_GPU_MIN_FREQ 1000000 | |
214 | /* sensor limits */ | |
215 | #define DRA752_GPU_MIN_TEMP -40000 | |
216 | #define DRA752_GPU_MAX_TEMP 125000 | |
217 | #define DRA752_GPU_HYST_VAL 5000 | |
218 | /* interrupts thresholds */ | |
219 | #define DRA752_GPU_TSHUT_HOT 915 | |
220 | #define DRA752_GPU_TSHUT_COLD 900 | |
221 | #define DRA752_GPU_T_HOT 800 | |
222 | #define DRA752_GPU_T_COLD 795 | |
223 | ||
224 | /* DRA752.MPU temperature definitions */ | |
225 | /* bandgap clock limits */ | |
226 | #define DRA752_MPU_MAX_FREQ 1500000 | |
227 | #define DRA752_MPU_MIN_FREQ 1000000 | |
228 | /* sensor limits */ | |
229 | #define DRA752_MPU_MIN_TEMP -40000 | |
230 | #define DRA752_MPU_MAX_TEMP 125000 | |
231 | #define DRA752_MPU_HYST_VAL 5000 | |
232 | /* interrupts thresholds */ | |
233 | #define DRA752_MPU_TSHUT_HOT 915 | |
234 | #define DRA752_MPU_TSHUT_COLD 900 | |
235 | #define DRA752_MPU_T_HOT 800 | |
236 | #define DRA752_MPU_T_COLD 795 | |
237 | ||
238 | /* DRA752.CORE temperature definitions */ | |
239 | /* bandgap clock limits */ | |
240 | #define DRA752_CORE_MAX_FREQ 1500000 | |
241 | #define DRA752_CORE_MIN_FREQ 1000000 | |
242 | /* sensor limits */ | |
243 | #define DRA752_CORE_MIN_TEMP -40000 | |
244 | #define DRA752_CORE_MAX_TEMP 125000 | |
245 | #define DRA752_CORE_HYST_VAL 5000 | |
246 | /* interrupts thresholds */ | |
247 | #define DRA752_CORE_TSHUT_HOT 915 | |
248 | #define DRA752_CORE_TSHUT_COLD 900 | |
249 | #define DRA752_CORE_T_HOT 800 | |
250 | #define DRA752_CORE_T_COLD 795 | |
251 | ||
252 | /* DRA752.DSPEVE temperature definitions */ | |
253 | /* bandgap clock limits */ | |
254 | #define DRA752_DSPEVE_MAX_FREQ 1500000 | |
255 | #define DRA752_DSPEVE_MIN_FREQ 1000000 | |
256 | /* sensor limits */ | |
257 | #define DRA752_DSPEVE_MIN_TEMP -40000 | |
258 | #define DRA752_DSPEVE_MAX_TEMP 125000 | |
259 | #define DRA752_DSPEVE_HYST_VAL 5000 | |
260 | /* interrupts thresholds */ | |
261 | #define DRA752_DSPEVE_TSHUT_HOT 915 | |
262 | #define DRA752_DSPEVE_TSHUT_COLD 900 | |
263 | #define DRA752_DSPEVE_T_HOT 800 | |
264 | #define DRA752_DSPEVE_T_COLD 795 | |
265 | ||
266 | /* DRA752.IVA temperature definitions */ | |
267 | /* bandgap clock limits */ | |
268 | #define DRA752_IVA_MAX_FREQ 1500000 | |
269 | #define DRA752_IVA_MIN_FREQ 1000000 | |
270 | /* sensor limits */ | |
271 | #define DRA752_IVA_MIN_TEMP -40000 | |
272 | #define DRA752_IVA_MAX_TEMP 125000 | |
273 | #define DRA752_IVA_HYST_VAL 5000 | |
274 | /* interrupts thresholds */ | |
275 | #define DRA752_IVA_TSHUT_HOT 915 | |
276 | #define DRA752_IVA_TSHUT_COLD 900 | |
277 | #define DRA752_IVA_T_HOT 800 | |
278 | #define DRA752_IVA_T_COLD 795 | |
279 | ||
280 | #endif /* __DRA752_BANDGAP_H */ |