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usb: fix sillies in the metro USB driver
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
1da177e4
LT		 13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
1da177e4
LT		 18
19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
1da177e4 29#include <linux/delay.h>
d052d1be 30#include <linux/platform_device.h>
1da177e4 31#include <linux/tty.h>
cd3ecad1 32#include <linux/ratelimit.h>
1da177e4
LT		 33#include <linux/tty_flip.h>
34#include <linux/serial_reg.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
78512ece 38#include <linux/nmi.h>
f392ecfa 39#include <linux/mutex.h>
5a0e3ad6 40#include <linux/slab.h>
6816383a
PG		 41#ifdef CONFIG_SPARC
42#include <linux/sunserialcore.h>
43#endif
1da177e4
LT		 44
45#include <asm/io.h>
46#include <asm/irq.h>
47
48#include "8250.h"
49
50/*
51 * Configuration:
40663cc7 52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 53 * is unsafe when used on edge-triggered interrupts.
54 */
408b664a 55static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 56
a61c2d78
DJ		 57static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
8440838b
DM		 59static struct uart_driver serial8250_reg;
60
61static int serial_index(struct uart_port *port)
62{
63 return (serial8250_reg.minor - 64) + port->line;
64}
65
d41a4b51
CE		 66static unsigned int skip_txen_test; /* force skip of txen test at init time */
67
1da177e4
LT		 68/*
69 * Debugging.
70 */
71#if 0
72#define DEBUG_AUTOCONF(fmt...) printk(fmt)
73#else
74#define DEBUG_AUTOCONF(fmt...) do { } while (0)
75#endif
76
77#if 0
78#define DEBUG_INTR(fmt...) printk(fmt)
79#else
80#define DEBUG_INTR(fmt...) do { } while (0)
81#endif
82
e7328ae1 83#define PASS_LIMIT 512
1da177e4 84
bca47613
DH		 85#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
86
87
1da177e4
LT		 88#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89#define CONFIG_SERIAL_DETECT_IRQ 1
90#endif
1da177e4
LT		 91#ifdef CONFIG_SERIAL_8250_MANY_PORTS
92#define CONFIG_SERIAL_MANY_PORTS 1
93#endif
94
95/*
96 * HUB6 is always on. This will be removed once the header
97 * files have been cleaned.
98 */
99#define CONFIG_HUB6 1
100
a4ed1e41 101#include <asm/serial.h>
1da177e4
LT		 102/*
103 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * standard enumeration mechanism. Platforms that can find all
105 * serial ports via mechanisms like ACPI or PCI need not supply it.
106 */
107#ifndef SERIAL_PORT_DFNS
108#define SERIAL_PORT_DFNS
109#endif
110
cb3592be 111static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
113};
114
026d02a2 115#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 116
117#ifdef CONFIG_SERIAL_8250_RSA
118
119#define PORT_RSA_MAX 4
120static unsigned long probe_rsa[PORT_RSA_MAX];
121static unsigned int probe_rsa_count;
122#endif /* CONFIG_SERIAL_8250_RSA */
123
1da177e4 124struct irq_info {
25db8ad5
AC		 125 struct hlist_node node;
126 int irq;
127 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 128 struct list_head *head;
129};
130
25db8ad5
AC		 131#define NR_IRQ_HASH 32 /* Can be adjusted later */
132static struct hlist_head irq_lists[NR_IRQ_HASH];
133static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 134
135/*
136 * Here we define the default xmit fifo size used for each type of UART.
137 */
138static const struct serial8250_config uart_config[] = {
139 [PORT_UNKNOWN] = {
140 .name = "unknown",
141 .fifo_size = 1,
142 .tx_loadsz = 1,
143 },
144 [PORT_8250] = {
145 .name = "8250",
146 .fifo_size = 1,
147 .tx_loadsz = 1,
148 },
149 [PORT_16450] = {
150 .name = "16450",
151 .fifo_size = 1,
152 .tx_loadsz = 1,
153 },
154 [PORT_16550] = {
155 .name = "16550",
156 .fifo_size = 1,
157 .tx_loadsz = 1,
158 },
159 [PORT_16550A] = {
160 .name = "16550A",
161 .fifo_size = 16,
162 .tx_loadsz = 16,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO,
165 },
166 [PORT_CIRRUS] = {
167 .name = "Cirrus",
168 .fifo_size = 1,
169 .tx_loadsz = 1,
170 },
171 [PORT_16650] = {
172 .name = "ST16650",
173 .fifo_size = 1,
174 .tx_loadsz = 1,
175 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
176 },
177 [PORT_16650V2] = {
178 .name = "ST16650V2",
179 .fifo_size = 32,
180 .tx_loadsz = 16,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
182 UART_FCR_T_TRIG_00,
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184 },
185 [PORT_16750] = {
186 .name = "TI16750",
187 .fifo_size = 64,
188 .tx_loadsz = 64,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
190 UART_FCR7_64BYTE,
191 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
192 },
193 [PORT_STARTECH] = {
194 .name = "Startech",
195 .fifo_size = 1,
196 .tx_loadsz = 1,
197 },
198 [PORT_16C950] = {
199 .name = "16C950/954",
200 .fifo_size = 128,
201 .tx_loadsz = 128,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
d0694e2a
PM		 203 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
1da177e4
LT		 205 },
206 [PORT_16654] = {
207 .name = "ST16654",
208 .fifo_size = 64,
209 .tx_loadsz = 32,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
211 UART_FCR_T_TRIG_10,
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
213 },
214 [PORT_16850] = {
215 .name = "XR16850",
216 .fifo_size = 128,
217 .tx_loadsz = 128,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220 },
221 [PORT_RSA] = {
222 .name = "RSA",
223 .fifo_size = 2048,
224 .tx_loadsz = 2048,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226 .flags = UART_CAP_FIFO,
227 },
228 [PORT_NS16550A] = {
229 .name = "NS16550A",
230 .fifo_size = 16,
231 .tx_loadsz = 16,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_NATSEMI,
234 },
235 [PORT_XSCALE] = {
236 .name = "XScale",
237 .fifo_size = 32,
238 .tx_loadsz = 32,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
4539c24f 240 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
1da177e4 241 },
bd71c182
TK		 242 [PORT_RM9000] = {
243 .name = "RM9000",
244 .fifo_size = 16,
245 .tx_loadsz = 16,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 247 .flags = UART_CAP_FIFO,
248 },
249 [PORT_OCTEON] = {
250 .name = "OCTEON",
251 .fifo_size = 64,
252 .tx_loadsz = 64,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 254 .flags = UART_CAP_FIFO,
255 },
08e0992f
FF		 256 [PORT_AR7] = {
257 .name = "AR7",
258 .fifo_size = 16,
259 .tx_loadsz = 16,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
261 .flags = UART_CAP_FIFO | UART_CAP_AFE,
262 },
235dae5d
PL		 263 [PORT_U6_16550A] = {
264 .name = "U6_16550A",
265 .fifo_size = 64,
266 .tx_loadsz = 64,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO | UART_CAP_AFE,
269 },
4539c24f
SW		 270 [PORT_TEGRA] = {
271 .name = "Tegra",
272 .fifo_size = 32,
273 .tx_loadsz = 8,
274 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
275 UART_FCR_T_TRIG_01,
276 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
277 },
06315348
SH		 278 [PORT_XR17D15X] = {
279 .name = "XR17D15X",
280 .fifo_size = 64,
281 .tx_loadsz = 64,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
283 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
284 },
7a514596
RS		 285 [PORT_LPC3220] = {
286 .name = "LPC3220",
287 .fifo_size = 64,
288 .tx_loadsz = 32,
289 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
290 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
291 .flags = UART_CAP_FIFO,
292 },
1da177e4
LT		 293};
294
cc419fa0 295/* Uart divisor latch read */
e8155629 296static int default_serial_dl_read(struct uart_8250_port *up)
cc419fa0
MD		 297{
298 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
299}
300
301/* Uart divisor latch write */
e8155629 302static void default_serial_dl_write(struct uart_8250_port *up, int value)
cc419fa0
MD		 303{
304 serial_out(up, UART_DLL, value & 0xff);
305 serial_out(up, UART_DLM, value >> 8 & 0xff);
306}
307
6b416031 308#ifdef CONFIG_MIPS_ALCHEMY
21c614a7
PA		 309
310/* Au1x00 UART hardware has a weird register layout */
311static const u8 au_io_in_map[] = {
312 [UART_RX] = 0,
313 [UART_IER] = 2,
314 [UART_IIR] = 3,
315 [UART_LCR] = 5,
316 [UART_MCR] = 6,
317 [UART_LSR] = 7,
318 [UART_MSR] = 8,
319};
320
321static const u8 au_io_out_map[] = {
322 [UART_TX] = 1,
323 [UART_IER] = 2,
324 [UART_FCR] = 4,
325 [UART_LCR] = 5,
326 [UART_MCR] = 6,
327};
328
6b416031 329static unsigned int au_serial_in(struct uart_port *p, int offset)
21c614a7 330{
6b416031
MD		 331 offset = au_io_in_map[offset] << p->regshift;
332 return __raw_readl(p->membase + offset);
21c614a7
PA		 333}
334
6b416031 335static void au_serial_out(struct uart_port *p, int offset, int value)
21c614a7 336{
6b416031
MD		 337 offset = au_io_out_map[offset] << p->regshift;
338 __raw_writel(value, p->membase + offset);
339}
340
341/* Au1x00 haven't got a standard divisor latch */
342static int au_serial_dl_read(struct uart_8250_port *up)
343{
344 return __raw_readl(up->port.membase + 0x28);
345}
346
347static void au_serial_dl_write(struct uart_8250_port *up, int value)
348{
349 __raw_writel(value, up->port.membase + 0x28);
21c614a7
PA		 350}
351
6b416031
MD		 352#endif
353
28bf4cf2 354#ifdef CONFIG_SERIAL_8250_RM9K
bd71c182
TK		 355
356static const u8
357 regmap_in[8] = {
358 [UART_RX] = 0x00,
359 [UART_IER] = 0x0c,
360 [UART_IIR] = 0x14,
361 [UART_LCR] = 0x1c,
362 [UART_MCR] = 0x20,
363 [UART_LSR] = 0x24,
364 [UART_MSR] = 0x28,
365 [UART_SCR] = 0x2c
366 },
367 regmap_out[8] = {
368 [UART_TX] = 0x04,
369 [UART_IER] = 0x0c,
370 [UART_FCR] = 0x18,
371 [UART_LCR] = 0x1c,
372 [UART_MCR] = 0x20,
373 [UART_LSR] = 0x24,
374 [UART_MSR] = 0x28,
375 [UART_SCR] = 0x2c
376 };
377
28bf4cf2 378static unsigned int rm9k_serial_in(struct uart_port *p, int offset)
bd71c182 379{
28bf4cf2
MD		 380 offset = regmap_in[offset] << p->regshift;
381 return readl(p->membase + offset);
bd71c182
TK		 382}
383
28bf4cf2 384static void rm9k_serial_out(struct uart_port *p, int offset, int value)
bd71c182 385{
28bf4cf2
MD		 386 offset = regmap_out[offset] << p->regshift;
387 writel(value, p->membase + offset);
bd71c182
TK		 388}
389
28bf4cf2
MD		 390static int rm9k_serial_dl_read(struct uart_8250_port *up)
391{
392 return ((__raw_readl(up->port.membase + 0x10) << 8) |
393 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff;
394}
395
396static void rm9k_serial_dl_write(struct uart_8250_port *up, int value)
397{
398 __raw_writel(value, up->port.membase + 0x08);
399 __raw_writel(value >> 8, up->port.membase + 0x10);
400}
401
402#endif
21c614a7 403
7d6a07d1 404static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 405{
e8155629 406 offset = offset << p->regshift;
7d6a07d1
DD		 407 outb(p->hub6 - 1 + offset, p->iobase);
408 return inb(p->iobase + 1);
409}
1da177e4 410
7d6a07d1
DD		 411static void hub6_serial_out(struct uart_port *p, int offset, int value)
412{
e8155629 413 offset = offset << p->regshift;
7d6a07d1
DD		 414 outb(p->hub6 - 1 + offset, p->iobase);
415 outb(value, p->iobase + 1);
416}
1da177e4 417
7d6a07d1
DD		 418static unsigned int mem_serial_in(struct uart_port *p, int offset)
419{
e8155629 420 offset = offset << p->regshift;
7d6a07d1
DD		 421 return readb(p->membase + offset);
422}
1da177e4 423
7d6a07d1
DD		 424static void mem_serial_out(struct uart_port *p, int offset, int value)
425{
e8155629 426 offset = offset << p->regshift;
7d6a07d1
DD		 427 writeb(value, p->membase + offset);
428}
429
430static void mem32_serial_out(struct uart_port *p, int offset, int value)
431{
e8155629 432 offset = offset << p->regshift;
7d6a07d1
DD		 433 writel(value, p->membase + offset);
434}
435
436static unsigned int mem32_serial_in(struct uart_port *p, int offset)
437{
e8155629 438 offset = offset << p->regshift;
7d6a07d1
DD		 439 return readl(p->membase + offset);
440}
1da177e4 441
7d6a07d1
DD		 442static unsigned int io_serial_in(struct uart_port *p, int offset)
443{
e8155629 444 offset = offset << p->regshift;
7d6a07d1
DD		 445 return inb(p->iobase + offset);
446}
447
448static void io_serial_out(struct uart_port *p, int offset, int value)
449{
e8155629 450 offset = offset << p->regshift;
7d6a07d1
DD		 451 outb(value, p->iobase + offset);
452}
453
583d28e9
JI		 454static int serial8250_default_handle_irq(struct uart_port *port);
455
7d6a07d1
DD		 456static void set_io_from_upio(struct uart_port *p)
457{
49d5741b
JI		 458 struct uart_8250_port *up =
459 container_of(p, struct uart_8250_port, port);
cc419fa0 460
e8155629
MD		 461 up->dl_read = default_serial_dl_read;
462 up->dl_write = default_serial_dl_write;
cc419fa0 463
7d6a07d1 464 switch (p->iotype) {
1da177e4 465 case UPIO_HUB6:
7d6a07d1
DD		 466 p->serial_in = hub6_serial_in;
467 p->serial_out = hub6_serial_out;
1da177e4
LT		 468 break;
469
470 case UPIO_MEM:
7d6a07d1
DD		 471 p->serial_in = mem_serial_in;
472 p->serial_out = mem_serial_out;
1da177e4
LT		 473 break;
474
475 case UPIO_MEM32:
7d6a07d1
DD		 476 p->serial_in = mem32_serial_in;
477 p->serial_out = mem32_serial_out;
1da177e4
LT		 478 break;
479
28bf4cf2
MD		 480#ifdef CONFIG_SERIAL_8250_RM9K
481 case UPIO_RM9000:
482 p->serial_in = rm9k_serial_in;
483 p->serial_out = rm9k_serial_out;
484 up->dl_read = rm9k_serial_dl_read;
485 up->dl_write = rm9k_serial_dl_write;
486 break;
487#endif
488
6b416031 489#ifdef CONFIG_MIPS_ALCHEMY
21c614a7 490 case UPIO_AU:
7d6a07d1
DD		 491 p->serial_in = au_serial_in;
492 p->serial_out = au_serial_out;
6b416031
MD		 493 up->dl_read = au_serial_dl_read;
494 up->dl_write = au_serial_dl_write;
21c614a7 495 break;
6b416031 496#endif
12bf3f24 497
1da177e4 498 default:
7d6a07d1
DD		 499 p->serial_in = io_serial_in;
500 p->serial_out = io_serial_out;
501 break;
1da177e4 502 }
b8e7e40a
AC		 503 /* Remember loaded iotype */
504 up->cur_iotype = p->iotype;
583d28e9 505 p->handle_irq = serial8250_default_handle_irq;
1da177e4
LT		 506}
507
40b36daa 508static void
55e4016d 509serial_port_out_sync(struct uart_port *p, int offset, int value)
40b36daa 510{
7d6a07d1 511 switch (p->iotype) {
40b36daa
AW		 512 case UPIO_MEM:
513 case UPIO_MEM32:
40b36daa 514 case UPIO_AU:
7d6a07d1
DD		 515 p->serial_out(p, offset, value);
516 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 517 break;
518 default:
7d6a07d1 519 p->serial_out(p, offset, value);
40b36daa
AW		 520 }
521}
522
1da177e4
LT		 523/*
524 * For the 16C950
525 */
526static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
527{
528 serial_out(up, UART_SCR, offset);
529 serial_out(up, UART_ICR, value);
530}
531
532static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
533{
534 unsigned int value;
535
536 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
537 serial_out(up, UART_SCR, offset);
538 value = serial_in(up, UART_ICR);
539 serial_icr_write(up, UART_ACR, up->acr);
540
541 return value;
542}
543
544/*
545 * FIFO support.
546 */
b5d674ab 547static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 548{
549 if (p->capabilities & UART_CAP_FIFO) {
0acf519f
PG		 550 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
551 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
1da177e4 552 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0acf519f 553 serial_out(p, UART_FCR, 0);
1da177e4
LT		 554 }
555}
556
0ad372b9
SM		 557void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
558{
559 unsigned char fcr;
560
561 serial8250_clear_fifos(p);
562 fcr = uart_config[p->port.type].fcr;
563 serial_out(p, UART_FCR, fcr);
564}
565EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
566
1da177e4
LT		 567/*
568 * IER sleep support. UARTs which have EFRs need the "extended
569 * capability" bit enabled. Note that on XR16C850s, we need to
570 * reset LCR to write to IER.
571 */
b5d674ab 572static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4
LT		 573{
574 if (p->capabilities & UART_CAP_SLEEP) {
575 if (p->capabilities & UART_CAP_EFR) {
0acf519f
PG		 576 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
577 serial_out(p, UART_EFR, UART_EFR_ECB);
578 serial_out(p, UART_LCR, 0);
1da177e4 579 }
0acf519f 580 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
1da177e4 581 if (p->capabilities & UART_CAP_EFR) {
0acf519f
PG		 582 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
583 serial_out(p, UART_EFR, 0);
584 serial_out(p, UART_LCR, 0);
1da177e4
LT		 585 }
586 }
587}
588
589#ifdef CONFIG_SERIAL_8250_RSA
590/*
591 * Attempts to turn on the RSA FIFO. Returns zero on failure.
592 * We set the port uart clock rate if we succeed.
593 */
594static int __enable_rsa(struct uart_8250_port *up)
595{
596 unsigned char mode;
597 int result;
598
0acf519f 599 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 600 result = mode & UART_RSA_MSR_FIFO;
601
602 if (!result) {
0acf519f
PG		 603 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
604 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 605 result = mode & UART_RSA_MSR_FIFO;
606 }
607
608 if (result)
609 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
610
611 return result;
612}
613
614static void enable_rsa(struct uart_8250_port *up)
615{
616 if (up->port.type == PORT_RSA) {
617 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
618 spin_lock_irq(&up->port.lock);
619 __enable_rsa(up);
620 spin_unlock_irq(&up->port.lock);
621 }
622 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
0acf519f 623 serial_out(up, UART_RSA_FRR, 0);
1da177e4
LT		 624 }
625}
626
627/*
628 * Attempts to turn off the RSA FIFO. Returns zero on failure.
629 * It is unknown why interrupts were disabled in here. However,
630 * the caller is expected to preserve this behaviour by grabbing
631 * the spinlock before calling this function.
632 */
633static void disable_rsa(struct uart_8250_port *up)
634{
635 unsigned char mode;
636 int result;
637
638 if (up->port.type == PORT_RSA &&
639 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
640 spin_lock_irq(&up->port.lock);
641
0acf519f 642 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 643 result = !(mode & UART_RSA_MSR_FIFO);
644
645 if (!result) {
0acf519f
PG		 646 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
647 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 648 result = !(mode & UART_RSA_MSR_FIFO);
649 }
650
651 if (result)
652 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
653 spin_unlock_irq(&up->port.lock);
654 }
655}
656#endif /* CONFIG_SERIAL_8250_RSA */
657
658/*
659 * This is a quickie test to see how big the FIFO is.
660 * It doesn't work at all the time, more's the pity.
661 */
662static int size_fifo(struct uart_8250_port *up)
663{
b32b19b8
JAH		 664 unsigned char old_fcr, old_mcr, old_lcr;
665 unsigned short old_dl;
1da177e4
LT		 666 int count;
667
0acf519f
PG		 668 old_lcr = serial_in(up, UART_LCR);
669 serial_out(up, UART_LCR, 0);
670 old_fcr = serial_in(up, UART_FCR);
671 old_mcr = serial_in(up, UART_MCR);
672 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1da177e4 673 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0acf519f
PG		 674 serial_out(up, UART_MCR, UART_MCR_LOOP);
675 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8
JAH		 676 old_dl = serial_dl_read(up);
677 serial_dl_write(up, 0x0001);
0acf519f 678 serial_out(up, UART_LCR, 0x03);
1da177e4 679 for (count = 0; count < 256; count++)
0acf519f 680 serial_out(up, UART_TX, count);
1da177e4 681 mdelay(20);/* FIXME - schedule_timeout */
0acf519f 682 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
1da177e4 683 (count < 256); count++)
0acf519f
PG		 684 serial_in(up, UART_RX);
685 serial_out(up, UART_FCR, old_fcr);
686 serial_out(up, UART_MCR, old_mcr);
687 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8 688 serial_dl_write(up, old_dl);
0acf519f 689 serial_out(up, UART_LCR, old_lcr);
1da177e4
LT		 690
691 return count;
692}
693
694/*
695 * Read UART ID using the divisor method - set DLL and DLM to zero
696 * and the revision will be in DLL and device type in DLM. We
697 * preserve the device state across this.
698 */
699static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
700{
701 unsigned char old_dll, old_dlm, old_lcr;
702 unsigned int id;
703
0acf519f
PG		 704 old_lcr = serial_in(p, UART_LCR);
705 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4 706
0acf519f
PG		 707 old_dll = serial_in(p, UART_DLL);
708 old_dlm = serial_in(p, UART_DLM);
1da177e4 709
0acf519f
PG		 710 serial_out(p, UART_DLL, 0);
711 serial_out(p, UART_DLM, 0);
1da177e4 712
0acf519f 713 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
1da177e4 714
0acf519f
PG		 715 serial_out(p, UART_DLL, old_dll);
716 serial_out(p, UART_DLM, old_dlm);
717 serial_out(p, UART_LCR, old_lcr);
1da177e4
LT		 718
719 return id;
720}
721
722/*
723 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
724 * When this function is called we know it is at least a StarTech
725 * 16650 V2, but it might be one of several StarTech UARTs, or one of
726 * its clones. (We treat the broken original StarTech 16650 V1 as a
727 * 16550, and why not? Startech doesn't seem to even acknowledge its
728 * existence.)
bd71c182 729 *
1da177e4
LT		 730 * What evil have men's minds wrought...
731 */
732static void autoconfig_has_efr(struct uart_8250_port *up)
733{
734 unsigned int id1, id2, id3, rev;
735
736 /*
737 * Everything with an EFR has SLEEP
738 */
739 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
740
741 /*
742 * First we check to see if it's an Oxford Semiconductor UART.
743 *
744 * If we have to do this here because some non-National
745 * Semiconductor clone chips lock up if you try writing to the
746 * LSR register (which serial_icr_read does)
747 */
748
749 /*
750 * Check for Oxford Semiconductor 16C950.
751 *
752 * EFR [4] must be set else this test fails.
753 *
754 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
755 * claims that it's needed for 952 dual UART's (which are not
756 * recommended for new designs).
757 */
758 up->acr = 0;
662b083a 759 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 760 serial_out(up, UART_EFR, UART_EFR_ECB);
761 serial_out(up, UART_LCR, 0x00);
762 id1 = serial_icr_read(up, UART_ID1);
763 id2 = serial_icr_read(up, UART_ID2);
764 id3 = serial_icr_read(up, UART_ID3);
765 rev = serial_icr_read(up, UART_REV);
766
767 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
768
769 if (id1 == 0x16 && id2 == 0xC9 &&
770 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
771 up->port.type = PORT_16C950;
4ba5e35d
RK		 772
773 /*
774 * Enable work around for the Oxford Semiconductor 952 rev B
775 * chip which causes it to seriously miscalculate baud rates
776 * when DLL is 0.
777 */
778 if (id3 == 0x52 && rev == 0x01)
779 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 780 return;
781 }
bd71c182 782
1da177e4
LT		 783 /*
784 * We check for a XR16C850 by setting DLL and DLM to 0, and then
785 * reading back DLL and DLM. The chip type depends on the DLM
786 * value read back:
787 * 0x10 - XR16C850 and the DLL contains the chip revision.
788 * 0x12 - XR16C2850.
789 * 0x14 - XR16C854.
790 */
791 id1 = autoconfig_read_divisor_id(up);
792 DEBUG_AUTOCONF("850id=%04x ", id1);
793
794 id2 = id1 >> 8;
795 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 796 up->port.type = PORT_16850;
797 return;
798 }
799
800 /*
801 * It wasn't an XR16C850.
802 *
803 * We distinguish between the '654 and the '650 by counting
804 * how many bytes are in the FIFO. I'm using this for now,
805 * since that's the technique that was sent to me in the
806 * serial driver update, but I'm not convinced this works.
807 * I've had problems doing this in the past. -TYT
808 */
809 if (size_fifo(up) == 64)
810 up->port.type = PORT_16654;
811 else
812 up->port.type = PORT_16650V2;
813}
814
815/*
816 * We detected a chip without a FIFO. Only two fall into
817 * this category - the original 8250 and the 16450. The
818 * 16450 has a scratch register (accessible with LCR=0)
819 */
820static void autoconfig_8250(struct uart_8250_port *up)
821{
822 unsigned char scratch, status1, status2;
823
824 up->port.type = PORT_8250;
825
826 scratch = serial_in(up, UART_SCR);
0acf519f 827 serial_out(up, UART_SCR, 0xa5);
1da177e4 828 status1 = serial_in(up, UART_SCR);
0acf519f 829 serial_out(up, UART_SCR, 0x5a);
1da177e4 830 status2 = serial_in(up, UART_SCR);
0acf519f 831 serial_out(up, UART_SCR, scratch);
1da177e4
LT		 832
833 if (status1 == 0xa5 && status2 == 0x5a)
834 up->port.type = PORT_16450;
835}
836
837static int broken_efr(struct uart_8250_port *up)
838{
839 /*
840 * Exar ST16C2550 "A2" devices incorrectly detect as
841 * having an EFR, and report an ID of 0x0201. See
631dd1a8 842 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1da177e4
LT		 843 */
844 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
845 return 1;
846
847 return 0;
848}
849
0d0389e5
YK		 850static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
851{
852 unsigned char status;
853
854 status = serial_in(up, 0x04); /* EXCR2 */
855#define PRESL(x) ((x) & 0x30)
856 if (PRESL(status) == 0x10) {
857 /* already in high speed mode */
858 return 0;
859 } else {
860 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
861 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
0acf519f 862 serial_out(up, 0x04, status);
0d0389e5
YK		 863 }
864 return 1;
865}
866
1da177e4
LT		 867/*
868 * We know that the chip has FIFOs. Does it have an EFR? The
869 * EFR is located in the same register position as the IIR and
870 * we know the top two bits of the IIR are currently set. The
871 * EFR should contain zero. Try to read the EFR.
872 */
873static void autoconfig_16550a(struct uart_8250_port *up)
874{
875 unsigned char status1, status2;
876 unsigned int iersave;
877
878 up->port.type = PORT_16550A;
879 up->capabilities |= UART_CAP_FIFO;
880
881 /*
882 * Check for presence of the EFR when DLAB is set.
883 * Only ST16C650V1 UARTs pass this test.
884 */
0acf519f 885 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4 886 if (serial_in(up, UART_EFR) == 0) {
0acf519f 887 serial_out(up, UART_EFR, 0xA8);
1da177e4
LT		 888 if (serial_in(up, UART_EFR) != 0) {
889 DEBUG_AUTOCONF("EFRv1 ");
890 up->port.type = PORT_16650;
891 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
892 } else {
893 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
894 }
0acf519f 895 serial_out(up, UART_EFR, 0);
1da177e4
LT		 896 return;
897 }
898
899 /*
900 * Maybe it requires 0xbf to be written to the LCR.
901 * (other ST16C650V2 UARTs, TI16C752A, etc)
902 */
0acf519f 903 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 904 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
905 DEBUG_AUTOCONF("EFRv2 ");
906 autoconfig_has_efr(up);
907 return;
908 }
909
910 /*
911 * Check for a National Semiconductor SuperIO chip.
912 * Attempt to switch to bank 2, read the value of the LOOP bit
913 * from EXCR1. Switch back to bank 0, change it in MCR. Then
914 * switch back to bank 2, read it from EXCR1 again and check
915 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4 916 */
0acf519f 917 serial_out(up, UART_LCR, 0);
1da177e4 918 status1 = serial_in(up, UART_MCR);
0acf519f 919 serial_out(up, UART_LCR, 0xE0);
1da177e4
LT		 920 status2 = serial_in(up, 0x02); /* EXCR1 */
921
922 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
0acf519f
PG		 923 serial_out(up, UART_LCR, 0);
924 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
925 serial_out(up, UART_LCR, 0xE0);
1da177e4 926 status2 = serial_in(up, 0x02); /* EXCR1 */
0acf519f
PG		 927 serial_out(up, UART_LCR, 0);
928 serial_out(up, UART_MCR, status1);
1da177e4
LT		 929
930 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 931 unsigned short quot;
932
0acf519f 933 serial_out(up, UART_LCR, 0xE0);
857dde2e 934
b32b19b8 935 quot = serial_dl_read(up);
857dde2e
DW		 936 quot <<= 3;
937
0d0389e5
YK		 938 if (ns16550a_goto_highspeed(up))
939 serial_dl_write(up, quot);
857dde2e 940
0acf519f 941 serial_out(up, UART_LCR, 0);
1da177e4 942
857dde2e 943 up->port.uartclk = 921600*16;
1da177e4
LT		 944 up->port.type = PORT_NS16550A;
945 up->capabilities |= UART_NATSEMI;
946 return;
947 }
948 }
949
950 /*
951 * No EFR. Try to detect a TI16750, which only sets bit 5 of
952 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
953 * Try setting it with and without DLAB set. Cheap clones
954 * set bit 5 without DLAB set.
955 */
0acf519f
PG		 956 serial_out(up, UART_LCR, 0);
957 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1da177e4 958 status1 = serial_in(up, UART_IIR) >> 5;
0acf519f
PG		 959 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
960 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
961 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1da177e4 962 status2 = serial_in(up, UART_IIR) >> 5;
0acf519f
PG		 963 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
964 serial_out(up, UART_LCR, 0);
1da177e4
LT		 965
966 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
967
968 if (status1 == 6 && status2 == 7) {
969 up->port.type = PORT_16750;
970 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
971 return;
972 }
973
974 /*
975 * Try writing and reading the UART_IER_UUE bit (b6).
976 * If it works, this is probably one of the Xscale platform's
977 * internal UARTs.
978 * We're going to explicitly set the UUE bit to 0 before
979 * trying to write and read a 1 just to make sure it's not
980 * already a 1 and maybe locked there before we even start start.
981 */
982 iersave = serial_in(up, UART_IER);
0acf519f 983 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1da177e4
LT		 984 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
985 /*
986 * OK it's in a known zero state, try writing and reading
987 * without disturbing the current state of the other bits.
988 */
0acf519f 989 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1da177e4
LT		 990 if (serial_in(up, UART_IER) & UART_IER_UUE) {
991 /*
992 * It's an Xscale.
993 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
994 */
995 DEBUG_AUTOCONF("Xscale ");
996 up->port.type = PORT_XSCALE;
5568181f 997 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1da177e4
LT		 998 return;
999 }
1000 } else {
1001 /*
1002 * If we got here we couldn't force the IER_UUE bit to 0.
1003 * Log it and continue.
1004 */
1005 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1006 }
0acf519f 1007 serial_out(up, UART_IER, iersave);
235dae5d 1008
06315348
SH		 1009 /*
1010 * Exar uarts have EFR in a weird location
1011 */
1012 if (up->port.flags & UPF_EXAR_EFR) {
1013 up->port.type = PORT_XR17D15X;
1014 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1015 }
1016
235dae5d
PL		 1017 /*
1018 * We distinguish between 16550A and U6 16550A by counting
1019 * how many bytes are in the FIFO.
1020 */
1021 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1022 up->port.type = PORT_U6_16550A;
1023 up->capabilities |= UART_CAP_AFE;
1024 }
1da177e4
LT		 1025}
1026
1027/*
1028 * This routine is called by rs_init() to initialize a specific serial
1029 * port. It determines what type of UART chip this serial port is
1030 * using: 8250, 16450, 16550, 16550A. The important question is
1031 * whether or not this UART is a 16550A or not, since this will
1032 * determine whether or not we can use its FIFO features or not.
1033 */
1034static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1035{
1036 unsigned char status1, scratch, scratch2, scratch3;
1037 unsigned char save_lcr, save_mcr;
dfe42443 1038 struct uart_port *port = &up->port;
1da177e4
LT		 1039 unsigned long flags;
1040
dfe42443 1041 if (!port->iobase && !port->mapbase && !port->membase)
1da177e4
LT		 1042 return;
1043
80647b95 1044 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
dfe42443 1045 serial_index(port), port->iobase, port->membase);
1da177e4
LT		 1046
1047 /*
1048 * We really do need global IRQs disabled here - we're going to
1049 * be frobbing the chips IRQ enable register to see if it exists.
1050 */
dfe42443 1051 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 1052
1053 up->capabilities = 0;
4ba5e35d 1054 up->bugs = 0;
1da177e4 1055
dfe42443 1056 if (!(port->flags & UPF_BUGGY_UART)) {
1da177e4
LT		 1057 /*
1058 * Do a simple existence test first; if we fail this,
1059 * there's no point trying anything else.
bd71c182 1060 *
1da177e4
LT		 1061 * 0x80 is used as a nonsense port to prevent against
1062 * false positives due to ISA bus float. The
1063 * assumption is that 0x80 is a non-existent port;
1064 * which should be safe since include/asm/io.h also
1065 * makes this assumption.
1066 *
1067 * Note: this is safe as long as MCR bit 4 is clear
1068 * and the device is in "PC" mode.
1069 */
0acf519f
PG		 1070 scratch = serial_in(up, UART_IER);
1071 serial_out(up, UART_IER, 0);
1da177e4
LT		 1072#ifdef __i386__
1073 outb(0xff, 0x080);
1074#endif
48212008
TH		 1075 /*
1076 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1077 * 16C754B) allow only to modify them if an EFR bit is set.
1078 */
0acf519f
PG		 1079 scratch2 = serial_in(up, UART_IER) & 0x0f;
1080 serial_out(up, UART_IER, 0x0F);
1da177e4
LT		 1081#ifdef __i386__
1082 outb(0, 0x080);
1083#endif
0acf519f
PG		 1084 scratch3 = serial_in(up, UART_IER) & 0x0f;
1085 serial_out(up, UART_IER, scratch);
1da177e4
LT		 1086 if (scratch2 != 0 || scratch3 != 0x0F) {
1087 /*
1088 * We failed; there's nothing here
1089 */
1090 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1091 scratch2, scratch3);
1092 goto out;
1093 }
1094 }
1095
1096 save_mcr = serial_in(up, UART_MCR);
1097 save_lcr = serial_in(up, UART_LCR);
1098
bd71c182 1099 /*
1da177e4
LT		 1100 * Check to see if a UART is really there. Certain broken
1101 * internal modems based on the Rockwell chipset fail this
1102 * test, because they apparently don't implement the loopback
1103 * test mode. So this test is skipped on the COM 1 through
1104 * COM 4 ports. This *should* be safe, since no board
1105 * manufacturer would be stupid enough to design a board
1106 * that conflicts with COM 1-4 --- we hope!
1107 */
dfe42443 1108 if (!(port->flags & UPF_SKIP_TEST)) {
0acf519f
PG		 1109 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1110 status1 = serial_in(up, UART_MSR) & 0xF0;
1111 serial_out(up, UART_MCR, save_mcr);
1da177e4
LT		 1112 if (status1 != 0x90) {
1113 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1114 status1);
1115 goto out;
1116 }
1117 }
1118
1119 /*
1120 * We're pretty sure there's a port here. Lets find out what
1121 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1122 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1123 * determines what we test for next.
1124 *
1125 * We also initialise the EFR (if any) to zero for later. The
1126 * EFR occupies the same register location as the FCR and IIR.
1127 */
0acf519f
PG		 1128 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1129 serial_out(up, UART_EFR, 0);
1130 serial_out(up, UART_LCR, 0);
1da177e4 1131
0acf519f 1132 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1da177e4
LT		 1133 scratch = serial_in(up, UART_IIR) >> 6;
1134
1135 DEBUG_AUTOCONF("iir=%d ", scratch);
1136
1137 switch (scratch) {
1138 case 0:
1139 autoconfig_8250(up);
1140 break;
1141 case 1:
dfe42443 1142 port->type = PORT_UNKNOWN;
1da177e4
LT		 1143 break;
1144 case 2:
dfe42443 1145 port->type = PORT_16550;
1da177e4
LT		 1146 break;
1147 case 3:
1148 autoconfig_16550a(up);
1149 break;
1150 }
1151
1152#ifdef CONFIG_SERIAL_8250_RSA
1153 /*
1154 * Only probe for RSA ports if we got the region.
1155 */
dfe42443 1156 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1da177e4
LT		 1157 int i;
1158
1159 for (i = 0 ; i < probe_rsa_count; ++i) {
dfe42443
PG		 1160 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1161 port->type = PORT_RSA;
1da177e4
LT		 1162 break;
1163 }
1164 }
1165 }
1166#endif
21c614a7 1167
0acf519f 1168 serial_out(up, UART_LCR, save_lcr);
1da177e4 1169
dfe42443 1170 if (up->capabilities != uart_config[port->type].flags) {
1da177e4
LT		 1171 printk(KERN_WARNING
1172 "ttyS%d: detected caps %08x should be %08x\n",
dfe42443
PG		 1173 serial_index(port), up->capabilities,
1174 uart_config[port->type].flags);
1da177e4
LT		 1175 }
1176
dfe42443
PG		 1177 port->fifosize = uart_config[up->port.type].fifo_size;
1178 up->capabilities = uart_config[port->type].flags;
1179 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1da177e4 1180
dfe42443 1181 if (port->type == PORT_UNKNOWN)
1da177e4
LT		 1182 goto out;
1183
1184 /*
1185 * Reset the UART.
1186 */
1187#ifdef CONFIG_SERIAL_8250_RSA
dfe42443 1188 if (port->type == PORT_RSA)
0acf519f 1189 serial_out(up, UART_RSA_FRR, 0);
1da177e4 1190#endif
0acf519f 1191 serial_out(up, UART_MCR, save_mcr);
1da177e4 1192 serial8250_clear_fifos(up);
40b36daa 1193 serial_in(up, UART_RX);
5c8c755c 1194 if (up->capabilities & UART_CAP_UUE)
0acf519f 1195 serial_out(up, UART_IER, UART_IER_UUE);
5c8c755c 1196 else
0acf519f 1197 serial_out(up, UART_IER, 0);
1da177e4 1198
bd71c182 1199 out:
dfe42443
PG		 1200 spin_unlock_irqrestore(&port->lock, flags);
1201 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1da177e4
LT		 1202}
1203
1204static void autoconfig_irq(struct uart_8250_port *up)
1205{
dfe42443 1206 struct uart_port *port = &up->port;
1da177e4
LT		 1207 unsigned char save_mcr, save_ier;
1208 unsigned char save_ICP = 0;
1209 unsigned int ICP = 0;
1210 unsigned long irqs;
1211 int irq;
1212
dfe42443
PG		 1213 if (port->flags & UPF_FOURPORT) {
1214 ICP = (port->iobase & 0xfe0) | 0x1f;
1da177e4
LT		 1215 save_ICP = inb_p(ICP);
1216 outb_p(0x80, ICP);
0d263a26 1217 inb_p(ICP);
1da177e4
LT		 1218 }
1219
1220 /* forget possible initially masked and pending IRQ */
1221 probe_irq_off(probe_irq_on());
0acf519f
PG		 1222 save_mcr = serial_in(up, UART_MCR);
1223 save_ier = serial_in(up, UART_IER);
1224 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1225
1da177e4 1226 irqs = probe_irq_on();
0acf519f 1227 serial_out(up, UART_MCR, 0);
6f803cd0 1228 udelay(10);
dfe42443 1229 if (port->flags & UPF_FOURPORT) {
0acf519f 1230 serial_out(up, UART_MCR,
1da177e4
LT		 1231 UART_MCR_DTR | UART_MCR_RTS);
1232 } else {
0acf519f 1233 serial_out(up, UART_MCR,
1da177e4
LT		 1234 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1235 }
0acf519f 1236 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
0d263a26
PG		 1237 serial_in(up, UART_LSR);
1238 serial_in(up, UART_RX);
1239 serial_in(up, UART_IIR);
1240 serial_in(up, UART_MSR);
0acf519f 1241 serial_out(up, UART_TX, 0xFF);
6f803cd0 1242 udelay(20);
1da177e4
LT		 1243 irq = probe_irq_off(irqs);
1244
0acf519f
PG		 1245 serial_out(up, UART_MCR, save_mcr);
1246 serial_out(up, UART_IER, save_ier);
1da177e4 1247
dfe42443 1248 if (port->flags & UPF_FOURPORT)
1da177e4
LT		 1249 outb_p(save_ICP, ICP);
1250
dfe42443 1251 port->irq = (irq > 0) ? irq : 0;
1da177e4
LT		 1252}
1253
e763b90c
RK		 1254static inline void __stop_tx(struct uart_8250_port *p)
1255{
1256 if (p->ier & UART_IER_THRI) {
1257 p->ier &= ~UART_IER_THRI;
1258 serial_out(p, UART_IER, p->ier);
1259 }
1260}
1261
b129a8cc 1262static void serial8250_stop_tx(struct uart_port *port)
1da177e4 1263{
49d5741b
JI		 1264 struct uart_8250_port *up =
1265 container_of(port, struct uart_8250_port, port);
1da177e4 1266
e763b90c 1267 __stop_tx(up);
1da177e4
LT		 1268
1269 /*
e763b90c 1270 * We really want to stop the transmitter from sending.
1da177e4 1271 */
dfe42443 1272 if (port->type == PORT_16C950) {
1da177e4
LT		 1273 up->acr |= UART_ACR_TXDIS;
1274 serial_icr_write(up, UART_ACR, up->acr);
1275 }
1276}
1277
b129a8cc 1278static void serial8250_start_tx(struct uart_port *port)
1da177e4 1279{
49d5741b
JI		 1280 struct uart_8250_port *up =
1281 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1282
1283 if (!(up->ier & UART_IER_THRI)) {
1284 up->ier |= UART_IER_THRI;
4fd996a1 1285 serial_port_out(port, UART_IER, up->ier);
55d3b282 1286
67f7654e 1287 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1288 unsigned char lsr;
55d3b282 1289 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1290 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
dfe42443 1291 if ((port->type == PORT_RM9000) ?
68cb4f8e
IJ		 1292 (lsr & UART_LSR_THRE) :
1293 (lsr & UART_LSR_TEMT))
3986fb2b 1294 serial8250_tx_chars(up);
55d3b282 1295 }
1da177e4 1296 }
e763b90c 1297
1da177e4 1298 /*
e763b90c 1299 * Re-enable the transmitter if we disabled it.
1da177e4 1300 */
dfe42443 1301 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1302 up->acr &= ~UART_ACR_TXDIS;
1303 serial_icr_write(up, UART_ACR, up->acr);
1304 }
1305}
1306
1307static void serial8250_stop_rx(struct uart_port *port)
1308{
49d5741b
JI		 1309 struct uart_8250_port *up =
1310 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1311
1312 up->ier &= ~UART_IER_RLSI;
1313 up->port.read_status_mask &= ~UART_LSR_DR;
4fd996a1 1314 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 1315}
1316
1317static void serial8250_enable_ms(struct uart_port *port)
1318{
49d5741b
JI		 1319 struct uart_8250_port *up =
1320 container_of(port, struct uart_8250_port, port);
1da177e4 1321
21c614a7
PA		 1322 /* no MSR capabilities */
1323 if (up->bugs & UART_BUG_NOMSR)
1324 return;
1325
1da177e4 1326 up->ier |= UART_IER_MSI;
4fd996a1 1327 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 1328}
1329
0690f41f 1330/*
3986fb2b 1331 * serial8250_rx_chars: processes according to the passed in LSR
0690f41f
PG		 1332 * value, and returns the remaining LSR bits not handled
1333 * by this Rx routine.
1334 */
3986fb2b
PG		 1335unsigned char
1336serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1da177e4 1337{
dfe42443
PG		 1338 struct uart_port *port = &up->port;
1339 struct tty_struct *tty = port->state->port.tty;
0690f41f 1340 unsigned char ch;
1da177e4
LT		 1341 int max_count = 256;
1342 char flag;
1343
1344 do {
7500b1f6 1345 if (likely(lsr & UART_LSR_DR))
0acf519f 1346 ch = serial_in(up, UART_RX);
7500b1f6
AR		 1347 else
1348 /*
1349 * Intel 82571 has a Serial Over Lan device that will
1350 * set UART_LSR_BI without setting UART_LSR_DR when
1351 * it receives a break. To avoid reading from the
1352 * receive buffer without UART_LSR_DR bit set, we
1353 * just force the read character to be 0
1354 */
1355 ch = 0;
1356
1da177e4 1357 flag = TTY_NORMAL;
dfe42443 1358 port->icount.rx++;
1da177e4 1359
ad4c2aa6
CM		 1360 lsr |= up->lsr_saved_flags;
1361 up->lsr_saved_flags = 0;
1da177e4 1362
ad4c2aa6 1363 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1364 if (lsr & UART_LSR_BI) {
1365 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
dfe42443 1366 port->icount.brk++;
1da177e4
LT		 1367 /*
1368 * We do the SysRQ and SAK checking
1369 * here because otherwise the break
1370 * may get masked by ignore_status_mask
1371 * or read_status_mask.
1372 */
dfe42443 1373 if (uart_handle_break(port))
1da177e4
LT		 1374 goto ignore_char;
1375 } else if (lsr & UART_LSR_PE)
dfe42443 1376 port->icount.parity++;
1da177e4 1377 else if (lsr & UART_LSR_FE)
dfe42443 1378 port->icount.frame++;
1da177e4 1379 if (lsr & UART_LSR_OE)
dfe42443 1380 port->icount.overrun++;
1da177e4
LT		 1381
1382 /*
23907eb8 1383 * Mask off conditions which should be ignored.
1da177e4 1384 */
dfe42443 1385 lsr &= port->read_status_mask;
1da177e4
LT		 1386
1387 if (lsr & UART_LSR_BI) {
1388 DEBUG_INTR("handling break....");
1389 flag = TTY_BREAK;
1390 } else if (lsr & UART_LSR_PE)
1391 flag = TTY_PARITY;
1392 else if (lsr & UART_LSR_FE)
1393 flag = TTY_FRAME;
1394 }
dfe42443 1395 if (uart_handle_sysrq_char(port, ch))
1da177e4 1396 goto ignore_char;
05ab3014 1397
dfe42443 1398 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
05ab3014 1399
6f803cd0 1400ignore_char:
0acf519f 1401 lsr = serial_in(up, UART_LSR);
7500b1f6 1402 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
dfe42443 1403 spin_unlock(&port->lock);
1da177e4 1404 tty_flip_buffer_push(tty);
dfe42443 1405 spin_lock(&port->lock);
0690f41f 1406 return lsr;
1da177e4 1407}
3986fb2b 1408EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1da177e4 1409
3986fb2b 1410void serial8250_tx_chars(struct uart_8250_port *up)
1da177e4 1411{
dfe42443
PG		 1412 struct uart_port *port = &up->port;
1413 struct circ_buf *xmit = &port->state->xmit;
1da177e4
LT		 1414 int count;
1415
dfe42443
PG		 1416 if (port->x_char) {
1417 serial_out(up, UART_TX, port->x_char);
1418 port->icount.tx++;
1419 port->x_char = 0;
1da177e4
LT		 1420 return;
1421 }
dfe42443
PG		 1422 if (uart_tx_stopped(port)) {
1423 serial8250_stop_tx(port);
b129a8cc
RK		 1424 return;
1425 }
1426 if (uart_circ_empty(xmit)) {
e763b90c 1427 __stop_tx(up);
1da177e4
LT		 1428 return;
1429 }
1430
1431 count = up->tx_loadsz;
1432 do {
1433 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1434 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
dfe42443 1435 port->icount.tx++;
1da177e4
LT		 1436 if (uart_circ_empty(xmit))
1437 break;
1438 } while (--count > 0);
1439
1440 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
dfe42443 1441 uart_write_wakeup(port);
1da177e4
LT		 1442
1443 DEBUG_INTR("THRE...");
1444
1445 if (uart_circ_empty(xmit))
e763b90c 1446 __stop_tx(up);
1da177e4 1447}
3986fb2b 1448EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1da177e4 1449
3986fb2b 1450unsigned int serial8250_modem_status(struct uart_8250_port *up)
1da177e4 1451{
dfe42443 1452 struct uart_port *port = &up->port;
2af7cd68
RK		 1453 unsigned int status = serial_in(up, UART_MSR);
1454
ad4c2aa6
CM		 1455 status |= up->msr_saved_flags;
1456 up->msr_saved_flags = 0;
fdc30b3d 1457 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
dfe42443 1458 port->state != NULL) {
2af7cd68 1459 if (status & UART_MSR_TERI)
dfe42443 1460 port->icount.rng++;
2af7cd68 1461 if (status & UART_MSR_DDSR)
dfe42443 1462 port->icount.dsr++;
2af7cd68 1463 if (status & UART_MSR_DDCD)
dfe42443 1464 uart_handle_dcd_change(port, status & UART_MSR_DCD);
2af7cd68 1465 if (status & UART_MSR_DCTS)
dfe42443 1466 uart_handle_cts_change(port, status & UART_MSR_CTS);
2af7cd68 1467
dfe42443 1468 wake_up_interruptible(&port->state->port.delta_msr_wait);
2af7cd68 1469 }
1da177e4 1470
2af7cd68 1471 return status;
1da177e4 1472}
3986fb2b 1473EXPORT_SYMBOL_GPL(serial8250_modem_status);
1da177e4
LT		 1474
1475/*
1476 * This handles the interrupt from one port.
1477 */
86b21199 1478int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1da177e4 1479{
0690f41f 1480 unsigned char status;
4bf3631c 1481 unsigned long flags;
86b21199
PG		 1482 struct uart_8250_port *up =
1483 container_of(port, struct uart_8250_port, port);
1484
1485 if (iir & UART_IIR_NO_INT)
1486 return 0;
45e24601 1487
dfe42443 1488 spin_lock_irqsave(&port->lock, flags);
45e24601 1489
4fd996a1 1490 status = serial_port_in(port, UART_LSR);
1da177e4
LT		 1491
1492 DEBUG_INTR("status = %x...", status);
1493
7500b1f6 1494 if (status & (UART_LSR_DR | UART_LSR_BI))
3986fb2b
PG		 1495 status = serial8250_rx_chars(up, status);
1496 serial8250_modem_status(up);
1da177e4 1497 if (status & UART_LSR_THRE)
3986fb2b 1498 serial8250_tx_chars(up);
45e24601 1499
dfe42443 1500 spin_unlock_irqrestore(&port->lock, flags);
86b21199 1501 return 1;
583d28e9 1502}
c7a1bdc5 1503EXPORT_SYMBOL_GPL(serial8250_handle_irq);
583d28e9
JI		 1504
1505static int serial8250_default_handle_irq(struct uart_port *port)
1506{
4fd996a1 1507 unsigned int iir = serial_port_in(port, UART_IIR);
583d28e9
JI		 1508
1509 return serial8250_handle_irq(port, iir);
1510}
1511
1da177e4
LT		 1512/*
1513 * This is the serial driver's interrupt routine.
1514 *
1515 * Arjan thinks the old way was overly complex, so it got simplified.
1516 * Alan disagrees, saying that need the complexity to handle the weird
1517 * nature of ISA shared interrupts. (This is a special exception.)
1518 *
1519 * In order to handle ISA shared interrupts properly, we need to check
1520 * that all ports have been serviced, and therefore the ISA interrupt
1521 * line has been de-asserted.
1522 *
1523 * This means we need to loop through all ports. checking that they
1524 * don't have an interrupt pending.
1525 */
7d12e780 1526static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1527{
1528 struct irq_info *i = dev_id;
1529 struct list_head *l, *end = NULL;
1530 int pass_counter = 0, handled = 0;
1531
1532 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1533
1534 spin_lock(&i->lock);
1535
1536 l = i->head;
1537 do {
1538 struct uart_8250_port *up;
583d28e9 1539 struct uart_port *port;
1da177e4
LT		 1540
1541 up = list_entry(l, struct uart_8250_port, list);
583d28e9 1542 port = &up->port;
1da177e4 1543
49b532f9 1544 if (port->handle_irq(port)) {
1da177e4 1545 handled = 1;
1da177e4
LT		 1546 end = NULL;
1547 } else if (end == NULL)
1548 end = l;
1549
1550 l = l->next;
1551
1552 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1553 /* If we hit this, we're dead. */
cd3ecad1
DD		 1554 printk_ratelimited(KERN_ERR
1555 "serial8250: too much work for irq%d\n", irq);
1da177e4
LT		 1556 break;
1557 }
1558 } while (l != end);
1559
1560 spin_unlock(&i->lock);
1561
1562 DEBUG_INTR("end.\n");
1563
1564 return IRQ_RETVAL(handled);
1565}
1566
1567/*
1568 * To support ISA shared interrupts, we need to have one interrupt
1569 * handler that ensures that the IRQ line has been deasserted
1570 * before returning. Failing to do this will result in the IRQ
1571 * line being stuck active, and, since ISA irqs are edge triggered,
1572 * no more IRQs will be seen.
1573 */
1574static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1575{
1576 spin_lock_irq(&i->lock);
1577
1578 if (!list_empty(i->head)) {
1579 if (i->head == &up->list)
1580 i->head = i->head->next;
1581 list_del(&up->list);
1582 } else {
1583 BUG_ON(i->head != &up->list);
1584 i->head = NULL;
1585 }
1da177e4 1586 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1587 /* List empty so throw away the hash node */
1588 if (i->head == NULL) {
1589 hlist_del(&i->node);
1590 kfree(i);
1591 }
1da177e4
LT		 1592}
1593
1594static int serial_link_irq_chain(struct uart_8250_port *up)
1595{
25db8ad5
AC		 1596 struct hlist_head *h;
1597 struct hlist_node *n;
1598 struct irq_info *i;
40663cc7 1599 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1600
25db8ad5
AC		 1601 mutex_lock(&hash_mutex);
1602
1603 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1604
1605 hlist_for_each(n, h) {
1606 i = hlist_entry(n, struct irq_info, node);
1607 if (i->irq == up->port.irq)
1608 break;
1609 }
1610
1611 if (n == NULL) {
1612 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1613 if (i == NULL) {
1614 mutex_unlock(&hash_mutex);
1615 return -ENOMEM;
1616 }
1617 spin_lock_init(&i->lock);
1618 i->irq = up->port.irq;
1619 hlist_add_head(&i->node, h);
1620 }
1621 mutex_unlock(&hash_mutex);
1622
1da177e4
LT		 1623 spin_lock_irq(&i->lock);
1624
1625 if (i->head) {
1626 list_add(&up->list, i->head);
1627 spin_unlock_irq(&i->lock);
1628
1629 ret = 0;
1630 } else {
1631 INIT_LIST_HEAD(&up->list);
1632 i->head = &up->list;
1633 spin_unlock_irq(&i->lock);
1c2f0493 1634 irq_flags |= up->port.irqflags;
1da177e4
LT		 1635 ret = request_irq(up->port.irq, serial8250_interrupt,
1636 irq_flags, "serial", i);
1637 if (ret < 0)
1638 serial_do_unlink(i, up);
1639 }
1640
1641 return ret;
1642}
1643
1644static void serial_unlink_irq_chain(struct uart_8250_port *up)
1645{
25db8ad5
AC		 1646 struct irq_info *i;
1647 struct hlist_node *n;
1648 struct hlist_head *h;
1da177e4 1649
25db8ad5
AC		 1650 mutex_lock(&hash_mutex);
1651
1652 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1653
1654 hlist_for_each(n, h) {
1655 i = hlist_entry(n, struct irq_info, node);
1656 if (i->irq == up->port.irq)
1657 break;
1658 }
1659
1660 BUG_ON(n == NULL);
1da177e4
LT		 1661 BUG_ON(i->head == NULL);
1662
1663 if (list_empty(i->head))
1664 free_irq(up->port.irq, i);
1665
1666 serial_do_unlink(i, up);
25db8ad5 1667 mutex_unlock(&hash_mutex);
1da177e4
LT		 1668}
1669
1670/*
1671 * This function is used to handle ports that do not have an
1672 * interrupt. This doesn't work very well for 16450's, but gives
1673 * barely passable results for a 16550A. (Although at the expense
1674 * of much CPU overhead).
1675 */
1676static void serial8250_timeout(unsigned long data)
1677{
1678 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4 1679
a0431476 1680 up->port.handle_irq(&up->port);
54381067 1681 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
40b36daa
AW		 1682}
1683
1684static void serial8250_backup_timeout(unsigned long data)
1685{
1686 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1687 unsigned int iir, ier = 0, lsr;
1688 unsigned long flags;
40b36daa 1689
dbb3b1ca
AC		 1690 spin_lock_irqsave(&up->port.lock, flags);
1691
40b36daa
AW		 1692 /*
1693 * Must disable interrupts or else we risk racing with the interrupt
1694 * based handler.
1695 */
d4e33fac 1696 if (up->port.irq) {
40b36daa
AW		 1697 ier = serial_in(up, UART_IER);
1698 serial_out(up, UART_IER, 0);
1699 }
1da177e4 1700
40b36daa
AW		 1701 iir = serial_in(up, UART_IIR);
1702
1703 /*
1704 * This should be a safe test for anyone who doesn't trust the
1705 * IIR bits on their UART, but it's specifically designed for
1706 * the "Diva" UART used on the management processor on many HP
1707 * ia64 and parisc boxes.
1708 */
ad4c2aa6
CM		 1709 lsr = serial_in(up, UART_LSR);
1710 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
40b36daa 1711 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1712 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1713 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1714 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1715 iir |= UART_IIR_THRI;
1716 }
1717
1718 if (!(iir & UART_IIR_NO_INT))
3986fb2b 1719 serial8250_tx_chars(up);
40b36daa 1720
d4e33fac 1721 if (up->port.irq)
40b36daa
AW		 1722 serial_out(up, UART_IER, ier);
1723
dbb3b1ca
AC		 1724 spin_unlock_irqrestore(&up->port.lock, flags);
1725
40b36daa 1726 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0 1727 mod_timer(&up->timer,
54381067 1728 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1da177e4
LT		 1729}
1730
1731static unsigned int serial8250_tx_empty(struct uart_port *port)
1732{
49d5741b
JI		 1733 struct uart_8250_port *up =
1734 container_of(port, struct uart_8250_port, port);
1da177e4 1735 unsigned long flags;
ad4c2aa6 1736 unsigned int lsr;
1da177e4 1737
dfe42443 1738 spin_lock_irqsave(&port->lock, flags);
4fd996a1 1739 lsr = serial_port_in(port, UART_LSR);
ad4c2aa6 1740 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
dfe42443 1741 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 1742
bca47613 1743 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1744}
1745
1746static unsigned int serial8250_get_mctrl(struct uart_port *port)
1747{
49d5741b
JI		 1748 struct uart_8250_port *up =
1749 container_of(port, struct uart_8250_port, port);
2af7cd68 1750 unsigned int status;
1da177e4
LT		 1751 unsigned int ret;
1752
3986fb2b 1753 status = serial8250_modem_status(up);
1da177e4
LT		 1754
1755 ret = 0;
1756 if (status & UART_MSR_DCD)
1757 ret |= TIOCM_CAR;
1758 if (status & UART_MSR_RI)
1759 ret |= TIOCM_RNG;
1760 if (status & UART_MSR_DSR)
1761 ret |= TIOCM_DSR;
1762 if (status & UART_MSR_CTS)
1763 ret |= TIOCM_CTS;
1764 return ret;
1765}
1766
1767static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1768{
49d5741b
JI		 1769 struct uart_8250_port *up =
1770 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1771 unsigned char mcr = 0;
1772
1773 if (mctrl & TIOCM_RTS)
1774 mcr |= UART_MCR_RTS;
1775 if (mctrl & TIOCM_DTR)
1776 mcr |= UART_MCR_DTR;
1777 if (mctrl & TIOCM_OUT1)
1778 mcr |= UART_MCR_OUT1;
1779 if (mctrl & TIOCM_OUT2)
1780 mcr |= UART_MCR_OUT2;
1781 if (mctrl & TIOCM_LOOP)
1782 mcr |= UART_MCR_LOOP;
1783
1784 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1785
4fd996a1 1786 serial_port_out(port, UART_MCR, mcr);
1da177e4
LT		 1787}
1788
1789static void serial8250_break_ctl(struct uart_port *port, int break_state)
1790{
49d5741b
JI		 1791 struct uart_8250_port *up =
1792 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1793 unsigned long flags;
1794
dfe42443 1795 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 1796 if (break_state == -1)
1797 up->lcr |= UART_LCR_SBC;
1798 else
1799 up->lcr &= ~UART_LCR_SBC;
4fd996a1 1800 serial_port_out(port, UART_LCR, up->lcr);
dfe42443 1801 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1802}
1803
40b36daa
AW		 1804/*
1805 * Wait for transmitter & holding register to empty
1806 */
b5d674ab 1807static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1808{
1809 unsigned int status, tmout = 10000;
1810
1811 /* Wait up to 10ms for the character(s) to be sent. */
97d303b7 1812 for (;;) {
40b36daa
AW		 1813 status = serial_in(up, UART_LSR);
1814
ad4c2aa6 1815 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa 1816
97d303b7
DD		 1817 if ((status & bits) == bits)
1818 break;
40b36daa
AW		 1819 if (--tmout == 0)
1820 break;
1821 udelay(1);
97d303b7 1822 }
40b36daa
AW		 1823
1824 /* Wait up to 1s for flow control if necessary */
1825 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1826 unsigned int tmout;
1827 for (tmout = 1000000; tmout; tmout--) {
1828 unsigned int msr = serial_in(up, UART_MSR);
1829 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1830 if (msr & UART_MSR_CTS)
1831 break;
40b36daa
AW		 1832 udelay(1);
1833 touch_nmi_watchdog();
1834 }
1835 }
1836}
1837
f2d937f3
JW		 1838#ifdef CONFIG_CONSOLE_POLL
1839/*
1840 * Console polling routines for writing and reading from the uart while
1841 * in an interrupt or debug context.
1842 */
1843
1844static int serial8250_get_poll_char(struct uart_port *port)
1845{
4fd996a1 1846 unsigned char lsr = serial_port_in(port, UART_LSR);
f2d937f3 1847
f5316b4a
JW		 1848 if (!(lsr & UART_LSR_DR))
1849 return NO_POLL_CHAR;
f2d937f3 1850
4fd996a1 1851 return serial_port_in(port, UART_RX);
f2d937f3
JW		 1852}
1853
1854
1855static void serial8250_put_poll_char(struct uart_port *port,
1856 unsigned char c)
1857{
1858 unsigned int ier;
49d5741b
JI		 1859 struct uart_8250_port *up =
1860 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1861
1862 /*
1863 * First save the IER then disable the interrupts
1864 */
4fd996a1 1865 ier = serial_port_in(port, UART_IER);
f2d937f3 1866 if (up->capabilities & UART_CAP_UUE)
4fd996a1 1867 serial_port_out(port, UART_IER, UART_IER_UUE);
f2d937f3 1868 else
4fd996a1 1869 serial_port_out(port, UART_IER, 0);
f2d937f3
JW		 1870
1871 wait_for_xmitr(up, BOTH_EMPTY);
1872 /*
1873 * Send the character out.
1874 * If a LF, also do CR...
1875 */
4fd996a1 1876 serial_port_out(port, UART_TX, c);
f2d937f3
JW		 1877 if (c == 10) {
1878 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 1879 serial_port_out(port, UART_TX, 13);
f2d937f3
JW		 1880 }
1881
1882 /*
1883 * Finally, wait for transmitter to become empty
1884 * and restore the IER
1885 */
1886 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 1887 serial_port_out(port, UART_IER, ier);
f2d937f3
JW		 1888}
1889
1890#endif /* CONFIG_CONSOLE_POLL */
1891
1da177e4
LT		 1892static int serial8250_startup(struct uart_port *port)
1893{
49d5741b
JI		 1894 struct uart_8250_port *up =
1895 container_of(port, struct uart_8250_port, port);
1da177e4 1896 unsigned long flags;
55d3b282 1897 unsigned char lsr, iir;
1da177e4
LT		 1898 int retval;
1899
dfe42443 1900 port->fifosize = uart_config[up->port.type].fifo_size;
e4f05af1 1901 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1da177e4
LT		 1902 up->capabilities = uart_config[up->port.type].flags;
1903 up->mcr = 0;
1904
dfe42443 1905 if (port->iotype != up->cur_iotype)
b8e7e40a
AC		 1906 set_io_from_upio(port);
1907
dfe42443 1908 if (port->type == PORT_16C950) {
1da177e4
LT		 1909 /* Wake up and initialize UART */
1910 up->acr = 0;
4fd996a1
PG		 1911 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1912 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1913 serial_port_out(port, UART_IER, 0);
1914 serial_port_out(port, UART_LCR, 0);
1da177e4 1915 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
4fd996a1
PG		 1916 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1917 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1918 serial_port_out(port, UART_LCR, 0);
1da177e4
LT		 1919 }
1920
1921#ifdef CONFIG_SERIAL_8250_RSA
1922 /*
1923 * If this is an RSA port, see if we can kick it up to the
1924 * higher speed clock.
1925 */
1926 enable_rsa(up);
1927#endif
1928
1929 /*
1930 * Clear the FIFO buffers and disable them.
7f927fcc 1931 * (they will be reenabled in set_termios())
1da177e4
LT		 1932 */
1933 serial8250_clear_fifos(up);
1934
1935 /*
1936 * Clear the interrupt registers.
1937 */
4fd996a1
PG		 1938 serial_port_in(port, UART_LSR);
1939 serial_port_in(port, UART_RX);
1940 serial_port_in(port, UART_IIR);
1941 serial_port_in(port, UART_MSR);
1da177e4
LT		 1942
1943 /*
1944 * At this point, there's no way the LSR could still be 0xff;
1945 * if it is, then bail out, because there's likely no UART
1946 * here.
1947 */
dfe42443 1948 if (!(port->flags & UPF_BUGGY_UART) &&
4fd996a1 1949 (serial_port_in(port, UART_LSR) == 0xff)) {
7808a4c4 1950 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
dfe42443 1951 serial_index(port));
1da177e4
LT		 1952 return -ENODEV;
1953 }
1954
1955 /*
1956 * For a XR16C850, we need to set the trigger levels
1957 */
dfe42443 1958 if (port->type == PORT_16850) {
1da177e4
LT		 1959 unsigned char fctr;
1960
0acf519f 1961 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4 1962
0acf519f 1963 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
4fd996a1
PG		 1964 serial_port_out(port, UART_FCTR,
1965 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1966 serial_port_out(port, UART_TRG, UART_TRG_96);
1967 serial_port_out(port, UART_FCTR,
1968 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1969 serial_port_out(port, UART_TRG, UART_TRG_96);
1da177e4 1970
4fd996a1 1971 serial_port_out(port, UART_LCR, 0);
1da177e4
LT		 1972 }
1973
dfe42443 1974 if (port->irq) {
01c194d9 1975 unsigned char iir1;
40b36daa
AW		 1976 /*
1977 * Test for UARTs that do not reassert THRE when the
1978 * transmitter is idle and the interrupt has already
1979 * been cleared. Real 16550s should always reassert
1980 * this interrupt whenever the transmitter is idle and
1981 * the interrupt is enabled. Delays are necessary to
1982 * allow register changes to become visible.
1983 */
dfe42443 1984 spin_lock_irqsave(&port->lock, flags);
1c2f0493 1985 if (up->port.irqflags & IRQF_SHARED)
dfe42443 1986 disable_irq_nosync(port->irq);
40b36daa
AW		 1987
1988 wait_for_xmitr(up, UART_LSR_THRE);
55e4016d 1989 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
40b36daa 1990 udelay(1); /* allow THRE to set */
4fd996a1
PG		 1991 iir1 = serial_port_in(port, UART_IIR);
1992 serial_port_out(port, UART_IER, 0);
55e4016d 1993 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
40b36daa 1994 udelay(1); /* allow a working UART time to re-assert THRE */
4fd996a1
PG		 1995 iir = serial_port_in(port, UART_IIR);
1996 serial_port_out(port, UART_IER, 0);
40b36daa 1997
dfe42443
PG		 1998 if (port->irqflags & IRQF_SHARED)
1999 enable_irq(port->irq);
2000 spin_unlock_irqrestore(&port->lock, flags);
40b36daa
AW		 2001
2002 /*
bc02d15a
DW		 2003 * If the interrupt is not reasserted, or we otherwise
2004 * don't trust the iir, setup a timer to kick the UART
2005 * on a regular basis.
40b36daa 2006 */
bc02d15a
DW		 2007 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2008 up->port.flags & UPF_BUG_THRE) {
363f66fe 2009 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2010 pr_debug("ttyS%d - using backup timer\n",
2011 serial_index(port));
40b36daa
AW		 2012 }
2013 }
2014
363f66fe
WN		 2015 /*
2016 * The above check will only give an accurate result the first time
2017 * the port is opened so this value needs to be preserved.
2018 */
2019 if (up->bugs & UART_BUG_THRE) {
2020 up->timer.function = serial8250_backup_timeout;
2021 up->timer.data = (unsigned long)up;
2022 mod_timer(&up->timer, jiffies +
54381067 2023 uart_poll_timeout(port) + HZ / 5);
363f66fe
WN		 2024 }
2025
1da177e4
LT		 2026 /*
2027 * If the "interrupt" for this port doesn't correspond with any
2028 * hardware interrupt, we use a timer-based system. The original
2029 * driver used to do this with IRQ0.
2030 */
dfe42443 2031 if (!port->irq) {
1da177e4 2032 up->timer.data = (unsigned long)up;
54381067 2033 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
1da177e4
LT		 2034 } else {
2035 retval = serial_link_irq_chain(up);
2036 if (retval)
2037 return retval;
2038 }
2039
2040 /*
2041 * Now, initialize the UART
2042 */
4fd996a1 2043 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
1da177e4 2044
dfe42443 2045 spin_lock_irqsave(&port->lock, flags);
1da177e4 2046 if (up->port.flags & UPF_FOURPORT) {
d4e33fac 2047 if (!up->port.irq)
1da177e4
LT		 2048 up->port.mctrl |= TIOCM_OUT1;
2049 } else
2050 /*
2051 * Most PC uarts need OUT2 raised to enable interrupts.
2052 */
dfe42443 2053 if (port->irq)
1da177e4
LT		 2054 up->port.mctrl |= TIOCM_OUT2;
2055
dfe42443 2056 serial8250_set_mctrl(port, port->mctrl);
55d3b282 2057
b6adea33
MCC		 2058 /* Serial over Lan (SoL) hack:
2059 Intel 8257x Gigabit ethernet chips have a
2060 16550 emulation, to be used for Serial Over Lan.
2061 Those chips take a longer time than a normal
2062 serial device to signalize that a transmission
2063 data was queued. Due to that, the above test generally
2064 fails. One solution would be to delay the reading of
2065 iir. However, this is not reliable, since the timeout
2066 is variable. So, let's just don't test if we receive
2067 TX irq. This way, we'll never enable UART_BUG_TXEN.
2068 */
d41a4b51 2069 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2070 goto dont_test_tx_en;
2071
55d3b282
RK		 2072 /*
2073 * Do a quick test to see if we receive an
2074 * interrupt when we enable the TX irq.
2075 */
4fd996a1
PG		 2076 serial_port_out(port, UART_IER, UART_IER_THRI);
2077 lsr = serial_port_in(port, UART_LSR);
2078 iir = serial_port_in(port, UART_IIR);
2079 serial_port_out(port, UART_IER, 0);
55d3b282
RK		 2080
2081 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2082 if (!(up->bugs & UART_BUG_TXEN)) {
2083 up->bugs |= UART_BUG_TXEN;
55d3b282 2084 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2085 serial_index(port));
55d3b282
RK		 2086 }
2087 } else {
67f7654e 2088 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2089 }
2090
b6adea33 2091dont_test_tx_en:
dfe42443 2092 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 2093
ad4c2aa6
CM		 2094 /*
2095 * Clear the interrupt registers again for luck, and clear the
2096 * saved flags to avoid getting false values from polling
2097 * routines or the previous session.
2098 */
4fd996a1
PG		 2099 serial_port_in(port, UART_LSR);
2100 serial_port_in(port, UART_RX);
2101 serial_port_in(port, UART_IIR);
2102 serial_port_in(port, UART_MSR);
ad4c2aa6
CM		 2103 up->lsr_saved_flags = 0;
2104 up->msr_saved_flags = 0;
2105
1da177e4
LT		 2106 /*
2107 * Finally, enable interrupts. Note: Modem status interrupts
2108 * are set via set_termios(), which will be occurring imminently
2109 * anyway, so we don't enable them here.
2110 */
2111 up->ier = UART_IER_RLSI | UART_IER_RDI;
4fd996a1 2112 serial_port_out(port, UART_IER, up->ier);
1da177e4 2113
dfe42443 2114 if (port->flags & UPF_FOURPORT) {
1da177e4
LT		 2115 unsigned int icp;
2116 /*
2117 * Enable interrupts on the AST Fourport board
2118 */
dfe42443 2119 icp = (port->iobase & 0xfe0) | 0x01f;
1da177e4 2120 outb_p(0x80, icp);
0d263a26 2121 inb_p(icp);
1da177e4
LT		 2122 }
2123
1da177e4
LT		 2124 return 0;
2125}
2126
2127static void serial8250_shutdown(struct uart_port *port)
2128{
49d5741b
JI		 2129 struct uart_8250_port *up =
2130 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2131 unsigned long flags;
2132
2133 /*
2134 * Disable interrupts from this port
2135 */
2136 up->ier = 0;
4fd996a1 2137 serial_port_out(port, UART_IER, 0);
1da177e4 2138
dfe42443
PG		 2139 spin_lock_irqsave(&port->lock, flags);
2140 if (port->flags & UPF_FOURPORT) {
1da177e4 2141 /* reset interrupts on the AST Fourport board */
dfe42443
PG		 2142 inb((port->iobase & 0xfe0) | 0x1f);
2143 port->mctrl |= TIOCM_OUT1;
1da177e4 2144 } else
dfe42443 2145 port->mctrl &= ~TIOCM_OUT2;
1da177e4 2146
dfe42443
PG		 2147 serial8250_set_mctrl(port, port->mctrl);
2148 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 2149
2150 /*
2151 * Disable break condition and FIFOs
2152 */
4fd996a1
PG		 2153 serial_port_out(port, UART_LCR,
2154 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
1da177e4
LT		 2155 serial8250_clear_fifos(up);
2156
2157#ifdef CONFIG_SERIAL_8250_RSA
2158 /*
2159 * Reset the RSA board back to 115kbps compat mode.
2160 */
2161 disable_rsa(up);
2162#endif
2163
2164 /*
2165 * Read data port to reset things, and then unlink from
2166 * the IRQ chain.
2167 */
4fd996a1 2168 serial_port_in(port, UART_RX);
1da177e4 2169
40b36daa
AW		 2170 del_timer_sync(&up->timer);
2171 up->timer.function = serial8250_timeout;
dfe42443 2172 if (port->irq)
1da177e4
LT		 2173 serial_unlink_irq_chain(up);
2174}
2175
2176static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2177{
2178 unsigned int quot;
2179
2180 /*
2181 * Handle magic divisors for baud rates above baud_base on
2182 * SMSC SuperIO chips.
2183 */
2184 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2185 baud == (port->uartclk/4))
2186 quot = 0x8001;
2187 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2188 baud == (port->uartclk/8))
2189 quot = 0x8002;
2190 else
2191 quot = uart_get_divisor(port, baud);
2192
2193 return quot;
2194}
2195
235dae5d
PL		 2196void
2197serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2198 struct ktermios *old)
1da177e4 2199{
49d5741b
JI		 2200 struct uart_8250_port *up =
2201 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2202 unsigned char cval, fcr = 0;
2203 unsigned long flags;
2204 unsigned int baud, quot;
2205
2206 switch (termios->c_cflag & CSIZE) {
2207 case CS5:
0a8b80c5 2208 cval = UART_LCR_WLEN5;
1da177e4
LT		 2209 break;
2210 case CS6:
0a8b80c5 2211 cval = UART_LCR_WLEN6;
1da177e4
LT		 2212 break;
2213 case CS7:
0a8b80c5 2214 cval = UART_LCR_WLEN7;
1da177e4
LT		 2215 break;
2216 default:
2217 case CS8:
0a8b80c5 2218 cval = UART_LCR_WLEN8;
1da177e4
LT		 2219 break;
2220 }
2221
2222 if (termios->c_cflag & CSTOPB)
0a8b80c5 2223 cval |= UART_LCR_STOP;
1da177e4
LT		 2224 if (termios->c_cflag & PARENB)
2225 cval |= UART_LCR_PARITY;
2226 if (!(termios->c_cflag & PARODD))
2227 cval |= UART_LCR_EPAR;
2228#ifdef CMSPAR
2229 if (termios->c_cflag & CMSPAR)
2230 cval |= UART_LCR_SPAR;
2231#endif
2232
2233 /*
2234 * Ask the core to calculate the divisor for us.
2235 */
24d481ec
AV		 2236 baud = uart_get_baud_rate(port, termios, old,
2237 port->uartclk / 16 / 0xffff,
2238 port->uartclk / 16);
1da177e4
LT		 2239 quot = serial8250_get_divisor(port, baud);
2240
2241 /*
4ba5e35d 2242 * Oxford Semi 952 rev B workaround
1da177e4 2243 */
4ba5e35d 2244 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2245 quot++;
1da177e4 2246
dfe42443 2247 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
f9a9111b
CM		 2248 fcr = uart_config[port->type].fcr;
2249 if (baud < 2400) {
2250 fcr &= ~UART_FCR_TRIGGER_MASK;
2251 fcr |= UART_FCR_TRIGGER_1;
2252 }
1da177e4
LT		 2253 }
2254
2255 /*
2256 * MCR-based auto flow control. When AFE is enabled, RTS will be
2257 * deasserted when the receive FIFO contains more characters than
2258 * the trigger, or the MCR RTS bit is cleared. In the case where
2259 * the remote UART is not using CTS auto flow control, we must
2260 * have sufficient FIFO entries for the latency of the remote
2261 * UART to respond. IOW, at least 32 bytes of FIFO.
2262 */
dfe42443 2263 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
1da177e4
LT		 2264 up->mcr &= ~UART_MCR_AFE;
2265 if (termios->c_cflag & CRTSCTS)
2266 up->mcr |= UART_MCR_AFE;
2267 }
2268
2269 /*
2270 * Ok, we're now changing the port state. Do it with
2271 * interrupts disabled.
2272 */
dfe42443 2273 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 2274
2275 /*
2276 * Update the per-port timeout.
2277 */
2278 uart_update_timeout(port, termios->c_cflag, baud);
2279
dfe42443 2280 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1da177e4 2281 if (termios->c_iflag & INPCK)
dfe42443 2282 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1da177e4 2283 if (termios->c_iflag & (BRKINT | PARMRK))
dfe42443 2284 port->read_status_mask |= UART_LSR_BI;
1da177e4
LT		 2285
2286 /*
2287 * Characteres to ignore
2288 */
dfe42443 2289 port->ignore_status_mask = 0;
1da177e4 2290 if (termios->c_iflag & IGNPAR)
dfe42443 2291 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1da177e4 2292 if (termios->c_iflag & IGNBRK) {
dfe42443 2293 port->ignore_status_mask |= UART_LSR_BI;
1da177e4
LT		 2294 /*
2295 * If we're ignoring parity and break indicators,
2296 * ignore overruns too (for real raw support).
2297 */
2298 if (termios->c_iflag & IGNPAR)
dfe42443 2299 port->ignore_status_mask |= UART_LSR_OE;
1da177e4
LT		 2300 }
2301
2302 /*
2303 * ignore all characters if CREAD is not set
2304 */
2305 if ((termios->c_cflag & CREAD) == 0)
dfe42443 2306 port->ignore_status_mask |= UART_LSR_DR;
1da177e4
LT		 2307
2308 /*
2309 * CTS flow control flag and modem status interrupts
2310 */
f8b372a1 2311 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2312 if (!(up->bugs & UART_BUG_NOMSR) &&
2313 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2314 up->ier |= UART_IER_MSI;
2315 if (up->capabilities & UART_CAP_UUE)
4539c24f
SW		 2316 up->ier |= UART_IER_UUE;
2317 if (up->capabilities & UART_CAP_RTOIE)
2318 up->ier |= UART_IER_RTOIE;
1da177e4 2319
4fd996a1 2320 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 2321
2322 if (up->capabilities & UART_CAP_EFR) {
2323 unsigned char efr = 0;
2324 /*
2325 * TI16C752/Startech hardware flow control. FIXME:
2326 * - TI16C752 requires control thresholds to be set.
2327 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2328 */
2329 if (termios->c_cflag & CRTSCTS)
2330 efr |= UART_EFR_CTS;
2331
4fd996a1 2332 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
dfe42443 2333 if (port->flags & UPF_EXAR_EFR)
4fd996a1 2334 serial_port_out(port, UART_XR_EFR, efr);
06315348 2335 else
4fd996a1 2336 serial_port_out(port, UART_EFR, efr);
1da177e4
LT		 2337 }
2338
f2eda27d 2339#ifdef CONFIG_ARCH_OMAP
255341c6 2340 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
5668545a 2341 if (cpu_is_omap1510() && is_omap_port(up)) {
255341c6
JM		 2342 if (baud == 115200) {
2343 quot = 1;
4fd996a1 2344 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
255341c6 2345 } else
4fd996a1 2346 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
255341c6
JM		 2347 }
2348#endif
2349
4fd996a1
PG		 2350 /*
2351 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2352 * otherwise just set DLAB
2353 */
2354 if (up->capabilities & UART_NATSEMI)
2355 serial_port_out(port, UART_LCR, 0xe0);
2356 else
2357 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
1da177e4 2358
b32b19b8 2359 serial_dl_write(up, quot);
1da177e4
LT		 2360
2361 /*
2362 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2363 * is written without DLAB set, this mode will be disabled.
2364 */
dfe42443 2365 if (port->type == PORT_16750)
4fd996a1 2366 serial_port_out(port, UART_FCR, fcr);
1da177e4 2367
4fd996a1 2368 serial_port_out(port, UART_LCR, cval); /* reset DLAB */
1da177e4 2369 up->lcr = cval; /* Save LCR */
dfe42443 2370 if (port->type != PORT_16750) {
4fd996a1
PG		 2371 /* emulated UARTs (Lucent Venus 167x) need two steps */
2372 if (fcr & UART_FCR_ENABLE_FIFO)
2373 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2374 serial_port_out(port, UART_FCR, fcr); /* set fcr */
1da177e4 2375 }
dfe42443
PG		 2376 serial8250_set_mctrl(port, port->mctrl);
2377 spin_unlock_irqrestore(&port->lock, flags);
e991a2bd
AC		 2378 /* Don't rewrite B0 */
2379 if (tty_termios_baud_rate(termios))
2380 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4 2381}
235dae5d
PL		 2382EXPORT_SYMBOL(serial8250_do_set_termios);
2383
2384static void
2385serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2386 struct ktermios *old)
2387{
2388 if (port->set_termios)
2389 port->set_termios(port, termios, old);
2390 else
2391 serial8250_do_set_termios(port, termios, old);
2392}
1da177e4 2393
dc77f161 2394static void
a0821df6 2395serial8250_set_ldisc(struct uart_port *port, int new)
dc77f161 2396{
a0821df6 2397 if (new == N_PPS) {
dc77f161
RG		 2398 port->flags |= UPF_HARDPPS_CD;
2399 serial8250_enable_ms(port);
2400 } else
2401 port->flags &= ~UPF_HARDPPS_CD;
2402}
2403
c161afe9
ML		 2404
2405void serial8250_do_pm(struct uart_port *port, unsigned int state,
2406 unsigned int oldstate)
1da177e4 2407{
49d5741b
JI		 2408 struct uart_8250_port *p =
2409 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2410
2411 serial8250_set_sleep(p, state != 0);
c161afe9
ML		 2412}
2413EXPORT_SYMBOL(serial8250_do_pm);
1da177e4 2414
c161afe9
ML		 2415static void
2416serial8250_pm(struct uart_port *port, unsigned int state,
2417 unsigned int oldstate)
2418{
2419 if (port->pm)
2420 port->pm(port, state, oldstate);
2421 else
2422 serial8250_do_pm(port, state, oldstate);
1da177e4
LT		 2423}
2424
f2eda27d
RK		 2425static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2426{
2427 if (pt->port.iotype == UPIO_AU)
b2b13cdf 2428 return 0x1000;
f2eda27d
RK		 2429#ifdef CONFIG_ARCH_OMAP
2430 if (is_omap_port(pt))
2431 return 0x16 << pt->port.regshift;
2432#endif
2433 return 8 << pt->port.regshift;
2434}
2435
1da177e4
LT		 2436/*
2437 * Resource handling.
2438 */
2439static int serial8250_request_std_resource(struct uart_8250_port *up)
2440{
f2eda27d 2441 unsigned int size = serial8250_port_size(up);
dfe42443 2442 struct uart_port *port = &up->port;
1da177e4
LT		 2443 int ret = 0;
2444
dfe42443 2445 switch (port->iotype) {
85835f44 2446 case UPIO_AU:
0b30d668
SS		 2447 case UPIO_TSI:
2448 case UPIO_MEM32:
1da177e4 2449 case UPIO_MEM:
dfe42443 2450 if (!port->mapbase)
1da177e4
LT		 2451 break;
2452
dfe42443 2453 if (!request_mem_region(port->mapbase, size, "serial")) {
1da177e4
LT		 2454 ret = -EBUSY;
2455 break;
2456 }
2457
dfe42443
PG		 2458 if (port->flags & UPF_IOREMAP) {
2459 port->membase = ioremap_nocache(port->mapbase, size);
2460 if (!port->membase) {
2461 release_mem_region(port->mapbase, size);
1da177e4
LT		 2462 ret = -ENOMEM;
2463 }
2464 }
2465 break;
2466
2467 case UPIO_HUB6:
2468 case UPIO_PORT:
dfe42443 2469 if (!request_region(port->iobase, size, "serial"))
1da177e4
LT		 2470 ret = -EBUSY;
2471 break;
2472 }
2473 return ret;
2474}
2475
2476static void serial8250_release_std_resource(struct uart_8250_port *up)
2477{
f2eda27d 2478 unsigned int size = serial8250_port_size(up);
dfe42443 2479 struct uart_port *port = &up->port;
1da177e4 2480
dfe42443 2481 switch (port->iotype) {
85835f44 2482 case UPIO_AU:
0b30d668
SS		 2483 case UPIO_TSI:
2484 case UPIO_MEM32:
1da177e4 2485 case UPIO_MEM:
dfe42443 2486 if (!port->mapbase)
1da177e4
LT		 2487 break;
2488
dfe42443
PG		 2489 if (port->flags & UPF_IOREMAP) {
2490 iounmap(port->membase);
2491 port->membase = NULL;
1da177e4
LT		 2492 }
2493
dfe42443 2494 release_mem_region(port->mapbase, size);
1da177e4
LT		 2495 break;
2496
2497 case UPIO_HUB6:
2498 case UPIO_PORT:
dfe42443 2499 release_region(port->iobase, size);
1da177e4
LT		 2500 break;
2501 }
2502}
2503
2504static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2505{
2506 unsigned long start = UART_RSA_BASE << up->port.regshift;
2507 unsigned int size = 8 << up->port.regshift;
dfe42443 2508 struct uart_port *port = &up->port;
0b30d668 2509 int ret = -EINVAL;
1da177e4 2510
dfe42443 2511 switch (port->iotype) {
1da177e4
LT		 2512 case UPIO_HUB6:
2513 case UPIO_PORT:
dfe42443 2514 start += port->iobase;
0b30d668
SS		 2515 if (request_region(start, size, "serial-rsa"))
2516 ret = 0;
2517 else
1da177e4
LT		 2518 ret = -EBUSY;
2519 break;
2520 }
2521
2522 return ret;
2523}
2524
2525static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2526{
2527 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2528 unsigned int size = 8 << up->port.regshift;
dfe42443 2529 struct uart_port *port = &up->port;
1da177e4 2530
dfe42443 2531 switch (port->iotype) {
1da177e4
LT		 2532 case UPIO_HUB6:
2533 case UPIO_PORT:
dfe42443 2534 release_region(port->iobase + offset, size);
1da177e4
LT		 2535 break;
2536 }
2537}
2538
2539static void serial8250_release_port(struct uart_port *port)
2540{
49d5741b
JI		 2541 struct uart_8250_port *up =
2542 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2543
2544 serial8250_release_std_resource(up);
dfe42443 2545 if (port->type == PORT_RSA)
1da177e4
LT		 2546 serial8250_release_rsa_resource(up);
2547}
2548
2549static int serial8250_request_port(struct uart_port *port)
2550{
49d5741b
JI		 2551 struct uart_8250_port *up =
2552 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2553 int ret = 0;
2554
2555 ret = serial8250_request_std_resource(up);
dfe42443 2556 if (ret == 0 && port->type == PORT_RSA) {
1da177e4
LT		 2557 ret = serial8250_request_rsa_resource(up);
2558 if (ret < 0)
2559 serial8250_release_std_resource(up);
2560 }
2561
2562 return ret;
2563}
2564
2565static void serial8250_config_port(struct uart_port *port, int flags)
2566{
49d5741b
JI		 2567 struct uart_8250_port *up =
2568 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2569 int probeflags = PROBE_ANY;
2570 int ret;
2571
1da177e4
LT		 2572 /*
2573 * Find the region that we can probe for. This in turn
2574 * tells us whether we can probe for the type of port.
2575 */
2576 ret = serial8250_request_std_resource(up);
2577 if (ret < 0)
2578 return;
2579
2580 ret = serial8250_request_rsa_resource(up);
2581 if (ret < 0)
2582 probeflags &= ~PROBE_RSA;
2583
dfe42443 2584 if (port->iotype != up->cur_iotype)
b8e7e40a
AC		 2585 set_io_from_upio(port);
2586
1da177e4
LT		 2587 if (flags & UART_CONFIG_TYPE)
2588 autoconfig(up, probeflags);
b2b13cdf 2589
b2b13cdf 2590 /* if access method is AU, it is a 16550 with a quirk */
dfe42443 2591 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
b2b13cdf 2592 up->bugs |= UART_BUG_NOMSR;
b2b13cdf 2593
dfe42443 2594 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
1da177e4
LT		 2595 autoconfig_irq(up);
2596
dfe42443 2597 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
1da177e4 2598 serial8250_release_rsa_resource(up);
dfe42443 2599 if (port->type == PORT_UNKNOWN)
1da177e4
LT		 2600 serial8250_release_std_resource(up);
2601}
2602
2603static int
2604serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2605{
a62c4133 2606 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2607 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2608 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2609 ser->type == PORT_STARTECH)
2610 return -EINVAL;
2611 return 0;
2612}
2613
2614static const char *
2615serial8250_type(struct uart_port *port)
2616{
2617 int type = port->type;
2618
2619 if (type >= ARRAY_SIZE(uart_config))
2620 type = 0;
2621 return uart_config[type].name;
2622}
2623
2624static struct uart_ops serial8250_pops = {
2625 .tx_empty = serial8250_tx_empty,
2626 .set_mctrl = serial8250_set_mctrl,
2627 .get_mctrl = serial8250_get_mctrl,
2628 .stop_tx = serial8250_stop_tx,
2629 .start_tx = serial8250_start_tx,
2630 .stop_rx = serial8250_stop_rx,
2631 .enable_ms = serial8250_enable_ms,
2632 .break_ctl = serial8250_break_ctl,
2633 .startup = serial8250_startup,
2634 .shutdown = serial8250_shutdown,
2635 .set_termios = serial8250_set_termios,
dc77f161 2636 .set_ldisc = serial8250_set_ldisc,
1da177e4
LT		 2637 .pm = serial8250_pm,
2638 .type = serial8250_type,
2639 .release_port = serial8250_release_port,
2640 .request_port = serial8250_request_port,
2641 .config_port = serial8250_config_port,
2642 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2643#ifdef CONFIG_CONSOLE_POLL
2644 .poll_get_char = serial8250_get_poll_char,
2645 .poll_put_char = serial8250_put_poll_char,
2646#endif
1da177e4
LT		 2647};
2648
2649static struct uart_8250_port serial8250_ports[UART_NR];
2650
af7f3743
AC		 2651static void (*serial8250_isa_config)(int port, struct uart_port *up,
2652 unsigned short *capabilities);
2653
2654void serial8250_set_isa_configurator(
2655 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2656{
2657 serial8250_isa_config = v;
2658}
2659EXPORT_SYMBOL(serial8250_set_isa_configurator);
2660
1da177e4
LT		 2661static void __init serial8250_isa_init_ports(void)
2662{
2663 struct uart_8250_port *up;
2664 static int first = 1;
4c0ebb80 2665 int i, irqflag = 0;
1da177e4
LT		 2666
2667 if (!first)
2668 return;
2669 first = 0;
2670
a61c2d78 2671 for (i = 0; i < nr_uarts; i++) {
1da177e4 2672 struct uart_8250_port *up = &serial8250_ports[i];
dfe42443 2673 struct uart_port *port = &up->port;
1da177e4 2674
dfe42443
PG		 2675 port->line = i;
2676 spin_lock_init(&port->lock);
1da177e4
LT		 2677
2678 init_timer(&up->timer);
2679 up->timer.function = serial8250_timeout;
2680
2681 /*
2682 * ALPHA_KLUDGE_MCR needs to be killed.
2683 */
2684 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2685 up->mcr_force = ALPHA_KLUDGE_MCR;
2686
dfe42443 2687 port->ops = &serial8250_pops;
1da177e4
LT		 2688 }
2689
4c0ebb80
AGR		 2690 if (share_irqs)
2691 irqflag = IRQF_SHARED;
2692
44454bcd 2693 for (i = 0, up = serial8250_ports;
a61c2d78 2694 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4 2695 i++, up++) {
dfe42443
PG		 2696 struct uart_port *port = &up->port;
2697
2698 port->iobase = old_serial_port[i].port;
2699 port->irq = irq_canonicalize(old_serial_port[i].irq);
2700 port->irqflags = old_serial_port[i].irqflags;
2701 port->uartclk = old_serial_port[i].baud_base * 16;
2702 port->flags = old_serial_port[i].flags;
2703 port->hub6 = old_serial_port[i].hub6;
2704 port->membase = old_serial_port[i].iomem_base;
2705 port->iotype = old_serial_port[i].io_type;
2706 port->regshift = old_serial_port[i].iomem_reg_shift;
2707 set_io_from_upio(port);
2708 port->irqflags |= irqflag;
af7f3743
AC		 2709 if (serial8250_isa_config != NULL)
2710 serial8250_isa_config(i, &up->port, &up->capabilities);
2711
1da177e4
LT		 2712 }
2713}
2714
b5d228cc
SL		 2715static void
2716serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2717{
2718 up->port.type = type;
2719 up->port.fifosize = uart_config[type].fifo_size;
2720 up->capabilities = uart_config[type].flags;
2721 up->tx_loadsz = uart_config[type].tx_loadsz;
2722}
2723
1da177e4
LT		 2724static void __init
2725serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2726{
2727 int i;
2728
b8e7e40a
AC		 2729 for (i = 0; i < nr_uarts; i++) {
2730 struct uart_8250_port *up = &serial8250_ports[i];
2731 up->cur_iotype = 0xFF;
2732 }
2733
1da177e4
LT		 2734 serial8250_isa_init_ports();
2735
a61c2d78 2736 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2737 struct uart_8250_port *up = &serial8250_ports[i];
2738
2739 up->port.dev = dev;
b5d228cc
SL		 2740
2741 if (up->port.flags & UPF_FIXED_TYPE)
2742 serial8250_init_fixed_type_port(up, up->port.type);
2743
1da177e4
LT		 2744 uart_add_one_port(drv, &up->port);
2745 }
2746}
2747
2748#ifdef CONFIG_SERIAL_8250_CONSOLE
2749
d358788f
RK		 2750static void serial8250_console_putchar(struct uart_port *port, int ch)
2751{
49d5741b
JI		 2752 struct uart_8250_port *up =
2753 container_of(port, struct uart_8250_port, port);
d358788f
RK		 2754
2755 wait_for_xmitr(up, UART_LSR_THRE);
4fd996a1 2756 serial_port_out(port, UART_TX, ch);
d358788f
RK		 2757}
2758
1da177e4
LT		 2759/*
2760 * Print a string to the serial port trying not to disturb
2761 * any possible real use of the port...
2762 *
2763 * The console_lock must be held when we get here.
2764 */
2765static void
2766serial8250_console_write(struct console *co, const char *s, unsigned int count)
2767{
2768 struct uart_8250_port *up = &serial8250_ports[co->index];
dfe42443 2769 struct uart_port *port = &up->port;
d8a5a8d7 2770 unsigned long flags;
1da177e4 2771 unsigned int ier;
d8a5a8d7 2772 int locked = 1;
1da177e4 2773
78512ece
AM		 2774 touch_nmi_watchdog();
2775
68aa2c0d 2776 local_irq_save(flags);
dfe42443 2777 if (port->sysrq) {
86b21199 2778 /* serial8250_handle_irq() already took the lock */
68aa2c0d
AM		 2779 locked = 0;
2780 } else if (oops_in_progress) {
dfe42443 2781 locked = spin_trylock(&port->lock);
d8a5a8d7 2782 } else
dfe42443 2783 spin_lock(&port->lock);
d8a5a8d7 2784
1da177e4 2785 /*
dc7bf130 2786 * First save the IER then disable the interrupts
1da177e4 2787 */
4fd996a1 2788 ier = serial_port_in(port, UART_IER);
1da177e4
LT		 2789
2790 if (up->capabilities & UART_CAP_UUE)
4fd996a1 2791 serial_port_out(port, UART_IER, UART_IER_UUE);
1da177e4 2792 else
4fd996a1 2793 serial_port_out(port, UART_IER, 0);
1da177e4 2794
dfe42443 2795 uart_console_write(port, s, count, serial8250_console_putchar);
1da177e4
LT		 2796
2797 /*
2798 * Finally, wait for transmitter to become empty
2799 * and restore the IER
2800 */
f91a3715 2801 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 2802 serial_port_out(port, UART_IER, ier);
d8a5a8d7 2803
ad4c2aa6
CM		 2804 /*
2805 * The receive handling will happen properly because the
2806 * receive ready bit will still be set; it is not cleared
2807 * on read. However, modem control will not, we must
2808 * call it if we have saved something in the saved flags
2809 * while processing with interrupts off.
2810 */
2811 if (up->msr_saved_flags)
3986fb2b 2812 serial8250_modem_status(up);
ad4c2aa6 2813
d8a5a8d7 2814 if (locked)
dfe42443 2815 spin_unlock(&port->lock);
68aa2c0d 2816 local_irq_restore(flags);
1da177e4
LT		 2817}
2818
118c0ace 2819static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2820{
2821 struct uart_port *port;
2822 int baud = 9600;
2823 int bits = 8;
2824 int parity = 'n';
2825 int flow = 'n';
2826
2827 /*
2828 * Check whether an invalid uart number has been specified, and
2829 * if so, search for the first available port that does have
2830 * console support.
2831 */
a61c2d78 2832 if (co->index >= nr_uarts)
1da177e4
LT		 2833 co->index = 0;
2834 port = &serial8250_ports[co->index].port;
2835 if (!port->iobase && !port->membase)
2836 return -ENODEV;
2837
2838 if (options)
2839 uart_parse_options(options, &baud, &parity, &bits, &flow);
2840
2841 return uart_set_options(port, co, baud, parity, bits, flow);
2842}
2843
b6b1d877 2844static int serial8250_console_early_setup(void)
18a8bd94
YL		 2845{
2846 return serial8250_find_port_for_earlycon();
2847}
2848
1da177e4
LT		 2849static struct console serial8250_console = {
2850 .name = "ttyS",
2851 .write = serial8250_console_write,
2852 .device = uart_console_device,
2853 .setup = serial8250_console_setup,
18a8bd94 2854 .early_setup = serial8250_console_early_setup,
a80c49db 2855 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2856 .index = -1,
2857 .data = &serial8250_reg,
2858};
2859
2860static int __init serial8250_console_init(void)
2861{
05d81d22
EB		 2862 if (nr_uarts > UART_NR)
2863 nr_uarts = UART_NR;
2864
1da177e4
LT		 2865 serial8250_isa_init_ports();
2866 register_console(&serial8250_console);
2867 return 0;
2868}
2869console_initcall(serial8250_console_init);
2870
18a8bd94 2871int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2872{
2873 int line;
2874 struct uart_port *port;
2875
a61c2d78 2876 for (line = 0; line < nr_uarts; line++) {
1da177e4 2877 port = &serial8250_ports[line].port;
50aec3b5 2878 if (uart_match_port(p, port))
1da177e4
LT		 2879 return line;
2880 }
2881 return -ENODEV;
2882}
2883
1da177e4
LT		 2884#define SERIAL8250_CONSOLE &serial8250_console
2885#else
2886#define SERIAL8250_CONSOLE NULL
2887#endif
2888
2889static struct uart_driver serial8250_reg = {
2890 .owner = THIS_MODULE,
2891 .driver_name = "serial",
1da177e4
LT		 2892 .dev_name = "ttyS",
2893 .major = TTY_MAJOR,
2894 .minor = 64,
1da177e4
LT		 2895 .cons = SERIAL8250_CONSOLE,
2896};
2897
d856c666
RK		 2898/*
2899 * early_serial_setup - early registration for 8250 ports
2900 *
2901 * Setup an 8250 port structure prior to console initialisation. Use
2902 * after console initialisation will cause undefined behaviour.
2903 */
1da177e4
LT		 2904int __init early_serial_setup(struct uart_port *port)
2905{
b430428a
DD		 2906 struct uart_port *p;
2907
1da177e4
LT		 2908 if (port->line >= ARRAY_SIZE(serial8250_ports))
2909 return -ENODEV;
2910
2911 serial8250_isa_init_ports();
b430428a
DD		 2912 p = &serial8250_ports[port->line].port;
2913 p->iobase = port->iobase;
2914 p->membase = port->membase;
2915 p->irq = port->irq;
1c2f0493 2916 p->irqflags = port->irqflags;
b430428a
DD		 2917 p->uartclk = port->uartclk;
2918 p->fifosize = port->fifosize;
2919 p->regshift = port->regshift;
2920 p->iotype = port->iotype;
2921 p->flags = port->flags;
2922 p->mapbase = port->mapbase;
2923 p->private_data = port->private_data;
125c97d8
HD		 2924 p->type = port->type;
2925 p->line = port->line;
7d6a07d1
DD		 2926
2927 set_io_from_upio(p);
2928 if (port->serial_in)
2929 p->serial_in = port->serial_in;
2930 if (port->serial_out)
2931 p->serial_out = port->serial_out;
583d28e9
JI		 2932 if (port->handle_irq)
2933 p->handle_irq = port->handle_irq;
2934 else
2935 p->handle_irq = serial8250_default_handle_irq;
7d6a07d1 2936
1da177e4
LT		 2937 return 0;
2938}
2939
2940/**
2941 * serial8250_suspend_port - suspend one serial port
2942 * @line: serial line number
1da177e4
LT		 2943 *
2944 * Suspend one serial port.
2945 */
2946void serial8250_suspend_port(int line)
2947{
2948 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2949}
2950
2951/**
2952 * serial8250_resume_port - resume one serial port
2953 * @line: serial line number
1da177e4
LT		 2954 *
2955 * Resume one serial port.
2956 */
2957void serial8250_resume_port(int line)
2958{
b5b82df6 2959 struct uart_8250_port *up = &serial8250_ports[line];
dfe42443 2960 struct uart_port *port = &up->port;
b5b82df6
DW		 2961
2962 if (up->capabilities & UART_NATSEMI) {
b5b82df6 2963 /* Ensure it's still in high speed mode */
4fd996a1 2964 serial_port_out(port, UART_LCR, 0xE0);
b5b82df6 2965
0d0389e5 2966 ns16550a_goto_highspeed(up);
b5b82df6 2967
4fd996a1 2968 serial_port_out(port, UART_LCR, 0);
dfe42443 2969 port->uartclk = 921600*16;
b5b82df6 2970 }
dfe42443 2971 uart_resume_port(&serial8250_reg, port);
1da177e4
LT		 2972}
2973
2974/*
2975 * Register a set of serial devices attached to a platform device. The
2976 * list is terminated with a zero flags entry, which means we expect
2977 * all entries to have at least UPF_BOOT_AUTOCONF set.
2978 */
3ae5eaec 2979static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2980{
3ae5eaec 2981 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2982 struct uart_port port;
4c0ebb80 2983 int ret, i, irqflag = 0;
1da177e4
LT		 2984
2985 memset(&port, 0, sizeof(struct uart_port));
2986
4c0ebb80
AGR		 2987 if (share_irqs)
2988 irqflag = IRQF_SHARED;
2989
ec9f47cd 2990 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 2991 port.iobase = p->iobase;
2992 port.membase = p->membase;
2993 port.irq = p->irq;
1c2f0493 2994 port.irqflags = p->irqflags;
74a19741
WN		 2995 port.uartclk = p->uartclk;
2996 port.regshift = p->regshift;
2997 port.iotype = p->iotype;
2998 port.flags = p->flags;
2999 port.mapbase = p->mapbase;
3000 port.hub6 = p->hub6;
3001 port.private_data = p->private_data;
8e23fcc8 3002 port.type = p->type;
7d6a07d1
DD		 3003 port.serial_in = p->serial_in;
3004 port.serial_out = p->serial_out;
583d28e9 3005 port.handle_irq = p->handle_irq;
bf03f65b 3006 port.handle_break = p->handle_break;
235dae5d 3007 port.set_termios = p->set_termios;
c161afe9 3008 port.pm = p->pm;
74a19741 3009 port.dev = &dev->dev;
4c0ebb80 3010 port.irqflags |= irqflag;
ec9f47cd
RK		 3011 ret = serial8250_register_port(&port);
3012 if (ret < 0) {
3ae5eaec 3013 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 3014 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3015 p->iobase, (unsigned long long)p->mapbase,
3016 p->irq, ret);
ec9f47cd 3017 }
1da177e4
LT		 3018 }
3019 return 0;
3020}
3021
3022/*
3023 * Remove serial ports registered against a platform device.
3024 */
3ae5eaec 3025static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 3026{
3027 int i;
3028
a61c2d78 3029 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 3030 struct uart_8250_port *up = &serial8250_ports[i];
3031
3ae5eaec 3032 if (up->port.dev == &dev->dev)
1da177e4
LT		 3033 serial8250_unregister_port(i);
3034 }
3035 return 0;
3036}
3037
3ae5eaec 3038static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 3039{
3040 int i;
3041
1da177e4
LT		 3042 for (i = 0; i < UART_NR; i++) {
3043 struct uart_8250_port *up = &serial8250_ports[i];
3044
3ae5eaec 3045 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3046 uart_suspend_port(&serial8250_reg, &up->port);
3047 }
3048
3049 return 0;
3050}
3051
3ae5eaec 3052static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3053{
3054 int i;
3055
1da177e4
LT		 3056 for (i = 0; i < UART_NR; i++) {
3057 struct uart_8250_port *up = &serial8250_ports[i];
3058
3ae5eaec 3059 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3060 serial8250_resume_port(i);
1da177e4
LT		 3061 }
3062
3063 return 0;
3064}
3065
3ae5eaec 3066static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 3067 .probe = serial8250_probe,
3068 .remove = __devexit_p(serial8250_remove),
3069 .suspend = serial8250_suspend,
3070 .resume = serial8250_resume,
3ae5eaec
RK		 3071 .driver = {
3072 .name = "serial8250",
7493a314 3073 .owner = THIS_MODULE,
3ae5eaec 3074 },
1da177e4
LT		 3075};
3076
3077/*
3078 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3079 * in the table in include/asm/serial.h
3080 */
3081static struct platform_device *serial8250_isa_devs;
3082
3083/*
3084 * serial8250_register_port and serial8250_unregister_port allows for
3085 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3086 * modems and PCI multiport cards.
3087 */
f392ecfa 3088static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3089
3090static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3091{
3092 int i;
3093
3094 /*
3095 * First, find a port entry which matches.
3096 */
a61c2d78 3097 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3098 if (uart_match_port(&serial8250_ports[i].port, port))
3099 return &serial8250_ports[i];
3100
3101 /*
3102 * We didn't find a matching entry, so look for the first
3103 * free entry. We look for one which hasn't been previously
3104 * used (indicated by zero iobase).
3105 */
a61c2d78 3106 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3107 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3108 serial8250_ports[i].port.iobase == 0)
3109 return &serial8250_ports[i];
3110
3111 /*
3112 * That also failed. Last resort is to find any entry which
3113 * doesn't have a real port associated with it.
3114 */
a61c2d78 3115 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3116 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3117 return &serial8250_ports[i];
3118
3119 return NULL;
3120}
3121
3122/**
f73fa05b 3123 * serial8250_register_8250_port - register a serial port
58bcd332 3124 * @up: serial port template
1da177e4
LT		 3125 *
3126 * Configure the serial port specified by the request. If the
3127 * port exists and is in use, it is hung up and unregistered
3128 * first.
3129 *
3130 * The port is then probed and if necessary the IRQ is autodetected
3131 * If this fails an error is returned.
3132 *
3133 * On success the port is ready to use and the line number is returned.
3134 */
f73fa05b 3135int serial8250_register_8250_port(struct uart_8250_port *up)
1da177e4
LT		 3136{
3137 struct uart_8250_port *uart;
3138 int ret = -ENOSPC;
3139
f73fa05b 3140 if (up->port.uartclk == 0)
1da177e4
LT		 3141 return -EINVAL;
3142
f392ecfa 3143 mutex_lock(&serial_mutex);
1da177e4 3144
f73fa05b 3145 uart = serial8250_find_match_or_unused(&up->port);
1da177e4
LT		 3146 if (uart) {
3147 uart_remove_one_port(&serial8250_reg, &uart->port);
3148
f73fa05b
MD		 3149 uart->port.iobase = up->port.iobase;
3150 uart->port.membase = up->port.membase;
3151 uart->port.irq = up->port.irq;
3152 uart->port.irqflags = up->port.irqflags;
3153 uart->port.uartclk = up->port.uartclk;
3154 uart->port.fifosize = up->port.fifosize;
3155 uart->port.regshift = up->port.regshift;
3156 uart->port.iotype = up->port.iotype;
3157 uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF;
3158 uart->port.mapbase = up->port.mapbase;
3159 uart->port.private_data = up->port.private_data;
3160 if (up->port.dev)
3161 uart->port.dev = up->port.dev;
3162
3163 if (up->port.flags & UPF_FIXED_TYPE)
3164 serial8250_init_fixed_type_port(uart, up->port.type);
8e23fcc8 3165
7d6a07d1
DD		 3166 set_io_from_upio(&uart->port);
3167 /* Possibly override default I/O functions. */
f73fa05b
MD		 3168 if (up->port.serial_in)
3169 uart->port.serial_in = up->port.serial_in;
3170 if (up->port.serial_out)
3171 uart->port.serial_out = up->port.serial_out;
3172 if (up->port.handle_irq)
3173 uart->port.handle_irq = up->port.handle_irq;
235dae5d 3174 /* Possibly override set_termios call */
f73fa05b
MD		 3175 if (up->port.set_termios)
3176 uart->port.set_termios = up->port.set_termios;
3177 if (up->port.pm)
3178 uart->port.pm = up->port.pm;
3179 if (up->port.handle_break)
3180 uart->port.handle_break = up->port.handle_break;
3181 if (up->dl_read)
3182 uart->dl_read = up->dl_read;
3183 if (up->dl_write)
3184 uart->dl_write = up->dl_write;
1da177e4 3185
af7f3743
AC		 3186 if (serial8250_isa_config != NULL)
3187 serial8250_isa_config(0, &uart->port,
3188 &uart->capabilities);
3189
1da177e4
LT		 3190 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3191 if (ret == 0)
3192 ret = uart->port.line;
3193 }
f392ecfa 3194 mutex_unlock(&serial_mutex);
1da177e4
LT		 3195
3196 return ret;
3197}
f73fa05b
MD		 3198EXPORT_SYMBOL(serial8250_register_8250_port);
3199
3200/**
3201 * serial8250_register_port - register a serial port
3202 * @port: serial port template
3203 *
3204 * Configure the serial port specified by the request. If the
3205 * port exists and is in use, it is hung up and unregistered
3206 * first.
3207 *
3208 * The port is then probed and if necessary the IRQ is autodetected
3209 * If this fails an error is returned.
3210 *
3211 * On success the port is ready to use and the line number is returned.
3212 */
3213int serial8250_register_port(struct uart_port *port)
3214{
3215 struct uart_8250_port up;
3216
3217 memset(&up, 0, sizeof(up));
3218 memcpy(&up.port, port, sizeof(*port));
3219 return serial8250_register_8250_port(&up);
3220}
1da177e4
LT		 3221EXPORT_SYMBOL(serial8250_register_port);
3222
3223/**
3224 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3225 * @line: serial line number
3226 *
3227 * Remove one serial port. This may not be called from interrupt
3228 * context. We hand the port back to the our control.
3229 */
3230void serial8250_unregister_port(int line)
3231{
3232 struct uart_8250_port *uart = &serial8250_ports[line];
3233
f392ecfa 3234 mutex_lock(&serial_mutex);
1da177e4
LT		 3235 uart_remove_one_port(&serial8250_reg, &uart->port);
3236 if (serial8250_isa_devs) {
3237 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3238 uart->port.type = PORT_UNKNOWN;
3239 uart->port.dev = &serial8250_isa_devs->dev;
cb01ece3 3240 uart->capabilities = uart_config[uart->port.type].flags;
1da177e4
LT		 3241 uart_add_one_port(&serial8250_reg, &uart->port);
3242 } else {
3243 uart->port.dev = NULL;
3244 }
f392ecfa 3245 mutex_unlock(&serial_mutex);
1da177e4
LT		 3246}
3247EXPORT_SYMBOL(serial8250_unregister_port);
3248
3249static int __init serial8250_init(void)
3250{
25db8ad5 3251 int ret;
1da177e4 3252
a61c2d78
DJ		 3253 if (nr_uarts > UART_NR)
3254 nr_uarts = UART_NR;
3255
f1fb9bb8 3256 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3257 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3258 share_irqs ? "en" : "dis");
3259
b70ac771
DM		 3260#ifdef CONFIG_SPARC
3261 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3262#else
3263 serial8250_reg.nr = UART_NR;
1da177e4 3264 ret = uart_register_driver(&serial8250_reg);
b70ac771 3265#endif
1da177e4
LT		 3266 if (ret)
3267 goto out;
3268
7493a314
DT		 3269 serial8250_isa_devs = platform_device_alloc("serial8250",
3270 PLAT8250_DEV_LEGACY);
3271 if (!serial8250_isa_devs) {
3272 ret = -ENOMEM;
bc965a7f 3273 goto unreg_uart_drv;
1da177e4
LT		 3274 }
3275
7493a314
DT		 3276 ret = platform_device_add(serial8250_isa_devs);
3277 if (ret)
3278 goto put_dev;
3279
1da177e4
LT		 3280 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3281
bc965a7f
RK		 3282 ret = platform_driver_register(&serial8250_isa_driver);
3283 if (ret == 0)
3284 goto out;
1da177e4 3285
bc965a7f 3286 platform_device_del(serial8250_isa_devs);
25db8ad5 3287put_dev:
7493a314 3288 platform_device_put(serial8250_isa_devs);
25db8ad5 3289unreg_uart_drv:
b70ac771
DM		 3290#ifdef CONFIG_SPARC
3291 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3292#else
1da177e4 3293 uart_unregister_driver(&serial8250_reg);
b70ac771 3294#endif
25db8ad5 3295out:
1da177e4
LT		 3296 return ret;
3297}
3298
3299static void __exit serial8250_exit(void)
3300{
3301 struct platform_device *isa_dev = serial8250_isa_devs;
3302
3303 /*
3304 * This tells serial8250_unregister_port() not to re-register
3305 * the ports (thereby making serial8250_isa_driver permanently
3306 * in use.)
3307 */
3308 serial8250_isa_devs = NULL;
3309
3ae5eaec 3310 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3311 platform_device_unregister(isa_dev);
3312
b70ac771
DM		 3313#ifdef CONFIG_SPARC
3314 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3315#else
1da177e4 3316 uart_unregister_driver(&serial8250_reg);
b70ac771 3317#endif
1da177e4
LT		 3318}
3319
3320module_init(serial8250_init);
3321module_exit(serial8250_exit);
3322
3323EXPORT_SYMBOL(serial8250_suspend_port);
3324EXPORT_SYMBOL(serial8250_resume_port);
3325
3326MODULE_LICENSE("GPL");
d87a6d95 3327MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3328
3329module_param(share_irqs, uint, 0644);
3330MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3331 " (unsafe)");
3332
a61c2d78
DJ		 3333module_param(nr_uarts, uint, 0644);
3334MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3335
d41a4b51
CE		 3336module_param(skip_txen_test, uint, 0644);
3337MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3338
1da177e4
LT		 3339#ifdef CONFIG_SERIAL_8250_RSA
3340module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3341MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3342#endif
3343MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux kernel - Deliverables
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