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tty: serial: remove use of __devexit_p
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
1da177e4
LT		 13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
1da177e4
LT		 18
19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
1da177e4 29#include <linux/delay.h>
d052d1be 30#include <linux/platform_device.h>
1da177e4 31#include <linux/tty.h>
cd3ecad1 32#include <linux/ratelimit.h>
1da177e4
LT		 33#include <linux/tty_flip.h>
34#include <linux/serial_reg.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
78512ece 38#include <linux/nmi.h>
f392ecfa 39#include <linux/mutex.h>
5a0e3ad6 40#include <linux/slab.h>
6816383a
PG		 41#ifdef CONFIG_SPARC
42#include <linux/sunserialcore.h>
43#endif
1da177e4
LT		 44
45#include <asm/io.h>
46#include <asm/irq.h>
47
48#include "8250.h"
49
50/*
51 * Configuration:
40663cc7 52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 53 * is unsafe when used on edge-triggered interrupts.
54 */
408b664a 55static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 56
a61c2d78
DJ		 57static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
8440838b
DM		 59static struct uart_driver serial8250_reg;
60
61static int serial_index(struct uart_port *port)
62{
63 return (serial8250_reg.minor - 64) + port->line;
64}
65
d41a4b51
CE		 66static unsigned int skip_txen_test; /* force skip of txen test at init time */
67
1da177e4
LT		 68/*
69 * Debugging.
70 */
71#if 0
72#define DEBUG_AUTOCONF(fmt...) printk(fmt)
73#else
74#define DEBUG_AUTOCONF(fmt...) do { } while (0)
75#endif
76
77#if 0
78#define DEBUG_INTR(fmt...) printk(fmt)
79#else
80#define DEBUG_INTR(fmt...) do { } while (0)
81#endif
82
e7328ae1 83#define PASS_LIMIT 512
1da177e4 84
bca47613
DH		 85#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
86
87
1da177e4
LT		 88#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89#define CONFIG_SERIAL_DETECT_IRQ 1
90#endif
1da177e4
LT		 91#ifdef CONFIG_SERIAL_8250_MANY_PORTS
92#define CONFIG_SERIAL_MANY_PORTS 1
93#endif
94
95/*
96 * HUB6 is always on. This will be removed once the header
97 * files have been cleaned.
98 */
99#define CONFIG_HUB6 1
100
a4ed1e41 101#include <asm/serial.h>
1da177e4
LT		 102/*
103 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * standard enumeration mechanism. Platforms that can find all
105 * serial ports via mechanisms like ACPI or PCI need not supply it.
106 */
107#ifndef SERIAL_PORT_DFNS
108#define SERIAL_PORT_DFNS
109#endif
110
cb3592be 111static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
113};
114
026d02a2 115#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 116
117#ifdef CONFIG_SERIAL_8250_RSA
118
119#define PORT_RSA_MAX 4
120static unsigned long probe_rsa[PORT_RSA_MAX];
121static unsigned int probe_rsa_count;
122#endif /* CONFIG_SERIAL_8250_RSA */
123
1da177e4 124struct irq_info {
25db8ad5
AC		 125 struct hlist_node node;
126 int irq;
127 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 128 struct list_head *head;
129};
130
25db8ad5
AC		 131#define NR_IRQ_HASH 32 /* Can be adjusted later */
132static struct hlist_head irq_lists[NR_IRQ_HASH];
133static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 134
135/*
136 * Here we define the default xmit fifo size used for each type of UART.
137 */
138static const struct serial8250_config uart_config[] = {
139 [PORT_UNKNOWN] = {
140 .name = "unknown",
141 .fifo_size = 1,
142 .tx_loadsz = 1,
143 },
144 [PORT_8250] = {
145 .name = "8250",
146 .fifo_size = 1,
147 .tx_loadsz = 1,
148 },
149 [PORT_16450] = {
150 .name = "16450",
151 .fifo_size = 1,
152 .tx_loadsz = 1,
153 },
154 [PORT_16550] = {
155 .name = "16550",
156 .fifo_size = 1,
157 .tx_loadsz = 1,
158 },
159 [PORT_16550A] = {
160 .name = "16550A",
161 .fifo_size = 16,
162 .tx_loadsz = 16,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO,
165 },
166 [PORT_CIRRUS] = {
167 .name = "Cirrus",
168 .fifo_size = 1,
169 .tx_loadsz = 1,
170 },
171 [PORT_16650] = {
172 .name = "ST16650",
173 .fifo_size = 1,
174 .tx_loadsz = 1,
175 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
176 },
177 [PORT_16650V2] = {
178 .name = "ST16650V2",
179 .fifo_size = 32,
180 .tx_loadsz = 16,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
182 UART_FCR_T_TRIG_00,
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184 },
185 [PORT_16750] = {
186 .name = "TI16750",
187 .fifo_size = 64,
188 .tx_loadsz = 64,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
190 UART_FCR7_64BYTE,
191 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
192 },
193 [PORT_STARTECH] = {
194 .name = "Startech",
195 .fifo_size = 1,
196 .tx_loadsz = 1,
197 },
198 [PORT_16C950] = {
199 .name = "16C950/954",
200 .fifo_size = 128,
201 .tx_loadsz = 128,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
d0694e2a
PM		 203 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
1da177e4
LT		 205 },
206 [PORT_16654] = {
207 .name = "ST16654",
208 .fifo_size = 64,
209 .tx_loadsz = 32,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
211 UART_FCR_T_TRIG_10,
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
213 },
214 [PORT_16850] = {
215 .name = "XR16850",
216 .fifo_size = 128,
217 .tx_loadsz = 128,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220 },
221 [PORT_RSA] = {
222 .name = "RSA",
223 .fifo_size = 2048,
224 .tx_loadsz = 2048,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226 .flags = UART_CAP_FIFO,
227 },
228 [PORT_NS16550A] = {
229 .name = "NS16550A",
230 .fifo_size = 16,
231 .tx_loadsz = 16,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_NATSEMI,
234 },
235 [PORT_XSCALE] = {
236 .name = "XScale",
237 .fifo_size = 32,
238 .tx_loadsz = 32,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
4539c24f 240 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
1da177e4 241 },
bd71c182
TK		 242 [PORT_RM9000] = {
243 .name = "RM9000",
244 .fifo_size = 16,
245 .tx_loadsz = 16,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 247 .flags = UART_CAP_FIFO,
248 },
249 [PORT_OCTEON] = {
250 .name = "OCTEON",
251 .fifo_size = 64,
252 .tx_loadsz = 64,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 254 .flags = UART_CAP_FIFO,
255 },
08e0992f
FF		 256 [PORT_AR7] = {
257 .name = "AR7",
258 .fifo_size = 16,
259 .tx_loadsz = 16,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
261 .flags = UART_CAP_FIFO | UART_CAP_AFE,
262 },
235dae5d
PL		 263 [PORT_U6_16550A] = {
264 .name = "U6_16550A",
265 .fifo_size = 64,
266 .tx_loadsz = 64,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO | UART_CAP_AFE,
269 },
4539c24f
SW		 270 [PORT_TEGRA] = {
271 .name = "Tegra",
272 .fifo_size = 32,
273 .tx_loadsz = 8,
274 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
275 UART_FCR_T_TRIG_01,
276 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
277 },
06315348
SH		 278 [PORT_XR17D15X] = {
279 .name = "XR17D15X",
280 .fifo_size = 64,
281 .tx_loadsz = 64,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
283 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
284 },
7a514596
RS		 285 [PORT_LPC3220] = {
286 .name = "LPC3220",
287 .fifo_size = 64,
288 .tx_loadsz = 32,
289 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
290 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
291 .flags = UART_CAP_FIFO,
292 },
65ecc9c0
SY		 293 [PORT_8250_CIR] = {
294 .name = "CIR port"
295 }
1da177e4
LT		 296};
297
cc419fa0 298/* Uart divisor latch read */
e8155629 299static int default_serial_dl_read(struct uart_8250_port *up)
cc419fa0
MD		 300{
301 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
302}
303
304/* Uart divisor latch write */
e8155629 305static void default_serial_dl_write(struct uart_8250_port *up, int value)
cc419fa0
MD		 306{
307 serial_out(up, UART_DLL, value & 0xff);
308 serial_out(up, UART_DLM, value >> 8 & 0xff);
309}
310
6b416031 311#ifdef CONFIG_MIPS_ALCHEMY
21c614a7
PA		 312
313/* Au1x00 UART hardware has a weird register layout */
314static const u8 au_io_in_map[] = {
315 [UART_RX] = 0,
316 [UART_IER] = 2,
317 [UART_IIR] = 3,
318 [UART_LCR] = 5,
319 [UART_MCR] = 6,
320 [UART_LSR] = 7,
321 [UART_MSR] = 8,
322};
323
324static const u8 au_io_out_map[] = {
325 [UART_TX] = 1,
326 [UART_IER] = 2,
327 [UART_FCR] = 4,
328 [UART_LCR] = 5,
329 [UART_MCR] = 6,
330};
331
6b416031 332static unsigned int au_serial_in(struct uart_port *p, int offset)
21c614a7 333{
6b416031
MD		 334 offset = au_io_in_map[offset] << p->regshift;
335 return __raw_readl(p->membase + offset);
21c614a7
PA		 336}
337
6b416031 338static void au_serial_out(struct uart_port *p, int offset, int value)
21c614a7 339{
6b416031
MD		 340 offset = au_io_out_map[offset] << p->regshift;
341 __raw_writel(value, p->membase + offset);
342}
343
344/* Au1x00 haven't got a standard divisor latch */
345static int au_serial_dl_read(struct uart_8250_port *up)
346{
347 return __raw_readl(up->port.membase + 0x28);
348}
349
350static void au_serial_dl_write(struct uart_8250_port *up, int value)
351{
352 __raw_writel(value, up->port.membase + 0x28);
21c614a7
PA		 353}
354
6b416031
MD		 355#endif
356
28bf4cf2 357#ifdef CONFIG_SERIAL_8250_RM9K
bd71c182
TK		 358
359static const u8
360 regmap_in[8] = {
361 [UART_RX] = 0x00,
362 [UART_IER] = 0x0c,
363 [UART_IIR] = 0x14,
364 [UART_LCR] = 0x1c,
365 [UART_MCR] = 0x20,
366 [UART_LSR] = 0x24,
367 [UART_MSR] = 0x28,
368 [UART_SCR] = 0x2c
369 },
370 regmap_out[8] = {
371 [UART_TX] = 0x04,
372 [UART_IER] = 0x0c,
373 [UART_FCR] = 0x18,
374 [UART_LCR] = 0x1c,
375 [UART_MCR] = 0x20,
376 [UART_LSR] = 0x24,
377 [UART_MSR] = 0x28,
378 [UART_SCR] = 0x2c
379 };
380
28bf4cf2 381static unsigned int rm9k_serial_in(struct uart_port *p, int offset)
bd71c182 382{
28bf4cf2
MD		 383 offset = regmap_in[offset] << p->regshift;
384 return readl(p->membase + offset);
bd71c182
TK		 385}
386
28bf4cf2 387static void rm9k_serial_out(struct uart_port *p, int offset, int value)
bd71c182 388{
28bf4cf2
MD		 389 offset = regmap_out[offset] << p->regshift;
390 writel(value, p->membase + offset);
bd71c182
TK		 391}
392
28bf4cf2
MD		 393static int rm9k_serial_dl_read(struct uart_8250_port *up)
394{
395 return ((__raw_readl(up->port.membase + 0x10) << 8) |
396 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff;
397}
398
399static void rm9k_serial_dl_write(struct uart_8250_port *up, int value)
400{
401 __raw_writel(value, up->port.membase + 0x08);
402 __raw_writel(value >> 8, up->port.membase + 0x10);
403}
404
405#endif
21c614a7 406
7d6a07d1 407static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 408{
e8155629 409 offset = offset << p->regshift;
7d6a07d1
DD		 410 outb(p->hub6 - 1 + offset, p->iobase);
411 return inb(p->iobase + 1);
412}
1da177e4 413
7d6a07d1
DD		 414static void hub6_serial_out(struct uart_port *p, int offset, int value)
415{
e8155629 416 offset = offset << p->regshift;
7d6a07d1
DD		 417 outb(p->hub6 - 1 + offset, p->iobase);
418 outb(value, p->iobase + 1);
419}
1da177e4 420
7d6a07d1
DD		 421static unsigned int mem_serial_in(struct uart_port *p, int offset)
422{
e8155629 423 offset = offset << p->regshift;
7d6a07d1
DD		 424 return readb(p->membase + offset);
425}
1da177e4 426
7d6a07d1
DD		 427static void mem_serial_out(struct uart_port *p, int offset, int value)
428{
e8155629 429 offset = offset << p->regshift;
7d6a07d1
DD		 430 writeb(value, p->membase + offset);
431}
432
433static void mem32_serial_out(struct uart_port *p, int offset, int value)
434{
e8155629 435 offset = offset << p->regshift;
7d6a07d1
DD		 436 writel(value, p->membase + offset);
437}
438
439static unsigned int mem32_serial_in(struct uart_port *p, int offset)
440{
e8155629 441 offset = offset << p->regshift;
7d6a07d1
DD		 442 return readl(p->membase + offset);
443}
1da177e4 444
7d6a07d1
DD		 445static unsigned int io_serial_in(struct uart_port *p, int offset)
446{
e8155629 447 offset = offset << p->regshift;
7d6a07d1
DD		 448 return inb(p->iobase + offset);
449}
450
451static void io_serial_out(struct uart_port *p, int offset, int value)
452{
e8155629 453 offset = offset << p->regshift;
7d6a07d1
DD		 454 outb(value, p->iobase + offset);
455}
456
583d28e9
JI		 457static int serial8250_default_handle_irq(struct uart_port *port);
458
7d6a07d1
DD		 459static void set_io_from_upio(struct uart_port *p)
460{
49d5741b
JI		 461 struct uart_8250_port *up =
462 container_of(p, struct uart_8250_port, port);
cc419fa0 463
e8155629
MD		 464 up->dl_read = default_serial_dl_read;
465 up->dl_write = default_serial_dl_write;
cc419fa0 466
7d6a07d1 467 switch (p->iotype) {
1da177e4 468 case UPIO_HUB6:
7d6a07d1
DD		 469 p->serial_in = hub6_serial_in;
470 p->serial_out = hub6_serial_out;
1da177e4
LT		 471 break;
472
473 case UPIO_MEM:
7d6a07d1
DD		 474 p->serial_in = mem_serial_in;
475 p->serial_out = mem_serial_out;
1da177e4
LT		 476 break;
477
478 case UPIO_MEM32:
7d6a07d1
DD		 479 p->serial_in = mem32_serial_in;
480 p->serial_out = mem32_serial_out;
1da177e4
LT		 481 break;
482
28bf4cf2
MD		 483#ifdef CONFIG_SERIAL_8250_RM9K
484 case UPIO_RM9000:
485 p->serial_in = rm9k_serial_in;
486 p->serial_out = rm9k_serial_out;
487 up->dl_read = rm9k_serial_dl_read;
488 up->dl_write = rm9k_serial_dl_write;
489 break;
490#endif
491
6b416031 492#ifdef CONFIG_MIPS_ALCHEMY
21c614a7 493 case UPIO_AU:
7d6a07d1
DD		 494 p->serial_in = au_serial_in;
495 p->serial_out = au_serial_out;
6b416031
MD		 496 up->dl_read = au_serial_dl_read;
497 up->dl_write = au_serial_dl_write;
21c614a7 498 break;
6b416031 499#endif
12bf3f24 500
1da177e4 501 default:
7d6a07d1
DD		 502 p->serial_in = io_serial_in;
503 p->serial_out = io_serial_out;
504 break;
1da177e4 505 }
b8e7e40a
AC		 506 /* Remember loaded iotype */
507 up->cur_iotype = p->iotype;
583d28e9 508 p->handle_irq = serial8250_default_handle_irq;
1da177e4
LT		 509}
510
40b36daa 511static void
55e4016d 512serial_port_out_sync(struct uart_port *p, int offset, int value)
40b36daa 513{
7d6a07d1 514 switch (p->iotype) {
40b36daa
AW		 515 case UPIO_MEM:
516 case UPIO_MEM32:
40b36daa 517 case UPIO_AU:
7d6a07d1
DD		 518 p->serial_out(p, offset, value);
519 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 520 break;
521 default:
7d6a07d1 522 p->serial_out(p, offset, value);
40b36daa
AW		 523 }
524}
525
1da177e4
LT		 526/*
527 * For the 16C950
528 */
529static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
530{
531 serial_out(up, UART_SCR, offset);
532 serial_out(up, UART_ICR, value);
533}
534
535static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
536{
537 unsigned int value;
538
539 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
540 serial_out(up, UART_SCR, offset);
541 value = serial_in(up, UART_ICR);
542 serial_icr_write(up, UART_ACR, up->acr);
543
544 return value;
545}
546
547/*
548 * FIFO support.
549 */
b5d674ab 550static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 551{
552 if (p->capabilities & UART_CAP_FIFO) {
0acf519f
PG		 553 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
554 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
1da177e4 555 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0acf519f 556 serial_out(p, UART_FCR, 0);
1da177e4
LT		 557 }
558}
559
0ad372b9
SM		 560void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
561{
562 unsigned char fcr;
563
564 serial8250_clear_fifos(p);
565 fcr = uart_config[p->port.type].fcr;
566 serial_out(p, UART_FCR, fcr);
567}
568EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
569
1da177e4
LT		 570/*
571 * IER sleep support. UARTs which have EFRs need the "extended
572 * capability" bit enabled. Note that on XR16C850s, we need to
573 * reset LCR to write to IER.
574 */
b5d674ab 575static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4
LT		 576{
577 if (p->capabilities & UART_CAP_SLEEP) {
578 if (p->capabilities & UART_CAP_EFR) {
0acf519f
PG		 579 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
580 serial_out(p, UART_EFR, UART_EFR_ECB);
581 serial_out(p, UART_LCR, 0);
1da177e4 582 }
0acf519f 583 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
1da177e4 584 if (p->capabilities & UART_CAP_EFR) {
0acf519f
PG		 585 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
586 serial_out(p, UART_EFR, 0);
587 serial_out(p, UART_LCR, 0);
1da177e4
LT		 588 }
589 }
590}
591
592#ifdef CONFIG_SERIAL_8250_RSA
593/*
594 * Attempts to turn on the RSA FIFO. Returns zero on failure.
595 * We set the port uart clock rate if we succeed.
596 */
597static int __enable_rsa(struct uart_8250_port *up)
598{
599 unsigned char mode;
600 int result;
601
0acf519f 602 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 603 result = mode & UART_RSA_MSR_FIFO;
604
605 if (!result) {
0acf519f
PG		 606 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
607 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 608 result = mode & UART_RSA_MSR_FIFO;
609 }
610
611 if (result)
612 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
613
614 return result;
615}
616
617static void enable_rsa(struct uart_8250_port *up)
618{
619 if (up->port.type == PORT_RSA) {
620 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
621 spin_lock_irq(&up->port.lock);
622 __enable_rsa(up);
623 spin_unlock_irq(&up->port.lock);
624 }
625 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
0acf519f 626 serial_out(up, UART_RSA_FRR, 0);
1da177e4
LT		 627 }
628}
629
630/*
631 * Attempts to turn off the RSA FIFO. Returns zero on failure.
632 * It is unknown why interrupts were disabled in here. However,
633 * the caller is expected to preserve this behaviour by grabbing
634 * the spinlock before calling this function.
635 */
636static void disable_rsa(struct uart_8250_port *up)
637{
638 unsigned char mode;
639 int result;
640
641 if (up->port.type == PORT_RSA &&
642 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
643 spin_lock_irq(&up->port.lock);
644
0acf519f 645 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 646 result = !(mode & UART_RSA_MSR_FIFO);
647
648 if (!result) {
0acf519f
PG		 649 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
650 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 651 result = !(mode & UART_RSA_MSR_FIFO);
652 }
653
654 if (result)
655 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
656 spin_unlock_irq(&up->port.lock);
657 }
658}
659#endif /* CONFIG_SERIAL_8250_RSA */
660
661/*
662 * This is a quickie test to see how big the FIFO is.
663 * It doesn't work at all the time, more's the pity.
664 */
665static int size_fifo(struct uart_8250_port *up)
666{
b32b19b8
JAH		 667 unsigned char old_fcr, old_mcr, old_lcr;
668 unsigned short old_dl;
1da177e4
LT		 669 int count;
670
0acf519f
PG		 671 old_lcr = serial_in(up, UART_LCR);
672 serial_out(up, UART_LCR, 0);
673 old_fcr = serial_in(up, UART_FCR);
674 old_mcr = serial_in(up, UART_MCR);
675 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1da177e4 676 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0acf519f
PG		 677 serial_out(up, UART_MCR, UART_MCR_LOOP);
678 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8
JAH		 679 old_dl = serial_dl_read(up);
680 serial_dl_write(up, 0x0001);
0acf519f 681 serial_out(up, UART_LCR, 0x03);
1da177e4 682 for (count = 0; count < 256; count++)
0acf519f 683 serial_out(up, UART_TX, count);
1da177e4 684 mdelay(20);/* FIXME - schedule_timeout */
0acf519f 685 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
1da177e4 686 (count < 256); count++)
0acf519f
PG		 687 serial_in(up, UART_RX);
688 serial_out(up, UART_FCR, old_fcr);
689 serial_out(up, UART_MCR, old_mcr);
690 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8 691 serial_dl_write(up, old_dl);
0acf519f 692 serial_out(up, UART_LCR, old_lcr);
1da177e4
LT		 693
694 return count;
695}
696
697/*
698 * Read UART ID using the divisor method - set DLL and DLM to zero
699 * and the revision will be in DLL and device type in DLM. We
700 * preserve the device state across this.
701 */
702static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
703{
704 unsigned char old_dll, old_dlm, old_lcr;
705 unsigned int id;
706
0acf519f
PG		 707 old_lcr = serial_in(p, UART_LCR);
708 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4 709
0acf519f
PG		 710 old_dll = serial_in(p, UART_DLL);
711 old_dlm = serial_in(p, UART_DLM);
1da177e4 712
0acf519f
PG		 713 serial_out(p, UART_DLL, 0);
714 serial_out(p, UART_DLM, 0);
1da177e4 715
0acf519f 716 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
1da177e4 717
0acf519f
PG		 718 serial_out(p, UART_DLL, old_dll);
719 serial_out(p, UART_DLM, old_dlm);
720 serial_out(p, UART_LCR, old_lcr);
1da177e4
LT		 721
722 return id;
723}
724
725/*
726 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
727 * When this function is called we know it is at least a StarTech
728 * 16650 V2, but it might be one of several StarTech UARTs, or one of
729 * its clones. (We treat the broken original StarTech 16650 V1 as a
730 * 16550, and why not? Startech doesn't seem to even acknowledge its
731 * existence.)
bd71c182 732 *
1da177e4
LT		 733 * What evil have men's minds wrought...
734 */
735static void autoconfig_has_efr(struct uart_8250_port *up)
736{
737 unsigned int id1, id2, id3, rev;
738
739 /*
740 * Everything with an EFR has SLEEP
741 */
742 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
743
744 /*
745 * First we check to see if it's an Oxford Semiconductor UART.
746 *
747 * If we have to do this here because some non-National
748 * Semiconductor clone chips lock up if you try writing to the
749 * LSR register (which serial_icr_read does)
750 */
751
752 /*
753 * Check for Oxford Semiconductor 16C950.
754 *
755 * EFR [4] must be set else this test fails.
756 *
757 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
758 * claims that it's needed for 952 dual UART's (which are not
759 * recommended for new designs).
760 */
761 up->acr = 0;
662b083a 762 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 763 serial_out(up, UART_EFR, UART_EFR_ECB);
764 serial_out(up, UART_LCR, 0x00);
765 id1 = serial_icr_read(up, UART_ID1);
766 id2 = serial_icr_read(up, UART_ID2);
767 id3 = serial_icr_read(up, UART_ID3);
768 rev = serial_icr_read(up, UART_REV);
769
770 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
771
772 if (id1 == 0x16 && id2 == 0xC9 &&
773 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
774 up->port.type = PORT_16C950;
4ba5e35d
RK		 775
776 /*
777 * Enable work around for the Oxford Semiconductor 952 rev B
778 * chip which causes it to seriously miscalculate baud rates
779 * when DLL is 0.
780 */
781 if (id3 == 0x52 && rev == 0x01)
782 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 783 return;
784 }
bd71c182 785
1da177e4
LT		 786 /*
787 * We check for a XR16C850 by setting DLL and DLM to 0, and then
788 * reading back DLL and DLM. The chip type depends on the DLM
789 * value read back:
790 * 0x10 - XR16C850 and the DLL contains the chip revision.
791 * 0x12 - XR16C2850.
792 * 0x14 - XR16C854.
793 */
794 id1 = autoconfig_read_divisor_id(up);
795 DEBUG_AUTOCONF("850id=%04x ", id1);
796
797 id2 = id1 >> 8;
798 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 799 up->port.type = PORT_16850;
800 return;
801 }
802
803 /*
804 * It wasn't an XR16C850.
805 *
806 * We distinguish between the '654 and the '650 by counting
807 * how many bytes are in the FIFO. I'm using this for now,
808 * since that's the technique that was sent to me in the
809 * serial driver update, but I'm not convinced this works.
810 * I've had problems doing this in the past. -TYT
811 */
812 if (size_fifo(up) == 64)
813 up->port.type = PORT_16654;
814 else
815 up->port.type = PORT_16650V2;
816}
817
818/*
819 * We detected a chip without a FIFO. Only two fall into
820 * this category - the original 8250 and the 16450. The
821 * 16450 has a scratch register (accessible with LCR=0)
822 */
823static void autoconfig_8250(struct uart_8250_port *up)
824{
825 unsigned char scratch, status1, status2;
826
827 up->port.type = PORT_8250;
828
829 scratch = serial_in(up, UART_SCR);
0acf519f 830 serial_out(up, UART_SCR, 0xa5);
1da177e4 831 status1 = serial_in(up, UART_SCR);
0acf519f 832 serial_out(up, UART_SCR, 0x5a);
1da177e4 833 status2 = serial_in(up, UART_SCR);
0acf519f 834 serial_out(up, UART_SCR, scratch);
1da177e4
LT		 835
836 if (status1 == 0xa5 && status2 == 0x5a)
837 up->port.type = PORT_16450;
838}
839
840static int broken_efr(struct uart_8250_port *up)
841{
842 /*
843 * Exar ST16C2550 "A2" devices incorrectly detect as
844 * having an EFR, and report an ID of 0x0201. See
631dd1a8 845 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1da177e4
LT		 846 */
847 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
848 return 1;
849
850 return 0;
851}
852
0d0389e5
YK		 853static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
854{
855 unsigned char status;
856
857 status = serial_in(up, 0x04); /* EXCR2 */
858#define PRESL(x) ((x) & 0x30)
859 if (PRESL(status) == 0x10) {
860 /* already in high speed mode */
861 return 0;
862 } else {
863 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
864 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
0acf519f 865 serial_out(up, 0x04, status);
0d0389e5
YK		 866 }
867 return 1;
868}
869
1da177e4
LT		 870/*
871 * We know that the chip has FIFOs. Does it have an EFR? The
872 * EFR is located in the same register position as the IIR and
873 * we know the top two bits of the IIR are currently set. The
874 * EFR should contain zero. Try to read the EFR.
875 */
876static void autoconfig_16550a(struct uart_8250_port *up)
877{
878 unsigned char status1, status2;
879 unsigned int iersave;
880
881 up->port.type = PORT_16550A;
882 up->capabilities |= UART_CAP_FIFO;
883
884 /*
885 * Check for presence of the EFR when DLAB is set.
886 * Only ST16C650V1 UARTs pass this test.
887 */
0acf519f 888 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4 889 if (serial_in(up, UART_EFR) == 0) {
0acf519f 890 serial_out(up, UART_EFR, 0xA8);
1da177e4
LT		 891 if (serial_in(up, UART_EFR) != 0) {
892 DEBUG_AUTOCONF("EFRv1 ");
893 up->port.type = PORT_16650;
894 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
895 } else {
896 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
897 }
0acf519f 898 serial_out(up, UART_EFR, 0);
1da177e4
LT		 899 return;
900 }
901
902 /*
903 * Maybe it requires 0xbf to be written to the LCR.
904 * (other ST16C650V2 UARTs, TI16C752A, etc)
905 */
0acf519f 906 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 907 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
908 DEBUG_AUTOCONF("EFRv2 ");
909 autoconfig_has_efr(up);
910 return;
911 }
912
913 /*
914 * Check for a National Semiconductor SuperIO chip.
915 * Attempt to switch to bank 2, read the value of the LOOP bit
916 * from EXCR1. Switch back to bank 0, change it in MCR. Then
917 * switch back to bank 2, read it from EXCR1 again and check
918 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4 919 */
0acf519f 920 serial_out(up, UART_LCR, 0);
1da177e4 921 status1 = serial_in(up, UART_MCR);
0acf519f 922 serial_out(up, UART_LCR, 0xE0);
1da177e4
LT		 923 status2 = serial_in(up, 0x02); /* EXCR1 */
924
925 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
0acf519f
PG		 926 serial_out(up, UART_LCR, 0);
927 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
928 serial_out(up, UART_LCR, 0xE0);
1da177e4 929 status2 = serial_in(up, 0x02); /* EXCR1 */
0acf519f
PG		 930 serial_out(up, UART_LCR, 0);
931 serial_out(up, UART_MCR, status1);
1da177e4
LT		 932
933 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 934 unsigned short quot;
935
0acf519f 936 serial_out(up, UART_LCR, 0xE0);
857dde2e 937
b32b19b8 938 quot = serial_dl_read(up);
857dde2e
DW		 939 quot <<= 3;
940
0d0389e5
YK		 941 if (ns16550a_goto_highspeed(up))
942 serial_dl_write(up, quot);
857dde2e 943
0acf519f 944 serial_out(up, UART_LCR, 0);
1da177e4 945
857dde2e 946 up->port.uartclk = 921600*16;
1da177e4
LT		 947 up->port.type = PORT_NS16550A;
948 up->capabilities |= UART_NATSEMI;
949 return;
950 }
951 }
952
953 /*
954 * No EFR. Try to detect a TI16750, which only sets bit 5 of
955 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
956 * Try setting it with and without DLAB set. Cheap clones
957 * set bit 5 without DLAB set.
958 */
0acf519f
PG		 959 serial_out(up, UART_LCR, 0);
960 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1da177e4 961 status1 = serial_in(up, UART_IIR) >> 5;
0acf519f
PG		 962 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
963 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
964 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1da177e4 965 status2 = serial_in(up, UART_IIR) >> 5;
0acf519f
PG		 966 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
967 serial_out(up, UART_LCR, 0);
1da177e4
LT		 968
969 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
970
971 if (status1 == 6 && status2 == 7) {
972 up->port.type = PORT_16750;
973 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
974 return;
975 }
976
977 /*
978 * Try writing and reading the UART_IER_UUE bit (b6).
979 * If it works, this is probably one of the Xscale platform's
980 * internal UARTs.
981 * We're going to explicitly set the UUE bit to 0 before
982 * trying to write and read a 1 just to make sure it's not
983 * already a 1 and maybe locked there before we even start start.
984 */
985 iersave = serial_in(up, UART_IER);
0acf519f 986 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1da177e4
LT		 987 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
988 /*
989 * OK it's in a known zero state, try writing and reading
990 * without disturbing the current state of the other bits.
991 */
0acf519f 992 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1da177e4
LT		 993 if (serial_in(up, UART_IER) & UART_IER_UUE) {
994 /*
995 * It's an Xscale.
996 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
997 */
998 DEBUG_AUTOCONF("Xscale ");
999 up->port.type = PORT_XSCALE;
5568181f 1000 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1da177e4
LT		 1001 return;
1002 }
1003 } else {
1004 /*
1005 * If we got here we couldn't force the IER_UUE bit to 0.
1006 * Log it and continue.
1007 */
1008 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1009 }
0acf519f 1010 serial_out(up, UART_IER, iersave);
235dae5d 1011
06315348
SH		 1012 /*
1013 * Exar uarts have EFR in a weird location
1014 */
1015 if (up->port.flags & UPF_EXAR_EFR) {
1016 up->port.type = PORT_XR17D15X;
1017 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1018 }
1019
235dae5d
PL		 1020 /*
1021 * We distinguish between 16550A and U6 16550A by counting
1022 * how many bytes are in the FIFO.
1023 */
1024 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1025 up->port.type = PORT_U6_16550A;
1026 up->capabilities |= UART_CAP_AFE;
1027 }
1da177e4
LT		 1028}
1029
1030/*
1031 * This routine is called by rs_init() to initialize a specific serial
1032 * port. It determines what type of UART chip this serial port is
1033 * using: 8250, 16450, 16550, 16550A. The important question is
1034 * whether or not this UART is a 16550A or not, since this will
1035 * determine whether or not we can use its FIFO features or not.
1036 */
1037static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1038{
1039 unsigned char status1, scratch, scratch2, scratch3;
1040 unsigned char save_lcr, save_mcr;
dfe42443 1041 struct uart_port *port = &up->port;
1da177e4 1042 unsigned long flags;
bd21f551 1043 unsigned int old_capabilities;
1da177e4 1044
dfe42443 1045 if (!port->iobase && !port->mapbase && !port->membase)
1da177e4
LT		 1046 return;
1047
80647b95 1048 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
dfe42443 1049 serial_index(port), port->iobase, port->membase);
1da177e4
LT		 1050
1051 /*
1052 * We really do need global IRQs disabled here - we're going to
1053 * be frobbing the chips IRQ enable register to see if it exists.
1054 */
dfe42443 1055 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 1056
1057 up->capabilities = 0;
4ba5e35d 1058 up->bugs = 0;
1da177e4 1059
dfe42443 1060 if (!(port->flags & UPF_BUGGY_UART)) {
1da177e4
LT		 1061 /*
1062 * Do a simple existence test first; if we fail this,
1063 * there's no point trying anything else.
bd71c182 1064 *
1da177e4
LT		 1065 * 0x80 is used as a nonsense port to prevent against
1066 * false positives due to ISA bus float. The
1067 * assumption is that 0x80 is a non-existent port;
1068 * which should be safe since include/asm/io.h also
1069 * makes this assumption.
1070 *
1071 * Note: this is safe as long as MCR bit 4 is clear
1072 * and the device is in "PC" mode.
1073 */
0acf519f
PG		 1074 scratch = serial_in(up, UART_IER);
1075 serial_out(up, UART_IER, 0);
1da177e4
LT		 1076#ifdef __i386__
1077 outb(0xff, 0x080);
1078#endif
48212008
TH		 1079 /*
1080 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1081 * 16C754B) allow only to modify them if an EFR bit is set.
1082 */
0acf519f
PG		 1083 scratch2 = serial_in(up, UART_IER) & 0x0f;
1084 serial_out(up, UART_IER, 0x0F);
1da177e4
LT		 1085#ifdef __i386__
1086 outb(0, 0x080);
1087#endif
0acf519f
PG		 1088 scratch3 = serial_in(up, UART_IER) & 0x0f;
1089 serial_out(up, UART_IER, scratch);
1da177e4
LT		 1090 if (scratch2 != 0 || scratch3 != 0x0F) {
1091 /*
1092 * We failed; there's nothing here
1093 */
bd21f551 1094 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1095 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1096 scratch2, scratch3);
1097 goto out;
1098 }
1099 }
1100
1101 save_mcr = serial_in(up, UART_MCR);
1102 save_lcr = serial_in(up, UART_LCR);
1103
bd71c182 1104 /*
1da177e4
LT		 1105 * Check to see if a UART is really there. Certain broken
1106 * internal modems based on the Rockwell chipset fail this
1107 * test, because they apparently don't implement the loopback
1108 * test mode. So this test is skipped on the COM 1 through
1109 * COM 4 ports. This *should* be safe, since no board
1110 * manufacturer would be stupid enough to design a board
1111 * that conflicts with COM 1-4 --- we hope!
1112 */
dfe42443 1113 if (!(port->flags & UPF_SKIP_TEST)) {
0acf519f
PG		 1114 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1115 status1 = serial_in(up, UART_MSR) & 0xF0;
1116 serial_out(up, UART_MCR, save_mcr);
1da177e4 1117 if (status1 != 0x90) {
bd21f551 1118 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1119 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1120 status1);
1121 goto out;
1122 }
1123 }
1124
1125 /*
1126 * We're pretty sure there's a port here. Lets find out what
1127 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1128 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1129 * determines what we test for next.
1130 *
1131 * We also initialise the EFR (if any) to zero for later. The
1132 * EFR occupies the same register location as the FCR and IIR.
1133 */
0acf519f
PG		 1134 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1135 serial_out(up, UART_EFR, 0);
1136 serial_out(up, UART_LCR, 0);
1da177e4 1137
0acf519f 1138 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1da177e4
LT		 1139 scratch = serial_in(up, UART_IIR) >> 6;
1140
1da177e4
LT		 1141 switch (scratch) {
1142 case 0:
1143 autoconfig_8250(up);
1144 break;
1145 case 1:
dfe42443 1146 port->type = PORT_UNKNOWN;
1da177e4
LT		 1147 break;
1148 case 2:
dfe42443 1149 port->type = PORT_16550;
1da177e4
LT		 1150 break;
1151 case 3:
1152 autoconfig_16550a(up);
1153 break;
1154 }
1155
1156#ifdef CONFIG_SERIAL_8250_RSA
1157 /*
1158 * Only probe for RSA ports if we got the region.
1159 */
dfe42443 1160 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1da177e4
LT		 1161 int i;
1162
1163 for (i = 0 ; i < probe_rsa_count; ++i) {
dfe42443
PG		 1164 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1165 port->type = PORT_RSA;
1da177e4
LT		 1166 break;
1167 }
1168 }
1169 }
1170#endif
21c614a7 1171
0acf519f 1172 serial_out(up, UART_LCR, save_lcr);
1da177e4 1173
dfe42443 1174 port->fifosize = uart_config[up->port.type].fifo_size;
bd21f551 1175 old_capabilities = up->capabilities;
dfe42443
PG		 1176 up->capabilities = uart_config[port->type].flags;
1177 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1da177e4 1178
dfe42443 1179 if (port->type == PORT_UNKNOWN)
bd21f551 1180 goto out_lock;
1da177e4
LT		 1181
1182 /*
1183 * Reset the UART.
1184 */
1185#ifdef CONFIG_SERIAL_8250_RSA
dfe42443 1186 if (port->type == PORT_RSA)
0acf519f 1187 serial_out(up, UART_RSA_FRR, 0);
1da177e4 1188#endif
0acf519f 1189 serial_out(up, UART_MCR, save_mcr);
1da177e4 1190 serial8250_clear_fifos(up);
40b36daa 1191 serial_in(up, UART_RX);
5c8c755c 1192 if (up->capabilities & UART_CAP_UUE)
0acf519f 1193 serial_out(up, UART_IER, UART_IER_UUE);
5c8c755c 1194 else
0acf519f 1195 serial_out(up, UART_IER, 0);
1da177e4 1196
bd21f551 1197out_lock:
dfe42443 1198 spin_unlock_irqrestore(&port->lock, flags);
bd21f551
FL		 1199 if (up->capabilities != old_capabilities) {
1200 printk(KERN_WARNING
1201 "ttyS%d: detected caps %08x should be %08x\n",
1202 serial_index(port), old_capabilities,
1203 up->capabilities);
1204 }
1205out:
1206 DEBUG_AUTOCONF("iir=%d ", scratch);
dfe42443 1207 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1da177e4
LT		 1208}
1209
1210static void autoconfig_irq(struct uart_8250_port *up)
1211{
dfe42443 1212 struct uart_port *port = &up->port;
1da177e4
LT		 1213 unsigned char save_mcr, save_ier;
1214 unsigned char save_ICP = 0;
1215 unsigned int ICP = 0;
1216 unsigned long irqs;
1217 int irq;
1218
dfe42443
PG		 1219 if (port->flags & UPF_FOURPORT) {
1220 ICP = (port->iobase & 0xfe0) | 0x1f;
1da177e4
LT		 1221 save_ICP = inb_p(ICP);
1222 outb_p(0x80, ICP);
0d263a26 1223 inb_p(ICP);
1da177e4
LT		 1224 }
1225
1226 /* forget possible initially masked and pending IRQ */
1227 probe_irq_off(probe_irq_on());
0acf519f
PG		 1228 save_mcr = serial_in(up, UART_MCR);
1229 save_ier = serial_in(up, UART_IER);
1230 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1231
1da177e4 1232 irqs = probe_irq_on();
0acf519f 1233 serial_out(up, UART_MCR, 0);
6f803cd0 1234 udelay(10);
dfe42443 1235 if (port->flags & UPF_FOURPORT) {
0acf519f 1236 serial_out(up, UART_MCR,
1da177e4
LT		 1237 UART_MCR_DTR | UART_MCR_RTS);
1238 } else {
0acf519f 1239 serial_out(up, UART_MCR,
1da177e4
LT		 1240 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1241 }
0acf519f 1242 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
0d263a26
PG		 1243 serial_in(up, UART_LSR);
1244 serial_in(up, UART_RX);
1245 serial_in(up, UART_IIR);
1246 serial_in(up, UART_MSR);
0acf519f 1247 serial_out(up, UART_TX, 0xFF);
6f803cd0 1248 udelay(20);
1da177e4
LT		 1249 irq = probe_irq_off(irqs);
1250
0acf519f
PG		 1251 serial_out(up, UART_MCR, save_mcr);
1252 serial_out(up, UART_IER, save_ier);
1da177e4 1253
dfe42443 1254 if (port->flags & UPF_FOURPORT)
1da177e4
LT		 1255 outb_p(save_ICP, ICP);
1256
dfe42443 1257 port->irq = (irq > 0) ? irq : 0;
1da177e4
LT		 1258}
1259
e763b90c
RK		 1260static inline void __stop_tx(struct uart_8250_port *p)
1261{
1262 if (p->ier & UART_IER_THRI) {
1263 p->ier &= ~UART_IER_THRI;
1264 serial_out(p, UART_IER, p->ier);
1265 }
1266}
1267
b129a8cc 1268static void serial8250_stop_tx(struct uart_port *port)
1da177e4 1269{
49d5741b
JI		 1270 struct uart_8250_port *up =
1271 container_of(port, struct uart_8250_port, port);
1da177e4 1272
e763b90c 1273 __stop_tx(up);
1da177e4
LT		 1274
1275 /*
e763b90c 1276 * We really want to stop the transmitter from sending.
1da177e4 1277 */
dfe42443 1278 if (port->type == PORT_16C950) {
1da177e4
LT		 1279 up->acr |= UART_ACR_TXDIS;
1280 serial_icr_write(up, UART_ACR, up->acr);
1281 }
1282}
1283
b129a8cc 1284static void serial8250_start_tx(struct uart_port *port)
1da177e4 1285{
49d5741b
JI		 1286 struct uart_8250_port *up =
1287 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1288
1289 if (!(up->ier & UART_IER_THRI)) {
1290 up->ier |= UART_IER_THRI;
4fd996a1 1291 serial_port_out(port, UART_IER, up->ier);
55d3b282 1292
67f7654e 1293 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1294 unsigned char lsr;
55d3b282 1295 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1296 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
dfe42443 1297 if ((port->type == PORT_RM9000) ?
68cb4f8e
IJ		 1298 (lsr & UART_LSR_THRE) :
1299 (lsr & UART_LSR_TEMT))
3986fb2b 1300 serial8250_tx_chars(up);
55d3b282 1301 }
1da177e4 1302 }
e763b90c 1303
1da177e4 1304 /*
e763b90c 1305 * Re-enable the transmitter if we disabled it.
1da177e4 1306 */
dfe42443 1307 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1308 up->acr &= ~UART_ACR_TXDIS;
1309 serial_icr_write(up, UART_ACR, up->acr);
1310 }
1311}
1312
1313static void serial8250_stop_rx(struct uart_port *port)
1314{
49d5741b
JI		 1315 struct uart_8250_port *up =
1316 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1317
1318 up->ier &= ~UART_IER_RLSI;
1319 up->port.read_status_mask &= ~UART_LSR_DR;
4fd996a1 1320 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 1321}
1322
1323static void serial8250_enable_ms(struct uart_port *port)
1324{
49d5741b
JI		 1325 struct uart_8250_port *up =
1326 container_of(port, struct uart_8250_port, port);
1da177e4 1327
21c614a7
PA		 1328 /* no MSR capabilities */
1329 if (up->bugs & UART_BUG_NOMSR)
1330 return;
1331
1da177e4 1332 up->ier |= UART_IER_MSI;
4fd996a1 1333 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 1334}
1335
0690f41f 1336/*
3986fb2b 1337 * serial8250_rx_chars: processes according to the passed in LSR
0690f41f
PG		 1338 * value, and returns the remaining LSR bits not handled
1339 * by this Rx routine.
1340 */
3986fb2b
PG		 1341unsigned char
1342serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1da177e4 1343{
dfe42443
PG		 1344 struct uart_port *port = &up->port;
1345 struct tty_struct *tty = port->state->port.tty;
0690f41f 1346 unsigned char ch;
1da177e4
LT		 1347 int max_count = 256;
1348 char flag;
1349
1350 do {
7500b1f6 1351 if (likely(lsr & UART_LSR_DR))
0acf519f 1352 ch = serial_in(up, UART_RX);
7500b1f6
AR		 1353 else
1354 /*
1355 * Intel 82571 has a Serial Over Lan device that will
1356 * set UART_LSR_BI without setting UART_LSR_DR when
1357 * it receives a break. To avoid reading from the
1358 * receive buffer without UART_LSR_DR bit set, we
1359 * just force the read character to be 0
1360 */
1361 ch = 0;
1362
1da177e4 1363 flag = TTY_NORMAL;
dfe42443 1364 port->icount.rx++;
1da177e4 1365
ad4c2aa6
CM		 1366 lsr |= up->lsr_saved_flags;
1367 up->lsr_saved_flags = 0;
1da177e4 1368
ad4c2aa6 1369 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1370 if (lsr & UART_LSR_BI) {
1371 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
dfe42443 1372 port->icount.brk++;
1da177e4
LT		 1373 /*
1374 * We do the SysRQ and SAK checking
1375 * here because otherwise the break
1376 * may get masked by ignore_status_mask
1377 * or read_status_mask.
1378 */
dfe42443 1379 if (uart_handle_break(port))
1da177e4
LT		 1380 goto ignore_char;
1381 } else if (lsr & UART_LSR_PE)
dfe42443 1382 port->icount.parity++;
1da177e4 1383 else if (lsr & UART_LSR_FE)
dfe42443 1384 port->icount.frame++;
1da177e4 1385 if (lsr & UART_LSR_OE)
dfe42443 1386 port->icount.overrun++;
1da177e4
LT		 1387
1388 /*
23907eb8 1389 * Mask off conditions which should be ignored.
1da177e4 1390 */
dfe42443 1391 lsr &= port->read_status_mask;
1da177e4
LT		 1392
1393 if (lsr & UART_LSR_BI) {
1394 DEBUG_INTR("handling break....");
1395 flag = TTY_BREAK;
1396 } else if (lsr & UART_LSR_PE)
1397 flag = TTY_PARITY;
1398 else if (lsr & UART_LSR_FE)
1399 flag = TTY_FRAME;
1400 }
dfe42443 1401 if (uart_handle_sysrq_char(port, ch))
1da177e4 1402 goto ignore_char;
05ab3014 1403
dfe42443 1404 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
05ab3014 1405
6f803cd0 1406ignore_char:
0acf519f 1407 lsr = serial_in(up, UART_LSR);
7500b1f6 1408 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
dfe42443 1409 spin_unlock(&port->lock);
1da177e4 1410 tty_flip_buffer_push(tty);
dfe42443 1411 spin_lock(&port->lock);
0690f41f 1412 return lsr;
1da177e4 1413}
3986fb2b 1414EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1da177e4 1415
3986fb2b 1416void serial8250_tx_chars(struct uart_8250_port *up)
1da177e4 1417{
dfe42443
PG		 1418 struct uart_port *port = &up->port;
1419 struct circ_buf *xmit = &port->state->xmit;
1da177e4
LT		 1420 int count;
1421
dfe42443
PG		 1422 if (port->x_char) {
1423 serial_out(up, UART_TX, port->x_char);
1424 port->icount.tx++;
1425 port->x_char = 0;
1da177e4
LT		 1426 return;
1427 }
dfe42443
PG		 1428 if (uart_tx_stopped(port)) {
1429 serial8250_stop_tx(port);
b129a8cc
RK		 1430 return;
1431 }
1432 if (uart_circ_empty(xmit)) {
e763b90c 1433 __stop_tx(up);
1da177e4
LT		 1434 return;
1435 }
1436
1437 count = up->tx_loadsz;
1438 do {
1439 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1440 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
dfe42443 1441 port->icount.tx++;
1da177e4
LT		 1442 if (uart_circ_empty(xmit))
1443 break;
1444 } while (--count > 0);
1445
1446 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
dfe42443 1447 uart_write_wakeup(port);
1da177e4
LT		 1448
1449 DEBUG_INTR("THRE...");
1450
1451 if (uart_circ_empty(xmit))
e763b90c 1452 __stop_tx(up);
1da177e4 1453}
3986fb2b 1454EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1da177e4 1455
3986fb2b 1456unsigned int serial8250_modem_status(struct uart_8250_port *up)
1da177e4 1457{
dfe42443 1458 struct uart_port *port = &up->port;
2af7cd68
RK		 1459 unsigned int status = serial_in(up, UART_MSR);
1460
ad4c2aa6
CM		 1461 status |= up->msr_saved_flags;
1462 up->msr_saved_flags = 0;
fdc30b3d 1463 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
dfe42443 1464 port->state != NULL) {
2af7cd68 1465 if (status & UART_MSR_TERI)
dfe42443 1466 port->icount.rng++;
2af7cd68 1467 if (status & UART_MSR_DDSR)
dfe42443 1468 port->icount.dsr++;
2af7cd68 1469 if (status & UART_MSR_DDCD)
dfe42443 1470 uart_handle_dcd_change(port, status & UART_MSR_DCD);
2af7cd68 1471 if (status & UART_MSR_DCTS)
dfe42443 1472 uart_handle_cts_change(port, status & UART_MSR_CTS);
2af7cd68 1473
dfe42443 1474 wake_up_interruptible(&port->state->port.delta_msr_wait);
2af7cd68 1475 }
1da177e4 1476
2af7cd68 1477 return status;
1da177e4 1478}
3986fb2b 1479EXPORT_SYMBOL_GPL(serial8250_modem_status);
1da177e4
LT		 1480
1481/*
1482 * This handles the interrupt from one port.
1483 */
86b21199 1484int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1da177e4 1485{
0690f41f 1486 unsigned char status;
4bf3631c 1487 unsigned long flags;
86b21199
PG		 1488 struct uart_8250_port *up =
1489 container_of(port, struct uart_8250_port, port);
1490
1491 if (iir & UART_IIR_NO_INT)
1492 return 0;
45e24601 1493
dfe42443 1494 spin_lock_irqsave(&port->lock, flags);
45e24601 1495
4fd996a1 1496 status = serial_port_in(port, UART_LSR);
1da177e4
LT		 1497
1498 DEBUG_INTR("status = %x...", status);
1499
7500b1f6 1500 if (status & (UART_LSR_DR | UART_LSR_BI))
3986fb2b
PG		 1501 status = serial8250_rx_chars(up, status);
1502 serial8250_modem_status(up);
1da177e4 1503 if (status & UART_LSR_THRE)
3986fb2b 1504 serial8250_tx_chars(up);
45e24601 1505
dfe42443 1506 spin_unlock_irqrestore(&port->lock, flags);
86b21199 1507 return 1;
583d28e9 1508}
c7a1bdc5 1509EXPORT_SYMBOL_GPL(serial8250_handle_irq);
583d28e9
JI		 1510
1511static int serial8250_default_handle_irq(struct uart_port *port)
1512{
4fd996a1 1513 unsigned int iir = serial_port_in(port, UART_IIR);
583d28e9
JI		 1514
1515 return serial8250_handle_irq(port, iir);
1516}
1517
1da177e4
LT		 1518/*
1519 * This is the serial driver's interrupt routine.
1520 *
1521 * Arjan thinks the old way was overly complex, so it got simplified.
1522 * Alan disagrees, saying that need the complexity to handle the weird
1523 * nature of ISA shared interrupts. (This is a special exception.)
1524 *
1525 * In order to handle ISA shared interrupts properly, we need to check
1526 * that all ports have been serviced, and therefore the ISA interrupt
1527 * line has been de-asserted.
1528 *
1529 * This means we need to loop through all ports. checking that they
1530 * don't have an interrupt pending.
1531 */
7d12e780 1532static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1533{
1534 struct irq_info *i = dev_id;
1535 struct list_head *l, *end = NULL;
1536 int pass_counter = 0, handled = 0;
1537
1538 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1539
1540 spin_lock(&i->lock);
1541
1542 l = i->head;
1543 do {
1544 struct uart_8250_port *up;
583d28e9 1545 struct uart_port *port;
1da177e4
LT		 1546
1547 up = list_entry(l, struct uart_8250_port, list);
583d28e9 1548 port = &up->port;
1da177e4 1549
49b532f9 1550 if (port->handle_irq(port)) {
1da177e4 1551 handled = 1;
1da177e4
LT		 1552 end = NULL;
1553 } else if (end == NULL)
1554 end = l;
1555
1556 l = l->next;
1557
1558 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1559 /* If we hit this, we're dead. */
cd3ecad1
DD		 1560 printk_ratelimited(KERN_ERR
1561 "serial8250: too much work for irq%d\n", irq);
1da177e4
LT		 1562 break;
1563 }
1564 } while (l != end);
1565
1566 spin_unlock(&i->lock);
1567
1568 DEBUG_INTR("end.\n");
1569
1570 return IRQ_RETVAL(handled);
1571}
1572
1573/*
1574 * To support ISA shared interrupts, we need to have one interrupt
1575 * handler that ensures that the IRQ line has been deasserted
1576 * before returning. Failing to do this will result in the IRQ
1577 * line being stuck active, and, since ISA irqs are edge triggered,
1578 * no more IRQs will be seen.
1579 */
1580static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1581{
1582 spin_lock_irq(&i->lock);
1583
1584 if (!list_empty(i->head)) {
1585 if (i->head == &up->list)
1586 i->head = i->head->next;
1587 list_del(&up->list);
1588 } else {
1589 BUG_ON(i->head != &up->list);
1590 i->head = NULL;
1591 }
1da177e4 1592 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1593 /* List empty so throw away the hash node */
1594 if (i->head == NULL) {
1595 hlist_del(&i->node);
1596 kfree(i);
1597 }
1da177e4
LT		 1598}
1599
1600static int serial_link_irq_chain(struct uart_8250_port *up)
1601{
25db8ad5
AC		 1602 struct hlist_head *h;
1603 struct hlist_node *n;
1604 struct irq_info *i;
40663cc7 1605 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1606
25db8ad5
AC		 1607 mutex_lock(&hash_mutex);
1608
1609 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1610
1611 hlist_for_each(n, h) {
1612 i = hlist_entry(n, struct irq_info, node);
1613 if (i->irq == up->port.irq)
1614 break;
1615 }
1616
1617 if (n == NULL) {
1618 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1619 if (i == NULL) {
1620 mutex_unlock(&hash_mutex);
1621 return -ENOMEM;
1622 }
1623 spin_lock_init(&i->lock);
1624 i->irq = up->port.irq;
1625 hlist_add_head(&i->node, h);
1626 }
1627 mutex_unlock(&hash_mutex);
1628
1da177e4
LT		 1629 spin_lock_irq(&i->lock);
1630
1631 if (i->head) {
1632 list_add(&up->list, i->head);
1633 spin_unlock_irq(&i->lock);
1634
1635 ret = 0;
1636 } else {
1637 INIT_LIST_HEAD(&up->list);
1638 i->head = &up->list;
1639 spin_unlock_irq(&i->lock);
1c2f0493 1640 irq_flags |= up->port.irqflags;
1da177e4
LT		 1641 ret = request_irq(up->port.irq, serial8250_interrupt,
1642 irq_flags, "serial", i);
1643 if (ret < 0)
1644 serial_do_unlink(i, up);
1645 }
1646
1647 return ret;
1648}
1649
1650static void serial_unlink_irq_chain(struct uart_8250_port *up)
1651{
25db8ad5
AC		 1652 struct irq_info *i;
1653 struct hlist_node *n;
1654 struct hlist_head *h;
1da177e4 1655
25db8ad5
AC		 1656 mutex_lock(&hash_mutex);
1657
1658 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1659
1660 hlist_for_each(n, h) {
1661 i = hlist_entry(n, struct irq_info, node);
1662 if (i->irq == up->port.irq)
1663 break;
1664 }
1665
1666 BUG_ON(n == NULL);
1da177e4
LT		 1667 BUG_ON(i->head == NULL);
1668
1669 if (list_empty(i->head))
1670 free_irq(up->port.irq, i);
1671
1672 serial_do_unlink(i, up);
25db8ad5 1673 mutex_unlock(&hash_mutex);
1da177e4
LT		 1674}
1675
1676/*
1677 * This function is used to handle ports that do not have an
1678 * interrupt. This doesn't work very well for 16450's, but gives
1679 * barely passable results for a 16550A. (Although at the expense
1680 * of much CPU overhead).
1681 */
1682static void serial8250_timeout(unsigned long data)
1683{
1684 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4 1685
a0431476 1686 up->port.handle_irq(&up->port);
54381067 1687 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
40b36daa
AW		 1688}
1689
1690static void serial8250_backup_timeout(unsigned long data)
1691{
1692 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1693 unsigned int iir, ier = 0, lsr;
1694 unsigned long flags;
40b36daa 1695
dbb3b1ca
AC		 1696 spin_lock_irqsave(&up->port.lock, flags);
1697
40b36daa
AW		 1698 /*
1699 * Must disable interrupts or else we risk racing with the interrupt
1700 * based handler.
1701 */
d4e33fac 1702 if (up->port.irq) {
40b36daa
AW		 1703 ier = serial_in(up, UART_IER);
1704 serial_out(up, UART_IER, 0);
1705 }
1da177e4 1706
40b36daa
AW		 1707 iir = serial_in(up, UART_IIR);
1708
1709 /*
1710 * This should be a safe test for anyone who doesn't trust the
1711 * IIR bits on their UART, but it's specifically designed for
1712 * the "Diva" UART used on the management processor on many HP
1713 * ia64 and parisc boxes.
1714 */
ad4c2aa6
CM		 1715 lsr = serial_in(up, UART_LSR);
1716 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
40b36daa 1717 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1718 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1719 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1720 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1721 iir |= UART_IIR_THRI;
1722 }
1723
1724 if (!(iir & UART_IIR_NO_INT))
3986fb2b 1725 serial8250_tx_chars(up);
40b36daa 1726
d4e33fac 1727 if (up->port.irq)
40b36daa
AW		 1728 serial_out(up, UART_IER, ier);
1729
dbb3b1ca
AC		 1730 spin_unlock_irqrestore(&up->port.lock, flags);
1731
40b36daa 1732 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0 1733 mod_timer(&up->timer,
54381067 1734 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1da177e4
LT		 1735}
1736
1737static unsigned int serial8250_tx_empty(struct uart_port *port)
1738{
49d5741b
JI		 1739 struct uart_8250_port *up =
1740 container_of(port, struct uart_8250_port, port);
1da177e4 1741 unsigned long flags;
ad4c2aa6 1742 unsigned int lsr;
1da177e4 1743
dfe42443 1744 spin_lock_irqsave(&port->lock, flags);
4fd996a1 1745 lsr = serial_port_in(port, UART_LSR);
ad4c2aa6 1746 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
dfe42443 1747 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 1748
bca47613 1749 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1750}
1751
1752static unsigned int serial8250_get_mctrl(struct uart_port *port)
1753{
49d5741b
JI		 1754 struct uart_8250_port *up =
1755 container_of(port, struct uart_8250_port, port);
2af7cd68 1756 unsigned int status;
1da177e4
LT		 1757 unsigned int ret;
1758
3986fb2b 1759 status = serial8250_modem_status(up);
1da177e4
LT		 1760
1761 ret = 0;
1762 if (status & UART_MSR_DCD)
1763 ret |= TIOCM_CAR;
1764 if (status & UART_MSR_RI)
1765 ret |= TIOCM_RNG;
1766 if (status & UART_MSR_DSR)
1767 ret |= TIOCM_DSR;
1768 if (status & UART_MSR_CTS)
1769 ret |= TIOCM_CTS;
1770 return ret;
1771}
1772
1773static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1774{
49d5741b
JI		 1775 struct uart_8250_port *up =
1776 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1777 unsigned char mcr = 0;
1778
1779 if (mctrl & TIOCM_RTS)
1780 mcr |= UART_MCR_RTS;
1781 if (mctrl & TIOCM_DTR)
1782 mcr |= UART_MCR_DTR;
1783 if (mctrl & TIOCM_OUT1)
1784 mcr |= UART_MCR_OUT1;
1785 if (mctrl & TIOCM_OUT2)
1786 mcr |= UART_MCR_OUT2;
1787 if (mctrl & TIOCM_LOOP)
1788 mcr |= UART_MCR_LOOP;
1789
1790 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1791
4fd996a1 1792 serial_port_out(port, UART_MCR, mcr);
1da177e4
LT		 1793}
1794
1795static void serial8250_break_ctl(struct uart_port *port, int break_state)
1796{
49d5741b
JI		 1797 struct uart_8250_port *up =
1798 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1799 unsigned long flags;
1800
dfe42443 1801 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 1802 if (break_state == -1)
1803 up->lcr |= UART_LCR_SBC;
1804 else
1805 up->lcr &= ~UART_LCR_SBC;
4fd996a1 1806 serial_port_out(port, UART_LCR, up->lcr);
dfe42443 1807 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1808}
1809
40b36daa
AW		 1810/*
1811 * Wait for transmitter & holding register to empty
1812 */
b5d674ab 1813static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1814{
1815 unsigned int status, tmout = 10000;
1816
1817 /* Wait up to 10ms for the character(s) to be sent. */
97d303b7 1818 for (;;) {
40b36daa
AW		 1819 status = serial_in(up, UART_LSR);
1820
ad4c2aa6 1821 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa 1822
97d303b7
DD		 1823 if ((status & bits) == bits)
1824 break;
40b36daa
AW		 1825 if (--tmout == 0)
1826 break;
1827 udelay(1);
97d303b7 1828 }
40b36daa
AW		 1829
1830 /* Wait up to 1s for flow control if necessary */
1831 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1832 unsigned int tmout;
1833 for (tmout = 1000000; tmout; tmout--) {
1834 unsigned int msr = serial_in(up, UART_MSR);
1835 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1836 if (msr & UART_MSR_CTS)
1837 break;
40b36daa
AW		 1838 udelay(1);
1839 touch_nmi_watchdog();
1840 }
1841 }
1842}
1843
f2d937f3
JW		 1844#ifdef CONFIG_CONSOLE_POLL
1845/*
1846 * Console polling routines for writing and reading from the uart while
1847 * in an interrupt or debug context.
1848 */
1849
1850static int serial8250_get_poll_char(struct uart_port *port)
1851{
4fd996a1 1852 unsigned char lsr = serial_port_in(port, UART_LSR);
f2d937f3 1853
f5316b4a
JW		 1854 if (!(lsr & UART_LSR_DR))
1855 return NO_POLL_CHAR;
f2d937f3 1856
4fd996a1 1857 return serial_port_in(port, UART_RX);
f2d937f3
JW		 1858}
1859
1860
1861static void serial8250_put_poll_char(struct uart_port *port,
1862 unsigned char c)
1863{
1864 unsigned int ier;
49d5741b
JI		 1865 struct uart_8250_port *up =
1866 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1867
1868 /*
1869 * First save the IER then disable the interrupts
1870 */
4fd996a1 1871 ier = serial_port_in(port, UART_IER);
f2d937f3 1872 if (up->capabilities & UART_CAP_UUE)
4fd996a1 1873 serial_port_out(port, UART_IER, UART_IER_UUE);
f2d937f3 1874 else
4fd996a1 1875 serial_port_out(port, UART_IER, 0);
f2d937f3
JW		 1876
1877 wait_for_xmitr(up, BOTH_EMPTY);
1878 /*
1879 * Send the character out.
1880 * If a LF, also do CR...
1881 */
4fd996a1 1882 serial_port_out(port, UART_TX, c);
f2d937f3
JW		 1883 if (c == 10) {
1884 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 1885 serial_port_out(port, UART_TX, 13);
f2d937f3
JW		 1886 }
1887
1888 /*
1889 * Finally, wait for transmitter to become empty
1890 * and restore the IER
1891 */
1892 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 1893 serial_port_out(port, UART_IER, ier);
f2d937f3
JW		 1894}
1895
1896#endif /* CONFIG_CONSOLE_POLL */
1897
1da177e4
LT		 1898static int serial8250_startup(struct uart_port *port)
1899{
49d5741b
JI		 1900 struct uart_8250_port *up =
1901 container_of(port, struct uart_8250_port, port);
1da177e4 1902 unsigned long flags;
55d3b282 1903 unsigned char lsr, iir;
1da177e4
LT		 1904 int retval;
1905
65ecc9c0
SY		 1906 if (port->type == PORT_8250_CIR)
1907 return -ENODEV;
1908
dfe42443 1909 port->fifosize = uart_config[up->port.type].fifo_size;
e4f05af1 1910 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1da177e4
LT		 1911 up->capabilities = uart_config[up->port.type].flags;
1912 up->mcr = 0;
1913
dfe42443 1914 if (port->iotype != up->cur_iotype)
b8e7e40a
AC		 1915 set_io_from_upio(port);
1916
dfe42443 1917 if (port->type == PORT_16C950) {
1da177e4
LT		 1918 /* Wake up and initialize UART */
1919 up->acr = 0;
4fd996a1
PG		 1920 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1921 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1922 serial_port_out(port, UART_IER, 0);
1923 serial_port_out(port, UART_LCR, 0);
1da177e4 1924 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
4fd996a1
PG		 1925 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1926 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1927 serial_port_out(port, UART_LCR, 0);
1da177e4
LT		 1928 }
1929
1930#ifdef CONFIG_SERIAL_8250_RSA
1931 /*
1932 * If this is an RSA port, see if we can kick it up to the
1933 * higher speed clock.
1934 */
1935 enable_rsa(up);
1936#endif
1937
1938 /*
1939 * Clear the FIFO buffers and disable them.
7f927fcc 1940 * (they will be reenabled in set_termios())
1da177e4
LT		 1941 */
1942 serial8250_clear_fifos(up);
1943
1944 /*
1945 * Clear the interrupt registers.
1946 */
4fd996a1
PG		 1947 serial_port_in(port, UART_LSR);
1948 serial_port_in(port, UART_RX);
1949 serial_port_in(port, UART_IIR);
1950 serial_port_in(port, UART_MSR);
1da177e4
LT		 1951
1952 /*
1953 * At this point, there's no way the LSR could still be 0xff;
1954 * if it is, then bail out, because there's likely no UART
1955 * here.
1956 */
dfe42443 1957 if (!(port->flags & UPF_BUGGY_UART) &&
4fd996a1 1958 (serial_port_in(port, UART_LSR) == 0xff)) {
7808a4c4 1959 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
dfe42443 1960 serial_index(port));
1da177e4
LT		 1961 return -ENODEV;
1962 }
1963
1964 /*
1965 * For a XR16C850, we need to set the trigger levels
1966 */
dfe42443 1967 if (port->type == PORT_16850) {
1da177e4
LT		 1968 unsigned char fctr;
1969
0acf519f 1970 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4 1971
0acf519f 1972 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
4fd996a1
PG		 1973 serial_port_out(port, UART_FCTR,
1974 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1975 serial_port_out(port, UART_TRG, UART_TRG_96);
1976 serial_port_out(port, UART_FCTR,
1977 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1978 serial_port_out(port, UART_TRG, UART_TRG_96);
1da177e4 1979
4fd996a1 1980 serial_port_out(port, UART_LCR, 0);
1da177e4
LT		 1981 }
1982
dfe42443 1983 if (port->irq) {
01c194d9 1984 unsigned char iir1;
40b36daa
AW		 1985 /*
1986 * Test for UARTs that do not reassert THRE when the
1987 * transmitter is idle and the interrupt has already
1988 * been cleared. Real 16550s should always reassert
1989 * this interrupt whenever the transmitter is idle and
1990 * the interrupt is enabled. Delays are necessary to
1991 * allow register changes to become visible.
1992 */
dfe42443 1993 spin_lock_irqsave(&port->lock, flags);
1c2f0493 1994 if (up->port.irqflags & IRQF_SHARED)
dfe42443 1995 disable_irq_nosync(port->irq);
40b36daa
AW		 1996
1997 wait_for_xmitr(up, UART_LSR_THRE);
55e4016d 1998 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
40b36daa 1999 udelay(1); /* allow THRE to set */
4fd996a1
PG		 2000 iir1 = serial_port_in(port, UART_IIR);
2001 serial_port_out(port, UART_IER, 0);
55e4016d 2002 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
40b36daa 2003 udelay(1); /* allow a working UART time to re-assert THRE */
4fd996a1
PG		 2004 iir = serial_port_in(port, UART_IIR);
2005 serial_port_out(port, UART_IER, 0);
40b36daa 2006
dfe42443
PG		 2007 if (port->irqflags & IRQF_SHARED)
2008 enable_irq(port->irq);
2009 spin_unlock_irqrestore(&port->lock, flags);
40b36daa
AW		 2010
2011 /*
bc02d15a
DW		 2012 * If the interrupt is not reasserted, or we otherwise
2013 * don't trust the iir, setup a timer to kick the UART
2014 * on a regular basis.
40b36daa 2015 */
bc02d15a
DW		 2016 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2017 up->port.flags & UPF_BUG_THRE) {
363f66fe 2018 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2019 pr_debug("ttyS%d - using backup timer\n",
2020 serial_index(port));
40b36daa
AW		 2021 }
2022 }
2023
363f66fe
WN		 2024 /*
2025 * The above check will only give an accurate result the first time
2026 * the port is opened so this value needs to be preserved.
2027 */
2028 if (up->bugs & UART_BUG_THRE) {
2029 up->timer.function = serial8250_backup_timeout;
2030 up->timer.data = (unsigned long)up;
2031 mod_timer(&up->timer, jiffies +
54381067 2032 uart_poll_timeout(port) + HZ / 5);
363f66fe
WN		 2033 }
2034
1da177e4
LT		 2035 /*
2036 * If the "interrupt" for this port doesn't correspond with any
2037 * hardware interrupt, we use a timer-based system. The original
2038 * driver used to do this with IRQ0.
2039 */
dfe42443 2040 if (!port->irq) {
1da177e4 2041 up->timer.data = (unsigned long)up;
54381067 2042 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
1da177e4
LT		 2043 } else {
2044 retval = serial_link_irq_chain(up);
2045 if (retval)
2046 return retval;
2047 }
2048
2049 /*
2050 * Now, initialize the UART
2051 */
4fd996a1 2052 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
1da177e4 2053
dfe42443 2054 spin_lock_irqsave(&port->lock, flags);
1da177e4 2055 if (up->port.flags & UPF_FOURPORT) {
d4e33fac 2056 if (!up->port.irq)
1da177e4
LT		 2057 up->port.mctrl |= TIOCM_OUT1;
2058 } else
2059 /*
2060 * Most PC uarts need OUT2 raised to enable interrupts.
2061 */
dfe42443 2062 if (port->irq)
1da177e4
LT		 2063 up->port.mctrl |= TIOCM_OUT2;
2064
dfe42443 2065 serial8250_set_mctrl(port, port->mctrl);
55d3b282 2066
b6adea33
MCC		 2067 /* Serial over Lan (SoL) hack:
2068 Intel 8257x Gigabit ethernet chips have a
2069 16550 emulation, to be used for Serial Over Lan.
2070 Those chips take a longer time than a normal
2071 serial device to signalize that a transmission
2072 data was queued. Due to that, the above test generally
2073 fails. One solution would be to delay the reading of
2074 iir. However, this is not reliable, since the timeout
2075 is variable. So, let's just don't test if we receive
2076 TX irq. This way, we'll never enable UART_BUG_TXEN.
2077 */
d41a4b51 2078 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2079 goto dont_test_tx_en;
2080
55d3b282
RK		 2081 /*
2082 * Do a quick test to see if we receive an
2083 * interrupt when we enable the TX irq.
2084 */
4fd996a1
PG		 2085 serial_port_out(port, UART_IER, UART_IER_THRI);
2086 lsr = serial_port_in(port, UART_LSR);
2087 iir = serial_port_in(port, UART_IIR);
2088 serial_port_out(port, UART_IER, 0);
55d3b282
RK		 2089
2090 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2091 if (!(up->bugs & UART_BUG_TXEN)) {
2092 up->bugs |= UART_BUG_TXEN;
55d3b282 2093 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2094 serial_index(port));
55d3b282
RK		 2095 }
2096 } else {
67f7654e 2097 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2098 }
2099
b6adea33 2100dont_test_tx_en:
dfe42443 2101 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 2102
ad4c2aa6
CM		 2103 /*
2104 * Clear the interrupt registers again for luck, and clear the
2105 * saved flags to avoid getting false values from polling
2106 * routines or the previous session.
2107 */
4fd996a1
PG		 2108 serial_port_in(port, UART_LSR);
2109 serial_port_in(port, UART_RX);
2110 serial_port_in(port, UART_IIR);
2111 serial_port_in(port, UART_MSR);
ad4c2aa6
CM		 2112 up->lsr_saved_flags = 0;
2113 up->msr_saved_flags = 0;
2114
1da177e4
LT		 2115 /*
2116 * Finally, enable interrupts. Note: Modem status interrupts
2117 * are set via set_termios(), which will be occurring imminently
2118 * anyway, so we don't enable them here.
2119 */
2120 up->ier = UART_IER_RLSI | UART_IER_RDI;
4fd996a1 2121 serial_port_out(port, UART_IER, up->ier);
1da177e4 2122
dfe42443 2123 if (port->flags & UPF_FOURPORT) {
1da177e4
LT		 2124 unsigned int icp;
2125 /*
2126 * Enable interrupts on the AST Fourport board
2127 */
dfe42443 2128 icp = (port->iobase & 0xfe0) | 0x01f;
1da177e4 2129 outb_p(0x80, icp);
0d263a26 2130 inb_p(icp);
1da177e4
LT		 2131 }
2132
1da177e4
LT		 2133 return 0;
2134}
2135
2136static void serial8250_shutdown(struct uart_port *port)
2137{
49d5741b
JI		 2138 struct uart_8250_port *up =
2139 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2140 unsigned long flags;
2141
2142 /*
2143 * Disable interrupts from this port
2144 */
2145 up->ier = 0;
4fd996a1 2146 serial_port_out(port, UART_IER, 0);
1da177e4 2147
dfe42443
PG		 2148 spin_lock_irqsave(&port->lock, flags);
2149 if (port->flags & UPF_FOURPORT) {
1da177e4 2150 /* reset interrupts on the AST Fourport board */
dfe42443
PG		 2151 inb((port->iobase & 0xfe0) | 0x1f);
2152 port->mctrl |= TIOCM_OUT1;
1da177e4 2153 } else
dfe42443 2154 port->mctrl &= ~TIOCM_OUT2;
1da177e4 2155
dfe42443
PG		 2156 serial8250_set_mctrl(port, port->mctrl);
2157 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 2158
2159 /*
2160 * Disable break condition and FIFOs
2161 */
4fd996a1
PG		 2162 serial_port_out(port, UART_LCR,
2163 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
1da177e4
LT		 2164 serial8250_clear_fifos(up);
2165
2166#ifdef CONFIG_SERIAL_8250_RSA
2167 /*
2168 * Reset the RSA board back to 115kbps compat mode.
2169 */
2170 disable_rsa(up);
2171#endif
2172
2173 /*
2174 * Read data port to reset things, and then unlink from
2175 * the IRQ chain.
2176 */
4fd996a1 2177 serial_port_in(port, UART_RX);
1da177e4 2178
40b36daa
AW		 2179 del_timer_sync(&up->timer);
2180 up->timer.function = serial8250_timeout;
dfe42443 2181 if (port->irq)
1da177e4
LT		 2182 serial_unlink_irq_chain(up);
2183}
2184
2185static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2186{
2187 unsigned int quot;
2188
2189 /*
2190 * Handle magic divisors for baud rates above baud_base on
2191 * SMSC SuperIO chips.
2192 */
2193 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2194 baud == (port->uartclk/4))
2195 quot = 0x8001;
2196 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2197 baud == (port->uartclk/8))
2198 quot = 0x8002;
2199 else
2200 quot = uart_get_divisor(port, baud);
2201
2202 return quot;
2203}
2204
235dae5d
PL		 2205void
2206serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2207 struct ktermios *old)
1da177e4 2208{
49d5741b
JI		 2209 struct uart_8250_port *up =
2210 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2211 unsigned char cval, fcr = 0;
2212 unsigned long flags;
2213 unsigned int baud, quot;
eb26dfe8 2214 int fifo_bug = 0;
1da177e4
LT		 2215
2216 switch (termios->c_cflag & CSIZE) {
2217 case CS5:
0a8b80c5 2218 cval = UART_LCR_WLEN5;
1da177e4
LT		 2219 break;
2220 case CS6:
0a8b80c5 2221 cval = UART_LCR_WLEN6;
1da177e4
LT		 2222 break;
2223 case CS7:
0a8b80c5 2224 cval = UART_LCR_WLEN7;
1da177e4
LT		 2225 break;
2226 default:
2227 case CS8:
0a8b80c5 2228 cval = UART_LCR_WLEN8;
1da177e4
LT		 2229 break;
2230 }
2231
2232 if (termios->c_cflag & CSTOPB)
0a8b80c5 2233 cval |= UART_LCR_STOP;
eb26dfe8 2234 if (termios->c_cflag & PARENB) {
1da177e4 2235 cval |= UART_LCR_PARITY;
eb26dfe8
AC		 2236 if (up->bugs & UART_BUG_PARITY)
2237 fifo_bug = 1;
2238 }
1da177e4
LT		 2239 if (!(termios->c_cflag & PARODD))
2240 cval |= UART_LCR_EPAR;
2241#ifdef CMSPAR
2242 if (termios->c_cflag & CMSPAR)
2243 cval |= UART_LCR_SPAR;
2244#endif
2245
2246 /*
2247 * Ask the core to calculate the divisor for us.
2248 */
24d481ec
AV		 2249 baud = uart_get_baud_rate(port, termios, old,
2250 port->uartclk / 16 / 0xffff,
2251 port->uartclk / 16);
1da177e4
LT		 2252 quot = serial8250_get_divisor(port, baud);
2253
2254 /*
4ba5e35d 2255 * Oxford Semi 952 rev B workaround
1da177e4 2256 */
4ba5e35d 2257 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2258 quot++;
1da177e4 2259
dfe42443 2260 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
f9a9111b 2261 fcr = uart_config[port->type].fcr;
eb26dfe8 2262 if (baud < 2400 || fifo_bug) {
f9a9111b
CM		 2263 fcr &= ~UART_FCR_TRIGGER_MASK;
2264 fcr |= UART_FCR_TRIGGER_1;
2265 }
1da177e4
LT		 2266 }
2267
2268 /*
2269 * MCR-based auto flow control. When AFE is enabled, RTS will be
2270 * deasserted when the receive FIFO contains more characters than
2271 * the trigger, or the MCR RTS bit is cleared. In the case where
2272 * the remote UART is not using CTS auto flow control, we must
2273 * have sufficient FIFO entries for the latency of the remote
2274 * UART to respond. IOW, at least 32 bytes of FIFO.
2275 */
dfe42443 2276 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
1da177e4
LT		 2277 up->mcr &= ~UART_MCR_AFE;
2278 if (termios->c_cflag & CRTSCTS)
2279 up->mcr |= UART_MCR_AFE;
2280 }
2281
2282 /*
2283 * Ok, we're now changing the port state. Do it with
2284 * interrupts disabled.
2285 */
dfe42443 2286 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 2287
2288 /*
2289 * Update the per-port timeout.
2290 */
2291 uart_update_timeout(port, termios->c_cflag, baud);
2292
dfe42443 2293 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1da177e4 2294 if (termios->c_iflag & INPCK)
dfe42443 2295 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1da177e4 2296 if (termios->c_iflag & (BRKINT | PARMRK))
dfe42443 2297 port->read_status_mask |= UART_LSR_BI;
1da177e4
LT		 2298
2299 /*
2300 * Characteres to ignore
2301 */
dfe42443 2302 port->ignore_status_mask = 0;
1da177e4 2303 if (termios->c_iflag & IGNPAR)
dfe42443 2304 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1da177e4 2305 if (termios->c_iflag & IGNBRK) {
dfe42443 2306 port->ignore_status_mask |= UART_LSR_BI;
1da177e4
LT		 2307 /*
2308 * If we're ignoring parity and break indicators,
2309 * ignore overruns too (for real raw support).
2310 */
2311 if (termios->c_iflag & IGNPAR)
dfe42443 2312 port->ignore_status_mask |= UART_LSR_OE;
1da177e4
LT		 2313 }
2314
2315 /*
2316 * ignore all characters if CREAD is not set
2317 */
2318 if ((termios->c_cflag & CREAD) == 0)
dfe42443 2319 port->ignore_status_mask |= UART_LSR_DR;
1da177e4
LT		 2320
2321 /*
2322 * CTS flow control flag and modem status interrupts
2323 */
f8b372a1 2324 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2325 if (!(up->bugs & UART_BUG_NOMSR) &&
2326 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2327 up->ier |= UART_IER_MSI;
2328 if (up->capabilities & UART_CAP_UUE)
4539c24f
SW		 2329 up->ier |= UART_IER_UUE;
2330 if (up->capabilities & UART_CAP_RTOIE)
2331 up->ier |= UART_IER_RTOIE;
1da177e4 2332
4fd996a1 2333 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 2334
2335 if (up->capabilities & UART_CAP_EFR) {
2336 unsigned char efr = 0;
2337 /*
2338 * TI16C752/Startech hardware flow control. FIXME:
2339 * - TI16C752 requires control thresholds to be set.
2340 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2341 */
2342 if (termios->c_cflag & CRTSCTS)
2343 efr |= UART_EFR_CTS;
2344
4fd996a1 2345 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
dfe42443 2346 if (port->flags & UPF_EXAR_EFR)
4fd996a1 2347 serial_port_out(port, UART_XR_EFR, efr);
06315348 2348 else
4fd996a1 2349 serial_port_out(port, UART_EFR, efr);
1da177e4
LT		 2350 }
2351
255341c6 2352 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
54ec52b6 2353 if (is_omap1510_8250(up)) {
255341c6
JM		 2354 if (baud == 115200) {
2355 quot = 1;
4fd996a1 2356 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
255341c6 2357 } else
4fd996a1 2358 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
255341c6 2359 }
255341c6 2360
4fd996a1
PG		 2361 /*
2362 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2363 * otherwise just set DLAB
2364 */
2365 if (up->capabilities & UART_NATSEMI)
2366 serial_port_out(port, UART_LCR, 0xe0);
2367 else
2368 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
1da177e4 2369
b32b19b8 2370 serial_dl_write(up, quot);
1da177e4
LT		 2371
2372 /*
2373 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2374 * is written without DLAB set, this mode will be disabled.
2375 */
dfe42443 2376 if (port->type == PORT_16750)
4fd996a1 2377 serial_port_out(port, UART_FCR, fcr);
1da177e4 2378
4fd996a1 2379 serial_port_out(port, UART_LCR, cval); /* reset DLAB */
1da177e4 2380 up->lcr = cval; /* Save LCR */
dfe42443 2381 if (port->type != PORT_16750) {
4fd996a1
PG		 2382 /* emulated UARTs (Lucent Venus 167x) need two steps */
2383 if (fcr & UART_FCR_ENABLE_FIFO)
2384 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2385 serial_port_out(port, UART_FCR, fcr); /* set fcr */
1da177e4 2386 }
dfe42443
PG		 2387 serial8250_set_mctrl(port, port->mctrl);
2388 spin_unlock_irqrestore(&port->lock, flags);
e991a2bd
AC		 2389 /* Don't rewrite B0 */
2390 if (tty_termios_baud_rate(termios))
2391 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4 2392}
235dae5d
PL		 2393EXPORT_SYMBOL(serial8250_do_set_termios);
2394
2395static void
2396serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2397 struct ktermios *old)
2398{
2399 if (port->set_termios)
2400 port->set_termios(port, termios, old);
2401 else
2402 serial8250_do_set_termios(port, termios, old);
2403}
1da177e4 2404
dc77f161 2405static void
a0821df6 2406serial8250_set_ldisc(struct uart_port *port, int new)
dc77f161 2407{
a0821df6 2408 if (new == N_PPS) {
dc77f161
RG		 2409 port->flags |= UPF_HARDPPS_CD;
2410 serial8250_enable_ms(port);
2411 } else
2412 port->flags &= ~UPF_HARDPPS_CD;
2413}
2414
c161afe9
ML		 2415
2416void serial8250_do_pm(struct uart_port *port, unsigned int state,
2417 unsigned int oldstate)
1da177e4 2418{
49d5741b
JI		 2419 struct uart_8250_port *p =
2420 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2421
2422 serial8250_set_sleep(p, state != 0);
c161afe9
ML		 2423}
2424EXPORT_SYMBOL(serial8250_do_pm);
1da177e4 2425
c161afe9
ML		 2426static void
2427serial8250_pm(struct uart_port *port, unsigned int state,
2428 unsigned int oldstate)
2429{
2430 if (port->pm)
2431 port->pm(port, state, oldstate);
2432 else
2433 serial8250_do_pm(port, state, oldstate);
1da177e4
LT		 2434}
2435
f2eda27d
RK		 2436static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2437{
2438 if (pt->port.iotype == UPIO_AU)
b2b13cdf 2439 return 0x1000;
54ec52b6 2440 if (is_omap1_8250(pt))
f2eda27d 2441 return 0x16 << pt->port.regshift;
54ec52b6 2442
f2eda27d
RK		 2443 return 8 << pt->port.regshift;
2444}
2445
1da177e4
LT		 2446/*
2447 * Resource handling.
2448 */
2449static int serial8250_request_std_resource(struct uart_8250_port *up)
2450{
f2eda27d 2451 unsigned int size = serial8250_port_size(up);
dfe42443 2452 struct uart_port *port = &up->port;
1da177e4
LT		 2453 int ret = 0;
2454
dfe42443 2455 switch (port->iotype) {
85835f44 2456 case UPIO_AU:
0b30d668
SS		 2457 case UPIO_TSI:
2458 case UPIO_MEM32:
1da177e4 2459 case UPIO_MEM:
dfe42443 2460 if (!port->mapbase)
1da177e4
LT		 2461 break;
2462
dfe42443 2463 if (!request_mem_region(port->mapbase, size, "serial")) {
1da177e4
LT		 2464 ret = -EBUSY;
2465 break;
2466 }
2467
dfe42443
PG		 2468 if (port->flags & UPF_IOREMAP) {
2469 port->membase = ioremap_nocache(port->mapbase, size);
2470 if (!port->membase) {
2471 release_mem_region(port->mapbase, size);
1da177e4
LT		 2472 ret = -ENOMEM;
2473 }
2474 }
2475 break;
2476
2477 case UPIO_HUB6:
2478 case UPIO_PORT:
dfe42443 2479 if (!request_region(port->iobase, size, "serial"))
1da177e4
LT		 2480 ret = -EBUSY;
2481 break;
2482 }
2483 return ret;
2484}
2485
2486static void serial8250_release_std_resource(struct uart_8250_port *up)
2487{
f2eda27d 2488 unsigned int size = serial8250_port_size(up);
dfe42443 2489 struct uart_port *port = &up->port;
1da177e4 2490
dfe42443 2491 switch (port->iotype) {
85835f44 2492 case UPIO_AU:
0b30d668
SS		 2493 case UPIO_TSI:
2494 case UPIO_MEM32:
1da177e4 2495 case UPIO_MEM:
dfe42443 2496 if (!port->mapbase)
1da177e4
LT		 2497 break;
2498
dfe42443
PG		 2499 if (port->flags & UPF_IOREMAP) {
2500 iounmap(port->membase);
2501 port->membase = NULL;
1da177e4
LT		 2502 }
2503
dfe42443 2504 release_mem_region(port->mapbase, size);
1da177e4
LT		 2505 break;
2506
2507 case UPIO_HUB6:
2508 case UPIO_PORT:
dfe42443 2509 release_region(port->iobase, size);
1da177e4
LT		 2510 break;
2511 }
2512}
2513
2514static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2515{
2516 unsigned long start = UART_RSA_BASE << up->port.regshift;
2517 unsigned int size = 8 << up->port.regshift;
dfe42443 2518 struct uart_port *port = &up->port;
0b30d668 2519 int ret = -EINVAL;
1da177e4 2520
dfe42443 2521 switch (port->iotype) {
1da177e4
LT		 2522 case UPIO_HUB6:
2523 case UPIO_PORT:
dfe42443 2524 start += port->iobase;
0b30d668
SS		 2525 if (request_region(start, size, "serial-rsa"))
2526 ret = 0;
2527 else
1da177e4
LT		 2528 ret = -EBUSY;
2529 break;
2530 }
2531
2532 return ret;
2533}
2534
2535static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2536{
2537 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2538 unsigned int size = 8 << up->port.regshift;
dfe42443 2539 struct uart_port *port = &up->port;
1da177e4 2540
dfe42443 2541 switch (port->iotype) {
1da177e4
LT		 2542 case UPIO_HUB6:
2543 case UPIO_PORT:
dfe42443 2544 release_region(port->iobase + offset, size);
1da177e4
LT		 2545 break;
2546 }
2547}
2548
2549static void serial8250_release_port(struct uart_port *port)
2550{
49d5741b
JI		 2551 struct uart_8250_port *up =
2552 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2553
2554 serial8250_release_std_resource(up);
dfe42443 2555 if (port->type == PORT_RSA)
1da177e4
LT		 2556 serial8250_release_rsa_resource(up);
2557}
2558
2559static int serial8250_request_port(struct uart_port *port)
2560{
49d5741b
JI		 2561 struct uart_8250_port *up =
2562 container_of(port, struct uart_8250_port, port);
65ecc9c0
SY		 2563 int ret;
2564
2565 if (port->type == PORT_8250_CIR)
2566 return -ENODEV;
1da177e4
LT		 2567
2568 ret = serial8250_request_std_resource(up);
dfe42443 2569 if (ret == 0 && port->type == PORT_RSA) {
1da177e4
LT		 2570 ret = serial8250_request_rsa_resource(up);
2571 if (ret < 0)
2572 serial8250_release_std_resource(up);
2573 }
2574
2575 return ret;
2576}
2577
2578static void serial8250_config_port(struct uart_port *port, int flags)
2579{
49d5741b
JI		 2580 struct uart_8250_port *up =
2581 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2582 int probeflags = PROBE_ANY;
2583 int ret;
2584
65ecc9c0
SY		 2585 if (port->type == PORT_8250_CIR)
2586 return;
2587
1da177e4
LT		 2588 /*
2589 * Find the region that we can probe for. This in turn
2590 * tells us whether we can probe for the type of port.
2591 */
2592 ret = serial8250_request_std_resource(up);
2593 if (ret < 0)
2594 return;
2595
2596 ret = serial8250_request_rsa_resource(up);
2597 if (ret < 0)
2598 probeflags &= ~PROBE_RSA;
2599
dfe42443 2600 if (port->iotype != up->cur_iotype)
b8e7e40a
AC		 2601 set_io_from_upio(port);
2602
1da177e4
LT		 2603 if (flags & UART_CONFIG_TYPE)
2604 autoconfig(up, probeflags);
b2b13cdf 2605
b2b13cdf 2606 /* if access method is AU, it is a 16550 with a quirk */
dfe42443 2607 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
b2b13cdf 2608 up->bugs |= UART_BUG_NOMSR;
b2b13cdf 2609
dfe42443 2610 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
1da177e4
LT		 2611 autoconfig_irq(up);
2612
dfe42443 2613 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
1da177e4 2614 serial8250_release_rsa_resource(up);
dfe42443 2615 if (port->type == PORT_UNKNOWN)
1da177e4
LT		 2616 serial8250_release_std_resource(up);
2617}
2618
2619static int
2620serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2621{
a62c4133 2622 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2623 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2624 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2625 ser->type == PORT_STARTECH)
2626 return -EINVAL;
2627 return 0;
2628}
2629
2630static const char *
2631serial8250_type(struct uart_port *port)
2632{
2633 int type = port->type;
2634
2635 if (type >= ARRAY_SIZE(uart_config))
2636 type = 0;
2637 return uart_config[type].name;
2638}
2639
2640static struct uart_ops serial8250_pops = {
2641 .tx_empty = serial8250_tx_empty,
2642 .set_mctrl = serial8250_set_mctrl,
2643 .get_mctrl = serial8250_get_mctrl,
2644 .stop_tx = serial8250_stop_tx,
2645 .start_tx = serial8250_start_tx,
2646 .stop_rx = serial8250_stop_rx,
2647 .enable_ms = serial8250_enable_ms,
2648 .break_ctl = serial8250_break_ctl,
2649 .startup = serial8250_startup,
2650 .shutdown = serial8250_shutdown,
2651 .set_termios = serial8250_set_termios,
dc77f161 2652 .set_ldisc = serial8250_set_ldisc,
1da177e4
LT		 2653 .pm = serial8250_pm,
2654 .type = serial8250_type,
2655 .release_port = serial8250_release_port,
2656 .request_port = serial8250_request_port,
2657 .config_port = serial8250_config_port,
2658 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2659#ifdef CONFIG_CONSOLE_POLL
2660 .poll_get_char = serial8250_get_poll_char,
2661 .poll_put_char = serial8250_put_poll_char,
2662#endif
1da177e4
LT		 2663};
2664
2665static struct uart_8250_port serial8250_ports[UART_NR];
2666
af7f3743
AC		 2667static void (*serial8250_isa_config)(int port, struct uart_port *up,
2668 unsigned short *capabilities);
2669
2670void serial8250_set_isa_configurator(
2671 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2672{
2673 serial8250_isa_config = v;
2674}
2675EXPORT_SYMBOL(serial8250_set_isa_configurator);
2676
1da177e4
LT		 2677static void __init serial8250_isa_init_ports(void)
2678{
2679 struct uart_8250_port *up;
2680 static int first = 1;
4c0ebb80 2681 int i, irqflag = 0;
1da177e4
LT		 2682
2683 if (!first)
2684 return;
2685 first = 0;
2686
835d844d
SY		 2687 if (nr_uarts > UART_NR)
2688 nr_uarts = UART_NR;
2689
a61c2d78 2690 for (i = 0; i < nr_uarts; i++) {
1da177e4 2691 struct uart_8250_port *up = &serial8250_ports[i];
dfe42443 2692 struct uart_port *port = &up->port;
1da177e4 2693
dfe42443
PG		 2694 port->line = i;
2695 spin_lock_init(&port->lock);
1da177e4
LT		 2696
2697 init_timer(&up->timer);
2698 up->timer.function = serial8250_timeout;
835d844d 2699 up->cur_iotype = 0xFF;
1da177e4
LT		 2700
2701 /*
2702 * ALPHA_KLUDGE_MCR needs to be killed.
2703 */
2704 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2705 up->mcr_force = ALPHA_KLUDGE_MCR;
2706
dfe42443 2707 port->ops = &serial8250_pops;
1da177e4
LT		 2708 }
2709
4c0ebb80
AGR		 2710 if (share_irqs)
2711 irqflag = IRQF_SHARED;
2712
44454bcd 2713 for (i = 0, up = serial8250_ports;
a61c2d78 2714 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4 2715 i++, up++) {
dfe42443
PG		 2716 struct uart_port *port = &up->port;
2717
2718 port->iobase = old_serial_port[i].port;
2719 port->irq = irq_canonicalize(old_serial_port[i].irq);
2720 port->irqflags = old_serial_port[i].irqflags;
2721 port->uartclk = old_serial_port[i].baud_base * 16;
2722 port->flags = old_serial_port[i].flags;
2723 port->hub6 = old_serial_port[i].hub6;
2724 port->membase = old_serial_port[i].iomem_base;
2725 port->iotype = old_serial_port[i].io_type;
2726 port->regshift = old_serial_port[i].iomem_reg_shift;
2727 set_io_from_upio(port);
2728 port->irqflags |= irqflag;
af7f3743
AC		 2729 if (serial8250_isa_config != NULL)
2730 serial8250_isa_config(i, &up->port, &up->capabilities);
2731
1da177e4
LT		 2732 }
2733}
2734
b5d228cc
SL		 2735static void
2736serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2737{
2738 up->port.type = type;
2739 up->port.fifosize = uart_config[type].fifo_size;
2740 up->capabilities = uart_config[type].flags;
2741 up->tx_loadsz = uart_config[type].tx_loadsz;
2742}
2743
1da177e4
LT		 2744static void __init
2745serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2746{
2747 int i;
2748
b8e7e40a
AC		 2749 for (i = 0; i < nr_uarts; i++) {
2750 struct uart_8250_port *up = &serial8250_ports[i];
b8e7e40a 2751
835d844d
SY		 2752 if (up->port.dev)
2753 continue;
1da177e4
LT		 2754
2755 up->port.dev = dev;
b5d228cc
SL		 2756
2757 if (up->port.flags & UPF_FIXED_TYPE)
2758 serial8250_init_fixed_type_port(up, up->port.type);
2759
1da177e4
LT		 2760 uart_add_one_port(drv, &up->port);
2761 }
2762}
2763
2764#ifdef CONFIG_SERIAL_8250_CONSOLE
2765
d358788f
RK		 2766static void serial8250_console_putchar(struct uart_port *port, int ch)
2767{
49d5741b
JI		 2768 struct uart_8250_port *up =
2769 container_of(port, struct uart_8250_port, port);
d358788f
RK		 2770
2771 wait_for_xmitr(up, UART_LSR_THRE);
4fd996a1 2772 serial_port_out(port, UART_TX, ch);
d358788f
RK		 2773}
2774
1da177e4
LT		 2775/*
2776 * Print a string to the serial port trying not to disturb
2777 * any possible real use of the port...
2778 *
2779 * The console_lock must be held when we get here.
2780 */
2781static void
2782serial8250_console_write(struct console *co, const char *s, unsigned int count)
2783{
2784 struct uart_8250_port *up = &serial8250_ports[co->index];
dfe42443 2785 struct uart_port *port = &up->port;
d8a5a8d7 2786 unsigned long flags;
1da177e4 2787 unsigned int ier;
d8a5a8d7 2788 int locked = 1;
1da177e4 2789
78512ece
AM		 2790 touch_nmi_watchdog();
2791
68aa2c0d 2792 local_irq_save(flags);
dfe42443 2793 if (port->sysrq) {
86b21199 2794 /* serial8250_handle_irq() already took the lock */
68aa2c0d
AM		 2795 locked = 0;
2796 } else if (oops_in_progress) {
dfe42443 2797 locked = spin_trylock(&port->lock);
d8a5a8d7 2798 } else
dfe42443 2799 spin_lock(&port->lock);
d8a5a8d7 2800
1da177e4 2801 /*
dc7bf130 2802 * First save the IER then disable the interrupts
1da177e4 2803 */
4fd996a1 2804 ier = serial_port_in(port, UART_IER);
1da177e4
LT		 2805
2806 if (up->capabilities & UART_CAP_UUE)
4fd996a1 2807 serial_port_out(port, UART_IER, UART_IER_UUE);
1da177e4 2808 else
4fd996a1 2809 serial_port_out(port, UART_IER, 0);
1da177e4 2810
dfe42443 2811 uart_console_write(port, s, count, serial8250_console_putchar);
1da177e4
LT		 2812
2813 /*
2814 * Finally, wait for transmitter to become empty
2815 * and restore the IER
2816 */
f91a3715 2817 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 2818 serial_port_out(port, UART_IER, ier);
d8a5a8d7 2819
ad4c2aa6
CM		 2820 /*
2821 * The receive handling will happen properly because the
2822 * receive ready bit will still be set; it is not cleared
2823 * on read. However, modem control will not, we must
2824 * call it if we have saved something in the saved flags
2825 * while processing with interrupts off.
2826 */
2827 if (up->msr_saved_flags)
3986fb2b 2828 serial8250_modem_status(up);
ad4c2aa6 2829
d8a5a8d7 2830 if (locked)
dfe42443 2831 spin_unlock(&port->lock);
68aa2c0d 2832 local_irq_restore(flags);
1da177e4
LT		 2833}
2834
118c0ace 2835static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2836{
2837 struct uart_port *port;
2838 int baud = 9600;
2839 int bits = 8;
2840 int parity = 'n';
2841 int flow = 'n';
2842
2843 /*
2844 * Check whether an invalid uart number has been specified, and
2845 * if so, search for the first available port that does have
2846 * console support.
2847 */
a61c2d78 2848 if (co->index >= nr_uarts)
1da177e4
LT		 2849 co->index = 0;
2850 port = &serial8250_ports[co->index].port;
2851 if (!port->iobase && !port->membase)
2852 return -ENODEV;
2853
2854 if (options)
2855 uart_parse_options(options, &baud, &parity, &bits, &flow);
2856
2857 return uart_set_options(port, co, baud, parity, bits, flow);
2858}
2859
b6b1d877 2860static int serial8250_console_early_setup(void)
18a8bd94
YL		 2861{
2862 return serial8250_find_port_for_earlycon();
2863}
2864
1da177e4
LT		 2865static struct console serial8250_console = {
2866 .name = "ttyS",
2867 .write = serial8250_console_write,
2868 .device = uart_console_device,
2869 .setup = serial8250_console_setup,
18a8bd94 2870 .early_setup = serial8250_console_early_setup,
a80c49db 2871 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2872 .index = -1,
2873 .data = &serial8250_reg,
2874};
2875
2876static int __init serial8250_console_init(void)
2877{
2878 serial8250_isa_init_ports();
2879 register_console(&serial8250_console);
2880 return 0;
2881}
2882console_initcall(serial8250_console_init);
2883
18a8bd94 2884int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2885{
2886 int line;
2887 struct uart_port *port;
2888
a61c2d78 2889 for (line = 0; line < nr_uarts; line++) {
1da177e4 2890 port = &serial8250_ports[line].port;
50aec3b5 2891 if (uart_match_port(p, port))
1da177e4
LT		 2892 return line;
2893 }
2894 return -ENODEV;
2895}
2896
1da177e4
LT		 2897#define SERIAL8250_CONSOLE &serial8250_console
2898#else
2899#define SERIAL8250_CONSOLE NULL
2900#endif
2901
2902static struct uart_driver serial8250_reg = {
2903 .owner = THIS_MODULE,
2904 .driver_name = "serial",
1da177e4
LT		 2905 .dev_name = "ttyS",
2906 .major = TTY_MAJOR,
2907 .minor = 64,
1da177e4
LT		 2908 .cons = SERIAL8250_CONSOLE,
2909};
2910
d856c666
RK		 2911/*
2912 * early_serial_setup - early registration for 8250 ports
2913 *
2914 * Setup an 8250 port structure prior to console initialisation. Use
2915 * after console initialisation will cause undefined behaviour.
2916 */
1da177e4
LT		 2917int __init early_serial_setup(struct uart_port *port)
2918{
b430428a
DD		 2919 struct uart_port *p;
2920
1da177e4
LT		 2921 if (port->line >= ARRAY_SIZE(serial8250_ports))
2922 return -ENODEV;
2923
2924 serial8250_isa_init_ports();
b430428a
DD		 2925 p = &serial8250_ports[port->line].port;
2926 p->iobase = port->iobase;
2927 p->membase = port->membase;
2928 p->irq = port->irq;
1c2f0493 2929 p->irqflags = port->irqflags;
b430428a
DD		 2930 p->uartclk = port->uartclk;
2931 p->fifosize = port->fifosize;
2932 p->regshift = port->regshift;
2933 p->iotype = port->iotype;
2934 p->flags = port->flags;
2935 p->mapbase = port->mapbase;
2936 p->private_data = port->private_data;
125c97d8
HD		 2937 p->type = port->type;
2938 p->line = port->line;
7d6a07d1
DD		 2939
2940 set_io_from_upio(p);
2941 if (port->serial_in)
2942 p->serial_in = port->serial_in;
2943 if (port->serial_out)
2944 p->serial_out = port->serial_out;
583d28e9
JI		 2945 if (port->handle_irq)
2946 p->handle_irq = port->handle_irq;
2947 else
2948 p->handle_irq = serial8250_default_handle_irq;
7d6a07d1 2949
1da177e4
LT		 2950 return 0;
2951}
2952
2953/**
2954 * serial8250_suspend_port - suspend one serial port
2955 * @line: serial line number
1da177e4
LT		 2956 *
2957 * Suspend one serial port.
2958 */
2959void serial8250_suspend_port(int line)
2960{
2961 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2962}
2963
2964/**
2965 * serial8250_resume_port - resume one serial port
2966 * @line: serial line number
1da177e4
LT		 2967 *
2968 * Resume one serial port.
2969 */
2970void serial8250_resume_port(int line)
2971{
b5b82df6 2972 struct uart_8250_port *up = &serial8250_ports[line];
dfe42443 2973 struct uart_port *port = &up->port;
b5b82df6
DW		 2974
2975 if (up->capabilities & UART_NATSEMI) {
b5b82df6 2976 /* Ensure it's still in high speed mode */
4fd996a1 2977 serial_port_out(port, UART_LCR, 0xE0);
b5b82df6 2978
0d0389e5 2979 ns16550a_goto_highspeed(up);
b5b82df6 2980
4fd996a1 2981 serial_port_out(port, UART_LCR, 0);
dfe42443 2982 port->uartclk = 921600*16;
b5b82df6 2983 }
dfe42443 2984 uart_resume_port(&serial8250_reg, port);
1da177e4
LT		 2985}
2986
2987/*
2988 * Register a set of serial devices attached to a platform device. The
2989 * list is terminated with a zero flags entry, which means we expect
2990 * all entries to have at least UPF_BOOT_AUTOCONF set.
2991 */
3ae5eaec 2992static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2993{
3ae5eaec 2994 struct plat_serial8250_port *p = dev->dev.platform_data;
2655a2c7 2995 struct uart_8250_port uart;
4c0ebb80 2996 int ret, i, irqflag = 0;
1da177e4 2997
2655a2c7 2998 memset(&uart, 0, sizeof(uart));
1da177e4 2999
4c0ebb80
AGR		 3000 if (share_irqs)
3001 irqflag = IRQF_SHARED;
3002
ec9f47cd 3003 for (i = 0; p && p->flags != 0; p++, i++) {
2655a2c7
AC		 3004 uart.port.iobase = p->iobase;
3005 uart.port.membase = p->membase;
3006 uart.port.irq = p->irq;
3007 uart.port.irqflags = p->irqflags;
3008 uart.port.uartclk = p->uartclk;
3009 uart.port.regshift = p->regshift;
3010 uart.port.iotype = p->iotype;
3011 uart.port.flags = p->flags;
3012 uart.port.mapbase = p->mapbase;
3013 uart.port.hub6 = p->hub6;
3014 uart.port.private_data = p->private_data;
3015 uart.port.type = p->type;
3016 uart.port.serial_in = p->serial_in;
3017 uart.port.serial_out = p->serial_out;
3018 uart.port.handle_irq = p->handle_irq;
3019 uart.port.handle_break = p->handle_break;
3020 uart.port.set_termios = p->set_termios;
3021 uart.port.pm = p->pm;
3022 uart.port.dev = &dev->dev;
3023 uart.port.irqflags |= irqflag;
3024 ret = serial8250_register_8250_port(&uart);
ec9f47cd 3025 if (ret < 0) {
3ae5eaec 3026 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 3027 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3028 p->iobase, (unsigned long long)p->mapbase,
3029 p->irq, ret);
ec9f47cd 3030 }
1da177e4
LT		 3031 }
3032 return 0;
3033}
3034
3035/*
3036 * Remove serial ports registered against a platform device.
3037 */
3ae5eaec 3038static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 3039{
3040 int i;
3041
a61c2d78 3042 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 3043 struct uart_8250_port *up = &serial8250_ports[i];
3044
3ae5eaec 3045 if (up->port.dev == &dev->dev)
1da177e4
LT		 3046 serial8250_unregister_port(i);
3047 }
3048 return 0;
3049}
3050
3ae5eaec 3051static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 3052{
3053 int i;
3054
1da177e4
LT		 3055 for (i = 0; i < UART_NR; i++) {
3056 struct uart_8250_port *up = &serial8250_ports[i];
3057
3ae5eaec 3058 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3059 uart_suspend_port(&serial8250_reg, &up->port);
3060 }
3061
3062 return 0;
3063}
3064
3ae5eaec 3065static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3066{
3067 int i;
3068
1da177e4
LT		 3069 for (i = 0; i < UART_NR; i++) {
3070 struct uart_8250_port *up = &serial8250_ports[i];
3071
3ae5eaec 3072 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3073 serial8250_resume_port(i);
1da177e4
LT		 3074 }
3075
3076 return 0;
3077}
3078
3ae5eaec 3079static struct platform_driver serial8250_isa_driver = {
1da177e4 3080 .probe = serial8250_probe,
2d47b716 3081 .remove = serial8250_remove,
1da177e4
LT		 3082 .suspend = serial8250_suspend,
3083 .resume = serial8250_resume,
3ae5eaec
RK		 3084 .driver = {
3085 .name = "serial8250",
7493a314 3086 .owner = THIS_MODULE,
3ae5eaec 3087 },
1da177e4
LT		 3088};
3089
3090/*
3091 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3092 * in the table in include/asm/serial.h
3093 */
3094static struct platform_device *serial8250_isa_devs;
3095
3096/*
2655a2c7 3097 * serial8250_register_8250_port and serial8250_unregister_port allows for
1da177e4
LT		 3098 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3099 * modems and PCI multiport cards.
3100 */
f392ecfa 3101static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3102
3103static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3104{
3105 int i;
3106
3107 /*
3108 * First, find a port entry which matches.
3109 */
a61c2d78 3110 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3111 if (uart_match_port(&serial8250_ports[i].port, port))
3112 return &serial8250_ports[i];
3113
3114 /*
3115 * We didn't find a matching entry, so look for the first
3116 * free entry. We look for one which hasn't been previously
3117 * used (indicated by zero iobase).
3118 */
a61c2d78 3119 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3120 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3121 serial8250_ports[i].port.iobase == 0)
3122 return &serial8250_ports[i];
3123
3124 /*
3125 * That also failed. Last resort is to find any entry which
3126 * doesn't have a real port associated with it.
3127 */
a61c2d78 3128 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3129 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3130 return &serial8250_ports[i];
3131
3132 return NULL;
3133}
3134
3135/**
f73fa05b 3136 * serial8250_register_8250_port - register a serial port
58bcd332 3137 * @up: serial port template
1da177e4
LT		 3138 *
3139 * Configure the serial port specified by the request. If the
3140 * port exists and is in use, it is hung up and unregistered
3141 * first.
3142 *
3143 * The port is then probed and if necessary the IRQ is autodetected
3144 * If this fails an error is returned.
3145 *
3146 * On success the port is ready to use and the line number is returned.
3147 */
f73fa05b 3148int serial8250_register_8250_port(struct uart_8250_port *up)
1da177e4
LT		 3149{
3150 struct uart_8250_port *uart;
3151 int ret = -ENOSPC;
3152
f73fa05b 3153 if (up->port.uartclk == 0)
1da177e4
LT		 3154 return -EINVAL;
3155
f392ecfa 3156 mutex_lock(&serial_mutex);
1da177e4 3157
f73fa05b 3158 uart = serial8250_find_match_or_unused(&up->port);
65ecc9c0 3159 if (uart && uart->port.type != PORT_8250_CIR) {
835d844d
SY		 3160 if (uart->port.dev)
3161 uart_remove_one_port(&serial8250_reg, &uart->port);
1da177e4 3162
f73fa05b
MD		 3163 uart->port.iobase = up->port.iobase;
3164 uart->port.membase = up->port.membase;
3165 uart->port.irq = up->port.irq;
3166 uart->port.irqflags = up->port.irqflags;
3167 uart->port.uartclk = up->port.uartclk;
3168 uart->port.fifosize = up->port.fifosize;
3169 uart->port.regshift = up->port.regshift;
3170 uart->port.iotype = up->port.iotype;
3171 uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF;
a2d33d87 3172 uart->bugs = up->bugs;
f73fa05b
MD		 3173 uart->port.mapbase = up->port.mapbase;
3174 uart->port.private_data = up->port.private_data;
3175 if (up->port.dev)
3176 uart->port.dev = up->port.dev;
3177
3178 if (up->port.flags & UPF_FIXED_TYPE)
3179 serial8250_init_fixed_type_port(uart, up->port.type);
8e23fcc8 3180
7d6a07d1
DD		 3181 set_io_from_upio(&uart->port);
3182 /* Possibly override default I/O functions. */
f73fa05b
MD		 3183 if (up->port.serial_in)
3184 uart->port.serial_in = up->port.serial_in;
3185 if (up->port.serial_out)
3186 uart->port.serial_out = up->port.serial_out;
3187 if (up->port.handle_irq)
3188 uart->port.handle_irq = up->port.handle_irq;
235dae5d 3189 /* Possibly override set_termios call */
f73fa05b
MD		 3190 if (up->port.set_termios)
3191 uart->port.set_termios = up->port.set_termios;
3192 if (up->port.pm)
3193 uart->port.pm = up->port.pm;
3194 if (up->port.handle_break)
3195 uart->port.handle_break = up->port.handle_break;
3196 if (up->dl_read)
3197 uart->dl_read = up->dl_read;
3198 if (up->dl_write)
3199 uart->dl_write = up->dl_write;
1da177e4 3200
af7f3743
AC		 3201 if (serial8250_isa_config != NULL)
3202 serial8250_isa_config(0, &uart->port,
3203 &uart->capabilities);
3204
1da177e4
LT		 3205 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3206 if (ret == 0)
3207 ret = uart->port.line;
3208 }
f392ecfa 3209 mutex_unlock(&serial_mutex);
1da177e4
LT		 3210
3211 return ret;
3212}
f73fa05b
MD		 3213EXPORT_SYMBOL(serial8250_register_8250_port);
3214
1da177e4
LT		 3215/**
3216 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3217 * @line: serial line number
3218 *
3219 * Remove one serial port. This may not be called from interrupt
3220 * context. We hand the port back to the our control.
3221 */
3222void serial8250_unregister_port(int line)
3223{
3224 struct uart_8250_port *uart = &serial8250_ports[line];
3225
f392ecfa 3226 mutex_lock(&serial_mutex);
1da177e4
LT		 3227 uart_remove_one_port(&serial8250_reg, &uart->port);
3228 if (serial8250_isa_devs) {
3229 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3230 uart->port.type = PORT_UNKNOWN;
3231 uart->port.dev = &serial8250_isa_devs->dev;
cb01ece3 3232 uart->capabilities = uart_config[uart->port.type].flags;
1da177e4
LT		 3233 uart_add_one_port(&serial8250_reg, &uart->port);
3234 } else {
3235 uart->port.dev = NULL;
3236 }
f392ecfa 3237 mutex_unlock(&serial_mutex);
1da177e4
LT		 3238}
3239EXPORT_SYMBOL(serial8250_unregister_port);
3240
3241static int __init serial8250_init(void)
3242{
25db8ad5 3243 int ret;
1da177e4 3244
835d844d 3245 serial8250_isa_init_ports();
a61c2d78 3246
f1fb9bb8 3247 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3248 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3249 share_irqs ? "en" : "dis");
3250
b70ac771
DM		 3251#ifdef CONFIG_SPARC
3252 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3253#else
3254 serial8250_reg.nr = UART_NR;
1da177e4 3255 ret = uart_register_driver(&serial8250_reg);
b70ac771 3256#endif
1da177e4
LT		 3257 if (ret)
3258 goto out;
3259
835d844d
SY		 3260 ret = serial8250_pnp_init();
3261 if (ret)
3262 goto unreg_uart_drv;
3263
7493a314
DT		 3264 serial8250_isa_devs = platform_device_alloc("serial8250",
3265 PLAT8250_DEV_LEGACY);
3266 if (!serial8250_isa_devs) {
3267 ret = -ENOMEM;
835d844d 3268 goto unreg_pnp;
1da177e4
LT		 3269 }
3270
7493a314
DT		 3271 ret = platform_device_add(serial8250_isa_devs);
3272 if (ret)
3273 goto put_dev;
3274
1da177e4
LT		 3275 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3276
bc965a7f
RK		 3277 ret = platform_driver_register(&serial8250_isa_driver);
3278 if (ret == 0)
3279 goto out;
1da177e4 3280
bc965a7f 3281 platform_device_del(serial8250_isa_devs);
25db8ad5 3282put_dev:
7493a314 3283 platform_device_put(serial8250_isa_devs);
835d844d
SY		 3284unreg_pnp:
3285 serial8250_pnp_exit();
25db8ad5 3286unreg_uart_drv:
b70ac771
DM		 3287#ifdef CONFIG_SPARC
3288 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3289#else
1da177e4 3290 uart_unregister_driver(&serial8250_reg);
b70ac771 3291#endif
25db8ad5 3292out:
1da177e4
LT		 3293 return ret;
3294}
3295
3296static void __exit serial8250_exit(void)
3297{
3298 struct platform_device *isa_dev = serial8250_isa_devs;
3299
3300 /*
3301 * This tells serial8250_unregister_port() not to re-register
3302 * the ports (thereby making serial8250_isa_driver permanently
3303 * in use.)
3304 */
3305 serial8250_isa_devs = NULL;
3306
3ae5eaec 3307 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3308 platform_device_unregister(isa_dev);
3309
835d844d
SY		 3310 serial8250_pnp_exit();
3311
b70ac771
DM		 3312#ifdef CONFIG_SPARC
3313 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3314#else
1da177e4 3315 uart_unregister_driver(&serial8250_reg);
b70ac771 3316#endif
1da177e4
LT		 3317}
3318
3319module_init(serial8250_init);
3320module_exit(serial8250_exit);
3321
3322EXPORT_SYMBOL(serial8250_suspend_port);
3323EXPORT_SYMBOL(serial8250_resume_port);
3324
3325MODULE_LICENSE("GPL");
d87a6d95 3326MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3327
3328module_param(share_irqs, uint, 0644);
3329MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3330 " (unsafe)");
3331
a61c2d78
DJ		 3332module_param(nr_uarts, uint, 0644);
3333MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3334
d41a4b51
CE		 3335module_param(skip_txen_test, uint, 0644);
3336MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3337
1da177e4
LT		 3338#ifdef CONFIG_SERIAL_8250_RSA
3339module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3340MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3341#endif
3342MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux kernel - Deliverables
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