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Linux 3.5-rc2
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
1da177e4
LT		 13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
1da177e4
LT		 18
19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
1da177e4 29#include <linux/delay.h>
d052d1be 30#include <linux/platform_device.h>
1da177e4 31#include <linux/tty.h>
cd3ecad1 32#include <linux/ratelimit.h>
1da177e4
LT		 33#include <linux/tty_flip.h>
34#include <linux/serial_reg.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
78512ece 38#include <linux/nmi.h>
f392ecfa 39#include <linux/mutex.h>
5a0e3ad6 40#include <linux/slab.h>
6816383a
PG		 41#ifdef CONFIG_SPARC
42#include <linux/sunserialcore.h>
43#endif
1da177e4
LT		 44
45#include <asm/io.h>
46#include <asm/irq.h>
47
48#include "8250.h"
49
50/*
51 * Configuration:
40663cc7 52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 53 * is unsafe when used on edge-triggered interrupts.
54 */
408b664a 55static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 56
a61c2d78
DJ		 57static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
8440838b
DM		 59static struct uart_driver serial8250_reg;
60
61static int serial_index(struct uart_port *port)
62{
63 return (serial8250_reg.minor - 64) + port->line;
64}
65
d41a4b51
CE		 66static unsigned int skip_txen_test; /* force skip of txen test at init time */
67
1da177e4
LT		 68/*
69 * Debugging.
70 */
71#if 0
72#define DEBUG_AUTOCONF(fmt...) printk(fmt)
73#else
74#define DEBUG_AUTOCONF(fmt...) do { } while (0)
75#endif
76
77#if 0
78#define DEBUG_INTR(fmt...) printk(fmt)
79#else
80#define DEBUG_INTR(fmt...) do { } while (0)
81#endif
82
e7328ae1 83#define PASS_LIMIT 512
1da177e4 84
bca47613
DH		 85#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
86
87
1da177e4
LT		 88#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89#define CONFIG_SERIAL_DETECT_IRQ 1
90#endif
1da177e4
LT		 91#ifdef CONFIG_SERIAL_8250_MANY_PORTS
92#define CONFIG_SERIAL_MANY_PORTS 1
93#endif
94
95/*
96 * HUB6 is always on. This will be removed once the header
97 * files have been cleaned.
98 */
99#define CONFIG_HUB6 1
100
a4ed1e41 101#include <asm/serial.h>
1da177e4
LT		 102/*
103 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * standard enumeration mechanism. Platforms that can find all
105 * serial ports via mechanisms like ACPI or PCI need not supply it.
106 */
107#ifndef SERIAL_PORT_DFNS
108#define SERIAL_PORT_DFNS
109#endif
110
cb3592be 111static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
113};
114
026d02a2 115#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 116
117#ifdef CONFIG_SERIAL_8250_RSA
118
119#define PORT_RSA_MAX 4
120static unsigned long probe_rsa[PORT_RSA_MAX];
121static unsigned int probe_rsa_count;
122#endif /* CONFIG_SERIAL_8250_RSA */
123
1da177e4 124struct irq_info {
25db8ad5
AC		 125 struct hlist_node node;
126 int irq;
127 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 128 struct list_head *head;
129};
130
25db8ad5
AC		 131#define NR_IRQ_HASH 32 /* Can be adjusted later */
132static struct hlist_head irq_lists[NR_IRQ_HASH];
133static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 134
135/*
136 * Here we define the default xmit fifo size used for each type of UART.
137 */
138static const struct serial8250_config uart_config[] = {
139 [PORT_UNKNOWN] = {
140 .name = "unknown",
141 .fifo_size = 1,
142 .tx_loadsz = 1,
143 },
144 [PORT_8250] = {
145 .name = "8250",
146 .fifo_size = 1,
147 .tx_loadsz = 1,
148 },
149 [PORT_16450] = {
150 .name = "16450",
151 .fifo_size = 1,
152 .tx_loadsz = 1,
153 },
154 [PORT_16550] = {
155 .name = "16550",
156 .fifo_size = 1,
157 .tx_loadsz = 1,
158 },
159 [PORT_16550A] = {
160 .name = "16550A",
161 .fifo_size = 16,
162 .tx_loadsz = 16,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO,
165 },
166 [PORT_CIRRUS] = {
167 .name = "Cirrus",
168 .fifo_size = 1,
169 .tx_loadsz = 1,
170 },
171 [PORT_16650] = {
172 .name = "ST16650",
173 .fifo_size = 1,
174 .tx_loadsz = 1,
175 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
176 },
177 [PORT_16650V2] = {
178 .name = "ST16650V2",
179 .fifo_size = 32,
180 .tx_loadsz = 16,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
182 UART_FCR_T_TRIG_00,
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184 },
185 [PORT_16750] = {
186 .name = "TI16750",
187 .fifo_size = 64,
188 .tx_loadsz = 64,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
190 UART_FCR7_64BYTE,
191 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
192 },
193 [PORT_STARTECH] = {
194 .name = "Startech",
195 .fifo_size = 1,
196 .tx_loadsz = 1,
197 },
198 [PORT_16C950] = {
199 .name = "16C950/954",
200 .fifo_size = 128,
201 .tx_loadsz = 128,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
d0694e2a
PM		 203 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
1da177e4
LT		 205 },
206 [PORT_16654] = {
207 .name = "ST16654",
208 .fifo_size = 64,
209 .tx_loadsz = 32,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
211 UART_FCR_T_TRIG_10,
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
213 },
214 [PORT_16850] = {
215 .name = "XR16850",
216 .fifo_size = 128,
217 .tx_loadsz = 128,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220 },
221 [PORT_RSA] = {
222 .name = "RSA",
223 .fifo_size = 2048,
224 .tx_loadsz = 2048,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226 .flags = UART_CAP_FIFO,
227 },
228 [PORT_NS16550A] = {
229 .name = "NS16550A",
230 .fifo_size = 16,
231 .tx_loadsz = 16,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_NATSEMI,
234 },
235 [PORT_XSCALE] = {
236 .name = "XScale",
237 .fifo_size = 32,
238 .tx_loadsz = 32,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
4539c24f 240 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
1da177e4 241 },
bd71c182
TK		 242 [PORT_RM9000] = {
243 .name = "RM9000",
244 .fifo_size = 16,
245 .tx_loadsz = 16,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 247 .flags = UART_CAP_FIFO,
248 },
249 [PORT_OCTEON] = {
250 .name = "OCTEON",
251 .fifo_size = 64,
252 .tx_loadsz = 64,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 254 .flags = UART_CAP_FIFO,
255 },
08e0992f
FF		 256 [PORT_AR7] = {
257 .name = "AR7",
258 .fifo_size = 16,
259 .tx_loadsz = 16,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
261 .flags = UART_CAP_FIFO | UART_CAP_AFE,
262 },
235dae5d
PL		 263 [PORT_U6_16550A] = {
264 .name = "U6_16550A",
265 .fifo_size = 64,
266 .tx_loadsz = 64,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO | UART_CAP_AFE,
269 },
4539c24f
SW		 270 [PORT_TEGRA] = {
271 .name = "Tegra",
272 .fifo_size = 32,
273 .tx_loadsz = 8,
274 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
275 UART_FCR_T_TRIG_01,
276 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
277 },
06315348
SH		 278 [PORT_XR17D15X] = {
279 .name = "XR17D15X",
280 .fifo_size = 64,
281 .tx_loadsz = 64,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
283 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
284 },
1da177e4
LT		 285};
286
cc419fa0 287/* Uart divisor latch read */
e8155629 288static int default_serial_dl_read(struct uart_8250_port *up)
cc419fa0
MD		 289{
290 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
291}
292
293/* Uart divisor latch write */
e8155629 294static void default_serial_dl_write(struct uart_8250_port *up, int value)
cc419fa0
MD		 295{
296 serial_out(up, UART_DLL, value & 0xff);
297 serial_out(up, UART_DLM, value >> 8 & 0xff);
298}
299
6b416031 300#ifdef CONFIG_MIPS_ALCHEMY
21c614a7
PA		 301
302/* Au1x00 UART hardware has a weird register layout */
303static const u8 au_io_in_map[] = {
304 [UART_RX] = 0,
305 [UART_IER] = 2,
306 [UART_IIR] = 3,
307 [UART_LCR] = 5,
308 [UART_MCR] = 6,
309 [UART_LSR] = 7,
310 [UART_MSR] = 8,
311};
312
313static const u8 au_io_out_map[] = {
314 [UART_TX] = 1,
315 [UART_IER] = 2,
316 [UART_FCR] = 4,
317 [UART_LCR] = 5,
318 [UART_MCR] = 6,
319};
320
6b416031 321static unsigned int au_serial_in(struct uart_port *p, int offset)
21c614a7 322{
6b416031
MD		 323 offset = au_io_in_map[offset] << p->regshift;
324 return __raw_readl(p->membase + offset);
21c614a7
PA		 325}
326
6b416031 327static void au_serial_out(struct uart_port *p, int offset, int value)
21c614a7 328{
6b416031
MD		 329 offset = au_io_out_map[offset] << p->regshift;
330 __raw_writel(value, p->membase + offset);
331}
332
333/* Au1x00 haven't got a standard divisor latch */
334static int au_serial_dl_read(struct uart_8250_port *up)
335{
336 return __raw_readl(up->port.membase + 0x28);
337}
338
339static void au_serial_dl_write(struct uart_8250_port *up, int value)
340{
341 __raw_writel(value, up->port.membase + 0x28);
21c614a7
PA		 342}
343
6b416031
MD		 344#endif
345
28bf4cf2 346#ifdef CONFIG_SERIAL_8250_RM9K
bd71c182
TK		 347
348static const u8
349 regmap_in[8] = {
350 [UART_RX] = 0x00,
351 [UART_IER] = 0x0c,
352 [UART_IIR] = 0x14,
353 [UART_LCR] = 0x1c,
354 [UART_MCR] = 0x20,
355 [UART_LSR] = 0x24,
356 [UART_MSR] = 0x28,
357 [UART_SCR] = 0x2c
358 },
359 regmap_out[8] = {
360 [UART_TX] = 0x04,
361 [UART_IER] = 0x0c,
362 [UART_FCR] = 0x18,
363 [UART_LCR] = 0x1c,
364 [UART_MCR] = 0x20,
365 [UART_LSR] = 0x24,
366 [UART_MSR] = 0x28,
367 [UART_SCR] = 0x2c
368 };
369
28bf4cf2 370static unsigned int rm9k_serial_in(struct uart_port *p, int offset)
bd71c182 371{
28bf4cf2
MD		 372 offset = regmap_in[offset] << p->regshift;
373 return readl(p->membase + offset);
bd71c182
TK		 374}
375
28bf4cf2 376static void rm9k_serial_out(struct uart_port *p, int offset, int value)
bd71c182 377{
28bf4cf2
MD		 378 offset = regmap_out[offset] << p->regshift;
379 writel(value, p->membase + offset);
bd71c182
TK		 380}
381
28bf4cf2
MD		 382static int rm9k_serial_dl_read(struct uart_8250_port *up)
383{
384 return ((__raw_readl(up->port.membase + 0x10) << 8) |
385 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff;
386}
387
388static void rm9k_serial_dl_write(struct uart_8250_port *up, int value)
389{
390 __raw_writel(value, up->port.membase + 0x08);
391 __raw_writel(value >> 8, up->port.membase + 0x10);
392}
393
394#endif
21c614a7 395
7d6a07d1 396static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 397{
e8155629 398 offset = offset << p->regshift;
7d6a07d1
DD		 399 outb(p->hub6 - 1 + offset, p->iobase);
400 return inb(p->iobase + 1);
401}
1da177e4 402
7d6a07d1
DD		 403static void hub6_serial_out(struct uart_port *p, int offset, int value)
404{
e8155629 405 offset = offset << p->regshift;
7d6a07d1
DD		 406 outb(p->hub6 - 1 + offset, p->iobase);
407 outb(value, p->iobase + 1);
408}
1da177e4 409
7d6a07d1
DD		 410static unsigned int mem_serial_in(struct uart_port *p, int offset)
411{
e8155629 412 offset = offset << p->regshift;
7d6a07d1
DD		 413 return readb(p->membase + offset);
414}
1da177e4 415
7d6a07d1
DD		 416static void mem_serial_out(struct uart_port *p, int offset, int value)
417{
e8155629 418 offset = offset << p->regshift;
7d6a07d1
DD		 419 writeb(value, p->membase + offset);
420}
421
422static void mem32_serial_out(struct uart_port *p, int offset, int value)
423{
e8155629 424 offset = offset << p->regshift;
7d6a07d1
DD		 425 writel(value, p->membase + offset);
426}
427
428static unsigned int mem32_serial_in(struct uart_port *p, int offset)
429{
e8155629 430 offset = offset << p->regshift;
7d6a07d1
DD		 431 return readl(p->membase + offset);
432}
1da177e4 433
7d6a07d1
DD		 434static unsigned int io_serial_in(struct uart_port *p, int offset)
435{
e8155629 436 offset = offset << p->regshift;
7d6a07d1
DD		 437 return inb(p->iobase + offset);
438}
439
440static void io_serial_out(struct uart_port *p, int offset, int value)
441{
e8155629 442 offset = offset << p->regshift;
7d6a07d1
DD		 443 outb(value, p->iobase + offset);
444}
445
583d28e9
JI		 446static int serial8250_default_handle_irq(struct uart_port *port);
447
7d6a07d1
DD		 448static void set_io_from_upio(struct uart_port *p)
449{
49d5741b
JI		 450 struct uart_8250_port *up =
451 container_of(p, struct uart_8250_port, port);
cc419fa0 452
e8155629
MD		 453 up->dl_read = default_serial_dl_read;
454 up->dl_write = default_serial_dl_write;
cc419fa0 455
7d6a07d1 456 switch (p->iotype) {
1da177e4 457 case UPIO_HUB6:
7d6a07d1
DD		 458 p->serial_in = hub6_serial_in;
459 p->serial_out = hub6_serial_out;
1da177e4
LT		 460 break;
461
462 case UPIO_MEM:
7d6a07d1
DD		 463 p->serial_in = mem_serial_in;
464 p->serial_out = mem_serial_out;
1da177e4
LT		 465 break;
466
467 case UPIO_MEM32:
7d6a07d1
DD		 468 p->serial_in = mem32_serial_in;
469 p->serial_out = mem32_serial_out;
1da177e4
LT		 470 break;
471
28bf4cf2
MD		 472#ifdef CONFIG_SERIAL_8250_RM9K
473 case UPIO_RM9000:
474 p->serial_in = rm9k_serial_in;
475 p->serial_out = rm9k_serial_out;
476 up->dl_read = rm9k_serial_dl_read;
477 up->dl_write = rm9k_serial_dl_write;
478 break;
479#endif
480
6b416031 481#ifdef CONFIG_MIPS_ALCHEMY
21c614a7 482 case UPIO_AU:
7d6a07d1
DD		 483 p->serial_in = au_serial_in;
484 p->serial_out = au_serial_out;
6b416031
MD		 485 up->dl_read = au_serial_dl_read;
486 up->dl_write = au_serial_dl_write;
21c614a7 487 break;
6b416031 488#endif
12bf3f24 489
1da177e4 490 default:
7d6a07d1
DD		 491 p->serial_in = io_serial_in;
492 p->serial_out = io_serial_out;
493 break;
1da177e4 494 }
b8e7e40a
AC		 495 /* Remember loaded iotype */
496 up->cur_iotype = p->iotype;
583d28e9 497 p->handle_irq = serial8250_default_handle_irq;
1da177e4
LT		 498}
499
40b36daa 500static void
55e4016d 501serial_port_out_sync(struct uart_port *p, int offset, int value)
40b36daa 502{
7d6a07d1 503 switch (p->iotype) {
40b36daa
AW		 504 case UPIO_MEM:
505 case UPIO_MEM32:
40b36daa 506 case UPIO_AU:
7d6a07d1
DD		 507 p->serial_out(p, offset, value);
508 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 509 break;
510 default:
7d6a07d1 511 p->serial_out(p, offset, value);
40b36daa
AW		 512 }
513}
514
1da177e4
LT		 515/*
516 * For the 16C950
517 */
518static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
519{
520 serial_out(up, UART_SCR, offset);
521 serial_out(up, UART_ICR, value);
522}
523
524static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
525{
526 unsigned int value;
527
528 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
529 serial_out(up, UART_SCR, offset);
530 value = serial_in(up, UART_ICR);
531 serial_icr_write(up, UART_ACR, up->acr);
532
533 return value;
534}
535
536/*
537 * FIFO support.
538 */
b5d674ab 539static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 540{
541 if (p->capabilities & UART_CAP_FIFO) {
0acf519f
PG		 542 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
543 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
1da177e4 544 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0acf519f 545 serial_out(p, UART_FCR, 0);
1da177e4
LT		 546 }
547}
548
0ad372b9
SM		 549void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
550{
551 unsigned char fcr;
552
553 serial8250_clear_fifos(p);
554 fcr = uart_config[p->port.type].fcr;
555 serial_out(p, UART_FCR, fcr);
556}
557EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
558
1da177e4
LT		 559/*
560 * IER sleep support. UARTs which have EFRs need the "extended
561 * capability" bit enabled. Note that on XR16C850s, we need to
562 * reset LCR to write to IER.
563 */
b5d674ab 564static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4
LT		 565{
566 if (p->capabilities & UART_CAP_SLEEP) {
567 if (p->capabilities & UART_CAP_EFR) {
0acf519f
PG		 568 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
569 serial_out(p, UART_EFR, UART_EFR_ECB);
570 serial_out(p, UART_LCR, 0);
1da177e4 571 }
0acf519f 572 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
1da177e4 573 if (p->capabilities & UART_CAP_EFR) {
0acf519f
PG		 574 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
575 serial_out(p, UART_EFR, 0);
576 serial_out(p, UART_LCR, 0);
1da177e4
LT		 577 }
578 }
579}
580
581#ifdef CONFIG_SERIAL_8250_RSA
582/*
583 * Attempts to turn on the RSA FIFO. Returns zero on failure.
584 * We set the port uart clock rate if we succeed.
585 */
586static int __enable_rsa(struct uart_8250_port *up)
587{
588 unsigned char mode;
589 int result;
590
0acf519f 591 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 592 result = mode & UART_RSA_MSR_FIFO;
593
594 if (!result) {
0acf519f
PG		 595 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
596 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 597 result = mode & UART_RSA_MSR_FIFO;
598 }
599
600 if (result)
601 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
602
603 return result;
604}
605
606static void enable_rsa(struct uart_8250_port *up)
607{
608 if (up->port.type == PORT_RSA) {
609 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
610 spin_lock_irq(&up->port.lock);
611 __enable_rsa(up);
612 spin_unlock_irq(&up->port.lock);
613 }
614 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
0acf519f 615 serial_out(up, UART_RSA_FRR, 0);
1da177e4
LT		 616 }
617}
618
619/*
620 * Attempts to turn off the RSA FIFO. Returns zero on failure.
621 * It is unknown why interrupts were disabled in here. However,
622 * the caller is expected to preserve this behaviour by grabbing
623 * the spinlock before calling this function.
624 */
625static void disable_rsa(struct uart_8250_port *up)
626{
627 unsigned char mode;
628 int result;
629
630 if (up->port.type == PORT_RSA &&
631 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
632 spin_lock_irq(&up->port.lock);
633
0acf519f 634 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 635 result = !(mode & UART_RSA_MSR_FIFO);
636
637 if (!result) {
0acf519f
PG		 638 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
639 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 640 result = !(mode & UART_RSA_MSR_FIFO);
641 }
642
643 if (result)
644 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
645 spin_unlock_irq(&up->port.lock);
646 }
647}
648#endif /* CONFIG_SERIAL_8250_RSA */
649
650/*
651 * This is a quickie test to see how big the FIFO is.
652 * It doesn't work at all the time, more's the pity.
653 */
654static int size_fifo(struct uart_8250_port *up)
655{
b32b19b8
JAH		 656 unsigned char old_fcr, old_mcr, old_lcr;
657 unsigned short old_dl;
1da177e4
LT		 658 int count;
659
0acf519f
PG		 660 old_lcr = serial_in(up, UART_LCR);
661 serial_out(up, UART_LCR, 0);
662 old_fcr = serial_in(up, UART_FCR);
663 old_mcr = serial_in(up, UART_MCR);
664 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1da177e4 665 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0acf519f
PG		 666 serial_out(up, UART_MCR, UART_MCR_LOOP);
667 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8
JAH		 668 old_dl = serial_dl_read(up);
669 serial_dl_write(up, 0x0001);
0acf519f 670 serial_out(up, UART_LCR, 0x03);
1da177e4 671 for (count = 0; count < 256; count++)
0acf519f 672 serial_out(up, UART_TX, count);
1da177e4 673 mdelay(20);/* FIXME - schedule_timeout */
0acf519f 674 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
1da177e4 675 (count < 256); count++)
0acf519f
PG		 676 serial_in(up, UART_RX);
677 serial_out(up, UART_FCR, old_fcr);
678 serial_out(up, UART_MCR, old_mcr);
679 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8 680 serial_dl_write(up, old_dl);
0acf519f 681 serial_out(up, UART_LCR, old_lcr);
1da177e4
LT		 682
683 return count;
684}
685
686/*
687 * Read UART ID using the divisor method - set DLL and DLM to zero
688 * and the revision will be in DLL and device type in DLM. We
689 * preserve the device state across this.
690 */
691static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
692{
693 unsigned char old_dll, old_dlm, old_lcr;
694 unsigned int id;
695
0acf519f
PG		 696 old_lcr = serial_in(p, UART_LCR);
697 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4 698
0acf519f
PG		 699 old_dll = serial_in(p, UART_DLL);
700 old_dlm = serial_in(p, UART_DLM);
1da177e4 701
0acf519f
PG		 702 serial_out(p, UART_DLL, 0);
703 serial_out(p, UART_DLM, 0);
1da177e4 704
0acf519f 705 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
1da177e4 706
0acf519f
PG		 707 serial_out(p, UART_DLL, old_dll);
708 serial_out(p, UART_DLM, old_dlm);
709 serial_out(p, UART_LCR, old_lcr);
1da177e4
LT		 710
711 return id;
712}
713
714/*
715 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
716 * When this function is called we know it is at least a StarTech
717 * 16650 V2, but it might be one of several StarTech UARTs, or one of
718 * its clones. (We treat the broken original StarTech 16650 V1 as a
719 * 16550, and why not? Startech doesn't seem to even acknowledge its
720 * existence.)
bd71c182 721 *
1da177e4
LT		 722 * What evil have men's minds wrought...
723 */
724static void autoconfig_has_efr(struct uart_8250_port *up)
725{
726 unsigned int id1, id2, id3, rev;
727
728 /*
729 * Everything with an EFR has SLEEP
730 */
731 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
732
733 /*
734 * First we check to see if it's an Oxford Semiconductor UART.
735 *
736 * If we have to do this here because some non-National
737 * Semiconductor clone chips lock up if you try writing to the
738 * LSR register (which serial_icr_read does)
739 */
740
741 /*
742 * Check for Oxford Semiconductor 16C950.
743 *
744 * EFR [4] must be set else this test fails.
745 *
746 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
747 * claims that it's needed for 952 dual UART's (which are not
748 * recommended for new designs).
749 */
750 up->acr = 0;
662b083a 751 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 752 serial_out(up, UART_EFR, UART_EFR_ECB);
753 serial_out(up, UART_LCR, 0x00);
754 id1 = serial_icr_read(up, UART_ID1);
755 id2 = serial_icr_read(up, UART_ID2);
756 id3 = serial_icr_read(up, UART_ID3);
757 rev = serial_icr_read(up, UART_REV);
758
759 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
760
761 if (id1 == 0x16 && id2 == 0xC9 &&
762 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
763 up->port.type = PORT_16C950;
4ba5e35d
RK		 764
765 /*
766 * Enable work around for the Oxford Semiconductor 952 rev B
767 * chip which causes it to seriously miscalculate baud rates
768 * when DLL is 0.
769 */
770 if (id3 == 0x52 && rev == 0x01)
771 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 772 return;
773 }
bd71c182 774
1da177e4
LT		 775 /*
776 * We check for a XR16C850 by setting DLL and DLM to 0, and then
777 * reading back DLL and DLM. The chip type depends on the DLM
778 * value read back:
779 * 0x10 - XR16C850 and the DLL contains the chip revision.
780 * 0x12 - XR16C2850.
781 * 0x14 - XR16C854.
782 */
783 id1 = autoconfig_read_divisor_id(up);
784 DEBUG_AUTOCONF("850id=%04x ", id1);
785
786 id2 = id1 >> 8;
787 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 788 up->port.type = PORT_16850;
789 return;
790 }
791
792 /*
793 * It wasn't an XR16C850.
794 *
795 * We distinguish between the '654 and the '650 by counting
796 * how many bytes are in the FIFO. I'm using this for now,
797 * since that's the technique that was sent to me in the
798 * serial driver update, but I'm not convinced this works.
799 * I've had problems doing this in the past. -TYT
800 */
801 if (size_fifo(up) == 64)
802 up->port.type = PORT_16654;
803 else
804 up->port.type = PORT_16650V2;
805}
806
807/*
808 * We detected a chip without a FIFO. Only two fall into
809 * this category - the original 8250 and the 16450. The
810 * 16450 has a scratch register (accessible with LCR=0)
811 */
812static void autoconfig_8250(struct uart_8250_port *up)
813{
814 unsigned char scratch, status1, status2;
815
816 up->port.type = PORT_8250;
817
818 scratch = serial_in(up, UART_SCR);
0acf519f 819 serial_out(up, UART_SCR, 0xa5);
1da177e4 820 status1 = serial_in(up, UART_SCR);
0acf519f 821 serial_out(up, UART_SCR, 0x5a);
1da177e4 822 status2 = serial_in(up, UART_SCR);
0acf519f 823 serial_out(up, UART_SCR, scratch);
1da177e4
LT		 824
825 if (status1 == 0xa5 && status2 == 0x5a)
826 up->port.type = PORT_16450;
827}
828
829static int broken_efr(struct uart_8250_port *up)
830{
831 /*
832 * Exar ST16C2550 "A2" devices incorrectly detect as
833 * having an EFR, and report an ID of 0x0201. See
631dd1a8 834 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1da177e4
LT		 835 */
836 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
837 return 1;
838
839 return 0;
840}
841
0d0389e5
YK		 842static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
843{
844 unsigned char status;
845
846 status = serial_in(up, 0x04); /* EXCR2 */
847#define PRESL(x) ((x) & 0x30)
848 if (PRESL(status) == 0x10) {
849 /* already in high speed mode */
850 return 0;
851 } else {
852 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
853 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
0acf519f 854 serial_out(up, 0x04, status);
0d0389e5
YK		 855 }
856 return 1;
857}
858
1da177e4
LT		 859/*
860 * We know that the chip has FIFOs. Does it have an EFR? The
861 * EFR is located in the same register position as the IIR and
862 * we know the top two bits of the IIR are currently set. The
863 * EFR should contain zero. Try to read the EFR.
864 */
865static void autoconfig_16550a(struct uart_8250_port *up)
866{
867 unsigned char status1, status2;
868 unsigned int iersave;
869
870 up->port.type = PORT_16550A;
871 up->capabilities |= UART_CAP_FIFO;
872
873 /*
874 * Check for presence of the EFR when DLAB is set.
875 * Only ST16C650V1 UARTs pass this test.
876 */
0acf519f 877 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4 878 if (serial_in(up, UART_EFR) == 0) {
0acf519f 879 serial_out(up, UART_EFR, 0xA8);
1da177e4
LT		 880 if (serial_in(up, UART_EFR) != 0) {
881 DEBUG_AUTOCONF("EFRv1 ");
882 up->port.type = PORT_16650;
883 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
884 } else {
885 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
886 }
0acf519f 887 serial_out(up, UART_EFR, 0);
1da177e4
LT		 888 return;
889 }
890
891 /*
892 * Maybe it requires 0xbf to be written to the LCR.
893 * (other ST16C650V2 UARTs, TI16C752A, etc)
894 */
0acf519f 895 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 896 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
897 DEBUG_AUTOCONF("EFRv2 ");
898 autoconfig_has_efr(up);
899 return;
900 }
901
902 /*
903 * Check for a National Semiconductor SuperIO chip.
904 * Attempt to switch to bank 2, read the value of the LOOP bit
905 * from EXCR1. Switch back to bank 0, change it in MCR. Then
906 * switch back to bank 2, read it from EXCR1 again and check
907 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4 908 */
0acf519f 909 serial_out(up, UART_LCR, 0);
1da177e4 910 status1 = serial_in(up, UART_MCR);
0acf519f 911 serial_out(up, UART_LCR, 0xE0);
1da177e4
LT		 912 status2 = serial_in(up, 0x02); /* EXCR1 */
913
914 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
0acf519f
PG		 915 serial_out(up, UART_LCR, 0);
916 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
917 serial_out(up, UART_LCR, 0xE0);
1da177e4 918 status2 = serial_in(up, 0x02); /* EXCR1 */
0acf519f
PG		 919 serial_out(up, UART_LCR, 0);
920 serial_out(up, UART_MCR, status1);
1da177e4
LT		 921
922 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 923 unsigned short quot;
924
0acf519f 925 serial_out(up, UART_LCR, 0xE0);
857dde2e 926
b32b19b8 927 quot = serial_dl_read(up);
857dde2e
DW		 928 quot <<= 3;
929
0d0389e5
YK		 930 if (ns16550a_goto_highspeed(up))
931 serial_dl_write(up, quot);
857dde2e 932
0acf519f 933 serial_out(up, UART_LCR, 0);
1da177e4 934
857dde2e 935 up->port.uartclk = 921600*16;
1da177e4
LT		 936 up->port.type = PORT_NS16550A;
937 up->capabilities |= UART_NATSEMI;
938 return;
939 }
940 }
941
942 /*
943 * No EFR. Try to detect a TI16750, which only sets bit 5 of
944 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
945 * Try setting it with and without DLAB set. Cheap clones
946 * set bit 5 without DLAB set.
947 */
0acf519f
PG		 948 serial_out(up, UART_LCR, 0);
949 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1da177e4 950 status1 = serial_in(up, UART_IIR) >> 5;
0acf519f
PG		 951 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
952 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
953 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1da177e4 954 status2 = serial_in(up, UART_IIR) >> 5;
0acf519f
PG		 955 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
956 serial_out(up, UART_LCR, 0);
1da177e4
LT		 957
958 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
959
960 if (status1 == 6 && status2 == 7) {
961 up->port.type = PORT_16750;
962 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
963 return;
964 }
965
966 /*
967 * Try writing and reading the UART_IER_UUE bit (b6).
968 * If it works, this is probably one of the Xscale platform's
969 * internal UARTs.
970 * We're going to explicitly set the UUE bit to 0 before
971 * trying to write and read a 1 just to make sure it's not
972 * already a 1 and maybe locked there before we even start start.
973 */
974 iersave = serial_in(up, UART_IER);
0acf519f 975 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1da177e4
LT		 976 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
977 /*
978 * OK it's in a known zero state, try writing and reading
979 * without disturbing the current state of the other bits.
980 */
0acf519f 981 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1da177e4
LT		 982 if (serial_in(up, UART_IER) & UART_IER_UUE) {
983 /*
984 * It's an Xscale.
985 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
986 */
987 DEBUG_AUTOCONF("Xscale ");
988 up->port.type = PORT_XSCALE;
5568181f 989 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1da177e4
LT		 990 return;
991 }
992 } else {
993 /*
994 * If we got here we couldn't force the IER_UUE bit to 0.
995 * Log it and continue.
996 */
997 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
998 }
0acf519f 999 serial_out(up, UART_IER, iersave);
235dae5d 1000
06315348
SH		 1001 /*
1002 * Exar uarts have EFR in a weird location
1003 */
1004 if (up->port.flags & UPF_EXAR_EFR) {
1005 up->port.type = PORT_XR17D15X;
1006 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1007 }
1008
235dae5d
PL		 1009 /*
1010 * We distinguish between 16550A and U6 16550A by counting
1011 * how many bytes are in the FIFO.
1012 */
1013 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1014 up->port.type = PORT_U6_16550A;
1015 up->capabilities |= UART_CAP_AFE;
1016 }
1da177e4
LT		 1017}
1018
1019/*
1020 * This routine is called by rs_init() to initialize a specific serial
1021 * port. It determines what type of UART chip this serial port is
1022 * using: 8250, 16450, 16550, 16550A. The important question is
1023 * whether or not this UART is a 16550A or not, since this will
1024 * determine whether or not we can use its FIFO features or not.
1025 */
1026static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1027{
1028 unsigned char status1, scratch, scratch2, scratch3;
1029 unsigned char save_lcr, save_mcr;
dfe42443 1030 struct uart_port *port = &up->port;
1da177e4
LT		 1031 unsigned long flags;
1032
dfe42443 1033 if (!port->iobase && !port->mapbase && !port->membase)
1da177e4
LT		 1034 return;
1035
80647b95 1036 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
dfe42443 1037 serial_index(port), port->iobase, port->membase);
1da177e4
LT		 1038
1039 /*
1040 * We really do need global IRQs disabled here - we're going to
1041 * be frobbing the chips IRQ enable register to see if it exists.
1042 */
dfe42443 1043 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 1044
1045 up->capabilities = 0;
4ba5e35d 1046 up->bugs = 0;
1da177e4 1047
dfe42443 1048 if (!(port->flags & UPF_BUGGY_UART)) {
1da177e4
LT		 1049 /*
1050 * Do a simple existence test first; if we fail this,
1051 * there's no point trying anything else.
bd71c182 1052 *
1da177e4
LT		 1053 * 0x80 is used as a nonsense port to prevent against
1054 * false positives due to ISA bus float. The
1055 * assumption is that 0x80 is a non-existent port;
1056 * which should be safe since include/asm/io.h also
1057 * makes this assumption.
1058 *
1059 * Note: this is safe as long as MCR bit 4 is clear
1060 * and the device is in "PC" mode.
1061 */
0acf519f
PG		 1062 scratch = serial_in(up, UART_IER);
1063 serial_out(up, UART_IER, 0);
1da177e4
LT		 1064#ifdef __i386__
1065 outb(0xff, 0x080);
1066#endif
48212008
TH		 1067 /*
1068 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1069 * 16C754B) allow only to modify them if an EFR bit is set.
1070 */
0acf519f
PG		 1071 scratch2 = serial_in(up, UART_IER) & 0x0f;
1072 serial_out(up, UART_IER, 0x0F);
1da177e4
LT		 1073#ifdef __i386__
1074 outb(0, 0x080);
1075#endif
0acf519f
PG		 1076 scratch3 = serial_in(up, UART_IER) & 0x0f;
1077 serial_out(up, UART_IER, scratch);
1da177e4
LT		 1078 if (scratch2 != 0 || scratch3 != 0x0F) {
1079 /*
1080 * We failed; there's nothing here
1081 */
1082 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1083 scratch2, scratch3);
1084 goto out;
1085 }
1086 }
1087
1088 save_mcr = serial_in(up, UART_MCR);
1089 save_lcr = serial_in(up, UART_LCR);
1090
bd71c182 1091 /*
1da177e4
LT		 1092 * Check to see if a UART is really there. Certain broken
1093 * internal modems based on the Rockwell chipset fail this
1094 * test, because they apparently don't implement the loopback
1095 * test mode. So this test is skipped on the COM 1 through
1096 * COM 4 ports. This *should* be safe, since no board
1097 * manufacturer would be stupid enough to design a board
1098 * that conflicts with COM 1-4 --- we hope!
1099 */
dfe42443 1100 if (!(port->flags & UPF_SKIP_TEST)) {
0acf519f
PG		 1101 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1102 status1 = serial_in(up, UART_MSR) & 0xF0;
1103 serial_out(up, UART_MCR, save_mcr);
1da177e4
LT		 1104 if (status1 != 0x90) {
1105 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1106 status1);
1107 goto out;
1108 }
1109 }
1110
1111 /*
1112 * We're pretty sure there's a port here. Lets find out what
1113 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1114 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1115 * determines what we test for next.
1116 *
1117 * We also initialise the EFR (if any) to zero for later. The
1118 * EFR occupies the same register location as the FCR and IIR.
1119 */
0acf519f
PG		 1120 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1121 serial_out(up, UART_EFR, 0);
1122 serial_out(up, UART_LCR, 0);
1da177e4 1123
0acf519f 1124 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1da177e4
LT		 1125 scratch = serial_in(up, UART_IIR) >> 6;
1126
1127 DEBUG_AUTOCONF("iir=%d ", scratch);
1128
1129 switch (scratch) {
1130 case 0:
1131 autoconfig_8250(up);
1132 break;
1133 case 1:
dfe42443 1134 port->type = PORT_UNKNOWN;
1da177e4
LT		 1135 break;
1136 case 2:
dfe42443 1137 port->type = PORT_16550;
1da177e4
LT		 1138 break;
1139 case 3:
1140 autoconfig_16550a(up);
1141 break;
1142 }
1143
1144#ifdef CONFIG_SERIAL_8250_RSA
1145 /*
1146 * Only probe for RSA ports if we got the region.
1147 */
dfe42443 1148 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1da177e4
LT		 1149 int i;
1150
1151 for (i = 0 ; i < probe_rsa_count; ++i) {
dfe42443
PG		 1152 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1153 port->type = PORT_RSA;
1da177e4
LT		 1154 break;
1155 }
1156 }
1157 }
1158#endif
21c614a7 1159
0acf519f 1160 serial_out(up, UART_LCR, save_lcr);
1da177e4 1161
dfe42443 1162 if (up->capabilities != uart_config[port->type].flags) {
1da177e4
LT		 1163 printk(KERN_WARNING
1164 "ttyS%d: detected caps %08x should be %08x\n",
dfe42443
PG		 1165 serial_index(port), up->capabilities,
1166 uart_config[port->type].flags);
1da177e4
LT		 1167 }
1168
dfe42443
PG		 1169 port->fifosize = uart_config[up->port.type].fifo_size;
1170 up->capabilities = uart_config[port->type].flags;
1171 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1da177e4 1172
dfe42443 1173 if (port->type == PORT_UNKNOWN)
1da177e4
LT		 1174 goto out;
1175
1176 /*
1177 * Reset the UART.
1178 */
1179#ifdef CONFIG_SERIAL_8250_RSA
dfe42443 1180 if (port->type == PORT_RSA)
0acf519f 1181 serial_out(up, UART_RSA_FRR, 0);
1da177e4 1182#endif
0acf519f 1183 serial_out(up, UART_MCR, save_mcr);
1da177e4 1184 serial8250_clear_fifos(up);
40b36daa 1185 serial_in(up, UART_RX);
5c8c755c 1186 if (up->capabilities & UART_CAP_UUE)
0acf519f 1187 serial_out(up, UART_IER, UART_IER_UUE);
5c8c755c 1188 else
0acf519f 1189 serial_out(up, UART_IER, 0);
1da177e4 1190
bd71c182 1191 out:
dfe42443
PG		 1192 spin_unlock_irqrestore(&port->lock, flags);
1193 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1da177e4
LT		 1194}
1195
1196static void autoconfig_irq(struct uart_8250_port *up)
1197{
dfe42443 1198 struct uart_port *port = &up->port;
1da177e4
LT		 1199 unsigned char save_mcr, save_ier;
1200 unsigned char save_ICP = 0;
1201 unsigned int ICP = 0;
1202 unsigned long irqs;
1203 int irq;
1204
dfe42443
PG		 1205 if (port->flags & UPF_FOURPORT) {
1206 ICP = (port->iobase & 0xfe0) | 0x1f;
1da177e4
LT		 1207 save_ICP = inb_p(ICP);
1208 outb_p(0x80, ICP);
0d263a26 1209 inb_p(ICP);
1da177e4
LT		 1210 }
1211
1212 /* forget possible initially masked and pending IRQ */
1213 probe_irq_off(probe_irq_on());
0acf519f
PG		 1214 save_mcr = serial_in(up, UART_MCR);
1215 save_ier = serial_in(up, UART_IER);
1216 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1217
1da177e4 1218 irqs = probe_irq_on();
0acf519f 1219 serial_out(up, UART_MCR, 0);
6f803cd0 1220 udelay(10);
dfe42443 1221 if (port->flags & UPF_FOURPORT) {
0acf519f 1222 serial_out(up, UART_MCR,
1da177e4
LT		 1223 UART_MCR_DTR | UART_MCR_RTS);
1224 } else {
0acf519f 1225 serial_out(up, UART_MCR,
1da177e4
LT		 1226 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1227 }
0acf519f 1228 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
0d263a26
PG		 1229 serial_in(up, UART_LSR);
1230 serial_in(up, UART_RX);
1231 serial_in(up, UART_IIR);
1232 serial_in(up, UART_MSR);
0acf519f 1233 serial_out(up, UART_TX, 0xFF);
6f803cd0 1234 udelay(20);
1da177e4
LT		 1235 irq = probe_irq_off(irqs);
1236
0acf519f
PG		 1237 serial_out(up, UART_MCR, save_mcr);
1238 serial_out(up, UART_IER, save_ier);
1da177e4 1239
dfe42443 1240 if (port->flags & UPF_FOURPORT)
1da177e4
LT		 1241 outb_p(save_ICP, ICP);
1242
dfe42443 1243 port->irq = (irq > 0) ? irq : 0;
1da177e4
LT		 1244}
1245
e763b90c
RK		 1246static inline void __stop_tx(struct uart_8250_port *p)
1247{
1248 if (p->ier & UART_IER_THRI) {
1249 p->ier &= ~UART_IER_THRI;
1250 serial_out(p, UART_IER, p->ier);
1251 }
1252}
1253
b129a8cc 1254static void serial8250_stop_tx(struct uart_port *port)
1da177e4 1255{
49d5741b
JI		 1256 struct uart_8250_port *up =
1257 container_of(port, struct uart_8250_port, port);
1da177e4 1258
e763b90c 1259 __stop_tx(up);
1da177e4
LT		 1260
1261 /*
e763b90c 1262 * We really want to stop the transmitter from sending.
1da177e4 1263 */
dfe42443 1264 if (port->type == PORT_16C950) {
1da177e4
LT		 1265 up->acr |= UART_ACR_TXDIS;
1266 serial_icr_write(up, UART_ACR, up->acr);
1267 }
1268}
1269
b129a8cc 1270static void serial8250_start_tx(struct uart_port *port)
1da177e4 1271{
49d5741b
JI		 1272 struct uart_8250_port *up =
1273 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1274
1275 if (!(up->ier & UART_IER_THRI)) {
1276 up->ier |= UART_IER_THRI;
4fd996a1 1277 serial_port_out(port, UART_IER, up->ier);
55d3b282 1278
67f7654e 1279 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1280 unsigned char lsr;
55d3b282 1281 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1282 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
dfe42443 1283 if ((port->type == PORT_RM9000) ?
68cb4f8e
IJ		 1284 (lsr & UART_LSR_THRE) :
1285 (lsr & UART_LSR_TEMT))
3986fb2b 1286 serial8250_tx_chars(up);
55d3b282 1287 }
1da177e4 1288 }
e763b90c 1289
1da177e4 1290 /*
e763b90c 1291 * Re-enable the transmitter if we disabled it.
1da177e4 1292 */
dfe42443 1293 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1294 up->acr &= ~UART_ACR_TXDIS;
1295 serial_icr_write(up, UART_ACR, up->acr);
1296 }
1297}
1298
1299static void serial8250_stop_rx(struct uart_port *port)
1300{
49d5741b
JI		 1301 struct uart_8250_port *up =
1302 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1303
1304 up->ier &= ~UART_IER_RLSI;
1305 up->port.read_status_mask &= ~UART_LSR_DR;
4fd996a1 1306 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 1307}
1308
1309static void serial8250_enable_ms(struct uart_port *port)
1310{
49d5741b
JI		 1311 struct uart_8250_port *up =
1312 container_of(port, struct uart_8250_port, port);
1da177e4 1313
21c614a7
PA		 1314 /* no MSR capabilities */
1315 if (up->bugs & UART_BUG_NOMSR)
1316 return;
1317
1da177e4 1318 up->ier |= UART_IER_MSI;
4fd996a1 1319 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 1320}
1321
0690f41f 1322/*
3986fb2b 1323 * serial8250_rx_chars: processes according to the passed in LSR
0690f41f
PG		 1324 * value, and returns the remaining LSR bits not handled
1325 * by this Rx routine.
1326 */
3986fb2b
PG		 1327unsigned char
1328serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1da177e4 1329{
dfe42443
PG		 1330 struct uart_port *port = &up->port;
1331 struct tty_struct *tty = port->state->port.tty;
0690f41f 1332 unsigned char ch;
1da177e4
LT		 1333 int max_count = 256;
1334 char flag;
1335
1336 do {
7500b1f6 1337 if (likely(lsr & UART_LSR_DR))
0acf519f 1338 ch = serial_in(up, UART_RX);
7500b1f6
AR		 1339 else
1340 /*
1341 * Intel 82571 has a Serial Over Lan device that will
1342 * set UART_LSR_BI without setting UART_LSR_DR when
1343 * it receives a break. To avoid reading from the
1344 * receive buffer without UART_LSR_DR bit set, we
1345 * just force the read character to be 0
1346 */
1347 ch = 0;
1348
1da177e4 1349 flag = TTY_NORMAL;
dfe42443 1350 port->icount.rx++;
1da177e4 1351
ad4c2aa6
CM		 1352 lsr |= up->lsr_saved_flags;
1353 up->lsr_saved_flags = 0;
1da177e4 1354
ad4c2aa6 1355 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1356 if (lsr & UART_LSR_BI) {
1357 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
dfe42443 1358 port->icount.brk++;
1da177e4
LT		 1359 /*
1360 * We do the SysRQ and SAK checking
1361 * here because otherwise the break
1362 * may get masked by ignore_status_mask
1363 * or read_status_mask.
1364 */
dfe42443 1365 if (uart_handle_break(port))
1da177e4
LT		 1366 goto ignore_char;
1367 } else if (lsr & UART_LSR_PE)
dfe42443 1368 port->icount.parity++;
1da177e4 1369 else if (lsr & UART_LSR_FE)
dfe42443 1370 port->icount.frame++;
1da177e4 1371 if (lsr & UART_LSR_OE)
dfe42443 1372 port->icount.overrun++;
1da177e4
LT		 1373
1374 /*
23907eb8 1375 * Mask off conditions which should be ignored.
1da177e4 1376 */
dfe42443 1377 lsr &= port->read_status_mask;
1da177e4
LT		 1378
1379 if (lsr & UART_LSR_BI) {
1380 DEBUG_INTR("handling break....");
1381 flag = TTY_BREAK;
1382 } else if (lsr & UART_LSR_PE)
1383 flag = TTY_PARITY;
1384 else if (lsr & UART_LSR_FE)
1385 flag = TTY_FRAME;
1386 }
dfe42443 1387 if (uart_handle_sysrq_char(port, ch))
1da177e4 1388 goto ignore_char;
05ab3014 1389
dfe42443 1390 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
05ab3014 1391
6f803cd0 1392ignore_char:
0acf519f 1393 lsr = serial_in(up, UART_LSR);
7500b1f6 1394 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
dfe42443 1395 spin_unlock(&port->lock);
1da177e4 1396 tty_flip_buffer_push(tty);
dfe42443 1397 spin_lock(&port->lock);
0690f41f 1398 return lsr;
1da177e4 1399}
3986fb2b 1400EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1da177e4 1401
3986fb2b 1402void serial8250_tx_chars(struct uart_8250_port *up)
1da177e4 1403{
dfe42443
PG		 1404 struct uart_port *port = &up->port;
1405 struct circ_buf *xmit = &port->state->xmit;
1da177e4
LT		 1406 int count;
1407
dfe42443
PG		 1408 if (port->x_char) {
1409 serial_out(up, UART_TX, port->x_char);
1410 port->icount.tx++;
1411 port->x_char = 0;
1da177e4
LT		 1412 return;
1413 }
dfe42443
PG		 1414 if (uart_tx_stopped(port)) {
1415 serial8250_stop_tx(port);
b129a8cc
RK		 1416 return;
1417 }
1418 if (uart_circ_empty(xmit)) {
e763b90c 1419 __stop_tx(up);
1da177e4
LT		 1420 return;
1421 }
1422
1423 count = up->tx_loadsz;
1424 do {
1425 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1426 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
dfe42443 1427 port->icount.tx++;
1da177e4
LT		 1428 if (uart_circ_empty(xmit))
1429 break;
1430 } while (--count > 0);
1431
1432 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
dfe42443 1433 uart_write_wakeup(port);
1da177e4
LT		 1434
1435 DEBUG_INTR("THRE...");
1436
1437 if (uart_circ_empty(xmit))
e763b90c 1438 __stop_tx(up);
1da177e4 1439}
3986fb2b 1440EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1da177e4 1441
3986fb2b 1442unsigned int serial8250_modem_status(struct uart_8250_port *up)
1da177e4 1443{
dfe42443 1444 struct uart_port *port = &up->port;
2af7cd68
RK		 1445 unsigned int status = serial_in(up, UART_MSR);
1446
ad4c2aa6
CM		 1447 status |= up->msr_saved_flags;
1448 up->msr_saved_flags = 0;
fdc30b3d 1449 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
dfe42443 1450 port->state != NULL) {
2af7cd68 1451 if (status & UART_MSR_TERI)
dfe42443 1452 port->icount.rng++;
2af7cd68 1453 if (status & UART_MSR_DDSR)
dfe42443 1454 port->icount.dsr++;
2af7cd68 1455 if (status & UART_MSR_DDCD)
dfe42443 1456 uart_handle_dcd_change(port, status & UART_MSR_DCD);
2af7cd68 1457 if (status & UART_MSR_DCTS)
dfe42443 1458 uart_handle_cts_change(port, status & UART_MSR_CTS);
2af7cd68 1459
dfe42443 1460 wake_up_interruptible(&port->state->port.delta_msr_wait);
2af7cd68 1461 }
1da177e4 1462
2af7cd68 1463 return status;
1da177e4 1464}
3986fb2b 1465EXPORT_SYMBOL_GPL(serial8250_modem_status);
1da177e4
LT		 1466
1467/*
1468 * This handles the interrupt from one port.
1469 */
86b21199 1470int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1da177e4 1471{
0690f41f 1472 unsigned char status;
4bf3631c 1473 unsigned long flags;
86b21199
PG		 1474 struct uart_8250_port *up =
1475 container_of(port, struct uart_8250_port, port);
1476
1477 if (iir & UART_IIR_NO_INT)
1478 return 0;
45e24601 1479
dfe42443 1480 spin_lock_irqsave(&port->lock, flags);
45e24601 1481
4fd996a1 1482 status = serial_port_in(port, UART_LSR);
1da177e4
LT		 1483
1484 DEBUG_INTR("status = %x...", status);
1485
7500b1f6 1486 if (status & (UART_LSR_DR | UART_LSR_BI))
3986fb2b
PG		 1487 status = serial8250_rx_chars(up, status);
1488 serial8250_modem_status(up);
1da177e4 1489 if (status & UART_LSR_THRE)
3986fb2b 1490 serial8250_tx_chars(up);
45e24601 1491
dfe42443 1492 spin_unlock_irqrestore(&port->lock, flags);
86b21199 1493 return 1;
583d28e9 1494}
c7a1bdc5 1495EXPORT_SYMBOL_GPL(serial8250_handle_irq);
583d28e9
JI		 1496
1497static int serial8250_default_handle_irq(struct uart_port *port)
1498{
4fd996a1 1499 unsigned int iir = serial_port_in(port, UART_IIR);
583d28e9
JI		 1500
1501 return serial8250_handle_irq(port, iir);
1502}
1503
1da177e4
LT		 1504/*
1505 * This is the serial driver's interrupt routine.
1506 *
1507 * Arjan thinks the old way was overly complex, so it got simplified.
1508 * Alan disagrees, saying that need the complexity to handle the weird
1509 * nature of ISA shared interrupts. (This is a special exception.)
1510 *
1511 * In order to handle ISA shared interrupts properly, we need to check
1512 * that all ports have been serviced, and therefore the ISA interrupt
1513 * line has been de-asserted.
1514 *
1515 * This means we need to loop through all ports. checking that they
1516 * don't have an interrupt pending.
1517 */
7d12e780 1518static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1519{
1520 struct irq_info *i = dev_id;
1521 struct list_head *l, *end = NULL;
1522 int pass_counter = 0, handled = 0;
1523
1524 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1525
1526 spin_lock(&i->lock);
1527
1528 l = i->head;
1529 do {
1530 struct uart_8250_port *up;
583d28e9 1531 struct uart_port *port;
1da177e4
LT		 1532
1533 up = list_entry(l, struct uart_8250_port, list);
583d28e9 1534 port = &up->port;
1da177e4 1535
49b532f9 1536 if (port->handle_irq(port)) {
1da177e4 1537 handled = 1;
1da177e4
LT		 1538 end = NULL;
1539 } else if (end == NULL)
1540 end = l;
1541
1542 l = l->next;
1543
1544 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1545 /* If we hit this, we're dead. */
cd3ecad1
DD		 1546 printk_ratelimited(KERN_ERR
1547 "serial8250: too much work for irq%d\n", irq);
1da177e4
LT		 1548 break;
1549 }
1550 } while (l != end);
1551
1552 spin_unlock(&i->lock);
1553
1554 DEBUG_INTR("end.\n");
1555
1556 return IRQ_RETVAL(handled);
1557}
1558
1559/*
1560 * To support ISA shared interrupts, we need to have one interrupt
1561 * handler that ensures that the IRQ line has been deasserted
1562 * before returning. Failing to do this will result in the IRQ
1563 * line being stuck active, and, since ISA irqs are edge triggered,
1564 * no more IRQs will be seen.
1565 */
1566static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1567{
1568 spin_lock_irq(&i->lock);
1569
1570 if (!list_empty(i->head)) {
1571 if (i->head == &up->list)
1572 i->head = i->head->next;
1573 list_del(&up->list);
1574 } else {
1575 BUG_ON(i->head != &up->list);
1576 i->head = NULL;
1577 }
1da177e4 1578 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1579 /* List empty so throw away the hash node */
1580 if (i->head == NULL) {
1581 hlist_del(&i->node);
1582 kfree(i);
1583 }
1da177e4
LT		 1584}
1585
1586static int serial_link_irq_chain(struct uart_8250_port *up)
1587{
25db8ad5
AC		 1588 struct hlist_head *h;
1589 struct hlist_node *n;
1590 struct irq_info *i;
40663cc7 1591 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1592
25db8ad5
AC		 1593 mutex_lock(&hash_mutex);
1594
1595 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1596
1597 hlist_for_each(n, h) {
1598 i = hlist_entry(n, struct irq_info, node);
1599 if (i->irq == up->port.irq)
1600 break;
1601 }
1602
1603 if (n == NULL) {
1604 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1605 if (i == NULL) {
1606 mutex_unlock(&hash_mutex);
1607 return -ENOMEM;
1608 }
1609 spin_lock_init(&i->lock);
1610 i->irq = up->port.irq;
1611 hlist_add_head(&i->node, h);
1612 }
1613 mutex_unlock(&hash_mutex);
1614
1da177e4
LT		 1615 spin_lock_irq(&i->lock);
1616
1617 if (i->head) {
1618 list_add(&up->list, i->head);
1619 spin_unlock_irq(&i->lock);
1620
1621 ret = 0;
1622 } else {
1623 INIT_LIST_HEAD(&up->list);
1624 i->head = &up->list;
1625 spin_unlock_irq(&i->lock);
1c2f0493 1626 irq_flags |= up->port.irqflags;
1da177e4
LT		 1627 ret = request_irq(up->port.irq, serial8250_interrupt,
1628 irq_flags, "serial", i);
1629 if (ret < 0)
1630 serial_do_unlink(i, up);
1631 }
1632
1633 return ret;
1634}
1635
1636static void serial_unlink_irq_chain(struct uart_8250_port *up)
1637{
25db8ad5
AC		 1638 struct irq_info *i;
1639 struct hlist_node *n;
1640 struct hlist_head *h;
1da177e4 1641
25db8ad5
AC		 1642 mutex_lock(&hash_mutex);
1643
1644 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1645
1646 hlist_for_each(n, h) {
1647 i = hlist_entry(n, struct irq_info, node);
1648 if (i->irq == up->port.irq)
1649 break;
1650 }
1651
1652 BUG_ON(n == NULL);
1da177e4
LT		 1653 BUG_ON(i->head == NULL);
1654
1655 if (list_empty(i->head))
1656 free_irq(up->port.irq, i);
1657
1658 serial_do_unlink(i, up);
25db8ad5 1659 mutex_unlock(&hash_mutex);
1da177e4
LT		 1660}
1661
1662/*
1663 * This function is used to handle ports that do not have an
1664 * interrupt. This doesn't work very well for 16450's, but gives
1665 * barely passable results for a 16550A. (Although at the expense
1666 * of much CPU overhead).
1667 */
1668static void serial8250_timeout(unsigned long data)
1669{
1670 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4 1671
a0431476 1672 up->port.handle_irq(&up->port);
54381067 1673 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
40b36daa
AW		 1674}
1675
1676static void serial8250_backup_timeout(unsigned long data)
1677{
1678 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1679 unsigned int iir, ier = 0, lsr;
1680 unsigned long flags;
40b36daa 1681
dbb3b1ca
AC		 1682 spin_lock_irqsave(&up->port.lock, flags);
1683
40b36daa
AW		 1684 /*
1685 * Must disable interrupts or else we risk racing with the interrupt
1686 * based handler.
1687 */
d4e33fac 1688 if (up->port.irq) {
40b36daa
AW		 1689 ier = serial_in(up, UART_IER);
1690 serial_out(up, UART_IER, 0);
1691 }
1da177e4 1692
40b36daa
AW		 1693 iir = serial_in(up, UART_IIR);
1694
1695 /*
1696 * This should be a safe test for anyone who doesn't trust the
1697 * IIR bits on their UART, but it's specifically designed for
1698 * the "Diva" UART used on the management processor on many HP
1699 * ia64 and parisc boxes.
1700 */
ad4c2aa6
CM		 1701 lsr = serial_in(up, UART_LSR);
1702 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
40b36daa 1703 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1704 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1705 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1706 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1707 iir |= UART_IIR_THRI;
1708 }
1709
1710 if (!(iir & UART_IIR_NO_INT))
3986fb2b 1711 serial8250_tx_chars(up);
40b36daa 1712
d4e33fac 1713 if (up->port.irq)
40b36daa
AW		 1714 serial_out(up, UART_IER, ier);
1715
dbb3b1ca
AC		 1716 spin_unlock_irqrestore(&up->port.lock, flags);
1717
40b36daa 1718 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0 1719 mod_timer(&up->timer,
54381067 1720 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1da177e4
LT		 1721}
1722
1723static unsigned int serial8250_tx_empty(struct uart_port *port)
1724{
49d5741b
JI		 1725 struct uart_8250_port *up =
1726 container_of(port, struct uart_8250_port, port);
1da177e4 1727 unsigned long flags;
ad4c2aa6 1728 unsigned int lsr;
1da177e4 1729
dfe42443 1730 spin_lock_irqsave(&port->lock, flags);
4fd996a1 1731 lsr = serial_port_in(port, UART_LSR);
ad4c2aa6 1732 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
dfe42443 1733 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 1734
bca47613 1735 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1736}
1737
1738static unsigned int serial8250_get_mctrl(struct uart_port *port)
1739{
49d5741b
JI		 1740 struct uart_8250_port *up =
1741 container_of(port, struct uart_8250_port, port);
2af7cd68 1742 unsigned int status;
1da177e4
LT		 1743 unsigned int ret;
1744
3986fb2b 1745 status = serial8250_modem_status(up);
1da177e4
LT		 1746
1747 ret = 0;
1748 if (status & UART_MSR_DCD)
1749 ret |= TIOCM_CAR;
1750 if (status & UART_MSR_RI)
1751 ret |= TIOCM_RNG;
1752 if (status & UART_MSR_DSR)
1753 ret |= TIOCM_DSR;
1754 if (status & UART_MSR_CTS)
1755 ret |= TIOCM_CTS;
1756 return ret;
1757}
1758
1759static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1760{
49d5741b
JI		 1761 struct uart_8250_port *up =
1762 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1763 unsigned char mcr = 0;
1764
1765 if (mctrl & TIOCM_RTS)
1766 mcr |= UART_MCR_RTS;
1767 if (mctrl & TIOCM_DTR)
1768 mcr |= UART_MCR_DTR;
1769 if (mctrl & TIOCM_OUT1)
1770 mcr |= UART_MCR_OUT1;
1771 if (mctrl & TIOCM_OUT2)
1772 mcr |= UART_MCR_OUT2;
1773 if (mctrl & TIOCM_LOOP)
1774 mcr |= UART_MCR_LOOP;
1775
1776 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1777
4fd996a1 1778 serial_port_out(port, UART_MCR, mcr);
1da177e4
LT		 1779}
1780
1781static void serial8250_break_ctl(struct uart_port *port, int break_state)
1782{
49d5741b
JI		 1783 struct uart_8250_port *up =
1784 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1785 unsigned long flags;
1786
dfe42443 1787 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 1788 if (break_state == -1)
1789 up->lcr |= UART_LCR_SBC;
1790 else
1791 up->lcr &= ~UART_LCR_SBC;
4fd996a1 1792 serial_port_out(port, UART_LCR, up->lcr);
dfe42443 1793 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1794}
1795
40b36daa
AW		 1796/*
1797 * Wait for transmitter & holding register to empty
1798 */
b5d674ab 1799static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1800{
1801 unsigned int status, tmout = 10000;
1802
1803 /* Wait up to 10ms for the character(s) to be sent. */
97d303b7 1804 for (;;) {
40b36daa
AW		 1805 status = serial_in(up, UART_LSR);
1806
ad4c2aa6 1807 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa 1808
97d303b7
DD		 1809 if ((status & bits) == bits)
1810 break;
40b36daa
AW		 1811 if (--tmout == 0)
1812 break;
1813 udelay(1);
97d303b7 1814 }
40b36daa
AW		 1815
1816 /* Wait up to 1s for flow control if necessary */
1817 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1818 unsigned int tmout;
1819 for (tmout = 1000000; tmout; tmout--) {
1820 unsigned int msr = serial_in(up, UART_MSR);
1821 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1822 if (msr & UART_MSR_CTS)
1823 break;
40b36daa
AW		 1824 udelay(1);
1825 touch_nmi_watchdog();
1826 }
1827 }
1828}
1829
f2d937f3
JW		 1830#ifdef CONFIG_CONSOLE_POLL
1831/*
1832 * Console polling routines for writing and reading from the uart while
1833 * in an interrupt or debug context.
1834 */
1835
1836static int serial8250_get_poll_char(struct uart_port *port)
1837{
4fd996a1 1838 unsigned char lsr = serial_port_in(port, UART_LSR);
f2d937f3 1839
f5316b4a
JW		 1840 if (!(lsr & UART_LSR_DR))
1841 return NO_POLL_CHAR;
f2d937f3 1842
4fd996a1 1843 return serial_port_in(port, UART_RX);
f2d937f3
JW		 1844}
1845
1846
1847static void serial8250_put_poll_char(struct uart_port *port,
1848 unsigned char c)
1849{
1850 unsigned int ier;
49d5741b
JI		 1851 struct uart_8250_port *up =
1852 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1853
1854 /*
1855 * First save the IER then disable the interrupts
1856 */
4fd996a1 1857 ier = serial_port_in(port, UART_IER);
f2d937f3 1858 if (up->capabilities & UART_CAP_UUE)
4fd996a1 1859 serial_port_out(port, UART_IER, UART_IER_UUE);
f2d937f3 1860 else
4fd996a1 1861 serial_port_out(port, UART_IER, 0);
f2d937f3
JW		 1862
1863 wait_for_xmitr(up, BOTH_EMPTY);
1864 /*
1865 * Send the character out.
1866 * If a LF, also do CR...
1867 */
4fd996a1 1868 serial_port_out(port, UART_TX, c);
f2d937f3
JW		 1869 if (c == 10) {
1870 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 1871 serial_port_out(port, UART_TX, 13);
f2d937f3
JW		 1872 }
1873
1874 /*
1875 * Finally, wait for transmitter to become empty
1876 * and restore the IER
1877 */
1878 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 1879 serial_port_out(port, UART_IER, ier);
f2d937f3
JW		 1880}
1881
1882#endif /* CONFIG_CONSOLE_POLL */
1883
1da177e4
LT		 1884static int serial8250_startup(struct uart_port *port)
1885{
49d5741b
JI		 1886 struct uart_8250_port *up =
1887 container_of(port, struct uart_8250_port, port);
1da177e4 1888 unsigned long flags;
55d3b282 1889 unsigned char lsr, iir;
1da177e4
LT		 1890 int retval;
1891
dfe42443 1892 port->fifosize = uart_config[up->port.type].fifo_size;
e4f05af1 1893 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1da177e4
LT		 1894 up->capabilities = uart_config[up->port.type].flags;
1895 up->mcr = 0;
1896
dfe42443 1897 if (port->iotype != up->cur_iotype)
b8e7e40a
AC		 1898 set_io_from_upio(port);
1899
dfe42443 1900 if (port->type == PORT_16C950) {
1da177e4
LT		 1901 /* Wake up and initialize UART */
1902 up->acr = 0;
4fd996a1
PG		 1903 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1904 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1905 serial_port_out(port, UART_IER, 0);
1906 serial_port_out(port, UART_LCR, 0);
1da177e4 1907 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
4fd996a1
PG		 1908 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1909 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1910 serial_port_out(port, UART_LCR, 0);
1da177e4
LT		 1911 }
1912
1913#ifdef CONFIG_SERIAL_8250_RSA
1914 /*
1915 * If this is an RSA port, see if we can kick it up to the
1916 * higher speed clock.
1917 */
1918 enable_rsa(up);
1919#endif
1920
1921 /*
1922 * Clear the FIFO buffers and disable them.
7f927fcc 1923 * (they will be reenabled in set_termios())
1da177e4
LT		 1924 */
1925 serial8250_clear_fifos(up);
1926
1927 /*
1928 * Clear the interrupt registers.
1929 */
4fd996a1
PG		 1930 serial_port_in(port, UART_LSR);
1931 serial_port_in(port, UART_RX);
1932 serial_port_in(port, UART_IIR);
1933 serial_port_in(port, UART_MSR);
1da177e4
LT		 1934
1935 /*
1936 * At this point, there's no way the LSR could still be 0xff;
1937 * if it is, then bail out, because there's likely no UART
1938 * here.
1939 */
dfe42443 1940 if (!(port->flags & UPF_BUGGY_UART) &&
4fd996a1 1941 (serial_port_in(port, UART_LSR) == 0xff)) {
7808a4c4 1942 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
dfe42443 1943 serial_index(port));
1da177e4
LT		 1944 return -ENODEV;
1945 }
1946
1947 /*
1948 * For a XR16C850, we need to set the trigger levels
1949 */
dfe42443 1950 if (port->type == PORT_16850) {
1da177e4
LT		 1951 unsigned char fctr;
1952
0acf519f 1953 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4 1954
0acf519f 1955 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
4fd996a1
PG		 1956 serial_port_out(port, UART_FCTR,
1957 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1958 serial_port_out(port, UART_TRG, UART_TRG_96);
1959 serial_port_out(port, UART_FCTR,
1960 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1961 serial_port_out(port, UART_TRG, UART_TRG_96);
1da177e4 1962
4fd996a1 1963 serial_port_out(port, UART_LCR, 0);
1da177e4
LT		 1964 }
1965
dfe42443 1966 if (port->irq) {
01c194d9 1967 unsigned char iir1;
40b36daa
AW		 1968 /*
1969 * Test for UARTs that do not reassert THRE when the
1970 * transmitter is idle and the interrupt has already
1971 * been cleared. Real 16550s should always reassert
1972 * this interrupt whenever the transmitter is idle and
1973 * the interrupt is enabled. Delays are necessary to
1974 * allow register changes to become visible.
1975 */
dfe42443 1976 spin_lock_irqsave(&port->lock, flags);
1c2f0493 1977 if (up->port.irqflags & IRQF_SHARED)
dfe42443 1978 disable_irq_nosync(port->irq);
40b36daa
AW		 1979
1980 wait_for_xmitr(up, UART_LSR_THRE);
55e4016d 1981 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
40b36daa 1982 udelay(1); /* allow THRE to set */
4fd996a1
PG		 1983 iir1 = serial_port_in(port, UART_IIR);
1984 serial_port_out(port, UART_IER, 0);
55e4016d 1985 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
40b36daa 1986 udelay(1); /* allow a working UART time to re-assert THRE */
4fd996a1
PG		 1987 iir = serial_port_in(port, UART_IIR);
1988 serial_port_out(port, UART_IER, 0);
40b36daa 1989
dfe42443
PG		 1990 if (port->irqflags & IRQF_SHARED)
1991 enable_irq(port->irq);
1992 spin_unlock_irqrestore(&port->lock, flags);
40b36daa
AW		 1993
1994 /*
bc02d15a
DW		 1995 * If the interrupt is not reasserted, or we otherwise
1996 * don't trust the iir, setup a timer to kick the UART
1997 * on a regular basis.
40b36daa 1998 */
bc02d15a
DW		 1999 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2000 up->port.flags & UPF_BUG_THRE) {
363f66fe 2001 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2002 pr_debug("ttyS%d - using backup timer\n",
2003 serial_index(port));
40b36daa
AW		 2004 }
2005 }
2006
363f66fe
WN		 2007 /*
2008 * The above check will only give an accurate result the first time
2009 * the port is opened so this value needs to be preserved.
2010 */
2011 if (up->bugs & UART_BUG_THRE) {
2012 up->timer.function = serial8250_backup_timeout;
2013 up->timer.data = (unsigned long)up;
2014 mod_timer(&up->timer, jiffies +
54381067 2015 uart_poll_timeout(port) + HZ / 5);
363f66fe
WN		 2016 }
2017
1da177e4
LT		 2018 /*
2019 * If the "interrupt" for this port doesn't correspond with any
2020 * hardware interrupt, we use a timer-based system. The original
2021 * driver used to do this with IRQ0.
2022 */
dfe42443 2023 if (!port->irq) {
1da177e4 2024 up->timer.data = (unsigned long)up;
54381067 2025 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
1da177e4
LT		 2026 } else {
2027 retval = serial_link_irq_chain(up);
2028 if (retval)
2029 return retval;
2030 }
2031
2032 /*
2033 * Now, initialize the UART
2034 */
4fd996a1 2035 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
1da177e4 2036
dfe42443 2037 spin_lock_irqsave(&port->lock, flags);
1da177e4 2038 if (up->port.flags & UPF_FOURPORT) {
d4e33fac 2039 if (!up->port.irq)
1da177e4
LT		 2040 up->port.mctrl |= TIOCM_OUT1;
2041 } else
2042 /*
2043 * Most PC uarts need OUT2 raised to enable interrupts.
2044 */
dfe42443 2045 if (port->irq)
1da177e4
LT		 2046 up->port.mctrl |= TIOCM_OUT2;
2047
dfe42443 2048 serial8250_set_mctrl(port, port->mctrl);
55d3b282 2049
b6adea33
MCC		 2050 /* Serial over Lan (SoL) hack:
2051 Intel 8257x Gigabit ethernet chips have a
2052 16550 emulation, to be used for Serial Over Lan.
2053 Those chips take a longer time than a normal
2054 serial device to signalize that a transmission
2055 data was queued. Due to that, the above test generally
2056 fails. One solution would be to delay the reading of
2057 iir. However, this is not reliable, since the timeout
2058 is variable. So, let's just don't test if we receive
2059 TX irq. This way, we'll never enable UART_BUG_TXEN.
2060 */
d41a4b51 2061 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2062 goto dont_test_tx_en;
2063
55d3b282
RK		 2064 /*
2065 * Do a quick test to see if we receive an
2066 * interrupt when we enable the TX irq.
2067 */
4fd996a1
PG		 2068 serial_port_out(port, UART_IER, UART_IER_THRI);
2069 lsr = serial_port_in(port, UART_LSR);
2070 iir = serial_port_in(port, UART_IIR);
2071 serial_port_out(port, UART_IER, 0);
55d3b282
RK		 2072
2073 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2074 if (!(up->bugs & UART_BUG_TXEN)) {
2075 up->bugs |= UART_BUG_TXEN;
55d3b282 2076 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2077 serial_index(port));
55d3b282
RK		 2078 }
2079 } else {
67f7654e 2080 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2081 }
2082
b6adea33 2083dont_test_tx_en:
dfe42443 2084 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 2085
ad4c2aa6
CM		 2086 /*
2087 * Clear the interrupt registers again for luck, and clear the
2088 * saved flags to avoid getting false values from polling
2089 * routines or the previous session.
2090 */
4fd996a1
PG		 2091 serial_port_in(port, UART_LSR);
2092 serial_port_in(port, UART_RX);
2093 serial_port_in(port, UART_IIR);
2094 serial_port_in(port, UART_MSR);
ad4c2aa6
CM		 2095 up->lsr_saved_flags = 0;
2096 up->msr_saved_flags = 0;
2097
1da177e4
LT		 2098 /*
2099 * Finally, enable interrupts. Note: Modem status interrupts
2100 * are set via set_termios(), which will be occurring imminently
2101 * anyway, so we don't enable them here.
2102 */
2103 up->ier = UART_IER_RLSI | UART_IER_RDI;
4fd996a1 2104 serial_port_out(port, UART_IER, up->ier);
1da177e4 2105
dfe42443 2106 if (port->flags & UPF_FOURPORT) {
1da177e4
LT		 2107 unsigned int icp;
2108 /*
2109 * Enable interrupts on the AST Fourport board
2110 */
dfe42443 2111 icp = (port->iobase & 0xfe0) | 0x01f;
1da177e4 2112 outb_p(0x80, icp);
0d263a26 2113 inb_p(icp);
1da177e4
LT		 2114 }
2115
1da177e4
LT		 2116 return 0;
2117}
2118
2119static void serial8250_shutdown(struct uart_port *port)
2120{
49d5741b
JI		 2121 struct uart_8250_port *up =
2122 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2123 unsigned long flags;
2124
2125 /*
2126 * Disable interrupts from this port
2127 */
2128 up->ier = 0;
4fd996a1 2129 serial_port_out(port, UART_IER, 0);
1da177e4 2130
dfe42443
PG		 2131 spin_lock_irqsave(&port->lock, flags);
2132 if (port->flags & UPF_FOURPORT) {
1da177e4 2133 /* reset interrupts on the AST Fourport board */
dfe42443
PG		 2134 inb((port->iobase & 0xfe0) | 0x1f);
2135 port->mctrl |= TIOCM_OUT1;
1da177e4 2136 } else
dfe42443 2137 port->mctrl &= ~TIOCM_OUT2;
1da177e4 2138
dfe42443
PG		 2139 serial8250_set_mctrl(port, port->mctrl);
2140 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 2141
2142 /*
2143 * Disable break condition and FIFOs
2144 */
4fd996a1
PG		 2145 serial_port_out(port, UART_LCR,
2146 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
1da177e4
LT		 2147 serial8250_clear_fifos(up);
2148
2149#ifdef CONFIG_SERIAL_8250_RSA
2150 /*
2151 * Reset the RSA board back to 115kbps compat mode.
2152 */
2153 disable_rsa(up);
2154#endif
2155
2156 /*
2157 * Read data port to reset things, and then unlink from
2158 * the IRQ chain.
2159 */
4fd996a1 2160 serial_port_in(port, UART_RX);
1da177e4 2161
40b36daa
AW		 2162 del_timer_sync(&up->timer);
2163 up->timer.function = serial8250_timeout;
dfe42443 2164 if (port->irq)
1da177e4
LT		 2165 serial_unlink_irq_chain(up);
2166}
2167
2168static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2169{
2170 unsigned int quot;
2171
2172 /*
2173 * Handle magic divisors for baud rates above baud_base on
2174 * SMSC SuperIO chips.
2175 */
2176 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2177 baud == (port->uartclk/4))
2178 quot = 0x8001;
2179 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2180 baud == (port->uartclk/8))
2181 quot = 0x8002;
2182 else
2183 quot = uart_get_divisor(port, baud);
2184
2185 return quot;
2186}
2187
235dae5d
PL		 2188void
2189serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2190 struct ktermios *old)
1da177e4 2191{
49d5741b
JI		 2192 struct uart_8250_port *up =
2193 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2194 unsigned char cval, fcr = 0;
2195 unsigned long flags;
2196 unsigned int baud, quot;
2197
2198 switch (termios->c_cflag & CSIZE) {
2199 case CS5:
0a8b80c5 2200 cval = UART_LCR_WLEN5;
1da177e4
LT		 2201 break;
2202 case CS6:
0a8b80c5 2203 cval = UART_LCR_WLEN6;
1da177e4
LT		 2204 break;
2205 case CS7:
0a8b80c5 2206 cval = UART_LCR_WLEN7;
1da177e4
LT		 2207 break;
2208 default:
2209 case CS8:
0a8b80c5 2210 cval = UART_LCR_WLEN8;
1da177e4
LT		 2211 break;
2212 }
2213
2214 if (termios->c_cflag & CSTOPB)
0a8b80c5 2215 cval |= UART_LCR_STOP;
1da177e4
LT		 2216 if (termios->c_cflag & PARENB)
2217 cval |= UART_LCR_PARITY;
2218 if (!(termios->c_cflag & PARODD))
2219 cval |= UART_LCR_EPAR;
2220#ifdef CMSPAR
2221 if (termios->c_cflag & CMSPAR)
2222 cval |= UART_LCR_SPAR;
2223#endif
2224
2225 /*
2226 * Ask the core to calculate the divisor for us.
2227 */
24d481ec
AV		 2228 baud = uart_get_baud_rate(port, termios, old,
2229 port->uartclk / 16 / 0xffff,
2230 port->uartclk / 16);
1da177e4
LT		 2231 quot = serial8250_get_divisor(port, baud);
2232
2233 /*
4ba5e35d 2234 * Oxford Semi 952 rev B workaround
1da177e4 2235 */
4ba5e35d 2236 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2237 quot++;
1da177e4 2238
dfe42443 2239 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
f9a9111b
CM		 2240 fcr = uart_config[port->type].fcr;
2241 if (baud < 2400) {
2242 fcr &= ~UART_FCR_TRIGGER_MASK;
2243 fcr |= UART_FCR_TRIGGER_1;
2244 }
1da177e4
LT		 2245 }
2246
2247 /*
2248 * MCR-based auto flow control. When AFE is enabled, RTS will be
2249 * deasserted when the receive FIFO contains more characters than
2250 * the trigger, or the MCR RTS bit is cleared. In the case where
2251 * the remote UART is not using CTS auto flow control, we must
2252 * have sufficient FIFO entries for the latency of the remote
2253 * UART to respond. IOW, at least 32 bytes of FIFO.
2254 */
dfe42443 2255 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
1da177e4
LT		 2256 up->mcr &= ~UART_MCR_AFE;
2257 if (termios->c_cflag & CRTSCTS)
2258 up->mcr |= UART_MCR_AFE;
2259 }
2260
2261 /*
2262 * Ok, we're now changing the port state. Do it with
2263 * interrupts disabled.
2264 */
dfe42443 2265 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 2266
2267 /*
2268 * Update the per-port timeout.
2269 */
2270 uart_update_timeout(port, termios->c_cflag, baud);
2271
dfe42443 2272 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1da177e4 2273 if (termios->c_iflag & INPCK)
dfe42443 2274 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1da177e4 2275 if (termios->c_iflag & (BRKINT | PARMRK))
dfe42443 2276 port->read_status_mask |= UART_LSR_BI;
1da177e4
LT		 2277
2278 /*
2279 * Characteres to ignore
2280 */
dfe42443 2281 port->ignore_status_mask = 0;
1da177e4 2282 if (termios->c_iflag & IGNPAR)
dfe42443 2283 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1da177e4 2284 if (termios->c_iflag & IGNBRK) {
dfe42443 2285 port->ignore_status_mask |= UART_LSR_BI;
1da177e4
LT		 2286 /*
2287 * If we're ignoring parity and break indicators,
2288 * ignore overruns too (for real raw support).
2289 */
2290 if (termios->c_iflag & IGNPAR)
dfe42443 2291 port->ignore_status_mask |= UART_LSR_OE;
1da177e4
LT		 2292 }
2293
2294 /*
2295 * ignore all characters if CREAD is not set
2296 */
2297 if ((termios->c_cflag & CREAD) == 0)
dfe42443 2298 port->ignore_status_mask |= UART_LSR_DR;
1da177e4
LT		 2299
2300 /*
2301 * CTS flow control flag and modem status interrupts
2302 */
f8b372a1 2303 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2304 if (!(up->bugs & UART_BUG_NOMSR) &&
2305 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2306 up->ier |= UART_IER_MSI;
2307 if (up->capabilities & UART_CAP_UUE)
4539c24f
SW		 2308 up->ier |= UART_IER_UUE;
2309 if (up->capabilities & UART_CAP_RTOIE)
2310 up->ier |= UART_IER_RTOIE;
1da177e4 2311
4fd996a1 2312 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 2313
2314 if (up->capabilities & UART_CAP_EFR) {
2315 unsigned char efr = 0;
2316 /*
2317 * TI16C752/Startech hardware flow control. FIXME:
2318 * - TI16C752 requires control thresholds to be set.
2319 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2320 */
2321 if (termios->c_cflag & CRTSCTS)
2322 efr |= UART_EFR_CTS;
2323
4fd996a1 2324 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
dfe42443 2325 if (port->flags & UPF_EXAR_EFR)
4fd996a1 2326 serial_port_out(port, UART_XR_EFR, efr);
06315348 2327 else
4fd996a1 2328 serial_port_out(port, UART_EFR, efr);
1da177e4
LT		 2329 }
2330
f2eda27d 2331#ifdef CONFIG_ARCH_OMAP
255341c6 2332 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
5668545a 2333 if (cpu_is_omap1510() && is_omap_port(up)) {
255341c6
JM		 2334 if (baud == 115200) {
2335 quot = 1;
4fd996a1 2336 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
255341c6 2337 } else
4fd996a1 2338 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
255341c6
JM		 2339 }
2340#endif
2341
4fd996a1
PG		 2342 /*
2343 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2344 * otherwise just set DLAB
2345 */
2346 if (up->capabilities & UART_NATSEMI)
2347 serial_port_out(port, UART_LCR, 0xe0);
2348 else
2349 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
1da177e4 2350
b32b19b8 2351 serial_dl_write(up, quot);
1da177e4
LT		 2352
2353 /*
2354 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2355 * is written without DLAB set, this mode will be disabled.
2356 */
dfe42443 2357 if (port->type == PORT_16750)
4fd996a1 2358 serial_port_out(port, UART_FCR, fcr);
1da177e4 2359
4fd996a1 2360 serial_port_out(port, UART_LCR, cval); /* reset DLAB */
1da177e4 2361 up->lcr = cval; /* Save LCR */
dfe42443 2362 if (port->type != PORT_16750) {
4fd996a1
PG		 2363 /* emulated UARTs (Lucent Venus 167x) need two steps */
2364 if (fcr & UART_FCR_ENABLE_FIFO)
2365 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2366 serial_port_out(port, UART_FCR, fcr); /* set fcr */
1da177e4 2367 }
dfe42443
PG		 2368 serial8250_set_mctrl(port, port->mctrl);
2369 spin_unlock_irqrestore(&port->lock, flags);
e991a2bd
AC		 2370 /* Don't rewrite B0 */
2371 if (tty_termios_baud_rate(termios))
2372 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4 2373}
235dae5d
PL		 2374EXPORT_SYMBOL(serial8250_do_set_termios);
2375
2376static void
2377serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2378 struct ktermios *old)
2379{
2380 if (port->set_termios)
2381 port->set_termios(port, termios, old);
2382 else
2383 serial8250_do_set_termios(port, termios, old);
2384}
1da177e4 2385
dc77f161 2386static void
a0821df6 2387serial8250_set_ldisc(struct uart_port *port, int new)
dc77f161 2388{
a0821df6 2389 if (new == N_PPS) {
dc77f161
RG		 2390 port->flags |= UPF_HARDPPS_CD;
2391 serial8250_enable_ms(port);
2392 } else
2393 port->flags &= ~UPF_HARDPPS_CD;
2394}
2395
c161afe9
ML		 2396
2397void serial8250_do_pm(struct uart_port *port, unsigned int state,
2398 unsigned int oldstate)
1da177e4 2399{
49d5741b
JI		 2400 struct uart_8250_port *p =
2401 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2402
2403 serial8250_set_sleep(p, state != 0);
c161afe9
ML		 2404}
2405EXPORT_SYMBOL(serial8250_do_pm);
1da177e4 2406
c161afe9
ML		 2407static void
2408serial8250_pm(struct uart_port *port, unsigned int state,
2409 unsigned int oldstate)
2410{
2411 if (port->pm)
2412 port->pm(port, state, oldstate);
2413 else
2414 serial8250_do_pm(port, state, oldstate);
1da177e4
LT		 2415}
2416
f2eda27d
RK		 2417static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2418{
2419 if (pt->port.iotype == UPIO_AU)
b2b13cdf 2420 return 0x1000;
f2eda27d
RK		 2421#ifdef CONFIG_ARCH_OMAP
2422 if (is_omap_port(pt))
2423 return 0x16 << pt->port.regshift;
2424#endif
2425 return 8 << pt->port.regshift;
2426}
2427
1da177e4
LT		 2428/*
2429 * Resource handling.
2430 */
2431static int serial8250_request_std_resource(struct uart_8250_port *up)
2432{
f2eda27d 2433 unsigned int size = serial8250_port_size(up);
dfe42443 2434 struct uart_port *port = &up->port;
1da177e4
LT		 2435 int ret = 0;
2436
dfe42443 2437 switch (port->iotype) {
85835f44 2438 case UPIO_AU:
0b30d668
SS		 2439 case UPIO_TSI:
2440 case UPIO_MEM32:
1da177e4 2441 case UPIO_MEM:
dfe42443 2442 if (!port->mapbase)
1da177e4
LT		 2443 break;
2444
dfe42443 2445 if (!request_mem_region(port->mapbase, size, "serial")) {
1da177e4
LT		 2446 ret = -EBUSY;
2447 break;
2448 }
2449
dfe42443
PG		 2450 if (port->flags & UPF_IOREMAP) {
2451 port->membase = ioremap_nocache(port->mapbase, size);
2452 if (!port->membase) {
2453 release_mem_region(port->mapbase, size);
1da177e4
LT		 2454 ret = -ENOMEM;
2455 }
2456 }
2457 break;
2458
2459 case UPIO_HUB6:
2460 case UPIO_PORT:
dfe42443 2461 if (!request_region(port->iobase, size, "serial"))
1da177e4
LT		 2462 ret = -EBUSY;
2463 break;
2464 }
2465 return ret;
2466}
2467
2468static void serial8250_release_std_resource(struct uart_8250_port *up)
2469{
f2eda27d 2470 unsigned int size = serial8250_port_size(up);
dfe42443 2471 struct uart_port *port = &up->port;
1da177e4 2472
dfe42443 2473 switch (port->iotype) {
85835f44 2474 case UPIO_AU:
0b30d668
SS		 2475 case UPIO_TSI:
2476 case UPIO_MEM32:
1da177e4 2477 case UPIO_MEM:
dfe42443 2478 if (!port->mapbase)
1da177e4
LT		 2479 break;
2480
dfe42443
PG		 2481 if (port->flags & UPF_IOREMAP) {
2482 iounmap(port->membase);
2483 port->membase = NULL;
1da177e4
LT		 2484 }
2485
dfe42443 2486 release_mem_region(port->mapbase, size);
1da177e4
LT		 2487 break;
2488
2489 case UPIO_HUB6:
2490 case UPIO_PORT:
dfe42443 2491 release_region(port->iobase, size);
1da177e4
LT		 2492 break;
2493 }
2494}
2495
2496static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2497{
2498 unsigned long start = UART_RSA_BASE << up->port.regshift;
2499 unsigned int size = 8 << up->port.regshift;
dfe42443 2500 struct uart_port *port = &up->port;
0b30d668 2501 int ret = -EINVAL;
1da177e4 2502
dfe42443 2503 switch (port->iotype) {
1da177e4
LT		 2504 case UPIO_HUB6:
2505 case UPIO_PORT:
dfe42443 2506 start += port->iobase;
0b30d668
SS		 2507 if (request_region(start, size, "serial-rsa"))
2508 ret = 0;
2509 else
1da177e4
LT		 2510 ret = -EBUSY;
2511 break;
2512 }
2513
2514 return ret;
2515}
2516
2517static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2518{
2519 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2520 unsigned int size = 8 << up->port.regshift;
dfe42443 2521 struct uart_port *port = &up->port;
1da177e4 2522
dfe42443 2523 switch (port->iotype) {
1da177e4
LT		 2524 case UPIO_HUB6:
2525 case UPIO_PORT:
dfe42443 2526 release_region(port->iobase + offset, size);
1da177e4
LT		 2527 break;
2528 }
2529}
2530
2531static void serial8250_release_port(struct uart_port *port)
2532{
49d5741b
JI		 2533 struct uart_8250_port *up =
2534 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2535
2536 serial8250_release_std_resource(up);
dfe42443 2537 if (port->type == PORT_RSA)
1da177e4
LT		 2538 serial8250_release_rsa_resource(up);
2539}
2540
2541static int serial8250_request_port(struct uart_port *port)
2542{
49d5741b
JI		 2543 struct uart_8250_port *up =
2544 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2545 int ret = 0;
2546
2547 ret = serial8250_request_std_resource(up);
dfe42443 2548 if (ret == 0 && port->type == PORT_RSA) {
1da177e4
LT		 2549 ret = serial8250_request_rsa_resource(up);
2550 if (ret < 0)
2551 serial8250_release_std_resource(up);
2552 }
2553
2554 return ret;
2555}
2556
2557static void serial8250_config_port(struct uart_port *port, int flags)
2558{
49d5741b
JI		 2559 struct uart_8250_port *up =
2560 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2561 int probeflags = PROBE_ANY;
2562 int ret;
2563
1da177e4
LT		 2564 /*
2565 * Find the region that we can probe for. This in turn
2566 * tells us whether we can probe for the type of port.
2567 */
2568 ret = serial8250_request_std_resource(up);
2569 if (ret < 0)
2570 return;
2571
2572 ret = serial8250_request_rsa_resource(up);
2573 if (ret < 0)
2574 probeflags &= ~PROBE_RSA;
2575
dfe42443 2576 if (port->iotype != up->cur_iotype)
b8e7e40a
AC		 2577 set_io_from_upio(port);
2578
1da177e4
LT		 2579 if (flags & UART_CONFIG_TYPE)
2580 autoconfig(up, probeflags);
b2b13cdf 2581
b2b13cdf 2582 /* if access method is AU, it is a 16550 with a quirk */
dfe42443 2583 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
b2b13cdf 2584 up->bugs |= UART_BUG_NOMSR;
b2b13cdf 2585
dfe42443 2586 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
1da177e4
LT		 2587 autoconfig_irq(up);
2588
dfe42443 2589 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
1da177e4 2590 serial8250_release_rsa_resource(up);
dfe42443 2591 if (port->type == PORT_UNKNOWN)
1da177e4
LT		 2592 serial8250_release_std_resource(up);
2593}
2594
2595static int
2596serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2597{
a62c4133 2598 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2599 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2600 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2601 ser->type == PORT_STARTECH)
2602 return -EINVAL;
2603 return 0;
2604}
2605
2606static const char *
2607serial8250_type(struct uart_port *port)
2608{
2609 int type = port->type;
2610
2611 if (type >= ARRAY_SIZE(uart_config))
2612 type = 0;
2613 return uart_config[type].name;
2614}
2615
2616static struct uart_ops serial8250_pops = {
2617 .tx_empty = serial8250_tx_empty,
2618 .set_mctrl = serial8250_set_mctrl,
2619 .get_mctrl = serial8250_get_mctrl,
2620 .stop_tx = serial8250_stop_tx,
2621 .start_tx = serial8250_start_tx,
2622 .stop_rx = serial8250_stop_rx,
2623 .enable_ms = serial8250_enable_ms,
2624 .break_ctl = serial8250_break_ctl,
2625 .startup = serial8250_startup,
2626 .shutdown = serial8250_shutdown,
2627 .set_termios = serial8250_set_termios,
dc77f161 2628 .set_ldisc = serial8250_set_ldisc,
1da177e4
LT		 2629 .pm = serial8250_pm,
2630 .type = serial8250_type,
2631 .release_port = serial8250_release_port,
2632 .request_port = serial8250_request_port,
2633 .config_port = serial8250_config_port,
2634 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2635#ifdef CONFIG_CONSOLE_POLL
2636 .poll_get_char = serial8250_get_poll_char,
2637 .poll_put_char = serial8250_put_poll_char,
2638#endif
1da177e4
LT		 2639};
2640
2641static struct uart_8250_port serial8250_ports[UART_NR];
2642
af7f3743
AC		 2643static void (*serial8250_isa_config)(int port, struct uart_port *up,
2644 unsigned short *capabilities);
2645
2646void serial8250_set_isa_configurator(
2647 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2648{
2649 serial8250_isa_config = v;
2650}
2651EXPORT_SYMBOL(serial8250_set_isa_configurator);
2652
1da177e4
LT		 2653static void __init serial8250_isa_init_ports(void)
2654{
2655 struct uart_8250_port *up;
2656 static int first = 1;
4c0ebb80 2657 int i, irqflag = 0;
1da177e4
LT		 2658
2659 if (!first)
2660 return;
2661 first = 0;
2662
a61c2d78 2663 for (i = 0; i < nr_uarts; i++) {
1da177e4 2664 struct uart_8250_port *up = &serial8250_ports[i];
dfe42443 2665 struct uart_port *port = &up->port;
1da177e4 2666
dfe42443
PG		 2667 port->line = i;
2668 spin_lock_init(&port->lock);
1da177e4
LT		 2669
2670 init_timer(&up->timer);
2671 up->timer.function = serial8250_timeout;
2672
2673 /*
2674 * ALPHA_KLUDGE_MCR needs to be killed.
2675 */
2676 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2677 up->mcr_force = ALPHA_KLUDGE_MCR;
2678
dfe42443 2679 port->ops = &serial8250_pops;
1da177e4
LT		 2680 }
2681
4c0ebb80
AGR		 2682 if (share_irqs)
2683 irqflag = IRQF_SHARED;
2684
44454bcd 2685 for (i = 0, up = serial8250_ports;
a61c2d78 2686 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4 2687 i++, up++) {
dfe42443
PG		 2688 struct uart_port *port = &up->port;
2689
2690 port->iobase = old_serial_port[i].port;
2691 port->irq = irq_canonicalize(old_serial_port[i].irq);
2692 port->irqflags = old_serial_port[i].irqflags;
2693 port->uartclk = old_serial_port[i].baud_base * 16;
2694 port->flags = old_serial_port[i].flags;
2695 port->hub6 = old_serial_port[i].hub6;
2696 port->membase = old_serial_port[i].iomem_base;
2697 port->iotype = old_serial_port[i].io_type;
2698 port->regshift = old_serial_port[i].iomem_reg_shift;
2699 set_io_from_upio(port);
2700 port->irqflags |= irqflag;
af7f3743
AC		 2701 if (serial8250_isa_config != NULL)
2702 serial8250_isa_config(i, &up->port, &up->capabilities);
2703
1da177e4
LT		 2704 }
2705}
2706
b5d228cc
SL		 2707static void
2708serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2709{
2710 up->port.type = type;
2711 up->port.fifosize = uart_config[type].fifo_size;
2712 up->capabilities = uart_config[type].flags;
2713 up->tx_loadsz = uart_config[type].tx_loadsz;
2714}
2715
1da177e4
LT		 2716static void __init
2717serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2718{
2719 int i;
2720
b8e7e40a
AC		 2721 for (i = 0; i < nr_uarts; i++) {
2722 struct uart_8250_port *up = &serial8250_ports[i];
2723 up->cur_iotype = 0xFF;
2724 }
2725
1da177e4
LT		 2726 serial8250_isa_init_ports();
2727
a61c2d78 2728 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2729 struct uart_8250_port *up = &serial8250_ports[i];
2730
2731 up->port.dev = dev;
b5d228cc
SL		 2732
2733 if (up->port.flags & UPF_FIXED_TYPE)
2734 serial8250_init_fixed_type_port(up, up->port.type);
2735
1da177e4
LT		 2736 uart_add_one_port(drv, &up->port);
2737 }
2738}
2739
2740#ifdef CONFIG_SERIAL_8250_CONSOLE
2741
d358788f
RK		 2742static void serial8250_console_putchar(struct uart_port *port, int ch)
2743{
49d5741b
JI		 2744 struct uart_8250_port *up =
2745 container_of(port, struct uart_8250_port, port);
d358788f
RK		 2746
2747 wait_for_xmitr(up, UART_LSR_THRE);
4fd996a1 2748 serial_port_out(port, UART_TX, ch);
d358788f
RK		 2749}
2750
1da177e4
LT		 2751/*
2752 * Print a string to the serial port trying not to disturb
2753 * any possible real use of the port...
2754 *
2755 * The console_lock must be held when we get here.
2756 */
2757static void
2758serial8250_console_write(struct console *co, const char *s, unsigned int count)
2759{
2760 struct uart_8250_port *up = &serial8250_ports[co->index];
dfe42443 2761 struct uart_port *port = &up->port;
d8a5a8d7 2762 unsigned long flags;
1da177e4 2763 unsigned int ier;
d8a5a8d7 2764 int locked = 1;
1da177e4 2765
78512ece
AM		 2766 touch_nmi_watchdog();
2767
68aa2c0d 2768 local_irq_save(flags);
dfe42443 2769 if (port->sysrq) {
86b21199 2770 /* serial8250_handle_irq() already took the lock */
68aa2c0d
AM		 2771 locked = 0;
2772 } else if (oops_in_progress) {
dfe42443 2773 locked = spin_trylock(&port->lock);
d8a5a8d7 2774 } else
dfe42443 2775 spin_lock(&port->lock);
d8a5a8d7 2776
1da177e4 2777 /*
dc7bf130 2778 * First save the IER then disable the interrupts
1da177e4 2779 */
4fd996a1 2780 ier = serial_port_in(port, UART_IER);
1da177e4
LT		 2781
2782 if (up->capabilities & UART_CAP_UUE)
4fd996a1 2783 serial_port_out(port, UART_IER, UART_IER_UUE);
1da177e4 2784 else
4fd996a1 2785 serial_port_out(port, UART_IER, 0);
1da177e4 2786
dfe42443 2787 uart_console_write(port, s, count, serial8250_console_putchar);
1da177e4
LT		 2788
2789 /*
2790 * Finally, wait for transmitter to become empty
2791 * and restore the IER
2792 */
f91a3715 2793 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 2794 serial_port_out(port, UART_IER, ier);
d8a5a8d7 2795
ad4c2aa6
CM		 2796 /*
2797 * The receive handling will happen properly because the
2798 * receive ready bit will still be set; it is not cleared
2799 * on read. However, modem control will not, we must
2800 * call it if we have saved something in the saved flags
2801 * while processing with interrupts off.
2802 */
2803 if (up->msr_saved_flags)
3986fb2b 2804 serial8250_modem_status(up);
ad4c2aa6 2805
d8a5a8d7 2806 if (locked)
dfe42443 2807 spin_unlock(&port->lock);
68aa2c0d 2808 local_irq_restore(flags);
1da177e4
LT		 2809}
2810
118c0ace 2811static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2812{
2813 struct uart_port *port;
2814 int baud = 9600;
2815 int bits = 8;
2816 int parity = 'n';
2817 int flow = 'n';
2818
2819 /*
2820 * Check whether an invalid uart number has been specified, and
2821 * if so, search for the first available port that does have
2822 * console support.
2823 */
a61c2d78 2824 if (co->index >= nr_uarts)
1da177e4
LT		 2825 co->index = 0;
2826 port = &serial8250_ports[co->index].port;
2827 if (!port->iobase && !port->membase)
2828 return -ENODEV;
2829
2830 if (options)
2831 uart_parse_options(options, &baud, &parity, &bits, &flow);
2832
2833 return uart_set_options(port, co, baud, parity, bits, flow);
2834}
2835
b6b1d877 2836static int serial8250_console_early_setup(void)
18a8bd94
YL		 2837{
2838 return serial8250_find_port_for_earlycon();
2839}
2840
1da177e4
LT		 2841static struct console serial8250_console = {
2842 .name = "ttyS",
2843 .write = serial8250_console_write,
2844 .device = uart_console_device,
2845 .setup = serial8250_console_setup,
18a8bd94 2846 .early_setup = serial8250_console_early_setup,
a80c49db 2847 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2848 .index = -1,
2849 .data = &serial8250_reg,
2850};
2851
2852static int __init serial8250_console_init(void)
2853{
05d81d22
EB		 2854 if (nr_uarts > UART_NR)
2855 nr_uarts = UART_NR;
2856
1da177e4
LT		 2857 serial8250_isa_init_ports();
2858 register_console(&serial8250_console);
2859 return 0;
2860}
2861console_initcall(serial8250_console_init);
2862
18a8bd94 2863int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2864{
2865 int line;
2866 struct uart_port *port;
2867
a61c2d78 2868 for (line = 0; line < nr_uarts; line++) {
1da177e4 2869 port = &serial8250_ports[line].port;
50aec3b5 2870 if (uart_match_port(p, port))
1da177e4
LT		 2871 return line;
2872 }
2873 return -ENODEV;
2874}
2875
1da177e4
LT		 2876#define SERIAL8250_CONSOLE &serial8250_console
2877#else
2878#define SERIAL8250_CONSOLE NULL
2879#endif
2880
2881static struct uart_driver serial8250_reg = {
2882 .owner = THIS_MODULE,
2883 .driver_name = "serial",
1da177e4
LT		 2884 .dev_name = "ttyS",
2885 .major = TTY_MAJOR,
2886 .minor = 64,
1da177e4
LT		 2887 .cons = SERIAL8250_CONSOLE,
2888};
2889
d856c666
RK		 2890/*
2891 * early_serial_setup - early registration for 8250 ports
2892 *
2893 * Setup an 8250 port structure prior to console initialisation. Use
2894 * after console initialisation will cause undefined behaviour.
2895 */
1da177e4
LT		 2896int __init early_serial_setup(struct uart_port *port)
2897{
b430428a
DD		 2898 struct uart_port *p;
2899
1da177e4
LT		 2900 if (port->line >= ARRAY_SIZE(serial8250_ports))
2901 return -ENODEV;
2902
2903 serial8250_isa_init_ports();
b430428a
DD		 2904 p = &serial8250_ports[port->line].port;
2905 p->iobase = port->iobase;
2906 p->membase = port->membase;
2907 p->irq = port->irq;
1c2f0493 2908 p->irqflags = port->irqflags;
b430428a
DD		 2909 p->uartclk = port->uartclk;
2910 p->fifosize = port->fifosize;
2911 p->regshift = port->regshift;
2912 p->iotype = port->iotype;
2913 p->flags = port->flags;
2914 p->mapbase = port->mapbase;
2915 p->private_data = port->private_data;
125c97d8
HD		 2916 p->type = port->type;
2917 p->line = port->line;
7d6a07d1
DD		 2918
2919 set_io_from_upio(p);
2920 if (port->serial_in)
2921 p->serial_in = port->serial_in;
2922 if (port->serial_out)
2923 p->serial_out = port->serial_out;
583d28e9
JI		 2924 if (port->handle_irq)
2925 p->handle_irq = port->handle_irq;
2926 else
2927 p->handle_irq = serial8250_default_handle_irq;
7d6a07d1 2928
1da177e4
LT		 2929 return 0;
2930}
2931
2932/**
2933 * serial8250_suspend_port - suspend one serial port
2934 * @line: serial line number
1da177e4
LT		 2935 *
2936 * Suspend one serial port.
2937 */
2938void serial8250_suspend_port(int line)
2939{
2940 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2941}
2942
2943/**
2944 * serial8250_resume_port - resume one serial port
2945 * @line: serial line number
1da177e4
LT		 2946 *
2947 * Resume one serial port.
2948 */
2949void serial8250_resume_port(int line)
2950{
b5b82df6 2951 struct uart_8250_port *up = &serial8250_ports[line];
dfe42443 2952 struct uart_port *port = &up->port;
b5b82df6
DW		 2953
2954 if (up->capabilities & UART_NATSEMI) {
b5b82df6 2955 /* Ensure it's still in high speed mode */
4fd996a1 2956 serial_port_out(port, UART_LCR, 0xE0);
b5b82df6 2957
0d0389e5 2958 ns16550a_goto_highspeed(up);
b5b82df6 2959
4fd996a1 2960 serial_port_out(port, UART_LCR, 0);
dfe42443 2961 port->uartclk = 921600*16;
b5b82df6 2962 }
dfe42443 2963 uart_resume_port(&serial8250_reg, port);
1da177e4
LT		 2964}
2965
2966/*
2967 * Register a set of serial devices attached to a platform device. The
2968 * list is terminated with a zero flags entry, which means we expect
2969 * all entries to have at least UPF_BOOT_AUTOCONF set.
2970 */
3ae5eaec 2971static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2972{
3ae5eaec 2973 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2974 struct uart_port port;
4c0ebb80 2975 int ret, i, irqflag = 0;
1da177e4
LT		 2976
2977 memset(&port, 0, sizeof(struct uart_port));
2978
4c0ebb80
AGR		 2979 if (share_irqs)
2980 irqflag = IRQF_SHARED;
2981
ec9f47cd 2982 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 2983 port.iobase = p->iobase;
2984 port.membase = p->membase;
2985 port.irq = p->irq;
1c2f0493 2986 port.irqflags = p->irqflags;
74a19741
WN		 2987 port.uartclk = p->uartclk;
2988 port.regshift = p->regshift;
2989 port.iotype = p->iotype;
2990 port.flags = p->flags;
2991 port.mapbase = p->mapbase;
2992 port.hub6 = p->hub6;
2993 port.private_data = p->private_data;
8e23fcc8 2994 port.type = p->type;
7d6a07d1
DD		 2995 port.serial_in = p->serial_in;
2996 port.serial_out = p->serial_out;
583d28e9 2997 port.handle_irq = p->handle_irq;
bf03f65b 2998 port.handle_break = p->handle_break;
235dae5d 2999 port.set_termios = p->set_termios;
c161afe9 3000 port.pm = p->pm;
74a19741 3001 port.dev = &dev->dev;
4c0ebb80 3002 port.irqflags |= irqflag;
ec9f47cd
RK		 3003 ret = serial8250_register_port(&port);
3004 if (ret < 0) {
3ae5eaec 3005 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 3006 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3007 p->iobase, (unsigned long long)p->mapbase,
3008 p->irq, ret);
ec9f47cd 3009 }
1da177e4
LT		 3010 }
3011 return 0;
3012}
3013
3014/*
3015 * Remove serial ports registered against a platform device.
3016 */
3ae5eaec 3017static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 3018{
3019 int i;
3020
a61c2d78 3021 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 3022 struct uart_8250_port *up = &serial8250_ports[i];
3023
3ae5eaec 3024 if (up->port.dev == &dev->dev)
1da177e4
LT		 3025 serial8250_unregister_port(i);
3026 }
3027 return 0;
3028}
3029
3ae5eaec 3030static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 3031{
3032 int i;
3033
1da177e4
LT		 3034 for (i = 0; i < UART_NR; i++) {
3035 struct uart_8250_port *up = &serial8250_ports[i];
3036
3ae5eaec 3037 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3038 uart_suspend_port(&serial8250_reg, &up->port);
3039 }
3040
3041 return 0;
3042}
3043
3ae5eaec 3044static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3045{
3046 int i;
3047
1da177e4
LT		 3048 for (i = 0; i < UART_NR; i++) {
3049 struct uart_8250_port *up = &serial8250_ports[i];
3050
3ae5eaec 3051 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3052 serial8250_resume_port(i);
1da177e4
LT		 3053 }
3054
3055 return 0;
3056}
3057
3ae5eaec 3058static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 3059 .probe = serial8250_probe,
3060 .remove = __devexit_p(serial8250_remove),
3061 .suspend = serial8250_suspend,
3062 .resume = serial8250_resume,
3ae5eaec
RK		 3063 .driver = {
3064 .name = "serial8250",
7493a314 3065 .owner = THIS_MODULE,
3ae5eaec 3066 },
1da177e4
LT		 3067};
3068
3069/*
3070 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3071 * in the table in include/asm/serial.h
3072 */
3073static struct platform_device *serial8250_isa_devs;
3074
3075/*
3076 * serial8250_register_port and serial8250_unregister_port allows for
3077 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3078 * modems and PCI multiport cards.
3079 */
f392ecfa 3080static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3081
3082static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3083{
3084 int i;
3085
3086 /*
3087 * First, find a port entry which matches.
3088 */
a61c2d78 3089 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3090 if (uart_match_port(&serial8250_ports[i].port, port))
3091 return &serial8250_ports[i];
3092
3093 /*
3094 * We didn't find a matching entry, so look for the first
3095 * free entry. We look for one which hasn't been previously
3096 * used (indicated by zero iobase).
3097 */
a61c2d78 3098 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3099 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3100 serial8250_ports[i].port.iobase == 0)
3101 return &serial8250_ports[i];
3102
3103 /*
3104 * That also failed. Last resort is to find any entry which
3105 * doesn't have a real port associated with it.
3106 */
a61c2d78 3107 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3108 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3109 return &serial8250_ports[i];
3110
3111 return NULL;
3112}
3113
3114/**
f73fa05b 3115 * serial8250_register_8250_port - register a serial port
1da177e4
LT		 3116 * @port: serial port template
3117 *
3118 * Configure the serial port specified by the request. If the
3119 * port exists and is in use, it is hung up and unregistered
3120 * first.
3121 *
3122 * The port is then probed and if necessary the IRQ is autodetected
3123 * If this fails an error is returned.
3124 *
3125 * On success the port is ready to use and the line number is returned.
3126 */
f73fa05b 3127int serial8250_register_8250_port(struct uart_8250_port *up)
1da177e4
LT		 3128{
3129 struct uart_8250_port *uart;
3130 int ret = -ENOSPC;
3131
f73fa05b 3132 if (up->port.uartclk == 0)
1da177e4
LT		 3133 return -EINVAL;
3134
f392ecfa 3135 mutex_lock(&serial_mutex);
1da177e4 3136
f73fa05b 3137 uart = serial8250_find_match_or_unused(&up->port);
1da177e4
LT		 3138 if (uart) {
3139 uart_remove_one_port(&serial8250_reg, &uart->port);
3140
f73fa05b
MD		 3141 uart->port.iobase = up->port.iobase;
3142 uart->port.membase = up->port.membase;
3143 uart->port.irq = up->port.irq;
3144 uart->port.irqflags = up->port.irqflags;
3145 uart->port.uartclk = up->port.uartclk;
3146 uart->port.fifosize = up->port.fifosize;
3147 uart->port.regshift = up->port.regshift;
3148 uart->port.iotype = up->port.iotype;
3149 uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF;
3150 uart->port.mapbase = up->port.mapbase;
3151 uart->port.private_data = up->port.private_data;
3152 if (up->port.dev)
3153 uart->port.dev = up->port.dev;
3154
3155 if (up->port.flags & UPF_FIXED_TYPE)
3156 serial8250_init_fixed_type_port(uart, up->port.type);
8e23fcc8 3157
7d6a07d1
DD		 3158 set_io_from_upio(&uart->port);
3159 /* Possibly override default I/O functions. */
f73fa05b
MD		 3160 if (up->port.serial_in)
3161 uart->port.serial_in = up->port.serial_in;
3162 if (up->port.serial_out)
3163 uart->port.serial_out = up->port.serial_out;
3164 if (up->port.handle_irq)
3165 uart->port.handle_irq = up->port.handle_irq;
235dae5d 3166 /* Possibly override set_termios call */
f73fa05b
MD		 3167 if (up->port.set_termios)
3168 uart->port.set_termios = up->port.set_termios;
3169 if (up->port.pm)
3170 uart->port.pm = up->port.pm;
3171 if (up->port.handle_break)
3172 uart->port.handle_break = up->port.handle_break;
3173 if (up->dl_read)
3174 uart->dl_read = up->dl_read;
3175 if (up->dl_write)
3176 uart->dl_write = up->dl_write;
1da177e4 3177
af7f3743
AC		 3178 if (serial8250_isa_config != NULL)
3179 serial8250_isa_config(0, &uart->port,
3180 &uart->capabilities);
3181
1da177e4
LT		 3182 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3183 if (ret == 0)
3184 ret = uart->port.line;
3185 }
f392ecfa 3186 mutex_unlock(&serial_mutex);
1da177e4
LT		 3187
3188 return ret;
3189}
f73fa05b
MD		 3190EXPORT_SYMBOL(serial8250_register_8250_port);
3191
3192/**
3193 * serial8250_register_port - register a serial port
3194 * @port: serial port template
3195 *
3196 * Configure the serial port specified by the request. If the
3197 * port exists and is in use, it is hung up and unregistered
3198 * first.
3199 *
3200 * The port is then probed and if necessary the IRQ is autodetected
3201 * If this fails an error is returned.
3202 *
3203 * On success the port is ready to use and the line number is returned.
3204 */
3205int serial8250_register_port(struct uart_port *port)
3206{
3207 struct uart_8250_port up;
3208
3209 memset(&up, 0, sizeof(up));
3210 memcpy(&up.port, port, sizeof(*port));
3211 return serial8250_register_8250_port(&up);
3212}
1da177e4
LT		 3213EXPORT_SYMBOL(serial8250_register_port);
3214
3215/**
3216 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3217 * @line: serial line number
3218 *
3219 * Remove one serial port. This may not be called from interrupt
3220 * context. We hand the port back to the our control.
3221 */
3222void serial8250_unregister_port(int line)
3223{
3224 struct uart_8250_port *uart = &serial8250_ports[line];
3225
f392ecfa 3226 mutex_lock(&serial_mutex);
1da177e4
LT		 3227 uart_remove_one_port(&serial8250_reg, &uart->port);
3228 if (serial8250_isa_devs) {
3229 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3230 uart->port.type = PORT_UNKNOWN;
3231 uart->port.dev = &serial8250_isa_devs->dev;
cb01ece3 3232 uart->capabilities = uart_config[uart->port.type].flags;
1da177e4
LT		 3233 uart_add_one_port(&serial8250_reg, &uart->port);
3234 } else {
3235 uart->port.dev = NULL;
3236 }
f392ecfa 3237 mutex_unlock(&serial_mutex);
1da177e4
LT		 3238}
3239EXPORT_SYMBOL(serial8250_unregister_port);
3240
3241static int __init serial8250_init(void)
3242{
25db8ad5 3243 int ret;
1da177e4 3244
a61c2d78
DJ		 3245 if (nr_uarts > UART_NR)
3246 nr_uarts = UART_NR;
3247
f1fb9bb8 3248 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3249 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3250 share_irqs ? "en" : "dis");
3251
b70ac771
DM		 3252#ifdef CONFIG_SPARC
3253 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3254#else
3255 serial8250_reg.nr = UART_NR;
1da177e4 3256 ret = uart_register_driver(&serial8250_reg);
b70ac771 3257#endif
1da177e4
LT		 3258 if (ret)
3259 goto out;
3260
7493a314
DT		 3261 serial8250_isa_devs = platform_device_alloc("serial8250",
3262 PLAT8250_DEV_LEGACY);
3263 if (!serial8250_isa_devs) {
3264 ret = -ENOMEM;
bc965a7f 3265 goto unreg_uart_drv;
1da177e4
LT		 3266 }
3267
7493a314
DT		 3268 ret = platform_device_add(serial8250_isa_devs);
3269 if (ret)
3270 goto put_dev;
3271
1da177e4
LT		 3272 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3273
bc965a7f
RK		 3274 ret = platform_driver_register(&serial8250_isa_driver);
3275 if (ret == 0)
3276 goto out;
1da177e4 3277
bc965a7f 3278 platform_device_del(serial8250_isa_devs);
25db8ad5 3279put_dev:
7493a314 3280 platform_device_put(serial8250_isa_devs);
25db8ad5 3281unreg_uart_drv:
b70ac771
DM		 3282#ifdef CONFIG_SPARC
3283 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3284#else
1da177e4 3285 uart_unregister_driver(&serial8250_reg);
b70ac771 3286#endif
25db8ad5 3287out:
1da177e4
LT		 3288 return ret;
3289}
3290
3291static void __exit serial8250_exit(void)
3292{
3293 struct platform_device *isa_dev = serial8250_isa_devs;
3294
3295 /*
3296 * This tells serial8250_unregister_port() not to re-register
3297 * the ports (thereby making serial8250_isa_driver permanently
3298 * in use.)
3299 */
3300 serial8250_isa_devs = NULL;
3301
3ae5eaec 3302 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3303 platform_device_unregister(isa_dev);
3304
b70ac771
DM		 3305#ifdef CONFIG_SPARC
3306 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3307#else
1da177e4 3308 uart_unregister_driver(&serial8250_reg);
b70ac771 3309#endif
1da177e4
LT		 3310}
3311
3312module_init(serial8250_init);
3313module_exit(serial8250_exit);
3314
3315EXPORT_SYMBOL(serial8250_suspend_port);
3316EXPORT_SYMBOL(serial8250_resume_port);
3317
3318MODULE_LICENSE("GPL");
d87a6d95 3319MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3320
3321module_param(share_irqs, uint, 0644);
3322MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3323 " (unsafe)");
3324
a61c2d78
DJ		 3325module_param(nr_uarts, uint, 0644);
3326MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3327
d41a4b51
CE		 3328module_param(skip_txen_test, uint, 0644);
3329MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3330
1da177e4
LT		 3331#ifdef CONFIG_SERIAL_8250_RSA
3332module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3333MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3334#endif
3335MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux kernel - Deliverables
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