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pty: return EINVAL for TIOCGPTN for BSD ptys
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
1da177e4
LT		 13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
1da177e4
LT		 18
19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
1da177e4 29#include <linux/delay.h>
d052d1be 30#include <linux/platform_device.h>
1da177e4 31#include <linux/tty.h>
cd3ecad1 32#include <linux/ratelimit.h>
1da177e4
LT		 33#include <linux/tty_flip.h>
34#include <linux/serial_reg.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
78512ece 38#include <linux/nmi.h>
f392ecfa 39#include <linux/mutex.h>
5a0e3ad6 40#include <linux/slab.h>
6816383a
PG		 41#ifdef CONFIG_SPARC
42#include <linux/sunserialcore.h>
43#endif
1da177e4
LT		 44
45#include <asm/io.h>
46#include <asm/irq.h>
47
48#include "8250.h"
49
50/*
51 * Configuration:
40663cc7 52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 53 * is unsafe when used on edge-triggered interrupts.
54 */
408b664a 55static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 56
a61c2d78
DJ		 57static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
8440838b
DM		 59static struct uart_driver serial8250_reg;
60
61static int serial_index(struct uart_port *port)
62{
63 return (serial8250_reg.minor - 64) + port->line;
64}
65
d41a4b51
CE		 66static unsigned int skip_txen_test; /* force skip of txen test at init time */
67
1da177e4
LT		 68/*
69 * Debugging.
70 */
71#if 0
72#define DEBUG_AUTOCONF(fmt...) printk(fmt)
73#else
74#define DEBUG_AUTOCONF(fmt...) do { } while (0)
75#endif
76
77#if 0
78#define DEBUG_INTR(fmt...) printk(fmt)
79#else
80#define DEBUG_INTR(fmt...) do { } while (0)
81#endif
82
e7328ae1 83#define PASS_LIMIT 512
1da177e4 84
bca47613
DH		 85#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
86
87
1da177e4
LT		 88#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89#define CONFIG_SERIAL_DETECT_IRQ 1
90#endif
1da177e4
LT		 91#ifdef CONFIG_SERIAL_8250_MANY_PORTS
92#define CONFIG_SERIAL_MANY_PORTS 1
93#endif
94
95/*
96 * HUB6 is always on. This will be removed once the header
97 * files have been cleaned.
98 */
99#define CONFIG_HUB6 1
100
a4ed1e41 101#include <asm/serial.h>
1da177e4
LT		 102/*
103 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * standard enumeration mechanism. Platforms that can find all
105 * serial ports via mechanisms like ACPI or PCI need not supply it.
106 */
107#ifndef SERIAL_PORT_DFNS
108#define SERIAL_PORT_DFNS
109#endif
110
cb3592be 111static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
113};
114
026d02a2 115#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 116
117#ifdef CONFIG_SERIAL_8250_RSA
118
119#define PORT_RSA_MAX 4
120static unsigned long probe_rsa[PORT_RSA_MAX];
121static unsigned int probe_rsa_count;
122#endif /* CONFIG_SERIAL_8250_RSA */
123
1da177e4 124struct irq_info {
25db8ad5
AC		 125 struct hlist_node node;
126 int irq;
127 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 128 struct list_head *head;
129};
130
25db8ad5
AC		 131#define NR_IRQ_HASH 32 /* Can be adjusted later */
132static struct hlist_head irq_lists[NR_IRQ_HASH];
133static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 134
135/*
136 * Here we define the default xmit fifo size used for each type of UART.
137 */
138static const struct serial8250_config uart_config[] = {
139 [PORT_UNKNOWN] = {
140 .name = "unknown",
141 .fifo_size = 1,
142 .tx_loadsz = 1,
143 },
144 [PORT_8250] = {
145 .name = "8250",
146 .fifo_size = 1,
147 .tx_loadsz = 1,
148 },
149 [PORT_16450] = {
150 .name = "16450",
151 .fifo_size = 1,
152 .tx_loadsz = 1,
153 },
154 [PORT_16550] = {
155 .name = "16550",
156 .fifo_size = 1,
157 .tx_loadsz = 1,
158 },
159 [PORT_16550A] = {
160 .name = "16550A",
161 .fifo_size = 16,
162 .tx_loadsz = 16,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO,
165 },
166 [PORT_CIRRUS] = {
167 .name = "Cirrus",
168 .fifo_size = 1,
169 .tx_loadsz = 1,
170 },
171 [PORT_16650] = {
172 .name = "ST16650",
173 .fifo_size = 1,
174 .tx_loadsz = 1,
175 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
176 },
177 [PORT_16650V2] = {
178 .name = "ST16650V2",
179 .fifo_size = 32,
180 .tx_loadsz = 16,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
182 UART_FCR_T_TRIG_00,
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184 },
185 [PORT_16750] = {
186 .name = "TI16750",
187 .fifo_size = 64,
188 .tx_loadsz = 64,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
190 UART_FCR7_64BYTE,
191 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
192 },
193 [PORT_STARTECH] = {
194 .name = "Startech",
195 .fifo_size = 1,
196 .tx_loadsz = 1,
197 },
198 [PORT_16C950] = {
199 .name = "16C950/954",
200 .fifo_size = 128,
201 .tx_loadsz = 128,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
d0694e2a
PM		 203 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
1da177e4
LT		 205 },
206 [PORT_16654] = {
207 .name = "ST16654",
208 .fifo_size = 64,
209 .tx_loadsz = 32,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
211 UART_FCR_T_TRIG_10,
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
213 },
214 [PORT_16850] = {
215 .name = "XR16850",
216 .fifo_size = 128,
217 .tx_loadsz = 128,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220 },
221 [PORT_RSA] = {
222 .name = "RSA",
223 .fifo_size = 2048,
224 .tx_loadsz = 2048,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226 .flags = UART_CAP_FIFO,
227 },
228 [PORT_NS16550A] = {
229 .name = "NS16550A",
230 .fifo_size = 16,
231 .tx_loadsz = 16,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_NATSEMI,
234 },
235 [PORT_XSCALE] = {
236 .name = "XScale",
237 .fifo_size = 32,
238 .tx_loadsz = 32,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
4539c24f 240 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
1da177e4 241 },
bd71c182
TK		 242 [PORT_RM9000] = {
243 .name = "RM9000",
244 .fifo_size = 16,
245 .tx_loadsz = 16,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 247 .flags = UART_CAP_FIFO,
248 },
249 [PORT_OCTEON] = {
250 .name = "OCTEON",
251 .fifo_size = 64,
252 .tx_loadsz = 64,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 254 .flags = UART_CAP_FIFO,
255 },
08e0992f
FF		 256 [PORT_AR7] = {
257 .name = "AR7",
258 .fifo_size = 16,
259 .tx_loadsz = 16,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
261 .flags = UART_CAP_FIFO | UART_CAP_AFE,
262 },
235dae5d
PL		 263 [PORT_U6_16550A] = {
264 .name = "U6_16550A",
265 .fifo_size = 64,
266 .tx_loadsz = 64,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO | UART_CAP_AFE,
269 },
4539c24f
SW		 270 [PORT_TEGRA] = {
271 .name = "Tegra",
272 .fifo_size = 32,
273 .tx_loadsz = 8,
274 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
275 UART_FCR_T_TRIG_01,
276 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
277 },
06315348
SH		 278 [PORT_XR17D15X] = {
279 .name = "XR17D15X",
280 .fifo_size = 64,
281 .tx_loadsz = 64,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
81db0772
MS		 283 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
284 UART_CAP_SLEEP,
06315348 285 },
dc96efb7
MS		 286 [PORT_XR17V35X] = {
287 .name = "XR17V35X",
288 .fifo_size = 256,
289 .tx_loadsz = 256,
290 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
291 UART_FCR_T_TRIG_11,
292 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
293 UART_CAP_SLEEP,
294 },
7a514596
RS		 295 [PORT_LPC3220] = {
296 .name = "LPC3220",
297 .fifo_size = 64,
298 .tx_loadsz = 32,
299 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
300 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
301 .flags = UART_CAP_FIFO,
302 },
65ecc9c0
SY		 303 [PORT_8250_CIR] = {
304 .name = "CIR port"
305 }
1da177e4
LT		 306};
307
cc419fa0 308/* Uart divisor latch read */
e8155629 309static int default_serial_dl_read(struct uart_8250_port *up)
cc419fa0
MD		 310{
311 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
312}
313
314/* Uart divisor latch write */
e8155629 315static void default_serial_dl_write(struct uart_8250_port *up, int value)
cc419fa0
MD		 316{
317 serial_out(up, UART_DLL, value & 0xff);
318 serial_out(up, UART_DLM, value >> 8 & 0xff);
319}
320
6b416031 321#ifdef CONFIG_MIPS_ALCHEMY
21c614a7
PA		 322
323/* Au1x00 UART hardware has a weird register layout */
324static const u8 au_io_in_map[] = {
325 [UART_RX] = 0,
326 [UART_IER] = 2,
327 [UART_IIR] = 3,
328 [UART_LCR] = 5,
329 [UART_MCR] = 6,
330 [UART_LSR] = 7,
331 [UART_MSR] = 8,
332};
333
334static const u8 au_io_out_map[] = {
335 [UART_TX] = 1,
336 [UART_IER] = 2,
337 [UART_FCR] = 4,
338 [UART_LCR] = 5,
339 [UART_MCR] = 6,
340};
341
6b416031 342static unsigned int au_serial_in(struct uart_port *p, int offset)
21c614a7 343{
6b416031
MD		 344 offset = au_io_in_map[offset] << p->regshift;
345 return __raw_readl(p->membase + offset);
21c614a7
PA		 346}
347
6b416031 348static void au_serial_out(struct uart_port *p, int offset, int value)
21c614a7 349{
6b416031
MD		 350 offset = au_io_out_map[offset] << p->regshift;
351 __raw_writel(value, p->membase + offset);
352}
353
354/* Au1x00 haven't got a standard divisor latch */
355static int au_serial_dl_read(struct uart_8250_port *up)
356{
357 return __raw_readl(up->port.membase + 0x28);
358}
359
360static void au_serial_dl_write(struct uart_8250_port *up, int value)
361{
362 __raw_writel(value, up->port.membase + 0x28);
21c614a7
PA		 363}
364
6b416031
MD		 365#endif
366
28bf4cf2 367#ifdef CONFIG_SERIAL_8250_RM9K
bd71c182
TK		 368
369static const u8
370 regmap_in[8] = {
371 [UART_RX] = 0x00,
372 [UART_IER] = 0x0c,
373 [UART_IIR] = 0x14,
374 [UART_LCR] = 0x1c,
375 [UART_MCR] = 0x20,
376 [UART_LSR] = 0x24,
377 [UART_MSR] = 0x28,
378 [UART_SCR] = 0x2c
379 },
380 regmap_out[8] = {
381 [UART_TX] = 0x04,
382 [UART_IER] = 0x0c,
383 [UART_FCR] = 0x18,
384 [UART_LCR] = 0x1c,
385 [UART_MCR] = 0x20,
386 [UART_LSR] = 0x24,
387 [UART_MSR] = 0x28,
388 [UART_SCR] = 0x2c
389 };
390
28bf4cf2 391static unsigned int rm9k_serial_in(struct uart_port *p, int offset)
bd71c182 392{
28bf4cf2
MD		 393 offset = regmap_in[offset] << p->regshift;
394 return readl(p->membase + offset);
bd71c182
TK		 395}
396
28bf4cf2 397static void rm9k_serial_out(struct uart_port *p, int offset, int value)
bd71c182 398{
28bf4cf2
MD		 399 offset = regmap_out[offset] << p->regshift;
400 writel(value, p->membase + offset);
bd71c182
TK		 401}
402
28bf4cf2
MD		 403static int rm9k_serial_dl_read(struct uart_8250_port *up)
404{
405 return ((__raw_readl(up->port.membase + 0x10) << 8) |
406 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff;
407}
408
409static void rm9k_serial_dl_write(struct uart_8250_port *up, int value)
410{
411 __raw_writel(value, up->port.membase + 0x08);
412 __raw_writel(value >> 8, up->port.membase + 0x10);
413}
414
415#endif
21c614a7 416
7d6a07d1 417static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 418{
e8155629 419 offset = offset << p->regshift;
7d6a07d1
DD		 420 outb(p->hub6 - 1 + offset, p->iobase);
421 return inb(p->iobase + 1);
422}
1da177e4 423
7d6a07d1
DD		 424static void hub6_serial_out(struct uart_port *p, int offset, int value)
425{
e8155629 426 offset = offset << p->regshift;
7d6a07d1
DD		 427 outb(p->hub6 - 1 + offset, p->iobase);
428 outb(value, p->iobase + 1);
429}
1da177e4 430
7d6a07d1
DD		 431static unsigned int mem_serial_in(struct uart_port *p, int offset)
432{
e8155629 433 offset = offset << p->regshift;
7d6a07d1
DD		 434 return readb(p->membase + offset);
435}
1da177e4 436
7d6a07d1
DD		 437static void mem_serial_out(struct uart_port *p, int offset, int value)
438{
e8155629 439 offset = offset << p->regshift;
7d6a07d1
DD		 440 writeb(value, p->membase + offset);
441}
442
443static void mem32_serial_out(struct uart_port *p, int offset, int value)
444{
e8155629 445 offset = offset << p->regshift;
7d6a07d1
DD		 446 writel(value, p->membase + offset);
447}
448
449static unsigned int mem32_serial_in(struct uart_port *p, int offset)
450{
e8155629 451 offset = offset << p->regshift;
7d6a07d1
DD		 452 return readl(p->membase + offset);
453}
1da177e4 454
7d6a07d1
DD		 455static unsigned int io_serial_in(struct uart_port *p, int offset)
456{
e8155629 457 offset = offset << p->regshift;
7d6a07d1
DD		 458 return inb(p->iobase + offset);
459}
460
461static void io_serial_out(struct uart_port *p, int offset, int value)
462{
e8155629 463 offset = offset << p->regshift;
7d6a07d1
DD		 464 outb(value, p->iobase + offset);
465}
466
583d28e9 467static int serial8250_default_handle_irq(struct uart_port *port);
dc96efb7 468static int exar_handle_irq(struct uart_port *port);
583d28e9 469
7d6a07d1
DD		 470static void set_io_from_upio(struct uart_port *p)
471{
49d5741b
JI		 472 struct uart_8250_port *up =
473 container_of(p, struct uart_8250_port, port);
cc419fa0 474
e8155629
MD		 475 up->dl_read = default_serial_dl_read;
476 up->dl_write = default_serial_dl_write;
cc419fa0 477
7d6a07d1 478 switch (p->iotype) {
1da177e4 479 case UPIO_HUB6:
7d6a07d1
DD		 480 p->serial_in = hub6_serial_in;
481 p->serial_out = hub6_serial_out;
1da177e4
LT		 482 break;
483
484 case UPIO_MEM:
7d6a07d1
DD		 485 p->serial_in = mem_serial_in;
486 p->serial_out = mem_serial_out;
1da177e4
LT		 487 break;
488
489 case UPIO_MEM32:
7d6a07d1
DD		 490 p->serial_in = mem32_serial_in;
491 p->serial_out = mem32_serial_out;
1da177e4
LT		 492 break;
493
28bf4cf2
MD		 494#ifdef CONFIG_SERIAL_8250_RM9K
495 case UPIO_RM9000:
496 p->serial_in = rm9k_serial_in;
497 p->serial_out = rm9k_serial_out;
498 up->dl_read = rm9k_serial_dl_read;
499 up->dl_write = rm9k_serial_dl_write;
500 break;
501#endif
502
6b416031 503#ifdef CONFIG_MIPS_ALCHEMY
21c614a7 504 case UPIO_AU:
7d6a07d1
DD		 505 p->serial_in = au_serial_in;
506 p->serial_out = au_serial_out;
6b416031
MD		 507 up->dl_read = au_serial_dl_read;
508 up->dl_write = au_serial_dl_write;
21c614a7 509 break;
6b416031 510#endif
12bf3f24 511
1da177e4 512 default:
7d6a07d1
DD		 513 p->serial_in = io_serial_in;
514 p->serial_out = io_serial_out;
515 break;
1da177e4 516 }
b8e7e40a
AC		 517 /* Remember loaded iotype */
518 up->cur_iotype = p->iotype;
583d28e9 519 p->handle_irq = serial8250_default_handle_irq;
1da177e4
LT		 520}
521
40b36daa 522static void
55e4016d 523serial_port_out_sync(struct uart_port *p, int offset, int value)
40b36daa 524{
7d6a07d1 525 switch (p->iotype) {
40b36daa
AW		 526 case UPIO_MEM:
527 case UPIO_MEM32:
40b36daa 528 case UPIO_AU:
7d6a07d1
DD		 529 p->serial_out(p, offset, value);
530 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 531 break;
532 default:
7d6a07d1 533 p->serial_out(p, offset, value);
40b36daa
AW		 534 }
535}
536
1da177e4
LT		 537/*
538 * For the 16C950
539 */
540static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
541{
542 serial_out(up, UART_SCR, offset);
543 serial_out(up, UART_ICR, value);
544}
545
546static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
547{
548 unsigned int value;
549
550 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
551 serial_out(up, UART_SCR, offset);
552 value = serial_in(up, UART_ICR);
553 serial_icr_write(up, UART_ACR, up->acr);
554
555 return value;
556}
557
558/*
559 * FIFO support.
560 */
b5d674ab 561static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 562{
563 if (p->capabilities & UART_CAP_FIFO) {
0acf519f
PG		 564 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
565 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
1da177e4 566 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0acf519f 567 serial_out(p, UART_FCR, 0);
1da177e4
LT		 568 }
569}
570
0ad372b9
SM		 571void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
572{
573 unsigned char fcr;
574
575 serial8250_clear_fifos(p);
576 fcr = uart_config[p->port.type].fcr;
577 serial_out(p, UART_FCR, fcr);
578}
579EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
580
1da177e4
LT		 581/*
582 * IER sleep support. UARTs which have EFRs need the "extended
583 * capability" bit enabled. Note that on XR16C850s, we need to
584 * reset LCR to write to IER.
585 */
b5d674ab 586static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4 587{
dc96efb7
MS		 588 /*
589 * Exar UARTs have a SLEEP register that enables or disables
590 * each UART to enter sleep mode separately. On the XR17V35x the
591 * register is accessible to each UART at the UART_EXAR_SLEEP
592 * offset but the UART channel may only write to the corresponding
593 * bit.
594 */
81db0772
MS		 595 if ((p->port.type == PORT_XR17V35X) ||
596 (p->port.type == PORT_XR17D15X)) {
dc96efb7
MS		 597 serial_out(p, UART_EXAR_SLEEP, 0xff);
598 return;
599 }
600
1da177e4
LT		 601 if (p->capabilities & UART_CAP_SLEEP) {
602 if (p->capabilities & UART_CAP_EFR) {
0acf519f
PG		 603 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
604 serial_out(p, UART_EFR, UART_EFR_ECB);
605 serial_out(p, UART_LCR, 0);
1da177e4 606 }
0acf519f 607 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
1da177e4 608 if (p->capabilities & UART_CAP_EFR) {
0acf519f
PG		 609 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
610 serial_out(p, UART_EFR, 0);
611 serial_out(p, UART_LCR, 0);
1da177e4
LT		 612 }
613 }
614}
615
616#ifdef CONFIG_SERIAL_8250_RSA
617/*
618 * Attempts to turn on the RSA FIFO. Returns zero on failure.
619 * We set the port uart clock rate if we succeed.
620 */
621static int __enable_rsa(struct uart_8250_port *up)
622{
623 unsigned char mode;
624 int result;
625
0acf519f 626 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 627 result = mode & UART_RSA_MSR_FIFO;
628
629 if (!result) {
0acf519f
PG		 630 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
631 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 632 result = mode & UART_RSA_MSR_FIFO;
633 }
634
635 if (result)
636 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
637
638 return result;
639}
640
641static void enable_rsa(struct uart_8250_port *up)
642{
643 if (up->port.type == PORT_RSA) {
644 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
645 spin_lock_irq(&up->port.lock);
646 __enable_rsa(up);
647 spin_unlock_irq(&up->port.lock);
648 }
649 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
0acf519f 650 serial_out(up, UART_RSA_FRR, 0);
1da177e4
LT		 651 }
652}
653
654/*
655 * Attempts to turn off the RSA FIFO. Returns zero on failure.
656 * It is unknown why interrupts were disabled in here. However,
657 * the caller is expected to preserve this behaviour by grabbing
658 * the spinlock before calling this function.
659 */
660static void disable_rsa(struct uart_8250_port *up)
661{
662 unsigned char mode;
663 int result;
664
665 if (up->port.type == PORT_RSA &&
666 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
667 spin_lock_irq(&up->port.lock);
668
0acf519f 669 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 670 result = !(mode & UART_RSA_MSR_FIFO);
671
672 if (!result) {
0acf519f
PG		 673 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
674 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 675 result = !(mode & UART_RSA_MSR_FIFO);
676 }
677
678 if (result)
679 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
680 spin_unlock_irq(&up->port.lock);
681 }
682}
683#endif /* CONFIG_SERIAL_8250_RSA */
684
685/*
686 * This is a quickie test to see how big the FIFO is.
687 * It doesn't work at all the time, more's the pity.
688 */
689static int size_fifo(struct uart_8250_port *up)
690{
b32b19b8
JAH		 691 unsigned char old_fcr, old_mcr, old_lcr;
692 unsigned short old_dl;
1da177e4
LT		 693 int count;
694
0acf519f
PG		 695 old_lcr = serial_in(up, UART_LCR);
696 serial_out(up, UART_LCR, 0);
697 old_fcr = serial_in(up, UART_FCR);
698 old_mcr = serial_in(up, UART_MCR);
699 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1da177e4 700 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0acf519f
PG		 701 serial_out(up, UART_MCR, UART_MCR_LOOP);
702 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8
JAH		 703 old_dl = serial_dl_read(up);
704 serial_dl_write(up, 0x0001);
0acf519f 705 serial_out(up, UART_LCR, 0x03);
1da177e4 706 for (count = 0; count < 256; count++)
0acf519f 707 serial_out(up, UART_TX, count);
1da177e4 708 mdelay(20);/* FIXME - schedule_timeout */
0acf519f 709 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
1da177e4 710 (count < 256); count++)
0acf519f
PG		 711 serial_in(up, UART_RX);
712 serial_out(up, UART_FCR, old_fcr);
713 serial_out(up, UART_MCR, old_mcr);
714 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8 715 serial_dl_write(up, old_dl);
0acf519f 716 serial_out(up, UART_LCR, old_lcr);
1da177e4
LT		 717
718 return count;
719}
720
721/*
722 * Read UART ID using the divisor method - set DLL and DLM to zero
723 * and the revision will be in DLL and device type in DLM. We
724 * preserve the device state across this.
725 */
726static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
727{
728 unsigned char old_dll, old_dlm, old_lcr;
729 unsigned int id;
730
0acf519f
PG		 731 old_lcr = serial_in(p, UART_LCR);
732 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4 733
0acf519f
PG		 734 old_dll = serial_in(p, UART_DLL);
735 old_dlm = serial_in(p, UART_DLM);
1da177e4 736
0acf519f
PG		 737 serial_out(p, UART_DLL, 0);
738 serial_out(p, UART_DLM, 0);
1da177e4 739
0acf519f 740 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
1da177e4 741
0acf519f
PG		 742 serial_out(p, UART_DLL, old_dll);
743 serial_out(p, UART_DLM, old_dlm);
744 serial_out(p, UART_LCR, old_lcr);
1da177e4
LT		 745
746 return id;
747}
748
749/*
750 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
751 * When this function is called we know it is at least a StarTech
752 * 16650 V2, but it might be one of several StarTech UARTs, or one of
753 * its clones. (We treat the broken original StarTech 16650 V1 as a
754 * 16550, and why not? Startech doesn't seem to even acknowledge its
755 * existence.)
bd71c182 756 *
1da177e4
LT		 757 * What evil have men's minds wrought...
758 */
759static void autoconfig_has_efr(struct uart_8250_port *up)
760{
761 unsigned int id1, id2, id3, rev;
762
763 /*
764 * Everything with an EFR has SLEEP
765 */
766 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
767
768 /*
769 * First we check to see if it's an Oxford Semiconductor UART.
770 *
771 * If we have to do this here because some non-National
772 * Semiconductor clone chips lock up if you try writing to the
773 * LSR register (which serial_icr_read does)
774 */
775
776 /*
777 * Check for Oxford Semiconductor 16C950.
778 *
779 * EFR [4] must be set else this test fails.
780 *
781 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
782 * claims that it's needed for 952 dual UART's (which are not
783 * recommended for new designs).
784 */
785 up->acr = 0;
662b083a 786 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 787 serial_out(up, UART_EFR, UART_EFR_ECB);
788 serial_out(up, UART_LCR, 0x00);
789 id1 = serial_icr_read(up, UART_ID1);
790 id2 = serial_icr_read(up, UART_ID2);
791 id3 = serial_icr_read(up, UART_ID3);
792 rev = serial_icr_read(up, UART_REV);
793
794 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
795
796 if (id1 == 0x16 && id2 == 0xC9 &&
797 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
798 up->port.type = PORT_16C950;
4ba5e35d
RK		 799
800 /*
801 * Enable work around for the Oxford Semiconductor 952 rev B
802 * chip which causes it to seriously miscalculate baud rates
803 * when DLL is 0.
804 */
805 if (id3 == 0x52 && rev == 0x01)
806 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 807 return;
808 }
bd71c182 809
1da177e4
LT		 810 /*
811 * We check for a XR16C850 by setting DLL and DLM to 0, and then
812 * reading back DLL and DLM. The chip type depends on the DLM
813 * value read back:
814 * 0x10 - XR16C850 and the DLL contains the chip revision.
815 * 0x12 - XR16C2850.
816 * 0x14 - XR16C854.
817 */
818 id1 = autoconfig_read_divisor_id(up);
819 DEBUG_AUTOCONF("850id=%04x ", id1);
820
821 id2 = id1 >> 8;
822 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 823 up->port.type = PORT_16850;
824 return;
825 }
826
827 /*
828 * It wasn't an XR16C850.
829 *
830 * We distinguish between the '654 and the '650 by counting
831 * how many bytes are in the FIFO. I'm using this for now,
832 * since that's the technique that was sent to me in the
833 * serial driver update, but I'm not convinced this works.
834 * I've had problems doing this in the past. -TYT
835 */
836 if (size_fifo(up) == 64)
837 up->port.type = PORT_16654;
838 else
839 up->port.type = PORT_16650V2;
840}
841
842/*
843 * We detected a chip without a FIFO. Only two fall into
844 * this category - the original 8250 and the 16450. The
845 * 16450 has a scratch register (accessible with LCR=0)
846 */
847static void autoconfig_8250(struct uart_8250_port *up)
848{
849 unsigned char scratch, status1, status2;
850
851 up->port.type = PORT_8250;
852
853 scratch = serial_in(up, UART_SCR);
0acf519f 854 serial_out(up, UART_SCR, 0xa5);
1da177e4 855 status1 = serial_in(up, UART_SCR);
0acf519f 856 serial_out(up, UART_SCR, 0x5a);
1da177e4 857 status2 = serial_in(up, UART_SCR);
0acf519f 858 serial_out(up, UART_SCR, scratch);
1da177e4
LT		 859
860 if (status1 == 0xa5 && status2 == 0x5a)
861 up->port.type = PORT_16450;
862}
863
864static int broken_efr(struct uart_8250_port *up)
865{
866 /*
867 * Exar ST16C2550 "A2" devices incorrectly detect as
868 * having an EFR, and report an ID of 0x0201. See
631dd1a8 869 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1da177e4
LT		 870 */
871 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
872 return 1;
873
874 return 0;
875}
876
0d0389e5
YK		 877static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
878{
879 unsigned char status;
880
881 status = serial_in(up, 0x04); /* EXCR2 */
882#define PRESL(x) ((x) & 0x30)
883 if (PRESL(status) == 0x10) {
884 /* already in high speed mode */
885 return 0;
886 } else {
887 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
888 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
0acf519f 889 serial_out(up, 0x04, status);
0d0389e5
YK		 890 }
891 return 1;
892}
893
1da177e4
LT		 894/*
895 * We know that the chip has FIFOs. Does it have an EFR? The
896 * EFR is located in the same register position as the IIR and
897 * we know the top two bits of the IIR are currently set. The
898 * EFR should contain zero. Try to read the EFR.
899 */
900static void autoconfig_16550a(struct uart_8250_port *up)
901{
902 unsigned char status1, status2;
903 unsigned int iersave;
904
905 up->port.type = PORT_16550A;
906 up->capabilities |= UART_CAP_FIFO;
907
dc96efb7
MS		 908 /*
909 * XR17V35x UARTs have an extra divisor register, DLD
910 * that gets enabled with when DLAB is set which will
911 * cause the device to incorrectly match and assign
912 * port type to PORT_16650. The EFR for this UART is
913 * found at offset 0x09. Instead check the Deice ID (DVID)
914 * register for a 2, 4 or 8 port UART.
915 */
b7a7e14f
MS		 916 if (up->port.flags & UPF_EXAR_EFR) {
917 status1 = serial_in(up, UART_EXAR_DVID);
918 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
dc96efb7
MS		 919 DEBUG_AUTOCONF("Exar XR17V35x ");
920 up->port.type = PORT_XR17V35X;
921 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
922 UART_CAP_SLEEP;
923
924 return;
925 }
926
927 }
928
1da177e4
LT		 929 /*
930 * Check for presence of the EFR when DLAB is set.
931 * Only ST16C650V1 UARTs pass this test.
932 */
0acf519f 933 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4 934 if (serial_in(up, UART_EFR) == 0) {
0acf519f 935 serial_out(up, UART_EFR, 0xA8);
1da177e4
LT		 936 if (serial_in(up, UART_EFR) != 0) {
937 DEBUG_AUTOCONF("EFRv1 ");
938 up->port.type = PORT_16650;
939 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
940 } else {
941 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
942 }
0acf519f 943 serial_out(up, UART_EFR, 0);
1da177e4
LT		 944 return;
945 }
946
947 /*
948 * Maybe it requires 0xbf to be written to the LCR.
949 * (other ST16C650V2 UARTs, TI16C752A, etc)
950 */
0acf519f 951 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 952 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
953 DEBUG_AUTOCONF("EFRv2 ");
954 autoconfig_has_efr(up);
955 return;
956 }
957
958 /*
959 * Check for a National Semiconductor SuperIO chip.
960 * Attempt to switch to bank 2, read the value of the LOOP bit
961 * from EXCR1. Switch back to bank 0, change it in MCR. Then
962 * switch back to bank 2, read it from EXCR1 again and check
963 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4 964 */
0acf519f 965 serial_out(up, UART_LCR, 0);
1da177e4 966 status1 = serial_in(up, UART_MCR);
0acf519f 967 serial_out(up, UART_LCR, 0xE0);
1da177e4
LT		 968 status2 = serial_in(up, 0x02); /* EXCR1 */
969
970 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
0acf519f
PG		 971 serial_out(up, UART_LCR, 0);
972 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
973 serial_out(up, UART_LCR, 0xE0);
1da177e4 974 status2 = serial_in(up, 0x02); /* EXCR1 */
0acf519f
PG		 975 serial_out(up, UART_LCR, 0);
976 serial_out(up, UART_MCR, status1);
1da177e4
LT		 977
978 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 979 unsigned short quot;
980
0acf519f 981 serial_out(up, UART_LCR, 0xE0);
857dde2e 982
b32b19b8 983 quot = serial_dl_read(up);
857dde2e
DW		 984 quot <<= 3;
985
0d0389e5
YK		 986 if (ns16550a_goto_highspeed(up))
987 serial_dl_write(up, quot);
857dde2e 988
0acf519f 989 serial_out(up, UART_LCR, 0);
1da177e4 990
857dde2e 991 up->port.uartclk = 921600*16;
1da177e4
LT		 992 up->port.type = PORT_NS16550A;
993 up->capabilities |= UART_NATSEMI;
994 return;
995 }
996 }
997
998 /*
999 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1000 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1001 * Try setting it with and without DLAB set. Cheap clones
1002 * set bit 5 without DLAB set.
1003 */
0acf519f
PG		 1004 serial_out(up, UART_LCR, 0);
1005 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1da177e4 1006 status1 = serial_in(up, UART_IIR) >> 5;
0acf519f
PG		 1007 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1008 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1009 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1da177e4 1010 status2 = serial_in(up, UART_IIR) >> 5;
0acf519f
PG		 1011 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1012 serial_out(up, UART_LCR, 0);
1da177e4
LT		 1013
1014 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1015
1016 if (status1 == 6 && status2 == 7) {
1017 up->port.type = PORT_16750;
1018 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1019 return;
1020 }
1021
1022 /*
1023 * Try writing and reading the UART_IER_UUE bit (b6).
1024 * If it works, this is probably one of the Xscale platform's
1025 * internal UARTs.
1026 * We're going to explicitly set the UUE bit to 0 before
1027 * trying to write and read a 1 just to make sure it's not
1028 * already a 1 and maybe locked there before we even start start.
1029 */
1030 iersave = serial_in(up, UART_IER);
0acf519f 1031 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1da177e4
LT		 1032 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1033 /*
1034 * OK it's in a known zero state, try writing and reading
1035 * without disturbing the current state of the other bits.
1036 */
0acf519f 1037 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1da177e4
LT		 1038 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1039 /*
1040 * It's an Xscale.
1041 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1042 */
1043 DEBUG_AUTOCONF("Xscale ");
1044 up->port.type = PORT_XSCALE;
5568181f 1045 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1da177e4
LT		 1046 return;
1047 }
1048 } else {
1049 /*
1050 * If we got here we couldn't force the IER_UUE bit to 0.
1051 * Log it and continue.
1052 */
1053 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1054 }
0acf519f 1055 serial_out(up, UART_IER, iersave);
235dae5d 1056
06315348
SH		 1057 /*
1058 * Exar uarts have EFR in a weird location
1059 */
1060 if (up->port.flags & UPF_EXAR_EFR) {
81db0772 1061 DEBUG_AUTOCONF("Exar XR17D15x ");
06315348 1062 up->port.type = PORT_XR17D15X;
81db0772
MS		 1063 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1064 UART_CAP_SLEEP;
1065
1066 return;
06315348
SH		 1067 }
1068
235dae5d
PL		 1069 /*
1070 * We distinguish between 16550A and U6 16550A by counting
1071 * how many bytes are in the FIFO.
1072 */
1073 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1074 up->port.type = PORT_U6_16550A;
1075 up->capabilities |= UART_CAP_AFE;
1076 }
1da177e4
LT		 1077}
1078
1079/*
1080 * This routine is called by rs_init() to initialize a specific serial
1081 * port. It determines what type of UART chip this serial port is
1082 * using: 8250, 16450, 16550, 16550A. The important question is
1083 * whether or not this UART is a 16550A or not, since this will
1084 * determine whether or not we can use its FIFO features or not.
1085 */
1086static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1087{
1088 unsigned char status1, scratch, scratch2, scratch3;
1089 unsigned char save_lcr, save_mcr;
dfe42443 1090 struct uart_port *port = &up->port;
1da177e4 1091 unsigned long flags;
bd21f551 1092 unsigned int old_capabilities;
1da177e4 1093
dfe42443 1094 if (!port->iobase && !port->mapbase && !port->membase)
1da177e4
LT		 1095 return;
1096
80647b95 1097 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
dfe42443 1098 serial_index(port), port->iobase, port->membase);
1da177e4
LT		 1099
1100 /*
1101 * We really do need global IRQs disabled here - we're going to
1102 * be frobbing the chips IRQ enable register to see if it exists.
1103 */
dfe42443 1104 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 1105
1106 up->capabilities = 0;
4ba5e35d 1107 up->bugs = 0;
1da177e4 1108
dfe42443 1109 if (!(port->flags & UPF_BUGGY_UART)) {
1da177e4
LT		 1110 /*
1111 * Do a simple existence test first; if we fail this,
1112 * there's no point trying anything else.
bd71c182 1113 *
1da177e4
LT		 1114 * 0x80 is used as a nonsense port to prevent against
1115 * false positives due to ISA bus float. The
1116 * assumption is that 0x80 is a non-existent port;
1117 * which should be safe since include/asm/io.h also
1118 * makes this assumption.
1119 *
1120 * Note: this is safe as long as MCR bit 4 is clear
1121 * and the device is in "PC" mode.
1122 */
0acf519f
PG		 1123 scratch = serial_in(up, UART_IER);
1124 serial_out(up, UART_IER, 0);
1da177e4
LT		 1125#ifdef __i386__
1126 outb(0xff, 0x080);
1127#endif
48212008
TH		 1128 /*
1129 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1130 * 16C754B) allow only to modify them if an EFR bit is set.
1131 */
0acf519f
PG		 1132 scratch2 = serial_in(up, UART_IER) & 0x0f;
1133 serial_out(up, UART_IER, 0x0F);
1da177e4
LT		 1134#ifdef __i386__
1135 outb(0, 0x080);
1136#endif
0acf519f
PG		 1137 scratch3 = serial_in(up, UART_IER) & 0x0f;
1138 serial_out(up, UART_IER, scratch);
1da177e4
LT		 1139 if (scratch2 != 0 || scratch3 != 0x0F) {
1140 /*
1141 * We failed; there's nothing here
1142 */
bd21f551 1143 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1144 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1145 scratch2, scratch3);
1146 goto out;
1147 }
1148 }
1149
1150 save_mcr = serial_in(up, UART_MCR);
1151 save_lcr = serial_in(up, UART_LCR);
1152
bd71c182 1153 /*
1da177e4
LT		 1154 * Check to see if a UART is really there. Certain broken
1155 * internal modems based on the Rockwell chipset fail this
1156 * test, because they apparently don't implement the loopback
1157 * test mode. So this test is skipped on the COM 1 through
1158 * COM 4 ports. This *should* be safe, since no board
1159 * manufacturer would be stupid enough to design a board
1160 * that conflicts with COM 1-4 --- we hope!
1161 */
dfe42443 1162 if (!(port->flags & UPF_SKIP_TEST)) {
0acf519f
PG		 1163 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1164 status1 = serial_in(up, UART_MSR) & 0xF0;
1165 serial_out(up, UART_MCR, save_mcr);
1da177e4 1166 if (status1 != 0x90) {
bd21f551 1167 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1168 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1169 status1);
1170 goto out;
1171 }
1172 }
1173
1174 /*
1175 * We're pretty sure there's a port here. Lets find out what
1176 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1177 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1178 * determines what we test for next.
1179 *
1180 * We also initialise the EFR (if any) to zero for later. The
1181 * EFR occupies the same register location as the FCR and IIR.
1182 */
0acf519f
PG		 1183 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1184 serial_out(up, UART_EFR, 0);
1185 serial_out(up, UART_LCR, 0);
1da177e4 1186
0acf519f 1187 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1da177e4
LT		 1188 scratch = serial_in(up, UART_IIR) >> 6;
1189
1da177e4
LT		 1190 switch (scratch) {
1191 case 0:
1192 autoconfig_8250(up);
1193 break;
1194 case 1:
dfe42443 1195 port->type = PORT_UNKNOWN;
1da177e4
LT		 1196 break;
1197 case 2:
dfe42443 1198 port->type = PORT_16550;
1da177e4
LT		 1199 break;
1200 case 3:
1201 autoconfig_16550a(up);
1202 break;
1203 }
1204
1205#ifdef CONFIG_SERIAL_8250_RSA
1206 /*
1207 * Only probe for RSA ports if we got the region.
1208 */
dfe42443 1209 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1da177e4
LT		 1210 int i;
1211
1212 for (i = 0 ; i < probe_rsa_count; ++i) {
dfe42443
PG		 1213 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1214 port->type = PORT_RSA;
1da177e4
LT		 1215 break;
1216 }
1217 }
1218 }
1219#endif
21c614a7 1220
0acf519f 1221 serial_out(up, UART_LCR, save_lcr);
1da177e4 1222
dfe42443 1223 port->fifosize = uart_config[up->port.type].fifo_size;
bd21f551 1224 old_capabilities = up->capabilities;
dfe42443
PG		 1225 up->capabilities = uart_config[port->type].flags;
1226 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1da177e4 1227
dfe42443 1228 if (port->type == PORT_UNKNOWN)
bd21f551 1229 goto out_lock;
1da177e4
LT		 1230
1231 /*
1232 * Reset the UART.
1233 */
1234#ifdef CONFIG_SERIAL_8250_RSA
dfe42443 1235 if (port->type == PORT_RSA)
0acf519f 1236 serial_out(up, UART_RSA_FRR, 0);
1da177e4 1237#endif
0acf519f 1238 serial_out(up, UART_MCR, save_mcr);
1da177e4 1239 serial8250_clear_fifos(up);
40b36daa 1240 serial_in(up, UART_RX);
5c8c755c 1241 if (up->capabilities & UART_CAP_UUE)
0acf519f 1242 serial_out(up, UART_IER, UART_IER_UUE);
5c8c755c 1243 else
0acf519f 1244 serial_out(up, UART_IER, 0);
1da177e4 1245
bd21f551 1246out_lock:
dfe42443 1247 spin_unlock_irqrestore(&port->lock, flags);
bd21f551
FL		 1248 if (up->capabilities != old_capabilities) {
1249 printk(KERN_WARNING
1250 "ttyS%d: detected caps %08x should be %08x\n",
1251 serial_index(port), old_capabilities,
1252 up->capabilities);
1253 }
1254out:
1255 DEBUG_AUTOCONF("iir=%d ", scratch);
dfe42443 1256 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1da177e4
LT		 1257}
1258
1259static void autoconfig_irq(struct uart_8250_port *up)
1260{
dfe42443 1261 struct uart_port *port = &up->port;
1da177e4
LT		 1262 unsigned char save_mcr, save_ier;
1263 unsigned char save_ICP = 0;
1264 unsigned int ICP = 0;
1265 unsigned long irqs;
1266 int irq;
1267
dfe42443
PG		 1268 if (port->flags & UPF_FOURPORT) {
1269 ICP = (port->iobase & 0xfe0) | 0x1f;
1da177e4
LT		 1270 save_ICP = inb_p(ICP);
1271 outb_p(0x80, ICP);
0d263a26 1272 inb_p(ICP);
1da177e4
LT		 1273 }
1274
1275 /* forget possible initially masked and pending IRQ */
1276 probe_irq_off(probe_irq_on());
0acf519f
PG		 1277 save_mcr = serial_in(up, UART_MCR);
1278 save_ier = serial_in(up, UART_IER);
1279 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1280
1da177e4 1281 irqs = probe_irq_on();
0acf519f 1282 serial_out(up, UART_MCR, 0);
6f803cd0 1283 udelay(10);
dfe42443 1284 if (port->flags & UPF_FOURPORT) {
0acf519f 1285 serial_out(up, UART_MCR,
1da177e4
LT		 1286 UART_MCR_DTR | UART_MCR_RTS);
1287 } else {
0acf519f 1288 serial_out(up, UART_MCR,
1da177e4
LT		 1289 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1290 }
0acf519f 1291 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
0d263a26
PG		 1292 serial_in(up, UART_LSR);
1293 serial_in(up, UART_RX);
1294 serial_in(up, UART_IIR);
1295 serial_in(up, UART_MSR);
0acf519f 1296 serial_out(up, UART_TX, 0xFF);
6f803cd0 1297 udelay(20);
1da177e4
LT		 1298 irq = probe_irq_off(irqs);
1299
0acf519f
PG		 1300 serial_out(up, UART_MCR, save_mcr);
1301 serial_out(up, UART_IER, save_ier);
1da177e4 1302
dfe42443 1303 if (port->flags & UPF_FOURPORT)
1da177e4
LT		 1304 outb_p(save_ICP, ICP);
1305
dfe42443 1306 port->irq = (irq > 0) ? irq : 0;
1da177e4
LT		 1307}
1308
e763b90c
RK		 1309static inline void __stop_tx(struct uart_8250_port *p)
1310{
1311 if (p->ier & UART_IER_THRI) {
1312 p->ier &= ~UART_IER_THRI;
1313 serial_out(p, UART_IER, p->ier);
1314 }
1315}
1316
b129a8cc 1317static void serial8250_stop_tx(struct uart_port *port)
1da177e4 1318{
49d5741b
JI		 1319 struct uart_8250_port *up =
1320 container_of(port, struct uart_8250_port, port);
1da177e4 1321
e763b90c 1322 __stop_tx(up);
1da177e4
LT		 1323
1324 /*
e763b90c 1325 * We really want to stop the transmitter from sending.
1da177e4 1326 */
dfe42443 1327 if (port->type == PORT_16C950) {
1da177e4
LT		 1328 up->acr |= UART_ACR_TXDIS;
1329 serial_icr_write(up, UART_ACR, up->acr);
1330 }
1331}
1332
b129a8cc 1333static void serial8250_start_tx(struct uart_port *port)
1da177e4 1334{
49d5741b
JI		 1335 struct uart_8250_port *up =
1336 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1337
1338 if (!(up->ier & UART_IER_THRI)) {
1339 up->ier |= UART_IER_THRI;
4fd996a1 1340 serial_port_out(port, UART_IER, up->ier);
55d3b282 1341
67f7654e 1342 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1343 unsigned char lsr;
55d3b282 1344 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1345 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
dfe42443 1346 if ((port->type == PORT_RM9000) ?
68cb4f8e
IJ		 1347 (lsr & UART_LSR_THRE) :
1348 (lsr & UART_LSR_TEMT))
3986fb2b 1349 serial8250_tx_chars(up);
55d3b282 1350 }
1da177e4 1351 }
e763b90c 1352
1da177e4 1353 /*
e763b90c 1354 * Re-enable the transmitter if we disabled it.
1da177e4 1355 */
dfe42443 1356 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1357 up->acr &= ~UART_ACR_TXDIS;
1358 serial_icr_write(up, UART_ACR, up->acr);
1359 }
1360}
1361
1362static void serial8250_stop_rx(struct uart_port *port)
1363{
49d5741b
JI		 1364 struct uart_8250_port *up =
1365 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1366
1367 up->ier &= ~UART_IER_RLSI;
1368 up->port.read_status_mask &= ~UART_LSR_DR;
4fd996a1 1369 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 1370}
1371
1372static void serial8250_enable_ms(struct uart_port *port)
1373{
49d5741b
JI		 1374 struct uart_8250_port *up =
1375 container_of(port, struct uart_8250_port, port);
1da177e4 1376
21c614a7
PA		 1377 /* no MSR capabilities */
1378 if (up->bugs & UART_BUG_NOMSR)
1379 return;
1380
1da177e4 1381 up->ier |= UART_IER_MSI;
4fd996a1 1382 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 1383}
1384
0690f41f 1385/*
3986fb2b 1386 * serial8250_rx_chars: processes according to the passed in LSR
0690f41f
PG		 1387 * value, and returns the remaining LSR bits not handled
1388 * by this Rx routine.
1389 */
3986fb2b
PG		 1390unsigned char
1391serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1da177e4 1392{
dfe42443
PG		 1393 struct uart_port *port = &up->port;
1394 struct tty_struct *tty = port->state->port.tty;
0690f41f 1395 unsigned char ch;
1da177e4
LT		 1396 int max_count = 256;
1397 char flag;
1398
1399 do {
7500b1f6 1400 if (likely(lsr & UART_LSR_DR))
0acf519f 1401 ch = serial_in(up, UART_RX);
7500b1f6
AR		 1402 else
1403 /*
1404 * Intel 82571 has a Serial Over Lan device that will
1405 * set UART_LSR_BI without setting UART_LSR_DR when
1406 * it receives a break. To avoid reading from the
1407 * receive buffer without UART_LSR_DR bit set, we
1408 * just force the read character to be 0
1409 */
1410 ch = 0;
1411
1da177e4 1412 flag = TTY_NORMAL;
dfe42443 1413 port->icount.rx++;
1da177e4 1414
ad4c2aa6
CM		 1415 lsr |= up->lsr_saved_flags;
1416 up->lsr_saved_flags = 0;
1da177e4 1417
ad4c2aa6 1418 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1419 if (lsr & UART_LSR_BI) {
1420 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
dfe42443 1421 port->icount.brk++;
1da177e4
LT		 1422 /*
1423 * We do the SysRQ and SAK checking
1424 * here because otherwise the break
1425 * may get masked by ignore_status_mask
1426 * or read_status_mask.
1427 */
dfe42443 1428 if (uart_handle_break(port))
1da177e4
LT		 1429 goto ignore_char;
1430 } else if (lsr & UART_LSR_PE)
dfe42443 1431 port->icount.parity++;
1da177e4 1432 else if (lsr & UART_LSR_FE)
dfe42443 1433 port->icount.frame++;
1da177e4 1434 if (lsr & UART_LSR_OE)
dfe42443 1435 port->icount.overrun++;
1da177e4
LT		 1436
1437 /*
23907eb8 1438 * Mask off conditions which should be ignored.
1da177e4 1439 */
dfe42443 1440 lsr &= port->read_status_mask;
1da177e4
LT		 1441
1442 if (lsr & UART_LSR_BI) {
1443 DEBUG_INTR("handling break....");
1444 flag = TTY_BREAK;
1445 } else if (lsr & UART_LSR_PE)
1446 flag = TTY_PARITY;
1447 else if (lsr & UART_LSR_FE)
1448 flag = TTY_FRAME;
1449 }
dfe42443 1450 if (uart_handle_sysrq_char(port, ch))
1da177e4 1451 goto ignore_char;
05ab3014 1452
dfe42443 1453 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
05ab3014 1454
6f803cd0 1455ignore_char:
0acf519f 1456 lsr = serial_in(up, UART_LSR);
7500b1f6 1457 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
dfe42443 1458 spin_unlock(&port->lock);
1da177e4 1459 tty_flip_buffer_push(tty);
dfe42443 1460 spin_lock(&port->lock);
0690f41f 1461 return lsr;
1da177e4 1462}
3986fb2b 1463EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1da177e4 1464
3986fb2b 1465void serial8250_tx_chars(struct uart_8250_port *up)
1da177e4 1466{
dfe42443
PG		 1467 struct uart_port *port = &up->port;
1468 struct circ_buf *xmit = &port->state->xmit;
1da177e4
LT		 1469 int count;
1470
dfe42443
PG		 1471 if (port->x_char) {
1472 serial_out(up, UART_TX, port->x_char);
1473 port->icount.tx++;
1474 port->x_char = 0;
1da177e4
LT		 1475 return;
1476 }
dfe42443
PG		 1477 if (uart_tx_stopped(port)) {
1478 serial8250_stop_tx(port);
b129a8cc
RK		 1479 return;
1480 }
1481 if (uart_circ_empty(xmit)) {
e763b90c 1482 __stop_tx(up);
1da177e4
LT		 1483 return;
1484 }
1485
1486 count = up->tx_loadsz;
1487 do {
1488 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1489 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
dfe42443 1490 port->icount.tx++;
1da177e4
LT		 1491 if (uart_circ_empty(xmit))
1492 break;
1493 } while (--count > 0);
1494
1495 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
dfe42443 1496 uart_write_wakeup(port);
1da177e4
LT		 1497
1498 DEBUG_INTR("THRE...");
1499
1500 if (uart_circ_empty(xmit))
e763b90c 1501 __stop_tx(up);
1da177e4 1502}
3986fb2b 1503EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1da177e4 1504
3986fb2b 1505unsigned int serial8250_modem_status(struct uart_8250_port *up)
1da177e4 1506{
dfe42443 1507 struct uart_port *port = &up->port;
2af7cd68
RK		 1508 unsigned int status = serial_in(up, UART_MSR);
1509
ad4c2aa6
CM		 1510 status |= up->msr_saved_flags;
1511 up->msr_saved_flags = 0;
fdc30b3d 1512 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
dfe42443 1513 port->state != NULL) {
2af7cd68 1514 if (status & UART_MSR_TERI)
dfe42443 1515 port->icount.rng++;
2af7cd68 1516 if (status & UART_MSR_DDSR)
dfe42443 1517 port->icount.dsr++;
2af7cd68 1518 if (status & UART_MSR_DDCD)
dfe42443 1519 uart_handle_dcd_change(port, status & UART_MSR_DCD);
2af7cd68 1520 if (status & UART_MSR_DCTS)
dfe42443 1521 uart_handle_cts_change(port, status & UART_MSR_CTS);
2af7cd68 1522
dfe42443 1523 wake_up_interruptible(&port->state->port.delta_msr_wait);
2af7cd68 1524 }
1da177e4 1525
2af7cd68 1526 return status;
1da177e4 1527}
3986fb2b 1528EXPORT_SYMBOL_GPL(serial8250_modem_status);
1da177e4
LT		 1529
1530/*
1531 * This handles the interrupt from one port.
1532 */
86b21199 1533int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1da177e4 1534{
0690f41f 1535 unsigned char status;
4bf3631c 1536 unsigned long flags;
86b21199
PG		 1537 struct uart_8250_port *up =
1538 container_of(port, struct uart_8250_port, port);
1539
1540 if (iir & UART_IIR_NO_INT)
1541 return 0;
45e24601 1542
dfe42443 1543 spin_lock_irqsave(&port->lock, flags);
45e24601 1544
4fd996a1 1545 status = serial_port_in(port, UART_LSR);
1da177e4
LT		 1546
1547 DEBUG_INTR("status = %x...", status);
1548
7500b1f6 1549 if (status & (UART_LSR_DR | UART_LSR_BI))
3986fb2b
PG		 1550 status = serial8250_rx_chars(up, status);
1551 serial8250_modem_status(up);
1da177e4 1552 if (status & UART_LSR_THRE)
3986fb2b 1553 serial8250_tx_chars(up);
45e24601 1554
dfe42443 1555 spin_unlock_irqrestore(&port->lock, flags);
86b21199 1556 return 1;
583d28e9 1557}
c7a1bdc5 1558EXPORT_SYMBOL_GPL(serial8250_handle_irq);
583d28e9
JI		 1559
1560static int serial8250_default_handle_irq(struct uart_port *port)
1561{
4fd996a1 1562 unsigned int iir = serial_port_in(port, UART_IIR);
583d28e9
JI		 1563
1564 return serial8250_handle_irq(port, iir);
1565}
1566
dc96efb7
MS		 1567/*
1568 * These Exar UARTs have an extra interrupt indicator that could
1569 * fire for a few unimplemented interrupts. One of which is a
1570 * wakeup event when coming out of sleep. Put this here just
1571 * to be on the safe side that these interrupts don't go unhandled.
1572 */
1573static int exar_handle_irq(struct uart_port *port)
1574{
1575 unsigned char int0, int1, int2, int3;
1576 unsigned int iir = serial_port_in(port, UART_IIR);
1577 int ret;
1578
1579 ret = serial8250_handle_irq(port, iir);
1580
30fa96a3
MS		 1581 if ((port->type == PORT_XR17V35X) ||
1582 (port->type == PORT_XR17D15X)) {
dc96efb7
MS		 1583 int0 = serial_port_in(port, 0x80);
1584 int1 = serial_port_in(port, 0x81);
1585 int2 = serial_port_in(port, 0x82);
1586 int3 = serial_port_in(port, 0x83);
1587 }
1588
1589 return ret;
1590}
1591
1da177e4
LT		 1592/*
1593 * This is the serial driver's interrupt routine.
1594 *
1595 * Arjan thinks the old way was overly complex, so it got simplified.
1596 * Alan disagrees, saying that need the complexity to handle the weird
1597 * nature of ISA shared interrupts. (This is a special exception.)
1598 *
1599 * In order to handle ISA shared interrupts properly, we need to check
1600 * that all ports have been serviced, and therefore the ISA interrupt
1601 * line has been de-asserted.
1602 *
1603 * This means we need to loop through all ports. checking that they
1604 * don't have an interrupt pending.
1605 */
7d12e780 1606static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1607{
1608 struct irq_info *i = dev_id;
1609 struct list_head *l, *end = NULL;
1610 int pass_counter = 0, handled = 0;
1611
1612 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1613
1614 spin_lock(&i->lock);
1615
1616 l = i->head;
1617 do {
1618 struct uart_8250_port *up;
583d28e9 1619 struct uart_port *port;
1da177e4
LT		 1620
1621 up = list_entry(l, struct uart_8250_port, list);
583d28e9 1622 port = &up->port;
1da177e4 1623
49b532f9 1624 if (port->handle_irq(port)) {
1da177e4 1625 handled = 1;
1da177e4
LT		 1626 end = NULL;
1627 } else if (end == NULL)
1628 end = l;
1629
1630 l = l->next;
1631
1632 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1633 /* If we hit this, we're dead. */
cd3ecad1
DD		 1634 printk_ratelimited(KERN_ERR
1635 "serial8250: too much work for irq%d\n", irq);
1da177e4
LT		 1636 break;
1637 }
1638 } while (l != end);
1639
1640 spin_unlock(&i->lock);
1641
1642 DEBUG_INTR("end.\n");
1643
1644 return IRQ_RETVAL(handled);
1645}
1646
1647/*
1648 * To support ISA shared interrupts, we need to have one interrupt
1649 * handler that ensures that the IRQ line has been deasserted
1650 * before returning. Failing to do this will result in the IRQ
1651 * line being stuck active, and, since ISA irqs are edge triggered,
1652 * no more IRQs will be seen.
1653 */
1654static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1655{
1656 spin_lock_irq(&i->lock);
1657
1658 if (!list_empty(i->head)) {
1659 if (i->head == &up->list)
1660 i->head = i->head->next;
1661 list_del(&up->list);
1662 } else {
1663 BUG_ON(i->head != &up->list);
1664 i->head = NULL;
1665 }
1da177e4 1666 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1667 /* List empty so throw away the hash node */
1668 if (i->head == NULL) {
1669 hlist_del(&i->node);
1670 kfree(i);
1671 }
1da177e4
LT		 1672}
1673
1674static int serial_link_irq_chain(struct uart_8250_port *up)
1675{
25db8ad5
AC		 1676 struct hlist_head *h;
1677 struct hlist_node *n;
1678 struct irq_info *i;
40663cc7 1679 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1680
25db8ad5
AC		 1681 mutex_lock(&hash_mutex);
1682
1683 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1684
1685 hlist_for_each(n, h) {
1686 i = hlist_entry(n, struct irq_info, node);
1687 if (i->irq == up->port.irq)
1688 break;
1689 }
1690
1691 if (n == NULL) {
1692 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1693 if (i == NULL) {
1694 mutex_unlock(&hash_mutex);
1695 return -ENOMEM;
1696 }
1697 spin_lock_init(&i->lock);
1698 i->irq = up->port.irq;
1699 hlist_add_head(&i->node, h);
1700 }
1701 mutex_unlock(&hash_mutex);
1702
1da177e4
LT		 1703 spin_lock_irq(&i->lock);
1704
1705 if (i->head) {
1706 list_add(&up->list, i->head);
1707 spin_unlock_irq(&i->lock);
1708
1709 ret = 0;
1710 } else {
1711 INIT_LIST_HEAD(&up->list);
1712 i->head = &up->list;
1713 spin_unlock_irq(&i->lock);
1c2f0493 1714 irq_flags |= up->port.irqflags;
1da177e4
LT		 1715 ret = request_irq(up->port.irq, serial8250_interrupt,
1716 irq_flags, "serial", i);
1717 if (ret < 0)
1718 serial_do_unlink(i, up);
1719 }
1720
1721 return ret;
1722}
1723
1724static void serial_unlink_irq_chain(struct uart_8250_port *up)
1725{
25db8ad5
AC		 1726 struct irq_info *i;
1727 struct hlist_node *n;
1728 struct hlist_head *h;
1da177e4 1729
25db8ad5
AC		 1730 mutex_lock(&hash_mutex);
1731
1732 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1733
1734 hlist_for_each(n, h) {
1735 i = hlist_entry(n, struct irq_info, node);
1736 if (i->irq == up->port.irq)
1737 break;
1738 }
1739
1740 BUG_ON(n == NULL);
1da177e4
LT		 1741 BUG_ON(i->head == NULL);
1742
1743 if (list_empty(i->head))
1744 free_irq(up->port.irq, i);
1745
1746 serial_do_unlink(i, up);
25db8ad5 1747 mutex_unlock(&hash_mutex);
1da177e4
LT		 1748}
1749
1750/*
1751 * This function is used to handle ports that do not have an
1752 * interrupt. This doesn't work very well for 16450's, but gives
1753 * barely passable results for a 16550A. (Although at the expense
1754 * of much CPU overhead).
1755 */
1756static void serial8250_timeout(unsigned long data)
1757{
1758 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4 1759
a0431476 1760 up->port.handle_irq(&up->port);
54381067 1761 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
40b36daa
AW		 1762}
1763
1764static void serial8250_backup_timeout(unsigned long data)
1765{
1766 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1767 unsigned int iir, ier = 0, lsr;
1768 unsigned long flags;
40b36daa 1769
dbb3b1ca
AC		 1770 spin_lock_irqsave(&up->port.lock, flags);
1771
40b36daa
AW		 1772 /*
1773 * Must disable interrupts or else we risk racing with the interrupt
1774 * based handler.
1775 */
d4e33fac 1776 if (up->port.irq) {
40b36daa
AW		 1777 ier = serial_in(up, UART_IER);
1778 serial_out(up, UART_IER, 0);
1779 }
1da177e4 1780
40b36daa
AW		 1781 iir = serial_in(up, UART_IIR);
1782
1783 /*
1784 * This should be a safe test for anyone who doesn't trust the
1785 * IIR bits on their UART, but it's specifically designed for
1786 * the "Diva" UART used on the management processor on many HP
1787 * ia64 and parisc boxes.
1788 */
ad4c2aa6
CM		 1789 lsr = serial_in(up, UART_LSR);
1790 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
40b36daa 1791 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1792 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1793 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1794 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1795 iir |= UART_IIR_THRI;
1796 }
1797
1798 if (!(iir & UART_IIR_NO_INT))
3986fb2b 1799 serial8250_tx_chars(up);
40b36daa 1800
d4e33fac 1801 if (up->port.irq)
40b36daa
AW		 1802 serial_out(up, UART_IER, ier);
1803
dbb3b1ca
AC		 1804 spin_unlock_irqrestore(&up->port.lock, flags);
1805
40b36daa 1806 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0 1807 mod_timer(&up->timer,
54381067 1808 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1da177e4
LT		 1809}
1810
1811static unsigned int serial8250_tx_empty(struct uart_port *port)
1812{
49d5741b
JI		 1813 struct uart_8250_port *up =
1814 container_of(port, struct uart_8250_port, port);
1da177e4 1815 unsigned long flags;
ad4c2aa6 1816 unsigned int lsr;
1da177e4 1817
dfe42443 1818 spin_lock_irqsave(&port->lock, flags);
4fd996a1 1819 lsr = serial_port_in(port, UART_LSR);
ad4c2aa6 1820 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
dfe42443 1821 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 1822
bca47613 1823 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1824}
1825
1826static unsigned int serial8250_get_mctrl(struct uart_port *port)
1827{
49d5741b
JI		 1828 struct uart_8250_port *up =
1829 container_of(port, struct uart_8250_port, port);
2af7cd68 1830 unsigned int status;
1da177e4
LT		 1831 unsigned int ret;
1832
3986fb2b 1833 status = serial8250_modem_status(up);
1da177e4
LT		 1834
1835 ret = 0;
1836 if (status & UART_MSR_DCD)
1837 ret |= TIOCM_CAR;
1838 if (status & UART_MSR_RI)
1839 ret |= TIOCM_RNG;
1840 if (status & UART_MSR_DSR)
1841 ret |= TIOCM_DSR;
1842 if (status & UART_MSR_CTS)
1843 ret |= TIOCM_CTS;
1844 return ret;
1845}
1846
1847static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1848{
49d5741b
JI		 1849 struct uart_8250_port *up =
1850 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1851 unsigned char mcr = 0;
1852
1853 if (mctrl & TIOCM_RTS)
1854 mcr |= UART_MCR_RTS;
1855 if (mctrl & TIOCM_DTR)
1856 mcr |= UART_MCR_DTR;
1857 if (mctrl & TIOCM_OUT1)
1858 mcr |= UART_MCR_OUT1;
1859 if (mctrl & TIOCM_OUT2)
1860 mcr |= UART_MCR_OUT2;
1861 if (mctrl & TIOCM_LOOP)
1862 mcr |= UART_MCR_LOOP;
1863
1864 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1865
4fd996a1 1866 serial_port_out(port, UART_MCR, mcr);
1da177e4
LT		 1867}
1868
1869static void serial8250_break_ctl(struct uart_port *port, int break_state)
1870{
49d5741b
JI		 1871 struct uart_8250_port *up =
1872 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1873 unsigned long flags;
1874
dfe42443 1875 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 1876 if (break_state == -1)
1877 up->lcr |= UART_LCR_SBC;
1878 else
1879 up->lcr &= ~UART_LCR_SBC;
4fd996a1 1880 serial_port_out(port, UART_LCR, up->lcr);
dfe42443 1881 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1882}
1883
40b36daa
AW		 1884/*
1885 * Wait for transmitter & holding register to empty
1886 */
b5d674ab 1887static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1888{
1889 unsigned int status, tmout = 10000;
1890
1891 /* Wait up to 10ms for the character(s) to be sent. */
97d303b7 1892 for (;;) {
40b36daa
AW		 1893 status = serial_in(up, UART_LSR);
1894
ad4c2aa6 1895 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa 1896
97d303b7
DD		 1897 if ((status & bits) == bits)
1898 break;
40b36daa
AW		 1899 if (--tmout == 0)
1900 break;
1901 udelay(1);
97d303b7 1902 }
40b36daa
AW		 1903
1904 /* Wait up to 1s for flow control if necessary */
1905 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1906 unsigned int tmout;
1907 for (tmout = 1000000; tmout; tmout--) {
1908 unsigned int msr = serial_in(up, UART_MSR);
1909 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1910 if (msr & UART_MSR_CTS)
1911 break;
40b36daa
AW		 1912 udelay(1);
1913 touch_nmi_watchdog();
1914 }
1915 }
1916}
1917
f2d937f3
JW		 1918#ifdef CONFIG_CONSOLE_POLL
1919/*
1920 * Console polling routines for writing and reading from the uart while
1921 * in an interrupt or debug context.
1922 */
1923
1924static int serial8250_get_poll_char(struct uart_port *port)
1925{
4fd996a1 1926 unsigned char lsr = serial_port_in(port, UART_LSR);
f2d937f3 1927
f5316b4a
JW		 1928 if (!(lsr & UART_LSR_DR))
1929 return NO_POLL_CHAR;
f2d937f3 1930
4fd996a1 1931 return serial_port_in(port, UART_RX);
f2d937f3
JW		 1932}
1933
1934
1935static void serial8250_put_poll_char(struct uart_port *port,
1936 unsigned char c)
1937{
1938 unsigned int ier;
49d5741b
JI		 1939 struct uart_8250_port *up =
1940 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1941
1942 /*
1943 * First save the IER then disable the interrupts
1944 */
4fd996a1 1945 ier = serial_port_in(port, UART_IER);
f2d937f3 1946 if (up->capabilities & UART_CAP_UUE)
4fd996a1 1947 serial_port_out(port, UART_IER, UART_IER_UUE);
f2d937f3 1948 else
4fd996a1 1949 serial_port_out(port, UART_IER, 0);
f2d937f3
JW		 1950
1951 wait_for_xmitr(up, BOTH_EMPTY);
1952 /*
1953 * Send the character out.
1954 * If a LF, also do CR...
1955 */
4fd996a1 1956 serial_port_out(port, UART_TX, c);
f2d937f3
JW		 1957 if (c == 10) {
1958 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 1959 serial_port_out(port, UART_TX, 13);
f2d937f3
JW		 1960 }
1961
1962 /*
1963 * Finally, wait for transmitter to become empty
1964 * and restore the IER
1965 */
1966 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 1967 serial_port_out(port, UART_IER, ier);
f2d937f3
JW		 1968}
1969
1970#endif /* CONFIG_CONSOLE_POLL */
1971
1da177e4
LT		 1972static int serial8250_startup(struct uart_port *port)
1973{
49d5741b
JI		 1974 struct uart_8250_port *up =
1975 container_of(port, struct uart_8250_port, port);
1da177e4 1976 unsigned long flags;
55d3b282 1977 unsigned char lsr, iir;
1da177e4
LT		 1978 int retval;
1979
65ecc9c0
SY		 1980 if (port->type == PORT_8250_CIR)
1981 return -ENODEV;
1982
dfe42443 1983 port->fifosize = uart_config[up->port.type].fifo_size;
e4f05af1 1984 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1da177e4
LT		 1985 up->capabilities = uart_config[up->port.type].flags;
1986 up->mcr = 0;
1987
dfe42443 1988 if (port->iotype != up->cur_iotype)
b8e7e40a
AC		 1989 set_io_from_upio(port);
1990
dfe42443 1991 if (port->type == PORT_16C950) {
1da177e4
LT		 1992 /* Wake up and initialize UART */
1993 up->acr = 0;
4fd996a1
PG		 1994 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1995 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1996 serial_port_out(port, UART_IER, 0);
1997 serial_port_out(port, UART_LCR, 0);
1da177e4 1998 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
4fd996a1
PG		 1999 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2000 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2001 serial_port_out(port, UART_LCR, 0);
1da177e4
LT		 2002 }
2003
2004#ifdef CONFIG_SERIAL_8250_RSA
2005 /*
2006 * If this is an RSA port, see if we can kick it up to the
2007 * higher speed clock.
2008 */
2009 enable_rsa(up);
2010#endif
2011
2012 /*
2013 * Clear the FIFO buffers and disable them.
7f927fcc 2014 * (they will be reenabled in set_termios())
1da177e4
LT		 2015 */
2016 serial8250_clear_fifos(up);
2017
2018 /*
2019 * Clear the interrupt registers.
2020 */
4fd996a1
PG		 2021 serial_port_in(port, UART_LSR);
2022 serial_port_in(port, UART_RX);
2023 serial_port_in(port, UART_IIR);
2024 serial_port_in(port, UART_MSR);
1da177e4
LT		 2025
2026 /*
2027 * At this point, there's no way the LSR could still be 0xff;
2028 * if it is, then bail out, because there's likely no UART
2029 * here.
2030 */
dfe42443 2031 if (!(port->flags & UPF_BUGGY_UART) &&
4fd996a1 2032 (serial_port_in(port, UART_LSR) == 0xff)) {
7808a4c4 2033 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
dfe42443 2034 serial_index(port));
1da177e4
LT		 2035 return -ENODEV;
2036 }
2037
2038 /*
2039 * For a XR16C850, we need to set the trigger levels
2040 */
dfe42443 2041 if (port->type == PORT_16850) {
1da177e4
LT		 2042 unsigned char fctr;
2043
0acf519f 2044 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4 2045
0acf519f 2046 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
4fd996a1
PG		 2047 serial_port_out(port, UART_FCTR,
2048 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2049 serial_port_out(port, UART_TRG, UART_TRG_96);
2050 serial_port_out(port, UART_FCTR,
2051 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2052 serial_port_out(port, UART_TRG, UART_TRG_96);
1da177e4 2053
4fd996a1 2054 serial_port_out(port, UART_LCR, 0);
1da177e4
LT		 2055 }
2056
dfe42443 2057 if (port->irq) {
01c194d9 2058 unsigned char iir1;
40b36daa
AW		 2059 /*
2060 * Test for UARTs that do not reassert THRE when the
2061 * transmitter is idle and the interrupt has already
2062 * been cleared. Real 16550s should always reassert
2063 * this interrupt whenever the transmitter is idle and
2064 * the interrupt is enabled. Delays are necessary to
2065 * allow register changes to become visible.
2066 */
dfe42443 2067 spin_lock_irqsave(&port->lock, flags);
1c2f0493 2068 if (up->port.irqflags & IRQF_SHARED)
dfe42443 2069 disable_irq_nosync(port->irq);
40b36daa
AW		 2070
2071 wait_for_xmitr(up, UART_LSR_THRE);
55e4016d 2072 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
40b36daa 2073 udelay(1); /* allow THRE to set */
4fd996a1
PG		 2074 iir1 = serial_port_in(port, UART_IIR);
2075 serial_port_out(port, UART_IER, 0);
55e4016d 2076 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
40b36daa 2077 udelay(1); /* allow a working UART time to re-assert THRE */
4fd996a1
PG		 2078 iir = serial_port_in(port, UART_IIR);
2079 serial_port_out(port, UART_IER, 0);
40b36daa 2080
dfe42443
PG		 2081 if (port->irqflags & IRQF_SHARED)
2082 enable_irq(port->irq);
2083 spin_unlock_irqrestore(&port->lock, flags);
40b36daa
AW		 2084
2085 /*
bc02d15a
DW		 2086 * If the interrupt is not reasserted, or we otherwise
2087 * don't trust the iir, setup a timer to kick the UART
2088 * on a regular basis.
40b36daa 2089 */
bc02d15a
DW		 2090 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2091 up->port.flags & UPF_BUG_THRE) {
363f66fe 2092 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2093 pr_debug("ttyS%d - using backup timer\n",
2094 serial_index(port));
40b36daa
AW		 2095 }
2096 }
2097
363f66fe
WN		 2098 /*
2099 * The above check will only give an accurate result the first time
2100 * the port is opened so this value needs to be preserved.
2101 */
2102 if (up->bugs & UART_BUG_THRE) {
2103 up->timer.function = serial8250_backup_timeout;
2104 up->timer.data = (unsigned long)up;
2105 mod_timer(&up->timer, jiffies +
54381067 2106 uart_poll_timeout(port) + HZ / 5);
363f66fe
WN		 2107 }
2108
1da177e4
LT		 2109 /*
2110 * If the "interrupt" for this port doesn't correspond with any
2111 * hardware interrupt, we use a timer-based system. The original
2112 * driver used to do this with IRQ0.
2113 */
dfe42443 2114 if (!port->irq) {
1da177e4 2115 up->timer.data = (unsigned long)up;
54381067 2116 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
1da177e4
LT		 2117 } else {
2118 retval = serial_link_irq_chain(up);
2119 if (retval)
2120 return retval;
2121 }
2122
2123 /*
2124 * Now, initialize the UART
2125 */
4fd996a1 2126 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
1da177e4 2127
dfe42443 2128 spin_lock_irqsave(&port->lock, flags);
1da177e4 2129 if (up->port.flags & UPF_FOURPORT) {
d4e33fac 2130 if (!up->port.irq)
1da177e4
LT		 2131 up->port.mctrl |= TIOCM_OUT1;
2132 } else
2133 /*
2134 * Most PC uarts need OUT2 raised to enable interrupts.
2135 */
dfe42443 2136 if (port->irq)
1da177e4
LT		 2137 up->port.mctrl |= TIOCM_OUT2;
2138
dfe42443 2139 serial8250_set_mctrl(port, port->mctrl);
55d3b282 2140
b6adea33
MCC		 2141 /* Serial over Lan (SoL) hack:
2142 Intel 8257x Gigabit ethernet chips have a
2143 16550 emulation, to be used for Serial Over Lan.
2144 Those chips take a longer time than a normal
2145 serial device to signalize that a transmission
2146 data was queued. Due to that, the above test generally
2147 fails. One solution would be to delay the reading of
2148 iir. However, this is not reliable, since the timeout
2149 is variable. So, let's just don't test if we receive
2150 TX irq. This way, we'll never enable UART_BUG_TXEN.
2151 */
d41a4b51 2152 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2153 goto dont_test_tx_en;
2154
55d3b282
RK		 2155 /*
2156 * Do a quick test to see if we receive an
2157 * interrupt when we enable the TX irq.
2158 */
4fd996a1
PG		 2159 serial_port_out(port, UART_IER, UART_IER_THRI);
2160 lsr = serial_port_in(port, UART_LSR);
2161 iir = serial_port_in(port, UART_IIR);
2162 serial_port_out(port, UART_IER, 0);
55d3b282
RK		 2163
2164 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2165 if (!(up->bugs & UART_BUG_TXEN)) {
2166 up->bugs |= UART_BUG_TXEN;
55d3b282 2167 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2168 serial_index(port));
55d3b282
RK		 2169 }
2170 } else {
67f7654e 2171 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2172 }
2173
b6adea33 2174dont_test_tx_en:
dfe42443 2175 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 2176
ad4c2aa6
CM		 2177 /*
2178 * Clear the interrupt registers again for luck, and clear the
2179 * saved flags to avoid getting false values from polling
2180 * routines or the previous session.
2181 */
4fd996a1
PG		 2182 serial_port_in(port, UART_LSR);
2183 serial_port_in(port, UART_RX);
2184 serial_port_in(port, UART_IIR);
2185 serial_port_in(port, UART_MSR);
ad4c2aa6
CM		 2186 up->lsr_saved_flags = 0;
2187 up->msr_saved_flags = 0;
2188
1da177e4
LT		 2189 /*
2190 * Finally, enable interrupts. Note: Modem status interrupts
2191 * are set via set_termios(), which will be occurring imminently
2192 * anyway, so we don't enable them here.
2193 */
2194 up->ier = UART_IER_RLSI | UART_IER_RDI;
4fd996a1 2195 serial_port_out(port, UART_IER, up->ier);
1da177e4 2196
dfe42443 2197 if (port->flags & UPF_FOURPORT) {
1da177e4
LT		 2198 unsigned int icp;
2199 /*
2200 * Enable interrupts on the AST Fourport board
2201 */
dfe42443 2202 icp = (port->iobase & 0xfe0) | 0x01f;
1da177e4 2203 outb_p(0x80, icp);
0d263a26 2204 inb_p(icp);
1da177e4
LT		 2205 }
2206
1da177e4
LT		 2207 return 0;
2208}
2209
2210static void serial8250_shutdown(struct uart_port *port)
2211{
49d5741b
JI		 2212 struct uart_8250_port *up =
2213 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2214 unsigned long flags;
2215
2216 /*
2217 * Disable interrupts from this port
2218 */
2219 up->ier = 0;
4fd996a1 2220 serial_port_out(port, UART_IER, 0);
1da177e4 2221
dfe42443
PG		 2222 spin_lock_irqsave(&port->lock, flags);
2223 if (port->flags & UPF_FOURPORT) {
1da177e4 2224 /* reset interrupts on the AST Fourport board */
dfe42443
PG		 2225 inb((port->iobase & 0xfe0) | 0x1f);
2226 port->mctrl |= TIOCM_OUT1;
1da177e4 2227 } else
dfe42443 2228 port->mctrl &= ~TIOCM_OUT2;
1da177e4 2229
dfe42443
PG		 2230 serial8250_set_mctrl(port, port->mctrl);
2231 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 2232
2233 /*
2234 * Disable break condition and FIFOs
2235 */
4fd996a1
PG		 2236 serial_port_out(port, UART_LCR,
2237 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
1da177e4
LT		 2238 serial8250_clear_fifos(up);
2239
2240#ifdef CONFIG_SERIAL_8250_RSA
2241 /*
2242 * Reset the RSA board back to 115kbps compat mode.
2243 */
2244 disable_rsa(up);
2245#endif
2246
2247 /*
2248 * Read data port to reset things, and then unlink from
2249 * the IRQ chain.
2250 */
4fd996a1 2251 serial_port_in(port, UART_RX);
1da177e4 2252
40b36daa
AW		 2253 del_timer_sync(&up->timer);
2254 up->timer.function = serial8250_timeout;
dfe42443 2255 if (port->irq)
1da177e4
LT		 2256 serial_unlink_irq_chain(up);
2257}
2258
2259static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2260{
2261 unsigned int quot;
2262
2263 /*
2264 * Handle magic divisors for baud rates above baud_base on
2265 * SMSC SuperIO chips.
2266 */
2267 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2268 baud == (port->uartclk/4))
2269 quot = 0x8001;
2270 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2271 baud == (port->uartclk/8))
2272 quot = 0x8002;
2273 else
2274 quot = uart_get_divisor(port, baud);
2275
2276 return quot;
2277}
2278
235dae5d
PL		 2279void
2280serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2281 struct ktermios *old)
1da177e4 2282{
49d5741b
JI		 2283 struct uart_8250_port *up =
2284 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2285 unsigned char cval, fcr = 0;
2286 unsigned long flags;
2287 unsigned int baud, quot;
eb26dfe8 2288 int fifo_bug = 0;
1da177e4
LT		 2289
2290 switch (termios->c_cflag & CSIZE) {
2291 case CS5:
0a8b80c5 2292 cval = UART_LCR_WLEN5;
1da177e4
LT		 2293 break;
2294 case CS6:
0a8b80c5 2295 cval = UART_LCR_WLEN6;
1da177e4
LT		 2296 break;
2297 case CS7:
0a8b80c5 2298 cval = UART_LCR_WLEN7;
1da177e4
LT		 2299 break;
2300 default:
2301 case CS8:
0a8b80c5 2302 cval = UART_LCR_WLEN8;
1da177e4
LT		 2303 break;
2304 }
2305
2306 if (termios->c_cflag & CSTOPB)
0a8b80c5 2307 cval |= UART_LCR_STOP;
eb26dfe8 2308 if (termios->c_cflag & PARENB) {
1da177e4 2309 cval |= UART_LCR_PARITY;
eb26dfe8
AC		 2310 if (up->bugs & UART_BUG_PARITY)
2311 fifo_bug = 1;
2312 }
1da177e4
LT		 2313 if (!(termios->c_cflag & PARODD))
2314 cval |= UART_LCR_EPAR;
2315#ifdef CMSPAR
2316 if (termios->c_cflag & CMSPAR)
2317 cval |= UART_LCR_SPAR;
2318#endif
2319
2320 /*
2321 * Ask the core to calculate the divisor for us.
2322 */
24d481ec
AV		 2323 baud = uart_get_baud_rate(port, termios, old,
2324 port->uartclk / 16 / 0xffff,
2325 port->uartclk / 16);
1da177e4
LT		 2326 quot = serial8250_get_divisor(port, baud);
2327
2328 /*
4ba5e35d 2329 * Oxford Semi 952 rev B workaround
1da177e4 2330 */
4ba5e35d 2331 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2332 quot++;
1da177e4 2333
dfe42443 2334 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
f9a9111b 2335 fcr = uart_config[port->type].fcr;
eb26dfe8 2336 if (baud < 2400 || fifo_bug) {
f9a9111b
CM		 2337 fcr &= ~UART_FCR_TRIGGER_MASK;
2338 fcr |= UART_FCR_TRIGGER_1;
2339 }
1da177e4
LT		 2340 }
2341
2342 /*
2343 * MCR-based auto flow control. When AFE is enabled, RTS will be
2344 * deasserted when the receive FIFO contains more characters than
2345 * the trigger, or the MCR RTS bit is cleared. In the case where
2346 * the remote UART is not using CTS auto flow control, we must
2347 * have sufficient FIFO entries for the latency of the remote
2348 * UART to respond. IOW, at least 32 bytes of FIFO.
2349 */
dfe42443 2350 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
1da177e4
LT		 2351 up->mcr &= ~UART_MCR_AFE;
2352 if (termios->c_cflag & CRTSCTS)
2353 up->mcr |= UART_MCR_AFE;
2354 }
2355
2356 /*
2357 * Ok, we're now changing the port state. Do it with
2358 * interrupts disabled.
2359 */
dfe42443 2360 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 2361
2362 /*
2363 * Update the per-port timeout.
2364 */
2365 uart_update_timeout(port, termios->c_cflag, baud);
2366
dfe42443 2367 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1da177e4 2368 if (termios->c_iflag & INPCK)
dfe42443 2369 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1da177e4 2370 if (termios->c_iflag & (BRKINT | PARMRK))
dfe42443 2371 port->read_status_mask |= UART_LSR_BI;
1da177e4
LT		 2372
2373 /*
2374 * Characteres to ignore
2375 */
dfe42443 2376 port->ignore_status_mask = 0;
1da177e4 2377 if (termios->c_iflag & IGNPAR)
dfe42443 2378 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1da177e4 2379 if (termios->c_iflag & IGNBRK) {
dfe42443 2380 port->ignore_status_mask |= UART_LSR_BI;
1da177e4
LT		 2381 /*
2382 * If we're ignoring parity and break indicators,
2383 * ignore overruns too (for real raw support).
2384 */
2385 if (termios->c_iflag & IGNPAR)
dfe42443 2386 port->ignore_status_mask |= UART_LSR_OE;
1da177e4
LT		 2387 }
2388
2389 /*
2390 * ignore all characters if CREAD is not set
2391 */
2392 if ((termios->c_cflag & CREAD) == 0)
dfe42443 2393 port->ignore_status_mask |= UART_LSR_DR;
1da177e4
LT		 2394
2395 /*
2396 * CTS flow control flag and modem status interrupts
2397 */
f8b372a1 2398 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2399 if (!(up->bugs & UART_BUG_NOMSR) &&
2400 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2401 up->ier |= UART_IER_MSI;
2402 if (up->capabilities & UART_CAP_UUE)
4539c24f
SW		 2403 up->ier |= UART_IER_UUE;
2404 if (up->capabilities & UART_CAP_RTOIE)
2405 up->ier |= UART_IER_RTOIE;
1da177e4 2406
4fd996a1 2407 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 2408
2409 if (up->capabilities & UART_CAP_EFR) {
2410 unsigned char efr = 0;
2411 /*
2412 * TI16C752/Startech hardware flow control. FIXME:
2413 * - TI16C752 requires control thresholds to be set.
2414 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2415 */
2416 if (termios->c_cflag & CRTSCTS)
2417 efr |= UART_EFR_CTS;
2418
4fd996a1 2419 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
dfe42443 2420 if (port->flags & UPF_EXAR_EFR)
4fd996a1 2421 serial_port_out(port, UART_XR_EFR, efr);
06315348 2422 else
4fd996a1 2423 serial_port_out(port, UART_EFR, efr);
1da177e4
LT		 2424 }
2425
255341c6 2426 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
54ec52b6 2427 if (is_omap1510_8250(up)) {
255341c6
JM		 2428 if (baud == 115200) {
2429 quot = 1;
4fd996a1 2430 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
255341c6 2431 } else
4fd996a1 2432 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
255341c6 2433 }
255341c6 2434
4fd996a1
PG		 2435 /*
2436 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2437 * otherwise just set DLAB
2438 */
2439 if (up->capabilities & UART_NATSEMI)
2440 serial_port_out(port, UART_LCR, 0xe0);
2441 else
2442 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
1da177e4 2443
b32b19b8 2444 serial_dl_write(up, quot);
1da177e4
LT		 2445
2446 /*
2447 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2448 * is written without DLAB set, this mode will be disabled.
2449 */
dfe42443 2450 if (port->type == PORT_16750)
4fd996a1 2451 serial_port_out(port, UART_FCR, fcr);
1da177e4 2452
4fd996a1 2453 serial_port_out(port, UART_LCR, cval); /* reset DLAB */
1da177e4 2454 up->lcr = cval; /* Save LCR */
dfe42443 2455 if (port->type != PORT_16750) {
4fd996a1
PG		 2456 /* emulated UARTs (Lucent Venus 167x) need two steps */
2457 if (fcr & UART_FCR_ENABLE_FIFO)
2458 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2459 serial_port_out(port, UART_FCR, fcr); /* set fcr */
1da177e4 2460 }
dfe42443
PG		 2461 serial8250_set_mctrl(port, port->mctrl);
2462 spin_unlock_irqrestore(&port->lock, flags);
e991a2bd
AC		 2463 /* Don't rewrite B0 */
2464 if (tty_termios_baud_rate(termios))
2465 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4 2466}
235dae5d
PL		 2467EXPORT_SYMBOL(serial8250_do_set_termios);
2468
2469static void
2470serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2471 struct ktermios *old)
2472{
2473 if (port->set_termios)
2474 port->set_termios(port, termios, old);
2475 else
2476 serial8250_do_set_termios(port, termios, old);
2477}
1da177e4 2478
dc77f161 2479static void
a0821df6 2480serial8250_set_ldisc(struct uart_port *port, int new)
dc77f161 2481{
a0821df6 2482 if (new == N_PPS) {
dc77f161
RG		 2483 port->flags |= UPF_HARDPPS_CD;
2484 serial8250_enable_ms(port);
2485 } else
2486 port->flags &= ~UPF_HARDPPS_CD;
2487}
2488
c161afe9
ML		 2489
2490void serial8250_do_pm(struct uart_port *port, unsigned int state,
2491 unsigned int oldstate)
1da177e4 2492{
49d5741b
JI		 2493 struct uart_8250_port *p =
2494 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2495
2496 serial8250_set_sleep(p, state != 0);
c161afe9
ML		 2497}
2498EXPORT_SYMBOL(serial8250_do_pm);
1da177e4 2499
c161afe9
ML		 2500static void
2501serial8250_pm(struct uart_port *port, unsigned int state,
2502 unsigned int oldstate)
2503{
2504 if (port->pm)
2505 port->pm(port, state, oldstate);
2506 else
2507 serial8250_do_pm(port, state, oldstate);
1da177e4
LT		 2508}
2509
f2eda27d
RK		 2510static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2511{
2512 if (pt->port.iotype == UPIO_AU)
b2b13cdf 2513 return 0x1000;
54ec52b6 2514 if (is_omap1_8250(pt))
f2eda27d 2515 return 0x16 << pt->port.regshift;
54ec52b6 2516
f2eda27d
RK		 2517 return 8 << pt->port.regshift;
2518}
2519
1da177e4
LT		 2520/*
2521 * Resource handling.
2522 */
2523static int serial8250_request_std_resource(struct uart_8250_port *up)
2524{
f2eda27d 2525 unsigned int size = serial8250_port_size(up);
dfe42443 2526 struct uart_port *port = &up->port;
1da177e4
LT		 2527 int ret = 0;
2528
dfe42443 2529 switch (port->iotype) {
85835f44 2530 case UPIO_AU:
0b30d668
SS		 2531 case UPIO_TSI:
2532 case UPIO_MEM32:
1da177e4 2533 case UPIO_MEM:
dfe42443 2534 if (!port->mapbase)
1da177e4
LT		 2535 break;
2536
dfe42443 2537 if (!request_mem_region(port->mapbase, size, "serial")) {
1da177e4
LT		 2538 ret = -EBUSY;
2539 break;
2540 }
2541
dfe42443
PG		 2542 if (port->flags & UPF_IOREMAP) {
2543 port->membase = ioremap_nocache(port->mapbase, size);
2544 if (!port->membase) {
2545 release_mem_region(port->mapbase, size);
1da177e4
LT		 2546 ret = -ENOMEM;
2547 }
2548 }
2549 break;
2550
2551 case UPIO_HUB6:
2552 case UPIO_PORT:
dfe42443 2553 if (!request_region(port->iobase, size, "serial"))
1da177e4
LT		 2554 ret = -EBUSY;
2555 break;
2556 }
2557 return ret;
2558}
2559
2560static void serial8250_release_std_resource(struct uart_8250_port *up)
2561{
f2eda27d 2562 unsigned int size = serial8250_port_size(up);
dfe42443 2563 struct uart_port *port = &up->port;
1da177e4 2564
dfe42443 2565 switch (port->iotype) {
85835f44 2566 case UPIO_AU:
0b30d668
SS		 2567 case UPIO_TSI:
2568 case UPIO_MEM32:
1da177e4 2569 case UPIO_MEM:
dfe42443 2570 if (!port->mapbase)
1da177e4
LT		 2571 break;
2572
dfe42443
PG		 2573 if (port->flags & UPF_IOREMAP) {
2574 iounmap(port->membase);
2575 port->membase = NULL;
1da177e4
LT		 2576 }
2577
dfe42443 2578 release_mem_region(port->mapbase, size);
1da177e4
LT		 2579 break;
2580
2581 case UPIO_HUB6:
2582 case UPIO_PORT:
dfe42443 2583 release_region(port->iobase, size);
1da177e4
LT		 2584 break;
2585 }
2586}
2587
2588static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2589{
2590 unsigned long start = UART_RSA_BASE << up->port.regshift;
2591 unsigned int size = 8 << up->port.regshift;
dfe42443 2592 struct uart_port *port = &up->port;
0b30d668 2593 int ret = -EINVAL;
1da177e4 2594
dfe42443 2595 switch (port->iotype) {
1da177e4
LT		 2596 case UPIO_HUB6:
2597 case UPIO_PORT:
dfe42443 2598 start += port->iobase;
0b30d668
SS		 2599 if (request_region(start, size, "serial-rsa"))
2600 ret = 0;
2601 else
1da177e4
LT		 2602 ret = -EBUSY;
2603 break;
2604 }
2605
2606 return ret;
2607}
2608
2609static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2610{
2611 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2612 unsigned int size = 8 << up->port.regshift;
dfe42443 2613 struct uart_port *port = &up->port;
1da177e4 2614
dfe42443 2615 switch (port->iotype) {
1da177e4
LT		 2616 case UPIO_HUB6:
2617 case UPIO_PORT:
dfe42443 2618 release_region(port->iobase + offset, size);
1da177e4
LT		 2619 break;
2620 }
2621}
2622
2623static void serial8250_release_port(struct uart_port *port)
2624{
49d5741b
JI		 2625 struct uart_8250_port *up =
2626 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2627
2628 serial8250_release_std_resource(up);
dfe42443 2629 if (port->type == PORT_RSA)
1da177e4
LT		 2630 serial8250_release_rsa_resource(up);
2631}
2632
2633static int serial8250_request_port(struct uart_port *port)
2634{
49d5741b
JI		 2635 struct uart_8250_port *up =
2636 container_of(port, struct uart_8250_port, port);
65ecc9c0
SY		 2637 int ret;
2638
2639 if (port->type == PORT_8250_CIR)
2640 return -ENODEV;
1da177e4
LT		 2641
2642 ret = serial8250_request_std_resource(up);
dfe42443 2643 if (ret == 0 && port->type == PORT_RSA) {
1da177e4
LT		 2644 ret = serial8250_request_rsa_resource(up);
2645 if (ret < 0)
2646 serial8250_release_std_resource(up);
2647 }
2648
2649 return ret;
2650}
2651
2652static void serial8250_config_port(struct uart_port *port, int flags)
2653{
49d5741b
JI		 2654 struct uart_8250_port *up =
2655 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2656 int probeflags = PROBE_ANY;
2657 int ret;
2658
65ecc9c0
SY		 2659 if (port->type == PORT_8250_CIR)
2660 return;
2661
1da177e4
LT		 2662 /*
2663 * Find the region that we can probe for. This in turn
2664 * tells us whether we can probe for the type of port.
2665 */
2666 ret = serial8250_request_std_resource(up);
2667 if (ret < 0)
2668 return;
2669
2670 ret = serial8250_request_rsa_resource(up);
2671 if (ret < 0)
2672 probeflags &= ~PROBE_RSA;
2673
dfe42443 2674 if (port->iotype != up->cur_iotype)
b8e7e40a
AC		 2675 set_io_from_upio(port);
2676
1da177e4
LT		 2677 if (flags & UART_CONFIG_TYPE)
2678 autoconfig(up, probeflags);
b2b13cdf 2679
b2b13cdf 2680 /* if access method is AU, it is a 16550 with a quirk */
dfe42443 2681 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
b2b13cdf 2682 up->bugs |= UART_BUG_NOMSR;
b2b13cdf 2683
dfe42443 2684 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
1da177e4
LT		 2685 autoconfig_irq(up);
2686
dfe42443 2687 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
1da177e4 2688 serial8250_release_rsa_resource(up);
dfe42443 2689 if (port->type == PORT_UNKNOWN)
1da177e4 2690 serial8250_release_std_resource(up);
dc96efb7
MS		 2691
2692 /* Fixme: probably not the best place for this */
30fa96a3
MS		 2693 if ((port->type == PORT_XR17V35X) ||
2694 (port->type == PORT_XR17D15X))
dc96efb7 2695 port->handle_irq = exar_handle_irq;
1da177e4
LT		 2696}
2697
2698static int
2699serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2700{
a62c4133 2701 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2702 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2703 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2704 ser->type == PORT_STARTECH)
2705 return -EINVAL;
2706 return 0;
2707}
2708
2709static const char *
2710serial8250_type(struct uart_port *port)
2711{
2712 int type = port->type;
2713
2714 if (type >= ARRAY_SIZE(uart_config))
2715 type = 0;
2716 return uart_config[type].name;
2717}
2718
2719static struct uart_ops serial8250_pops = {
2720 .tx_empty = serial8250_tx_empty,
2721 .set_mctrl = serial8250_set_mctrl,
2722 .get_mctrl = serial8250_get_mctrl,
2723 .stop_tx = serial8250_stop_tx,
2724 .start_tx = serial8250_start_tx,
2725 .stop_rx = serial8250_stop_rx,
2726 .enable_ms = serial8250_enable_ms,
2727 .break_ctl = serial8250_break_ctl,
2728 .startup = serial8250_startup,
2729 .shutdown = serial8250_shutdown,
2730 .set_termios = serial8250_set_termios,
dc77f161 2731 .set_ldisc = serial8250_set_ldisc,
1da177e4
LT		 2732 .pm = serial8250_pm,
2733 .type = serial8250_type,
2734 .release_port = serial8250_release_port,
2735 .request_port = serial8250_request_port,
2736 .config_port = serial8250_config_port,
2737 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2738#ifdef CONFIG_CONSOLE_POLL
2739 .poll_get_char = serial8250_get_poll_char,
2740 .poll_put_char = serial8250_put_poll_char,
2741#endif
1da177e4
LT		 2742};
2743
2744static struct uart_8250_port serial8250_ports[UART_NR];
2745
af7f3743
AC		 2746static void (*serial8250_isa_config)(int port, struct uart_port *up,
2747 unsigned short *capabilities);
2748
2749void serial8250_set_isa_configurator(
2750 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2751{
2752 serial8250_isa_config = v;
2753}
2754EXPORT_SYMBOL(serial8250_set_isa_configurator);
2755
1da177e4
LT		 2756static void __init serial8250_isa_init_ports(void)
2757{
2758 struct uart_8250_port *up;
2759 static int first = 1;
4c0ebb80 2760 int i, irqflag = 0;
1da177e4
LT		 2761
2762 if (!first)
2763 return;
2764 first = 0;
2765
835d844d
SY		 2766 if (nr_uarts > UART_NR)
2767 nr_uarts = UART_NR;
2768
a61c2d78 2769 for (i = 0; i < nr_uarts; i++) {
1da177e4 2770 struct uart_8250_port *up = &serial8250_ports[i];
dfe42443 2771 struct uart_port *port = &up->port;
1da177e4 2772
dfe42443
PG		 2773 port->line = i;
2774 spin_lock_init(&port->lock);
1da177e4
LT		 2775
2776 init_timer(&up->timer);
2777 up->timer.function = serial8250_timeout;
835d844d 2778 up->cur_iotype = 0xFF;
1da177e4
LT		 2779
2780 /*
2781 * ALPHA_KLUDGE_MCR needs to be killed.
2782 */
2783 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2784 up->mcr_force = ALPHA_KLUDGE_MCR;
2785
dfe42443 2786 port->ops = &serial8250_pops;
1da177e4
LT		 2787 }
2788
4c0ebb80
AGR		 2789 if (share_irqs)
2790 irqflag = IRQF_SHARED;
2791
44454bcd 2792 for (i = 0, up = serial8250_ports;
a61c2d78 2793 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4 2794 i++, up++) {
dfe42443
PG		 2795 struct uart_port *port = &up->port;
2796
2797 port->iobase = old_serial_port[i].port;
2798 port->irq = irq_canonicalize(old_serial_port[i].irq);
2799 port->irqflags = old_serial_port[i].irqflags;
2800 port->uartclk = old_serial_port[i].baud_base * 16;
2801 port->flags = old_serial_port[i].flags;
2802 port->hub6 = old_serial_port[i].hub6;
2803 port->membase = old_serial_port[i].iomem_base;
2804 port->iotype = old_serial_port[i].io_type;
2805 port->regshift = old_serial_port[i].iomem_reg_shift;
2806 set_io_from_upio(port);
2807 port->irqflags |= irqflag;
af7f3743
AC		 2808 if (serial8250_isa_config != NULL)
2809 serial8250_isa_config(i, &up->port, &up->capabilities);
2810
1da177e4
LT		 2811 }
2812}
2813
b5d228cc
SL		 2814static void
2815serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2816{
2817 up->port.type = type;
2818 up->port.fifosize = uart_config[type].fifo_size;
2819 up->capabilities = uart_config[type].flags;
2820 up->tx_loadsz = uart_config[type].tx_loadsz;
2821}
2822
1da177e4
LT		 2823static void __init
2824serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2825{
2826 int i;
2827
b8e7e40a
AC		 2828 for (i = 0; i < nr_uarts; i++) {
2829 struct uart_8250_port *up = &serial8250_ports[i];
b8e7e40a 2830
835d844d
SY		 2831 if (up->port.dev)
2832 continue;
1da177e4
LT		 2833
2834 up->port.dev = dev;
b5d228cc
SL		 2835
2836 if (up->port.flags & UPF_FIXED_TYPE)
2837 serial8250_init_fixed_type_port(up, up->port.type);
2838
1da177e4
LT		 2839 uart_add_one_port(drv, &up->port);
2840 }
2841}
2842
2843#ifdef CONFIG_SERIAL_8250_CONSOLE
2844
d358788f
RK		 2845static void serial8250_console_putchar(struct uart_port *port, int ch)
2846{
49d5741b
JI		 2847 struct uart_8250_port *up =
2848 container_of(port, struct uart_8250_port, port);
d358788f
RK		 2849
2850 wait_for_xmitr(up, UART_LSR_THRE);
4fd996a1 2851 serial_port_out(port, UART_TX, ch);
d358788f
RK		 2852}
2853
1da177e4
LT		 2854/*
2855 * Print a string to the serial port trying not to disturb
2856 * any possible real use of the port...
2857 *
2858 * The console_lock must be held when we get here.
2859 */
2860static void
2861serial8250_console_write(struct console *co, const char *s, unsigned int count)
2862{
2863 struct uart_8250_port *up = &serial8250_ports[co->index];
dfe42443 2864 struct uart_port *port = &up->port;
d8a5a8d7 2865 unsigned long flags;
1da177e4 2866 unsigned int ier;
d8a5a8d7 2867 int locked = 1;
1da177e4 2868
78512ece
AM		 2869 touch_nmi_watchdog();
2870
68aa2c0d 2871 local_irq_save(flags);
dfe42443 2872 if (port->sysrq) {
86b21199 2873 /* serial8250_handle_irq() already took the lock */
68aa2c0d
AM		 2874 locked = 0;
2875 } else if (oops_in_progress) {
dfe42443 2876 locked = spin_trylock(&port->lock);
d8a5a8d7 2877 } else
dfe42443 2878 spin_lock(&port->lock);
d8a5a8d7 2879
1da177e4 2880 /*
dc7bf130 2881 * First save the IER then disable the interrupts
1da177e4 2882 */
4fd996a1 2883 ier = serial_port_in(port, UART_IER);
1da177e4
LT		 2884
2885 if (up->capabilities & UART_CAP_UUE)
4fd996a1 2886 serial_port_out(port, UART_IER, UART_IER_UUE);
1da177e4 2887 else
4fd996a1 2888 serial_port_out(port, UART_IER, 0);
1da177e4 2889
dfe42443 2890 uart_console_write(port, s, count, serial8250_console_putchar);
1da177e4
LT		 2891
2892 /*
2893 * Finally, wait for transmitter to become empty
2894 * and restore the IER
2895 */
f91a3715 2896 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 2897 serial_port_out(port, UART_IER, ier);
d8a5a8d7 2898
ad4c2aa6
CM		 2899 /*
2900 * The receive handling will happen properly because the
2901 * receive ready bit will still be set; it is not cleared
2902 * on read. However, modem control will not, we must
2903 * call it if we have saved something in the saved flags
2904 * while processing with interrupts off.
2905 */
2906 if (up->msr_saved_flags)
3986fb2b 2907 serial8250_modem_status(up);
ad4c2aa6 2908
d8a5a8d7 2909 if (locked)
dfe42443 2910 spin_unlock(&port->lock);
68aa2c0d 2911 local_irq_restore(flags);
1da177e4
LT		 2912}
2913
118c0ace 2914static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2915{
2916 struct uart_port *port;
2917 int baud = 9600;
2918 int bits = 8;
2919 int parity = 'n';
2920 int flow = 'n';
2921
2922 /*
2923 * Check whether an invalid uart number has been specified, and
2924 * if so, search for the first available port that does have
2925 * console support.
2926 */
a61c2d78 2927 if (co->index >= nr_uarts)
1da177e4
LT		 2928 co->index = 0;
2929 port = &serial8250_ports[co->index].port;
2930 if (!port->iobase && !port->membase)
2931 return -ENODEV;
2932
2933 if (options)
2934 uart_parse_options(options, &baud, &parity, &bits, &flow);
2935
2936 return uart_set_options(port, co, baud, parity, bits, flow);
2937}
2938
b6b1d877 2939static int serial8250_console_early_setup(void)
18a8bd94
YL		 2940{
2941 return serial8250_find_port_for_earlycon();
2942}
2943
1da177e4
LT		 2944static struct console serial8250_console = {
2945 .name = "ttyS",
2946 .write = serial8250_console_write,
2947 .device = uart_console_device,
2948 .setup = serial8250_console_setup,
18a8bd94 2949 .early_setup = serial8250_console_early_setup,
a80c49db 2950 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2951 .index = -1,
2952 .data = &serial8250_reg,
2953};
2954
2955static int __init serial8250_console_init(void)
2956{
2957 serial8250_isa_init_ports();
2958 register_console(&serial8250_console);
2959 return 0;
2960}
2961console_initcall(serial8250_console_init);
2962
18a8bd94 2963int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2964{
2965 int line;
2966 struct uart_port *port;
2967
a61c2d78 2968 for (line = 0; line < nr_uarts; line++) {
1da177e4 2969 port = &serial8250_ports[line].port;
50aec3b5 2970 if (uart_match_port(p, port))
1da177e4
LT		 2971 return line;
2972 }
2973 return -ENODEV;
2974}
2975
1da177e4
LT		 2976#define SERIAL8250_CONSOLE &serial8250_console
2977#else
2978#define SERIAL8250_CONSOLE NULL
2979#endif
2980
2981static struct uart_driver serial8250_reg = {
2982 .owner = THIS_MODULE,
2983 .driver_name = "serial",
1da177e4
LT		 2984 .dev_name = "ttyS",
2985 .major = TTY_MAJOR,
2986 .minor = 64,
1da177e4
LT		 2987 .cons = SERIAL8250_CONSOLE,
2988};
2989
d856c666
RK		 2990/*
2991 * early_serial_setup - early registration for 8250 ports
2992 *
2993 * Setup an 8250 port structure prior to console initialisation. Use
2994 * after console initialisation will cause undefined behaviour.
2995 */
1da177e4
LT		 2996int __init early_serial_setup(struct uart_port *port)
2997{
b430428a
DD		 2998 struct uart_port *p;
2999
1da177e4
LT		 3000 if (port->line >= ARRAY_SIZE(serial8250_ports))
3001 return -ENODEV;
3002
3003 serial8250_isa_init_ports();
b430428a
DD		 3004 p = &serial8250_ports[port->line].port;
3005 p->iobase = port->iobase;
3006 p->membase = port->membase;
3007 p->irq = port->irq;
1c2f0493 3008 p->irqflags = port->irqflags;
b430428a
DD		 3009 p->uartclk = port->uartclk;
3010 p->fifosize = port->fifosize;
3011 p->regshift = port->regshift;
3012 p->iotype = port->iotype;
3013 p->flags = port->flags;
3014 p->mapbase = port->mapbase;
3015 p->private_data = port->private_data;
125c97d8
HD		 3016 p->type = port->type;
3017 p->line = port->line;
7d6a07d1
DD		 3018
3019 set_io_from_upio(p);
3020 if (port->serial_in)
3021 p->serial_in = port->serial_in;
3022 if (port->serial_out)
3023 p->serial_out = port->serial_out;
583d28e9
JI		 3024 if (port->handle_irq)
3025 p->handle_irq = port->handle_irq;
3026 else
3027 p->handle_irq = serial8250_default_handle_irq;
7d6a07d1 3028
1da177e4
LT		 3029 return 0;
3030}
3031
3032/**
3033 * serial8250_suspend_port - suspend one serial port
3034 * @line: serial line number
1da177e4
LT		 3035 *
3036 * Suspend one serial port.
3037 */
3038void serial8250_suspend_port(int line)
3039{
3040 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3041}
3042
3043/**
3044 * serial8250_resume_port - resume one serial port
3045 * @line: serial line number
1da177e4
LT		 3046 *
3047 * Resume one serial port.
3048 */
3049void serial8250_resume_port(int line)
3050{
b5b82df6 3051 struct uart_8250_port *up = &serial8250_ports[line];
dfe42443 3052 struct uart_port *port = &up->port;
b5b82df6
DW		 3053
3054 if (up->capabilities & UART_NATSEMI) {
b5b82df6 3055 /* Ensure it's still in high speed mode */
4fd996a1 3056 serial_port_out(port, UART_LCR, 0xE0);
b5b82df6 3057
0d0389e5 3058 ns16550a_goto_highspeed(up);
b5b82df6 3059
4fd996a1 3060 serial_port_out(port, UART_LCR, 0);
dfe42443 3061 port->uartclk = 921600*16;
b5b82df6 3062 }
dfe42443 3063 uart_resume_port(&serial8250_reg, port);
1da177e4
LT		 3064}
3065
3066/*
3067 * Register a set of serial devices attached to a platform device. The
3068 * list is terminated with a zero flags entry, which means we expect
3069 * all entries to have at least UPF_BOOT_AUTOCONF set.
3070 */
9671f099 3071static int serial8250_probe(struct platform_device *dev)
1da177e4 3072{
3ae5eaec 3073 struct plat_serial8250_port *p = dev->dev.platform_data;
2655a2c7 3074 struct uart_8250_port uart;
4c0ebb80 3075 int ret, i, irqflag = 0;
1da177e4 3076
2655a2c7 3077 memset(&uart, 0, sizeof(uart));
1da177e4 3078
4c0ebb80
AGR		 3079 if (share_irqs)
3080 irqflag = IRQF_SHARED;
3081
ec9f47cd 3082 for (i = 0; p && p->flags != 0; p++, i++) {
2655a2c7
AC		 3083 uart.port.iobase = p->iobase;
3084 uart.port.membase = p->membase;
3085 uart.port.irq = p->irq;
3086 uart.port.irqflags = p->irqflags;
3087 uart.port.uartclk = p->uartclk;
3088 uart.port.regshift = p->regshift;
3089 uart.port.iotype = p->iotype;
3090 uart.port.flags = p->flags;
3091 uart.port.mapbase = p->mapbase;
3092 uart.port.hub6 = p->hub6;
3093 uart.port.private_data = p->private_data;
3094 uart.port.type = p->type;
3095 uart.port.serial_in = p->serial_in;
3096 uart.port.serial_out = p->serial_out;
3097 uart.port.handle_irq = p->handle_irq;
3098 uart.port.handle_break = p->handle_break;
3099 uart.port.set_termios = p->set_termios;
3100 uart.port.pm = p->pm;
3101 uart.port.dev = &dev->dev;
3102 uart.port.irqflags |= irqflag;
3103 ret = serial8250_register_8250_port(&uart);
ec9f47cd 3104 if (ret < 0) {
3ae5eaec 3105 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 3106 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3107 p->iobase, (unsigned long long)p->mapbase,
3108 p->irq, ret);
ec9f47cd 3109 }
1da177e4
LT		 3110 }
3111 return 0;
3112}
3113
3114/*
3115 * Remove serial ports registered against a platform device.
3116 */
ae8d8a14 3117static int serial8250_remove(struct platform_device *dev)
1da177e4
LT		 3118{
3119 int i;
3120
a61c2d78 3121 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 3122 struct uart_8250_port *up = &serial8250_ports[i];
3123
3ae5eaec 3124 if (up->port.dev == &dev->dev)
1da177e4
LT		 3125 serial8250_unregister_port(i);
3126 }
3127 return 0;
3128}
3129
3ae5eaec 3130static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 3131{
3132 int i;
3133
1da177e4
LT		 3134 for (i = 0; i < UART_NR; i++) {
3135 struct uart_8250_port *up = &serial8250_ports[i];
3136
3ae5eaec 3137 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3138 uart_suspend_port(&serial8250_reg, &up->port);
3139 }
3140
3141 return 0;
3142}
3143
3ae5eaec 3144static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3145{
3146 int i;
3147
1da177e4
LT		 3148 for (i = 0; i < UART_NR; i++) {
3149 struct uart_8250_port *up = &serial8250_ports[i];
3150
3ae5eaec 3151 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3152 serial8250_resume_port(i);
1da177e4
LT		 3153 }
3154
3155 return 0;
3156}
3157
3ae5eaec 3158static struct platform_driver serial8250_isa_driver = {
1da177e4 3159 .probe = serial8250_probe,
2d47b716 3160 .remove = serial8250_remove,
1da177e4
LT		 3161 .suspend = serial8250_suspend,
3162 .resume = serial8250_resume,
3ae5eaec
RK		 3163 .driver = {
3164 .name = "serial8250",
7493a314 3165 .owner = THIS_MODULE,
3ae5eaec 3166 },
1da177e4
LT		 3167};
3168
3169/*
3170 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3171 * in the table in include/asm/serial.h
3172 */
3173static struct platform_device *serial8250_isa_devs;
3174
3175/*
2655a2c7 3176 * serial8250_register_8250_port and serial8250_unregister_port allows for
1da177e4
LT		 3177 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3178 * modems and PCI multiport cards.
3179 */
f392ecfa 3180static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3181
3182static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3183{
3184 int i;
3185
3186 /*
3187 * First, find a port entry which matches.
3188 */
a61c2d78 3189 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3190 if (uart_match_port(&serial8250_ports[i].port, port))
3191 return &serial8250_ports[i];
3192
3193 /*
3194 * We didn't find a matching entry, so look for the first
3195 * free entry. We look for one which hasn't been previously
3196 * used (indicated by zero iobase).
3197 */
a61c2d78 3198 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3199 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3200 serial8250_ports[i].port.iobase == 0)
3201 return &serial8250_ports[i];
3202
3203 /*
3204 * That also failed. Last resort is to find any entry which
3205 * doesn't have a real port associated with it.
3206 */
a61c2d78 3207 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3208 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3209 return &serial8250_ports[i];
3210
3211 return NULL;
3212}
3213
3214/**
f73fa05b 3215 * serial8250_register_8250_port - register a serial port
58bcd332 3216 * @up: serial port template
1da177e4
LT		 3217 *
3218 * Configure the serial port specified by the request. If the
3219 * port exists and is in use, it is hung up and unregistered
3220 * first.
3221 *
3222 * The port is then probed and if necessary the IRQ is autodetected
3223 * If this fails an error is returned.
3224 *
3225 * On success the port is ready to use and the line number is returned.
3226 */
f73fa05b 3227int serial8250_register_8250_port(struct uart_8250_port *up)
1da177e4
LT		 3228{
3229 struct uart_8250_port *uart;
3230 int ret = -ENOSPC;
3231
f73fa05b 3232 if (up->port.uartclk == 0)
1da177e4
LT		 3233 return -EINVAL;
3234
f392ecfa 3235 mutex_lock(&serial_mutex);
1da177e4 3236
f73fa05b 3237 uart = serial8250_find_match_or_unused(&up->port);
65ecc9c0 3238 if (uart && uart->port.type != PORT_8250_CIR) {
835d844d
SY		 3239 if (uart->port.dev)
3240 uart_remove_one_port(&serial8250_reg, &uart->port);
1da177e4 3241
f73fa05b
MD		 3242 uart->port.iobase = up->port.iobase;
3243 uart->port.membase = up->port.membase;
3244 uart->port.irq = up->port.irq;
3245 uart->port.irqflags = up->port.irqflags;
3246 uart->port.uartclk = up->port.uartclk;
3247 uart->port.fifosize = up->port.fifosize;
3248 uart->port.regshift = up->port.regshift;
3249 uart->port.iotype = up->port.iotype;
3250 uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF;
a2d33d87 3251 uart->bugs = up->bugs;
f73fa05b
MD		 3252 uart->port.mapbase = up->port.mapbase;
3253 uart->port.private_data = up->port.private_data;
3254 if (up->port.dev)
3255 uart->port.dev = up->port.dev;
3256
3257 if (up->port.flags & UPF_FIXED_TYPE)
3258 serial8250_init_fixed_type_port(uart, up->port.type);
8e23fcc8 3259
7d6a07d1
DD		 3260 set_io_from_upio(&uart->port);
3261 /* Possibly override default I/O functions. */
f73fa05b
MD		 3262 if (up->port.serial_in)
3263 uart->port.serial_in = up->port.serial_in;
3264 if (up->port.serial_out)
3265 uart->port.serial_out = up->port.serial_out;
3266 if (up->port.handle_irq)
3267 uart->port.handle_irq = up->port.handle_irq;
235dae5d 3268 /* Possibly override set_termios call */
f73fa05b
MD		 3269 if (up->port.set_termios)
3270 uart->port.set_termios = up->port.set_termios;
3271 if (up->port.pm)
3272 uart->port.pm = up->port.pm;
3273 if (up->port.handle_break)
3274 uart->port.handle_break = up->port.handle_break;
3275 if (up->dl_read)
3276 uart->dl_read = up->dl_read;
3277 if (up->dl_write)
3278 uart->dl_write = up->dl_write;
1da177e4 3279
af7f3743
AC		 3280 if (serial8250_isa_config != NULL)
3281 serial8250_isa_config(0, &uart->port,
3282 &uart->capabilities);
3283
1da177e4
LT		 3284 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3285 if (ret == 0)
3286 ret = uart->port.line;
3287 }
f392ecfa 3288 mutex_unlock(&serial_mutex);
1da177e4
LT		 3289
3290 return ret;
3291}
f73fa05b
MD		 3292EXPORT_SYMBOL(serial8250_register_8250_port);
3293
1da177e4
LT		 3294/**
3295 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3296 * @line: serial line number
3297 *
3298 * Remove one serial port. This may not be called from interrupt
3299 * context. We hand the port back to the our control.
3300 */
3301void serial8250_unregister_port(int line)
3302{
3303 struct uart_8250_port *uart = &serial8250_ports[line];
3304
f392ecfa 3305 mutex_lock(&serial_mutex);
1da177e4
LT		 3306 uart_remove_one_port(&serial8250_reg, &uart->port);
3307 if (serial8250_isa_devs) {
3308 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3309 uart->port.type = PORT_UNKNOWN;
3310 uart->port.dev = &serial8250_isa_devs->dev;
cb01ece3 3311 uart->capabilities = uart_config[uart->port.type].flags;
1da177e4
LT		 3312 uart_add_one_port(&serial8250_reg, &uart->port);
3313 } else {
3314 uart->port.dev = NULL;
3315 }
f392ecfa 3316 mutex_unlock(&serial_mutex);
1da177e4
LT		 3317}
3318EXPORT_SYMBOL(serial8250_unregister_port);
3319
3320static int __init serial8250_init(void)
3321{
25db8ad5 3322 int ret;
1da177e4 3323
835d844d 3324 serial8250_isa_init_ports();
a61c2d78 3325
f1fb9bb8 3326 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3327 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3328 share_irqs ? "en" : "dis");
3329
b70ac771
DM		 3330#ifdef CONFIG_SPARC
3331 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3332#else
3333 serial8250_reg.nr = UART_NR;
1da177e4 3334 ret = uart_register_driver(&serial8250_reg);
b70ac771 3335#endif
1da177e4
LT		 3336 if (ret)
3337 goto out;
3338
835d844d
SY		 3339 ret = serial8250_pnp_init();
3340 if (ret)
3341 goto unreg_uart_drv;
3342
7493a314
DT		 3343 serial8250_isa_devs = platform_device_alloc("serial8250",
3344 PLAT8250_DEV_LEGACY);
3345 if (!serial8250_isa_devs) {
3346 ret = -ENOMEM;
835d844d 3347 goto unreg_pnp;
1da177e4
LT		 3348 }
3349
7493a314
DT		 3350 ret = platform_device_add(serial8250_isa_devs);
3351 if (ret)
3352 goto put_dev;
3353
1da177e4
LT		 3354 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3355
bc965a7f
RK		 3356 ret = platform_driver_register(&serial8250_isa_driver);
3357 if (ret == 0)
3358 goto out;
1da177e4 3359
bc965a7f 3360 platform_device_del(serial8250_isa_devs);
25db8ad5 3361put_dev:
7493a314 3362 platform_device_put(serial8250_isa_devs);
835d844d
SY		 3363unreg_pnp:
3364 serial8250_pnp_exit();
25db8ad5 3365unreg_uart_drv:
b70ac771
DM		 3366#ifdef CONFIG_SPARC
3367 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3368#else
1da177e4 3369 uart_unregister_driver(&serial8250_reg);
b70ac771 3370#endif
25db8ad5 3371out:
1da177e4
LT		 3372 return ret;
3373}
3374
3375static void __exit serial8250_exit(void)
3376{
3377 struct platform_device *isa_dev = serial8250_isa_devs;
3378
3379 /*
3380 * This tells serial8250_unregister_port() not to re-register
3381 * the ports (thereby making serial8250_isa_driver permanently
3382 * in use.)
3383 */
3384 serial8250_isa_devs = NULL;
3385
3ae5eaec 3386 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3387 platform_device_unregister(isa_dev);
3388
835d844d
SY		 3389 serial8250_pnp_exit();
3390
b70ac771
DM		 3391#ifdef CONFIG_SPARC
3392 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3393#else
1da177e4 3394 uart_unregister_driver(&serial8250_reg);
b70ac771 3395#endif
1da177e4
LT		 3396}
3397
3398module_init(serial8250_init);
3399module_exit(serial8250_exit);
3400
3401EXPORT_SYMBOL(serial8250_suspend_port);
3402EXPORT_SYMBOL(serial8250_resume_port);
3403
3404MODULE_LICENSE("GPL");
d87a6d95 3405MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3406
3407module_param(share_irqs, uint, 0644);
3408MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3409 " (unsafe)");
3410
a61c2d78
DJ		 3411module_param(nr_uarts, uint, 0644);
3412MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3413
d41a4b51
CE		 3414module_param(skip_txen_test, uint, 0644);
3415MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3416
1da177e4
LT		 3417#ifdef CONFIG_SERIAL_8250_RSA
3418module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3419MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3420#endif
3421MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux kernel - Deliverables
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