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8250.c: less than 2400 baud fix.
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
1da177e4
LT		 13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
1da177e4
LT		 18
19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
1da177e4 29#include <linux/delay.h>
d052d1be 30#include <linux/platform_device.h>
1da177e4 31#include <linux/tty.h>
cd3ecad1 32#include <linux/ratelimit.h>
1da177e4
LT		 33#include <linux/tty_flip.h>
34#include <linux/serial_reg.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
78512ece 38#include <linux/nmi.h>
f392ecfa 39#include <linux/mutex.h>
5a0e3ad6 40#include <linux/slab.h>
6816383a
PG		 41#ifdef CONFIG_SPARC
42#include <linux/sunserialcore.h>
43#endif
1da177e4
LT		 44
45#include <asm/io.h>
46#include <asm/irq.h>
47
48#include "8250.h"
49
50/*
51 * Configuration:
40663cc7 52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 53 * is unsafe when used on edge-triggered interrupts.
54 */
408b664a 55static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 56
a61c2d78
DJ		 57static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
8440838b
DM		 59static struct uart_driver serial8250_reg;
60
61static int serial_index(struct uart_port *port)
62{
63 return (serial8250_reg.minor - 64) + port->line;
64}
65
d41a4b51
CE		 66static unsigned int skip_txen_test; /* force skip of txen test at init time */
67
1da177e4
LT		 68/*
69 * Debugging.
70 */
71#if 0
72#define DEBUG_AUTOCONF(fmt...) printk(fmt)
73#else
74#define DEBUG_AUTOCONF(fmt...) do { } while (0)
75#endif
76
77#if 0
78#define DEBUG_INTR(fmt...) printk(fmt)
79#else
80#define DEBUG_INTR(fmt...) do { } while (0)
81#endif
82
e7328ae1 83#define PASS_LIMIT 512
1da177e4 84
bca47613
DH		 85#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
86
87
1da177e4
LT		 88#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89#define CONFIG_SERIAL_DETECT_IRQ 1
90#endif
1da177e4
LT		 91#ifdef CONFIG_SERIAL_8250_MANY_PORTS
92#define CONFIG_SERIAL_MANY_PORTS 1
93#endif
94
95/*
96 * HUB6 is always on. This will be removed once the header
97 * files have been cleaned.
98 */
99#define CONFIG_HUB6 1
100
a4ed1e41 101#include <asm/serial.h>
1da177e4
LT		 102/*
103 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * standard enumeration mechanism. Platforms that can find all
105 * serial ports via mechanisms like ACPI or PCI need not supply it.
106 */
107#ifndef SERIAL_PORT_DFNS
108#define SERIAL_PORT_DFNS
109#endif
110
cb3592be 111static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
113};
114
026d02a2 115#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 116
117#ifdef CONFIG_SERIAL_8250_RSA
118
119#define PORT_RSA_MAX 4
120static unsigned long probe_rsa[PORT_RSA_MAX];
121static unsigned int probe_rsa_count;
122#endif /* CONFIG_SERIAL_8250_RSA */
123
1da177e4 124struct irq_info {
25db8ad5
AC		 125 struct hlist_node node;
126 int irq;
127 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 128 struct list_head *head;
129};
130
25db8ad5
AC		 131#define NR_IRQ_HASH 32 /* Can be adjusted later */
132static struct hlist_head irq_lists[NR_IRQ_HASH];
133static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 134
135/*
136 * Here we define the default xmit fifo size used for each type of UART.
137 */
138static const struct serial8250_config uart_config[] = {
139 [PORT_UNKNOWN] = {
140 .name = "unknown",
141 .fifo_size = 1,
142 .tx_loadsz = 1,
143 },
144 [PORT_8250] = {
145 .name = "8250",
146 .fifo_size = 1,
147 .tx_loadsz = 1,
148 },
149 [PORT_16450] = {
150 .name = "16450",
151 .fifo_size = 1,
152 .tx_loadsz = 1,
153 },
154 [PORT_16550] = {
155 .name = "16550",
156 .fifo_size = 1,
157 .tx_loadsz = 1,
158 },
159 [PORT_16550A] = {
160 .name = "16550A",
161 .fifo_size = 16,
162 .tx_loadsz = 16,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO,
165 },
166 [PORT_CIRRUS] = {
167 .name = "Cirrus",
168 .fifo_size = 1,
169 .tx_loadsz = 1,
170 },
171 [PORT_16650] = {
172 .name = "ST16650",
173 .fifo_size = 1,
174 .tx_loadsz = 1,
175 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
176 },
177 [PORT_16650V2] = {
178 .name = "ST16650V2",
179 .fifo_size = 32,
180 .tx_loadsz = 16,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
182 UART_FCR_T_TRIG_00,
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184 },
185 [PORT_16750] = {
186 .name = "TI16750",
187 .fifo_size = 64,
188 .tx_loadsz = 64,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
190 UART_FCR7_64BYTE,
191 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
192 },
193 [PORT_STARTECH] = {
194 .name = "Startech",
195 .fifo_size = 1,
196 .tx_loadsz = 1,
197 },
198 [PORT_16C950] = {
199 .name = "16C950/954",
200 .fifo_size = 128,
201 .tx_loadsz = 128,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
d0694e2a
PM		 203 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
1da177e4
LT		 205 },
206 [PORT_16654] = {
207 .name = "ST16654",
208 .fifo_size = 64,
209 .tx_loadsz = 32,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
211 UART_FCR_T_TRIG_10,
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
213 },
214 [PORT_16850] = {
215 .name = "XR16850",
216 .fifo_size = 128,
217 .tx_loadsz = 128,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220 },
221 [PORT_RSA] = {
222 .name = "RSA",
223 .fifo_size = 2048,
224 .tx_loadsz = 2048,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226 .flags = UART_CAP_FIFO,
227 },
228 [PORT_NS16550A] = {
229 .name = "NS16550A",
230 .fifo_size = 16,
231 .tx_loadsz = 16,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_NATSEMI,
234 },
235 [PORT_XSCALE] = {
236 .name = "XScale",
237 .fifo_size = 32,
238 .tx_loadsz = 32,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
4539c24f 240 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
1da177e4 241 },
bd71c182
TK		 242 [PORT_RM9000] = {
243 .name = "RM9000",
244 .fifo_size = 16,
245 .tx_loadsz = 16,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 247 .flags = UART_CAP_FIFO,
248 },
249 [PORT_OCTEON] = {
250 .name = "OCTEON",
251 .fifo_size = 64,
252 .tx_loadsz = 64,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 254 .flags = UART_CAP_FIFO,
255 },
08e0992f
FF		 256 [PORT_AR7] = {
257 .name = "AR7",
258 .fifo_size = 16,
259 .tx_loadsz = 16,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
261 .flags = UART_CAP_FIFO | UART_CAP_AFE,
262 },
235dae5d
PL		 263 [PORT_U6_16550A] = {
264 .name = "U6_16550A",
265 .fifo_size = 64,
266 .tx_loadsz = 64,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO | UART_CAP_AFE,
269 },
4539c24f
SW		 270 [PORT_TEGRA] = {
271 .name = "Tegra",
272 .fifo_size = 32,
273 .tx_loadsz = 8,
274 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
275 UART_FCR_T_TRIG_01,
276 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
277 },
06315348
SH		 278 [PORT_XR17D15X] = {
279 .name = "XR17D15X",
280 .fifo_size = 64,
281 .tx_loadsz = 64,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
283 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
284 },
1da177e4
LT		 285};
286
12bf3f24 287#if defined(CONFIG_MIPS_ALCHEMY)
21c614a7
PA		 288
289/* Au1x00 UART hardware has a weird register layout */
290static const u8 au_io_in_map[] = {
291 [UART_RX] = 0,
292 [UART_IER] = 2,
293 [UART_IIR] = 3,
294 [UART_LCR] = 5,
295 [UART_MCR] = 6,
296 [UART_LSR] = 7,
297 [UART_MSR] = 8,
298};
299
300static const u8 au_io_out_map[] = {
301 [UART_TX] = 1,
302 [UART_IER] = 2,
303 [UART_FCR] = 4,
304 [UART_LCR] = 5,
305 [UART_MCR] = 6,
306};
307
308/* sane hardware needs no mapping */
7d6a07d1 309static inline int map_8250_in_reg(struct uart_port *p, int offset)
21c614a7 310{
7d6a07d1 311 if (p->iotype != UPIO_AU)
21c614a7
PA		 312 return offset;
313 return au_io_in_map[offset];
314}
315
7d6a07d1 316static inline int map_8250_out_reg(struct uart_port *p, int offset)
21c614a7 317{
7d6a07d1 318 if (p->iotype != UPIO_AU)
21c614a7
PA		 319 return offset;
320 return au_io_out_map[offset];
321}
322
6f803cd0 323#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 324
325static const u8
326 regmap_in[8] = {
327 [UART_RX] = 0x00,
328 [UART_IER] = 0x0c,
329 [UART_IIR] = 0x14,
330 [UART_LCR] = 0x1c,
331 [UART_MCR] = 0x20,
332 [UART_LSR] = 0x24,
333 [UART_MSR] = 0x28,
334 [UART_SCR] = 0x2c
335 },
336 regmap_out[8] = {
337 [UART_TX] = 0x04,
338 [UART_IER] = 0x0c,
339 [UART_FCR] = 0x18,
340 [UART_LCR] = 0x1c,
341 [UART_MCR] = 0x20,
342 [UART_LSR] = 0x24,
343 [UART_MSR] = 0x28,
344 [UART_SCR] = 0x2c
345 };
346
7d6a07d1 347static inline int map_8250_in_reg(struct uart_port *p, int offset)
bd71c182 348{
7d6a07d1 349 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 350 return offset;
351 return regmap_in[offset];
352}
353
7d6a07d1 354static inline int map_8250_out_reg(struct uart_port *p, int offset)
bd71c182 355{
7d6a07d1 356 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 357 return offset;
358 return regmap_out[offset];
359}
360
21c614a7
PA		 361#else
362
363/* sane hardware needs no mapping */
364#define map_8250_in_reg(up, offset) (offset)
365#define map_8250_out_reg(up, offset) (offset)
366
367#endif
368
7d6a07d1 369static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 370{
7d6a07d1
DD		 371 offset = map_8250_in_reg(p, offset) << p->regshift;
372 outb(p->hub6 - 1 + offset, p->iobase);
373 return inb(p->iobase + 1);
374}
1da177e4 375
7d6a07d1
DD		 376static void hub6_serial_out(struct uart_port *p, int offset, int value)
377{
378 offset = map_8250_out_reg(p, offset) << p->regshift;
379 outb(p->hub6 - 1 + offset, p->iobase);
380 outb(value, p->iobase + 1);
381}
1da177e4 382
7d6a07d1
DD		 383static unsigned int mem_serial_in(struct uart_port *p, int offset)
384{
385 offset = map_8250_in_reg(p, offset) << p->regshift;
386 return readb(p->membase + offset);
387}
1da177e4 388
7d6a07d1
DD		 389static void mem_serial_out(struct uart_port *p, int offset, int value)
390{
391 offset = map_8250_out_reg(p, offset) << p->regshift;
392 writeb(value, p->membase + offset);
393}
394
395static void mem32_serial_out(struct uart_port *p, int offset, int value)
396{
397 offset = map_8250_out_reg(p, offset) << p->regshift;
398 writel(value, p->membase + offset);
399}
400
401static unsigned int mem32_serial_in(struct uart_port *p, int offset)
402{
403 offset = map_8250_in_reg(p, offset) << p->regshift;
404 return readl(p->membase + offset);
405}
1da177e4 406
7d6a07d1
DD		 407static unsigned int au_serial_in(struct uart_port *p, int offset)
408{
409 offset = map_8250_in_reg(p, offset) << p->regshift;
410 return __raw_readl(p->membase + offset);
411}
412
413static void au_serial_out(struct uart_port *p, int offset, int value)
414{
415 offset = map_8250_out_reg(p, offset) << p->regshift;
416 __raw_writel(value, p->membase + offset);
417}
21c614a7 418
7d6a07d1
DD		 419static unsigned int io_serial_in(struct uart_port *p, int offset)
420{
421 offset = map_8250_in_reg(p, offset) << p->regshift;
422 return inb(p->iobase + offset);
423}
424
425static void io_serial_out(struct uart_port *p, int offset, int value)
426{
427 offset = map_8250_out_reg(p, offset) << p->regshift;
428 outb(value, p->iobase + offset);
429}
430
583d28e9
JI		 431static int serial8250_default_handle_irq(struct uart_port *port);
432
7d6a07d1
DD		 433static void set_io_from_upio(struct uart_port *p)
434{
49d5741b
JI		 435 struct uart_8250_port *up =
436 container_of(p, struct uart_8250_port, port);
7d6a07d1 437 switch (p->iotype) {
1da177e4 438 case UPIO_HUB6:
7d6a07d1
DD		 439 p->serial_in = hub6_serial_in;
440 p->serial_out = hub6_serial_out;
1da177e4
LT		 441 break;
442
443 case UPIO_MEM:
7d6a07d1
DD		 444 p->serial_in = mem_serial_in;
445 p->serial_out = mem_serial_out;
1da177e4
LT		 446 break;
447
bd71c182 448 case UPIO_RM9000:
1da177e4 449 case UPIO_MEM32:
7d6a07d1
DD		 450 p->serial_in = mem32_serial_in;
451 p->serial_out = mem32_serial_out;
1da177e4
LT		 452 break;
453
21c614a7 454 case UPIO_AU:
7d6a07d1
DD		 455 p->serial_in = au_serial_in;
456 p->serial_out = au_serial_out;
21c614a7 457 break;
12bf3f24 458
1da177e4 459 default:
7d6a07d1
DD		 460 p->serial_in = io_serial_in;
461 p->serial_out = io_serial_out;
462 break;
1da177e4 463 }
b8e7e40a
AC		 464 /* Remember loaded iotype */
465 up->cur_iotype = p->iotype;
583d28e9 466 p->handle_irq = serial8250_default_handle_irq;
1da177e4
LT		 467}
468
40b36daa 469static void
55e4016d 470serial_port_out_sync(struct uart_port *p, int offset, int value)
40b36daa 471{
7d6a07d1 472 switch (p->iotype) {
40b36daa
AW		 473 case UPIO_MEM:
474 case UPIO_MEM32:
40b36daa 475 case UPIO_AU:
7d6a07d1
DD		 476 p->serial_out(p, offset, value);
477 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 478 break;
479 default:
7d6a07d1 480 p->serial_out(p, offset, value);
40b36daa
AW		 481 }
482}
483
b32b19b8
JAH		 484/* Uart divisor latch read */
485static inline int _serial_dl_read(struct uart_8250_port *up)
486{
0acf519f 487 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
b32b19b8
JAH		 488}
489
490/* Uart divisor latch write */
491static inline void _serial_dl_write(struct uart_8250_port *up, int value)
492{
0acf519f
PG		 493 serial_out(up, UART_DLL, value & 0xff);
494 serial_out(up, UART_DLM, value >> 8 & 0xff);
b32b19b8
JAH		 495}
496
12bf3f24 497#if defined(CONFIG_MIPS_ALCHEMY)
b32b19b8
JAH		 498/* Au1x00 haven't got a standard divisor latch */
499static int serial_dl_read(struct uart_8250_port *up)
500{
501 if (up->port.iotype == UPIO_AU)
502 return __raw_readl(up->port.membase + 0x28);
503 else
504 return _serial_dl_read(up);
505}
506
507static void serial_dl_write(struct uart_8250_port *up, int value)
508{
509 if (up->port.iotype == UPIO_AU)
510 __raw_writel(value, up->port.membase + 0x28);
511 else
512 _serial_dl_write(up, value);
513}
6f803cd0 514#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 515static int serial_dl_read(struct uart_8250_port *up)
516{
517 return (up->port.iotype == UPIO_RM9000) ?
518 (((__raw_readl(up->port.membase + 0x10) << 8) |
519 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
520 _serial_dl_read(up);
521}
522
523static void serial_dl_write(struct uart_8250_port *up, int value)
524{
525 if (up->port.iotype == UPIO_RM9000) {
526 __raw_writel(value, up->port.membase + 0x08);
527 __raw_writel(value >> 8, up->port.membase + 0x10);
528 } else {
529 _serial_dl_write(up, value);
530 }
531}
b32b19b8
JAH		 532#else
533#define serial_dl_read(up) _serial_dl_read(up)
534#define serial_dl_write(up, value) _serial_dl_write(up, value)
535#endif
1da177e4
LT		 536
537/*
538 * For the 16C950
539 */
540static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
541{
542 serial_out(up, UART_SCR, offset);
543 serial_out(up, UART_ICR, value);
544}
545
546static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
547{
548 unsigned int value;
549
550 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
551 serial_out(up, UART_SCR, offset);
552 value = serial_in(up, UART_ICR);
553 serial_icr_write(up, UART_ACR, up->acr);
554
555 return value;
556}
557
558/*
559 * FIFO support.
560 */
b5d674ab 561static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 562{
563 if (p->capabilities & UART_CAP_FIFO) {
0acf519f
PG		 564 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
565 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
1da177e4 566 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0acf519f 567 serial_out(p, UART_FCR, 0);
1da177e4
LT		 568 }
569}
570
0ad372b9
SM		 571void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
572{
573 unsigned char fcr;
574
575 serial8250_clear_fifos(p);
576 fcr = uart_config[p->port.type].fcr;
577 serial_out(p, UART_FCR, fcr);
578}
579EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
580
1da177e4
LT		 581/*
582 * IER sleep support. UARTs which have EFRs need the "extended
583 * capability" bit enabled. Note that on XR16C850s, we need to
584 * reset LCR to write to IER.
585 */
b5d674ab 586static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4
LT		 587{
588 if (p->capabilities & UART_CAP_SLEEP) {
589 if (p->capabilities & UART_CAP_EFR) {
0acf519f
PG		 590 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
591 serial_out(p, UART_EFR, UART_EFR_ECB);
592 serial_out(p, UART_LCR, 0);
1da177e4 593 }
0acf519f 594 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
1da177e4 595 if (p->capabilities & UART_CAP_EFR) {
0acf519f
PG		 596 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
597 serial_out(p, UART_EFR, 0);
598 serial_out(p, UART_LCR, 0);
1da177e4
LT		 599 }
600 }
601}
602
603#ifdef CONFIG_SERIAL_8250_RSA
604/*
605 * Attempts to turn on the RSA FIFO. Returns zero on failure.
606 * We set the port uart clock rate if we succeed.
607 */
608static int __enable_rsa(struct uart_8250_port *up)
609{
610 unsigned char mode;
611 int result;
612
0acf519f 613 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 614 result = mode & UART_RSA_MSR_FIFO;
615
616 if (!result) {
0acf519f
PG		 617 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
618 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 619 result = mode & UART_RSA_MSR_FIFO;
620 }
621
622 if (result)
623 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
624
625 return result;
626}
627
628static void enable_rsa(struct uart_8250_port *up)
629{
630 if (up->port.type == PORT_RSA) {
631 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
632 spin_lock_irq(&up->port.lock);
633 __enable_rsa(up);
634 spin_unlock_irq(&up->port.lock);
635 }
636 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
0acf519f 637 serial_out(up, UART_RSA_FRR, 0);
1da177e4
LT		 638 }
639}
640
641/*
642 * Attempts to turn off the RSA FIFO. Returns zero on failure.
643 * It is unknown why interrupts were disabled in here. However,
644 * the caller is expected to preserve this behaviour by grabbing
645 * the spinlock before calling this function.
646 */
647static void disable_rsa(struct uart_8250_port *up)
648{
649 unsigned char mode;
650 int result;
651
652 if (up->port.type == PORT_RSA &&
653 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
654 spin_lock_irq(&up->port.lock);
655
0acf519f 656 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 657 result = !(mode & UART_RSA_MSR_FIFO);
658
659 if (!result) {
0acf519f
PG		 660 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
661 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 662 result = !(mode & UART_RSA_MSR_FIFO);
663 }
664
665 if (result)
666 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
667 spin_unlock_irq(&up->port.lock);
668 }
669}
670#endif /* CONFIG_SERIAL_8250_RSA */
671
672/*
673 * This is a quickie test to see how big the FIFO is.
674 * It doesn't work at all the time, more's the pity.
675 */
676static int size_fifo(struct uart_8250_port *up)
677{
b32b19b8
JAH		 678 unsigned char old_fcr, old_mcr, old_lcr;
679 unsigned short old_dl;
1da177e4
LT		 680 int count;
681
0acf519f
PG		 682 old_lcr = serial_in(up, UART_LCR);
683 serial_out(up, UART_LCR, 0);
684 old_fcr = serial_in(up, UART_FCR);
685 old_mcr = serial_in(up, UART_MCR);
686 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1da177e4 687 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0acf519f
PG		 688 serial_out(up, UART_MCR, UART_MCR_LOOP);
689 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8
JAH		 690 old_dl = serial_dl_read(up);
691 serial_dl_write(up, 0x0001);
0acf519f 692 serial_out(up, UART_LCR, 0x03);
1da177e4 693 for (count = 0; count < 256; count++)
0acf519f 694 serial_out(up, UART_TX, count);
1da177e4 695 mdelay(20);/* FIXME - schedule_timeout */
0acf519f 696 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
1da177e4 697 (count < 256); count++)
0acf519f
PG		 698 serial_in(up, UART_RX);
699 serial_out(up, UART_FCR, old_fcr);
700 serial_out(up, UART_MCR, old_mcr);
701 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8 702 serial_dl_write(up, old_dl);
0acf519f 703 serial_out(up, UART_LCR, old_lcr);
1da177e4
LT		 704
705 return count;
706}
707
708/*
709 * Read UART ID using the divisor method - set DLL and DLM to zero
710 * and the revision will be in DLL and device type in DLM. We
711 * preserve the device state across this.
712 */
713static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
714{
715 unsigned char old_dll, old_dlm, old_lcr;
716 unsigned int id;
717
0acf519f
PG		 718 old_lcr = serial_in(p, UART_LCR);
719 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4 720
0acf519f
PG		 721 old_dll = serial_in(p, UART_DLL);
722 old_dlm = serial_in(p, UART_DLM);
1da177e4 723
0acf519f
PG		 724 serial_out(p, UART_DLL, 0);
725 serial_out(p, UART_DLM, 0);
1da177e4 726
0acf519f 727 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
1da177e4 728
0acf519f
PG		 729 serial_out(p, UART_DLL, old_dll);
730 serial_out(p, UART_DLM, old_dlm);
731 serial_out(p, UART_LCR, old_lcr);
1da177e4
LT		 732
733 return id;
734}
735
736/*
737 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
738 * When this function is called we know it is at least a StarTech
739 * 16650 V2, but it might be one of several StarTech UARTs, or one of
740 * its clones. (We treat the broken original StarTech 16650 V1 as a
741 * 16550, and why not? Startech doesn't seem to even acknowledge its
742 * existence.)
bd71c182 743 *
1da177e4
LT		 744 * What evil have men's minds wrought...
745 */
746static void autoconfig_has_efr(struct uart_8250_port *up)
747{
748 unsigned int id1, id2, id3, rev;
749
750 /*
751 * Everything with an EFR has SLEEP
752 */
753 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
754
755 /*
756 * First we check to see if it's an Oxford Semiconductor UART.
757 *
758 * If we have to do this here because some non-National
759 * Semiconductor clone chips lock up if you try writing to the
760 * LSR register (which serial_icr_read does)
761 */
762
763 /*
764 * Check for Oxford Semiconductor 16C950.
765 *
766 * EFR [4] must be set else this test fails.
767 *
768 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
769 * claims that it's needed for 952 dual UART's (which are not
770 * recommended for new designs).
771 */
772 up->acr = 0;
662b083a 773 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 774 serial_out(up, UART_EFR, UART_EFR_ECB);
775 serial_out(up, UART_LCR, 0x00);
776 id1 = serial_icr_read(up, UART_ID1);
777 id2 = serial_icr_read(up, UART_ID2);
778 id3 = serial_icr_read(up, UART_ID3);
779 rev = serial_icr_read(up, UART_REV);
780
781 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
782
783 if (id1 == 0x16 && id2 == 0xC9 &&
784 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
785 up->port.type = PORT_16C950;
4ba5e35d
RK		 786
787 /*
788 * Enable work around for the Oxford Semiconductor 952 rev B
789 * chip which causes it to seriously miscalculate baud rates
790 * when DLL is 0.
791 */
792 if (id3 == 0x52 && rev == 0x01)
793 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 794 return;
795 }
bd71c182 796
1da177e4
LT		 797 /*
798 * We check for a XR16C850 by setting DLL and DLM to 0, and then
799 * reading back DLL and DLM. The chip type depends on the DLM
800 * value read back:
801 * 0x10 - XR16C850 and the DLL contains the chip revision.
802 * 0x12 - XR16C2850.
803 * 0x14 - XR16C854.
804 */
805 id1 = autoconfig_read_divisor_id(up);
806 DEBUG_AUTOCONF("850id=%04x ", id1);
807
808 id2 = id1 >> 8;
809 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 810 up->port.type = PORT_16850;
811 return;
812 }
813
814 /*
815 * It wasn't an XR16C850.
816 *
817 * We distinguish between the '654 and the '650 by counting
818 * how many bytes are in the FIFO. I'm using this for now,
819 * since that's the technique that was sent to me in the
820 * serial driver update, but I'm not convinced this works.
821 * I've had problems doing this in the past. -TYT
822 */
823 if (size_fifo(up) == 64)
824 up->port.type = PORT_16654;
825 else
826 up->port.type = PORT_16650V2;
827}
828
829/*
830 * We detected a chip without a FIFO. Only two fall into
831 * this category - the original 8250 and the 16450. The
832 * 16450 has a scratch register (accessible with LCR=0)
833 */
834static void autoconfig_8250(struct uart_8250_port *up)
835{
836 unsigned char scratch, status1, status2;
837
838 up->port.type = PORT_8250;
839
840 scratch = serial_in(up, UART_SCR);
0acf519f 841 serial_out(up, UART_SCR, 0xa5);
1da177e4 842 status1 = serial_in(up, UART_SCR);
0acf519f 843 serial_out(up, UART_SCR, 0x5a);
1da177e4 844 status2 = serial_in(up, UART_SCR);
0acf519f 845 serial_out(up, UART_SCR, scratch);
1da177e4
LT		 846
847 if (status1 == 0xa5 && status2 == 0x5a)
848 up->port.type = PORT_16450;
849}
850
851static int broken_efr(struct uart_8250_port *up)
852{
853 /*
854 * Exar ST16C2550 "A2" devices incorrectly detect as
855 * having an EFR, and report an ID of 0x0201. See
631dd1a8 856 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1da177e4
LT		 857 */
858 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
859 return 1;
860
861 return 0;
862}
863
0d0389e5
YK		 864static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
865{
866 unsigned char status;
867
868 status = serial_in(up, 0x04); /* EXCR2 */
869#define PRESL(x) ((x) & 0x30)
870 if (PRESL(status) == 0x10) {
871 /* already in high speed mode */
872 return 0;
873 } else {
874 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
875 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
0acf519f 876 serial_out(up, 0x04, status);
0d0389e5
YK		 877 }
878 return 1;
879}
880
1da177e4
LT		 881/*
882 * We know that the chip has FIFOs. Does it have an EFR? The
883 * EFR is located in the same register position as the IIR and
884 * we know the top two bits of the IIR are currently set. The
885 * EFR should contain zero. Try to read the EFR.
886 */
887static void autoconfig_16550a(struct uart_8250_port *up)
888{
889 unsigned char status1, status2;
890 unsigned int iersave;
891
892 up->port.type = PORT_16550A;
893 up->capabilities |= UART_CAP_FIFO;
894
895 /*
896 * Check for presence of the EFR when DLAB is set.
897 * Only ST16C650V1 UARTs pass this test.
898 */
0acf519f 899 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4 900 if (serial_in(up, UART_EFR) == 0) {
0acf519f 901 serial_out(up, UART_EFR, 0xA8);
1da177e4
LT		 902 if (serial_in(up, UART_EFR) != 0) {
903 DEBUG_AUTOCONF("EFRv1 ");
904 up->port.type = PORT_16650;
905 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
906 } else {
907 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
908 }
0acf519f 909 serial_out(up, UART_EFR, 0);
1da177e4
LT		 910 return;
911 }
912
913 /*
914 * Maybe it requires 0xbf to be written to the LCR.
915 * (other ST16C650V2 UARTs, TI16C752A, etc)
916 */
0acf519f 917 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 918 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
919 DEBUG_AUTOCONF("EFRv2 ");
920 autoconfig_has_efr(up);
921 return;
922 }
923
924 /*
925 * Check for a National Semiconductor SuperIO chip.
926 * Attempt to switch to bank 2, read the value of the LOOP bit
927 * from EXCR1. Switch back to bank 0, change it in MCR. Then
928 * switch back to bank 2, read it from EXCR1 again and check
929 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4 930 */
0acf519f 931 serial_out(up, UART_LCR, 0);
1da177e4 932 status1 = serial_in(up, UART_MCR);
0acf519f 933 serial_out(up, UART_LCR, 0xE0);
1da177e4
LT		 934 status2 = serial_in(up, 0x02); /* EXCR1 */
935
936 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
0acf519f
PG		 937 serial_out(up, UART_LCR, 0);
938 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
939 serial_out(up, UART_LCR, 0xE0);
1da177e4 940 status2 = serial_in(up, 0x02); /* EXCR1 */
0acf519f
PG		 941 serial_out(up, UART_LCR, 0);
942 serial_out(up, UART_MCR, status1);
1da177e4
LT		 943
944 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 945 unsigned short quot;
946
0acf519f 947 serial_out(up, UART_LCR, 0xE0);
857dde2e 948
b32b19b8 949 quot = serial_dl_read(up);
857dde2e
DW		 950 quot <<= 3;
951
0d0389e5
YK		 952 if (ns16550a_goto_highspeed(up))
953 serial_dl_write(up, quot);
857dde2e 954
0acf519f 955 serial_out(up, UART_LCR, 0);
1da177e4 956
857dde2e 957 up->port.uartclk = 921600*16;
1da177e4
LT		 958 up->port.type = PORT_NS16550A;
959 up->capabilities |= UART_NATSEMI;
960 return;
961 }
962 }
963
964 /*
965 * No EFR. Try to detect a TI16750, which only sets bit 5 of
966 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
967 * Try setting it with and without DLAB set. Cheap clones
968 * set bit 5 without DLAB set.
969 */
0acf519f
PG		 970 serial_out(up, UART_LCR, 0);
971 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1da177e4 972 status1 = serial_in(up, UART_IIR) >> 5;
0acf519f
PG		 973 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
974 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
975 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1da177e4 976 status2 = serial_in(up, UART_IIR) >> 5;
0acf519f
PG		 977 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
978 serial_out(up, UART_LCR, 0);
1da177e4
LT		 979
980 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
981
982 if (status1 == 6 && status2 == 7) {
983 up->port.type = PORT_16750;
984 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
985 return;
986 }
987
988 /*
989 * Try writing and reading the UART_IER_UUE bit (b6).
990 * If it works, this is probably one of the Xscale platform's
991 * internal UARTs.
992 * We're going to explicitly set the UUE bit to 0 before
993 * trying to write and read a 1 just to make sure it's not
994 * already a 1 and maybe locked there before we even start start.
995 */
996 iersave = serial_in(up, UART_IER);
0acf519f 997 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1da177e4
LT		 998 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
999 /*
1000 * OK it's in a known zero state, try writing and reading
1001 * without disturbing the current state of the other bits.
1002 */
0acf519f 1003 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1da177e4
LT		 1004 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1005 /*
1006 * It's an Xscale.
1007 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1008 */
1009 DEBUG_AUTOCONF("Xscale ");
1010 up->port.type = PORT_XSCALE;
5568181f 1011 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1da177e4
LT		 1012 return;
1013 }
1014 } else {
1015 /*
1016 * If we got here we couldn't force the IER_UUE bit to 0.
1017 * Log it and continue.
1018 */
1019 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1020 }
0acf519f 1021 serial_out(up, UART_IER, iersave);
235dae5d 1022
06315348
SH		 1023 /*
1024 * Exar uarts have EFR in a weird location
1025 */
1026 if (up->port.flags & UPF_EXAR_EFR) {
1027 up->port.type = PORT_XR17D15X;
1028 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1029 }
1030
235dae5d
PL		 1031 /*
1032 * We distinguish between 16550A and U6 16550A by counting
1033 * how many bytes are in the FIFO.
1034 */
1035 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1036 up->port.type = PORT_U6_16550A;
1037 up->capabilities |= UART_CAP_AFE;
1038 }
1da177e4
LT		 1039}
1040
1041/*
1042 * This routine is called by rs_init() to initialize a specific serial
1043 * port. It determines what type of UART chip this serial port is
1044 * using: 8250, 16450, 16550, 16550A. The important question is
1045 * whether or not this UART is a 16550A or not, since this will
1046 * determine whether or not we can use its FIFO features or not.
1047 */
1048static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1049{
1050 unsigned char status1, scratch, scratch2, scratch3;
1051 unsigned char save_lcr, save_mcr;
dfe42443 1052 struct uart_port *port = &up->port;
1da177e4
LT		 1053 unsigned long flags;
1054
dfe42443 1055 if (!port->iobase && !port->mapbase && !port->membase)
1da177e4
LT		 1056 return;
1057
80647b95 1058 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
dfe42443 1059 serial_index(port), port->iobase, port->membase);
1da177e4
LT		 1060
1061 /*
1062 * We really do need global IRQs disabled here - we're going to
1063 * be frobbing the chips IRQ enable register to see if it exists.
1064 */
dfe42443 1065 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 1066
1067 up->capabilities = 0;
4ba5e35d 1068 up->bugs = 0;
1da177e4 1069
dfe42443 1070 if (!(port->flags & UPF_BUGGY_UART)) {
1da177e4
LT		 1071 /*
1072 * Do a simple existence test first; if we fail this,
1073 * there's no point trying anything else.
bd71c182 1074 *
1da177e4
LT		 1075 * 0x80 is used as a nonsense port to prevent against
1076 * false positives due to ISA bus float. The
1077 * assumption is that 0x80 is a non-existent port;
1078 * which should be safe since include/asm/io.h also
1079 * makes this assumption.
1080 *
1081 * Note: this is safe as long as MCR bit 4 is clear
1082 * and the device is in "PC" mode.
1083 */
0acf519f
PG		 1084 scratch = serial_in(up, UART_IER);
1085 serial_out(up, UART_IER, 0);
1da177e4
LT		 1086#ifdef __i386__
1087 outb(0xff, 0x080);
1088#endif
48212008
TH		 1089 /*
1090 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1091 * 16C754B) allow only to modify them if an EFR bit is set.
1092 */
0acf519f
PG		 1093 scratch2 = serial_in(up, UART_IER) & 0x0f;
1094 serial_out(up, UART_IER, 0x0F);
1da177e4
LT		 1095#ifdef __i386__
1096 outb(0, 0x080);
1097#endif
0acf519f
PG		 1098 scratch3 = serial_in(up, UART_IER) & 0x0f;
1099 serial_out(up, UART_IER, scratch);
1da177e4
LT		 1100 if (scratch2 != 0 || scratch3 != 0x0F) {
1101 /*
1102 * We failed; there's nothing here
1103 */
1104 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1105 scratch2, scratch3);
1106 goto out;
1107 }
1108 }
1109
1110 save_mcr = serial_in(up, UART_MCR);
1111 save_lcr = serial_in(up, UART_LCR);
1112
bd71c182 1113 /*
1da177e4
LT		 1114 * Check to see if a UART is really there. Certain broken
1115 * internal modems based on the Rockwell chipset fail this
1116 * test, because they apparently don't implement the loopback
1117 * test mode. So this test is skipped on the COM 1 through
1118 * COM 4 ports. This *should* be safe, since no board
1119 * manufacturer would be stupid enough to design a board
1120 * that conflicts with COM 1-4 --- we hope!
1121 */
dfe42443 1122 if (!(port->flags & UPF_SKIP_TEST)) {
0acf519f
PG		 1123 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1124 status1 = serial_in(up, UART_MSR) & 0xF0;
1125 serial_out(up, UART_MCR, save_mcr);
1da177e4
LT		 1126 if (status1 != 0x90) {
1127 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1128 status1);
1129 goto out;
1130 }
1131 }
1132
1133 /*
1134 * We're pretty sure there's a port here. Lets find out what
1135 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1136 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1137 * determines what we test for next.
1138 *
1139 * We also initialise the EFR (if any) to zero for later. The
1140 * EFR occupies the same register location as the FCR and IIR.
1141 */
0acf519f
PG		 1142 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1143 serial_out(up, UART_EFR, 0);
1144 serial_out(up, UART_LCR, 0);
1da177e4 1145
0acf519f 1146 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1da177e4
LT		 1147 scratch = serial_in(up, UART_IIR) >> 6;
1148
1149 DEBUG_AUTOCONF("iir=%d ", scratch);
1150
1151 switch (scratch) {
1152 case 0:
1153 autoconfig_8250(up);
1154 break;
1155 case 1:
dfe42443 1156 port->type = PORT_UNKNOWN;
1da177e4
LT		 1157 break;
1158 case 2:
dfe42443 1159 port->type = PORT_16550;
1da177e4
LT		 1160 break;
1161 case 3:
1162 autoconfig_16550a(up);
1163 break;
1164 }
1165
1166#ifdef CONFIG_SERIAL_8250_RSA
1167 /*
1168 * Only probe for RSA ports if we got the region.
1169 */
dfe42443 1170 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1da177e4
LT		 1171 int i;
1172
1173 for (i = 0 ; i < probe_rsa_count; ++i) {
dfe42443
PG		 1174 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1175 port->type = PORT_RSA;
1da177e4
LT		 1176 break;
1177 }
1178 }
1179 }
1180#endif
21c614a7 1181
0acf519f 1182 serial_out(up, UART_LCR, save_lcr);
1da177e4 1183
dfe42443 1184 if (up->capabilities != uart_config[port->type].flags) {
1da177e4
LT		 1185 printk(KERN_WARNING
1186 "ttyS%d: detected caps %08x should be %08x\n",
dfe42443
PG		 1187 serial_index(port), up->capabilities,
1188 uart_config[port->type].flags);
1da177e4
LT		 1189 }
1190
dfe42443
PG		 1191 port->fifosize = uart_config[up->port.type].fifo_size;
1192 up->capabilities = uart_config[port->type].flags;
1193 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1da177e4 1194
dfe42443 1195 if (port->type == PORT_UNKNOWN)
1da177e4
LT		 1196 goto out;
1197
1198 /*
1199 * Reset the UART.
1200 */
1201#ifdef CONFIG_SERIAL_8250_RSA
dfe42443 1202 if (port->type == PORT_RSA)
0acf519f 1203 serial_out(up, UART_RSA_FRR, 0);
1da177e4 1204#endif
0acf519f 1205 serial_out(up, UART_MCR, save_mcr);
1da177e4 1206 serial8250_clear_fifos(up);
40b36daa 1207 serial_in(up, UART_RX);
5c8c755c 1208 if (up->capabilities & UART_CAP_UUE)
0acf519f 1209 serial_out(up, UART_IER, UART_IER_UUE);
5c8c755c 1210 else
0acf519f 1211 serial_out(up, UART_IER, 0);
1da177e4 1212
bd71c182 1213 out:
dfe42443
PG		 1214 spin_unlock_irqrestore(&port->lock, flags);
1215 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1da177e4
LT		 1216}
1217
1218static void autoconfig_irq(struct uart_8250_port *up)
1219{
dfe42443 1220 struct uart_port *port = &up->port;
1da177e4
LT		 1221 unsigned char save_mcr, save_ier;
1222 unsigned char save_ICP = 0;
1223 unsigned int ICP = 0;
1224 unsigned long irqs;
1225 int irq;
1226
dfe42443
PG		 1227 if (port->flags & UPF_FOURPORT) {
1228 ICP = (port->iobase & 0xfe0) | 0x1f;
1da177e4
LT		 1229 save_ICP = inb_p(ICP);
1230 outb_p(0x80, ICP);
0d263a26 1231 inb_p(ICP);
1da177e4
LT		 1232 }
1233
1234 /* forget possible initially masked and pending IRQ */
1235 probe_irq_off(probe_irq_on());
0acf519f
PG		 1236 save_mcr = serial_in(up, UART_MCR);
1237 save_ier = serial_in(up, UART_IER);
1238 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1239
1da177e4 1240 irqs = probe_irq_on();
0acf519f 1241 serial_out(up, UART_MCR, 0);
6f803cd0 1242 udelay(10);
dfe42443 1243 if (port->flags & UPF_FOURPORT) {
0acf519f 1244 serial_out(up, UART_MCR,
1da177e4
LT		 1245 UART_MCR_DTR | UART_MCR_RTS);
1246 } else {
0acf519f 1247 serial_out(up, UART_MCR,
1da177e4
LT		 1248 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1249 }
0acf519f 1250 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
0d263a26
PG		 1251 serial_in(up, UART_LSR);
1252 serial_in(up, UART_RX);
1253 serial_in(up, UART_IIR);
1254 serial_in(up, UART_MSR);
0acf519f 1255 serial_out(up, UART_TX, 0xFF);
6f803cd0 1256 udelay(20);
1da177e4
LT		 1257 irq = probe_irq_off(irqs);
1258
0acf519f
PG		 1259 serial_out(up, UART_MCR, save_mcr);
1260 serial_out(up, UART_IER, save_ier);
1da177e4 1261
dfe42443 1262 if (port->flags & UPF_FOURPORT)
1da177e4
LT		 1263 outb_p(save_ICP, ICP);
1264
dfe42443 1265 port->irq = (irq > 0) ? irq : 0;
1da177e4
LT		 1266}
1267
e763b90c
RK		 1268static inline void __stop_tx(struct uart_8250_port *p)
1269{
1270 if (p->ier & UART_IER_THRI) {
1271 p->ier &= ~UART_IER_THRI;
1272 serial_out(p, UART_IER, p->ier);
1273 }
1274}
1275
b129a8cc 1276static void serial8250_stop_tx(struct uart_port *port)
1da177e4 1277{
49d5741b
JI		 1278 struct uart_8250_port *up =
1279 container_of(port, struct uart_8250_port, port);
1da177e4 1280
e763b90c 1281 __stop_tx(up);
1da177e4
LT		 1282
1283 /*
e763b90c 1284 * We really want to stop the transmitter from sending.
1da177e4 1285 */
dfe42443 1286 if (port->type == PORT_16C950) {
1da177e4
LT		 1287 up->acr |= UART_ACR_TXDIS;
1288 serial_icr_write(up, UART_ACR, up->acr);
1289 }
1290}
1291
b129a8cc 1292static void serial8250_start_tx(struct uart_port *port)
1da177e4 1293{
49d5741b
JI		 1294 struct uart_8250_port *up =
1295 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1296
1297 if (!(up->ier & UART_IER_THRI)) {
1298 up->ier |= UART_IER_THRI;
4fd996a1 1299 serial_port_out(port, UART_IER, up->ier);
55d3b282 1300
67f7654e 1301 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1302 unsigned char lsr;
55d3b282 1303 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1304 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
dfe42443 1305 if ((port->type == PORT_RM9000) ?
68cb4f8e
IJ		 1306 (lsr & UART_LSR_THRE) :
1307 (lsr & UART_LSR_TEMT))
3986fb2b 1308 serial8250_tx_chars(up);
55d3b282 1309 }
1da177e4 1310 }
e763b90c 1311
1da177e4 1312 /*
e763b90c 1313 * Re-enable the transmitter if we disabled it.
1da177e4 1314 */
dfe42443 1315 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1316 up->acr &= ~UART_ACR_TXDIS;
1317 serial_icr_write(up, UART_ACR, up->acr);
1318 }
1319}
1320
1321static void serial8250_stop_rx(struct uart_port *port)
1322{
49d5741b
JI		 1323 struct uart_8250_port *up =
1324 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1325
1326 up->ier &= ~UART_IER_RLSI;
1327 up->port.read_status_mask &= ~UART_LSR_DR;
4fd996a1 1328 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 1329}
1330
1331static void serial8250_enable_ms(struct uart_port *port)
1332{
49d5741b
JI		 1333 struct uart_8250_port *up =
1334 container_of(port, struct uart_8250_port, port);
1da177e4 1335
21c614a7
PA		 1336 /* no MSR capabilities */
1337 if (up->bugs & UART_BUG_NOMSR)
1338 return;
1339
1da177e4 1340 up->ier |= UART_IER_MSI;
4fd996a1 1341 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 1342}
1343
0690f41f 1344/*
3986fb2b 1345 * serial8250_rx_chars: processes according to the passed in LSR
0690f41f
PG		 1346 * value, and returns the remaining LSR bits not handled
1347 * by this Rx routine.
1348 */
3986fb2b
PG		 1349unsigned char
1350serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1da177e4 1351{
dfe42443
PG		 1352 struct uart_port *port = &up->port;
1353 struct tty_struct *tty = port->state->port.tty;
0690f41f 1354 unsigned char ch;
1da177e4
LT		 1355 int max_count = 256;
1356 char flag;
1357
1358 do {
7500b1f6 1359 if (likely(lsr & UART_LSR_DR))
0acf519f 1360 ch = serial_in(up, UART_RX);
7500b1f6
AR		 1361 else
1362 /*
1363 * Intel 82571 has a Serial Over Lan device that will
1364 * set UART_LSR_BI without setting UART_LSR_DR when
1365 * it receives a break. To avoid reading from the
1366 * receive buffer without UART_LSR_DR bit set, we
1367 * just force the read character to be 0
1368 */
1369 ch = 0;
1370
1da177e4 1371 flag = TTY_NORMAL;
dfe42443 1372 port->icount.rx++;
1da177e4 1373
ad4c2aa6
CM		 1374 lsr |= up->lsr_saved_flags;
1375 up->lsr_saved_flags = 0;
1da177e4 1376
ad4c2aa6 1377 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1378 if (lsr & UART_LSR_BI) {
1379 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
dfe42443 1380 port->icount.brk++;
1da177e4
LT		 1381 /*
1382 * We do the SysRQ and SAK checking
1383 * here because otherwise the break
1384 * may get masked by ignore_status_mask
1385 * or read_status_mask.
1386 */
dfe42443 1387 if (uart_handle_break(port))
1da177e4
LT		 1388 goto ignore_char;
1389 } else if (lsr & UART_LSR_PE)
dfe42443 1390 port->icount.parity++;
1da177e4 1391 else if (lsr & UART_LSR_FE)
dfe42443 1392 port->icount.frame++;
1da177e4 1393 if (lsr & UART_LSR_OE)
dfe42443 1394 port->icount.overrun++;
1da177e4
LT		 1395
1396 /*
23907eb8 1397 * Mask off conditions which should be ignored.
1da177e4 1398 */
dfe42443 1399 lsr &= port->read_status_mask;
1da177e4
LT		 1400
1401 if (lsr & UART_LSR_BI) {
1402 DEBUG_INTR("handling break....");
1403 flag = TTY_BREAK;
1404 } else if (lsr & UART_LSR_PE)
1405 flag = TTY_PARITY;
1406 else if (lsr & UART_LSR_FE)
1407 flag = TTY_FRAME;
1408 }
dfe42443 1409 if (uart_handle_sysrq_char(port, ch))
1da177e4 1410 goto ignore_char;
05ab3014 1411
dfe42443 1412 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
05ab3014 1413
6f803cd0 1414ignore_char:
0acf519f 1415 lsr = serial_in(up, UART_LSR);
7500b1f6 1416 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
dfe42443 1417 spin_unlock(&port->lock);
1da177e4 1418 tty_flip_buffer_push(tty);
dfe42443 1419 spin_lock(&port->lock);
0690f41f 1420 return lsr;
1da177e4 1421}
3986fb2b 1422EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1da177e4 1423
3986fb2b 1424void serial8250_tx_chars(struct uart_8250_port *up)
1da177e4 1425{
dfe42443
PG		 1426 struct uart_port *port = &up->port;
1427 struct circ_buf *xmit = &port->state->xmit;
1da177e4
LT		 1428 int count;
1429
dfe42443
PG		 1430 if (port->x_char) {
1431 serial_out(up, UART_TX, port->x_char);
1432 port->icount.tx++;
1433 port->x_char = 0;
1da177e4
LT		 1434 return;
1435 }
dfe42443
PG		 1436 if (uart_tx_stopped(port)) {
1437 serial8250_stop_tx(port);
b129a8cc
RK		 1438 return;
1439 }
1440 if (uart_circ_empty(xmit)) {
e763b90c 1441 __stop_tx(up);
1da177e4
LT		 1442 return;
1443 }
1444
1445 count = up->tx_loadsz;
1446 do {
1447 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1448 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
dfe42443 1449 port->icount.tx++;
1da177e4
LT		 1450 if (uart_circ_empty(xmit))
1451 break;
1452 } while (--count > 0);
1453
1454 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
dfe42443 1455 uart_write_wakeup(port);
1da177e4
LT		 1456
1457 DEBUG_INTR("THRE...");
1458
1459 if (uart_circ_empty(xmit))
e763b90c 1460 __stop_tx(up);
1da177e4 1461}
3986fb2b 1462EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1da177e4 1463
3986fb2b 1464unsigned int serial8250_modem_status(struct uart_8250_port *up)
1da177e4 1465{
dfe42443 1466 struct uart_port *port = &up->port;
2af7cd68
RK		 1467 unsigned int status = serial_in(up, UART_MSR);
1468
ad4c2aa6
CM		 1469 status |= up->msr_saved_flags;
1470 up->msr_saved_flags = 0;
fdc30b3d 1471 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
dfe42443 1472 port->state != NULL) {
2af7cd68 1473 if (status & UART_MSR_TERI)
dfe42443 1474 port->icount.rng++;
2af7cd68 1475 if (status & UART_MSR_DDSR)
dfe42443 1476 port->icount.dsr++;
2af7cd68 1477 if (status & UART_MSR_DDCD)
dfe42443 1478 uart_handle_dcd_change(port, status & UART_MSR_DCD);
2af7cd68 1479 if (status & UART_MSR_DCTS)
dfe42443 1480 uart_handle_cts_change(port, status & UART_MSR_CTS);
2af7cd68 1481
dfe42443 1482 wake_up_interruptible(&port->state->port.delta_msr_wait);
2af7cd68 1483 }
1da177e4 1484
2af7cd68 1485 return status;
1da177e4 1486}
3986fb2b 1487EXPORT_SYMBOL_GPL(serial8250_modem_status);
1da177e4
LT		 1488
1489/*
1490 * This handles the interrupt from one port.
1491 */
86b21199 1492int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1da177e4 1493{
0690f41f 1494 unsigned char status;
4bf3631c 1495 unsigned long flags;
86b21199
PG		 1496 struct uart_8250_port *up =
1497 container_of(port, struct uart_8250_port, port);
1498
1499 if (iir & UART_IIR_NO_INT)
1500 return 0;
45e24601 1501
dfe42443 1502 spin_lock_irqsave(&port->lock, flags);
45e24601 1503
4fd996a1 1504 status = serial_port_in(port, UART_LSR);
1da177e4
LT		 1505
1506 DEBUG_INTR("status = %x...", status);
1507
7500b1f6 1508 if (status & (UART_LSR_DR | UART_LSR_BI))
3986fb2b
PG		 1509 status = serial8250_rx_chars(up, status);
1510 serial8250_modem_status(up);
1da177e4 1511 if (status & UART_LSR_THRE)
3986fb2b 1512 serial8250_tx_chars(up);
45e24601 1513
dfe42443 1514 spin_unlock_irqrestore(&port->lock, flags);
86b21199 1515 return 1;
583d28e9 1516}
c7a1bdc5 1517EXPORT_SYMBOL_GPL(serial8250_handle_irq);
583d28e9
JI		 1518
1519static int serial8250_default_handle_irq(struct uart_port *port)
1520{
4fd996a1 1521 unsigned int iir = serial_port_in(port, UART_IIR);
583d28e9
JI		 1522
1523 return serial8250_handle_irq(port, iir);
1524}
1525
1da177e4
LT		 1526/*
1527 * This is the serial driver's interrupt routine.
1528 *
1529 * Arjan thinks the old way was overly complex, so it got simplified.
1530 * Alan disagrees, saying that need the complexity to handle the weird
1531 * nature of ISA shared interrupts. (This is a special exception.)
1532 *
1533 * In order to handle ISA shared interrupts properly, we need to check
1534 * that all ports have been serviced, and therefore the ISA interrupt
1535 * line has been de-asserted.
1536 *
1537 * This means we need to loop through all ports. checking that they
1538 * don't have an interrupt pending.
1539 */
7d12e780 1540static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1541{
1542 struct irq_info *i = dev_id;
1543 struct list_head *l, *end = NULL;
1544 int pass_counter = 0, handled = 0;
1545
1546 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1547
1548 spin_lock(&i->lock);
1549
1550 l = i->head;
1551 do {
1552 struct uart_8250_port *up;
583d28e9 1553 struct uart_port *port;
1da177e4
LT		 1554
1555 up = list_entry(l, struct uart_8250_port, list);
583d28e9 1556 port = &up->port;
1da177e4 1557
49b532f9 1558 if (port->handle_irq(port)) {
1da177e4 1559 handled = 1;
1da177e4
LT		 1560 end = NULL;
1561 } else if (end == NULL)
1562 end = l;
1563
1564 l = l->next;
1565
1566 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1567 /* If we hit this, we're dead. */
cd3ecad1
DD		 1568 printk_ratelimited(KERN_ERR
1569 "serial8250: too much work for irq%d\n", irq);
1da177e4
LT		 1570 break;
1571 }
1572 } while (l != end);
1573
1574 spin_unlock(&i->lock);
1575
1576 DEBUG_INTR("end.\n");
1577
1578 return IRQ_RETVAL(handled);
1579}
1580
1581/*
1582 * To support ISA shared interrupts, we need to have one interrupt
1583 * handler that ensures that the IRQ line has been deasserted
1584 * before returning. Failing to do this will result in the IRQ
1585 * line being stuck active, and, since ISA irqs are edge triggered,
1586 * no more IRQs will be seen.
1587 */
1588static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1589{
1590 spin_lock_irq(&i->lock);
1591
1592 if (!list_empty(i->head)) {
1593 if (i->head == &up->list)
1594 i->head = i->head->next;
1595 list_del(&up->list);
1596 } else {
1597 BUG_ON(i->head != &up->list);
1598 i->head = NULL;
1599 }
1da177e4 1600 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1601 /* List empty so throw away the hash node */
1602 if (i->head == NULL) {
1603 hlist_del(&i->node);
1604 kfree(i);
1605 }
1da177e4
LT		 1606}
1607
1608static int serial_link_irq_chain(struct uart_8250_port *up)
1609{
25db8ad5
AC		 1610 struct hlist_head *h;
1611 struct hlist_node *n;
1612 struct irq_info *i;
40663cc7 1613 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1614
25db8ad5
AC		 1615 mutex_lock(&hash_mutex);
1616
1617 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1618
1619 hlist_for_each(n, h) {
1620 i = hlist_entry(n, struct irq_info, node);
1621 if (i->irq == up->port.irq)
1622 break;
1623 }
1624
1625 if (n == NULL) {
1626 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1627 if (i == NULL) {
1628 mutex_unlock(&hash_mutex);
1629 return -ENOMEM;
1630 }
1631 spin_lock_init(&i->lock);
1632 i->irq = up->port.irq;
1633 hlist_add_head(&i->node, h);
1634 }
1635 mutex_unlock(&hash_mutex);
1636
1da177e4
LT		 1637 spin_lock_irq(&i->lock);
1638
1639 if (i->head) {
1640 list_add(&up->list, i->head);
1641 spin_unlock_irq(&i->lock);
1642
1643 ret = 0;
1644 } else {
1645 INIT_LIST_HEAD(&up->list);
1646 i->head = &up->list;
1647 spin_unlock_irq(&i->lock);
1c2f0493 1648 irq_flags |= up->port.irqflags;
1da177e4
LT		 1649 ret = request_irq(up->port.irq, serial8250_interrupt,
1650 irq_flags, "serial", i);
1651 if (ret < 0)
1652 serial_do_unlink(i, up);
1653 }
1654
1655 return ret;
1656}
1657
1658static void serial_unlink_irq_chain(struct uart_8250_port *up)
1659{
25db8ad5
AC		 1660 struct irq_info *i;
1661 struct hlist_node *n;
1662 struct hlist_head *h;
1da177e4 1663
25db8ad5
AC		 1664 mutex_lock(&hash_mutex);
1665
1666 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1667
1668 hlist_for_each(n, h) {
1669 i = hlist_entry(n, struct irq_info, node);
1670 if (i->irq == up->port.irq)
1671 break;
1672 }
1673
1674 BUG_ON(n == NULL);
1da177e4
LT		 1675 BUG_ON(i->head == NULL);
1676
1677 if (list_empty(i->head))
1678 free_irq(up->port.irq, i);
1679
1680 serial_do_unlink(i, up);
25db8ad5 1681 mutex_unlock(&hash_mutex);
1da177e4
LT		 1682}
1683
1684/*
1685 * This function is used to handle ports that do not have an
1686 * interrupt. This doesn't work very well for 16450's, but gives
1687 * barely passable results for a 16550A. (Although at the expense
1688 * of much CPU overhead).
1689 */
1690static void serial8250_timeout(unsigned long data)
1691{
1692 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4 1693
a0431476 1694 up->port.handle_irq(&up->port);
54381067 1695 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
40b36daa
AW		 1696}
1697
1698static void serial8250_backup_timeout(unsigned long data)
1699{
1700 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1701 unsigned int iir, ier = 0, lsr;
1702 unsigned long flags;
40b36daa 1703
dbb3b1ca
AC		 1704 spin_lock_irqsave(&up->port.lock, flags);
1705
40b36daa
AW		 1706 /*
1707 * Must disable interrupts or else we risk racing with the interrupt
1708 * based handler.
1709 */
d4e33fac 1710 if (up->port.irq) {
40b36daa
AW		 1711 ier = serial_in(up, UART_IER);
1712 serial_out(up, UART_IER, 0);
1713 }
1da177e4 1714
40b36daa
AW		 1715 iir = serial_in(up, UART_IIR);
1716
1717 /*
1718 * This should be a safe test for anyone who doesn't trust the
1719 * IIR bits on their UART, but it's specifically designed for
1720 * the "Diva" UART used on the management processor on many HP
1721 * ia64 and parisc boxes.
1722 */
ad4c2aa6
CM		 1723 lsr = serial_in(up, UART_LSR);
1724 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
40b36daa 1725 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1726 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1727 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1728 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1729 iir |= UART_IIR_THRI;
1730 }
1731
1732 if (!(iir & UART_IIR_NO_INT))
3986fb2b 1733 serial8250_tx_chars(up);
40b36daa 1734
d4e33fac 1735 if (up->port.irq)
40b36daa
AW		 1736 serial_out(up, UART_IER, ier);
1737
dbb3b1ca
AC		 1738 spin_unlock_irqrestore(&up->port.lock, flags);
1739
40b36daa 1740 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0 1741 mod_timer(&up->timer,
54381067 1742 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1da177e4
LT		 1743}
1744
1745static unsigned int serial8250_tx_empty(struct uart_port *port)
1746{
49d5741b
JI		 1747 struct uart_8250_port *up =
1748 container_of(port, struct uart_8250_port, port);
1da177e4 1749 unsigned long flags;
ad4c2aa6 1750 unsigned int lsr;
1da177e4 1751
dfe42443 1752 spin_lock_irqsave(&port->lock, flags);
4fd996a1 1753 lsr = serial_port_in(port, UART_LSR);
ad4c2aa6 1754 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
dfe42443 1755 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 1756
bca47613 1757 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1758}
1759
1760static unsigned int serial8250_get_mctrl(struct uart_port *port)
1761{
49d5741b
JI		 1762 struct uart_8250_port *up =
1763 container_of(port, struct uart_8250_port, port);
2af7cd68 1764 unsigned int status;
1da177e4
LT		 1765 unsigned int ret;
1766
3986fb2b 1767 status = serial8250_modem_status(up);
1da177e4
LT		 1768
1769 ret = 0;
1770 if (status & UART_MSR_DCD)
1771 ret |= TIOCM_CAR;
1772 if (status & UART_MSR_RI)
1773 ret |= TIOCM_RNG;
1774 if (status & UART_MSR_DSR)
1775 ret |= TIOCM_DSR;
1776 if (status & UART_MSR_CTS)
1777 ret |= TIOCM_CTS;
1778 return ret;
1779}
1780
1781static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1782{
49d5741b
JI		 1783 struct uart_8250_port *up =
1784 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1785 unsigned char mcr = 0;
1786
1787 if (mctrl & TIOCM_RTS)
1788 mcr |= UART_MCR_RTS;
1789 if (mctrl & TIOCM_DTR)
1790 mcr |= UART_MCR_DTR;
1791 if (mctrl & TIOCM_OUT1)
1792 mcr |= UART_MCR_OUT1;
1793 if (mctrl & TIOCM_OUT2)
1794 mcr |= UART_MCR_OUT2;
1795 if (mctrl & TIOCM_LOOP)
1796 mcr |= UART_MCR_LOOP;
1797
1798 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1799
4fd996a1 1800 serial_port_out(port, UART_MCR, mcr);
1da177e4
LT		 1801}
1802
1803static void serial8250_break_ctl(struct uart_port *port, int break_state)
1804{
49d5741b
JI		 1805 struct uart_8250_port *up =
1806 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1807 unsigned long flags;
1808
dfe42443 1809 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 1810 if (break_state == -1)
1811 up->lcr |= UART_LCR_SBC;
1812 else
1813 up->lcr &= ~UART_LCR_SBC;
4fd996a1 1814 serial_port_out(port, UART_LCR, up->lcr);
dfe42443 1815 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1816}
1817
40b36daa
AW		 1818/*
1819 * Wait for transmitter & holding register to empty
1820 */
b5d674ab 1821static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1822{
1823 unsigned int status, tmout = 10000;
1824
1825 /* Wait up to 10ms for the character(s) to be sent. */
97d303b7 1826 for (;;) {
40b36daa
AW		 1827 status = serial_in(up, UART_LSR);
1828
ad4c2aa6 1829 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa 1830
97d303b7
DD		 1831 if ((status & bits) == bits)
1832 break;
40b36daa
AW		 1833 if (--tmout == 0)
1834 break;
1835 udelay(1);
97d303b7 1836 }
40b36daa
AW		 1837
1838 /* Wait up to 1s for flow control if necessary */
1839 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1840 unsigned int tmout;
1841 for (tmout = 1000000; tmout; tmout--) {
1842 unsigned int msr = serial_in(up, UART_MSR);
1843 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1844 if (msr & UART_MSR_CTS)
1845 break;
40b36daa
AW		 1846 udelay(1);
1847 touch_nmi_watchdog();
1848 }
1849 }
1850}
1851
f2d937f3
JW		 1852#ifdef CONFIG_CONSOLE_POLL
1853/*
1854 * Console polling routines for writing and reading from the uart while
1855 * in an interrupt or debug context.
1856 */
1857
1858static int serial8250_get_poll_char(struct uart_port *port)
1859{
4fd996a1 1860 unsigned char lsr = serial_port_in(port, UART_LSR);
f2d937f3 1861
f5316b4a
JW		 1862 if (!(lsr & UART_LSR_DR))
1863 return NO_POLL_CHAR;
f2d937f3 1864
4fd996a1 1865 return serial_port_in(port, UART_RX);
f2d937f3
JW		 1866}
1867
1868
1869static void serial8250_put_poll_char(struct uart_port *port,
1870 unsigned char c)
1871{
1872 unsigned int ier;
49d5741b
JI		 1873 struct uart_8250_port *up =
1874 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1875
1876 /*
1877 * First save the IER then disable the interrupts
1878 */
4fd996a1 1879 ier = serial_port_in(port, UART_IER);
f2d937f3 1880 if (up->capabilities & UART_CAP_UUE)
4fd996a1 1881 serial_port_out(port, UART_IER, UART_IER_UUE);
f2d937f3 1882 else
4fd996a1 1883 serial_port_out(port, UART_IER, 0);
f2d937f3
JW		 1884
1885 wait_for_xmitr(up, BOTH_EMPTY);
1886 /*
1887 * Send the character out.
1888 * If a LF, also do CR...
1889 */
4fd996a1 1890 serial_port_out(port, UART_TX, c);
f2d937f3
JW		 1891 if (c == 10) {
1892 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 1893 serial_port_out(port, UART_TX, 13);
f2d937f3
JW		 1894 }
1895
1896 /*
1897 * Finally, wait for transmitter to become empty
1898 * and restore the IER
1899 */
1900 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 1901 serial_port_out(port, UART_IER, ier);
f2d937f3
JW		 1902}
1903
1904#endif /* CONFIG_CONSOLE_POLL */
1905
1da177e4
LT		 1906static int serial8250_startup(struct uart_port *port)
1907{
49d5741b
JI		 1908 struct uart_8250_port *up =
1909 container_of(port, struct uart_8250_port, port);
1da177e4 1910 unsigned long flags;
55d3b282 1911 unsigned char lsr, iir;
1da177e4
LT		 1912 int retval;
1913
dfe42443 1914 port->fifosize = uart_config[up->port.type].fifo_size;
e4f05af1 1915 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1da177e4
LT		 1916 up->capabilities = uart_config[up->port.type].flags;
1917 up->mcr = 0;
1918
dfe42443 1919 if (port->iotype != up->cur_iotype)
b8e7e40a
AC		 1920 set_io_from_upio(port);
1921
dfe42443 1922 if (port->type == PORT_16C950) {
1da177e4
LT		 1923 /* Wake up and initialize UART */
1924 up->acr = 0;
4fd996a1
PG		 1925 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1926 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1927 serial_port_out(port, UART_IER, 0);
1928 serial_port_out(port, UART_LCR, 0);
1da177e4 1929 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
4fd996a1
PG		 1930 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1931 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1932 serial_port_out(port, UART_LCR, 0);
1da177e4
LT		 1933 }
1934
1935#ifdef CONFIG_SERIAL_8250_RSA
1936 /*
1937 * If this is an RSA port, see if we can kick it up to the
1938 * higher speed clock.
1939 */
1940 enable_rsa(up);
1941#endif
1942
1943 /*
1944 * Clear the FIFO buffers and disable them.
7f927fcc 1945 * (they will be reenabled in set_termios())
1da177e4
LT		 1946 */
1947 serial8250_clear_fifos(up);
1948
1949 /*
1950 * Clear the interrupt registers.
1951 */
4fd996a1
PG		 1952 serial_port_in(port, UART_LSR);
1953 serial_port_in(port, UART_RX);
1954 serial_port_in(port, UART_IIR);
1955 serial_port_in(port, UART_MSR);
1da177e4
LT		 1956
1957 /*
1958 * At this point, there's no way the LSR could still be 0xff;
1959 * if it is, then bail out, because there's likely no UART
1960 * here.
1961 */
dfe42443 1962 if (!(port->flags & UPF_BUGGY_UART) &&
4fd996a1 1963 (serial_port_in(port, UART_LSR) == 0xff)) {
7808a4c4 1964 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
dfe42443 1965 serial_index(port));
1da177e4
LT		 1966 return -ENODEV;
1967 }
1968
1969 /*
1970 * For a XR16C850, we need to set the trigger levels
1971 */
dfe42443 1972 if (port->type == PORT_16850) {
1da177e4
LT		 1973 unsigned char fctr;
1974
0acf519f 1975 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4 1976
0acf519f 1977 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
4fd996a1
PG		 1978 serial_port_out(port, UART_FCTR,
1979 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1980 serial_port_out(port, UART_TRG, UART_TRG_96);
1981 serial_port_out(port, UART_FCTR,
1982 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1983 serial_port_out(port, UART_TRG, UART_TRG_96);
1da177e4 1984
4fd996a1 1985 serial_port_out(port, UART_LCR, 0);
1da177e4
LT		 1986 }
1987
dfe42443 1988 if (port->irq) {
01c194d9 1989 unsigned char iir1;
40b36daa
AW		 1990 /*
1991 * Test for UARTs that do not reassert THRE when the
1992 * transmitter is idle and the interrupt has already
1993 * been cleared. Real 16550s should always reassert
1994 * this interrupt whenever the transmitter is idle and
1995 * the interrupt is enabled. Delays are necessary to
1996 * allow register changes to become visible.
1997 */
dfe42443 1998 spin_lock_irqsave(&port->lock, flags);
1c2f0493 1999 if (up->port.irqflags & IRQF_SHARED)
dfe42443 2000 disable_irq_nosync(port->irq);
40b36daa
AW		 2001
2002 wait_for_xmitr(up, UART_LSR_THRE);
55e4016d 2003 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
40b36daa 2004 udelay(1); /* allow THRE to set */
4fd996a1
PG		 2005 iir1 = serial_port_in(port, UART_IIR);
2006 serial_port_out(port, UART_IER, 0);
55e4016d 2007 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
40b36daa 2008 udelay(1); /* allow a working UART time to re-assert THRE */
4fd996a1
PG		 2009 iir = serial_port_in(port, UART_IIR);
2010 serial_port_out(port, UART_IER, 0);
40b36daa 2011
dfe42443
PG		 2012 if (port->irqflags & IRQF_SHARED)
2013 enable_irq(port->irq);
2014 spin_unlock_irqrestore(&port->lock, flags);
40b36daa
AW		 2015
2016 /*
bc02d15a
DW		 2017 * If the interrupt is not reasserted, or we otherwise
2018 * don't trust the iir, setup a timer to kick the UART
2019 * on a regular basis.
40b36daa 2020 */
bc02d15a
DW		 2021 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2022 up->port.flags & UPF_BUG_THRE) {
363f66fe 2023 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2024 pr_debug("ttyS%d - using backup timer\n",
2025 serial_index(port));
40b36daa
AW		 2026 }
2027 }
2028
363f66fe
WN		 2029 /*
2030 * The above check will only give an accurate result the first time
2031 * the port is opened so this value needs to be preserved.
2032 */
2033 if (up->bugs & UART_BUG_THRE) {
2034 up->timer.function = serial8250_backup_timeout;
2035 up->timer.data = (unsigned long)up;
2036 mod_timer(&up->timer, jiffies +
54381067 2037 uart_poll_timeout(port) + HZ / 5);
363f66fe
WN		 2038 }
2039
1da177e4
LT		 2040 /*
2041 * If the "interrupt" for this port doesn't correspond with any
2042 * hardware interrupt, we use a timer-based system. The original
2043 * driver used to do this with IRQ0.
2044 */
dfe42443 2045 if (!port->irq) {
1da177e4 2046 up->timer.data = (unsigned long)up;
54381067 2047 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
1da177e4
LT		 2048 } else {
2049 retval = serial_link_irq_chain(up);
2050 if (retval)
2051 return retval;
2052 }
2053
2054 /*
2055 * Now, initialize the UART
2056 */
4fd996a1 2057 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
1da177e4 2058
dfe42443 2059 spin_lock_irqsave(&port->lock, flags);
1da177e4 2060 if (up->port.flags & UPF_FOURPORT) {
d4e33fac 2061 if (!up->port.irq)
1da177e4
LT		 2062 up->port.mctrl |= TIOCM_OUT1;
2063 } else
2064 /*
2065 * Most PC uarts need OUT2 raised to enable interrupts.
2066 */
dfe42443 2067 if (port->irq)
1da177e4
LT		 2068 up->port.mctrl |= TIOCM_OUT2;
2069
dfe42443 2070 serial8250_set_mctrl(port, port->mctrl);
55d3b282 2071
b6adea33
MCC		 2072 /* Serial over Lan (SoL) hack:
2073 Intel 8257x Gigabit ethernet chips have a
2074 16550 emulation, to be used for Serial Over Lan.
2075 Those chips take a longer time than a normal
2076 serial device to signalize that a transmission
2077 data was queued. Due to that, the above test generally
2078 fails. One solution would be to delay the reading of
2079 iir. However, this is not reliable, since the timeout
2080 is variable. So, let's just don't test if we receive
2081 TX irq. This way, we'll never enable UART_BUG_TXEN.
2082 */
d41a4b51 2083 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2084 goto dont_test_tx_en;
2085
55d3b282
RK		 2086 /*
2087 * Do a quick test to see if we receive an
2088 * interrupt when we enable the TX irq.
2089 */
4fd996a1
PG		 2090 serial_port_out(port, UART_IER, UART_IER_THRI);
2091 lsr = serial_port_in(port, UART_LSR);
2092 iir = serial_port_in(port, UART_IIR);
2093 serial_port_out(port, UART_IER, 0);
55d3b282
RK		 2094
2095 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2096 if (!(up->bugs & UART_BUG_TXEN)) {
2097 up->bugs |= UART_BUG_TXEN;
55d3b282 2098 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2099 serial_index(port));
55d3b282
RK		 2100 }
2101 } else {
67f7654e 2102 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2103 }
2104
b6adea33 2105dont_test_tx_en:
dfe42443 2106 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 2107
ad4c2aa6
CM		 2108 /*
2109 * Clear the interrupt registers again for luck, and clear the
2110 * saved flags to avoid getting false values from polling
2111 * routines or the previous session.
2112 */
4fd996a1
PG		 2113 serial_port_in(port, UART_LSR);
2114 serial_port_in(port, UART_RX);
2115 serial_port_in(port, UART_IIR);
2116 serial_port_in(port, UART_MSR);
ad4c2aa6
CM		 2117 up->lsr_saved_flags = 0;
2118 up->msr_saved_flags = 0;
2119
1da177e4
LT		 2120 /*
2121 * Finally, enable interrupts. Note: Modem status interrupts
2122 * are set via set_termios(), which will be occurring imminently
2123 * anyway, so we don't enable them here.
2124 */
2125 up->ier = UART_IER_RLSI | UART_IER_RDI;
4fd996a1 2126 serial_port_out(port, UART_IER, up->ier);
1da177e4 2127
dfe42443 2128 if (port->flags & UPF_FOURPORT) {
1da177e4
LT		 2129 unsigned int icp;
2130 /*
2131 * Enable interrupts on the AST Fourport board
2132 */
dfe42443 2133 icp = (port->iobase & 0xfe0) | 0x01f;
1da177e4 2134 outb_p(0x80, icp);
0d263a26 2135 inb_p(icp);
1da177e4
LT		 2136 }
2137
1da177e4
LT		 2138 return 0;
2139}
2140
2141static void serial8250_shutdown(struct uart_port *port)
2142{
49d5741b
JI		 2143 struct uart_8250_port *up =
2144 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2145 unsigned long flags;
2146
2147 /*
2148 * Disable interrupts from this port
2149 */
2150 up->ier = 0;
4fd996a1 2151 serial_port_out(port, UART_IER, 0);
1da177e4 2152
dfe42443
PG		 2153 spin_lock_irqsave(&port->lock, flags);
2154 if (port->flags & UPF_FOURPORT) {
1da177e4 2155 /* reset interrupts on the AST Fourport board */
dfe42443
PG		 2156 inb((port->iobase & 0xfe0) | 0x1f);
2157 port->mctrl |= TIOCM_OUT1;
1da177e4 2158 } else
dfe42443 2159 port->mctrl &= ~TIOCM_OUT2;
1da177e4 2160
dfe42443
PG		 2161 serial8250_set_mctrl(port, port->mctrl);
2162 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 2163
2164 /*
2165 * Disable break condition and FIFOs
2166 */
4fd996a1
PG		 2167 serial_port_out(port, UART_LCR,
2168 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
1da177e4
LT		 2169 serial8250_clear_fifos(up);
2170
2171#ifdef CONFIG_SERIAL_8250_RSA
2172 /*
2173 * Reset the RSA board back to 115kbps compat mode.
2174 */
2175 disable_rsa(up);
2176#endif
2177
2178 /*
2179 * Read data port to reset things, and then unlink from
2180 * the IRQ chain.
2181 */
4fd996a1 2182 serial_port_in(port, UART_RX);
1da177e4 2183
40b36daa
AW		 2184 del_timer_sync(&up->timer);
2185 up->timer.function = serial8250_timeout;
dfe42443 2186 if (port->irq)
1da177e4
LT		 2187 serial_unlink_irq_chain(up);
2188}
2189
2190static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2191{
2192 unsigned int quot;
2193
2194 /*
2195 * Handle magic divisors for baud rates above baud_base on
2196 * SMSC SuperIO chips.
2197 */
2198 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2199 baud == (port->uartclk/4))
2200 quot = 0x8001;
2201 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2202 baud == (port->uartclk/8))
2203 quot = 0x8002;
2204 else
2205 quot = uart_get_divisor(port, baud);
2206
2207 return quot;
2208}
2209
235dae5d
PL		 2210void
2211serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2212 struct ktermios *old)
1da177e4 2213{
49d5741b
JI		 2214 struct uart_8250_port *up =
2215 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2216 unsigned char cval, fcr = 0;
2217 unsigned long flags;
2218 unsigned int baud, quot;
2219
2220 switch (termios->c_cflag & CSIZE) {
2221 case CS5:
0a8b80c5 2222 cval = UART_LCR_WLEN5;
1da177e4
LT		 2223 break;
2224 case CS6:
0a8b80c5 2225 cval = UART_LCR_WLEN6;
1da177e4
LT		 2226 break;
2227 case CS7:
0a8b80c5 2228 cval = UART_LCR_WLEN7;
1da177e4
LT		 2229 break;
2230 default:
2231 case CS8:
0a8b80c5 2232 cval = UART_LCR_WLEN8;
1da177e4
LT		 2233 break;
2234 }
2235
2236 if (termios->c_cflag & CSTOPB)
0a8b80c5 2237 cval |= UART_LCR_STOP;
1da177e4
LT		 2238 if (termios->c_cflag & PARENB)
2239 cval |= UART_LCR_PARITY;
2240 if (!(termios->c_cflag & PARODD))
2241 cval |= UART_LCR_EPAR;
2242#ifdef CMSPAR
2243 if (termios->c_cflag & CMSPAR)
2244 cval |= UART_LCR_SPAR;
2245#endif
2246
2247 /*
2248 * Ask the core to calculate the divisor for us.
2249 */
24d481ec
AV		 2250 baud = uart_get_baud_rate(port, termios, old,
2251 port->uartclk / 16 / 0xffff,
2252 port->uartclk / 16);
1da177e4
LT		 2253 quot = serial8250_get_divisor(port, baud);
2254
2255 /*
4ba5e35d 2256 * Oxford Semi 952 rev B workaround
1da177e4 2257 */
4ba5e35d 2258 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2259 quot++;
1da177e4 2260
dfe42443 2261 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
f9a9111b
CM		 2262 fcr = uart_config[port->type].fcr;
2263 if (baud < 2400) {
2264 fcr &= ~UART_FCR_TRIGGER_MASK;
2265 fcr |= UART_FCR_TRIGGER_1;
2266 }
1da177e4
LT		 2267 }
2268
2269 /*
2270 * MCR-based auto flow control. When AFE is enabled, RTS will be
2271 * deasserted when the receive FIFO contains more characters than
2272 * the trigger, or the MCR RTS bit is cleared. In the case where
2273 * the remote UART is not using CTS auto flow control, we must
2274 * have sufficient FIFO entries for the latency of the remote
2275 * UART to respond. IOW, at least 32 bytes of FIFO.
2276 */
dfe42443 2277 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
1da177e4
LT		 2278 up->mcr &= ~UART_MCR_AFE;
2279 if (termios->c_cflag & CRTSCTS)
2280 up->mcr |= UART_MCR_AFE;
2281 }
2282
2283 /*
2284 * Ok, we're now changing the port state. Do it with
2285 * interrupts disabled.
2286 */
dfe42443 2287 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 2288
2289 /*
2290 * Update the per-port timeout.
2291 */
2292 uart_update_timeout(port, termios->c_cflag, baud);
2293
dfe42443 2294 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1da177e4 2295 if (termios->c_iflag & INPCK)
dfe42443 2296 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1da177e4 2297 if (termios->c_iflag & (BRKINT | PARMRK))
dfe42443 2298 port->read_status_mask |= UART_LSR_BI;
1da177e4
LT		 2299
2300 /*
2301 * Characteres to ignore
2302 */
dfe42443 2303 port->ignore_status_mask = 0;
1da177e4 2304 if (termios->c_iflag & IGNPAR)
dfe42443 2305 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1da177e4 2306 if (termios->c_iflag & IGNBRK) {
dfe42443 2307 port->ignore_status_mask |= UART_LSR_BI;
1da177e4
LT		 2308 /*
2309 * If we're ignoring parity and break indicators,
2310 * ignore overruns too (for real raw support).
2311 */
2312 if (termios->c_iflag & IGNPAR)
dfe42443 2313 port->ignore_status_mask |= UART_LSR_OE;
1da177e4
LT		 2314 }
2315
2316 /*
2317 * ignore all characters if CREAD is not set
2318 */
2319 if ((termios->c_cflag & CREAD) == 0)
dfe42443 2320 port->ignore_status_mask |= UART_LSR_DR;
1da177e4
LT		 2321
2322 /*
2323 * CTS flow control flag and modem status interrupts
2324 */
f8b372a1 2325 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2326 if (!(up->bugs & UART_BUG_NOMSR) &&
2327 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2328 up->ier |= UART_IER_MSI;
2329 if (up->capabilities & UART_CAP_UUE)
4539c24f
SW		 2330 up->ier |= UART_IER_UUE;
2331 if (up->capabilities & UART_CAP_RTOIE)
2332 up->ier |= UART_IER_RTOIE;
1da177e4 2333
4fd996a1 2334 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 2335
2336 if (up->capabilities & UART_CAP_EFR) {
2337 unsigned char efr = 0;
2338 /*
2339 * TI16C752/Startech hardware flow control. FIXME:
2340 * - TI16C752 requires control thresholds to be set.
2341 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2342 */
2343 if (termios->c_cflag & CRTSCTS)
2344 efr |= UART_EFR_CTS;
2345
4fd996a1 2346 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
dfe42443 2347 if (port->flags & UPF_EXAR_EFR)
4fd996a1 2348 serial_port_out(port, UART_XR_EFR, efr);
06315348 2349 else
4fd996a1 2350 serial_port_out(port, UART_EFR, efr);
1da177e4
LT		 2351 }
2352
f2eda27d 2353#ifdef CONFIG_ARCH_OMAP
255341c6 2354 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
5668545a 2355 if (cpu_is_omap1510() && is_omap_port(up)) {
255341c6
JM		 2356 if (baud == 115200) {
2357 quot = 1;
4fd996a1 2358 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
255341c6 2359 } else
4fd996a1 2360 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
255341c6
JM		 2361 }
2362#endif
2363
4fd996a1
PG		 2364 /*
2365 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2366 * otherwise just set DLAB
2367 */
2368 if (up->capabilities & UART_NATSEMI)
2369 serial_port_out(port, UART_LCR, 0xe0);
2370 else
2371 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
1da177e4 2372
b32b19b8 2373 serial_dl_write(up, quot);
1da177e4
LT		 2374
2375 /*
2376 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2377 * is written without DLAB set, this mode will be disabled.
2378 */
dfe42443 2379 if (port->type == PORT_16750)
4fd996a1 2380 serial_port_out(port, UART_FCR, fcr);
1da177e4 2381
4fd996a1 2382 serial_port_out(port, UART_LCR, cval); /* reset DLAB */
1da177e4 2383 up->lcr = cval; /* Save LCR */
dfe42443 2384 if (port->type != PORT_16750) {
4fd996a1
PG		 2385 /* emulated UARTs (Lucent Venus 167x) need two steps */
2386 if (fcr & UART_FCR_ENABLE_FIFO)
2387 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2388 serial_port_out(port, UART_FCR, fcr); /* set fcr */
1da177e4 2389 }
dfe42443
PG		 2390 serial8250_set_mctrl(port, port->mctrl);
2391 spin_unlock_irqrestore(&port->lock, flags);
e991a2bd
AC		 2392 /* Don't rewrite B0 */
2393 if (tty_termios_baud_rate(termios))
2394 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4 2395}
235dae5d
PL		 2396EXPORT_SYMBOL(serial8250_do_set_termios);
2397
2398static void
2399serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2400 struct ktermios *old)
2401{
2402 if (port->set_termios)
2403 port->set_termios(port, termios, old);
2404 else
2405 serial8250_do_set_termios(port, termios, old);
2406}
1da177e4 2407
dc77f161 2408static void
a0821df6 2409serial8250_set_ldisc(struct uart_port *port, int new)
dc77f161 2410{
a0821df6 2411 if (new == N_PPS) {
dc77f161
RG		 2412 port->flags |= UPF_HARDPPS_CD;
2413 serial8250_enable_ms(port);
2414 } else
2415 port->flags &= ~UPF_HARDPPS_CD;
2416}
2417
c161afe9
ML		 2418
2419void serial8250_do_pm(struct uart_port *port, unsigned int state,
2420 unsigned int oldstate)
1da177e4 2421{
49d5741b
JI		 2422 struct uart_8250_port *p =
2423 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2424
2425 serial8250_set_sleep(p, state != 0);
c161afe9
ML		 2426}
2427EXPORT_SYMBOL(serial8250_do_pm);
1da177e4 2428
c161afe9
ML		 2429static void
2430serial8250_pm(struct uart_port *port, unsigned int state,
2431 unsigned int oldstate)
2432{
2433 if (port->pm)
2434 port->pm(port, state, oldstate);
2435 else
2436 serial8250_do_pm(port, state, oldstate);
1da177e4
LT		 2437}
2438
f2eda27d
RK		 2439static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2440{
2441 if (pt->port.iotype == UPIO_AU)
b2b13cdf 2442 return 0x1000;
f2eda27d
RK		 2443#ifdef CONFIG_ARCH_OMAP
2444 if (is_omap_port(pt))
2445 return 0x16 << pt->port.regshift;
2446#endif
2447 return 8 << pt->port.regshift;
2448}
2449
1da177e4
LT		 2450/*
2451 * Resource handling.
2452 */
2453static int serial8250_request_std_resource(struct uart_8250_port *up)
2454{
f2eda27d 2455 unsigned int size = serial8250_port_size(up);
dfe42443 2456 struct uart_port *port = &up->port;
1da177e4
LT		 2457 int ret = 0;
2458
dfe42443 2459 switch (port->iotype) {
85835f44 2460 case UPIO_AU:
0b30d668
SS		 2461 case UPIO_TSI:
2462 case UPIO_MEM32:
1da177e4 2463 case UPIO_MEM:
dfe42443 2464 if (!port->mapbase)
1da177e4
LT		 2465 break;
2466
dfe42443 2467 if (!request_mem_region(port->mapbase, size, "serial")) {
1da177e4
LT		 2468 ret = -EBUSY;
2469 break;
2470 }
2471
dfe42443
PG		 2472 if (port->flags & UPF_IOREMAP) {
2473 port->membase = ioremap_nocache(port->mapbase, size);
2474 if (!port->membase) {
2475 release_mem_region(port->mapbase, size);
1da177e4
LT		 2476 ret = -ENOMEM;
2477 }
2478 }
2479 break;
2480
2481 case UPIO_HUB6:
2482 case UPIO_PORT:
dfe42443 2483 if (!request_region(port->iobase, size, "serial"))
1da177e4
LT		 2484 ret = -EBUSY;
2485 break;
2486 }
2487 return ret;
2488}
2489
2490static void serial8250_release_std_resource(struct uart_8250_port *up)
2491{
f2eda27d 2492 unsigned int size = serial8250_port_size(up);
dfe42443 2493 struct uart_port *port = &up->port;
1da177e4 2494
dfe42443 2495 switch (port->iotype) {
85835f44 2496 case UPIO_AU:
0b30d668
SS		 2497 case UPIO_TSI:
2498 case UPIO_MEM32:
1da177e4 2499 case UPIO_MEM:
dfe42443 2500 if (!port->mapbase)
1da177e4
LT		 2501 break;
2502
dfe42443
PG		 2503 if (port->flags & UPF_IOREMAP) {
2504 iounmap(port->membase);
2505 port->membase = NULL;
1da177e4
LT		 2506 }
2507
dfe42443 2508 release_mem_region(port->mapbase, size);
1da177e4
LT		 2509 break;
2510
2511 case UPIO_HUB6:
2512 case UPIO_PORT:
dfe42443 2513 release_region(port->iobase, size);
1da177e4
LT		 2514 break;
2515 }
2516}
2517
2518static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2519{
2520 unsigned long start = UART_RSA_BASE << up->port.regshift;
2521 unsigned int size = 8 << up->port.regshift;
dfe42443 2522 struct uart_port *port = &up->port;
0b30d668 2523 int ret = -EINVAL;
1da177e4 2524
dfe42443 2525 switch (port->iotype) {
1da177e4
LT		 2526 case UPIO_HUB6:
2527 case UPIO_PORT:
dfe42443 2528 start += port->iobase;
0b30d668
SS		 2529 if (request_region(start, size, "serial-rsa"))
2530 ret = 0;
2531 else
1da177e4
LT		 2532 ret = -EBUSY;
2533 break;
2534 }
2535
2536 return ret;
2537}
2538
2539static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2540{
2541 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2542 unsigned int size = 8 << up->port.regshift;
dfe42443 2543 struct uart_port *port = &up->port;
1da177e4 2544
dfe42443 2545 switch (port->iotype) {
1da177e4
LT		 2546 case UPIO_HUB6:
2547 case UPIO_PORT:
dfe42443 2548 release_region(port->iobase + offset, size);
1da177e4
LT		 2549 break;
2550 }
2551}
2552
2553static void serial8250_release_port(struct uart_port *port)
2554{
49d5741b
JI		 2555 struct uart_8250_port *up =
2556 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2557
2558 serial8250_release_std_resource(up);
dfe42443 2559 if (port->type == PORT_RSA)
1da177e4
LT		 2560 serial8250_release_rsa_resource(up);
2561}
2562
2563static int serial8250_request_port(struct uart_port *port)
2564{
49d5741b
JI		 2565 struct uart_8250_port *up =
2566 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2567 int ret = 0;
2568
2569 ret = serial8250_request_std_resource(up);
dfe42443 2570 if (ret == 0 && port->type == PORT_RSA) {
1da177e4
LT		 2571 ret = serial8250_request_rsa_resource(up);
2572 if (ret < 0)
2573 serial8250_release_std_resource(up);
2574 }
2575
2576 return ret;
2577}
2578
2579static void serial8250_config_port(struct uart_port *port, int flags)
2580{
49d5741b
JI		 2581 struct uart_8250_port *up =
2582 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2583 int probeflags = PROBE_ANY;
2584 int ret;
2585
1da177e4
LT		 2586 /*
2587 * Find the region that we can probe for. This in turn
2588 * tells us whether we can probe for the type of port.
2589 */
2590 ret = serial8250_request_std_resource(up);
2591 if (ret < 0)
2592 return;
2593
2594 ret = serial8250_request_rsa_resource(up);
2595 if (ret < 0)
2596 probeflags &= ~PROBE_RSA;
2597
dfe42443 2598 if (port->iotype != up->cur_iotype)
b8e7e40a
AC		 2599 set_io_from_upio(port);
2600
1da177e4
LT		 2601 if (flags & UART_CONFIG_TYPE)
2602 autoconfig(up, probeflags);
b2b13cdf 2603
b2b13cdf 2604 /* if access method is AU, it is a 16550 with a quirk */
dfe42443 2605 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
b2b13cdf 2606 up->bugs |= UART_BUG_NOMSR;
b2b13cdf 2607
dfe42443 2608 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
1da177e4
LT		 2609 autoconfig_irq(up);
2610
dfe42443 2611 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
1da177e4 2612 serial8250_release_rsa_resource(up);
dfe42443 2613 if (port->type == PORT_UNKNOWN)
1da177e4
LT		 2614 serial8250_release_std_resource(up);
2615}
2616
2617static int
2618serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2619{
a62c4133 2620 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2621 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2622 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2623 ser->type == PORT_STARTECH)
2624 return -EINVAL;
2625 return 0;
2626}
2627
2628static const char *
2629serial8250_type(struct uart_port *port)
2630{
2631 int type = port->type;
2632
2633 if (type >= ARRAY_SIZE(uart_config))
2634 type = 0;
2635 return uart_config[type].name;
2636}
2637
2638static struct uart_ops serial8250_pops = {
2639 .tx_empty = serial8250_tx_empty,
2640 .set_mctrl = serial8250_set_mctrl,
2641 .get_mctrl = serial8250_get_mctrl,
2642 .stop_tx = serial8250_stop_tx,
2643 .start_tx = serial8250_start_tx,
2644 .stop_rx = serial8250_stop_rx,
2645 .enable_ms = serial8250_enable_ms,
2646 .break_ctl = serial8250_break_ctl,
2647 .startup = serial8250_startup,
2648 .shutdown = serial8250_shutdown,
2649 .set_termios = serial8250_set_termios,
dc77f161 2650 .set_ldisc = serial8250_set_ldisc,
1da177e4
LT		 2651 .pm = serial8250_pm,
2652 .type = serial8250_type,
2653 .release_port = serial8250_release_port,
2654 .request_port = serial8250_request_port,
2655 .config_port = serial8250_config_port,
2656 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2657#ifdef CONFIG_CONSOLE_POLL
2658 .poll_get_char = serial8250_get_poll_char,
2659 .poll_put_char = serial8250_put_poll_char,
2660#endif
1da177e4
LT		 2661};
2662
2663static struct uart_8250_port serial8250_ports[UART_NR];
2664
af7f3743
AC		 2665static void (*serial8250_isa_config)(int port, struct uart_port *up,
2666 unsigned short *capabilities);
2667
2668void serial8250_set_isa_configurator(
2669 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2670{
2671 serial8250_isa_config = v;
2672}
2673EXPORT_SYMBOL(serial8250_set_isa_configurator);
2674
1da177e4
LT		 2675static void __init serial8250_isa_init_ports(void)
2676{
2677 struct uart_8250_port *up;
2678 static int first = 1;
4c0ebb80 2679 int i, irqflag = 0;
1da177e4
LT		 2680
2681 if (!first)
2682 return;
2683 first = 0;
2684
a61c2d78 2685 for (i = 0; i < nr_uarts; i++) {
1da177e4 2686 struct uart_8250_port *up = &serial8250_ports[i];
dfe42443 2687 struct uart_port *port = &up->port;
1da177e4 2688
dfe42443
PG		 2689 port->line = i;
2690 spin_lock_init(&port->lock);
1da177e4
LT		 2691
2692 init_timer(&up->timer);
2693 up->timer.function = serial8250_timeout;
2694
2695 /*
2696 * ALPHA_KLUDGE_MCR needs to be killed.
2697 */
2698 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2699 up->mcr_force = ALPHA_KLUDGE_MCR;
2700
dfe42443 2701 port->ops = &serial8250_pops;
1da177e4
LT		 2702 }
2703
4c0ebb80
AGR		 2704 if (share_irqs)
2705 irqflag = IRQF_SHARED;
2706
44454bcd 2707 for (i = 0, up = serial8250_ports;
a61c2d78 2708 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4 2709 i++, up++) {
dfe42443
PG		 2710 struct uart_port *port = &up->port;
2711
2712 port->iobase = old_serial_port[i].port;
2713 port->irq = irq_canonicalize(old_serial_port[i].irq);
2714 port->irqflags = old_serial_port[i].irqflags;
2715 port->uartclk = old_serial_port[i].baud_base * 16;
2716 port->flags = old_serial_port[i].flags;
2717 port->hub6 = old_serial_port[i].hub6;
2718 port->membase = old_serial_port[i].iomem_base;
2719 port->iotype = old_serial_port[i].io_type;
2720 port->regshift = old_serial_port[i].iomem_reg_shift;
2721 set_io_from_upio(port);
2722 port->irqflags |= irqflag;
af7f3743
AC		 2723 if (serial8250_isa_config != NULL)
2724 serial8250_isa_config(i, &up->port, &up->capabilities);
2725
1da177e4
LT		 2726 }
2727}
2728
b5d228cc
SL		 2729static void
2730serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2731{
2732 up->port.type = type;
2733 up->port.fifosize = uart_config[type].fifo_size;
2734 up->capabilities = uart_config[type].flags;
2735 up->tx_loadsz = uart_config[type].tx_loadsz;
2736}
2737
1da177e4
LT		 2738static void __init
2739serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2740{
2741 int i;
2742
b8e7e40a
AC		 2743 for (i = 0; i < nr_uarts; i++) {
2744 struct uart_8250_port *up = &serial8250_ports[i];
2745 up->cur_iotype = 0xFF;
2746 }
2747
1da177e4
LT		 2748 serial8250_isa_init_ports();
2749
a61c2d78 2750 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2751 struct uart_8250_port *up = &serial8250_ports[i];
2752
2753 up->port.dev = dev;
b5d228cc
SL		 2754
2755 if (up->port.flags & UPF_FIXED_TYPE)
2756 serial8250_init_fixed_type_port(up, up->port.type);
2757
1da177e4
LT		 2758 uart_add_one_port(drv, &up->port);
2759 }
2760}
2761
2762#ifdef CONFIG_SERIAL_8250_CONSOLE
2763
d358788f
RK		 2764static void serial8250_console_putchar(struct uart_port *port, int ch)
2765{
49d5741b
JI		 2766 struct uart_8250_port *up =
2767 container_of(port, struct uart_8250_port, port);
d358788f
RK		 2768
2769 wait_for_xmitr(up, UART_LSR_THRE);
4fd996a1 2770 serial_port_out(port, UART_TX, ch);
d358788f
RK		 2771}
2772
1da177e4
LT		 2773/*
2774 * Print a string to the serial port trying not to disturb
2775 * any possible real use of the port...
2776 *
2777 * The console_lock must be held when we get here.
2778 */
2779static void
2780serial8250_console_write(struct console *co, const char *s, unsigned int count)
2781{
2782 struct uart_8250_port *up = &serial8250_ports[co->index];
dfe42443 2783 struct uart_port *port = &up->port;
d8a5a8d7 2784 unsigned long flags;
1da177e4 2785 unsigned int ier;
d8a5a8d7 2786 int locked = 1;
1da177e4 2787
78512ece
AM		 2788 touch_nmi_watchdog();
2789
68aa2c0d 2790 local_irq_save(flags);
dfe42443 2791 if (port->sysrq) {
86b21199 2792 /* serial8250_handle_irq() already took the lock */
68aa2c0d
AM		 2793 locked = 0;
2794 } else if (oops_in_progress) {
dfe42443 2795 locked = spin_trylock(&port->lock);
d8a5a8d7 2796 } else
dfe42443 2797 spin_lock(&port->lock);
d8a5a8d7 2798
1da177e4 2799 /*
dc7bf130 2800 * First save the IER then disable the interrupts
1da177e4 2801 */
4fd996a1 2802 ier = serial_port_in(port, UART_IER);
1da177e4
LT		 2803
2804 if (up->capabilities & UART_CAP_UUE)
4fd996a1 2805 serial_port_out(port, UART_IER, UART_IER_UUE);
1da177e4 2806 else
4fd996a1 2807 serial_port_out(port, UART_IER, 0);
1da177e4 2808
dfe42443 2809 uart_console_write(port, s, count, serial8250_console_putchar);
1da177e4
LT		 2810
2811 /*
2812 * Finally, wait for transmitter to become empty
2813 * and restore the IER
2814 */
f91a3715 2815 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 2816 serial_port_out(port, UART_IER, ier);
d8a5a8d7 2817
ad4c2aa6
CM		 2818 /*
2819 * The receive handling will happen properly because the
2820 * receive ready bit will still be set; it is not cleared
2821 * on read. However, modem control will not, we must
2822 * call it if we have saved something in the saved flags
2823 * while processing with interrupts off.
2824 */
2825 if (up->msr_saved_flags)
3986fb2b 2826 serial8250_modem_status(up);
ad4c2aa6 2827
d8a5a8d7 2828 if (locked)
dfe42443 2829 spin_unlock(&port->lock);
68aa2c0d 2830 local_irq_restore(flags);
1da177e4
LT		 2831}
2832
118c0ace 2833static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2834{
2835 struct uart_port *port;
2836 int baud = 9600;
2837 int bits = 8;
2838 int parity = 'n';
2839 int flow = 'n';
2840
2841 /*
2842 * Check whether an invalid uart number has been specified, and
2843 * if so, search for the first available port that does have
2844 * console support.
2845 */
a61c2d78 2846 if (co->index >= nr_uarts)
1da177e4
LT		 2847 co->index = 0;
2848 port = &serial8250_ports[co->index].port;
2849 if (!port->iobase && !port->membase)
2850 return -ENODEV;
2851
2852 if (options)
2853 uart_parse_options(options, &baud, &parity, &bits, &flow);
2854
2855 return uart_set_options(port, co, baud, parity, bits, flow);
2856}
2857
b6b1d877 2858static int serial8250_console_early_setup(void)
18a8bd94
YL		 2859{
2860 return serial8250_find_port_for_earlycon();
2861}
2862
1da177e4
LT		 2863static struct console serial8250_console = {
2864 .name = "ttyS",
2865 .write = serial8250_console_write,
2866 .device = uart_console_device,
2867 .setup = serial8250_console_setup,
18a8bd94 2868 .early_setup = serial8250_console_early_setup,
a80c49db 2869 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2870 .index = -1,
2871 .data = &serial8250_reg,
2872};
2873
2874static int __init serial8250_console_init(void)
2875{
05d81d22
EB		 2876 if (nr_uarts > UART_NR)
2877 nr_uarts = UART_NR;
2878
1da177e4
LT		 2879 serial8250_isa_init_ports();
2880 register_console(&serial8250_console);
2881 return 0;
2882}
2883console_initcall(serial8250_console_init);
2884
18a8bd94 2885int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2886{
2887 int line;
2888 struct uart_port *port;
2889
a61c2d78 2890 for (line = 0; line < nr_uarts; line++) {
1da177e4 2891 port = &serial8250_ports[line].port;
50aec3b5 2892 if (uart_match_port(p, port))
1da177e4
LT		 2893 return line;
2894 }
2895 return -ENODEV;
2896}
2897
1da177e4
LT		 2898#define SERIAL8250_CONSOLE &serial8250_console
2899#else
2900#define SERIAL8250_CONSOLE NULL
2901#endif
2902
2903static struct uart_driver serial8250_reg = {
2904 .owner = THIS_MODULE,
2905 .driver_name = "serial",
1da177e4
LT		 2906 .dev_name = "ttyS",
2907 .major = TTY_MAJOR,
2908 .minor = 64,
1da177e4
LT		 2909 .cons = SERIAL8250_CONSOLE,
2910};
2911
d856c666
RK		 2912/*
2913 * early_serial_setup - early registration for 8250 ports
2914 *
2915 * Setup an 8250 port structure prior to console initialisation. Use
2916 * after console initialisation will cause undefined behaviour.
2917 */
1da177e4
LT		 2918int __init early_serial_setup(struct uart_port *port)
2919{
b430428a
DD		 2920 struct uart_port *p;
2921
1da177e4
LT		 2922 if (port->line >= ARRAY_SIZE(serial8250_ports))
2923 return -ENODEV;
2924
2925 serial8250_isa_init_ports();
b430428a
DD		 2926 p = &serial8250_ports[port->line].port;
2927 p->iobase = port->iobase;
2928 p->membase = port->membase;
2929 p->irq = port->irq;
1c2f0493 2930 p->irqflags = port->irqflags;
b430428a
DD		 2931 p->uartclk = port->uartclk;
2932 p->fifosize = port->fifosize;
2933 p->regshift = port->regshift;
2934 p->iotype = port->iotype;
2935 p->flags = port->flags;
2936 p->mapbase = port->mapbase;
2937 p->private_data = port->private_data;
125c97d8
HD		 2938 p->type = port->type;
2939 p->line = port->line;
7d6a07d1
DD		 2940
2941 set_io_from_upio(p);
2942 if (port->serial_in)
2943 p->serial_in = port->serial_in;
2944 if (port->serial_out)
2945 p->serial_out = port->serial_out;
583d28e9
JI		 2946 if (port->handle_irq)
2947 p->handle_irq = port->handle_irq;
2948 else
2949 p->handle_irq = serial8250_default_handle_irq;
7d6a07d1 2950
1da177e4
LT		 2951 return 0;
2952}
2953
2954/**
2955 * serial8250_suspend_port - suspend one serial port
2956 * @line: serial line number
1da177e4
LT		 2957 *
2958 * Suspend one serial port.
2959 */
2960void serial8250_suspend_port(int line)
2961{
2962 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2963}
2964
2965/**
2966 * serial8250_resume_port - resume one serial port
2967 * @line: serial line number
1da177e4
LT		 2968 *
2969 * Resume one serial port.
2970 */
2971void serial8250_resume_port(int line)
2972{
b5b82df6 2973 struct uart_8250_port *up = &serial8250_ports[line];
dfe42443 2974 struct uart_port *port = &up->port;
b5b82df6
DW		 2975
2976 if (up->capabilities & UART_NATSEMI) {
b5b82df6 2977 /* Ensure it's still in high speed mode */
4fd996a1 2978 serial_port_out(port, UART_LCR, 0xE0);
b5b82df6 2979
0d0389e5 2980 ns16550a_goto_highspeed(up);
b5b82df6 2981
4fd996a1 2982 serial_port_out(port, UART_LCR, 0);
dfe42443 2983 port->uartclk = 921600*16;
b5b82df6 2984 }
dfe42443 2985 uart_resume_port(&serial8250_reg, port);
1da177e4
LT		 2986}
2987
2988/*
2989 * Register a set of serial devices attached to a platform device. The
2990 * list is terminated with a zero flags entry, which means we expect
2991 * all entries to have at least UPF_BOOT_AUTOCONF set.
2992 */
3ae5eaec 2993static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2994{
3ae5eaec 2995 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2996 struct uart_port port;
4c0ebb80 2997 int ret, i, irqflag = 0;
1da177e4
LT		 2998
2999 memset(&port, 0, sizeof(struct uart_port));
3000
4c0ebb80
AGR		 3001 if (share_irqs)
3002 irqflag = IRQF_SHARED;
3003
ec9f47cd 3004 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 3005 port.iobase = p->iobase;
3006 port.membase = p->membase;
3007 port.irq = p->irq;
1c2f0493 3008 port.irqflags = p->irqflags;
74a19741
WN		 3009 port.uartclk = p->uartclk;
3010 port.regshift = p->regshift;
3011 port.iotype = p->iotype;
3012 port.flags = p->flags;
3013 port.mapbase = p->mapbase;
3014 port.hub6 = p->hub6;
3015 port.private_data = p->private_data;
8e23fcc8 3016 port.type = p->type;
7d6a07d1
DD		 3017 port.serial_in = p->serial_in;
3018 port.serial_out = p->serial_out;
583d28e9 3019 port.handle_irq = p->handle_irq;
bf03f65b 3020 port.handle_break = p->handle_break;
235dae5d 3021 port.set_termios = p->set_termios;
c161afe9 3022 port.pm = p->pm;
74a19741 3023 port.dev = &dev->dev;
4c0ebb80 3024 port.irqflags |= irqflag;
ec9f47cd
RK		 3025 ret = serial8250_register_port(&port);
3026 if (ret < 0) {
3ae5eaec 3027 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 3028 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3029 p->iobase, (unsigned long long)p->mapbase,
3030 p->irq, ret);
ec9f47cd 3031 }
1da177e4
LT		 3032 }
3033 return 0;
3034}
3035
3036/*
3037 * Remove serial ports registered against a platform device.
3038 */
3ae5eaec 3039static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 3040{
3041 int i;
3042
a61c2d78 3043 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 3044 struct uart_8250_port *up = &serial8250_ports[i];
3045
3ae5eaec 3046 if (up->port.dev == &dev->dev)
1da177e4
LT		 3047 serial8250_unregister_port(i);
3048 }
3049 return 0;
3050}
3051
3ae5eaec 3052static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 3053{
3054 int i;
3055
1da177e4
LT		 3056 for (i = 0; i < UART_NR; i++) {
3057 struct uart_8250_port *up = &serial8250_ports[i];
3058
3ae5eaec 3059 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3060 uart_suspend_port(&serial8250_reg, &up->port);
3061 }
3062
3063 return 0;
3064}
3065
3ae5eaec 3066static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3067{
3068 int i;
3069
1da177e4
LT		 3070 for (i = 0; i < UART_NR; i++) {
3071 struct uart_8250_port *up = &serial8250_ports[i];
3072
3ae5eaec 3073 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3074 serial8250_resume_port(i);
1da177e4
LT		 3075 }
3076
3077 return 0;
3078}
3079
3ae5eaec 3080static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 3081 .probe = serial8250_probe,
3082 .remove = __devexit_p(serial8250_remove),
3083 .suspend = serial8250_suspend,
3084 .resume = serial8250_resume,
3ae5eaec
RK		 3085 .driver = {
3086 .name = "serial8250",
7493a314 3087 .owner = THIS_MODULE,
3ae5eaec 3088 },
1da177e4
LT		 3089};
3090
3091/*
3092 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3093 * in the table in include/asm/serial.h
3094 */
3095static struct platform_device *serial8250_isa_devs;
3096
3097/*
3098 * serial8250_register_port and serial8250_unregister_port allows for
3099 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3100 * modems and PCI multiport cards.
3101 */
f392ecfa 3102static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3103
3104static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3105{
3106 int i;
3107
3108 /*
3109 * First, find a port entry which matches.
3110 */
a61c2d78 3111 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3112 if (uart_match_port(&serial8250_ports[i].port, port))
3113 return &serial8250_ports[i];
3114
3115 /*
3116 * We didn't find a matching entry, so look for the first
3117 * free entry. We look for one which hasn't been previously
3118 * used (indicated by zero iobase).
3119 */
a61c2d78 3120 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3121 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3122 serial8250_ports[i].port.iobase == 0)
3123 return &serial8250_ports[i];
3124
3125 /*
3126 * That also failed. Last resort is to find any entry which
3127 * doesn't have a real port associated with it.
3128 */
a61c2d78 3129 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3130 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3131 return &serial8250_ports[i];
3132
3133 return NULL;
3134}
3135
3136/**
3137 * serial8250_register_port - register a serial port
3138 * @port: serial port template
3139 *
3140 * Configure the serial port specified by the request. If the
3141 * port exists and is in use, it is hung up and unregistered
3142 * first.
3143 *
3144 * The port is then probed and if necessary the IRQ is autodetected
3145 * If this fails an error is returned.
3146 *
3147 * On success the port is ready to use and the line number is returned.
3148 */
3149int serial8250_register_port(struct uart_port *port)
3150{
3151 struct uart_8250_port *uart;
3152 int ret = -ENOSPC;
3153
3154 if (port->uartclk == 0)
3155 return -EINVAL;
3156
f392ecfa 3157 mutex_lock(&serial_mutex);
1da177e4
LT		 3158
3159 uart = serial8250_find_match_or_unused(port);
3160 if (uart) {
3161 uart_remove_one_port(&serial8250_reg, &uart->port);
3162
74a19741
WN		 3163 uart->port.iobase = port->iobase;
3164 uart->port.membase = port->membase;
3165 uart->port.irq = port->irq;
1c2f0493 3166 uart->port.irqflags = port->irqflags;
74a19741
WN		 3167 uart->port.uartclk = port->uartclk;
3168 uart->port.fifosize = port->fifosize;
3169 uart->port.regshift = port->regshift;
3170 uart->port.iotype = port->iotype;
3171 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3172 uart->port.mapbase = port->mapbase;
3173 uart->port.private_data = port->private_data;
1da177e4
LT		 3174 if (port->dev)
3175 uart->port.dev = port->dev;
8e23fcc8 3176
b5d228cc
SL		 3177 if (port->flags & UPF_FIXED_TYPE)
3178 serial8250_init_fixed_type_port(uart, port->type);
8e23fcc8 3179
7d6a07d1
DD		 3180 set_io_from_upio(&uart->port);
3181 /* Possibly override default I/O functions. */
3182 if (port->serial_in)
3183 uart->port.serial_in = port->serial_in;
3184 if (port->serial_out)
3185 uart->port.serial_out = port->serial_out;
583d28e9
JI		 3186 if (port->handle_irq)
3187 uart->port.handle_irq = port->handle_irq;
235dae5d
PL		 3188 /* Possibly override set_termios call */
3189 if (port->set_termios)
3190 uart->port.set_termios = port->set_termios;
c161afe9
ML		 3191 if (port->pm)
3192 uart->port.pm = port->pm;
bf03f65b
DW		 3193 if (port->handle_break)
3194 uart->port.handle_break = port->handle_break;
1da177e4 3195
af7f3743
AC		 3196 if (serial8250_isa_config != NULL)
3197 serial8250_isa_config(0, &uart->port,
3198 &uart->capabilities);
3199
1da177e4
LT		 3200 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3201 if (ret == 0)
3202 ret = uart->port.line;
3203 }
f392ecfa 3204 mutex_unlock(&serial_mutex);
1da177e4
LT		 3205
3206 return ret;
3207}
3208EXPORT_SYMBOL(serial8250_register_port);
3209
3210/**
3211 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3212 * @line: serial line number
3213 *
3214 * Remove one serial port. This may not be called from interrupt
3215 * context. We hand the port back to the our control.
3216 */
3217void serial8250_unregister_port(int line)
3218{
3219 struct uart_8250_port *uart = &serial8250_ports[line];
3220
f392ecfa 3221 mutex_lock(&serial_mutex);
1da177e4
LT		 3222 uart_remove_one_port(&serial8250_reg, &uart->port);
3223 if (serial8250_isa_devs) {
3224 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3225 uart->port.type = PORT_UNKNOWN;
3226 uart->port.dev = &serial8250_isa_devs->dev;
cb01ece3 3227 uart->capabilities = uart_config[uart->port.type].flags;
1da177e4
LT		 3228 uart_add_one_port(&serial8250_reg, &uart->port);
3229 } else {
3230 uart->port.dev = NULL;
3231 }
f392ecfa 3232 mutex_unlock(&serial_mutex);
1da177e4
LT		 3233}
3234EXPORT_SYMBOL(serial8250_unregister_port);
3235
3236static int __init serial8250_init(void)
3237{
25db8ad5 3238 int ret;
1da177e4 3239
a61c2d78
DJ		 3240 if (nr_uarts > UART_NR)
3241 nr_uarts = UART_NR;
3242
f1fb9bb8 3243 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3244 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3245 share_irqs ? "en" : "dis");
3246
b70ac771
DM		 3247#ifdef CONFIG_SPARC
3248 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3249#else
3250 serial8250_reg.nr = UART_NR;
1da177e4 3251 ret = uart_register_driver(&serial8250_reg);
b70ac771 3252#endif
1da177e4
LT		 3253 if (ret)
3254 goto out;
3255
7493a314
DT		 3256 serial8250_isa_devs = platform_device_alloc("serial8250",
3257 PLAT8250_DEV_LEGACY);
3258 if (!serial8250_isa_devs) {
3259 ret = -ENOMEM;
bc965a7f 3260 goto unreg_uart_drv;
1da177e4
LT		 3261 }
3262
7493a314
DT		 3263 ret = platform_device_add(serial8250_isa_devs);
3264 if (ret)
3265 goto put_dev;
3266
1da177e4
LT		 3267 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3268
bc965a7f
RK		 3269 ret = platform_driver_register(&serial8250_isa_driver);
3270 if (ret == 0)
3271 goto out;
1da177e4 3272
bc965a7f 3273 platform_device_del(serial8250_isa_devs);
25db8ad5 3274put_dev:
7493a314 3275 platform_device_put(serial8250_isa_devs);
25db8ad5 3276unreg_uart_drv:
b70ac771
DM		 3277#ifdef CONFIG_SPARC
3278 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3279#else
1da177e4 3280 uart_unregister_driver(&serial8250_reg);
b70ac771 3281#endif
25db8ad5 3282out:
1da177e4
LT		 3283 return ret;
3284}
3285
3286static void __exit serial8250_exit(void)
3287{
3288 struct platform_device *isa_dev = serial8250_isa_devs;
3289
3290 /*
3291 * This tells serial8250_unregister_port() not to re-register
3292 * the ports (thereby making serial8250_isa_driver permanently
3293 * in use.)
3294 */
3295 serial8250_isa_devs = NULL;
3296
3ae5eaec 3297 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3298 platform_device_unregister(isa_dev);
3299
b70ac771
DM		 3300#ifdef CONFIG_SPARC
3301 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3302#else
1da177e4 3303 uart_unregister_driver(&serial8250_reg);
b70ac771 3304#endif
1da177e4
LT		 3305}
3306
3307module_init(serial8250_init);
3308module_exit(serial8250_exit);
3309
3310EXPORT_SYMBOL(serial8250_suspend_port);
3311EXPORT_SYMBOL(serial8250_resume_port);
3312
3313MODULE_LICENSE("GPL");
d87a6d95 3314MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3315
3316module_param(share_irqs, uint, 0644);
3317MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3318 " (unsafe)");
3319
a61c2d78
DJ		 3320module_param(nr_uarts, uint, 0644);
3321MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3322
d41a4b51
CE		 3323module_param(skip_txen_test, uint, 0644);
3324MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3325
1da177e4
LT		 3326#ifdef CONFIG_SERIAL_8250_RSA
3327module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3328MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3329#endif
3330MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux kernel - Deliverables
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