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serial: 8250: do not copy port.fifosize member twice
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250_core.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
1da177e4
LT		 13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
1da177e4
LT		 18
19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
1da177e4 29#include <linux/delay.h>
d052d1be 30#include <linux/platform_device.h>
1da177e4 31#include <linux/tty.h>
cd3ecad1 32#include <linux/ratelimit.h>
1da177e4 33#include <linux/tty_flip.h>
1da177e4
LT		 34#include <linux/serial.h>
35#include <linux/serial_8250.h>
78512ece 36#include <linux/nmi.h>
f392ecfa 37#include <linux/mutex.h>
5a0e3ad6 38#include <linux/slab.h>
0b4af1d9 39#include <linux/uaccess.h>
d74d5d1b 40#include <linux/pm_runtime.h>
6816383a
PG		 41#ifdef CONFIG_SPARC
42#include <linux/sunserialcore.h>
43#endif
1da177e4
LT		 44
45#include <asm/io.h>
46#include <asm/irq.h>
47
48#include "8250.h"
49
50/*
51 * Configuration:
40663cc7 52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 53 * is unsafe when used on edge-triggered interrupts.
54 */
408b664a 55static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 56
a61c2d78
DJ		 57static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
8440838b
DM		 59static struct uart_driver serial8250_reg;
60
61static int serial_index(struct uart_port *port)
62{
51c39814 63 return port->minor - 64;
8440838b
DM		 64}
65
d41a4b51
CE		 66static unsigned int skip_txen_test; /* force skip of txen test at init time */
67
1da177e4
LT		 68/*
69 * Debugging.
70 */
71#if 0
72#define DEBUG_AUTOCONF(fmt...) printk(fmt)
73#else
74#define DEBUG_AUTOCONF(fmt...) do { } while (0)
75#endif
76
77#if 0
78#define DEBUG_INTR(fmt...) printk(fmt)
79#else
80#define DEBUG_INTR(fmt...) do { } while (0)
81#endif
82
e7328ae1 83#define PASS_LIMIT 512
1da177e4 84
bca47613
DH		 85#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
86
87
a4ed1e41 88#include <asm/serial.h>
1da177e4
LT		 89/*
90 * SERIAL_PORT_DFNS tells us about built-in ports that have no
91 * standard enumeration mechanism. Platforms that can find all
92 * serial ports via mechanisms like ACPI or PCI need not supply it.
93 */
94#ifndef SERIAL_PORT_DFNS
95#define SERIAL_PORT_DFNS
96#endif
97
cb3592be 98static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 99 SERIAL_PORT_DFNS /* defined in asm/serial.h */
100};
101
026d02a2 102#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 103
104#ifdef CONFIG_SERIAL_8250_RSA
105
106#define PORT_RSA_MAX 4
107static unsigned long probe_rsa[PORT_RSA_MAX];
108static unsigned int probe_rsa_count;
109#endif /* CONFIG_SERIAL_8250_RSA */
110
1da177e4 111struct irq_info {
25db8ad5
AC		 112 struct hlist_node node;
113 int irq;
114 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 115 struct list_head *head;
116};
117
25db8ad5
AC		 118#define NR_IRQ_HASH 32 /* Can be adjusted later */
119static struct hlist_head irq_lists[NR_IRQ_HASH];
120static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 121
122/*
123 * Here we define the default xmit fifo size used for each type of UART.
124 */
125static const struct serial8250_config uart_config[] = {
126 [PORT_UNKNOWN] = {
127 .name = "unknown",
128 .fifo_size = 1,
129 .tx_loadsz = 1,
130 },
131 [PORT_8250] = {
132 .name = "8250",
133 .fifo_size = 1,
134 .tx_loadsz = 1,
135 },
136 [PORT_16450] = {
137 .name = "16450",
138 .fifo_size = 1,
139 .tx_loadsz = 1,
140 },
141 [PORT_16550] = {
142 .name = "16550",
143 .fifo_size = 1,
144 .tx_loadsz = 1,
145 },
146 [PORT_16550A] = {
147 .name = "16550A",
148 .fifo_size = 16,
149 .tx_loadsz = 16,
150 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
aef9a7bd 151 .rxtrig_bytes = {1, 4, 8, 14},
1da177e4
LT		 152 .flags = UART_CAP_FIFO,
153 },
154 [PORT_CIRRUS] = {
155 .name = "Cirrus",
156 .fifo_size = 1,
157 .tx_loadsz = 1,
158 },
159 [PORT_16650] = {
160 .name = "ST16650",
161 .fifo_size = 1,
162 .tx_loadsz = 1,
163 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
164 },
165 [PORT_16650V2] = {
166 .name = "ST16650V2",
167 .fifo_size = 32,
168 .tx_loadsz = 16,
169 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
170 UART_FCR_T_TRIG_00,
aef9a7bd 171 .rxtrig_bytes = {8, 16, 24, 28},
1da177e4
LT		 172 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
173 },
174 [PORT_16750] = {
175 .name = "TI16750",
176 .fifo_size = 64,
177 .tx_loadsz = 64,
178 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
179 UART_FCR7_64BYTE,
aef9a7bd 180 .rxtrig_bytes = {1, 16, 32, 56},
1da177e4
LT		 181 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
182 },
183 [PORT_STARTECH] = {
184 .name = "Startech",
185 .fifo_size = 1,
186 .tx_loadsz = 1,
187 },
188 [PORT_16C950] = {
189 .name = "16C950/954",
190 .fifo_size = 128,
191 .tx_loadsz = 128,
192 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
d0694e2a
PM		 193 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
194 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
1da177e4
LT		 195 },
196 [PORT_16654] = {
197 .name = "ST16654",
198 .fifo_size = 64,
199 .tx_loadsz = 32,
200 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
201 UART_FCR_T_TRIG_10,
aef9a7bd 202 .rxtrig_bytes = {8, 16, 56, 60},
1da177e4
LT		 203 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
204 },
205 [PORT_16850] = {
206 .name = "XR16850",
207 .fifo_size = 128,
208 .tx_loadsz = 128,
209 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
210 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
211 },
212 [PORT_RSA] = {
213 .name = "RSA",
214 .fifo_size = 2048,
215 .tx_loadsz = 2048,
216 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
217 .flags = UART_CAP_FIFO,
218 },
219 [PORT_NS16550A] = {
220 .name = "NS16550A",
221 .fifo_size = 16,
222 .tx_loadsz = 16,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
224 .flags = UART_CAP_FIFO | UART_NATSEMI,
225 },
226 [PORT_XSCALE] = {
227 .name = "XScale",
228 .fifo_size = 32,
229 .tx_loadsz = 32,
230 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
4539c24f 231 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
1da177e4 232 },
6b06f191
DD		 233 [PORT_OCTEON] = {
234 .name = "OCTEON",
235 .fifo_size = 64,
236 .tx_loadsz = 64,
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 238 .flags = UART_CAP_FIFO,
239 },
08e0992f
FF		 240 [PORT_AR7] = {
241 .name = "AR7",
242 .fifo_size = 16,
243 .tx_loadsz = 16,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
245 .flags = UART_CAP_FIFO | UART_CAP_AFE,
246 },
235dae5d
PL		 247 [PORT_U6_16550A] = {
248 .name = "U6_16550A",
249 .fifo_size = 64,
250 .tx_loadsz = 64,
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_AFE,
253 },
4539c24f
SW		 254 [PORT_TEGRA] = {
255 .name = "Tegra",
256 .fifo_size = 32,
257 .tx_loadsz = 8,
258 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
259 UART_FCR_T_TRIG_01,
aef9a7bd 260 .rxtrig_bytes = {1, 4, 8, 14},
4539c24f
SW		 261 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
262 },
06315348
SH		 263 [PORT_XR17D15X] = {
264 .name = "XR17D15X",
265 .fifo_size = 64,
266 .tx_loadsz = 64,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
81db0772
MS		 268 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
269 UART_CAP_SLEEP,
06315348 270 },
dc96efb7
MS		 271 [PORT_XR17V35X] = {
272 .name = "XR17V35X",
273 .fifo_size = 256,
274 .tx_loadsz = 256,
275 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
276 UART_FCR_T_TRIG_11,
277 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
278 UART_CAP_SLEEP,
279 },
7a514596
RS		 280 [PORT_LPC3220] = {
281 .name = "LPC3220",
282 .fifo_size = 64,
283 .tx_loadsz = 32,
284 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
285 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
286 .flags = UART_CAP_FIFO,
287 },
ebebd49a
SH		 288 [PORT_BRCM_TRUMANAGE] = {
289 .name = "TruManage",
290 .fifo_size = 1,
291 .tx_loadsz = 1024,
292 .flags = UART_CAP_HFIFO,
293 },
65ecc9c0
SY		 294 [PORT_8250_CIR] = {
295 .name = "CIR port"
e06c93ca
LFT		 296 },
297 [PORT_ALTR_16550_F32] = {
298 .name = "Altera 16550 FIFO32",
299 .fifo_size = 32,
300 .tx_loadsz = 32,
301 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
302 .flags = UART_CAP_FIFO | UART_CAP_AFE,
303 },
304 [PORT_ALTR_16550_F64] = {
305 .name = "Altera 16550 FIFO64",
306 .fifo_size = 64,
307 .tx_loadsz = 64,
308 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
309 .flags = UART_CAP_FIFO | UART_CAP_AFE,
310 },
311 [PORT_ALTR_16550_F128] = {
312 .name = "Altera 16550 FIFO128",
313 .fifo_size = 128,
314 .tx_loadsz = 128,
315 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
316 .flags = UART_CAP_FIFO | UART_CAP_AFE,
317 },
fddceb8b
VR		 318/* tx_loadsz is set to 63-bytes instead of 64-bytes to implement
319workaround of errata A-008006 which states that tx_loadsz should be
320configured less than Maximum supported fifo bytes */
321 [PORT_16550A_FSL64] = {
322 .name = "16550A_FSL64",
323 .fifo_size = 64,
324 .tx_loadsz = 63,
325 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
326 UART_FCR7_64BYTE,
327 .flags = UART_CAP_FIFO,
328 },
1da177e4
LT		 329};
330
cc419fa0 331/* Uart divisor latch read */
e8155629 332static int default_serial_dl_read(struct uart_8250_port *up)
cc419fa0
MD		 333{
334 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
335}
336
337/* Uart divisor latch write */
e8155629 338static void default_serial_dl_write(struct uart_8250_port *up, int value)
cc419fa0
MD		 339{
340 serial_out(up, UART_DLL, value & 0xff);
341 serial_out(up, UART_DLM, value >> 8 & 0xff);
342}
343
c420811f 344#if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
21c614a7 345
c420811f 346/* Au1x00/RT288x UART hardware has a weird register layout */
509cb7dc
PH		 347static const s8 au_io_in_map[8] = {
348 0, /* UART_RX */
349 2, /* UART_IER */
350 3, /* UART_IIR */
351 5, /* UART_LCR */
352 6, /* UART_MCR */
353 7, /* UART_LSR */
354 8, /* UART_MSR */
355 -1, /* UART_SCR (unmapped) */
21c614a7
PA		 356};
357
509cb7dc
PH		 358static const s8 au_io_out_map[8] = {
359 1, /* UART_TX */
360 2, /* UART_IER */
361 4, /* UART_FCR */
362 5, /* UART_LCR */
363 6, /* UART_MCR */
364 -1, /* UART_LSR (unmapped) */
365 -1, /* UART_MSR (unmapped) */
366 -1, /* UART_SCR (unmapped) */
21c614a7
PA		 367};
368
6b416031 369static unsigned int au_serial_in(struct uart_port *p, int offset)
21c614a7 370{
509cb7dc
PH		 371 if (offset >= ARRAY_SIZE(au_io_in_map))
372 return UINT_MAX;
373 offset = au_io_in_map[offset];
374 if (offset < 0)
375 return UINT_MAX;
376 return __raw_readl(p->membase + (offset << p->regshift));
21c614a7
PA		 377}
378
6b416031 379static void au_serial_out(struct uart_port *p, int offset, int value)
21c614a7 380{
509cb7dc
PH		 381 if (offset >= ARRAY_SIZE(au_io_out_map))
382 return;
383 offset = au_io_out_map[offset];
384 if (offset < 0)
385 return;
386 __raw_writel(value, p->membase + (offset << p->regshift));
6b416031
MD		 387}
388
389/* Au1x00 haven't got a standard divisor latch */
390static int au_serial_dl_read(struct uart_8250_port *up)
391{
392 return __raw_readl(up->port.membase + 0x28);
393}
394
395static void au_serial_dl_write(struct uart_8250_port *up, int value)
396{
397 __raw_writel(value, up->port.membase + 0x28);
21c614a7
PA		 398}
399
6b416031
MD		 400#endif
401
7d6a07d1 402static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 403{
e8155629 404 offset = offset << p->regshift;
7d6a07d1
DD		 405 outb(p->hub6 - 1 + offset, p->iobase);
406 return inb(p->iobase + 1);
407}
1da177e4 408
7d6a07d1
DD		 409static void hub6_serial_out(struct uart_port *p, int offset, int value)
410{
e8155629 411 offset = offset << p->regshift;
7d6a07d1
DD		 412 outb(p->hub6 - 1 + offset, p->iobase);
413 outb(value, p->iobase + 1);
414}
1da177e4 415
7d6a07d1
DD		 416static unsigned int mem_serial_in(struct uart_port *p, int offset)
417{
e8155629 418 offset = offset << p->regshift;
7d6a07d1
DD		 419 return readb(p->membase + offset);
420}
1da177e4 421
7d6a07d1
DD		 422static void mem_serial_out(struct uart_port *p, int offset, int value)
423{
e8155629 424 offset = offset << p->regshift;
7d6a07d1
DD		 425 writeb(value, p->membase + offset);
426}
427
428static void mem32_serial_out(struct uart_port *p, int offset, int value)
429{
e8155629 430 offset = offset << p->regshift;
7d6a07d1
DD		 431 writel(value, p->membase + offset);
432}
433
434static unsigned int mem32_serial_in(struct uart_port *p, int offset)
435{
e8155629 436 offset = offset << p->regshift;
7d6a07d1
DD		 437 return readl(p->membase + offset);
438}
1da177e4 439
c627f2ce
KC		 440static void mem32be_serial_out(struct uart_port *p, int offset, int value)
441{
442 offset = offset << p->regshift;
443 iowrite32be(value, p->membase + offset);
444}
445
446static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
447{
448 offset = offset << p->regshift;
449 return ioread32be(p->membase + offset);
450}
451
7d6a07d1
DD		 452static unsigned int io_serial_in(struct uart_port *p, int offset)
453{
e8155629 454 offset = offset << p->regshift;
7d6a07d1
DD		 455 return inb(p->iobase + offset);
456}
457
458static void io_serial_out(struct uart_port *p, int offset, int value)
459{
e8155629 460 offset = offset << p->regshift;
7d6a07d1
DD		 461 outb(value, p->iobase + offset);
462}
463
583d28e9 464static int serial8250_default_handle_irq(struct uart_port *port);
dc96efb7 465static int exar_handle_irq(struct uart_port *port);
583d28e9 466
7d6a07d1
DD		 467static void set_io_from_upio(struct uart_port *p)
468{
b1261c86 469 struct uart_8250_port *up = up_to_u8250p(p);
cc419fa0 470
e8155629
MD		 471 up->dl_read = default_serial_dl_read;
472 up->dl_write = default_serial_dl_write;
cc419fa0 473
7d6a07d1 474 switch (p->iotype) {
1da177e4 475 case UPIO_HUB6:
7d6a07d1
DD		 476 p->serial_in = hub6_serial_in;
477 p->serial_out = hub6_serial_out;
1da177e4
LT		 478 break;
479
480 case UPIO_MEM:
7d6a07d1
DD		 481 p->serial_in = mem_serial_in;
482 p->serial_out = mem_serial_out;
1da177e4
LT		 483 break;
484
485 case UPIO_MEM32:
7d6a07d1
DD		 486 p->serial_in = mem32_serial_in;
487 p->serial_out = mem32_serial_out;
1da177e4
LT		 488 break;
489
c627f2ce
KC		 490 case UPIO_MEM32BE:
491 p->serial_in = mem32be_serial_in;
492 p->serial_out = mem32be_serial_out;
493 break;
494
c420811f 495#if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
21c614a7 496 case UPIO_AU:
7d6a07d1
DD		 497 p->serial_in = au_serial_in;
498 p->serial_out = au_serial_out;
6b416031
MD		 499 up->dl_read = au_serial_dl_read;
500 up->dl_write = au_serial_dl_write;
21c614a7 501 break;
6b416031 502#endif
12bf3f24 503
1da177e4 504 default:
7d6a07d1
DD		 505 p->serial_in = io_serial_in;
506 p->serial_out = io_serial_out;
507 break;
1da177e4 508 }
b8e7e40a
AC		 509 /* Remember loaded iotype */
510 up->cur_iotype = p->iotype;
583d28e9 511 p->handle_irq = serial8250_default_handle_irq;
1da177e4
LT		 512}
513
40b36daa 514static void
55e4016d 515serial_port_out_sync(struct uart_port *p, int offset, int value)
40b36daa 516{
7d6a07d1 517 switch (p->iotype) {
40b36daa
AW		 518 case UPIO_MEM:
519 case UPIO_MEM32:
c627f2ce 520 case UPIO_MEM32BE:
40b36daa 521 case UPIO_AU:
7d6a07d1
DD		 522 p->serial_out(p, offset, value);
523 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 524 break;
525 default:
7d6a07d1 526 p->serial_out(p, offset, value);
40b36daa
AW		 527 }
528}
529
1da177e4
LT		 530/*
531 * For the 16C950
532 */
533static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
534{
535 serial_out(up, UART_SCR, offset);
536 serial_out(up, UART_ICR, value);
537}
538
539static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
540{
541 unsigned int value;
542
543 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
544 serial_out(up, UART_SCR, offset);
545 value = serial_in(up, UART_ICR);
546 serial_icr_write(up, UART_ACR, up->acr);
547
548 return value;
549}
550
551/*
552 * FIFO support.
553 */
b5d674ab 554static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 555{
556 if (p->capabilities & UART_CAP_FIFO) {
0acf519f
PG		 557 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
558 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
1da177e4 559 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0acf519f 560 serial_out(p, UART_FCR, 0);
1da177e4
LT		 561 }
562}
563
0ad372b9
SM		 564void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
565{
0ad372b9 566 serial8250_clear_fifos(p);
aef9a7bd 567 serial_out(p, UART_FCR, p->fcr);
0ad372b9
SM		 568}
569EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
570
77285243 571void serial8250_rpm_get(struct uart_8250_port *p)
d74d5d1b
SAS		 572{
573 if (!(p->capabilities & UART_CAP_RPM))
574 return;
575 pm_runtime_get_sync(p->port.dev);
576}
77285243 577EXPORT_SYMBOL_GPL(serial8250_rpm_get);
d74d5d1b 578
77285243 579void serial8250_rpm_put(struct uart_8250_port *p)
d74d5d1b
SAS		 580{
581 if (!(p->capabilities & UART_CAP_RPM))
582 return;
583 pm_runtime_mark_last_busy(p->port.dev);
584 pm_runtime_put_autosuspend(p->port.dev);
585}
77285243 586EXPORT_SYMBOL_GPL(serial8250_rpm_put);
d74d5d1b
SAS		 587
588/*
6a529aba 589 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
d74d5d1b
SAS		 590 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
591 * empty and the HW can idle again.
592 */
593static void serial8250_rpm_get_tx(struct uart_8250_port *p)
594{
595 unsigned char rpm_active;
596
597 if (!(p->capabilities & UART_CAP_RPM))
598 return;
599
600 rpm_active = xchg(&p->rpm_tx_active, 1);
601 if (rpm_active)
602 return;
603 pm_runtime_get_sync(p->port.dev);
604}
605
606static void serial8250_rpm_put_tx(struct uart_8250_port *p)
607{
608 unsigned char rpm_active;
609
610 if (!(p->capabilities & UART_CAP_RPM))
611 return;
612
613 rpm_active = xchg(&p->rpm_tx_active, 0);
614 if (!rpm_active)
615 return;
616 pm_runtime_mark_last_busy(p->port.dev);
617 pm_runtime_put_autosuspend(p->port.dev);
618}
619
1da177e4
LT		 620/*
621 * IER sleep support. UARTs which have EFRs need the "extended
622 * capability" bit enabled. Note that on XR16C850s, we need to
623 * reset LCR to write to IER.
624 */
b5d674ab 625static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4 626{
edf4edac 627 unsigned char lcr = 0, efr = 0;
dc96efb7
MS		 628 /*
629 * Exar UARTs have a SLEEP register that enables or disables
630 * each UART to enter sleep mode separately. On the XR17V35x the
631 * register is accessible to each UART at the UART_EXAR_SLEEP
632 * offset but the UART channel may only write to the corresponding
633 * bit.
634 */
d74d5d1b 635 serial8250_rpm_get(p);
81db0772
MS		 636 if ((p->port.type == PORT_XR17V35X) ||
637 (p->port.type == PORT_XR17D15X)) {
b790f210 638 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0);
d74d5d1b 639 goto out;
dc96efb7
MS		 640 }
641
1da177e4
LT		 642 if (p->capabilities & UART_CAP_SLEEP) {
643 if (p->capabilities & UART_CAP_EFR) {
edf4edac
SS		 644 lcr = serial_in(p, UART_LCR);
645 efr = serial_in(p, UART_EFR);
0acf519f
PG		 646 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
647 serial_out(p, UART_EFR, UART_EFR_ECB);
648 serial_out(p, UART_LCR, 0);
1da177e4 649 }
0acf519f 650 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
1da177e4 651 if (p->capabilities & UART_CAP_EFR) {
0acf519f 652 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
edf4edac
SS		 653 serial_out(p, UART_EFR, efr);
654 serial_out(p, UART_LCR, lcr);
1da177e4
LT		 655 }
656 }
d74d5d1b
SAS		 657out:
658 serial8250_rpm_put(p);
1da177e4
LT		 659}
660
661#ifdef CONFIG_SERIAL_8250_RSA
662/*
663 * Attempts to turn on the RSA FIFO. Returns zero on failure.
664 * We set the port uart clock rate if we succeed.
665 */
666static int __enable_rsa(struct uart_8250_port *up)
667{
668 unsigned char mode;
669 int result;
670
0acf519f 671 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 672 result = mode & UART_RSA_MSR_FIFO;
673
674 if (!result) {
0acf519f
PG		 675 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
676 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 677 result = mode & UART_RSA_MSR_FIFO;
678 }
679
680 if (result)
681 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
682
683 return result;
684}
685
686static void enable_rsa(struct uart_8250_port *up)
687{
688 if (up->port.type == PORT_RSA) {
689 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
690 spin_lock_irq(&up->port.lock);
691 __enable_rsa(up);
692 spin_unlock_irq(&up->port.lock);
693 }
694 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
0acf519f 695 serial_out(up, UART_RSA_FRR, 0);
1da177e4
LT		 696 }
697}
698
699/*
700 * Attempts to turn off the RSA FIFO. Returns zero on failure.
701 * It is unknown why interrupts were disabled in here. However,
702 * the caller is expected to preserve this behaviour by grabbing
703 * the spinlock before calling this function.
704 */
705static void disable_rsa(struct uart_8250_port *up)
706{
707 unsigned char mode;
708 int result;
709
710 if (up->port.type == PORT_RSA &&
711 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
712 spin_lock_irq(&up->port.lock);
713
0acf519f 714 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 715 result = !(mode & UART_RSA_MSR_FIFO);
716
717 if (!result) {
0acf519f
PG		 718 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
719 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 720 result = !(mode & UART_RSA_MSR_FIFO);
721 }
722
723 if (result)
724 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
725 spin_unlock_irq(&up->port.lock);
726 }
727}
728#endif /* CONFIG_SERIAL_8250_RSA */
729
730/*
731 * This is a quickie test to see how big the FIFO is.
732 * It doesn't work at all the time, more's the pity.
733 */
734static int size_fifo(struct uart_8250_port *up)
735{
b32b19b8
JAH		 736 unsigned char old_fcr, old_mcr, old_lcr;
737 unsigned short old_dl;
1da177e4
LT		 738 int count;
739
0acf519f
PG		 740 old_lcr = serial_in(up, UART_LCR);
741 serial_out(up, UART_LCR, 0);
742 old_fcr = serial_in(up, UART_FCR);
743 old_mcr = serial_in(up, UART_MCR);
744 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1da177e4 745 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0acf519f
PG		 746 serial_out(up, UART_MCR, UART_MCR_LOOP);
747 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8
JAH		 748 old_dl = serial_dl_read(up);
749 serial_dl_write(up, 0x0001);
0acf519f 750 serial_out(up, UART_LCR, 0x03);
1da177e4 751 for (count = 0; count < 256; count++)
0acf519f 752 serial_out(up, UART_TX, count);
1da177e4 753 mdelay(20);/* FIXME - schedule_timeout */
0acf519f 754 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
1da177e4 755 (count < 256); count++)
0acf519f
PG		 756 serial_in(up, UART_RX);
757 serial_out(up, UART_FCR, old_fcr);
758 serial_out(up, UART_MCR, old_mcr);
759 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8 760 serial_dl_write(up, old_dl);
0acf519f 761 serial_out(up, UART_LCR, old_lcr);
1da177e4
LT		 762
763 return count;
764}
765
766/*
767 * Read UART ID using the divisor method - set DLL and DLM to zero
768 * and the revision will be in DLL and device type in DLM. We
769 * preserve the device state across this.
770 */
771static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
772{
773 unsigned char old_dll, old_dlm, old_lcr;
774 unsigned int id;
775
0acf519f
PG		 776 old_lcr = serial_in(p, UART_LCR);
777 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4 778
0acf519f
PG		 779 old_dll = serial_in(p, UART_DLL);
780 old_dlm = serial_in(p, UART_DLM);
1da177e4 781
0acf519f
PG		 782 serial_out(p, UART_DLL, 0);
783 serial_out(p, UART_DLM, 0);
1da177e4 784
0acf519f 785 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
1da177e4 786
0acf519f
PG		 787 serial_out(p, UART_DLL, old_dll);
788 serial_out(p, UART_DLM, old_dlm);
789 serial_out(p, UART_LCR, old_lcr);
1da177e4
LT		 790
791 return id;
792}
793
794/*
795 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
796 * When this function is called we know it is at least a StarTech
797 * 16650 V2, but it might be one of several StarTech UARTs, or one of
798 * its clones. (We treat the broken original StarTech 16650 V1 as a
799 * 16550, and why not? Startech doesn't seem to even acknowledge its
800 * existence.)
bd71c182 801 *
1da177e4
LT		 802 * What evil have men's minds wrought...
803 */
804static void autoconfig_has_efr(struct uart_8250_port *up)
805{
806 unsigned int id1, id2, id3, rev;
807
808 /*
809 * Everything with an EFR has SLEEP
810 */
811 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
812
813 /*
814 * First we check to see if it's an Oxford Semiconductor UART.
815 *
816 * If we have to do this here because some non-National
817 * Semiconductor clone chips lock up if you try writing to the
818 * LSR register (which serial_icr_read does)
819 */
820
821 /*
822 * Check for Oxford Semiconductor 16C950.
823 *
824 * EFR [4] must be set else this test fails.
825 *
826 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
827 * claims that it's needed for 952 dual UART's (which are not
828 * recommended for new designs).
829 */
830 up->acr = 0;
662b083a 831 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 832 serial_out(up, UART_EFR, UART_EFR_ECB);
833 serial_out(up, UART_LCR, 0x00);
834 id1 = serial_icr_read(up, UART_ID1);
835 id2 = serial_icr_read(up, UART_ID2);
836 id3 = serial_icr_read(up, UART_ID3);
837 rev = serial_icr_read(up, UART_REV);
838
839 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
840
841 if (id1 == 0x16 && id2 == 0xC9 &&
842 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
843 up->port.type = PORT_16C950;
4ba5e35d
RK		 844
845 /*
846 * Enable work around for the Oxford Semiconductor 952 rev B
847 * chip which causes it to seriously miscalculate baud rates
848 * when DLL is 0.
849 */
850 if (id3 == 0x52 && rev == 0x01)
851 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 852 return;
853 }
bd71c182 854
1da177e4
LT		 855 /*
856 * We check for a XR16C850 by setting DLL and DLM to 0, and then
857 * reading back DLL and DLM. The chip type depends on the DLM
858 * value read back:
859 * 0x10 - XR16C850 and the DLL contains the chip revision.
860 * 0x12 - XR16C2850.
861 * 0x14 - XR16C854.
862 */
863 id1 = autoconfig_read_divisor_id(up);
864 DEBUG_AUTOCONF("850id=%04x ", id1);
865
866 id2 = id1 >> 8;
867 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 868 up->port.type = PORT_16850;
869 return;
870 }
871
872 /*
873 * It wasn't an XR16C850.
874 *
875 * We distinguish between the '654 and the '650 by counting
876 * how many bytes are in the FIFO. I'm using this for now,
877 * since that's the technique that was sent to me in the
878 * serial driver update, but I'm not convinced this works.
879 * I've had problems doing this in the past. -TYT
880 */
881 if (size_fifo(up) == 64)
882 up->port.type = PORT_16654;
883 else
884 up->port.type = PORT_16650V2;
885}
886
887/*
888 * We detected a chip without a FIFO. Only two fall into
889 * this category - the original 8250 and the 16450. The
890 * 16450 has a scratch register (accessible with LCR=0)
891 */
892static void autoconfig_8250(struct uart_8250_port *up)
893{
894 unsigned char scratch, status1, status2;
895
896 up->port.type = PORT_8250;
897
898 scratch = serial_in(up, UART_SCR);
0acf519f 899 serial_out(up, UART_SCR, 0xa5);
1da177e4 900 status1 = serial_in(up, UART_SCR);
0acf519f 901 serial_out(up, UART_SCR, 0x5a);
1da177e4 902 status2 = serial_in(up, UART_SCR);
0acf519f 903 serial_out(up, UART_SCR, scratch);
1da177e4
LT		 904
905 if (status1 == 0xa5 && status2 == 0x5a)
906 up->port.type = PORT_16450;
907}
908
909static int broken_efr(struct uart_8250_port *up)
910{
911 /*
912 * Exar ST16C2550 "A2" devices incorrectly detect as
913 * having an EFR, and report an ID of 0x0201. See
6ae4a16c 914 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1da177e4
LT		 915 */
916 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
917 return 1;
918
919 return 0;
920}
921
922/*
923 * We know that the chip has FIFOs. Does it have an EFR? The
924 * EFR is located in the same register position as the IIR and
925 * we know the top two bits of the IIR are currently set. The
926 * EFR should contain zero. Try to read the EFR.
927 */
928static void autoconfig_16550a(struct uart_8250_port *up)
929{
930 unsigned char status1, status2;
931 unsigned int iersave;
932
933 up->port.type = PORT_16550A;
934 up->capabilities |= UART_CAP_FIFO;
935
dc96efb7
MS		 936 /*
937 * XR17V35x UARTs have an extra divisor register, DLD
938 * that gets enabled with when DLAB is set which will
939 * cause the device to incorrectly match and assign
940 * port type to PORT_16650. The EFR for this UART is
941 * found at offset 0x09. Instead check the Deice ID (DVID)
942 * register for a 2, 4 or 8 port UART.
943 */
b7a7e14f
MS		 944 if (up->port.flags & UPF_EXAR_EFR) {
945 status1 = serial_in(up, UART_EXAR_DVID);
946 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
dc96efb7
MS		 947 DEBUG_AUTOCONF("Exar XR17V35x ");
948 up->port.type = PORT_XR17V35X;
949 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
950 UART_CAP_SLEEP;
951
952 return;
953 }
954
955 }
956
1da177e4
LT		 957 /*
958 * Check for presence of the EFR when DLAB is set.
959 * Only ST16C650V1 UARTs pass this test.
960 */
0acf519f 961 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4 962 if (serial_in(up, UART_EFR) == 0) {
0acf519f 963 serial_out(up, UART_EFR, 0xA8);
1da177e4
LT		 964 if (serial_in(up, UART_EFR) != 0) {
965 DEBUG_AUTOCONF("EFRv1 ");
966 up->port.type = PORT_16650;
967 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
968 } else {
fddceb8b
VR		 969 serial_out(up, UART_LCR, 0);
970 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
971 UART_FCR7_64BYTE);
972 status1 = serial_in(up, UART_IIR) >> 5;
973 serial_out(up, UART_FCR, 0);
974 serial_out(up, UART_LCR, 0);
975
976 if (status1 == 7)
977 up->port.type = PORT_16550A_FSL64;
978 else
979 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1da177e4 980 }
0acf519f 981 serial_out(up, UART_EFR, 0);
1da177e4
LT		 982 return;
983 }
984
985 /*
986 * Maybe it requires 0xbf to be written to the LCR.
987 * (other ST16C650V2 UARTs, TI16C752A, etc)
988 */
0acf519f 989 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 990 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
991 DEBUG_AUTOCONF("EFRv2 ");
992 autoconfig_has_efr(up);
993 return;
994 }
995
996 /*
997 * Check for a National Semiconductor SuperIO chip.
998 * Attempt to switch to bank 2, read the value of the LOOP bit
999 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1000 * switch back to bank 2, read it from EXCR1 again and check
1001 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4 1002 */
0acf519f 1003 serial_out(up, UART_LCR, 0);
1da177e4 1004 status1 = serial_in(up, UART_MCR);
0acf519f 1005 serial_out(up, UART_LCR, 0xE0);
1da177e4
LT		 1006 status2 = serial_in(up, 0x02); /* EXCR1 */
1007
1008 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
0acf519f
PG		 1009 serial_out(up, UART_LCR, 0);
1010 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
1011 serial_out(up, UART_LCR, 0xE0);
1da177e4 1012 status2 = serial_in(up, 0x02); /* EXCR1 */
0acf519f
PG		 1013 serial_out(up, UART_LCR, 0);
1014 serial_out(up, UART_MCR, status1);
1da177e4
LT		 1015
1016 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 1017 unsigned short quot;
1018
0acf519f 1019 serial_out(up, UART_LCR, 0xE0);
857dde2e 1020
b32b19b8 1021 quot = serial_dl_read(up);
857dde2e
DW		 1022 quot <<= 3;
1023
0d0389e5
YK		 1024 if (ns16550a_goto_highspeed(up))
1025 serial_dl_write(up, quot);
857dde2e 1026
0acf519f 1027 serial_out(up, UART_LCR, 0);
1da177e4 1028
857dde2e 1029 up->port.uartclk = 921600*16;
1da177e4
LT		 1030 up->port.type = PORT_NS16550A;
1031 up->capabilities |= UART_NATSEMI;
1032 return;
1033 }
1034 }
1035
1036 /*
1037 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1038 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1039 * Try setting it with and without DLAB set. Cheap clones
1040 * set bit 5 without DLAB set.
1041 */
0acf519f
PG		 1042 serial_out(up, UART_LCR, 0);
1043 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1da177e4 1044 status1 = serial_in(up, UART_IIR) >> 5;
0acf519f
PG		 1045 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1046 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1047 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1da177e4 1048 status2 = serial_in(up, UART_IIR) >> 5;
0acf519f
PG		 1049 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1050 serial_out(up, UART_LCR, 0);
1da177e4
LT		 1051
1052 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1053
1054 if (status1 == 6 && status2 == 7) {
1055 up->port.type = PORT_16750;
1056 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1057 return;
1058 }
1059
1060 /*
1061 * Try writing and reading the UART_IER_UUE bit (b6).
1062 * If it works, this is probably one of the Xscale platform's
1063 * internal UARTs.
1064 * We're going to explicitly set the UUE bit to 0 before
1065 * trying to write and read a 1 just to make sure it's not
1066 * already a 1 and maybe locked there before we even start start.
1067 */
1068 iersave = serial_in(up, UART_IER);
0acf519f 1069 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1da177e4
LT		 1070 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1071 /*
1072 * OK it's in a known zero state, try writing and reading
1073 * without disturbing the current state of the other bits.
1074 */
0acf519f 1075 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1da177e4
LT		 1076 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1077 /*
1078 * It's an Xscale.
1079 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1080 */
1081 DEBUG_AUTOCONF("Xscale ");
1082 up->port.type = PORT_XSCALE;
5568181f 1083 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1da177e4
LT		 1084 return;
1085 }
1086 } else {
1087 /*
1088 * If we got here we couldn't force the IER_UUE bit to 0.
1089 * Log it and continue.
1090 */
1091 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1092 }
0acf519f 1093 serial_out(up, UART_IER, iersave);
235dae5d 1094
06315348
SH		 1095 /*
1096 * Exar uarts have EFR in a weird location
1097 */
1098 if (up->port.flags & UPF_EXAR_EFR) {
81db0772 1099 DEBUG_AUTOCONF("Exar XR17D15x ");
06315348 1100 up->port.type = PORT_XR17D15X;
81db0772
MS		 1101 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1102 UART_CAP_SLEEP;
1103
1104 return;
06315348
SH		 1105 }
1106
235dae5d
PL		 1107 /*
1108 * We distinguish between 16550A and U6 16550A by counting
1109 * how many bytes are in the FIFO.
1110 */
1111 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1112 up->port.type = PORT_U6_16550A;
1113 up->capabilities |= UART_CAP_AFE;
1114 }
1da177e4
LT		 1115}
1116
1117/*
1118 * This routine is called by rs_init() to initialize a specific serial
1119 * port. It determines what type of UART chip this serial port is
1120 * using: 8250, 16450, 16550, 16550A. The important question is
1121 * whether or not this UART is a 16550A or not, since this will
1122 * determine whether or not we can use its FIFO features or not.
1123 */
40375393 1124static void autoconfig(struct uart_8250_port *up)
1da177e4
LT		 1125{
1126 unsigned char status1, scratch, scratch2, scratch3;
1127 unsigned char save_lcr, save_mcr;
dfe42443 1128 struct uart_port *port = &up->port;
1da177e4 1129 unsigned long flags;
bd21f551 1130 unsigned int old_capabilities;
1da177e4 1131
dfe42443 1132 if (!port->iobase && !port->mapbase && !port->membase)
1da177e4
LT		 1133 return;
1134
80647b95 1135 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
dfe42443 1136 serial_index(port), port->iobase, port->membase);
1da177e4
LT		 1137
1138 /*
1139 * We really do need global IRQs disabled here - we're going to
1140 * be frobbing the chips IRQ enable register to see if it exists.
1141 */
dfe42443 1142 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 1143
1144 up->capabilities = 0;
4ba5e35d 1145 up->bugs = 0;
1da177e4 1146
dfe42443 1147 if (!(port->flags & UPF_BUGGY_UART)) {
1da177e4
LT		 1148 /*
1149 * Do a simple existence test first; if we fail this,
1150 * there's no point trying anything else.
bd71c182 1151 *
1da177e4
LT		 1152 * 0x80 is used as a nonsense port to prevent against
1153 * false positives due to ISA bus float. The
1154 * assumption is that 0x80 is a non-existent port;
1155 * which should be safe since include/asm/io.h also
1156 * makes this assumption.
1157 *
1158 * Note: this is safe as long as MCR bit 4 is clear
1159 * and the device is in "PC" mode.
1160 */
0acf519f
PG		 1161 scratch = serial_in(up, UART_IER);
1162 serial_out(up, UART_IER, 0);
1da177e4
LT		 1163#ifdef __i386__
1164 outb(0xff, 0x080);
1165#endif
48212008
TH		 1166 /*
1167 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1168 * 16C754B) allow only to modify them if an EFR bit is set.
1169 */
0acf519f
PG		 1170 scratch2 = serial_in(up, UART_IER) & 0x0f;
1171 serial_out(up, UART_IER, 0x0F);
1da177e4
LT		 1172#ifdef __i386__
1173 outb(0, 0x080);
1174#endif
0acf519f
PG		 1175 scratch3 = serial_in(up, UART_IER) & 0x0f;
1176 serial_out(up, UART_IER, scratch);
1da177e4
LT		 1177 if (scratch2 != 0 || scratch3 != 0x0F) {
1178 /*
1179 * We failed; there's nothing here
1180 */
bd21f551 1181 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1182 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1183 scratch2, scratch3);
1184 goto out;
1185 }
1186 }
1187
1188 save_mcr = serial_in(up, UART_MCR);
1189 save_lcr = serial_in(up, UART_LCR);
1190
bd71c182 1191 /*
1da177e4
LT		 1192 * Check to see if a UART is really there. Certain broken
1193 * internal modems based on the Rockwell chipset fail this
1194 * test, because they apparently don't implement the loopback
1195 * test mode. So this test is skipped on the COM 1 through
1196 * COM 4 ports. This *should* be safe, since no board
1197 * manufacturer would be stupid enough to design a board
1198 * that conflicts with COM 1-4 --- we hope!
1199 */
dfe42443 1200 if (!(port->flags & UPF_SKIP_TEST)) {
0acf519f
PG		 1201 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1202 status1 = serial_in(up, UART_MSR) & 0xF0;
1203 serial_out(up, UART_MCR, save_mcr);
1da177e4 1204 if (status1 != 0x90) {
bd21f551 1205 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1206 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1207 status1);
1208 goto out;
1209 }
1210 }
1211
1212 /*
1213 * We're pretty sure there's a port here. Lets find out what
1214 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1215 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1216 * determines what we test for next.
1217 *
1218 * We also initialise the EFR (if any) to zero for later. The
1219 * EFR occupies the same register location as the FCR and IIR.
1220 */
0acf519f
PG		 1221 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1222 serial_out(up, UART_EFR, 0);
1223 serial_out(up, UART_LCR, 0);
1da177e4 1224
0acf519f 1225 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1da177e4
LT		 1226 scratch = serial_in(up, UART_IIR) >> 6;
1227
1da177e4
LT		 1228 switch (scratch) {
1229 case 0:
1230 autoconfig_8250(up);
1231 break;
1232 case 1:
dfe42443 1233 port->type = PORT_UNKNOWN;
1da177e4
LT		 1234 break;
1235 case 2:
dfe42443 1236 port->type = PORT_16550;
1da177e4
LT		 1237 break;
1238 case 3:
1239 autoconfig_16550a(up);
1240 break;
1241 }
1242
1243#ifdef CONFIG_SERIAL_8250_RSA
1244 /*
1245 * Only probe for RSA ports if we got the region.
1246 */
40375393 1247 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
3b81c26c
PH		 1248 __enable_rsa(up))
1249 port->type = PORT_RSA;
1da177e4 1250#endif
21c614a7 1251
0acf519f 1252 serial_out(up, UART_LCR, save_lcr);
1da177e4 1253
dfe42443 1254 port->fifosize = uart_config[up->port.type].fifo_size;
6ae4a16c 1255 old_capabilities = up->capabilities;
dfe42443
PG		 1256 up->capabilities = uart_config[port->type].flags;
1257 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1da177e4 1258
dfe42443 1259 if (port->type == PORT_UNKNOWN)
bd21f551 1260 goto out_lock;
1da177e4
LT		 1261
1262 /*
1263 * Reset the UART.
1264 */
1265#ifdef CONFIG_SERIAL_8250_RSA
dfe42443 1266 if (port->type == PORT_RSA)
0acf519f 1267 serial_out(up, UART_RSA_FRR, 0);
1da177e4 1268#endif
0acf519f 1269 serial_out(up, UART_MCR, save_mcr);
1da177e4 1270 serial8250_clear_fifos(up);
40b36daa 1271 serial_in(up, UART_RX);
5c8c755c 1272 if (up->capabilities & UART_CAP_UUE)
0acf519f 1273 serial_out(up, UART_IER, UART_IER_UUE);
5c8c755c 1274 else
0acf519f 1275 serial_out(up, UART_IER, 0);
1da177e4 1276
bd21f551 1277out_lock:
dfe42443 1278 spin_unlock_irqrestore(&port->lock, flags);
bd21f551
FL		 1279 if (up->capabilities != old_capabilities) {
1280 printk(KERN_WARNING
1281 "ttyS%d: detected caps %08x should be %08x\n",
1282 serial_index(port), old_capabilities,
1283 up->capabilities);
1284 }
1285out:
1286 DEBUG_AUTOCONF("iir=%d ", scratch);
dfe42443 1287 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1da177e4
LT		 1288}
1289
1290static void autoconfig_irq(struct uart_8250_port *up)
1291{
dfe42443 1292 struct uart_port *port = &up->port;
1da177e4
LT		 1293 unsigned char save_mcr, save_ier;
1294 unsigned char save_ICP = 0;
1295 unsigned int ICP = 0;
1296 unsigned long irqs;
1297 int irq;
1298
dfe42443
PG		 1299 if (port->flags & UPF_FOURPORT) {
1300 ICP = (port->iobase & 0xfe0) | 0x1f;
1da177e4
LT		 1301 save_ICP = inb_p(ICP);
1302 outb_p(0x80, ICP);
0d263a26 1303 inb_p(ICP);
1da177e4
LT		 1304 }
1305
1306 /* forget possible initially masked and pending IRQ */
1307 probe_irq_off(probe_irq_on());
0acf519f
PG		 1308 save_mcr = serial_in(up, UART_MCR);
1309 save_ier = serial_in(up, UART_IER);
1310 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1311
1da177e4 1312 irqs = probe_irq_on();
0acf519f 1313 serial_out(up, UART_MCR, 0);
6f803cd0 1314 udelay(10);
dfe42443 1315 if (port->flags & UPF_FOURPORT) {
0acf519f 1316 serial_out(up, UART_MCR,
1da177e4
LT		 1317 UART_MCR_DTR | UART_MCR_RTS);
1318 } else {
0acf519f 1319 serial_out(up, UART_MCR,
1da177e4
LT		 1320 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1321 }
0acf519f 1322 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
0d263a26
PG		 1323 serial_in(up, UART_LSR);
1324 serial_in(up, UART_RX);
1325 serial_in(up, UART_IIR);
1326 serial_in(up, UART_MSR);
0acf519f 1327 serial_out(up, UART_TX, 0xFF);
6f803cd0 1328 udelay(20);
1da177e4
LT		 1329 irq = probe_irq_off(irqs);
1330
0acf519f
PG		 1331 serial_out(up, UART_MCR, save_mcr);
1332 serial_out(up, UART_IER, save_ier);
1da177e4 1333
dfe42443 1334 if (port->flags & UPF_FOURPORT)
1da177e4
LT		 1335 outb_p(save_ICP, ICP);
1336
dfe42443 1337 port->irq = (irq > 0) ? irq : 0;
1da177e4
LT		 1338}
1339
e763b90c
RK		 1340static inline void __stop_tx(struct uart_8250_port *p)
1341{
1342 if (p->ier & UART_IER_THRI) {
1343 p->ier &= ~UART_IER_THRI;
1344 serial_out(p, UART_IER, p->ier);
d74d5d1b 1345 serial8250_rpm_put_tx(p);
e763b90c
RK		 1346 }
1347}
1348
b129a8cc 1349static void serial8250_stop_tx(struct uart_port *port)
1da177e4 1350{
b1261c86 1351 struct uart_8250_port *up = up_to_u8250p(port);
1da177e4 1352
d74d5d1b 1353 serial8250_rpm_get(up);
e763b90c 1354 __stop_tx(up);
1da177e4
LT		 1355
1356 /*
e763b90c 1357 * We really want to stop the transmitter from sending.
1da177e4 1358 */
dfe42443 1359 if (port->type == PORT_16C950) {
1da177e4
LT		 1360 up->acr |= UART_ACR_TXDIS;
1361 serial_icr_write(up, UART_ACR, up->acr);
1362 }
d74d5d1b 1363 serial8250_rpm_put(up);
1da177e4
LT		 1364}
1365
b129a8cc 1366static void serial8250_start_tx(struct uart_port *port)
1da177e4 1367{
b1261c86 1368 struct uart_8250_port *up = up_to_u8250p(port);
1da177e4 1369
d74d5d1b 1370 serial8250_rpm_get_tx(up);
a39d1da1
AS		 1371
1372 if (up->dma && !up->dma->tx_dma(up))
9ee4b83e 1373 return;
a39d1da1
AS		 1374
1375 if (!(up->ier & UART_IER_THRI)) {
1da177e4 1376 up->ier |= UART_IER_THRI;
4fd996a1 1377 serial_port_out(port, UART_IER, up->ier);
55d3b282 1378
67f7654e 1379 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1380 unsigned char lsr;
55d3b282 1381 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1382 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
c09babfa 1383 if (lsr & UART_LSR_THRE)
3986fb2b 1384 serial8250_tx_chars(up);
55d3b282 1385 }
1da177e4 1386 }
e763b90c 1387
1da177e4 1388 /*
e763b90c 1389 * Re-enable the transmitter if we disabled it.
1da177e4 1390 */
dfe42443 1391 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1392 up->acr &= ~UART_ACR_TXDIS;
1393 serial_icr_write(up, UART_ACR, up->acr);
1394 }
1395}
1396
234abab1
SAS		 1397static void serial8250_throttle(struct uart_port *port)
1398{
1399 port->throttle(port);
1400}
1401
1402static void serial8250_unthrottle(struct uart_port *port)
1403{
1404 port->unthrottle(port);
1405}
1406
1da177e4
LT		 1407static void serial8250_stop_rx(struct uart_port *port)
1408{
b1261c86 1409 struct uart_8250_port *up = up_to_u8250p(port);
1da177e4 1410
d74d5d1b
SAS		 1411 serial8250_rpm_get(up);
1412
9137568e 1413 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1da177e4 1414 up->port.read_status_mask &= ~UART_LSR_DR;
4fd996a1 1415 serial_port_out(port, UART_IER, up->ier);
d74d5d1b
SAS		 1416
1417 serial8250_rpm_put(up);
1da177e4
LT		 1418}
1419
cab68f89
PH		 1420static void serial8250_disable_ms(struct uart_port *port)
1421{
1422 struct uart_8250_port *up =
1423 container_of(port, struct uart_8250_port, port);
1424
1425 /* no MSR capabilities */
1426 if (up->bugs & UART_BUG_NOMSR)
1427 return;
1428
1429 up->ier &= ~UART_IER_MSI;
1430 serial_port_out(port, UART_IER, up->ier);
1431}
1432
1da177e4
LT		 1433static void serial8250_enable_ms(struct uart_port *port)
1434{
b1261c86 1435 struct uart_8250_port *up = up_to_u8250p(port);
1da177e4 1436
21c614a7
PA		 1437 /* no MSR capabilities */
1438 if (up->bugs & UART_BUG_NOMSR)
1439 return;
1440
1da177e4 1441 up->ier |= UART_IER_MSI;
d74d5d1b
SAS		 1442
1443 serial8250_rpm_get(up);
4fd996a1 1444 serial_port_out(port, UART_IER, up->ier);
d74d5d1b 1445 serial8250_rpm_put(up);
1da177e4
LT		 1446}
1447
0690f41f 1448/*
3986fb2b 1449 * serial8250_rx_chars: processes according to the passed in LSR
0690f41f
PG		 1450 * value, and returns the remaining LSR bits not handled
1451 * by this Rx routine.
1452 */
3986fb2b
PG		 1453unsigned char
1454serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1da177e4 1455{
dfe42443 1456 struct uart_port *port = &up->port;
0690f41f 1457 unsigned char ch;
1da177e4
LT		 1458 int max_count = 256;
1459 char flag;
1460
1461 do {
7500b1f6 1462 if (likely(lsr & UART_LSR_DR))
0acf519f 1463 ch = serial_in(up, UART_RX);
7500b1f6
AR		 1464 else
1465 /*
1466 * Intel 82571 has a Serial Over Lan device that will
1467 * set UART_LSR_BI without setting UART_LSR_DR when
1468 * it receives a break. To avoid reading from the
1469 * receive buffer without UART_LSR_DR bit set, we
1470 * just force the read character to be 0
1471 */
1472 ch = 0;
1473
1da177e4 1474 flag = TTY_NORMAL;
dfe42443 1475 port->icount.rx++;
1da177e4 1476
ad4c2aa6
CM		 1477 lsr |= up->lsr_saved_flags;
1478 up->lsr_saved_flags = 0;
1da177e4 1479
ad4c2aa6 1480 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1481 if (lsr & UART_LSR_BI) {
1482 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
dfe42443 1483 port->icount.brk++;
1da177e4
LT		 1484 /*
1485 * We do the SysRQ and SAK checking
1486 * here because otherwise the break
1487 * may get masked by ignore_status_mask
1488 * or read_status_mask.
1489 */
dfe42443 1490 if (uart_handle_break(port))
1da177e4
LT		 1491 goto ignore_char;
1492 } else if (lsr & UART_LSR_PE)
dfe42443 1493 port->icount.parity++;
1da177e4 1494 else if (lsr & UART_LSR_FE)
dfe42443 1495 port->icount.frame++;
1da177e4 1496 if (lsr & UART_LSR_OE)
dfe42443 1497 port->icount.overrun++;
1da177e4
LT		 1498
1499 /*
23907eb8 1500 * Mask off conditions which should be ignored.
1da177e4 1501 */
dfe42443 1502 lsr &= port->read_status_mask;
1da177e4
LT		 1503
1504 if (lsr & UART_LSR_BI) {
1505 DEBUG_INTR("handling break....");
1506 flag = TTY_BREAK;
1507 } else if (lsr & UART_LSR_PE)
1508 flag = TTY_PARITY;
1509 else if (lsr & UART_LSR_FE)
1510 flag = TTY_FRAME;
1511 }
dfe42443 1512 if (uart_handle_sysrq_char(port, ch))
1da177e4 1513 goto ignore_char;
05ab3014 1514
dfe42443 1515 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
05ab3014 1516
6f803cd0 1517ignore_char:
0acf519f 1518 lsr = serial_in(up, UART_LSR);
c904375d 1519 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (--max_count > 0));
dfe42443 1520 spin_unlock(&port->lock);
2e124b4a 1521 tty_flip_buffer_push(&port->state->port);
dfe42443 1522 spin_lock(&port->lock);
0690f41f 1523 return lsr;
1da177e4 1524}
3986fb2b 1525EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1da177e4 1526
3986fb2b 1527void serial8250_tx_chars(struct uart_8250_port *up)
1da177e4 1528{
dfe42443
PG		 1529 struct uart_port *port = &up->port;
1530 struct circ_buf *xmit = &port->state->xmit;
1da177e4
LT		 1531 int count;
1532
dfe42443
PG		 1533 if (port->x_char) {
1534 serial_out(up, UART_TX, port->x_char);
1535 port->icount.tx++;
1536 port->x_char = 0;
1da177e4
LT		 1537 return;
1538 }
dfe42443
PG		 1539 if (uart_tx_stopped(port)) {
1540 serial8250_stop_tx(port);
b129a8cc
RK		 1541 return;
1542 }
1543 if (uart_circ_empty(xmit)) {
e763b90c 1544 __stop_tx(up);
1da177e4
LT		 1545 return;
1546 }
1547
1548 count = up->tx_loadsz;
1549 do {
1550 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1551 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
dfe42443 1552 port->icount.tx++;
1da177e4
LT		 1553 if (uart_circ_empty(xmit))
1554 break;
ebebd49a
SH		 1555 if (up->capabilities & UART_CAP_HFIFO) {
1556 if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1557 BOTH_EMPTY)
1558 break;
1559 }
1da177e4
LT		 1560 } while (--count > 0);
1561
1562 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
dfe42443 1563 uart_write_wakeup(port);
1da177e4
LT		 1564
1565 DEBUG_INTR("THRE...");
1566
d74d5d1b 1567 /*
6a529aba 1568 * With RPM enabled, we have to wait until the FIFO is empty before the
d74d5d1b
SAS		 1569 * HW can go idle. So we get here once again with empty FIFO and disable
1570 * the interrupt and RPM in __stop_tx()
1571 */
1572 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
e763b90c 1573 __stop_tx(up);
1da177e4 1574}
3986fb2b 1575EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1da177e4 1576
5435d20f 1577/* Caller holds uart port lock */
3986fb2b 1578unsigned int serial8250_modem_status(struct uart_8250_port *up)
1da177e4 1579{
dfe42443 1580 struct uart_port *port = &up->port;
2af7cd68
RK		 1581 unsigned int status = serial_in(up, UART_MSR);
1582
ad4c2aa6
CM		 1583 status |= up->msr_saved_flags;
1584 up->msr_saved_flags = 0;
fdc30b3d 1585 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
dfe42443 1586 port->state != NULL) {
2af7cd68 1587 if (status & UART_MSR_TERI)
dfe42443 1588 port->icount.rng++;
2af7cd68 1589 if (status & UART_MSR_DDSR)
dfe42443 1590 port->icount.dsr++;
2af7cd68 1591 if (status & UART_MSR_DDCD)
dfe42443 1592 uart_handle_dcd_change(port, status & UART_MSR_DCD);
2af7cd68 1593 if (status & UART_MSR_DCTS)
dfe42443 1594 uart_handle_cts_change(port, status & UART_MSR_CTS);
2af7cd68 1595
dfe42443 1596 wake_up_interruptible(&port->state->port.delta_msr_wait);
2af7cd68 1597 }
1da177e4 1598
2af7cd68 1599 return status;
1da177e4 1600}
3986fb2b 1601EXPORT_SYMBOL_GPL(serial8250_modem_status);
1da177e4
LT		 1602
1603/*
1604 * This handles the interrupt from one port.
1605 */
86b21199 1606int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1da177e4 1607{
0690f41f 1608 unsigned char status;
4bf3631c 1609 unsigned long flags;
b1261c86 1610 struct uart_8250_port *up = up_to_u8250p(port);
9ee4b83e 1611 int dma_err = 0;
86b21199
PG		 1612
1613 if (iir & UART_IIR_NO_INT)
1614 return 0;
45e24601 1615
dfe42443 1616 spin_lock_irqsave(&port->lock, flags);
45e24601 1617
4fd996a1 1618 status = serial_port_in(port, UART_LSR);
1da177e4
LT		 1619
1620 DEBUG_INTR("status = %x...", status);
1621
9ee4b83e
HK		 1622 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1623 if (up->dma)
f1a297bb 1624 dma_err = up->dma->rx_dma(up, iir);
9ee4b83e
HK		 1625
1626 if (!up->dma || dma_err)
1627 status = serial8250_rx_chars(up, status);
1628 }
3986fb2b 1629 serial8250_modem_status(up);
b2202821
SAS		 1630 if ((!up->dma || (up->dma && up->dma->tx_err)) &&
1631 (status & UART_LSR_THRE))
3986fb2b 1632 serial8250_tx_chars(up);
45e24601 1633
dfe42443 1634 spin_unlock_irqrestore(&port->lock, flags);
86b21199 1635 return 1;
583d28e9 1636}
c7a1bdc5 1637EXPORT_SYMBOL_GPL(serial8250_handle_irq);
583d28e9
JI		 1638
1639static int serial8250_default_handle_irq(struct uart_port *port)
1640{
d74d5d1b
SAS		 1641 struct uart_8250_port *up = up_to_u8250p(port);
1642 unsigned int iir;
1643 int ret;
1644
1645 serial8250_rpm_get(up);
583d28e9 1646
d74d5d1b
SAS		 1647 iir = serial_port_in(port, UART_IIR);
1648 ret = serial8250_handle_irq(port, iir);
1649
1650 serial8250_rpm_put(up);
1651 return ret;
583d28e9
JI		 1652}
1653
dc96efb7
MS		 1654/*
1655 * These Exar UARTs have an extra interrupt indicator that could
1656 * fire for a few unimplemented interrupts. One of which is a
1657 * wakeup event when coming out of sleep. Put this here just
1658 * to be on the safe side that these interrupts don't go unhandled.
1659 */
1660static int exar_handle_irq(struct uart_port *port)
1661{
1662 unsigned char int0, int1, int2, int3;
1663 unsigned int iir = serial_port_in(port, UART_IIR);
1664 int ret;
1665
1666 ret = serial8250_handle_irq(port, iir);
1667
30fa96a3
MS		 1668 if ((port->type == PORT_XR17V35X) ||
1669 (port->type == PORT_XR17D15X)) {
dc96efb7
MS		 1670 int0 = serial_port_in(port, 0x80);
1671 int1 = serial_port_in(port, 0x81);
1672 int2 = serial_port_in(port, 0x82);
1673 int3 = serial_port_in(port, 0x83);
1674 }
1675
1676 return ret;
1677}
1678
1da177e4
LT		 1679/*
1680 * This is the serial driver's interrupt routine.
1681 *
1682 * Arjan thinks the old way was overly complex, so it got simplified.
1683 * Alan disagrees, saying that need the complexity to handle the weird
1684 * nature of ISA shared interrupts. (This is a special exception.)
1685 *
1686 * In order to handle ISA shared interrupts properly, we need to check
1687 * that all ports have been serviced, and therefore the ISA interrupt
1688 * line has been de-asserted.
1689 *
1690 * This means we need to loop through all ports. checking that they
1691 * don't have an interrupt pending.
1692 */
7d12e780 1693static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1694{
1695 struct irq_info *i = dev_id;
1696 struct list_head *l, *end = NULL;
1697 int pass_counter = 0, handled = 0;
1698
1699 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1700
1701 spin_lock(&i->lock);
1702
1703 l = i->head;
1704 do {
1705 struct uart_8250_port *up;
583d28e9 1706 struct uart_port *port;
1da177e4
LT		 1707
1708 up = list_entry(l, struct uart_8250_port, list);
583d28e9 1709 port = &up->port;
1da177e4 1710
49b532f9 1711 if (port->handle_irq(port)) {
1da177e4 1712 handled = 1;
1da177e4
LT		 1713 end = NULL;
1714 } else if (end == NULL)
1715 end = l;
1716
1717 l = l->next;
1718
1719 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1720 /* If we hit this, we're dead. */
cd3ecad1
DD		 1721 printk_ratelimited(KERN_ERR
1722 "serial8250: too much work for irq%d\n", irq);
1da177e4
LT		 1723 break;
1724 }
1725 } while (l != end);
1726
1727 spin_unlock(&i->lock);
1728
1729 DEBUG_INTR("end.\n");
1730
1731 return IRQ_RETVAL(handled);
1732}
1733
1734/*
1735 * To support ISA shared interrupts, we need to have one interrupt
1736 * handler that ensures that the IRQ line has been deasserted
1737 * before returning. Failing to do this will result in the IRQ
1738 * line being stuck active, and, since ISA irqs are edge triggered,
1739 * no more IRQs will be seen.
1740 */
1741static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1742{
1743 spin_lock_irq(&i->lock);
1744
1745 if (!list_empty(i->head)) {
1746 if (i->head == &up->list)
1747 i->head = i->head->next;
1748 list_del(&up->list);
1749 } else {
1750 BUG_ON(i->head != &up->list);
1751 i->head = NULL;
1752 }
1da177e4 1753 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1754 /* List empty so throw away the hash node */
1755 if (i->head == NULL) {
1756 hlist_del(&i->node);
1757 kfree(i);
1758 }
1da177e4
LT		 1759}
1760
1761static int serial_link_irq_chain(struct uart_8250_port *up)
1762{
25db8ad5
AC		 1763 struct hlist_head *h;
1764 struct hlist_node *n;
1765 struct irq_info *i;
40663cc7 1766 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1767
25db8ad5
AC		 1768 mutex_lock(&hash_mutex);
1769
1770 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1771
1772 hlist_for_each(n, h) {
1773 i = hlist_entry(n, struct irq_info, node);
1774 if (i->irq == up->port.irq)
1775 break;
1776 }
1777
1778 if (n == NULL) {
1779 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1780 if (i == NULL) {
1781 mutex_unlock(&hash_mutex);
1782 return -ENOMEM;
1783 }
1784 spin_lock_init(&i->lock);
1785 i->irq = up->port.irq;
1786 hlist_add_head(&i->node, h);
1787 }
1788 mutex_unlock(&hash_mutex);
1789
1da177e4
LT		 1790 spin_lock_irq(&i->lock);
1791
1792 if (i->head) {
1793 list_add(&up->list, i->head);
1794 spin_unlock_irq(&i->lock);
1795
1796 ret = 0;
1797 } else {
1798 INIT_LIST_HEAD(&up->list);
1799 i->head = &up->list;
1800 spin_unlock_irq(&i->lock);
1c2f0493 1801 irq_flags |= up->port.irqflags;
1da177e4
LT		 1802 ret = request_irq(up->port.irq, serial8250_interrupt,
1803 irq_flags, "serial", i);
1804 if (ret < 0)
1805 serial_do_unlink(i, up);
1806 }
1807
1808 return ret;
1809}
1810
1811static void serial_unlink_irq_chain(struct uart_8250_port *up)
1812{
bd2fe272
PG		 1813 /*
1814 * yes, some broken gcc emit "warning: 'i' may be used uninitialized"
1815 * but no, we are not going to take a patch that assigns NULL below.
1816 */
25db8ad5
AC		 1817 struct irq_info *i;
1818 struct hlist_node *n;
1819 struct hlist_head *h;
1da177e4 1820
25db8ad5
AC		 1821 mutex_lock(&hash_mutex);
1822
1823 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1824
1825 hlist_for_each(n, h) {
1826 i = hlist_entry(n, struct irq_info, node);
1827 if (i->irq == up->port.irq)
1828 break;
1829 }
1830
1831 BUG_ON(n == NULL);
1da177e4
LT		 1832 BUG_ON(i->head == NULL);
1833
1834 if (list_empty(i->head))
1835 free_irq(up->port.irq, i);
1836
1837 serial_do_unlink(i, up);
25db8ad5 1838 mutex_unlock(&hash_mutex);
1da177e4
LT		 1839}
1840
1841/*
1842 * This function is used to handle ports that do not have an
1843 * interrupt. This doesn't work very well for 16450's, but gives
1844 * barely passable results for a 16550A. (Although at the expense
1845 * of much CPU overhead).
1846 */
1847static void serial8250_timeout(unsigned long data)
1848{
1849 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4 1850
a0431476 1851 up->port.handle_irq(&up->port);
54381067 1852 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
40b36daa
AW		 1853}
1854
1855static void serial8250_backup_timeout(unsigned long data)
1856{
1857 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1858 unsigned int iir, ier = 0, lsr;
1859 unsigned long flags;
40b36daa 1860
dbb3b1ca
AC		 1861 spin_lock_irqsave(&up->port.lock, flags);
1862
40b36daa
AW		 1863 /*
1864 * Must disable interrupts or else we risk racing with the interrupt
1865 * based handler.
1866 */
d4e33fac 1867 if (up->port.irq) {
40b36daa
AW		 1868 ier = serial_in(up, UART_IER);
1869 serial_out(up, UART_IER, 0);
1870 }
1da177e4 1871
40b36daa
AW		 1872 iir = serial_in(up, UART_IIR);
1873
1874 /*
1875 * This should be a safe test for anyone who doesn't trust the
1876 * IIR bits on their UART, but it's specifically designed for
1877 * the "Diva" UART used on the management processor on many HP
1878 * ia64 and parisc boxes.
1879 */
ad4c2aa6
CM		 1880 lsr = serial_in(up, UART_LSR);
1881 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
40b36daa 1882 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1883 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1884 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1885 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1886 iir |= UART_IIR_THRI;
1887 }
1888
1889 if (!(iir & UART_IIR_NO_INT))
3986fb2b 1890 serial8250_tx_chars(up);
40b36daa 1891
d4e33fac 1892 if (up->port.irq)
40b36daa
AW		 1893 serial_out(up, UART_IER, ier);
1894
dbb3b1ca
AC		 1895 spin_unlock_irqrestore(&up->port.lock, flags);
1896
40b36daa 1897 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0 1898 mod_timer(&up->timer,
54381067 1899 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1da177e4
LT		 1900}
1901
a4416cd1
PH		 1902static int univ8250_setup_irq(struct uart_8250_port *up)
1903{
1904 struct uart_port *port = &up->port;
1905 int retval = 0;
1906
1907 /*
1908 * The above check will only give an accurate result the first time
1909 * the port is opened so this value needs to be preserved.
1910 */
1911 if (up->bugs & UART_BUG_THRE) {
1912 pr_debug("ttyS%d - using backup timer\n", serial_index(port));
1913
1914 up->timer.function = serial8250_backup_timeout;
1915 up->timer.data = (unsigned long)up;
1916 mod_timer(&up->timer, jiffies +
1917 uart_poll_timeout(port) + HZ / 5);
1918 }
1919
1920 /*
1921 * If the "interrupt" for this port doesn't correspond with any
1922 * hardware interrupt, we use a timer-based system. The original
1923 * driver used to do this with IRQ0.
1924 */
1925 if (!port->irq) {
1926 up->timer.data = (unsigned long)up;
1927 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
1928 } else
1929 retval = serial_link_irq_chain(up);
1930
1931 return retval;
1932}
1933
1934static void univ8250_release_irq(struct uart_8250_port *up)
1935{
1936 struct uart_port *port = &up->port;
1937
1938 del_timer_sync(&up->timer);
1939 up->timer.function = serial8250_timeout;
1940 if (port->irq)
1941 serial_unlink_irq_chain(up);
1942}
1943
1da177e4
LT		 1944static unsigned int serial8250_tx_empty(struct uart_port *port)
1945{
b1261c86 1946 struct uart_8250_port *up = up_to_u8250p(port);
1da177e4 1947 unsigned long flags;
ad4c2aa6 1948 unsigned int lsr;
1da177e4 1949
d74d5d1b
SAS		 1950 serial8250_rpm_get(up);
1951
dfe42443 1952 spin_lock_irqsave(&port->lock, flags);
4fd996a1 1953 lsr = serial_port_in(port, UART_LSR);
ad4c2aa6 1954 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
dfe42443 1955 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 1956
d74d5d1b
SAS		 1957 serial8250_rpm_put(up);
1958
bca47613 1959 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1960}
1961
1962static unsigned int serial8250_get_mctrl(struct uart_port *port)
1963{
b1261c86 1964 struct uart_8250_port *up = up_to_u8250p(port);
2af7cd68 1965 unsigned int status;
1da177e4
LT		 1966 unsigned int ret;
1967
d74d5d1b 1968 serial8250_rpm_get(up);
3986fb2b 1969 status = serial8250_modem_status(up);
d74d5d1b 1970 serial8250_rpm_put(up);
1da177e4
LT		 1971
1972 ret = 0;
1973 if (status & UART_MSR_DCD)
1974 ret |= TIOCM_CAR;
1975 if (status & UART_MSR_RI)
1976 ret |= TIOCM_RNG;
1977 if (status & UART_MSR_DSR)
1978 ret |= TIOCM_DSR;
1979 if (status & UART_MSR_CTS)
1980 ret |= TIOCM_CTS;
1981 return ret;
1982}
1983
4bf4ea9d 1984void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 1985{
b1261c86 1986 struct uart_8250_port *up = up_to_u8250p(port);
1da177e4
LT		 1987 unsigned char mcr = 0;
1988
1989 if (mctrl & TIOCM_RTS)
1990 mcr |= UART_MCR_RTS;
1991 if (mctrl & TIOCM_DTR)
1992 mcr |= UART_MCR_DTR;
1993 if (mctrl & TIOCM_OUT1)
1994 mcr |= UART_MCR_OUT1;
1995 if (mctrl & TIOCM_OUT2)
1996 mcr |= UART_MCR_OUT2;
1997 if (mctrl & TIOCM_LOOP)
1998 mcr |= UART_MCR_LOOP;
1999
2000 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
2001
4fd996a1 2002 serial_port_out(port, UART_MCR, mcr);
1da177e4 2003}
4bf4ea9d
PH		 2004EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2005
2006static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2007{
2008 if (port->set_mctrl)
2009 return port->set_mctrl(port, mctrl);
2010 return serial8250_do_set_mctrl(port, mctrl);
2011}
1da177e4
LT		 2012
2013static void serial8250_break_ctl(struct uart_port *port, int break_state)
2014{
b1261c86 2015 struct uart_8250_port *up = up_to_u8250p(port);
1da177e4
LT		 2016 unsigned long flags;
2017
d74d5d1b 2018 serial8250_rpm_get(up);
dfe42443 2019 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 2020 if (break_state == -1)
2021 up->lcr |= UART_LCR_SBC;
2022 else
2023 up->lcr &= ~UART_LCR_SBC;
4fd996a1 2024 serial_port_out(port, UART_LCR, up->lcr);
dfe42443 2025 spin_unlock_irqrestore(&port->lock, flags);
d74d5d1b 2026 serial8250_rpm_put(up);
1da177e4
LT		 2027}
2028
40b36daa
AW		 2029/*
2030 * Wait for transmitter & holding register to empty
2031 */
b5d674ab 2032static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 2033{
2034 unsigned int status, tmout = 10000;
2035
2036 /* Wait up to 10ms for the character(s) to be sent. */
97d303b7 2037 for (;;) {
40b36daa
AW		 2038 status = serial_in(up, UART_LSR);
2039
ad4c2aa6 2040 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa 2041
97d303b7
DD		 2042 if ((status & bits) == bits)
2043 break;
40b36daa
AW		 2044 if (--tmout == 0)
2045 break;
2046 udelay(1);
97d303b7 2047 }
40b36daa
AW		 2048
2049 /* Wait up to 1s for flow control if necessary */
2050 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 2051 unsigned int tmout;
2052 for (tmout = 1000000; tmout; tmout--) {
2053 unsigned int msr = serial_in(up, UART_MSR);
2054 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2055 if (msr & UART_MSR_CTS)
2056 break;
40b36daa
AW		 2057 udelay(1);
2058 touch_nmi_watchdog();
2059 }
2060 }
2061}
2062
f2d937f3
JW		 2063#ifdef CONFIG_CONSOLE_POLL
2064/*
2065 * Console polling routines for writing and reading from the uart while
2066 * in an interrupt or debug context.
2067 */
2068
2069static int serial8250_get_poll_char(struct uart_port *port)
2070{
d74d5d1b
SAS		 2071 struct uart_8250_port *up = up_to_u8250p(port);
2072 unsigned char lsr;
2073 int status;
f2d937f3 2074
d74d5d1b 2075 serial8250_rpm_get(up);
f2d937f3 2076
d74d5d1b 2077 lsr = serial_port_in(port, UART_LSR);
f2d937f3 2078
d74d5d1b
SAS		 2079 if (!(lsr & UART_LSR_DR)) {
2080 status = NO_POLL_CHAR;
2081 goto out;
2082 }
f2d937f3 2083
d74d5d1b
SAS		 2084 status = serial_port_in(port, UART_RX);
2085out:
2086 serial8250_rpm_put(up);
2087 return status;
f2d937f3
JW		 2088}
2089
2090
2091static void serial8250_put_poll_char(struct uart_port *port,
2092 unsigned char c)
2093{
2094 unsigned int ier;
b1261c86 2095 struct uart_8250_port *up = up_to_u8250p(port);
f2d937f3 2096
d74d5d1b 2097 serial8250_rpm_get(up);
f2d937f3
JW		 2098 /*
2099 * First save the IER then disable the interrupts
2100 */
4fd996a1 2101 ier = serial_port_in(port, UART_IER);
f2d937f3 2102 if (up->capabilities & UART_CAP_UUE)
4fd996a1 2103 serial_port_out(port, UART_IER, UART_IER_UUE);
f2d937f3 2104 else
4fd996a1 2105 serial_port_out(port, UART_IER, 0);
f2d937f3
JW		 2106
2107 wait_for_xmitr(up, BOTH_EMPTY);
2108 /*
2109 * Send the character out.
f2d937f3 2110 */
4fd996a1 2111 serial_port_out(port, UART_TX, c);
f2d937f3
JW		 2112
2113 /*
2114 * Finally, wait for transmitter to become empty
2115 * and restore the IER
2116 */
2117 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 2118 serial_port_out(port, UART_IER, ier);
d74d5d1b 2119 serial8250_rpm_put(up);
f2d937f3
JW		 2120}
2121
2122#endif /* CONFIG_CONSOLE_POLL */
2123
b99b121b 2124int serial8250_do_startup(struct uart_port *port)
1da177e4 2125{
b1261c86 2126 struct uart_8250_port *up = up_to_u8250p(port);
1da177e4 2127 unsigned long flags;
55d3b282 2128 unsigned char lsr, iir;
1da177e4
LT		 2129 int retval;
2130
65ecc9c0
SY		 2131 if (port->type == PORT_8250_CIR)
2132 return -ENODEV;
2133
9660497c
HK		 2134 if (!port->fifosize)
2135 port->fifosize = uart_config[port->type].fifo_size;
2136 if (!up->tx_loadsz)
2137 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2138 if (!up->capabilities)
2139 up->capabilities = uart_config[port->type].flags;
1da177e4
LT		 2140 up->mcr = 0;
2141
dfe42443 2142 if (port->iotype != up->cur_iotype)
b8e7e40a
AC		 2143 set_io_from_upio(port);
2144
d74d5d1b 2145 serial8250_rpm_get(up);
dfe42443 2146 if (port->type == PORT_16C950) {
1da177e4
LT		 2147 /* Wake up and initialize UART */
2148 up->acr = 0;
4fd996a1
PG		 2149 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2150 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2151 serial_port_out(port, UART_IER, 0);
2152 serial_port_out(port, UART_LCR, 0);
1da177e4 2153 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
4fd996a1
PG		 2154 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2155 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2156 serial_port_out(port, UART_LCR, 0);
1da177e4
LT		 2157 }
2158
2159#ifdef CONFIG_SERIAL_8250_RSA
2160 /*
2161 * If this is an RSA port, see if we can kick it up to the
2162 * higher speed clock.
2163 */
2164 enable_rsa(up);
2165#endif
1da177e4
LT		 2166 /*
2167 * Clear the FIFO buffers and disable them.
7f927fcc 2168 * (they will be reenabled in set_termios())
1da177e4
LT		 2169 */
2170 serial8250_clear_fifos(up);
2171
2172 /*
2173 * Clear the interrupt registers.
2174 */
ca8bb4ae
SAS		 2175 serial_port_in(port, UART_LSR);
2176 serial_port_in(port, UART_RX);
4fd996a1
PG		 2177 serial_port_in(port, UART_IIR);
2178 serial_port_in(port, UART_MSR);
1da177e4
LT		 2179
2180 /*
2181 * At this point, there's no way the LSR could still be 0xff;
2182 * if it is, then bail out, because there's likely no UART
2183 * here.
2184 */
dfe42443 2185 if (!(port->flags & UPF_BUGGY_UART) &&
4fd996a1 2186 (serial_port_in(port, UART_LSR) == 0xff)) {
7808a4c4 2187 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
dfe42443 2188 serial_index(port));
d74d5d1b
SAS		 2189 retval = -ENODEV;
2190 goto out;
1da177e4
LT		 2191 }
2192
2193 /*
2194 * For a XR16C850, we need to set the trigger levels
2195 */
dfe42443 2196 if (port->type == PORT_16850) {
1da177e4
LT		 2197 unsigned char fctr;
2198
0acf519f 2199 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4 2200
0acf519f 2201 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
4fd996a1
PG		 2202 serial_port_out(port, UART_FCTR,
2203 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2204 serial_port_out(port, UART_TRG, UART_TRG_96);
2205 serial_port_out(port, UART_FCTR,
2206 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2207 serial_port_out(port, UART_TRG, UART_TRG_96);
1da177e4 2208
4fd996a1 2209 serial_port_out(port, UART_LCR, 0);
1da177e4
LT		 2210 }
2211
dfe42443 2212 if (port->irq) {
01c194d9 2213 unsigned char iir1;
40b36daa
AW		 2214 /*
2215 * Test for UARTs that do not reassert THRE when the
2216 * transmitter is idle and the interrupt has already
2217 * been cleared. Real 16550s should always reassert
2218 * this interrupt whenever the transmitter is idle and
2219 * the interrupt is enabled. Delays are necessary to
2220 * allow register changes to become visible.
2221 */
dfe42443 2222 spin_lock_irqsave(&port->lock, flags);
1c2f0493 2223 if (up->port.irqflags & IRQF_SHARED)
dfe42443 2224 disable_irq_nosync(port->irq);
40b36daa
AW		 2225
2226 wait_for_xmitr(up, UART_LSR_THRE);
55e4016d 2227 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
40b36daa 2228 udelay(1); /* allow THRE to set */
4fd996a1
PG		 2229 iir1 = serial_port_in(port, UART_IIR);
2230 serial_port_out(port, UART_IER, 0);
55e4016d 2231 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
40b36daa 2232 udelay(1); /* allow a working UART time to re-assert THRE */
4fd996a1
PG		 2233 iir = serial_port_in(port, UART_IIR);
2234 serial_port_out(port, UART_IER, 0);
40b36daa 2235
dfe42443
PG		 2236 if (port->irqflags & IRQF_SHARED)
2237 enable_irq(port->irq);
2238 spin_unlock_irqrestore(&port->lock, flags);
40b36daa
AW		 2239
2240 /*
bc02d15a
DW		 2241 * If the interrupt is not reasserted, or we otherwise
2242 * don't trust the iir, setup a timer to kick the UART
2243 * on a regular basis.
40b36daa 2244 */
bc02d15a
DW		 2245 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2246 up->port.flags & UPF_BUG_THRE) {
363f66fe 2247 up->bugs |= UART_BUG_THRE;
40b36daa
AW		 2248 }
2249 }
2250
a4416cd1
PH		 2251 retval = up->ops->setup_irq(up);
2252 if (retval)
2253 goto out;
1da177e4
LT		 2254
2255 /*
2256 * Now, initialize the UART
2257 */
4fd996a1 2258 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
1da177e4 2259
dfe42443 2260 spin_lock_irqsave(&port->lock, flags);
1da177e4 2261 if (up->port.flags & UPF_FOURPORT) {
d4e33fac 2262 if (!up->port.irq)
1da177e4
LT		 2263 up->port.mctrl |= TIOCM_OUT1;
2264 } else
2265 /*
2266 * Most PC uarts need OUT2 raised to enable interrupts.
2267 */
dfe42443 2268 if (port->irq)
1da177e4
LT		 2269 up->port.mctrl |= TIOCM_OUT2;
2270
dfe42443 2271 serial8250_set_mctrl(port, port->mctrl);
55d3b282 2272
b6adea33
MCC		 2273 /* Serial over Lan (SoL) hack:
2274 Intel 8257x Gigabit ethernet chips have a
2275 16550 emulation, to be used for Serial Over Lan.
2276 Those chips take a longer time than a normal
2277 serial device to signalize that a transmission
2278 data was queued. Due to that, the above test generally
2279 fails. One solution would be to delay the reading of
2280 iir. However, this is not reliable, since the timeout
2281 is variable. So, let's just don't test if we receive
2282 TX irq. This way, we'll never enable UART_BUG_TXEN.
2283 */
e13cb72b 2284 if (up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2285 goto dont_test_tx_en;
2286
55d3b282
RK		 2287 /*
2288 * Do a quick test to see if we receive an
2289 * interrupt when we enable the TX irq.
2290 */
4fd996a1
PG		 2291 serial_port_out(port, UART_IER, UART_IER_THRI);
2292 lsr = serial_port_in(port, UART_LSR);
2293 iir = serial_port_in(port, UART_IIR);
2294 serial_port_out(port, UART_IER, 0);
55d3b282
RK		 2295
2296 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2297 if (!(up->bugs & UART_BUG_TXEN)) {
2298 up->bugs |= UART_BUG_TXEN;
55d3b282 2299 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2300 serial_index(port));
55d3b282
RK		 2301 }
2302 } else {
67f7654e 2303 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2304 }
2305
b6adea33 2306dont_test_tx_en:
dfe42443 2307 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 2308
ad4c2aa6
CM		 2309 /*
2310 * Clear the interrupt registers again for luck, and clear the
2311 * saved flags to avoid getting false values from polling
2312 * routines or the previous session.
2313 */
ca8bb4ae
SAS		 2314 serial_port_in(port, UART_LSR);
2315 serial_port_in(port, UART_RX);
4fd996a1
PG		 2316 serial_port_in(port, UART_IIR);
2317 serial_port_in(port, UART_MSR);
ad4c2aa6
CM		 2318 up->lsr_saved_flags = 0;
2319 up->msr_saved_flags = 0;
2320
9ee4b83e
HK		 2321 /*
2322 * Request DMA channels for both RX and TX.
2323 */
2324 if (up->dma) {
2325 retval = serial8250_request_dma(up);
2326 if (retval) {
2327 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2328 serial_index(port));
2329 up->dma = NULL;
2330 }
2331 }
2332
1da177e4
LT		 2333 /*
2334 * Finally, enable interrupts. Note: Modem status interrupts
2335 * are set via set_termios(), which will be occurring imminently
2336 * anyway, so we don't enable them here.
2337 */
2338 up->ier = UART_IER_RLSI | UART_IER_RDI;
4fd996a1 2339 serial_port_out(port, UART_IER, up->ier);
1da177e4 2340
dfe42443 2341 if (port->flags & UPF_FOURPORT) {
1da177e4
LT		 2342 unsigned int icp;
2343 /*
2344 * Enable interrupts on the AST Fourport board
2345 */
dfe42443 2346 icp = (port->iobase & 0xfe0) | 0x01f;
1da177e4 2347 outb_p(0x80, icp);
0d263a26 2348 inb_p(icp);
1da177e4 2349 }
d74d5d1b
SAS		 2350 retval = 0;
2351out:
2352 serial8250_rpm_put(up);
2353 return retval;
1da177e4 2354}
b99b121b 2355EXPORT_SYMBOL_GPL(serial8250_do_startup);
1da177e4 2356
b99b121b
SAS		 2357static int serial8250_startup(struct uart_port *port)
2358{
2359 if (port->startup)
2360 return port->startup(port);
2361 return serial8250_do_startup(port);
1da177e4
LT		 2362}
2363
b99b121b 2364void serial8250_do_shutdown(struct uart_port *port)
1da177e4 2365{
b1261c86 2366 struct uart_8250_port *up = up_to_u8250p(port);
1da177e4
LT		 2367 unsigned long flags;
2368
d74d5d1b 2369 serial8250_rpm_get(up);
1da177e4
LT		 2370 /*
2371 * Disable interrupts from this port
2372 */
2373 up->ier = 0;
4fd996a1 2374 serial_port_out(port, UART_IER, 0);
1da177e4 2375
9ee4b83e
HK		 2376 if (up->dma)
2377 serial8250_release_dma(up);
2378
dfe42443
PG		 2379 spin_lock_irqsave(&port->lock, flags);
2380 if (port->flags & UPF_FOURPORT) {
1da177e4 2381 /* reset interrupts on the AST Fourport board */
dfe42443
PG		 2382 inb((port->iobase & 0xfe0) | 0x1f);
2383 port->mctrl |= TIOCM_OUT1;
1da177e4 2384 } else
dfe42443 2385 port->mctrl &= ~TIOCM_OUT2;
1da177e4 2386
dfe42443
PG		 2387 serial8250_set_mctrl(port, port->mctrl);
2388 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 2389
2390 /*
2391 * Disable break condition and FIFOs
2392 */
4fd996a1
PG		 2393 serial_port_out(port, UART_LCR,
2394 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
1da177e4
LT		 2395 serial8250_clear_fifos(up);
2396
2397#ifdef CONFIG_SERIAL_8250_RSA
2398 /*
2399 * Reset the RSA board back to 115kbps compat mode.
2400 */
2401 disable_rsa(up);
2402#endif
2403
2404 /*
2405 * Read data port to reset things, and then unlink from
2406 * the IRQ chain.
2407 */
ca8bb4ae 2408 serial_port_in(port, UART_RX);
d74d5d1b 2409 serial8250_rpm_put(up);
1da177e4 2410
a4416cd1 2411 up->ops->release_irq(up);
1da177e4 2412}
b99b121b
SAS		 2413EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2414
2415static void serial8250_shutdown(struct uart_port *port)
2416{
2417 if (port->shutdown)
2418 port->shutdown(port);
2419 else
2420 serial8250_do_shutdown(port);
2421}
1da177e4 2422
06a4c710
PH		 2423/*
2424 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2425 * Calculate divisor with extra 4-bit fractional portion
2426 */
2427static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up,
2428 unsigned int baud,
2429 unsigned int *frac)
2430{
2431 struct uart_port *port = &up->port;
2432 unsigned int quot_16;
2433
2434 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud);
2435 *frac = quot_16 & 0x0f;
2436
2437 return quot_16 >> 4;
2438}
2439
2440static unsigned int serial8250_get_divisor(struct uart_8250_port *up,
2441 unsigned int baud,
2442 unsigned int *frac)
1da177e4 2443{
d1f2f219 2444 struct uart_port *port = &up->port;
1da177e4
LT		 2445 unsigned int quot;
2446
2447 /*
2448 * Handle magic divisors for baud rates above baud_base on
2449 * SMSC SuperIO chips.
06a4c710 2450 *
1da177e4
LT		 2451 */
2452 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2453 baud == (port->uartclk/4))
2454 quot = 0x8001;
2455 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2456 baud == (port->uartclk/8))
2457 quot = 0x8002;
06a4c710
PH		 2458 else if (up->port.type == PORT_XR17V35X)
2459 quot = xr17v35x_get_divisor(up, baud, frac);
1da177e4
LT		 2460 else
2461 quot = uart_get_divisor(port, baud);
2462
d1f2f219
PH		 2463 /*
2464 * Oxford Semi 952 rev B workaround
2465 */
2466 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2467 quot++;
2468
1da177e4
LT		 2469 return quot;
2470}
2471
0ec3f585
PH		 2472static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2473 tcflag_t c_cflag)
1da177e4 2474{
aef9a7bd 2475 unsigned char cval;
1da177e4 2476
0ec3f585 2477 switch (c_cflag & CSIZE) {
1da177e4 2478 case CS5:
0a8b80c5 2479 cval = UART_LCR_WLEN5;
1da177e4
LT		 2480 break;
2481 case CS6:
0a8b80c5 2482 cval = UART_LCR_WLEN6;
1da177e4
LT		 2483 break;
2484 case CS7:
0a8b80c5 2485 cval = UART_LCR_WLEN7;
1da177e4
LT		 2486 break;
2487 default:
2488 case CS8:
0a8b80c5 2489 cval = UART_LCR_WLEN8;
1da177e4
LT		 2490 break;
2491 }
2492
0ec3f585 2493 if (c_cflag & CSTOPB)
0a8b80c5 2494 cval |= UART_LCR_STOP;
0ec3f585 2495 if (c_cflag & PARENB) {
1da177e4 2496 cval |= UART_LCR_PARITY;
eb26dfe8 2497 if (up->bugs & UART_BUG_PARITY)
aef9a7bd 2498 up->fifo_bug = true;
eb26dfe8 2499 }
0ec3f585 2500 if (!(c_cflag & PARODD))
1da177e4
LT		 2501 cval |= UART_LCR_EPAR;
2502#ifdef CMSPAR
0ec3f585 2503 if (c_cflag & CMSPAR)
1da177e4
LT		 2504 cval |= UART_LCR_SPAR;
2505#endif
2506
0ec3f585
PH		 2507 return cval;
2508}
2509
eb1527a8 2510static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
06a4c710 2511 unsigned int quot, unsigned int quot_frac)
e72abd5d
PH		 2512{
2513 struct uart_8250_port *up = up_to_u8250p(port);
2514
2515 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2516 if (is_omap1510_8250(up)) {
2517 if (baud == 115200) {
2518 quot = 1;
2519 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2520 } else
2521 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2522 }
2523
2524 /*
2525 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2526 * otherwise just set DLAB
2527 */
2528 if (up->capabilities & UART_NATSEMI)
2529 serial_port_out(port, UART_LCR, 0xe0);
2530 else
2531 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2532
2533 serial_dl_write(up, quot);
2534
06a4c710
PH		 2535 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */
2536 if (up->port.type == PORT_XR17V35X)
2537 serial_port_out(port, 0x2, quot_frac);
e72abd5d
PH		 2538}
2539
0ec3f585
PH		 2540void
2541serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2542 struct ktermios *old)
2543{
2544 struct uart_8250_port *up = up_to_u8250p(port);
2545 unsigned char cval;
2546 unsigned long flags;
06a4c710 2547 unsigned int baud, quot, frac = 0;
0ec3f585
PH		 2548
2549 cval = serial8250_compute_lcr(up, termios->c_cflag);
2550
1da177e4
LT		 2551 /*
2552 * Ask the core to calculate the divisor for us.
2553 */
24d481ec
AV		 2554 baud = uart_get_baud_rate(port, termios, old,
2555 port->uartclk / 16 / 0xffff,
2556 port->uartclk / 16);
06a4c710 2557 quot = serial8250_get_divisor(up, baud, &frac);
1da177e4 2558
e9cef862
PH		 2559 /*
2560 * Ok, we're now changing the port state. Do it with
2561 * interrupts disabled.
2562 */
2563 serial8250_rpm_get(up);
2564 spin_lock_irqsave(&port->lock, flags);
2565
2566 up->lcr = cval; /* Save computed LCR */
2567
dfe42443 2568 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
aef9a7bd
YY		 2569 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2570 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2571 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2572 up->fcr |= UART_FCR_TRIGGER_1;
f9a9111b 2573 }
1da177e4
LT		 2574 }
2575
2576 /*
2577 * MCR-based auto flow control. When AFE is enabled, RTS will be
2578 * deasserted when the receive FIFO contains more characters than
2579 * the trigger, or the MCR RTS bit is cleared. In the case where
2580 * the remote UART is not using CTS auto flow control, we must
2581 * have sufficient FIFO entries for the latency of the remote
a6eec92e 2582 * UART to respond. IOW, at least 32 bytes of FIFO.
1da177e4 2583 */
a6eec92e 2584 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
1da177e4
LT		 2585 up->mcr &= ~UART_MCR_AFE;
2586 if (termios->c_cflag & CRTSCTS)
2587 up->mcr |= UART_MCR_AFE;
2588 }
2589
1da177e4
LT		 2590 /*
2591 * Update the per-port timeout.
2592 */
2593 uart_update_timeout(port, termios->c_cflag, baud);
2594
dfe42443 2595 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1da177e4 2596 if (termios->c_iflag & INPCK)
dfe42443 2597 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
ef8b9ddc 2598 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
dfe42443 2599 port->read_status_mask |= UART_LSR_BI;
1da177e4
LT		 2600
2601 /*
2602 * Characteres to ignore
2603 */
dfe42443 2604 port->ignore_status_mask = 0;
1da177e4 2605 if (termios->c_iflag & IGNPAR)
dfe42443 2606 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1da177e4 2607 if (termios->c_iflag & IGNBRK) {
dfe42443 2608 port->ignore_status_mask |= UART_LSR_BI;
1da177e4
LT		 2609 /*
2610 * If we're ignoring parity and break indicators,
2611 * ignore overruns too (for real raw support).
2612 */
2613 if (termios->c_iflag & IGNPAR)
dfe42443 2614 port->ignore_status_mask |= UART_LSR_OE;
1da177e4
LT		 2615 }
2616
2617 /*
2618 * ignore all characters if CREAD is not set
2619 */
2620 if ((termios->c_cflag & CREAD) == 0)
dfe42443 2621 port->ignore_status_mask |= UART_LSR_DR;
1da177e4
LT		 2622
2623 /*
2624 * CTS flow control flag and modem status interrupts
2625 */
f8b372a1 2626 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2627 if (!(up->bugs & UART_BUG_NOMSR) &&
2628 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2629 up->ier |= UART_IER_MSI;
2630 if (up->capabilities & UART_CAP_UUE)
4539c24f
SW		 2631 up->ier |= UART_IER_UUE;
2632 if (up->capabilities & UART_CAP_RTOIE)
2633 up->ier |= UART_IER_RTOIE;
1da177e4 2634
4fd996a1 2635 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 2636
2637 if (up->capabilities & UART_CAP_EFR) {
2638 unsigned char efr = 0;
2639 /*
2640 * TI16C752/Startech hardware flow control. FIXME:
2641 * - TI16C752 requires control thresholds to be set.
2642 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2643 */
2644 if (termios->c_cflag & CRTSCTS)
2645 efr |= UART_EFR_CTS;
2646
4fd996a1 2647 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
dfe42443 2648 if (port->flags & UPF_EXAR_EFR)
4fd996a1 2649 serial_port_out(port, UART_XR_EFR, efr);
06315348 2650 else
4fd996a1 2651 serial_port_out(port, UART_EFR, efr);
1da177e4
LT		 2652 }
2653
06a4c710 2654 serial8250_set_divisor(port, baud, quot, frac);
45a7bd63 2655
1da177e4
LT		 2656 /*
2657 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2658 * is written without DLAB set, this mode will be disabled.
2659 */
dfe42443 2660 if (port->type == PORT_16750)
aef9a7bd 2661 serial_port_out(port, UART_FCR, up->fcr);
1da177e4 2662
e72abd5d 2663 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
dfe42443 2664 if (port->type != PORT_16750) {
4fd996a1 2665 /* emulated UARTs (Lucent Venus 167x) need two steps */
aef9a7bd 2666 if (up->fcr & UART_FCR_ENABLE_FIFO)
4fd996a1 2667 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
aef9a7bd 2668 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
1da177e4 2669 }
dfe42443
PG		 2670 serial8250_set_mctrl(port, port->mctrl);
2671 spin_unlock_irqrestore(&port->lock, flags);
d74d5d1b
SAS		 2672 serial8250_rpm_put(up);
2673
e991a2bd
AC		 2674 /* Don't rewrite B0 */
2675 if (tty_termios_baud_rate(termios))
2676 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4 2677}
235dae5d
PL		 2678EXPORT_SYMBOL(serial8250_do_set_termios);
2679
2680static void
2681serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2682 struct ktermios *old)
2683{
2684 if (port->set_termios)
2685 port->set_termios(port, termios, old);
2686 else
2687 serial8250_do_set_termios(port, termios, old);
2688}
1da177e4 2689
dc77f161 2690static void
732a84a0 2691serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
dc77f161 2692{
732a84a0 2693 if (termios->c_line == N_PPS) {
dc77f161 2694 port->flags |= UPF_HARDPPS_CD;
d41510ce 2695 spin_lock_irq(&port->lock);
dc77f161 2696 serial8250_enable_ms(port);
d41510ce 2697 spin_unlock_irq(&port->lock);
cab68f89 2698 } else {
dc77f161 2699 port->flags &= ~UPF_HARDPPS_CD;
cab68f89
PH		 2700 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2701 spin_lock_irq(&port->lock);
2702 serial8250_disable_ms(port);
2703 spin_unlock_irq(&port->lock);
2704 }
2705 }
dc77f161
RG		 2706}
2707
c161afe9
ML		 2708
2709void serial8250_do_pm(struct uart_port *port, unsigned int state,
2710 unsigned int oldstate)
1da177e4 2711{
b1261c86 2712 struct uart_8250_port *p = up_to_u8250p(port);
1da177e4
LT		 2713
2714 serial8250_set_sleep(p, state != 0);
c161afe9
ML		 2715}
2716EXPORT_SYMBOL(serial8250_do_pm);
1da177e4 2717
c161afe9
ML		 2718static void
2719serial8250_pm(struct uart_port *port, unsigned int state,
2720 unsigned int oldstate)
2721{
2722 if (port->pm)
2723 port->pm(port, state, oldstate);
2724 else
2725 serial8250_do_pm(port, state, oldstate);
1da177e4
LT		 2726}
2727
f2eda27d
RK		 2728static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2729{
ee97d0e3
MR		 2730 if (pt->port.mapsize)
2731 return pt->port.mapsize;
9b8777e3
JC		 2732 if (pt->port.iotype == UPIO_AU) {
2733 if (pt->port.type == PORT_RT2880)
2734 return 0x100;
b2b13cdf 2735 return 0x1000;
9b8777e3 2736 }
54ec52b6 2737 if (is_omap1_8250(pt))
f2eda27d 2738 return 0x16 << pt->port.regshift;
54ec52b6 2739
f2eda27d
RK		 2740 return 8 << pt->port.regshift;
2741}
2742
1da177e4
LT		 2743/*
2744 * Resource handling.
2745 */
2746static int serial8250_request_std_resource(struct uart_8250_port *up)
2747{
f2eda27d 2748 unsigned int size = serial8250_port_size(up);
dfe42443 2749 struct uart_port *port = &up->port;
1da177e4
LT		 2750 int ret = 0;
2751
dfe42443 2752 switch (port->iotype) {
85835f44 2753 case UPIO_AU:
0b30d668
SS		 2754 case UPIO_TSI:
2755 case UPIO_MEM32:
c627f2ce 2756 case UPIO_MEM32BE:
1da177e4 2757 case UPIO_MEM:
dfe42443 2758 if (!port->mapbase)
1da177e4
LT		 2759 break;
2760
dfe42443 2761 if (!request_mem_region(port->mapbase, size, "serial")) {
1da177e4
LT		 2762 ret = -EBUSY;
2763 break;
2764 }
2765
dfe42443
PG		 2766 if (port->flags & UPF_IOREMAP) {
2767 port->membase = ioremap_nocache(port->mapbase, size);
2768 if (!port->membase) {
2769 release_mem_region(port->mapbase, size);
1da177e4
LT		 2770 ret = -ENOMEM;
2771 }
2772 }
2773 break;
2774
2775 case UPIO_HUB6:
2776 case UPIO_PORT:
dfe42443 2777 if (!request_region(port->iobase, size, "serial"))
1da177e4
LT		 2778 ret = -EBUSY;
2779 break;
2780 }
2781 return ret;
2782}
2783
2784static void serial8250_release_std_resource(struct uart_8250_port *up)
2785{
f2eda27d 2786 unsigned int size = serial8250_port_size(up);
dfe42443 2787 struct uart_port *port = &up->port;
1da177e4 2788
dfe42443 2789 switch (port->iotype) {
85835f44 2790 case UPIO_AU:
0b30d668
SS		 2791 case UPIO_TSI:
2792 case UPIO_MEM32:
c627f2ce 2793 case UPIO_MEM32BE:
1da177e4 2794 case UPIO_MEM:
dfe42443 2795 if (!port->mapbase)
1da177e4
LT		 2796 break;
2797
dfe42443
PG		 2798 if (port->flags & UPF_IOREMAP) {
2799 iounmap(port->membase);
2800 port->membase = NULL;
1da177e4
LT		 2801 }
2802
dfe42443 2803 release_mem_region(port->mapbase, size);
1da177e4
LT		 2804 break;
2805
2806 case UPIO_HUB6:
2807 case UPIO_PORT:
dfe42443 2808 release_region(port->iobase, size);
1da177e4
LT		 2809 break;
2810 }
2811}
2812
cd52b759 2813#ifdef CONFIG_SERIAL_8250_RSA
1da177e4
LT		 2814static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2815{
2816 unsigned long start = UART_RSA_BASE << up->port.regshift;
2817 unsigned int size = 8 << up->port.regshift;
dfe42443 2818 struct uart_port *port = &up->port;
0b30d668 2819 int ret = -EINVAL;
1da177e4 2820
dfe42443 2821 switch (port->iotype) {
1da177e4
LT		 2822 case UPIO_HUB6:
2823 case UPIO_PORT:
dfe42443 2824 start += port->iobase;
0b30d668
SS		 2825 if (request_region(start, size, "serial-rsa"))
2826 ret = 0;
2827 else
1da177e4
LT		 2828 ret = -EBUSY;
2829 break;
2830 }
2831
2832 return ret;
2833}
2834
2835static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2836{
2837 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2838 unsigned int size = 8 << up->port.regshift;
dfe42443 2839 struct uart_port *port = &up->port;
1da177e4 2840
dfe42443 2841 switch (port->iotype) {
1da177e4
LT		 2842 case UPIO_HUB6:
2843 case UPIO_PORT:
dfe42443 2844 release_region(port->iobase + offset, size);
1da177e4
LT		 2845 break;
2846 }
2847}
cd52b759 2848#endif
1da177e4
LT		 2849
2850static void serial8250_release_port(struct uart_port *port)
2851{
b1261c86 2852 struct uart_8250_port *up = up_to_u8250p(port);
1da177e4
LT		 2853
2854 serial8250_release_std_resource(up);
1da177e4
LT		 2855}
2856
2857static int serial8250_request_port(struct uart_port *port)
2858{
b1261c86 2859 struct uart_8250_port *up = up_to_u8250p(port);
65ecc9c0
SY		 2860 int ret;
2861
2862 if (port->type == PORT_8250_CIR)
2863 return -ENODEV;
1da177e4
LT		 2864
2865 ret = serial8250_request_std_resource(up);
1da177e4
LT		 2866
2867 return ret;
2868}
2869
aef9a7bd
YY		 2870static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2871{
2872 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2873 unsigned char bytes;
2874
2875 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
2876
2877 return bytes ? bytes : -EOPNOTSUPP;
2878}
2879
2880static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
2881{
2882 const struct serial8250_config *conf_type = &uart_config[up->port.type];
2883 int i;
2884
2885 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
2886 return -EOPNOTSUPP;
2887
2888 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
2889 if (bytes < conf_type->rxtrig_bytes[i])
2890 /* Use the nearest lower value */
2891 return (--i) << UART_FCR_R_TRIG_SHIFT;
2892 }
2893
2894 return UART_FCR_R_TRIG_11;
2895}
2896
2897static int do_get_rxtrig(struct tty_port *port)
2898{
2899 struct uart_state *state = container_of(port, struct uart_state, port);
2900 struct uart_port *uport = state->uart_port;
2901 struct uart_8250_port *up =
2902 container_of(uport, struct uart_8250_port, port);
2903
2904 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
2905 return -EINVAL;
2906
2907 return fcr_get_rxtrig_bytes(up);
2908}
2909
2910static int do_serial8250_get_rxtrig(struct tty_port *port)
2911{
2912 int rxtrig_bytes;
2913
2914 mutex_lock(&port->mutex);
2915 rxtrig_bytes = do_get_rxtrig(port);
2916 mutex_unlock(&port->mutex);
2917
2918 return rxtrig_bytes;
2919}
2920
2921static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev,
2922 struct device_attribute *attr, char *buf)
2923{
2924 struct tty_port *port = dev_get_drvdata(dev);
2925 int rxtrig_bytes;
2926
2927 rxtrig_bytes = do_serial8250_get_rxtrig(port);
2928 if (rxtrig_bytes < 0)
2929 return rxtrig_bytes;
2930
2931 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes);
2932}
2933
2934static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
2935{
2936 struct uart_state *state = container_of(port, struct uart_state, port);
2937 struct uart_port *uport = state->uart_port;
2938 struct uart_8250_port *up =
2939 container_of(uport, struct uart_8250_port, port);
2940 int rxtrig;
2941
2942 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
2943 up->fifo_bug)
2944 return -EINVAL;
2945
2946 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
2947 if (rxtrig < 0)
2948 return rxtrig;
2949
2950 serial8250_clear_fifos(up);
2951 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2952 up->fcr |= (unsigned char)rxtrig;
2953 serial_out(up, UART_FCR, up->fcr);
2954 return 0;
2955}
2956
2957static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
2958{
2959 int ret;
2960
2961 mutex_lock(&port->mutex);
2962 ret = do_set_rxtrig(port, bytes);
2963 mutex_unlock(&port->mutex);
2964
2965 return ret;
2966}
2967
2968static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev,
2969 struct device_attribute *attr, const char *buf, size_t count)
2970{
2971 struct tty_port *port = dev_get_drvdata(dev);
2972 unsigned char bytes;
2973 int ret;
2974
2975 if (!count)
2976 return -EINVAL;
2977
2978 ret = kstrtou8(buf, 10, &bytes);
2979 if (ret < 0)
2980 return ret;
2981
2982 ret = do_serial8250_set_rxtrig(port, bytes);
2983 if (ret < 0)
2984 return ret;
2985
2986 return count;
2987}
2988
2989static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP,
2990 serial8250_get_attr_rx_trig_bytes,
2991 serial8250_set_attr_rx_trig_bytes);
2992
2993static struct attribute *serial8250_dev_attrs[] = {
2994 &dev_attr_rx_trig_bytes.attr,
2995 NULL,
2996 };
2997
2998static struct attribute_group serial8250_dev_attr_group = {
2999 .attrs = serial8250_dev_attrs,
3000 };
3001
3002static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3003{
3004 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3005
3006 if (conf_type->rxtrig_bytes[0])
3007 up->port.attr_group = &serial8250_dev_attr_group;
3008}
3009
1da177e4
LT		 3010static void serial8250_config_port(struct uart_port *port, int flags)
3011{
b1261c86 3012 struct uart_8250_port *up = up_to_u8250p(port);
1da177e4
LT		 3013 int ret;
3014
65ecc9c0
SY		 3015 if (port->type == PORT_8250_CIR)
3016 return;
3017
1da177e4
LT		 3018 /*
3019 * Find the region that we can probe for. This in turn
3020 * tells us whether we can probe for the type of port.
3021 */
3022 ret = serial8250_request_std_resource(up);
3023 if (ret < 0)
3024 return;
3025
dfe42443 3026 if (port->iotype != up->cur_iotype)
b8e7e40a
AC		 3027 set_io_from_upio(port);
3028
1da177e4 3029 if (flags & UART_CONFIG_TYPE)
40375393 3030 autoconfig(up);
b2b13cdf 3031
b2b13cdf 3032 /* if access method is AU, it is a 16550 with a quirk */
dfe42443 3033 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
b2b13cdf 3034 up->bugs |= UART_BUG_NOMSR;
b2b13cdf 3035
3685f19e
SW		 3036 /* HW bugs may trigger IRQ while IIR == NO_INT */
3037 if (port->type == PORT_TEGRA)
3038 up->bugs |= UART_BUG_NOMSR;
3039
dfe42443 3040 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
1da177e4
LT		 3041 autoconfig_irq(up);
3042
dfe42443 3043 if (port->type == PORT_UNKNOWN)
1da177e4 3044 serial8250_release_std_resource(up);
dc96efb7
MS		 3045
3046 /* Fixme: probably not the best place for this */
30fa96a3
MS		 3047 if ((port->type == PORT_XR17V35X) ||
3048 (port->type == PORT_XR17D15X))
dc96efb7 3049 port->handle_irq = exar_handle_irq;
aef9a7bd
YY		 3050
3051 register_dev_spec_attr_grp(up);
3052 up->fcr = uart_config[up->port.type].fcr;
1da177e4
LT		 3053}
3054
3055static int
3056serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3057{
a62c4133 3058 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 3059 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3060 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3061 ser->type == PORT_STARTECH)
3062 return -EINVAL;
3063 return 0;
3064}
3065
3066static const char *
3067serial8250_type(struct uart_port *port)
3068{
3069 int type = port->type;
3070
3071 if (type >= ARRAY_SIZE(uart_config))
3072 type = 0;
3073 return uart_config[type].name;
3074}
3075
72a33aad 3076static const struct uart_ops serial8250_pops = {
1da177e4
LT		 3077 .tx_empty = serial8250_tx_empty,
3078 .set_mctrl = serial8250_set_mctrl,
3079 .get_mctrl = serial8250_get_mctrl,
3080 .stop_tx = serial8250_stop_tx,
3081 .start_tx = serial8250_start_tx,
234abab1
SAS		 3082 .throttle = serial8250_throttle,
3083 .unthrottle = serial8250_unthrottle,
1da177e4
LT		 3084 .stop_rx = serial8250_stop_rx,
3085 .enable_ms = serial8250_enable_ms,
3086 .break_ctl = serial8250_break_ctl,
3087 .startup = serial8250_startup,
3088 .shutdown = serial8250_shutdown,
3089 .set_termios = serial8250_set_termios,
dc77f161 3090 .set_ldisc = serial8250_set_ldisc,
1da177e4
LT		 3091 .pm = serial8250_pm,
3092 .type = serial8250_type,
3093 .release_port = serial8250_release_port,
3094 .request_port = serial8250_request_port,
3095 .config_port = serial8250_config_port,
3096 .verify_port = serial8250_verify_port,
f2d937f3
JW		 3097#ifdef CONFIG_CONSOLE_POLL
3098 .poll_get_char = serial8250_get_poll_char,
3099 .poll_put_char = serial8250_put_poll_char,
3100#endif
1da177e4
LT		 3101};
3102
40375393
PH		 3103static const struct uart_ops *base_ops;
3104static struct uart_ops univ8250_port_ops;
3105
a4416cd1
PH		 3106static const struct uart_8250_ops univ8250_driver_ops = {
3107 .setup_irq = univ8250_setup_irq,
3108 .release_irq = univ8250_release_irq,
3109};
3110
1da177e4
LT		 3111static struct uart_8250_port serial8250_ports[UART_NR];
3112
ae14a795
SAS		 3113/**
3114 * serial8250_get_port - retrieve struct uart_8250_port
3115 * @line: serial line number
3116 *
3117 * This function retrieves struct uart_8250_port for the specific line.
3118 * This struct *must* *not* be used to perform a 8250 or serial core operation
3119 * which is not accessible otherwise. Its only purpose is to make the struct
3120 * accessible to the runtime-pm callbacks for context suspend/restore.
3121 * The lock assumption made here is none because runtime-pm suspend/resume
3122 * callbacks should not be invoked if there is any operation performed on the
3123 * port.
3124 */
3125struct uart_8250_port *serial8250_get_port(int line)
3126{
3127 return &serial8250_ports[line];
3128}
3129EXPORT_SYMBOL_GPL(serial8250_get_port);
3130
af7f3743
AC		 3131static void (*serial8250_isa_config)(int port, struct uart_port *up,
3132 unsigned short *capabilities);
3133
3134void serial8250_set_isa_configurator(
3135 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
3136{
3137 serial8250_isa_config = v;
3138}
3139EXPORT_SYMBOL(serial8250_set_isa_configurator);
3140
0a16e2c1
PH		 3141static void serial8250_init_port(struct uart_8250_port *up)
3142{
3143 struct uart_port *port = &up->port;
3144
3145 spin_lock_init(&port->lock);
3146 port->ops = &serial8250_pops;
3147
3148 up->cur_iotype = 0xFF;
3149}
3150
1a53e079
PH		 3151static void serial8250_set_defaults(struct uart_8250_port *up)
3152{
3153 struct uart_port *port = &up->port;
3154
afd483bd
PH		 3155 if (up->port.flags & UPF_FIXED_TYPE) {
3156 unsigned int type = up->port.type;
3157
3158 if (!up->port.fifosize)
3159 up->port.fifosize = uart_config[type].fifo_size;
3160 if (!up->tx_loadsz)
3161 up->tx_loadsz = uart_config[type].tx_loadsz;
3162 if (!up->capabilities)
3163 up->capabilities = uart_config[type].flags;
3164 }
3165
1a53e079 3166 set_io_from_upio(port);
d53e1428
PH		 3167
3168 /* default dma handlers */
3169 if (up->dma) {
3170 if (!up->dma->tx_dma)
3171 up->dma->tx_dma = serial8250_tx_dma;
3172 if (!up->dma->rx_dma)
3173 up->dma->rx_dma = serial8250_rx_dma;
3174 }
1a53e079
PH		 3175}
3176
40375393
PH		 3177#ifdef CONFIG_SERIAL_8250_RSA
3178
3179static void univ8250_config_port(struct uart_port *port, int flags)
3180{
3181 struct uart_8250_port *up = up_to_u8250p(port);
3182
3183 up->probe &= ~UART_PROBE_RSA;
3184 if (port->type == PORT_RSA) {
3185 if (serial8250_request_rsa_resource(up) == 0)
3186 up->probe |= UART_PROBE_RSA;
3187 } else if (flags & UART_CONFIG_TYPE) {
3188 int i;
3189
3190 for (i = 0; i < probe_rsa_count; i++) {
3191 if (probe_rsa[i] == up->port.iobase) {
3192 if (serial8250_request_rsa_resource(up) == 0)
3193 up->probe |= UART_PROBE_RSA;
3194 break;
3195 }
3196 }
3197 }
3198
3199 base_ops->config_port(port, flags);
3200
3201 if (port->type != PORT_RSA && up->probe & UART_PROBE_RSA)
3202 serial8250_release_rsa_resource(up);
3203}
3204
3205static int univ8250_request_port(struct uart_port *port)
3206{
3207 struct uart_8250_port *up = up_to_u8250p(port);
3208 int ret;
3209
3210 ret = base_ops->request_port(port);
3211 if (ret == 0 && port->type == PORT_RSA) {
3212 ret = serial8250_request_rsa_resource(up);
3213 if (ret < 0)
3214 base_ops->release_port(port);
3215 }
3216
3217 return ret;
3218}
3219
3220static void univ8250_release_port(struct uart_port *port)
3221{
3222 struct uart_8250_port *up = up_to_u8250p(port);
3223
3224 if (port->type == PORT_RSA)
3225 serial8250_release_rsa_resource(up);
3226 base_ops->release_port(port);
3227}
3228
3229static void univ8250_rsa_support(struct uart_ops *ops)
3230{
3231 ops->config_port = univ8250_config_port;
3232 ops->request_port = univ8250_request_port;
3233 ops->release_port = univ8250_release_port;
3234}
3235
3236#else
3237#define univ8250_rsa_support(x) do { } while (0)
3238#endif /* CONFIG_SERIAL_8250_RSA */
3239
1da177e4
LT		 3240static void __init serial8250_isa_init_ports(void)
3241{
3242 struct uart_8250_port *up;
3243 static int first = 1;
4c0ebb80 3244 int i, irqflag = 0;
1da177e4
LT		 3245
3246 if (!first)
3247 return;
3248 first = 0;
3249
835d844d
SY		 3250 if (nr_uarts > UART_NR)
3251 nr_uarts = UART_NR;
3252
317a6842 3253 for (i = 0; i < nr_uarts; i++) {
1da177e4 3254 struct uart_8250_port *up = &serial8250_ports[i];
dfe42443 3255 struct uart_port *port = &up->port;
1da177e4 3256
dfe42443 3257 port->line = i;
0a16e2c1 3258 serial8250_init_port(up);
40375393
PH		 3259 if (!base_ops)
3260 base_ops = port->ops;
3261 port->ops = &univ8250_port_ops;
1da177e4
LT		 3262
3263 init_timer(&up->timer);
3264 up->timer.function = serial8250_timeout;
3265
a4416cd1
PH		 3266 up->ops = &univ8250_driver_ops;
3267
1da177e4
LT		 3268 /*
3269 * ALPHA_KLUDGE_MCR needs to be killed.
3270 */
3271 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
3272 up->mcr_force = ALPHA_KLUDGE_MCR;
1da177e4
LT		 3273 }
3274
40375393
PH		 3275 /* chain base port ops to support Remote Supervisor Adapter */
3276 univ8250_port_ops = *base_ops;
3277 univ8250_rsa_support(&univ8250_port_ops);
3278
4c0ebb80
AGR		 3279 if (share_irqs)
3280 irqflag = IRQF_SHARED;
3281
44454bcd 3282 for (i = 0, up = serial8250_ports;
a61c2d78 3283 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4 3284 i++, up++) {
dfe42443
PG		 3285 struct uart_port *port = &up->port;
3286
3287 port->iobase = old_serial_port[i].port;
3288 port->irq = irq_canonicalize(old_serial_port[i].irq);
3289 port->irqflags = old_serial_port[i].irqflags;
3290 port->uartclk = old_serial_port[i].baud_base * 16;
3291 port->flags = old_serial_port[i].flags;
3292 port->hub6 = old_serial_port[i].hub6;
3293 port->membase = old_serial_port[i].iomem_base;
3294 port->iotype = old_serial_port[i].io_type;
3295 port->regshift = old_serial_port[i].iomem_reg_shift;
1a53e079
PH		 3296 serial8250_set_defaults(up);
3297
dfe42443 3298 port->irqflags |= irqflag;
af7f3743
AC		 3299 if (serial8250_isa_config != NULL)
3300 serial8250_isa_config(i, &up->port, &up->capabilities);
1da177e4
LT		 3301 }
3302}
3303
3304static void __init
3305serial8250_register_ports(struct uart_driver *drv, struct device *dev)
3306{
3307 int i;
3308
b8e7e40a
AC		 3309 for (i = 0; i < nr_uarts; i++) {
3310 struct uart_8250_port *up = &serial8250_ports[i];
b8e7e40a 3311
835d844d
SY		 3312 if (up->port.dev)
3313 continue;
1da177e4
LT		 3314
3315 up->port.dev = dev;
b5d228cc 3316
e13cb72b
PH		 3317 if (skip_txen_test)
3318 up->port.flags |= UPF_NO_TXEN_TEST;
3319
1da177e4
LT		 3320 uart_add_one_port(drv, &up->port);
3321 }
3322}
3323
3324#ifdef CONFIG_SERIAL_8250_CONSOLE
3325
d358788f
RK		 3326static void serial8250_console_putchar(struct uart_port *port, int ch)
3327{
b1261c86 3328 struct uart_8250_port *up = up_to_u8250p(port);
d358788f
RK		 3329
3330 wait_for_xmitr(up, UART_LSR_THRE);
4fd996a1 3331 serial_port_out(port, UART_TX, ch);
d358788f
RK		 3332}
3333
1da177e4
LT		 3334/*
3335 * Print a string to the serial port trying not to disturb
3336 * any possible real use of the port...
3337 *
3338 * The console_lock must be held when we get here.
3339 */
6e281571
PH		 3340static void serial8250_console_write(struct uart_8250_port *up, const char *s,
3341 unsigned int count)
1da177e4 3342{
dfe42443 3343 struct uart_port *port = &up->port;
d8a5a8d7 3344 unsigned long flags;
1da177e4 3345 unsigned int ier;
d8a5a8d7 3346 int locked = 1;
1da177e4 3347
78512ece
AM		 3348 touch_nmi_watchdog();
3349
d74d5d1b
SAS		 3350 serial8250_rpm_get(up);
3351
6fad18fa
RV		 3352 if (port->sysrq)
3353 locked = 0;
3354 else if (oops_in_progress)
ebade5e8
IM		 3355 locked = spin_trylock_irqsave(&port->lock, flags);
3356 else
3357 spin_lock_irqsave(&port->lock, flags);
d8a5a8d7 3358
1da177e4 3359 /*
dc7bf130 3360 * First save the IER then disable the interrupts
1da177e4 3361 */
4fd996a1 3362 ier = serial_port_in(port, UART_IER);
1da177e4
LT		 3363
3364 if (up->capabilities & UART_CAP_UUE)
4fd996a1 3365 serial_port_out(port, UART_IER, UART_IER_UUE);
1da177e4 3366 else
4fd996a1 3367 serial_port_out(port, UART_IER, 0);
1da177e4 3368
4516d50a
PH		 3369 /* check scratch reg to see if port powered off during system sleep */
3370 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3371 struct ktermios termios;
3372 unsigned int baud, quot, frac = 0;
3373
3374 termios.c_cflag = port->cons->cflag;
3375 if (port->state->port.tty && termios.c_cflag == 0)
3376 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3377
3378 baud = uart_get_baud_rate(port, &termios, NULL,
3379 port->uartclk / 16 / 0xffff,
3380 port->uartclk / 16);
3381 quot = serial8250_get_divisor(up, baud, &frac);
3382
3383 serial8250_set_divisor(port, baud, quot, frac);
3384 serial_port_out(port, UART_LCR, up->lcr);
3385 serial_port_out(port, UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
3386
3387 up->canary = 0;
3388 }
3389
dfe42443 3390 uart_console_write(port, s, count, serial8250_console_putchar);
1da177e4
LT		 3391
3392 /*
3393 * Finally, wait for transmitter to become empty
3394 * and restore the IER
3395 */
f91a3715 3396 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 3397 serial_port_out(port, UART_IER, ier);
d8a5a8d7 3398
ad4c2aa6
CM		 3399 /*
3400 * The receive handling will happen properly because the
3401 * receive ready bit will still be set; it is not cleared
3402 * on read. However, modem control will not, we must
3403 * call it if we have saved something in the saved flags
3404 * while processing with interrupts off.
3405 */
3406 if (up->msr_saved_flags)
3986fb2b 3407 serial8250_modem_status(up);
ad4c2aa6 3408
d8a5a8d7 3409 if (locked)
ebade5e8 3410 spin_unlock_irqrestore(&port->lock, flags);
d74d5d1b 3411 serial8250_rpm_put(up);
1da177e4
LT		 3412}
3413
6e281571
PH		 3414static void univ8250_console_write(struct console *co, const char *s,
3415 unsigned int count)
3416{
3417 struct uart_8250_port *up = &serial8250_ports[co->index];
3418
3419 serial8250_console_write(up, s, count);
3420}
3421
87515772
PH		 3422static unsigned int probe_baud(struct uart_port *port)
3423{
3424 unsigned char lcr, dll, dlm;
3425 unsigned int quot;
3426
3427 lcr = serial_port_in(port, UART_LCR);
3428 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3429 dll = serial_port_in(port, UART_DLL);
3430 dlm = serial_port_in(port, UART_DLM);
3431 serial_port_out(port, UART_LCR, lcr);
3432
3433 quot = (dlm << 8) | dll;
3434 return (port->uartclk / 16) / quot;
3435}
3436
3437static int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
1da177e4 3438{
1da177e4
LT		 3439 int baud = 9600;
3440 int bits = 8;
3441 int parity = 'n';
3442 int flow = 'n';
3443
6e281571
PH		 3444 if (!port->iobase && !port->membase)
3445 return -ENODEV;
3446
3447 if (options)
3448 uart_parse_options(options, &baud, &parity, &bits, &flow);
87515772
PH		 3449 else if (probe)
3450 baud = probe_baud(port);
6e281571
PH		 3451
3452 return uart_set_options(port, port->cons, baud, parity, bits, flow);
3453}
3454
3455static int univ8250_console_setup(struct console *co, char *options)
3456{
87515772 3457 struct uart_port *port;
6e281571 3458
1da177e4
LT		 3459 /*
3460 * Check whether an invalid uart number has been specified, and
3461 * if so, search for the first available port that does have
3462 * console support.
3463 */
317a6842 3464 if (co->index >= nr_uarts)
1da177e4 3465 co->index = 0;
87515772 3466 port = &serial8250_ports[co->index].port;
6e281571 3467 /* link port to console */
87515772 3468 port->cons = co;
1da177e4 3469
87515772 3470 return serial8250_console_setup(port, options, false);
1da177e4
LT		 3471}
3472
c7cef0a8 3473/**
6e281571 3474 * univ8250_console_match - non-standard console matching
c7cef0a8
PH		 3475 * @co: registering console
3476 * @name: name from console command line
3477 * @idx: index from console command line
3478 * @options: ptr to option string from console command line
3479 *
3480 * Only attempts to match console command lines of the form:
ca782f16
PH		 3481 * console=uart[8250],io|mmio|mmio32,<addr>[,<options>]
3482 * console=uart[8250],0x<addr>[,<options>]
c7cef0a8
PH		 3483 * This form is used to register an initial earlycon boot console and
3484 * replace it with the serial8250_console at 8250 driver init.
3485 *
3486 * Performs console setup for a match (as required by interface)
ca782f16 3487 * If no <options> are specified, then assume the h/w is already setup.
c7cef0a8
PH		 3488 *
3489 * Returns 0 if console matches; otherwise non-zero to use default matching
3490 */
6e281571
PH		 3491static int univ8250_console_match(struct console *co, char *name, int idx,
3492 char *options)
18a8bd94 3493{
c7cef0a8
PH		 3494 char match[] = "uart"; /* 8250-specific earlycon name */
3495 unsigned char iotype;
3496 unsigned long addr;
3497 int i;
3498
3499 if (strncmp(name, match, 4) != 0)
3500 return -ENODEV;
3501
3502 if (uart_parse_earlycon(options, &iotype, &addr, &options))
3503 return -ENODEV;
3504
3505 /* try to match the port specified on the command line */
3506 for (i = 0; i < nr_uarts; i++) {
3507 struct uart_port *port = &serial8250_ports[i].port;
3508
3509 if (port->iotype != iotype)
3510 continue;
3511 if ((iotype == UPIO_MEM || iotype == UPIO_MEM32) &&
3512 (port->mapbase != addr))
3513 continue;
3514 if (iotype == UPIO_PORT && port->iobase != addr)
3515 continue;
3516
3517 co->index = i;
87515772
PH		 3518 port->cons = co;
3519 return serial8250_console_setup(port, options, true);
c7cef0a8
PH		 3520 }
3521
3522 return -ENODEV;
18a8bd94
YL		 3523}
3524
6e281571 3525static struct console univ8250_console = {
1da177e4 3526 .name = "ttyS",
6e281571 3527 .write = univ8250_console_write,
1da177e4 3528 .device = uart_console_device,
6e281571
PH		 3529 .setup = univ8250_console_setup,
3530 .match = univ8250_console_match,
a80c49db 3531 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 3532 .index = -1,
3533 .data = &serial8250_reg,
3534};
3535
6e281571 3536static int __init univ8250_console_init(void)
1da177e4 3537{
59cfc45f
JK		 3538 if (nr_uarts == 0)
3539 return -ENODEV;
3540
1da177e4 3541 serial8250_isa_init_ports();
6e281571 3542 register_console(&univ8250_console);
1da177e4
LT		 3543 return 0;
3544}
6e281571 3545console_initcall(univ8250_console_init);
1da177e4 3546
6e281571 3547#define SERIAL8250_CONSOLE &univ8250_console
1da177e4
LT		 3548#else
3549#define SERIAL8250_CONSOLE NULL
3550#endif
3551
3552static struct uart_driver serial8250_reg = {
3553 .owner = THIS_MODULE,
3554 .driver_name = "serial",
1da177e4
LT		 3555 .dev_name = "ttyS",
3556 .major = TTY_MAJOR,
3557 .minor = 64,
1da177e4
LT		 3558 .cons = SERIAL8250_CONSOLE,
3559};
3560
d856c666
RK		 3561/*
3562 * early_serial_setup - early registration for 8250 ports
3563 *
3564 * Setup an 8250 port structure prior to console initialisation. Use
3565 * after console initialisation will cause undefined behaviour.
3566 */
1da177e4
LT		 3567int __init early_serial_setup(struct uart_port *port)
3568{
b430428a
DD		 3569 struct uart_port *p;
3570
59cfc45f 3571 if (port->line >= ARRAY_SIZE(serial8250_ports) || nr_uarts == 0)
1da177e4
LT		 3572 return -ENODEV;
3573
3574 serial8250_isa_init_ports();
b430428a
DD		 3575 p = &serial8250_ports[port->line].port;
3576 p->iobase = port->iobase;
3577 p->membase = port->membase;
3578 p->irq = port->irq;
1c2f0493 3579 p->irqflags = port->irqflags;
b430428a
DD		 3580 p->uartclk = port->uartclk;
3581 p->fifosize = port->fifosize;
3582 p->regshift = port->regshift;
3583 p->iotype = port->iotype;
3584 p->flags = port->flags;
3585 p->mapbase = port->mapbase;
ee97d0e3 3586 p->mapsize = port->mapsize;
b430428a 3587 p->private_data = port->private_data;
125c97d8
HD		 3588 p->type = port->type;
3589 p->line = port->line;
7d6a07d1 3590
1a53e079
PH		 3591 serial8250_set_defaults(up_to_u8250p(p));
3592
7d6a07d1
DD		 3593 if (port->serial_in)
3594 p->serial_in = port->serial_in;
3595 if (port->serial_out)
3596 p->serial_out = port->serial_out;
583d28e9
JI		 3597 if (port->handle_irq)
3598 p->handle_irq = port->handle_irq;
7d6a07d1 3599
1da177e4
LT		 3600 return 0;
3601}
3602
3603/**
3604 * serial8250_suspend_port - suspend one serial port
3605 * @line: serial line number
1da177e4
LT		 3606 *
3607 * Suspend one serial port.
3608 */
3609void serial8250_suspend_port(int line)
3610{
4516d50a
PH		 3611 struct uart_8250_port *up = &serial8250_ports[line];
3612 struct uart_port *port = &up->port;
3613
3614 if (!console_suspend_enabled && uart_console(port) &&
3615 port->type != PORT_8250) {
3616 unsigned char canary = 0xa5;
3617 serial_out(up, UART_SCR, canary);
f01a0bd8
PH		 3618 if (serial_in(up, UART_SCR) == canary)
3619 up->canary = canary;
4516d50a
PH		 3620 }
3621
3622 uart_suspend_port(&serial8250_reg, port);
1da177e4
LT		 3623}
3624
3625/**
3626 * serial8250_resume_port - resume one serial port
3627 * @line: serial line number
1da177e4
LT		 3628 *
3629 * Resume one serial port.
3630 */
3631void serial8250_resume_port(int line)
3632{
b5b82df6 3633 struct uart_8250_port *up = &serial8250_ports[line];
dfe42443 3634 struct uart_port *port = &up->port;
b5b82df6 3635
4516d50a
PH		 3636 up->canary = 0;
3637
b5b82df6 3638 if (up->capabilities & UART_NATSEMI) {
b5b82df6 3639 /* Ensure it's still in high speed mode */
4fd996a1 3640 serial_port_out(port, UART_LCR, 0xE0);
b5b82df6 3641
0d0389e5 3642 ns16550a_goto_highspeed(up);
b5b82df6 3643
4fd996a1 3644 serial_port_out(port, UART_LCR, 0);
dfe42443 3645 port->uartclk = 921600*16;
b5b82df6 3646 }
dfe42443 3647 uart_resume_port(&serial8250_reg, port);
1da177e4
LT		 3648}
3649
3650/*
3651 * Register a set of serial devices attached to a platform device. The
3652 * list is terminated with a zero flags entry, which means we expect
3653 * all entries to have at least UPF_BOOT_AUTOCONF set.
3654 */
9671f099 3655static int serial8250_probe(struct platform_device *dev)
1da177e4 3656{
574de559 3657 struct plat_serial8250_port *p = dev_get_platdata(&dev->dev);
2655a2c7 3658 struct uart_8250_port uart;
4c0ebb80 3659 int ret, i, irqflag = 0;
1da177e4 3660
2655a2c7 3661 memset(&uart, 0, sizeof(uart));
1da177e4 3662
4c0ebb80
AGR		 3663 if (share_irqs)
3664 irqflag = IRQF_SHARED;
3665
ec9f47cd 3666 for (i = 0; p && p->flags != 0; p++, i++) {
2655a2c7
AC		 3667 uart.port.iobase = p->iobase;
3668 uart.port.membase = p->membase;
3669 uart.port.irq = p->irq;
3670 uart.port.irqflags = p->irqflags;
3671 uart.port.uartclk = p->uartclk;
3672 uart.port.regshift = p->regshift;
3673 uart.port.iotype = p->iotype;
3674 uart.port.flags = p->flags;
3675 uart.port.mapbase = p->mapbase;
3676 uart.port.hub6 = p->hub6;
3677 uart.port.private_data = p->private_data;
3678 uart.port.type = p->type;
3679 uart.port.serial_in = p->serial_in;
3680 uart.port.serial_out = p->serial_out;
3681 uart.port.handle_irq = p->handle_irq;
3682 uart.port.handle_break = p->handle_break;
3683 uart.port.set_termios = p->set_termios;
3684 uart.port.pm = p->pm;
3685 uart.port.dev = &dev->dev;
3686 uart.port.irqflags |= irqflag;
3687 ret = serial8250_register_8250_port(&uart);
ec9f47cd 3688 if (ret < 0) {
3ae5eaec 3689 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 3690 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3691 p->iobase, (unsigned long long)p->mapbase,
3692 p->irq, ret);
ec9f47cd 3693 }
1da177e4
LT		 3694 }
3695 return 0;
3696}
3697
3698/*
3699 * Remove serial ports registered against a platform device.
3700 */
ae8d8a14 3701static int serial8250_remove(struct platform_device *dev)
1da177e4
LT		 3702{
3703 int i;
3704
317a6842 3705 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 3706 struct uart_8250_port *up = &serial8250_ports[i];
3707
3ae5eaec 3708 if (up->port.dev == &dev->dev)
1da177e4
LT		 3709 serial8250_unregister_port(i);
3710 }
3711 return 0;
3712}
3713
3ae5eaec 3714static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 3715{
3716 int i;
3717
1da177e4
LT		 3718 for (i = 0; i < UART_NR; i++) {
3719 struct uart_8250_port *up = &serial8250_ports[i];
3720
3ae5eaec 3721 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3722 uart_suspend_port(&serial8250_reg, &up->port);
3723 }
3724
3725 return 0;
3726}
3727
3ae5eaec 3728static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3729{
3730 int i;
3731
1da177e4
LT		 3732 for (i = 0; i < UART_NR; i++) {
3733 struct uart_8250_port *up = &serial8250_ports[i];
3734
3ae5eaec 3735 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3736 serial8250_resume_port(i);
1da177e4
LT		 3737 }
3738
3739 return 0;
3740}
3741
3ae5eaec 3742static struct platform_driver serial8250_isa_driver = {
1da177e4 3743 .probe = serial8250_probe,
2d47b716 3744 .remove = serial8250_remove,
1da177e4
LT		 3745 .suspend = serial8250_suspend,
3746 .resume = serial8250_resume,
3ae5eaec
RK		 3747 .driver = {
3748 .name = "serial8250",
3749 },
1da177e4
LT		 3750};
3751
3752/*
3753 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3754 * in the table in include/asm/serial.h
3755 */
3756static struct platform_device *serial8250_isa_devs;
3757
3758/*
2655a2c7 3759 * serial8250_register_8250_port and serial8250_unregister_port allows for
1da177e4
LT		 3760 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3761 * modems and PCI multiport cards.
3762 */
f392ecfa 3763static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3764
3765static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3766{
3767 int i;
3768
3769 /*
3770 * First, find a port entry which matches.
3771 */
317a6842 3772 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3773 if (uart_match_port(&serial8250_ports[i].port, port))
3774 return &serial8250_ports[i];
3775
59b3e898
SAS		 3776 /* try line number first if still available */
3777 i = port->line;
3778 if (i < nr_uarts && serial8250_ports[i].port.type == PORT_UNKNOWN &&
3779 serial8250_ports[i].port.iobase == 0)
3780 return &serial8250_ports[i];
1da177e4
LT		 3781 /*
3782 * We didn't find a matching entry, so look for the first
3783 * free entry. We look for one which hasn't been previously
3784 * used (indicated by zero iobase).
3785 */
317a6842 3786 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3787 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3788 serial8250_ports[i].port.iobase == 0)
3789 return &serial8250_ports[i];
3790
3791 /*
3792 * That also failed. Last resort is to find any entry which
3793 * doesn't have a real port associated with it.
3794 */
317a6842 3795 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3796 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3797 return &serial8250_ports[i];
3798
3799 return NULL;
3800}
3801
3802/**
f73fa05b 3803 * serial8250_register_8250_port - register a serial port
58bcd332 3804 * @up: serial port template
1da177e4
LT		 3805 *
3806 * Configure the serial port specified by the request. If the
3807 * port exists and is in use, it is hung up and unregistered
3808 * first.
3809 *
3810 * The port is then probed and if necessary the IRQ is autodetected
3811 * If this fails an error is returned.
3812 *
3813 * On success the port is ready to use and the line number is returned.
3814 */
f73fa05b 3815int serial8250_register_8250_port(struct uart_8250_port *up)
1da177e4
LT		 3816{
3817 struct uart_8250_port *uart;
3818 int ret = -ENOSPC;
3819
f73fa05b 3820 if (up->port.uartclk == 0)
1da177e4
LT		 3821 return -EINVAL;
3822
f392ecfa 3823 mutex_lock(&serial_mutex);
1da177e4 3824
f73fa05b 3825 uart = serial8250_find_match_or_unused(&up->port);
65ecc9c0 3826 if (uart && uart->port.type != PORT_8250_CIR) {
835d844d
SY		 3827 if (uart->port.dev)
3828 uart_remove_one_port(&serial8250_reg, &uart->port);
1da177e4 3829
f73fa05b
MD		 3830 uart->port.iobase = up->port.iobase;
3831 uart->port.membase = up->port.membase;
3832 uart->port.irq = up->port.irq;
3833 uart->port.irqflags = up->port.irqflags;
3834 uart->port.uartclk = up->port.uartclk;
3835 uart->port.fifosize = up->port.fifosize;
3836 uart->port.regshift = up->port.regshift;
3837 uart->port.iotype = up->port.iotype;
3838 uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF;
a2d33d87 3839 uart->bugs = up->bugs;
f73fa05b 3840 uart->port.mapbase = up->port.mapbase;
ee97d0e3 3841 uart->port.mapsize = up->port.mapsize;
f73fa05b 3842 uart->port.private_data = up->port.private_data;
9660497c
HK		 3843 uart->tx_loadsz = up->tx_loadsz;
3844 uart->capabilities = up->capabilities;
234abab1
SAS		 3845 uart->port.throttle = up->port.throttle;
3846 uart->port.unthrottle = up->port.unthrottle;
46c55b4b
RRD		 3847 uart->port.rs485_config = up->port.rs485_config;
3848 uart->port.rs485 = up->port.rs485;
d53e1428 3849 uart->dma = up->dma;
9660497c 3850
6a3f45dc
HK		 3851 /* Take tx_loadsz from fifosize if it wasn't set separately */
3852 if (uart->port.fifosize && !uart->tx_loadsz)
3853 uart->tx_loadsz = uart->port.fifosize;
3854
f73fa05b
MD		 3855 if (up->port.dev)
3856 uart->port.dev = up->port.dev;
3857
e13cb72b
PH		 3858 if (skip_txen_test)
3859 uart->port.flags |= UPF_NO_TXEN_TEST;
3860
f73fa05b 3861 if (up->port.flags & UPF_FIXED_TYPE)
afd483bd 3862 uart->port.type = up->port.type;
8e23fcc8 3863
1a53e079
PH		 3864 serial8250_set_defaults(uart);
3865
7d6a07d1 3866 /* Possibly override default I/O functions. */
f73fa05b
MD		 3867 if (up->port.serial_in)
3868 uart->port.serial_in = up->port.serial_in;
3869 if (up->port.serial_out)
3870 uart->port.serial_out = up->port.serial_out;
3871 if (up->port.handle_irq)
3872 uart->port.handle_irq = up->port.handle_irq;
235dae5d 3873 /* Possibly override set_termios call */
f73fa05b
MD		 3874 if (up->port.set_termios)
3875 uart->port.set_termios = up->port.set_termios;
4bf4ea9d
PH		 3876 if (up->port.set_mctrl)
3877 uart->port.set_mctrl = up->port.set_mctrl;
b99b121b
SAS		 3878 if (up->port.startup)
3879 uart->port.startup = up->port.startup;
3880 if (up->port.shutdown)
3881 uart->port.shutdown = up->port.shutdown;
f73fa05b
MD		 3882 if (up->port.pm)
3883 uart->port.pm = up->port.pm;
3884 if (up->port.handle_break)
3885 uart->port.handle_break = up->port.handle_break;
3886 if (up->dl_read)
3887 uart->dl_read = up->dl_read;
3888 if (up->dl_write)
3889 uart->dl_write = up->dl_write;
1da177e4 3890
af7f3743
AC		 3891 if (serial8250_isa_config != NULL)
3892 serial8250_isa_config(0, &uart->port,
3893 &uart->capabilities);
3894
1da177e4
LT		 3895 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3896 if (ret == 0)
3897 ret = uart->port.line;
3898 }
f392ecfa 3899 mutex_unlock(&serial_mutex);
1da177e4
LT		 3900
3901 return ret;
3902}
f73fa05b
MD		 3903EXPORT_SYMBOL(serial8250_register_8250_port);
3904
1da177e4
LT		 3905/**
3906 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3907 * @line: serial line number
3908 *
3909 * Remove one serial port. This may not be called from interrupt
3910 * context. We hand the port back to the our control.
3911 */
3912void serial8250_unregister_port(int line)
3913{
3914 struct uart_8250_port *uart = &serial8250_ports[line];
3915
f392ecfa 3916 mutex_lock(&serial_mutex);
1da177e4
LT		 3917 uart_remove_one_port(&serial8250_reg, &uart->port);
3918 if (serial8250_isa_devs) {
3919 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
e13cb72b
PH		 3920 if (skip_txen_test)
3921 uart->port.flags |= UPF_NO_TXEN_TEST;
1da177e4
LT		 3922 uart->port.type = PORT_UNKNOWN;
3923 uart->port.dev = &serial8250_isa_devs->dev;
5db496b9 3924 uart->capabilities = 0;
1da177e4
LT		 3925 uart_add_one_port(&serial8250_reg, &uart->port);
3926 } else {
3927 uart->port.dev = NULL;
3928 }
f392ecfa 3929 mutex_unlock(&serial_mutex);
1da177e4
LT		 3930}
3931EXPORT_SYMBOL(serial8250_unregister_port);
3932
3933static int __init serial8250_init(void)
3934{
25db8ad5 3935 int ret;
1da177e4 3936
59cfc45f
JK		 3937 if (nr_uarts == 0)
3938 return -ENODEV;
3939
835d844d 3940 serial8250_isa_init_ports();
a61c2d78 3941
f1fb9bb8 3942 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3943 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3944 share_irqs ? "en" : "dis");
3945
b70ac771
DM		 3946#ifdef CONFIG_SPARC
3947 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3948#else
3949 serial8250_reg.nr = UART_NR;
1da177e4 3950 ret = uart_register_driver(&serial8250_reg);
b70ac771 3951#endif
1da177e4
LT		 3952 if (ret)
3953 goto out;
3954
835d844d
SY		 3955 ret = serial8250_pnp_init();
3956 if (ret)
3957 goto unreg_uart_drv;
3958
7493a314
DT		 3959 serial8250_isa_devs = platform_device_alloc("serial8250",
3960 PLAT8250_DEV_LEGACY);
3961 if (!serial8250_isa_devs) {
3962 ret = -ENOMEM;
835d844d 3963 goto unreg_pnp;
1da177e4
LT		 3964 }
3965
7493a314
DT		 3966 ret = platform_device_add(serial8250_isa_devs);
3967 if (ret)
3968 goto put_dev;
3969
1da177e4
LT		 3970 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3971
bc965a7f
RK		 3972 ret = platform_driver_register(&serial8250_isa_driver);
3973 if (ret == 0)
3974 goto out;
1da177e4 3975
bc965a7f 3976 platform_device_del(serial8250_isa_devs);
25db8ad5 3977put_dev:
7493a314 3978 platform_device_put(serial8250_isa_devs);
835d844d
SY		 3979unreg_pnp:
3980 serial8250_pnp_exit();
25db8ad5 3981unreg_uart_drv:
b70ac771
DM		 3982#ifdef CONFIG_SPARC
3983 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3984#else
1da177e4 3985 uart_unregister_driver(&serial8250_reg);
b70ac771 3986#endif
25db8ad5 3987out:
1da177e4
LT		 3988 return ret;
3989}
3990
3991static void __exit serial8250_exit(void)
3992{
3993 struct platform_device *isa_dev = serial8250_isa_devs;
3994
3995 /*
3996 * This tells serial8250_unregister_port() not to re-register
3997 * the ports (thereby making serial8250_isa_driver permanently
3998 * in use.)
3999 */
4000 serial8250_isa_devs = NULL;
4001
3ae5eaec 4002 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 4003 platform_device_unregister(isa_dev);
4004
835d844d
SY		 4005 serial8250_pnp_exit();
4006
b70ac771
DM		 4007#ifdef CONFIG_SPARC
4008 sunserial_unregister_minors(&serial8250_reg, UART_NR);
4009#else
1da177e4 4010 uart_unregister_driver(&serial8250_reg);
b70ac771 4011#endif
1da177e4
LT		 4012}
4013
4014module_init(serial8250_init);
4015module_exit(serial8250_exit);
4016
4017EXPORT_SYMBOL(serial8250_suspend_port);
4018EXPORT_SYMBOL(serial8250_resume_port);
4019
4020MODULE_LICENSE("GPL");
d87a6d95 4021MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 4022
4023module_param(share_irqs, uint, 0644);
4024MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
4025 " (unsafe)");
4026
a61c2d78
DJ		 4027module_param(nr_uarts, uint, 0644);
4028MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
4029
d41a4b51
CE		 4030module_param(skip_txen_test, uint, 0644);
4031MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
4032
1da177e4
LT		 4033#ifdef CONFIG_SERIAL_8250_RSA
4034module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
4035MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
4036#endif
4037MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
f2b8dfd9 4038
9326b047 4039#ifdef CONFIG_SERIAL_8250_DEPRECATED_OPTIONS
f2b8dfd9
JB		 4040#ifndef MODULE
4041/* This module was renamed to 8250_core in 3.7. Keep the old "8250" name
4042 * working as well for the module options so we don't break people. We
4043 * need to keep the names identical and the convenient macros will happily
4044 * refuse to let us do that by failing the build with redefinition errors
4045 * of global variables. So we stick them inside a dummy function to avoid
4046 * those conflicts. The options still get parsed, and the redefined
4047 * MODULE_PARAM_PREFIX lets us keep the "8250." syntax alive.
4048 *
4049 * This is hacky. I'm sorry.
4050 */
4051static void __used s8250_options(void)
4052{
4053#undef MODULE_PARAM_PREFIX
9196d8ac 4054#define MODULE_PARAM_PREFIX "8250_core."
f2b8dfd9
JB		 4055
4056 module_param_cb(share_irqs, &param_ops_uint, &share_irqs, 0644);
4057 module_param_cb(nr_uarts, &param_ops_uint, &nr_uarts, 0644);
4058 module_param_cb(skip_txen_test, &param_ops_uint, &skip_txen_test, 0644);
4059#ifdef CONFIG_SERIAL_8250_RSA
4060 __module_param_call(MODULE_PARAM_PREFIX, probe_rsa,
4061 &param_array_ops, .arr = &__param_arr_probe_rsa,
91f9d330 4062 0444, -1, 0);
f2b8dfd9
JB		 4063#endif
4064}
4065#else
9196d8ac 4066MODULE_ALIAS("8250_core");
f2b8dfd9 4067#endif
f2b8dfd9 4068#endif
Linux kernel - Deliverables
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