Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for 8250/16550-type serial ports |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * | |
6 | * Copyright (C) 2001 Russell King. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
1da177e4 LT |
13 | * A note about mapbase / membase |
14 | * | |
15 | * mapbase is the physical address of the IO port. | |
16 | * membase is an 'ioremapped' cookie. | |
17 | */ | |
1da177e4 LT |
18 | |
19 | #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
20 | #define SUPPORT_SYSRQ | |
21 | #endif | |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/moduleparam.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/console.h> | |
28 | #include <linux/sysrq.h> | |
1da177e4 | 29 | #include <linux/delay.h> |
d052d1be | 30 | #include <linux/platform_device.h> |
1da177e4 | 31 | #include <linux/tty.h> |
cd3ecad1 | 32 | #include <linux/ratelimit.h> |
1da177e4 | 33 | #include <linux/tty_flip.h> |
1da177e4 LT |
34 | #include <linux/serial_core.h> |
35 | #include <linux/serial.h> | |
36 | #include <linux/serial_8250.h> | |
78512ece | 37 | #include <linux/nmi.h> |
f392ecfa | 38 | #include <linux/mutex.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
0b4af1d9 | 40 | #include <linux/uaccess.h> |
d74d5d1b | 41 | #include <linux/pm_runtime.h> |
6816383a PG |
42 | #ifdef CONFIG_SPARC |
43 | #include <linux/sunserialcore.h> | |
44 | #endif | |
1da177e4 LT |
45 | |
46 | #include <asm/io.h> | |
47 | #include <asm/irq.h> | |
48 | ||
49 | #include "8250.h" | |
50 | ||
51 | /* | |
52 | * Configuration: | |
40663cc7 | 53 | * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option |
1da177e4 LT |
54 | * is unsafe when used on edge-triggered interrupts. |
55 | */ | |
408b664a | 56 | static unsigned int share_irqs = SERIAL8250_SHARE_IRQS; |
1da177e4 | 57 | |
a61c2d78 DJ |
58 | static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS; |
59 | ||
8440838b DM |
60 | static struct uart_driver serial8250_reg; |
61 | ||
62 | static int serial_index(struct uart_port *port) | |
63 | { | |
64 | return (serial8250_reg.minor - 64) + port->line; | |
65 | } | |
66 | ||
d41a4b51 CE |
67 | static unsigned int skip_txen_test; /* force skip of txen test at init time */ |
68 | ||
1da177e4 LT |
69 | /* |
70 | * Debugging. | |
71 | */ | |
72 | #if 0 | |
73 | #define DEBUG_AUTOCONF(fmt...) printk(fmt) | |
74 | #else | |
75 | #define DEBUG_AUTOCONF(fmt...) do { } while (0) | |
76 | #endif | |
77 | ||
78 | #if 0 | |
79 | #define DEBUG_INTR(fmt...) printk(fmt) | |
80 | #else | |
81 | #define DEBUG_INTR(fmt...) do { } while (0) | |
82 | #endif | |
83 | ||
e7328ae1 | 84 | #define PASS_LIMIT 512 |
1da177e4 | 85 | |
bca47613 DH |
86 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
87 | ||
88 | ||
1da177e4 LT |
89 | #ifdef CONFIG_SERIAL_8250_DETECT_IRQ |
90 | #define CONFIG_SERIAL_DETECT_IRQ 1 | |
91 | #endif | |
1da177e4 LT |
92 | #ifdef CONFIG_SERIAL_8250_MANY_PORTS |
93 | #define CONFIG_SERIAL_MANY_PORTS 1 | |
94 | #endif | |
95 | ||
96 | /* | |
97 | * HUB6 is always on. This will be removed once the header | |
98 | * files have been cleaned. | |
99 | */ | |
100 | #define CONFIG_HUB6 1 | |
101 | ||
a4ed1e41 | 102 | #include <asm/serial.h> |
1da177e4 LT |
103 | /* |
104 | * SERIAL_PORT_DFNS tells us about built-in ports that have no | |
105 | * standard enumeration mechanism. Platforms that can find all | |
106 | * serial ports via mechanisms like ACPI or PCI need not supply it. | |
107 | */ | |
108 | #ifndef SERIAL_PORT_DFNS | |
109 | #define SERIAL_PORT_DFNS | |
110 | #endif | |
111 | ||
cb3592be | 112 | static const struct old_serial_port old_serial_port[] = { |
1da177e4 LT |
113 | SERIAL_PORT_DFNS /* defined in asm/serial.h */ |
114 | }; | |
115 | ||
026d02a2 | 116 | #define UART_NR CONFIG_SERIAL_8250_NR_UARTS |
1da177e4 LT |
117 | |
118 | #ifdef CONFIG_SERIAL_8250_RSA | |
119 | ||
120 | #define PORT_RSA_MAX 4 | |
121 | static unsigned long probe_rsa[PORT_RSA_MAX]; | |
122 | static unsigned int probe_rsa_count; | |
123 | #endif /* CONFIG_SERIAL_8250_RSA */ | |
124 | ||
1da177e4 | 125 | struct irq_info { |
25db8ad5 AC |
126 | struct hlist_node node; |
127 | int irq; | |
128 | spinlock_t lock; /* Protects list not the hash */ | |
1da177e4 LT |
129 | struct list_head *head; |
130 | }; | |
131 | ||
25db8ad5 AC |
132 | #define NR_IRQ_HASH 32 /* Can be adjusted later */ |
133 | static struct hlist_head irq_lists[NR_IRQ_HASH]; | |
134 | static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */ | |
1da177e4 LT |
135 | |
136 | /* | |
137 | * Here we define the default xmit fifo size used for each type of UART. | |
138 | */ | |
139 | static const struct serial8250_config uart_config[] = { | |
140 | [PORT_UNKNOWN] = { | |
141 | .name = "unknown", | |
142 | .fifo_size = 1, | |
143 | .tx_loadsz = 1, | |
144 | }, | |
145 | [PORT_8250] = { | |
146 | .name = "8250", | |
147 | .fifo_size = 1, | |
148 | .tx_loadsz = 1, | |
149 | }, | |
150 | [PORT_16450] = { | |
151 | .name = "16450", | |
152 | .fifo_size = 1, | |
153 | .tx_loadsz = 1, | |
154 | }, | |
155 | [PORT_16550] = { | |
156 | .name = "16550", | |
157 | .fifo_size = 1, | |
158 | .tx_loadsz = 1, | |
159 | }, | |
160 | [PORT_16550A] = { | |
161 | .name = "16550A", | |
162 | .fifo_size = 16, | |
163 | .tx_loadsz = 16, | |
164 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
aef9a7bd | 165 | .rxtrig_bytes = {1, 4, 8, 14}, |
1da177e4 LT |
166 | .flags = UART_CAP_FIFO, |
167 | }, | |
168 | [PORT_CIRRUS] = { | |
169 | .name = "Cirrus", | |
170 | .fifo_size = 1, | |
171 | .tx_loadsz = 1, | |
172 | }, | |
173 | [PORT_16650] = { | |
174 | .name = "ST16650", | |
175 | .fifo_size = 1, | |
176 | .tx_loadsz = 1, | |
177 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
178 | }, | |
179 | [PORT_16650V2] = { | |
180 | .name = "ST16650V2", | |
181 | .fifo_size = 32, | |
182 | .tx_loadsz = 16, | |
183 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
184 | UART_FCR_T_TRIG_00, | |
aef9a7bd | 185 | .rxtrig_bytes = {8, 16, 24, 28}, |
1da177e4 LT |
186 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, |
187 | }, | |
188 | [PORT_16750] = { | |
189 | .name = "TI16750", | |
190 | .fifo_size = 64, | |
191 | .tx_loadsz = 64, | |
192 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | | |
193 | UART_FCR7_64BYTE, | |
aef9a7bd | 194 | .rxtrig_bytes = {1, 16, 32, 56}, |
1da177e4 LT |
195 | .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, |
196 | }, | |
197 | [PORT_STARTECH] = { | |
198 | .name = "Startech", | |
199 | .fifo_size = 1, | |
200 | .tx_loadsz = 1, | |
201 | }, | |
202 | [PORT_16C950] = { | |
203 | .name = "16C950/954", | |
204 | .fifo_size = 128, | |
205 | .tx_loadsz = 128, | |
206 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
d0694e2a PM |
207 | /* UART_CAP_EFR breaks billionon CF bluetooth card. */ |
208 | .flags = UART_CAP_FIFO | UART_CAP_SLEEP, | |
1da177e4 LT |
209 | }, |
210 | [PORT_16654] = { | |
211 | .name = "ST16654", | |
212 | .fifo_size = 64, | |
213 | .tx_loadsz = 32, | |
214 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
215 | UART_FCR_T_TRIG_10, | |
aef9a7bd | 216 | .rxtrig_bytes = {8, 16, 56, 60}, |
1da177e4 LT |
217 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, |
218 | }, | |
219 | [PORT_16850] = { | |
220 | .name = "XR16850", | |
221 | .fifo_size = 128, | |
222 | .tx_loadsz = 128, | |
223 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
224 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
225 | }, | |
226 | [PORT_RSA] = { | |
227 | .name = "RSA", | |
228 | .fifo_size = 2048, | |
229 | .tx_loadsz = 2048, | |
230 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11, | |
231 | .flags = UART_CAP_FIFO, | |
232 | }, | |
233 | [PORT_NS16550A] = { | |
234 | .name = "NS16550A", | |
235 | .fifo_size = 16, | |
236 | .tx_loadsz = 16, | |
237 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
238 | .flags = UART_CAP_FIFO | UART_NATSEMI, | |
239 | }, | |
240 | [PORT_XSCALE] = { | |
241 | .name = "XScale", | |
242 | .fifo_size = 32, | |
243 | .tx_loadsz = 32, | |
244 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
4539c24f | 245 | .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE, |
1da177e4 | 246 | }, |
6b06f191 DD |
247 | [PORT_OCTEON] = { |
248 | .name = "OCTEON", | |
249 | .fifo_size = 64, | |
250 | .tx_loadsz = 64, | |
251 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
bd71c182 TK |
252 | .flags = UART_CAP_FIFO, |
253 | }, | |
08e0992f FF |
254 | [PORT_AR7] = { |
255 | .name = "AR7", | |
256 | .fifo_size = 16, | |
257 | .tx_loadsz = 16, | |
258 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, | |
259 | .flags = UART_CAP_FIFO | UART_CAP_AFE, | |
260 | }, | |
235dae5d PL |
261 | [PORT_U6_16550A] = { |
262 | .name = "U6_16550A", | |
263 | .fifo_size = 64, | |
264 | .tx_loadsz = 64, | |
265 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
266 | .flags = UART_CAP_FIFO | UART_CAP_AFE, | |
267 | }, | |
4539c24f SW |
268 | [PORT_TEGRA] = { |
269 | .name = "Tegra", | |
270 | .fifo_size = 32, | |
271 | .tx_loadsz = 8, | |
272 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
273 | UART_FCR_T_TRIG_01, | |
aef9a7bd | 274 | .rxtrig_bytes = {1, 4, 8, 14}, |
4539c24f SW |
275 | .flags = UART_CAP_FIFO | UART_CAP_RTOIE, |
276 | }, | |
06315348 SH |
277 | [PORT_XR17D15X] = { |
278 | .name = "XR17D15X", | |
279 | .fifo_size = 64, | |
280 | .tx_loadsz = 64, | |
281 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
81db0772 MS |
282 | .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR | |
283 | UART_CAP_SLEEP, | |
06315348 | 284 | }, |
dc96efb7 MS |
285 | [PORT_XR17V35X] = { |
286 | .name = "XR17V35X", | |
287 | .fifo_size = 256, | |
288 | .tx_loadsz = 256, | |
289 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 | | |
290 | UART_FCR_T_TRIG_11, | |
291 | .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR | | |
292 | UART_CAP_SLEEP, | |
293 | }, | |
7a514596 RS |
294 | [PORT_LPC3220] = { |
295 | .name = "LPC3220", | |
296 | .fifo_size = 64, | |
297 | .tx_loadsz = 32, | |
298 | .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO | | |
299 | UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00, | |
300 | .flags = UART_CAP_FIFO, | |
301 | }, | |
ebebd49a SH |
302 | [PORT_BRCM_TRUMANAGE] = { |
303 | .name = "TruManage", | |
304 | .fifo_size = 1, | |
305 | .tx_loadsz = 1024, | |
306 | .flags = UART_CAP_HFIFO, | |
307 | }, | |
65ecc9c0 SY |
308 | [PORT_8250_CIR] = { |
309 | .name = "CIR port" | |
e06c93ca LFT |
310 | }, |
311 | [PORT_ALTR_16550_F32] = { | |
312 | .name = "Altera 16550 FIFO32", | |
313 | .fifo_size = 32, | |
314 | .tx_loadsz = 32, | |
315 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
316 | .flags = UART_CAP_FIFO | UART_CAP_AFE, | |
317 | }, | |
318 | [PORT_ALTR_16550_F64] = { | |
319 | .name = "Altera 16550 FIFO64", | |
320 | .fifo_size = 64, | |
321 | .tx_loadsz = 64, | |
322 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
323 | .flags = UART_CAP_FIFO | UART_CAP_AFE, | |
324 | }, | |
325 | [PORT_ALTR_16550_F128] = { | |
326 | .name = "Altera 16550 FIFO128", | |
327 | .fifo_size = 128, | |
328 | .tx_loadsz = 128, | |
329 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
330 | .flags = UART_CAP_FIFO | UART_CAP_AFE, | |
331 | }, | |
1da177e4 LT |
332 | }; |
333 | ||
cc419fa0 | 334 | /* Uart divisor latch read */ |
e8155629 | 335 | static int default_serial_dl_read(struct uart_8250_port *up) |
cc419fa0 MD |
336 | { |
337 | return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8; | |
338 | } | |
339 | ||
340 | /* Uart divisor latch write */ | |
e8155629 | 341 | static void default_serial_dl_write(struct uart_8250_port *up, int value) |
cc419fa0 MD |
342 | { |
343 | serial_out(up, UART_DLL, value & 0xff); | |
344 | serial_out(up, UART_DLM, value >> 8 & 0xff); | |
345 | } | |
346 | ||
c420811f | 347 | #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X) |
21c614a7 | 348 | |
c420811f | 349 | /* Au1x00/RT288x UART hardware has a weird register layout */ |
21c614a7 PA |
350 | static const u8 au_io_in_map[] = { |
351 | [UART_RX] = 0, | |
352 | [UART_IER] = 2, | |
353 | [UART_IIR] = 3, | |
354 | [UART_LCR] = 5, | |
355 | [UART_MCR] = 6, | |
356 | [UART_LSR] = 7, | |
357 | [UART_MSR] = 8, | |
358 | }; | |
359 | ||
360 | static const u8 au_io_out_map[] = { | |
361 | [UART_TX] = 1, | |
362 | [UART_IER] = 2, | |
363 | [UART_FCR] = 4, | |
364 | [UART_LCR] = 5, | |
365 | [UART_MCR] = 6, | |
366 | }; | |
367 | ||
6b416031 | 368 | static unsigned int au_serial_in(struct uart_port *p, int offset) |
21c614a7 | 369 | { |
6b416031 MD |
370 | offset = au_io_in_map[offset] << p->regshift; |
371 | return __raw_readl(p->membase + offset); | |
21c614a7 PA |
372 | } |
373 | ||
6b416031 | 374 | static void au_serial_out(struct uart_port *p, int offset, int value) |
21c614a7 | 375 | { |
6b416031 MD |
376 | offset = au_io_out_map[offset] << p->regshift; |
377 | __raw_writel(value, p->membase + offset); | |
378 | } | |
379 | ||
380 | /* Au1x00 haven't got a standard divisor latch */ | |
381 | static int au_serial_dl_read(struct uart_8250_port *up) | |
382 | { | |
383 | return __raw_readl(up->port.membase + 0x28); | |
384 | } | |
385 | ||
386 | static void au_serial_dl_write(struct uart_8250_port *up, int value) | |
387 | { | |
388 | __raw_writel(value, up->port.membase + 0x28); | |
21c614a7 PA |
389 | } |
390 | ||
6b416031 MD |
391 | #endif |
392 | ||
7d6a07d1 | 393 | static unsigned int hub6_serial_in(struct uart_port *p, int offset) |
1da177e4 | 394 | { |
e8155629 | 395 | offset = offset << p->regshift; |
7d6a07d1 DD |
396 | outb(p->hub6 - 1 + offset, p->iobase); |
397 | return inb(p->iobase + 1); | |
398 | } | |
1da177e4 | 399 | |
7d6a07d1 DD |
400 | static void hub6_serial_out(struct uart_port *p, int offset, int value) |
401 | { | |
e8155629 | 402 | offset = offset << p->regshift; |
7d6a07d1 DD |
403 | outb(p->hub6 - 1 + offset, p->iobase); |
404 | outb(value, p->iobase + 1); | |
405 | } | |
1da177e4 | 406 | |
7d6a07d1 DD |
407 | static unsigned int mem_serial_in(struct uart_port *p, int offset) |
408 | { | |
e8155629 | 409 | offset = offset << p->regshift; |
7d6a07d1 DD |
410 | return readb(p->membase + offset); |
411 | } | |
1da177e4 | 412 | |
7d6a07d1 DD |
413 | static void mem_serial_out(struct uart_port *p, int offset, int value) |
414 | { | |
e8155629 | 415 | offset = offset << p->regshift; |
7d6a07d1 DD |
416 | writeb(value, p->membase + offset); |
417 | } | |
418 | ||
419 | static void mem32_serial_out(struct uart_port *p, int offset, int value) | |
420 | { | |
e8155629 | 421 | offset = offset << p->regshift; |
7d6a07d1 DD |
422 | writel(value, p->membase + offset); |
423 | } | |
424 | ||
425 | static unsigned int mem32_serial_in(struct uart_port *p, int offset) | |
426 | { | |
e8155629 | 427 | offset = offset << p->regshift; |
7d6a07d1 DD |
428 | return readl(p->membase + offset); |
429 | } | |
1da177e4 | 430 | |
7d6a07d1 DD |
431 | static unsigned int io_serial_in(struct uart_port *p, int offset) |
432 | { | |
e8155629 | 433 | offset = offset << p->regshift; |
7d6a07d1 DD |
434 | return inb(p->iobase + offset); |
435 | } | |
436 | ||
437 | static void io_serial_out(struct uart_port *p, int offset, int value) | |
438 | { | |
e8155629 | 439 | offset = offset << p->regshift; |
7d6a07d1 DD |
440 | outb(value, p->iobase + offset); |
441 | } | |
442 | ||
583d28e9 | 443 | static int serial8250_default_handle_irq(struct uart_port *port); |
dc96efb7 | 444 | static int exar_handle_irq(struct uart_port *port); |
583d28e9 | 445 | |
7d6a07d1 DD |
446 | static void set_io_from_upio(struct uart_port *p) |
447 | { | |
b1261c86 | 448 | struct uart_8250_port *up = up_to_u8250p(p); |
cc419fa0 | 449 | |
e8155629 MD |
450 | up->dl_read = default_serial_dl_read; |
451 | up->dl_write = default_serial_dl_write; | |
cc419fa0 | 452 | |
7d6a07d1 | 453 | switch (p->iotype) { |
1da177e4 | 454 | case UPIO_HUB6: |
7d6a07d1 DD |
455 | p->serial_in = hub6_serial_in; |
456 | p->serial_out = hub6_serial_out; | |
1da177e4 LT |
457 | break; |
458 | ||
459 | case UPIO_MEM: | |
7d6a07d1 DD |
460 | p->serial_in = mem_serial_in; |
461 | p->serial_out = mem_serial_out; | |
1da177e4 LT |
462 | break; |
463 | ||
464 | case UPIO_MEM32: | |
7d6a07d1 DD |
465 | p->serial_in = mem32_serial_in; |
466 | p->serial_out = mem32_serial_out; | |
1da177e4 LT |
467 | break; |
468 | ||
c420811f | 469 | #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X) |
21c614a7 | 470 | case UPIO_AU: |
7d6a07d1 DD |
471 | p->serial_in = au_serial_in; |
472 | p->serial_out = au_serial_out; | |
6b416031 MD |
473 | up->dl_read = au_serial_dl_read; |
474 | up->dl_write = au_serial_dl_write; | |
21c614a7 | 475 | break; |
6b416031 | 476 | #endif |
12bf3f24 | 477 | |
1da177e4 | 478 | default: |
7d6a07d1 DD |
479 | p->serial_in = io_serial_in; |
480 | p->serial_out = io_serial_out; | |
481 | break; | |
1da177e4 | 482 | } |
b8e7e40a AC |
483 | /* Remember loaded iotype */ |
484 | up->cur_iotype = p->iotype; | |
583d28e9 | 485 | p->handle_irq = serial8250_default_handle_irq; |
1da177e4 LT |
486 | } |
487 | ||
40b36daa | 488 | static void |
55e4016d | 489 | serial_port_out_sync(struct uart_port *p, int offset, int value) |
40b36daa | 490 | { |
7d6a07d1 | 491 | switch (p->iotype) { |
40b36daa AW |
492 | case UPIO_MEM: |
493 | case UPIO_MEM32: | |
40b36daa | 494 | case UPIO_AU: |
7d6a07d1 DD |
495 | p->serial_out(p, offset, value); |
496 | p->serial_in(p, UART_LCR); /* safe, no side-effects */ | |
40b36daa AW |
497 | break; |
498 | default: | |
7d6a07d1 | 499 | p->serial_out(p, offset, value); |
40b36daa AW |
500 | } |
501 | } | |
502 | ||
1da177e4 LT |
503 | /* |
504 | * For the 16C950 | |
505 | */ | |
506 | static void serial_icr_write(struct uart_8250_port *up, int offset, int value) | |
507 | { | |
508 | serial_out(up, UART_SCR, offset); | |
509 | serial_out(up, UART_ICR, value); | |
510 | } | |
511 | ||
512 | static unsigned int serial_icr_read(struct uart_8250_port *up, int offset) | |
513 | { | |
514 | unsigned int value; | |
515 | ||
516 | serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); | |
517 | serial_out(up, UART_SCR, offset); | |
518 | value = serial_in(up, UART_ICR); | |
519 | serial_icr_write(up, UART_ACR, up->acr); | |
520 | ||
521 | return value; | |
522 | } | |
523 | ||
524 | /* | |
525 | * FIFO support. | |
526 | */ | |
b5d674ab | 527 | static void serial8250_clear_fifos(struct uart_8250_port *p) |
1da177e4 LT |
528 | { |
529 | if (p->capabilities & UART_CAP_FIFO) { | |
0acf519f PG |
530 | serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO); |
531 | serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO | | |
1da177e4 | 532 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); |
0acf519f | 533 | serial_out(p, UART_FCR, 0); |
1da177e4 LT |
534 | } |
535 | } | |
536 | ||
0ad372b9 SM |
537 | void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p) |
538 | { | |
0ad372b9 | 539 | serial8250_clear_fifos(p); |
aef9a7bd | 540 | serial_out(p, UART_FCR, p->fcr); |
0ad372b9 SM |
541 | } |
542 | EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos); | |
543 | ||
d74d5d1b SAS |
544 | static void serial8250_rpm_get(struct uart_8250_port *p) |
545 | { | |
546 | if (!(p->capabilities & UART_CAP_RPM)) | |
547 | return; | |
548 | pm_runtime_get_sync(p->port.dev); | |
549 | } | |
550 | ||
551 | static void serial8250_rpm_put(struct uart_8250_port *p) | |
552 | { | |
553 | if (!(p->capabilities & UART_CAP_RPM)) | |
554 | return; | |
555 | pm_runtime_mark_last_busy(p->port.dev); | |
556 | pm_runtime_put_autosuspend(p->port.dev); | |
557 | } | |
558 | ||
559 | /* | |
560 | * This two wrapper ensure, that enable_runtime_pm_tx() can be called more than | |
561 | * once and disable_runtime_pm_tx() will still disable RPM because the fifo is | |
562 | * empty and the HW can idle again. | |
563 | */ | |
564 | static void serial8250_rpm_get_tx(struct uart_8250_port *p) | |
565 | { | |
566 | unsigned char rpm_active; | |
567 | ||
568 | if (!(p->capabilities & UART_CAP_RPM)) | |
569 | return; | |
570 | ||
571 | rpm_active = xchg(&p->rpm_tx_active, 1); | |
572 | if (rpm_active) | |
573 | return; | |
574 | pm_runtime_get_sync(p->port.dev); | |
575 | } | |
576 | ||
577 | static void serial8250_rpm_put_tx(struct uart_8250_port *p) | |
578 | { | |
579 | unsigned char rpm_active; | |
580 | ||
581 | if (!(p->capabilities & UART_CAP_RPM)) | |
582 | return; | |
583 | ||
584 | rpm_active = xchg(&p->rpm_tx_active, 0); | |
585 | if (!rpm_active) | |
586 | return; | |
587 | pm_runtime_mark_last_busy(p->port.dev); | |
588 | pm_runtime_put_autosuspend(p->port.dev); | |
589 | } | |
590 | ||
1da177e4 LT |
591 | /* |
592 | * IER sleep support. UARTs which have EFRs need the "extended | |
593 | * capability" bit enabled. Note that on XR16C850s, we need to | |
594 | * reset LCR to write to IER. | |
595 | */ | |
b5d674ab | 596 | static void serial8250_set_sleep(struct uart_8250_port *p, int sleep) |
1da177e4 | 597 | { |
dc96efb7 MS |
598 | /* |
599 | * Exar UARTs have a SLEEP register that enables or disables | |
600 | * each UART to enter sleep mode separately. On the XR17V35x the | |
601 | * register is accessible to each UART at the UART_EXAR_SLEEP | |
602 | * offset but the UART channel may only write to the corresponding | |
603 | * bit. | |
604 | */ | |
d74d5d1b | 605 | serial8250_rpm_get(p); |
81db0772 MS |
606 | if ((p->port.type == PORT_XR17V35X) || |
607 | (p->port.type == PORT_XR17D15X)) { | |
b790f210 | 608 | serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0); |
d74d5d1b | 609 | goto out; |
dc96efb7 MS |
610 | } |
611 | ||
1da177e4 LT |
612 | if (p->capabilities & UART_CAP_SLEEP) { |
613 | if (p->capabilities & UART_CAP_EFR) { | |
0acf519f PG |
614 | serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B); |
615 | serial_out(p, UART_EFR, UART_EFR_ECB); | |
616 | serial_out(p, UART_LCR, 0); | |
1da177e4 | 617 | } |
0acf519f | 618 | serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); |
1da177e4 | 619 | if (p->capabilities & UART_CAP_EFR) { |
0acf519f PG |
620 | serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B); |
621 | serial_out(p, UART_EFR, 0); | |
622 | serial_out(p, UART_LCR, 0); | |
1da177e4 LT |
623 | } |
624 | } | |
d74d5d1b SAS |
625 | out: |
626 | serial8250_rpm_put(p); | |
1da177e4 LT |
627 | } |
628 | ||
629 | #ifdef CONFIG_SERIAL_8250_RSA | |
630 | /* | |
631 | * Attempts to turn on the RSA FIFO. Returns zero on failure. | |
632 | * We set the port uart clock rate if we succeed. | |
633 | */ | |
634 | static int __enable_rsa(struct uart_8250_port *up) | |
635 | { | |
636 | unsigned char mode; | |
637 | int result; | |
638 | ||
0acf519f | 639 | mode = serial_in(up, UART_RSA_MSR); |
1da177e4 LT |
640 | result = mode & UART_RSA_MSR_FIFO; |
641 | ||
642 | if (!result) { | |
0acf519f PG |
643 | serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); |
644 | mode = serial_in(up, UART_RSA_MSR); | |
1da177e4 LT |
645 | result = mode & UART_RSA_MSR_FIFO; |
646 | } | |
647 | ||
648 | if (result) | |
649 | up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; | |
650 | ||
651 | return result; | |
652 | } | |
653 | ||
654 | static void enable_rsa(struct uart_8250_port *up) | |
655 | { | |
656 | if (up->port.type == PORT_RSA) { | |
657 | if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { | |
658 | spin_lock_irq(&up->port.lock); | |
659 | __enable_rsa(up); | |
660 | spin_unlock_irq(&up->port.lock); | |
661 | } | |
662 | if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) | |
0acf519f | 663 | serial_out(up, UART_RSA_FRR, 0); |
1da177e4 LT |
664 | } |
665 | } | |
666 | ||
667 | /* | |
668 | * Attempts to turn off the RSA FIFO. Returns zero on failure. | |
669 | * It is unknown why interrupts were disabled in here. However, | |
670 | * the caller is expected to preserve this behaviour by grabbing | |
671 | * the spinlock before calling this function. | |
672 | */ | |
673 | static void disable_rsa(struct uart_8250_port *up) | |
674 | { | |
675 | unsigned char mode; | |
676 | int result; | |
677 | ||
678 | if (up->port.type == PORT_RSA && | |
679 | up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { | |
680 | spin_lock_irq(&up->port.lock); | |
681 | ||
0acf519f | 682 | mode = serial_in(up, UART_RSA_MSR); |
1da177e4 LT |
683 | result = !(mode & UART_RSA_MSR_FIFO); |
684 | ||
685 | if (!result) { | |
0acf519f PG |
686 | serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); |
687 | mode = serial_in(up, UART_RSA_MSR); | |
1da177e4 LT |
688 | result = !(mode & UART_RSA_MSR_FIFO); |
689 | } | |
690 | ||
691 | if (result) | |
692 | up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; | |
693 | spin_unlock_irq(&up->port.lock); | |
694 | } | |
695 | } | |
696 | #endif /* CONFIG_SERIAL_8250_RSA */ | |
697 | ||
698 | /* | |
699 | * This is a quickie test to see how big the FIFO is. | |
700 | * It doesn't work at all the time, more's the pity. | |
701 | */ | |
702 | static int size_fifo(struct uart_8250_port *up) | |
703 | { | |
b32b19b8 JAH |
704 | unsigned char old_fcr, old_mcr, old_lcr; |
705 | unsigned short old_dl; | |
1da177e4 LT |
706 | int count; |
707 | ||
0acf519f PG |
708 | old_lcr = serial_in(up, UART_LCR); |
709 | serial_out(up, UART_LCR, 0); | |
710 | old_fcr = serial_in(up, UART_FCR); | |
711 | old_mcr = serial_in(up, UART_MCR); | |
712 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
1da177e4 | 713 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); |
0acf519f PG |
714 | serial_out(up, UART_MCR, UART_MCR_LOOP); |
715 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
b32b19b8 JAH |
716 | old_dl = serial_dl_read(up); |
717 | serial_dl_write(up, 0x0001); | |
0acf519f | 718 | serial_out(up, UART_LCR, 0x03); |
1da177e4 | 719 | for (count = 0; count < 256; count++) |
0acf519f | 720 | serial_out(up, UART_TX, count); |
1da177e4 | 721 | mdelay(20);/* FIXME - schedule_timeout */ |
0acf519f | 722 | for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) && |
1da177e4 | 723 | (count < 256); count++) |
0acf519f PG |
724 | serial_in(up, UART_RX); |
725 | serial_out(up, UART_FCR, old_fcr); | |
726 | serial_out(up, UART_MCR, old_mcr); | |
727 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
b32b19b8 | 728 | serial_dl_write(up, old_dl); |
0acf519f | 729 | serial_out(up, UART_LCR, old_lcr); |
1da177e4 LT |
730 | |
731 | return count; | |
732 | } | |
733 | ||
734 | /* | |
735 | * Read UART ID using the divisor method - set DLL and DLM to zero | |
736 | * and the revision will be in DLL and device type in DLM. We | |
737 | * preserve the device state across this. | |
738 | */ | |
739 | static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) | |
740 | { | |
741 | unsigned char old_dll, old_dlm, old_lcr; | |
742 | unsigned int id; | |
743 | ||
0acf519f PG |
744 | old_lcr = serial_in(p, UART_LCR); |
745 | serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A); | |
1da177e4 | 746 | |
0acf519f PG |
747 | old_dll = serial_in(p, UART_DLL); |
748 | old_dlm = serial_in(p, UART_DLM); | |
1da177e4 | 749 | |
0acf519f PG |
750 | serial_out(p, UART_DLL, 0); |
751 | serial_out(p, UART_DLM, 0); | |
1da177e4 | 752 | |
0acf519f | 753 | id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8; |
1da177e4 | 754 | |
0acf519f PG |
755 | serial_out(p, UART_DLL, old_dll); |
756 | serial_out(p, UART_DLM, old_dlm); | |
757 | serial_out(p, UART_LCR, old_lcr); | |
1da177e4 LT |
758 | |
759 | return id; | |
760 | } | |
761 | ||
762 | /* | |
763 | * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's. | |
764 | * When this function is called we know it is at least a StarTech | |
765 | * 16650 V2, but it might be one of several StarTech UARTs, or one of | |
766 | * its clones. (We treat the broken original StarTech 16650 V1 as a | |
767 | * 16550, and why not? Startech doesn't seem to even acknowledge its | |
768 | * existence.) | |
bd71c182 | 769 | * |
1da177e4 LT |
770 | * What evil have men's minds wrought... |
771 | */ | |
772 | static void autoconfig_has_efr(struct uart_8250_port *up) | |
773 | { | |
774 | unsigned int id1, id2, id3, rev; | |
775 | ||
776 | /* | |
777 | * Everything with an EFR has SLEEP | |
778 | */ | |
779 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; | |
780 | ||
781 | /* | |
782 | * First we check to see if it's an Oxford Semiconductor UART. | |
783 | * | |
784 | * If we have to do this here because some non-National | |
785 | * Semiconductor clone chips lock up if you try writing to the | |
786 | * LSR register (which serial_icr_read does) | |
787 | */ | |
788 | ||
789 | /* | |
790 | * Check for Oxford Semiconductor 16C950. | |
791 | * | |
792 | * EFR [4] must be set else this test fails. | |
793 | * | |
794 | * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca) | |
795 | * claims that it's needed for 952 dual UART's (which are not | |
796 | * recommended for new designs). | |
797 | */ | |
798 | up->acr = 0; | |
662b083a | 799 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
1da177e4 LT |
800 | serial_out(up, UART_EFR, UART_EFR_ECB); |
801 | serial_out(up, UART_LCR, 0x00); | |
802 | id1 = serial_icr_read(up, UART_ID1); | |
803 | id2 = serial_icr_read(up, UART_ID2); | |
804 | id3 = serial_icr_read(up, UART_ID3); | |
805 | rev = serial_icr_read(up, UART_REV); | |
806 | ||
807 | DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev); | |
808 | ||
809 | if (id1 == 0x16 && id2 == 0xC9 && | |
810 | (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) { | |
811 | up->port.type = PORT_16C950; | |
4ba5e35d RK |
812 | |
813 | /* | |
814 | * Enable work around for the Oxford Semiconductor 952 rev B | |
815 | * chip which causes it to seriously miscalculate baud rates | |
816 | * when DLL is 0. | |
817 | */ | |
818 | if (id3 == 0x52 && rev == 0x01) | |
819 | up->bugs |= UART_BUG_QUOT; | |
1da177e4 LT |
820 | return; |
821 | } | |
bd71c182 | 822 | |
1da177e4 LT |
823 | /* |
824 | * We check for a XR16C850 by setting DLL and DLM to 0, and then | |
825 | * reading back DLL and DLM. The chip type depends on the DLM | |
826 | * value read back: | |
827 | * 0x10 - XR16C850 and the DLL contains the chip revision. | |
828 | * 0x12 - XR16C2850. | |
829 | * 0x14 - XR16C854. | |
830 | */ | |
831 | id1 = autoconfig_read_divisor_id(up); | |
832 | DEBUG_AUTOCONF("850id=%04x ", id1); | |
833 | ||
834 | id2 = id1 >> 8; | |
835 | if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) { | |
1da177e4 LT |
836 | up->port.type = PORT_16850; |
837 | return; | |
838 | } | |
839 | ||
840 | /* | |
841 | * It wasn't an XR16C850. | |
842 | * | |
843 | * We distinguish between the '654 and the '650 by counting | |
844 | * how many bytes are in the FIFO. I'm using this for now, | |
845 | * since that's the technique that was sent to me in the | |
846 | * serial driver update, but I'm not convinced this works. | |
847 | * I've had problems doing this in the past. -TYT | |
848 | */ | |
849 | if (size_fifo(up) == 64) | |
850 | up->port.type = PORT_16654; | |
851 | else | |
852 | up->port.type = PORT_16650V2; | |
853 | } | |
854 | ||
855 | /* | |
856 | * We detected a chip without a FIFO. Only two fall into | |
857 | * this category - the original 8250 and the 16450. The | |
858 | * 16450 has a scratch register (accessible with LCR=0) | |
859 | */ | |
860 | static void autoconfig_8250(struct uart_8250_port *up) | |
861 | { | |
862 | unsigned char scratch, status1, status2; | |
863 | ||
864 | up->port.type = PORT_8250; | |
865 | ||
866 | scratch = serial_in(up, UART_SCR); | |
0acf519f | 867 | serial_out(up, UART_SCR, 0xa5); |
1da177e4 | 868 | status1 = serial_in(up, UART_SCR); |
0acf519f | 869 | serial_out(up, UART_SCR, 0x5a); |
1da177e4 | 870 | status2 = serial_in(up, UART_SCR); |
0acf519f | 871 | serial_out(up, UART_SCR, scratch); |
1da177e4 LT |
872 | |
873 | if (status1 == 0xa5 && status2 == 0x5a) | |
874 | up->port.type = PORT_16450; | |
875 | } | |
876 | ||
877 | static int broken_efr(struct uart_8250_port *up) | |
878 | { | |
879 | /* | |
880 | * Exar ST16C2550 "A2" devices incorrectly detect as | |
881 | * having an EFR, and report an ID of 0x0201. See | |
631dd1a8 | 882 | * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html |
1da177e4 LT |
883 | */ |
884 | if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) | |
885 | return 1; | |
886 | ||
887 | return 0; | |
888 | } | |
889 | ||
0d0389e5 YK |
890 | static inline int ns16550a_goto_highspeed(struct uart_8250_port *up) |
891 | { | |
892 | unsigned char status; | |
893 | ||
894 | status = serial_in(up, 0x04); /* EXCR2 */ | |
895 | #define PRESL(x) ((x) & 0x30) | |
896 | if (PRESL(status) == 0x10) { | |
897 | /* already in high speed mode */ | |
898 | return 0; | |
899 | } else { | |
900 | status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ | |
901 | status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ | |
0acf519f | 902 | serial_out(up, 0x04, status); |
0d0389e5 YK |
903 | } |
904 | return 1; | |
905 | } | |
906 | ||
1da177e4 LT |
907 | /* |
908 | * We know that the chip has FIFOs. Does it have an EFR? The | |
909 | * EFR is located in the same register position as the IIR and | |
910 | * we know the top two bits of the IIR are currently set. The | |
911 | * EFR should contain zero. Try to read the EFR. | |
912 | */ | |
913 | static void autoconfig_16550a(struct uart_8250_port *up) | |
914 | { | |
915 | unsigned char status1, status2; | |
916 | unsigned int iersave; | |
917 | ||
918 | up->port.type = PORT_16550A; | |
919 | up->capabilities |= UART_CAP_FIFO; | |
920 | ||
dc96efb7 MS |
921 | /* |
922 | * XR17V35x UARTs have an extra divisor register, DLD | |
923 | * that gets enabled with when DLAB is set which will | |
924 | * cause the device to incorrectly match and assign | |
925 | * port type to PORT_16650. The EFR for this UART is | |
926 | * found at offset 0x09. Instead check the Deice ID (DVID) | |
927 | * register for a 2, 4 or 8 port UART. | |
928 | */ | |
b7a7e14f MS |
929 | if (up->port.flags & UPF_EXAR_EFR) { |
930 | status1 = serial_in(up, UART_EXAR_DVID); | |
931 | if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) { | |
dc96efb7 MS |
932 | DEBUG_AUTOCONF("Exar XR17V35x "); |
933 | up->port.type = PORT_XR17V35X; | |
934 | up->capabilities |= UART_CAP_AFE | UART_CAP_EFR | | |
935 | UART_CAP_SLEEP; | |
936 | ||
937 | return; | |
938 | } | |
939 | ||
940 | } | |
941 | ||
1da177e4 LT |
942 | /* |
943 | * Check for presence of the EFR when DLAB is set. | |
944 | * Only ST16C650V1 UARTs pass this test. | |
945 | */ | |
0acf519f | 946 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
1da177e4 | 947 | if (serial_in(up, UART_EFR) == 0) { |
0acf519f | 948 | serial_out(up, UART_EFR, 0xA8); |
1da177e4 LT |
949 | if (serial_in(up, UART_EFR) != 0) { |
950 | DEBUG_AUTOCONF("EFRv1 "); | |
951 | up->port.type = PORT_16650; | |
952 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; | |
953 | } else { | |
954 | DEBUG_AUTOCONF("Motorola 8xxx DUART "); | |
955 | } | |
0acf519f | 956 | serial_out(up, UART_EFR, 0); |
1da177e4 LT |
957 | return; |
958 | } | |
959 | ||
960 | /* | |
961 | * Maybe it requires 0xbf to be written to the LCR. | |
962 | * (other ST16C650V2 UARTs, TI16C752A, etc) | |
963 | */ | |
0acf519f | 964 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
1da177e4 LT |
965 | if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) { |
966 | DEBUG_AUTOCONF("EFRv2 "); | |
967 | autoconfig_has_efr(up); | |
968 | return; | |
969 | } | |
970 | ||
971 | /* | |
972 | * Check for a National Semiconductor SuperIO chip. | |
973 | * Attempt to switch to bank 2, read the value of the LOOP bit | |
974 | * from EXCR1. Switch back to bank 0, change it in MCR. Then | |
975 | * switch back to bank 2, read it from EXCR1 again and check | |
976 | * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2 | |
1da177e4 | 977 | */ |
0acf519f | 978 | serial_out(up, UART_LCR, 0); |
1da177e4 | 979 | status1 = serial_in(up, UART_MCR); |
0acf519f | 980 | serial_out(up, UART_LCR, 0xE0); |
1da177e4 LT |
981 | status2 = serial_in(up, 0x02); /* EXCR1 */ |
982 | ||
983 | if (!((status2 ^ status1) & UART_MCR_LOOP)) { | |
0acf519f PG |
984 | serial_out(up, UART_LCR, 0); |
985 | serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP); | |
986 | serial_out(up, UART_LCR, 0xE0); | |
1da177e4 | 987 | status2 = serial_in(up, 0x02); /* EXCR1 */ |
0acf519f PG |
988 | serial_out(up, UART_LCR, 0); |
989 | serial_out(up, UART_MCR, status1); | |
1da177e4 LT |
990 | |
991 | if ((status2 ^ status1) & UART_MCR_LOOP) { | |
857dde2e DW |
992 | unsigned short quot; |
993 | ||
0acf519f | 994 | serial_out(up, UART_LCR, 0xE0); |
857dde2e | 995 | |
b32b19b8 | 996 | quot = serial_dl_read(up); |
857dde2e DW |
997 | quot <<= 3; |
998 | ||
0d0389e5 YK |
999 | if (ns16550a_goto_highspeed(up)) |
1000 | serial_dl_write(up, quot); | |
857dde2e | 1001 | |
0acf519f | 1002 | serial_out(up, UART_LCR, 0); |
1da177e4 | 1003 | |
857dde2e | 1004 | up->port.uartclk = 921600*16; |
1da177e4 LT |
1005 | up->port.type = PORT_NS16550A; |
1006 | up->capabilities |= UART_NATSEMI; | |
1007 | return; | |
1008 | } | |
1009 | } | |
1010 | ||
1011 | /* | |
1012 | * No EFR. Try to detect a TI16750, which only sets bit 5 of | |
1013 | * the IIR when 64 byte FIFO mode is enabled when DLAB is set. | |
1014 | * Try setting it with and without DLAB set. Cheap clones | |
1015 | * set bit 5 without DLAB set. | |
1016 | */ | |
0acf519f PG |
1017 | serial_out(up, UART_LCR, 0); |
1018 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); | |
1da177e4 | 1019 | status1 = serial_in(up, UART_IIR) >> 5; |
0acf519f PG |
1020 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); |
1021 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
1022 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); | |
1da177e4 | 1023 | status2 = serial_in(up, UART_IIR) >> 5; |
0acf519f PG |
1024 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); |
1025 | serial_out(up, UART_LCR, 0); | |
1da177e4 LT |
1026 | |
1027 | DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2); | |
1028 | ||
1029 | if (status1 == 6 && status2 == 7) { | |
1030 | up->port.type = PORT_16750; | |
1031 | up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; | |
1032 | return; | |
1033 | } | |
1034 | ||
1035 | /* | |
1036 | * Try writing and reading the UART_IER_UUE bit (b6). | |
1037 | * If it works, this is probably one of the Xscale platform's | |
1038 | * internal UARTs. | |
1039 | * We're going to explicitly set the UUE bit to 0 before | |
1040 | * trying to write and read a 1 just to make sure it's not | |
1041 | * already a 1 and maybe locked there before we even start start. | |
1042 | */ | |
1043 | iersave = serial_in(up, UART_IER); | |
0acf519f | 1044 | serial_out(up, UART_IER, iersave & ~UART_IER_UUE); |
1da177e4 LT |
1045 | if (!(serial_in(up, UART_IER) & UART_IER_UUE)) { |
1046 | /* | |
1047 | * OK it's in a known zero state, try writing and reading | |
1048 | * without disturbing the current state of the other bits. | |
1049 | */ | |
0acf519f | 1050 | serial_out(up, UART_IER, iersave | UART_IER_UUE); |
1da177e4 LT |
1051 | if (serial_in(up, UART_IER) & UART_IER_UUE) { |
1052 | /* | |
1053 | * It's an Xscale. | |
1054 | * We'll leave the UART_IER_UUE bit set to 1 (enabled). | |
1055 | */ | |
1056 | DEBUG_AUTOCONF("Xscale "); | |
1057 | up->port.type = PORT_XSCALE; | |
5568181f | 1058 | up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE; |
1da177e4 LT |
1059 | return; |
1060 | } | |
1061 | } else { | |
1062 | /* | |
1063 | * If we got here we couldn't force the IER_UUE bit to 0. | |
1064 | * Log it and continue. | |
1065 | */ | |
1066 | DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 "); | |
1067 | } | |
0acf519f | 1068 | serial_out(up, UART_IER, iersave); |
235dae5d | 1069 | |
06315348 SH |
1070 | /* |
1071 | * Exar uarts have EFR in a weird location | |
1072 | */ | |
1073 | if (up->port.flags & UPF_EXAR_EFR) { | |
81db0772 | 1074 | DEBUG_AUTOCONF("Exar XR17D15x "); |
06315348 | 1075 | up->port.type = PORT_XR17D15X; |
81db0772 MS |
1076 | up->capabilities |= UART_CAP_AFE | UART_CAP_EFR | |
1077 | UART_CAP_SLEEP; | |
1078 | ||
1079 | return; | |
06315348 SH |
1080 | } |
1081 | ||
235dae5d PL |
1082 | /* |
1083 | * We distinguish between 16550A and U6 16550A by counting | |
1084 | * how many bytes are in the FIFO. | |
1085 | */ | |
1086 | if (up->port.type == PORT_16550A && size_fifo(up) == 64) { | |
1087 | up->port.type = PORT_U6_16550A; | |
1088 | up->capabilities |= UART_CAP_AFE; | |
1089 | } | |
1da177e4 LT |
1090 | } |
1091 | ||
1092 | /* | |
1093 | * This routine is called by rs_init() to initialize a specific serial | |
1094 | * port. It determines what type of UART chip this serial port is | |
1095 | * using: 8250, 16450, 16550, 16550A. The important question is | |
1096 | * whether or not this UART is a 16550A or not, since this will | |
1097 | * determine whether or not we can use its FIFO features or not. | |
1098 | */ | |
1099 | static void autoconfig(struct uart_8250_port *up, unsigned int probeflags) | |
1100 | { | |
1101 | unsigned char status1, scratch, scratch2, scratch3; | |
1102 | unsigned char save_lcr, save_mcr; | |
dfe42443 | 1103 | struct uart_port *port = &up->port; |
1da177e4 | 1104 | unsigned long flags; |
bd21f551 | 1105 | unsigned int old_capabilities; |
1da177e4 | 1106 | |
dfe42443 | 1107 | if (!port->iobase && !port->mapbase && !port->membase) |
1da177e4 LT |
1108 | return; |
1109 | ||
80647b95 | 1110 | DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ", |
dfe42443 | 1111 | serial_index(port), port->iobase, port->membase); |
1da177e4 LT |
1112 | |
1113 | /* | |
1114 | * We really do need global IRQs disabled here - we're going to | |
1115 | * be frobbing the chips IRQ enable register to see if it exists. | |
1116 | */ | |
dfe42443 | 1117 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 LT |
1118 | |
1119 | up->capabilities = 0; | |
4ba5e35d | 1120 | up->bugs = 0; |
1da177e4 | 1121 | |
dfe42443 | 1122 | if (!(port->flags & UPF_BUGGY_UART)) { |
1da177e4 LT |
1123 | /* |
1124 | * Do a simple existence test first; if we fail this, | |
1125 | * there's no point trying anything else. | |
bd71c182 | 1126 | * |
1da177e4 LT |
1127 | * 0x80 is used as a nonsense port to prevent against |
1128 | * false positives due to ISA bus float. The | |
1129 | * assumption is that 0x80 is a non-existent port; | |
1130 | * which should be safe since include/asm/io.h also | |
1131 | * makes this assumption. | |
1132 | * | |
1133 | * Note: this is safe as long as MCR bit 4 is clear | |
1134 | * and the device is in "PC" mode. | |
1135 | */ | |
0acf519f PG |
1136 | scratch = serial_in(up, UART_IER); |
1137 | serial_out(up, UART_IER, 0); | |
1da177e4 LT |
1138 | #ifdef __i386__ |
1139 | outb(0xff, 0x080); | |
1140 | #endif | |
48212008 TH |
1141 | /* |
1142 | * Mask out IER[7:4] bits for test as some UARTs (e.g. TL | |
1143 | * 16C754B) allow only to modify them if an EFR bit is set. | |
1144 | */ | |
0acf519f PG |
1145 | scratch2 = serial_in(up, UART_IER) & 0x0f; |
1146 | serial_out(up, UART_IER, 0x0F); | |
1da177e4 LT |
1147 | #ifdef __i386__ |
1148 | outb(0, 0x080); | |
1149 | #endif | |
0acf519f PG |
1150 | scratch3 = serial_in(up, UART_IER) & 0x0f; |
1151 | serial_out(up, UART_IER, scratch); | |
1da177e4 LT |
1152 | if (scratch2 != 0 || scratch3 != 0x0F) { |
1153 | /* | |
1154 | * We failed; there's nothing here | |
1155 | */ | |
bd21f551 | 1156 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
1157 | DEBUG_AUTOCONF("IER test failed (%02x, %02x) ", |
1158 | scratch2, scratch3); | |
1159 | goto out; | |
1160 | } | |
1161 | } | |
1162 | ||
1163 | save_mcr = serial_in(up, UART_MCR); | |
1164 | save_lcr = serial_in(up, UART_LCR); | |
1165 | ||
bd71c182 | 1166 | /* |
1da177e4 LT |
1167 | * Check to see if a UART is really there. Certain broken |
1168 | * internal modems based on the Rockwell chipset fail this | |
1169 | * test, because they apparently don't implement the loopback | |
1170 | * test mode. So this test is skipped on the COM 1 through | |
1171 | * COM 4 ports. This *should* be safe, since no board | |
1172 | * manufacturer would be stupid enough to design a board | |
1173 | * that conflicts with COM 1-4 --- we hope! | |
1174 | */ | |
dfe42443 | 1175 | if (!(port->flags & UPF_SKIP_TEST)) { |
0acf519f PG |
1176 | serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A); |
1177 | status1 = serial_in(up, UART_MSR) & 0xF0; | |
1178 | serial_out(up, UART_MCR, save_mcr); | |
1da177e4 | 1179 | if (status1 != 0x90) { |
bd21f551 | 1180 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
1181 | DEBUG_AUTOCONF("LOOP test failed (%02x) ", |
1182 | status1); | |
1183 | goto out; | |
1184 | } | |
1185 | } | |
1186 | ||
1187 | /* | |
1188 | * We're pretty sure there's a port here. Lets find out what | |
1189 | * type of port it is. The IIR top two bits allows us to find | |
6f0d618f | 1190 | * out if it's 8250 or 16450, 16550, 16550A or later. This |
1da177e4 LT |
1191 | * determines what we test for next. |
1192 | * | |
1193 | * We also initialise the EFR (if any) to zero for later. The | |
1194 | * EFR occupies the same register location as the FCR and IIR. | |
1195 | */ | |
0acf519f PG |
1196 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
1197 | serial_out(up, UART_EFR, 0); | |
1198 | serial_out(up, UART_LCR, 0); | |
1da177e4 | 1199 | |
0acf519f | 1200 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); |
1da177e4 LT |
1201 | scratch = serial_in(up, UART_IIR) >> 6; |
1202 | ||
1da177e4 LT |
1203 | switch (scratch) { |
1204 | case 0: | |
1205 | autoconfig_8250(up); | |
1206 | break; | |
1207 | case 1: | |
dfe42443 | 1208 | port->type = PORT_UNKNOWN; |
1da177e4 LT |
1209 | break; |
1210 | case 2: | |
dfe42443 | 1211 | port->type = PORT_16550; |
1da177e4 LT |
1212 | break; |
1213 | case 3: | |
1214 | autoconfig_16550a(up); | |
1215 | break; | |
1216 | } | |
1217 | ||
1218 | #ifdef CONFIG_SERIAL_8250_RSA | |
1219 | /* | |
1220 | * Only probe for RSA ports if we got the region. | |
1221 | */ | |
dfe42443 | 1222 | if (port->type == PORT_16550A && probeflags & PROBE_RSA) { |
1da177e4 LT |
1223 | int i; |
1224 | ||
1225 | for (i = 0 ; i < probe_rsa_count; ++i) { | |
dfe42443 PG |
1226 | if (probe_rsa[i] == port->iobase && __enable_rsa(up)) { |
1227 | port->type = PORT_RSA; | |
1da177e4 LT |
1228 | break; |
1229 | } | |
1230 | } | |
1231 | } | |
1232 | #endif | |
21c614a7 | 1233 | |
0acf519f | 1234 | serial_out(up, UART_LCR, save_lcr); |
1da177e4 | 1235 | |
dfe42443 | 1236 | port->fifosize = uart_config[up->port.type].fifo_size; |
bd21f551 | 1237 | old_capabilities = up->capabilities; |
dfe42443 PG |
1238 | up->capabilities = uart_config[port->type].flags; |
1239 | up->tx_loadsz = uart_config[port->type].tx_loadsz; | |
1da177e4 | 1240 | |
dfe42443 | 1241 | if (port->type == PORT_UNKNOWN) |
bd21f551 | 1242 | goto out_lock; |
1da177e4 LT |
1243 | |
1244 | /* | |
1245 | * Reset the UART. | |
1246 | */ | |
1247 | #ifdef CONFIG_SERIAL_8250_RSA | |
dfe42443 | 1248 | if (port->type == PORT_RSA) |
0acf519f | 1249 | serial_out(up, UART_RSA_FRR, 0); |
1da177e4 | 1250 | #endif |
0acf519f | 1251 | serial_out(up, UART_MCR, save_mcr); |
1da177e4 | 1252 | serial8250_clear_fifos(up); |
40b36daa | 1253 | serial_in(up, UART_RX); |
5c8c755c | 1254 | if (up->capabilities & UART_CAP_UUE) |
0acf519f | 1255 | serial_out(up, UART_IER, UART_IER_UUE); |
5c8c755c | 1256 | else |
0acf519f | 1257 | serial_out(up, UART_IER, 0); |
1da177e4 | 1258 | |
bd21f551 | 1259 | out_lock: |
dfe42443 | 1260 | spin_unlock_irqrestore(&port->lock, flags); |
bd21f551 FL |
1261 | if (up->capabilities != old_capabilities) { |
1262 | printk(KERN_WARNING | |
1263 | "ttyS%d: detected caps %08x should be %08x\n", | |
1264 | serial_index(port), old_capabilities, | |
1265 | up->capabilities); | |
1266 | } | |
1267 | out: | |
1268 | DEBUG_AUTOCONF("iir=%d ", scratch); | |
dfe42443 | 1269 | DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name); |
1da177e4 LT |
1270 | } |
1271 | ||
1272 | static void autoconfig_irq(struct uart_8250_port *up) | |
1273 | { | |
dfe42443 | 1274 | struct uart_port *port = &up->port; |
1da177e4 LT |
1275 | unsigned char save_mcr, save_ier; |
1276 | unsigned char save_ICP = 0; | |
1277 | unsigned int ICP = 0; | |
1278 | unsigned long irqs; | |
1279 | int irq; | |
1280 | ||
dfe42443 PG |
1281 | if (port->flags & UPF_FOURPORT) { |
1282 | ICP = (port->iobase & 0xfe0) | 0x1f; | |
1da177e4 LT |
1283 | save_ICP = inb_p(ICP); |
1284 | outb_p(0x80, ICP); | |
0d263a26 | 1285 | inb_p(ICP); |
1da177e4 LT |
1286 | } |
1287 | ||
1288 | /* forget possible initially masked and pending IRQ */ | |
1289 | probe_irq_off(probe_irq_on()); | |
0acf519f PG |
1290 | save_mcr = serial_in(up, UART_MCR); |
1291 | save_ier = serial_in(up, UART_IER); | |
1292 | serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2); | |
bd71c182 | 1293 | |
1da177e4 | 1294 | irqs = probe_irq_on(); |
0acf519f | 1295 | serial_out(up, UART_MCR, 0); |
6f803cd0 | 1296 | udelay(10); |
dfe42443 | 1297 | if (port->flags & UPF_FOURPORT) { |
0acf519f | 1298 | serial_out(up, UART_MCR, |
1da177e4 LT |
1299 | UART_MCR_DTR | UART_MCR_RTS); |
1300 | } else { | |
0acf519f | 1301 | serial_out(up, UART_MCR, |
1da177e4 LT |
1302 | UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); |
1303 | } | |
0acf519f | 1304 | serial_out(up, UART_IER, 0x0f); /* enable all intrs */ |
0d263a26 PG |
1305 | serial_in(up, UART_LSR); |
1306 | serial_in(up, UART_RX); | |
1307 | serial_in(up, UART_IIR); | |
1308 | serial_in(up, UART_MSR); | |
0acf519f | 1309 | serial_out(up, UART_TX, 0xFF); |
6f803cd0 | 1310 | udelay(20); |
1da177e4 LT |
1311 | irq = probe_irq_off(irqs); |
1312 | ||
0acf519f PG |
1313 | serial_out(up, UART_MCR, save_mcr); |
1314 | serial_out(up, UART_IER, save_ier); | |
1da177e4 | 1315 | |
dfe42443 | 1316 | if (port->flags & UPF_FOURPORT) |
1da177e4 LT |
1317 | outb_p(save_ICP, ICP); |
1318 | ||
dfe42443 | 1319 | port->irq = (irq > 0) ? irq : 0; |
1da177e4 LT |
1320 | } |
1321 | ||
e763b90c RK |
1322 | static inline void __stop_tx(struct uart_8250_port *p) |
1323 | { | |
1324 | if (p->ier & UART_IER_THRI) { | |
1325 | p->ier &= ~UART_IER_THRI; | |
1326 | serial_out(p, UART_IER, p->ier); | |
d74d5d1b | 1327 | serial8250_rpm_put_tx(p); |
e763b90c RK |
1328 | } |
1329 | } | |
1330 | ||
b129a8cc | 1331 | static void serial8250_stop_tx(struct uart_port *port) |
1da177e4 | 1332 | { |
b1261c86 | 1333 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 | 1334 | |
d74d5d1b | 1335 | serial8250_rpm_get(up); |
e763b90c | 1336 | __stop_tx(up); |
1da177e4 LT |
1337 | |
1338 | /* | |
e763b90c | 1339 | * We really want to stop the transmitter from sending. |
1da177e4 | 1340 | */ |
dfe42443 | 1341 | if (port->type == PORT_16C950) { |
1da177e4 LT |
1342 | up->acr |= UART_ACR_TXDIS; |
1343 | serial_icr_write(up, UART_ACR, up->acr); | |
1344 | } | |
d74d5d1b | 1345 | serial8250_rpm_put(up); |
1da177e4 LT |
1346 | } |
1347 | ||
b129a8cc | 1348 | static void serial8250_start_tx(struct uart_port *port) |
1da177e4 | 1349 | { |
b1261c86 | 1350 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 | 1351 | |
d74d5d1b | 1352 | serial8250_rpm_get_tx(up); |
9ee4b83e HK |
1353 | if (up->dma && !serial8250_tx_dma(up)) { |
1354 | return; | |
1355 | } else if (!(up->ier & UART_IER_THRI)) { | |
1da177e4 | 1356 | up->ier |= UART_IER_THRI; |
4fd996a1 | 1357 | serial_port_out(port, UART_IER, up->ier); |
55d3b282 | 1358 | |
67f7654e | 1359 | if (up->bugs & UART_BUG_TXEN) { |
68cb4f8e | 1360 | unsigned char lsr; |
55d3b282 | 1361 | lsr = serial_in(up, UART_LSR); |
ad4c2aa6 | 1362 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; |
a205a56d | 1363 | if (lsr & UART_LSR_TEMT) |
3986fb2b | 1364 | serial8250_tx_chars(up); |
55d3b282 | 1365 | } |
1da177e4 | 1366 | } |
e763b90c | 1367 | |
1da177e4 | 1368 | /* |
e763b90c | 1369 | * Re-enable the transmitter if we disabled it. |
1da177e4 | 1370 | */ |
dfe42443 | 1371 | if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { |
1da177e4 LT |
1372 | up->acr &= ~UART_ACR_TXDIS; |
1373 | serial_icr_write(up, UART_ACR, up->acr); | |
1374 | } | |
1375 | } | |
1376 | ||
234abab1 SAS |
1377 | static void serial8250_throttle(struct uart_port *port) |
1378 | { | |
1379 | port->throttle(port); | |
1380 | } | |
1381 | ||
1382 | static void serial8250_unthrottle(struct uart_port *port) | |
1383 | { | |
1384 | port->unthrottle(port); | |
1385 | } | |
1386 | ||
1da177e4 LT |
1387 | static void serial8250_stop_rx(struct uart_port *port) |
1388 | { | |
b1261c86 | 1389 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 | 1390 | |
d74d5d1b SAS |
1391 | serial8250_rpm_get(up); |
1392 | ||
1da177e4 LT |
1393 | up->ier &= ~UART_IER_RLSI; |
1394 | up->port.read_status_mask &= ~UART_LSR_DR; | |
4fd996a1 | 1395 | serial_port_out(port, UART_IER, up->ier); |
d74d5d1b SAS |
1396 | |
1397 | serial8250_rpm_put(up); | |
1da177e4 LT |
1398 | } |
1399 | ||
1400 | static void serial8250_enable_ms(struct uart_port *port) | |
1401 | { | |
b1261c86 | 1402 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 | 1403 | |
21c614a7 PA |
1404 | /* no MSR capabilities */ |
1405 | if (up->bugs & UART_BUG_NOMSR) | |
1406 | return; | |
1407 | ||
1da177e4 | 1408 | up->ier |= UART_IER_MSI; |
d74d5d1b SAS |
1409 | |
1410 | serial8250_rpm_get(up); | |
4fd996a1 | 1411 | serial_port_out(port, UART_IER, up->ier); |
d74d5d1b | 1412 | serial8250_rpm_put(up); |
1da177e4 LT |
1413 | } |
1414 | ||
0690f41f | 1415 | /* |
3986fb2b | 1416 | * serial8250_rx_chars: processes according to the passed in LSR |
0690f41f PG |
1417 | * value, and returns the remaining LSR bits not handled |
1418 | * by this Rx routine. | |
1419 | */ | |
3986fb2b PG |
1420 | unsigned char |
1421 | serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr) | |
1da177e4 | 1422 | { |
dfe42443 | 1423 | struct uart_port *port = &up->port; |
0690f41f | 1424 | unsigned char ch; |
1da177e4 LT |
1425 | int max_count = 256; |
1426 | char flag; | |
1427 | ||
1428 | do { | |
7500b1f6 | 1429 | if (likely(lsr & UART_LSR_DR)) |
0acf519f | 1430 | ch = serial_in(up, UART_RX); |
7500b1f6 AR |
1431 | else |
1432 | /* | |
1433 | * Intel 82571 has a Serial Over Lan device that will | |
1434 | * set UART_LSR_BI without setting UART_LSR_DR when | |
1435 | * it receives a break. To avoid reading from the | |
1436 | * receive buffer without UART_LSR_DR bit set, we | |
1437 | * just force the read character to be 0 | |
1438 | */ | |
1439 | ch = 0; | |
1440 | ||
1da177e4 | 1441 | flag = TTY_NORMAL; |
dfe42443 | 1442 | port->icount.rx++; |
1da177e4 | 1443 | |
ad4c2aa6 CM |
1444 | lsr |= up->lsr_saved_flags; |
1445 | up->lsr_saved_flags = 0; | |
1da177e4 | 1446 | |
ad4c2aa6 | 1447 | if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { |
1da177e4 LT |
1448 | if (lsr & UART_LSR_BI) { |
1449 | lsr &= ~(UART_LSR_FE | UART_LSR_PE); | |
dfe42443 | 1450 | port->icount.brk++; |
1da177e4 LT |
1451 | /* |
1452 | * We do the SysRQ and SAK checking | |
1453 | * here because otherwise the break | |
1454 | * may get masked by ignore_status_mask | |
1455 | * or read_status_mask. | |
1456 | */ | |
dfe42443 | 1457 | if (uart_handle_break(port)) |
1da177e4 LT |
1458 | goto ignore_char; |
1459 | } else if (lsr & UART_LSR_PE) | |
dfe42443 | 1460 | port->icount.parity++; |
1da177e4 | 1461 | else if (lsr & UART_LSR_FE) |
dfe42443 | 1462 | port->icount.frame++; |
1da177e4 | 1463 | if (lsr & UART_LSR_OE) |
dfe42443 | 1464 | port->icount.overrun++; |
1da177e4 LT |
1465 | |
1466 | /* | |
23907eb8 | 1467 | * Mask off conditions which should be ignored. |
1da177e4 | 1468 | */ |
dfe42443 | 1469 | lsr &= port->read_status_mask; |
1da177e4 LT |
1470 | |
1471 | if (lsr & UART_LSR_BI) { | |
1472 | DEBUG_INTR("handling break...."); | |
1473 | flag = TTY_BREAK; | |
1474 | } else if (lsr & UART_LSR_PE) | |
1475 | flag = TTY_PARITY; | |
1476 | else if (lsr & UART_LSR_FE) | |
1477 | flag = TTY_FRAME; | |
1478 | } | |
dfe42443 | 1479 | if (uart_handle_sysrq_char(port, ch)) |
1da177e4 | 1480 | goto ignore_char; |
05ab3014 | 1481 | |
dfe42443 | 1482 | uart_insert_char(port, lsr, UART_LSR_OE, ch, flag); |
05ab3014 | 1483 | |
6f803cd0 | 1484 | ignore_char: |
0acf519f | 1485 | lsr = serial_in(up, UART_LSR); |
7500b1f6 | 1486 | } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0)); |
dfe42443 | 1487 | spin_unlock(&port->lock); |
2e124b4a | 1488 | tty_flip_buffer_push(&port->state->port); |
dfe42443 | 1489 | spin_lock(&port->lock); |
0690f41f | 1490 | return lsr; |
1da177e4 | 1491 | } |
3986fb2b | 1492 | EXPORT_SYMBOL_GPL(serial8250_rx_chars); |
1da177e4 | 1493 | |
3986fb2b | 1494 | void serial8250_tx_chars(struct uart_8250_port *up) |
1da177e4 | 1495 | { |
dfe42443 PG |
1496 | struct uart_port *port = &up->port; |
1497 | struct circ_buf *xmit = &port->state->xmit; | |
1da177e4 LT |
1498 | int count; |
1499 | ||
dfe42443 PG |
1500 | if (port->x_char) { |
1501 | serial_out(up, UART_TX, port->x_char); | |
1502 | port->icount.tx++; | |
1503 | port->x_char = 0; | |
1da177e4 LT |
1504 | return; |
1505 | } | |
dfe42443 PG |
1506 | if (uart_tx_stopped(port)) { |
1507 | serial8250_stop_tx(port); | |
b129a8cc RK |
1508 | return; |
1509 | } | |
1510 | if (uart_circ_empty(xmit)) { | |
e763b90c | 1511 | __stop_tx(up); |
1da177e4 LT |
1512 | return; |
1513 | } | |
1514 | ||
1515 | count = up->tx_loadsz; | |
1516 | do { | |
1517 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
1518 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
dfe42443 | 1519 | port->icount.tx++; |
1da177e4 LT |
1520 | if (uart_circ_empty(xmit)) |
1521 | break; | |
ebebd49a SH |
1522 | if (up->capabilities & UART_CAP_HFIFO) { |
1523 | if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) != | |
1524 | BOTH_EMPTY) | |
1525 | break; | |
1526 | } | |
1da177e4 LT |
1527 | } while (--count > 0); |
1528 | ||
1529 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
dfe42443 | 1530 | uart_write_wakeup(port); |
1da177e4 LT |
1531 | |
1532 | DEBUG_INTR("THRE..."); | |
1533 | ||
d74d5d1b SAS |
1534 | /* |
1535 | * With RPM enabled, we have to wait once the FIFO is empty before the | |
1536 | * HW can go idle. So we get here once again with empty FIFO and disable | |
1537 | * the interrupt and RPM in __stop_tx() | |
1538 | */ | |
1539 | if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM)) | |
e763b90c | 1540 | __stop_tx(up); |
1da177e4 | 1541 | } |
3986fb2b | 1542 | EXPORT_SYMBOL_GPL(serial8250_tx_chars); |
1da177e4 | 1543 | |
5435d20f | 1544 | /* Caller holds uart port lock */ |
3986fb2b | 1545 | unsigned int serial8250_modem_status(struct uart_8250_port *up) |
1da177e4 | 1546 | { |
dfe42443 | 1547 | struct uart_port *port = &up->port; |
2af7cd68 RK |
1548 | unsigned int status = serial_in(up, UART_MSR); |
1549 | ||
ad4c2aa6 CM |
1550 | status |= up->msr_saved_flags; |
1551 | up->msr_saved_flags = 0; | |
fdc30b3d | 1552 | if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && |
dfe42443 | 1553 | port->state != NULL) { |
2af7cd68 | 1554 | if (status & UART_MSR_TERI) |
dfe42443 | 1555 | port->icount.rng++; |
2af7cd68 | 1556 | if (status & UART_MSR_DDSR) |
dfe42443 | 1557 | port->icount.dsr++; |
2af7cd68 | 1558 | if (status & UART_MSR_DDCD) |
dfe42443 | 1559 | uart_handle_dcd_change(port, status & UART_MSR_DCD); |
2af7cd68 | 1560 | if (status & UART_MSR_DCTS) |
dfe42443 | 1561 | uart_handle_cts_change(port, status & UART_MSR_CTS); |
2af7cd68 | 1562 | |
dfe42443 | 1563 | wake_up_interruptible(&port->state->port.delta_msr_wait); |
2af7cd68 | 1564 | } |
1da177e4 | 1565 | |
2af7cd68 | 1566 | return status; |
1da177e4 | 1567 | } |
3986fb2b | 1568 | EXPORT_SYMBOL_GPL(serial8250_modem_status); |
1da177e4 LT |
1569 | |
1570 | /* | |
1571 | * This handles the interrupt from one port. | |
1572 | */ | |
86b21199 | 1573 | int serial8250_handle_irq(struct uart_port *port, unsigned int iir) |
1da177e4 | 1574 | { |
0690f41f | 1575 | unsigned char status; |
4bf3631c | 1576 | unsigned long flags; |
b1261c86 | 1577 | struct uart_8250_port *up = up_to_u8250p(port); |
9ee4b83e | 1578 | int dma_err = 0; |
86b21199 PG |
1579 | |
1580 | if (iir & UART_IIR_NO_INT) | |
1581 | return 0; | |
45e24601 | 1582 | |
dfe42443 | 1583 | spin_lock_irqsave(&port->lock, flags); |
45e24601 | 1584 | |
4fd996a1 | 1585 | status = serial_port_in(port, UART_LSR); |
1da177e4 LT |
1586 | |
1587 | DEBUG_INTR("status = %x...", status); | |
1588 | ||
9ee4b83e HK |
1589 | if (status & (UART_LSR_DR | UART_LSR_BI)) { |
1590 | if (up->dma) | |
1591 | dma_err = serial8250_rx_dma(up, iir); | |
1592 | ||
1593 | if (!up->dma || dma_err) | |
1594 | status = serial8250_rx_chars(up, status); | |
1595 | } | |
3986fb2b | 1596 | serial8250_modem_status(up); |
b08c9c31 | 1597 | if (!up->dma && (status & UART_LSR_THRE)) |
3986fb2b | 1598 | serial8250_tx_chars(up); |
45e24601 | 1599 | |
dfe42443 | 1600 | spin_unlock_irqrestore(&port->lock, flags); |
86b21199 | 1601 | return 1; |
583d28e9 | 1602 | } |
c7a1bdc5 | 1603 | EXPORT_SYMBOL_GPL(serial8250_handle_irq); |
583d28e9 JI |
1604 | |
1605 | static int serial8250_default_handle_irq(struct uart_port *port) | |
1606 | { | |
d74d5d1b SAS |
1607 | struct uart_8250_port *up = up_to_u8250p(port); |
1608 | unsigned int iir; | |
1609 | int ret; | |
1610 | ||
1611 | serial8250_rpm_get(up); | |
583d28e9 | 1612 | |
d74d5d1b SAS |
1613 | iir = serial_port_in(port, UART_IIR); |
1614 | ret = serial8250_handle_irq(port, iir); | |
1615 | ||
1616 | serial8250_rpm_put(up); | |
1617 | return ret; | |
583d28e9 JI |
1618 | } |
1619 | ||
dc96efb7 MS |
1620 | /* |
1621 | * These Exar UARTs have an extra interrupt indicator that could | |
1622 | * fire for a few unimplemented interrupts. One of which is a | |
1623 | * wakeup event when coming out of sleep. Put this here just | |
1624 | * to be on the safe side that these interrupts don't go unhandled. | |
1625 | */ | |
1626 | static int exar_handle_irq(struct uart_port *port) | |
1627 | { | |
1628 | unsigned char int0, int1, int2, int3; | |
1629 | unsigned int iir = serial_port_in(port, UART_IIR); | |
1630 | int ret; | |
1631 | ||
1632 | ret = serial8250_handle_irq(port, iir); | |
1633 | ||
30fa96a3 MS |
1634 | if ((port->type == PORT_XR17V35X) || |
1635 | (port->type == PORT_XR17D15X)) { | |
dc96efb7 MS |
1636 | int0 = serial_port_in(port, 0x80); |
1637 | int1 = serial_port_in(port, 0x81); | |
1638 | int2 = serial_port_in(port, 0x82); | |
1639 | int3 = serial_port_in(port, 0x83); | |
1640 | } | |
1641 | ||
1642 | return ret; | |
1643 | } | |
1644 | ||
1da177e4 LT |
1645 | /* |
1646 | * This is the serial driver's interrupt routine. | |
1647 | * | |
1648 | * Arjan thinks the old way was overly complex, so it got simplified. | |
1649 | * Alan disagrees, saying that need the complexity to handle the weird | |
1650 | * nature of ISA shared interrupts. (This is a special exception.) | |
1651 | * | |
1652 | * In order to handle ISA shared interrupts properly, we need to check | |
1653 | * that all ports have been serviced, and therefore the ISA interrupt | |
1654 | * line has been de-asserted. | |
1655 | * | |
1656 | * This means we need to loop through all ports. checking that they | |
1657 | * don't have an interrupt pending. | |
1658 | */ | |
7d12e780 | 1659 | static irqreturn_t serial8250_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1660 | { |
1661 | struct irq_info *i = dev_id; | |
1662 | struct list_head *l, *end = NULL; | |
1663 | int pass_counter = 0, handled = 0; | |
1664 | ||
1665 | DEBUG_INTR("serial8250_interrupt(%d)...", irq); | |
1666 | ||
1667 | spin_lock(&i->lock); | |
1668 | ||
1669 | l = i->head; | |
1670 | do { | |
1671 | struct uart_8250_port *up; | |
583d28e9 | 1672 | struct uart_port *port; |
1da177e4 LT |
1673 | |
1674 | up = list_entry(l, struct uart_8250_port, list); | |
583d28e9 | 1675 | port = &up->port; |
1da177e4 | 1676 | |
49b532f9 | 1677 | if (port->handle_irq(port)) { |
1da177e4 | 1678 | handled = 1; |
1da177e4 LT |
1679 | end = NULL; |
1680 | } else if (end == NULL) | |
1681 | end = l; | |
1682 | ||
1683 | l = l->next; | |
1684 | ||
1685 | if (l == i->head && pass_counter++ > PASS_LIMIT) { | |
1686 | /* If we hit this, we're dead. */ | |
cd3ecad1 DD |
1687 | printk_ratelimited(KERN_ERR |
1688 | "serial8250: too much work for irq%d\n", irq); | |
1da177e4 LT |
1689 | break; |
1690 | } | |
1691 | } while (l != end); | |
1692 | ||
1693 | spin_unlock(&i->lock); | |
1694 | ||
1695 | DEBUG_INTR("end.\n"); | |
1696 | ||
1697 | return IRQ_RETVAL(handled); | |
1698 | } | |
1699 | ||
1700 | /* | |
1701 | * To support ISA shared interrupts, we need to have one interrupt | |
1702 | * handler that ensures that the IRQ line has been deasserted | |
1703 | * before returning. Failing to do this will result in the IRQ | |
1704 | * line being stuck active, and, since ISA irqs are edge triggered, | |
1705 | * no more IRQs will be seen. | |
1706 | */ | |
1707 | static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up) | |
1708 | { | |
1709 | spin_lock_irq(&i->lock); | |
1710 | ||
1711 | if (!list_empty(i->head)) { | |
1712 | if (i->head == &up->list) | |
1713 | i->head = i->head->next; | |
1714 | list_del(&up->list); | |
1715 | } else { | |
1716 | BUG_ON(i->head != &up->list); | |
1717 | i->head = NULL; | |
1718 | } | |
1da177e4 | 1719 | spin_unlock_irq(&i->lock); |
25db8ad5 AC |
1720 | /* List empty so throw away the hash node */ |
1721 | if (i->head == NULL) { | |
1722 | hlist_del(&i->node); | |
1723 | kfree(i); | |
1724 | } | |
1da177e4 LT |
1725 | } |
1726 | ||
1727 | static int serial_link_irq_chain(struct uart_8250_port *up) | |
1728 | { | |
25db8ad5 AC |
1729 | struct hlist_head *h; |
1730 | struct hlist_node *n; | |
1731 | struct irq_info *i; | |
40663cc7 | 1732 | int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0; |
1da177e4 | 1733 | |
25db8ad5 AC |
1734 | mutex_lock(&hash_mutex); |
1735 | ||
1736 | h = &irq_lists[up->port.irq % NR_IRQ_HASH]; | |
1737 | ||
1738 | hlist_for_each(n, h) { | |
1739 | i = hlist_entry(n, struct irq_info, node); | |
1740 | if (i->irq == up->port.irq) | |
1741 | break; | |
1742 | } | |
1743 | ||
1744 | if (n == NULL) { | |
1745 | i = kzalloc(sizeof(struct irq_info), GFP_KERNEL); | |
1746 | if (i == NULL) { | |
1747 | mutex_unlock(&hash_mutex); | |
1748 | return -ENOMEM; | |
1749 | } | |
1750 | spin_lock_init(&i->lock); | |
1751 | i->irq = up->port.irq; | |
1752 | hlist_add_head(&i->node, h); | |
1753 | } | |
1754 | mutex_unlock(&hash_mutex); | |
1755 | ||
1da177e4 LT |
1756 | spin_lock_irq(&i->lock); |
1757 | ||
1758 | if (i->head) { | |
1759 | list_add(&up->list, i->head); | |
1760 | spin_unlock_irq(&i->lock); | |
1761 | ||
1762 | ret = 0; | |
1763 | } else { | |
1764 | INIT_LIST_HEAD(&up->list); | |
1765 | i->head = &up->list; | |
1766 | spin_unlock_irq(&i->lock); | |
1c2f0493 | 1767 | irq_flags |= up->port.irqflags; |
1da177e4 LT |
1768 | ret = request_irq(up->port.irq, serial8250_interrupt, |
1769 | irq_flags, "serial", i); | |
1770 | if (ret < 0) | |
1771 | serial_do_unlink(i, up); | |
1772 | } | |
1773 | ||
1774 | return ret; | |
1775 | } | |
1776 | ||
1777 | static void serial_unlink_irq_chain(struct uart_8250_port *up) | |
1778 | { | |
bd2fe272 PG |
1779 | /* |
1780 | * yes, some broken gcc emit "warning: 'i' may be used uninitialized" | |
1781 | * but no, we are not going to take a patch that assigns NULL below. | |
1782 | */ | |
25db8ad5 AC |
1783 | struct irq_info *i; |
1784 | struct hlist_node *n; | |
1785 | struct hlist_head *h; | |
1da177e4 | 1786 | |
25db8ad5 AC |
1787 | mutex_lock(&hash_mutex); |
1788 | ||
1789 | h = &irq_lists[up->port.irq % NR_IRQ_HASH]; | |
1790 | ||
1791 | hlist_for_each(n, h) { | |
1792 | i = hlist_entry(n, struct irq_info, node); | |
1793 | if (i->irq == up->port.irq) | |
1794 | break; | |
1795 | } | |
1796 | ||
1797 | BUG_ON(n == NULL); | |
1da177e4 LT |
1798 | BUG_ON(i->head == NULL); |
1799 | ||
1800 | if (list_empty(i->head)) | |
1801 | free_irq(up->port.irq, i); | |
1802 | ||
1803 | serial_do_unlink(i, up); | |
25db8ad5 | 1804 | mutex_unlock(&hash_mutex); |
1da177e4 LT |
1805 | } |
1806 | ||
1807 | /* | |
1808 | * This function is used to handle ports that do not have an | |
1809 | * interrupt. This doesn't work very well for 16450's, but gives | |
1810 | * barely passable results for a 16550A. (Although at the expense | |
1811 | * of much CPU overhead). | |
1812 | */ | |
1813 | static void serial8250_timeout(unsigned long data) | |
1814 | { | |
1815 | struct uart_8250_port *up = (struct uart_8250_port *)data; | |
1da177e4 | 1816 | |
a0431476 | 1817 | up->port.handle_irq(&up->port); |
54381067 | 1818 | mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port)); |
40b36daa AW |
1819 | } |
1820 | ||
1821 | static void serial8250_backup_timeout(unsigned long data) | |
1822 | { | |
1823 | struct uart_8250_port *up = (struct uart_8250_port *)data; | |
ad4c2aa6 CM |
1824 | unsigned int iir, ier = 0, lsr; |
1825 | unsigned long flags; | |
40b36daa | 1826 | |
dbb3b1ca AC |
1827 | spin_lock_irqsave(&up->port.lock, flags); |
1828 | ||
40b36daa AW |
1829 | /* |
1830 | * Must disable interrupts or else we risk racing with the interrupt | |
1831 | * based handler. | |
1832 | */ | |
d4e33fac | 1833 | if (up->port.irq) { |
40b36daa AW |
1834 | ier = serial_in(up, UART_IER); |
1835 | serial_out(up, UART_IER, 0); | |
1836 | } | |
1da177e4 | 1837 | |
40b36daa AW |
1838 | iir = serial_in(up, UART_IIR); |
1839 | ||
1840 | /* | |
1841 | * This should be a safe test for anyone who doesn't trust the | |
1842 | * IIR bits on their UART, but it's specifically designed for | |
1843 | * the "Diva" UART used on the management processor on many HP | |
1844 | * ia64 and parisc boxes. | |
1845 | */ | |
ad4c2aa6 CM |
1846 | lsr = serial_in(up, UART_LSR); |
1847 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; | |
40b36daa | 1848 | if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) && |
ebd2c8f6 | 1849 | (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) && |
ad4c2aa6 | 1850 | (lsr & UART_LSR_THRE)) { |
40b36daa AW |
1851 | iir &= ~(UART_IIR_ID | UART_IIR_NO_INT); |
1852 | iir |= UART_IIR_THRI; | |
1853 | } | |
1854 | ||
1855 | if (!(iir & UART_IIR_NO_INT)) | |
3986fb2b | 1856 | serial8250_tx_chars(up); |
40b36daa | 1857 | |
d4e33fac | 1858 | if (up->port.irq) |
40b36daa AW |
1859 | serial_out(up, UART_IER, ier); |
1860 | ||
dbb3b1ca AC |
1861 | spin_unlock_irqrestore(&up->port.lock, flags); |
1862 | ||
40b36daa | 1863 | /* Standard timer interval plus 0.2s to keep the port running */ |
6f803cd0 | 1864 | mod_timer(&up->timer, |
54381067 | 1865 | jiffies + uart_poll_timeout(&up->port) + HZ / 5); |
1da177e4 LT |
1866 | } |
1867 | ||
1868 | static unsigned int serial8250_tx_empty(struct uart_port *port) | |
1869 | { | |
b1261c86 | 1870 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 | 1871 | unsigned long flags; |
ad4c2aa6 | 1872 | unsigned int lsr; |
1da177e4 | 1873 | |
d74d5d1b SAS |
1874 | serial8250_rpm_get(up); |
1875 | ||
dfe42443 | 1876 | spin_lock_irqsave(&port->lock, flags); |
4fd996a1 | 1877 | lsr = serial_port_in(port, UART_LSR); |
ad4c2aa6 | 1878 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; |
dfe42443 | 1879 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 | 1880 | |
d74d5d1b SAS |
1881 | serial8250_rpm_put(up); |
1882 | ||
bca47613 | 1883 | return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0; |
1da177e4 LT |
1884 | } |
1885 | ||
1886 | static unsigned int serial8250_get_mctrl(struct uart_port *port) | |
1887 | { | |
b1261c86 | 1888 | struct uart_8250_port *up = up_to_u8250p(port); |
2af7cd68 | 1889 | unsigned int status; |
1da177e4 LT |
1890 | unsigned int ret; |
1891 | ||
d74d5d1b | 1892 | serial8250_rpm_get(up); |
3986fb2b | 1893 | status = serial8250_modem_status(up); |
d74d5d1b | 1894 | serial8250_rpm_put(up); |
1da177e4 LT |
1895 | |
1896 | ret = 0; | |
1897 | if (status & UART_MSR_DCD) | |
1898 | ret |= TIOCM_CAR; | |
1899 | if (status & UART_MSR_RI) | |
1900 | ret |= TIOCM_RNG; | |
1901 | if (status & UART_MSR_DSR) | |
1902 | ret |= TIOCM_DSR; | |
1903 | if (status & UART_MSR_CTS) | |
1904 | ret |= TIOCM_CTS; | |
1905 | return ret; | |
1906 | } | |
1907 | ||
1908 | static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1909 | { | |
b1261c86 | 1910 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 LT |
1911 | unsigned char mcr = 0; |
1912 | ||
1913 | if (mctrl & TIOCM_RTS) | |
1914 | mcr |= UART_MCR_RTS; | |
1915 | if (mctrl & TIOCM_DTR) | |
1916 | mcr |= UART_MCR_DTR; | |
1917 | if (mctrl & TIOCM_OUT1) | |
1918 | mcr |= UART_MCR_OUT1; | |
1919 | if (mctrl & TIOCM_OUT2) | |
1920 | mcr |= UART_MCR_OUT2; | |
1921 | if (mctrl & TIOCM_LOOP) | |
1922 | mcr |= UART_MCR_LOOP; | |
1923 | ||
1924 | mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr; | |
1925 | ||
4fd996a1 | 1926 | serial_port_out(port, UART_MCR, mcr); |
1da177e4 LT |
1927 | } |
1928 | ||
1929 | static void serial8250_break_ctl(struct uart_port *port, int break_state) | |
1930 | { | |
b1261c86 | 1931 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 LT |
1932 | unsigned long flags; |
1933 | ||
d74d5d1b | 1934 | serial8250_rpm_get(up); |
dfe42443 | 1935 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 LT |
1936 | if (break_state == -1) |
1937 | up->lcr |= UART_LCR_SBC; | |
1938 | else | |
1939 | up->lcr &= ~UART_LCR_SBC; | |
4fd996a1 | 1940 | serial_port_out(port, UART_LCR, up->lcr); |
dfe42443 | 1941 | spin_unlock_irqrestore(&port->lock, flags); |
d74d5d1b | 1942 | serial8250_rpm_put(up); |
1da177e4 LT |
1943 | } |
1944 | ||
40b36daa AW |
1945 | /* |
1946 | * Wait for transmitter & holding register to empty | |
1947 | */ | |
b5d674ab | 1948 | static void wait_for_xmitr(struct uart_8250_port *up, int bits) |
40b36daa AW |
1949 | { |
1950 | unsigned int status, tmout = 10000; | |
1951 | ||
1952 | /* Wait up to 10ms for the character(s) to be sent. */ | |
97d303b7 | 1953 | for (;;) { |
40b36daa AW |
1954 | status = serial_in(up, UART_LSR); |
1955 | ||
ad4c2aa6 | 1956 | up->lsr_saved_flags |= status & LSR_SAVE_FLAGS; |
40b36daa | 1957 | |
97d303b7 DD |
1958 | if ((status & bits) == bits) |
1959 | break; | |
40b36daa AW |
1960 | if (--tmout == 0) |
1961 | break; | |
1962 | udelay(1); | |
97d303b7 | 1963 | } |
40b36daa AW |
1964 | |
1965 | /* Wait up to 1s for flow control if necessary */ | |
1966 | if (up->port.flags & UPF_CONS_FLOW) { | |
ad4c2aa6 CM |
1967 | unsigned int tmout; |
1968 | for (tmout = 1000000; tmout; tmout--) { | |
1969 | unsigned int msr = serial_in(up, UART_MSR); | |
1970 | up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; | |
1971 | if (msr & UART_MSR_CTS) | |
1972 | break; | |
40b36daa AW |
1973 | udelay(1); |
1974 | touch_nmi_watchdog(); | |
1975 | } | |
1976 | } | |
1977 | } | |
1978 | ||
f2d937f3 JW |
1979 | #ifdef CONFIG_CONSOLE_POLL |
1980 | /* | |
1981 | * Console polling routines for writing and reading from the uart while | |
1982 | * in an interrupt or debug context. | |
1983 | */ | |
1984 | ||
1985 | static int serial8250_get_poll_char(struct uart_port *port) | |
1986 | { | |
d74d5d1b SAS |
1987 | struct uart_8250_port *up = up_to_u8250p(port); |
1988 | unsigned char lsr; | |
1989 | int status; | |
f2d937f3 | 1990 | |
d74d5d1b | 1991 | serial8250_rpm_get(up); |
f2d937f3 | 1992 | |
d74d5d1b SAS |
1993 | lsr = serial_port_in(port, UART_LSR); |
1994 | ||
1995 | if (!(lsr & UART_LSR_DR)) { | |
1996 | status = NO_POLL_CHAR; | |
1997 | goto out; | |
1998 | } | |
1999 | ||
2000 | status = serial_port_in(port, UART_RX); | |
2001 | out: | |
2002 | serial8250_rpm_put(up); | |
2003 | return status; | |
f2d937f3 JW |
2004 | } |
2005 | ||
2006 | ||
2007 | static void serial8250_put_poll_char(struct uart_port *port, | |
2008 | unsigned char c) | |
2009 | { | |
2010 | unsigned int ier; | |
b1261c86 | 2011 | struct uart_8250_port *up = up_to_u8250p(port); |
f2d937f3 | 2012 | |
d74d5d1b | 2013 | serial8250_rpm_get(up); |
f2d937f3 JW |
2014 | /* |
2015 | * First save the IER then disable the interrupts | |
2016 | */ | |
4fd996a1 | 2017 | ier = serial_port_in(port, UART_IER); |
f2d937f3 | 2018 | if (up->capabilities & UART_CAP_UUE) |
4fd996a1 | 2019 | serial_port_out(port, UART_IER, UART_IER_UUE); |
f2d937f3 | 2020 | else |
4fd996a1 | 2021 | serial_port_out(port, UART_IER, 0); |
f2d937f3 JW |
2022 | |
2023 | wait_for_xmitr(up, BOTH_EMPTY); | |
2024 | /* | |
2025 | * Send the character out. | |
f2d937f3 | 2026 | */ |
4fd996a1 | 2027 | serial_port_out(port, UART_TX, c); |
f2d937f3 JW |
2028 | |
2029 | /* | |
2030 | * Finally, wait for transmitter to become empty | |
2031 | * and restore the IER | |
2032 | */ | |
2033 | wait_for_xmitr(up, BOTH_EMPTY); | |
4fd996a1 | 2034 | serial_port_out(port, UART_IER, ier); |
d74d5d1b | 2035 | serial8250_rpm_put(up); |
f2d937f3 JW |
2036 | } |
2037 | ||
2038 | #endif /* CONFIG_CONSOLE_POLL */ | |
2039 | ||
b99b121b | 2040 | int serial8250_do_startup(struct uart_port *port) |
1da177e4 | 2041 | { |
b1261c86 | 2042 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 | 2043 | unsigned long flags; |
55d3b282 | 2044 | unsigned char lsr, iir; |
1da177e4 LT |
2045 | int retval; |
2046 | ||
65ecc9c0 SY |
2047 | if (port->type == PORT_8250_CIR) |
2048 | return -ENODEV; | |
2049 | ||
9660497c HK |
2050 | if (!port->fifosize) |
2051 | port->fifosize = uart_config[port->type].fifo_size; | |
2052 | if (!up->tx_loadsz) | |
2053 | up->tx_loadsz = uart_config[port->type].tx_loadsz; | |
2054 | if (!up->capabilities) | |
2055 | up->capabilities = uart_config[port->type].flags; | |
1da177e4 LT |
2056 | up->mcr = 0; |
2057 | ||
dfe42443 | 2058 | if (port->iotype != up->cur_iotype) |
b8e7e40a AC |
2059 | set_io_from_upio(port); |
2060 | ||
d74d5d1b | 2061 | serial8250_rpm_get(up); |
dfe42443 | 2062 | if (port->type == PORT_16C950) { |
1da177e4 LT |
2063 | /* Wake up and initialize UART */ |
2064 | up->acr = 0; | |
4fd996a1 PG |
2065 | serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); |
2066 | serial_port_out(port, UART_EFR, UART_EFR_ECB); | |
2067 | serial_port_out(port, UART_IER, 0); | |
2068 | serial_port_out(port, UART_LCR, 0); | |
1da177e4 | 2069 | serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ |
4fd996a1 PG |
2070 | serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); |
2071 | serial_port_out(port, UART_EFR, UART_EFR_ECB); | |
2072 | serial_port_out(port, UART_LCR, 0); | |
1da177e4 LT |
2073 | } |
2074 | ||
2075 | #ifdef CONFIG_SERIAL_8250_RSA | |
2076 | /* | |
2077 | * If this is an RSA port, see if we can kick it up to the | |
2078 | * higher speed clock. | |
2079 | */ | |
2080 | enable_rsa(up); | |
2081 | #endif | |
1da177e4 LT |
2082 | /* |
2083 | * Clear the FIFO buffers and disable them. | |
7f927fcc | 2084 | * (they will be reenabled in set_termios()) |
1da177e4 LT |
2085 | */ |
2086 | serial8250_clear_fifos(up); | |
2087 | ||
2088 | /* | |
2089 | * Clear the interrupt registers. | |
2090 | */ | |
0aa525d1 SAS |
2091 | if (serial_port_in(port, UART_LSR) & UART_LSR_DR) |
2092 | serial_port_in(port, UART_RX); | |
4fd996a1 PG |
2093 | serial_port_in(port, UART_IIR); |
2094 | serial_port_in(port, UART_MSR); | |
1da177e4 LT |
2095 | |
2096 | /* | |
2097 | * At this point, there's no way the LSR could still be 0xff; | |
2098 | * if it is, then bail out, because there's likely no UART | |
2099 | * here. | |
2100 | */ | |
dfe42443 | 2101 | if (!(port->flags & UPF_BUGGY_UART) && |
4fd996a1 | 2102 | (serial_port_in(port, UART_LSR) == 0xff)) { |
7808a4c4 | 2103 | printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n", |
dfe42443 | 2104 | serial_index(port)); |
d74d5d1b SAS |
2105 | retval = -ENODEV; |
2106 | goto out; | |
1da177e4 LT |
2107 | } |
2108 | ||
2109 | /* | |
2110 | * For a XR16C850, we need to set the trigger levels | |
2111 | */ | |
dfe42443 | 2112 | if (port->type == PORT_16850) { |
1da177e4 LT |
2113 | unsigned char fctr; |
2114 | ||
0acf519f | 2115 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
1da177e4 | 2116 | |
0acf519f | 2117 | fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX); |
4fd996a1 PG |
2118 | serial_port_out(port, UART_FCTR, |
2119 | fctr | UART_FCTR_TRGD | UART_FCTR_RX); | |
2120 | serial_port_out(port, UART_TRG, UART_TRG_96); | |
2121 | serial_port_out(port, UART_FCTR, | |
2122 | fctr | UART_FCTR_TRGD | UART_FCTR_TX); | |
2123 | serial_port_out(port, UART_TRG, UART_TRG_96); | |
1da177e4 | 2124 | |
4fd996a1 | 2125 | serial_port_out(port, UART_LCR, 0); |
1da177e4 LT |
2126 | } |
2127 | ||
dfe42443 | 2128 | if (port->irq) { |
01c194d9 | 2129 | unsigned char iir1; |
40b36daa AW |
2130 | /* |
2131 | * Test for UARTs that do not reassert THRE when the | |
2132 | * transmitter is idle and the interrupt has already | |
2133 | * been cleared. Real 16550s should always reassert | |
2134 | * this interrupt whenever the transmitter is idle and | |
2135 | * the interrupt is enabled. Delays are necessary to | |
2136 | * allow register changes to become visible. | |
2137 | */ | |
dfe42443 | 2138 | spin_lock_irqsave(&port->lock, flags); |
1c2f0493 | 2139 | if (up->port.irqflags & IRQF_SHARED) |
dfe42443 | 2140 | disable_irq_nosync(port->irq); |
40b36daa AW |
2141 | |
2142 | wait_for_xmitr(up, UART_LSR_THRE); | |
55e4016d | 2143 | serial_port_out_sync(port, UART_IER, UART_IER_THRI); |
40b36daa | 2144 | udelay(1); /* allow THRE to set */ |
4fd996a1 PG |
2145 | iir1 = serial_port_in(port, UART_IIR); |
2146 | serial_port_out(port, UART_IER, 0); | |
55e4016d | 2147 | serial_port_out_sync(port, UART_IER, UART_IER_THRI); |
40b36daa | 2148 | udelay(1); /* allow a working UART time to re-assert THRE */ |
4fd996a1 PG |
2149 | iir = serial_port_in(port, UART_IIR); |
2150 | serial_port_out(port, UART_IER, 0); | |
40b36daa | 2151 | |
dfe42443 PG |
2152 | if (port->irqflags & IRQF_SHARED) |
2153 | enable_irq(port->irq); | |
2154 | spin_unlock_irqrestore(&port->lock, flags); | |
40b36daa AW |
2155 | |
2156 | /* | |
bc02d15a DW |
2157 | * If the interrupt is not reasserted, or we otherwise |
2158 | * don't trust the iir, setup a timer to kick the UART | |
2159 | * on a regular basis. | |
40b36daa | 2160 | */ |
bc02d15a DW |
2161 | if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) || |
2162 | up->port.flags & UPF_BUG_THRE) { | |
363f66fe | 2163 | up->bugs |= UART_BUG_THRE; |
8440838b DM |
2164 | pr_debug("ttyS%d - using backup timer\n", |
2165 | serial_index(port)); | |
40b36daa AW |
2166 | } |
2167 | } | |
2168 | ||
363f66fe WN |
2169 | /* |
2170 | * The above check will only give an accurate result the first time | |
2171 | * the port is opened so this value needs to be preserved. | |
2172 | */ | |
2173 | if (up->bugs & UART_BUG_THRE) { | |
2174 | up->timer.function = serial8250_backup_timeout; | |
2175 | up->timer.data = (unsigned long)up; | |
2176 | mod_timer(&up->timer, jiffies + | |
54381067 | 2177 | uart_poll_timeout(port) + HZ / 5); |
363f66fe WN |
2178 | } |
2179 | ||
1da177e4 LT |
2180 | /* |
2181 | * If the "interrupt" for this port doesn't correspond with any | |
2182 | * hardware interrupt, we use a timer-based system. The original | |
2183 | * driver used to do this with IRQ0. | |
2184 | */ | |
dfe42443 | 2185 | if (!port->irq) { |
1da177e4 | 2186 | up->timer.data = (unsigned long)up; |
54381067 | 2187 | mod_timer(&up->timer, jiffies + uart_poll_timeout(port)); |
1da177e4 LT |
2188 | } else { |
2189 | retval = serial_link_irq_chain(up); | |
2190 | if (retval) | |
d74d5d1b | 2191 | goto out; |
1da177e4 LT |
2192 | } |
2193 | ||
2194 | /* | |
2195 | * Now, initialize the UART | |
2196 | */ | |
4fd996a1 | 2197 | serial_port_out(port, UART_LCR, UART_LCR_WLEN8); |
1da177e4 | 2198 | |
dfe42443 | 2199 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 | 2200 | if (up->port.flags & UPF_FOURPORT) { |
d4e33fac | 2201 | if (!up->port.irq) |
1da177e4 LT |
2202 | up->port.mctrl |= TIOCM_OUT1; |
2203 | } else | |
2204 | /* | |
2205 | * Most PC uarts need OUT2 raised to enable interrupts. | |
2206 | */ | |
dfe42443 | 2207 | if (port->irq) |
1da177e4 LT |
2208 | up->port.mctrl |= TIOCM_OUT2; |
2209 | ||
dfe42443 | 2210 | serial8250_set_mctrl(port, port->mctrl); |
55d3b282 | 2211 | |
b6adea33 MCC |
2212 | /* Serial over Lan (SoL) hack: |
2213 | Intel 8257x Gigabit ethernet chips have a | |
2214 | 16550 emulation, to be used for Serial Over Lan. | |
2215 | Those chips take a longer time than a normal | |
2216 | serial device to signalize that a transmission | |
2217 | data was queued. Due to that, the above test generally | |
2218 | fails. One solution would be to delay the reading of | |
2219 | iir. However, this is not reliable, since the timeout | |
2220 | is variable. So, let's just don't test if we receive | |
2221 | TX irq. This way, we'll never enable UART_BUG_TXEN. | |
2222 | */ | |
d41a4b51 | 2223 | if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST) |
b6adea33 MCC |
2224 | goto dont_test_tx_en; |
2225 | ||
55d3b282 RK |
2226 | /* |
2227 | * Do a quick test to see if we receive an | |
2228 | * interrupt when we enable the TX irq. | |
2229 | */ | |
4fd996a1 PG |
2230 | serial_port_out(port, UART_IER, UART_IER_THRI); |
2231 | lsr = serial_port_in(port, UART_LSR); | |
2232 | iir = serial_port_in(port, UART_IIR); | |
2233 | serial_port_out(port, UART_IER, 0); | |
55d3b282 RK |
2234 | |
2235 | if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) { | |
67f7654e RK |
2236 | if (!(up->bugs & UART_BUG_TXEN)) { |
2237 | up->bugs |= UART_BUG_TXEN; | |
55d3b282 | 2238 | pr_debug("ttyS%d - enabling bad tx status workarounds\n", |
8440838b | 2239 | serial_index(port)); |
55d3b282 RK |
2240 | } |
2241 | } else { | |
67f7654e | 2242 | up->bugs &= ~UART_BUG_TXEN; |
55d3b282 RK |
2243 | } |
2244 | ||
b6adea33 | 2245 | dont_test_tx_en: |
dfe42443 | 2246 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 | 2247 | |
ad4c2aa6 CM |
2248 | /* |
2249 | * Clear the interrupt registers again for luck, and clear the | |
2250 | * saved flags to avoid getting false values from polling | |
2251 | * routines or the previous session. | |
2252 | */ | |
0aa525d1 SAS |
2253 | if (serial_port_in(port, UART_LSR) & UART_LSR_DR) |
2254 | serial_port_in(port, UART_RX); | |
4fd996a1 PG |
2255 | serial_port_in(port, UART_IIR); |
2256 | serial_port_in(port, UART_MSR); | |
ad4c2aa6 CM |
2257 | up->lsr_saved_flags = 0; |
2258 | up->msr_saved_flags = 0; | |
2259 | ||
9ee4b83e HK |
2260 | /* |
2261 | * Request DMA channels for both RX and TX. | |
2262 | */ | |
2263 | if (up->dma) { | |
2264 | retval = serial8250_request_dma(up); | |
2265 | if (retval) { | |
2266 | pr_warn_ratelimited("ttyS%d - failed to request DMA\n", | |
2267 | serial_index(port)); | |
2268 | up->dma = NULL; | |
2269 | } | |
2270 | } | |
2271 | ||
1da177e4 LT |
2272 | /* |
2273 | * Finally, enable interrupts. Note: Modem status interrupts | |
2274 | * are set via set_termios(), which will be occurring imminently | |
2275 | * anyway, so we don't enable them here. | |
2276 | */ | |
2277 | up->ier = UART_IER_RLSI | UART_IER_RDI; | |
4fd996a1 | 2278 | serial_port_out(port, UART_IER, up->ier); |
1da177e4 | 2279 | |
dfe42443 | 2280 | if (port->flags & UPF_FOURPORT) { |
1da177e4 LT |
2281 | unsigned int icp; |
2282 | /* | |
2283 | * Enable interrupts on the AST Fourport board | |
2284 | */ | |
dfe42443 | 2285 | icp = (port->iobase & 0xfe0) | 0x01f; |
1da177e4 | 2286 | outb_p(0x80, icp); |
0d263a26 | 2287 | inb_p(icp); |
1da177e4 | 2288 | } |
d74d5d1b SAS |
2289 | retval = 0; |
2290 | out: | |
2291 | serial8250_rpm_put(up); | |
2292 | return retval; | |
1da177e4 | 2293 | } |
b99b121b | 2294 | EXPORT_SYMBOL_GPL(serial8250_do_startup); |
1da177e4 | 2295 | |
b99b121b SAS |
2296 | static int serial8250_startup(struct uart_port *port) |
2297 | { | |
2298 | if (port->startup) | |
2299 | return port->startup(port); | |
2300 | return serial8250_do_startup(port); | |
2301 | } | |
2302 | ||
2303 | void serial8250_do_shutdown(struct uart_port *port) | |
1da177e4 | 2304 | { |
b1261c86 | 2305 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 LT |
2306 | unsigned long flags; |
2307 | ||
d74d5d1b | 2308 | serial8250_rpm_get(up); |
1da177e4 LT |
2309 | /* |
2310 | * Disable interrupts from this port | |
2311 | */ | |
2312 | up->ier = 0; | |
4fd996a1 | 2313 | serial_port_out(port, UART_IER, 0); |
1da177e4 | 2314 | |
9ee4b83e HK |
2315 | if (up->dma) |
2316 | serial8250_release_dma(up); | |
2317 | ||
dfe42443 PG |
2318 | spin_lock_irqsave(&port->lock, flags); |
2319 | if (port->flags & UPF_FOURPORT) { | |
1da177e4 | 2320 | /* reset interrupts on the AST Fourport board */ |
dfe42443 PG |
2321 | inb((port->iobase & 0xfe0) | 0x1f); |
2322 | port->mctrl |= TIOCM_OUT1; | |
1da177e4 | 2323 | } else |
dfe42443 | 2324 | port->mctrl &= ~TIOCM_OUT2; |
1da177e4 | 2325 | |
dfe42443 PG |
2326 | serial8250_set_mctrl(port, port->mctrl); |
2327 | spin_unlock_irqrestore(&port->lock, flags); | |
1da177e4 LT |
2328 | |
2329 | /* | |
2330 | * Disable break condition and FIFOs | |
2331 | */ | |
4fd996a1 PG |
2332 | serial_port_out(port, UART_LCR, |
2333 | serial_port_in(port, UART_LCR) & ~UART_LCR_SBC); | |
1da177e4 LT |
2334 | serial8250_clear_fifos(up); |
2335 | ||
2336 | #ifdef CONFIG_SERIAL_8250_RSA | |
2337 | /* | |
2338 | * Reset the RSA board back to 115kbps compat mode. | |
2339 | */ | |
2340 | disable_rsa(up); | |
2341 | #endif | |
2342 | ||
2343 | /* | |
2344 | * Read data port to reset things, and then unlink from | |
2345 | * the IRQ chain. | |
2346 | */ | |
0aa525d1 SAS |
2347 | if (serial_port_in(port, UART_LSR) & UART_LSR_DR) |
2348 | serial_port_in(port, UART_RX); | |
d74d5d1b | 2349 | serial8250_rpm_put(up); |
1da177e4 | 2350 | |
40b36daa AW |
2351 | del_timer_sync(&up->timer); |
2352 | up->timer.function = serial8250_timeout; | |
dfe42443 | 2353 | if (port->irq) |
1da177e4 LT |
2354 | serial_unlink_irq_chain(up); |
2355 | } | |
b99b121b SAS |
2356 | EXPORT_SYMBOL_GPL(serial8250_do_shutdown); |
2357 | ||
2358 | static void serial8250_shutdown(struct uart_port *port) | |
2359 | { | |
2360 | if (port->shutdown) | |
2361 | port->shutdown(port); | |
2362 | else | |
2363 | serial8250_do_shutdown(port); | |
2364 | } | |
1da177e4 LT |
2365 | |
2366 | static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud) | |
2367 | { | |
2368 | unsigned int quot; | |
2369 | ||
2370 | /* | |
2371 | * Handle magic divisors for baud rates above baud_base on | |
2372 | * SMSC SuperIO chips. | |
2373 | */ | |
2374 | if ((port->flags & UPF_MAGIC_MULTIPLIER) && | |
2375 | baud == (port->uartclk/4)) | |
2376 | quot = 0x8001; | |
2377 | else if ((port->flags & UPF_MAGIC_MULTIPLIER) && | |
2378 | baud == (port->uartclk/8)) | |
2379 | quot = 0x8002; | |
2380 | else | |
2381 | quot = uart_get_divisor(port, baud); | |
2382 | ||
2383 | return quot; | |
2384 | } | |
2385 | ||
235dae5d PL |
2386 | void |
2387 | serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios, | |
2388 | struct ktermios *old) | |
1da177e4 | 2389 | { |
b1261c86 | 2390 | struct uart_8250_port *up = up_to_u8250p(port); |
aef9a7bd | 2391 | unsigned char cval; |
1da177e4 LT |
2392 | unsigned long flags; |
2393 | unsigned int baud, quot; | |
2394 | ||
2395 | switch (termios->c_cflag & CSIZE) { | |
2396 | case CS5: | |
0a8b80c5 | 2397 | cval = UART_LCR_WLEN5; |
1da177e4 LT |
2398 | break; |
2399 | case CS6: | |
0a8b80c5 | 2400 | cval = UART_LCR_WLEN6; |
1da177e4 LT |
2401 | break; |
2402 | case CS7: | |
0a8b80c5 | 2403 | cval = UART_LCR_WLEN7; |
1da177e4 LT |
2404 | break; |
2405 | default: | |
2406 | case CS8: | |
0a8b80c5 | 2407 | cval = UART_LCR_WLEN8; |
1da177e4 LT |
2408 | break; |
2409 | } | |
2410 | ||
2411 | if (termios->c_cflag & CSTOPB) | |
0a8b80c5 | 2412 | cval |= UART_LCR_STOP; |
eb26dfe8 | 2413 | if (termios->c_cflag & PARENB) { |
1da177e4 | 2414 | cval |= UART_LCR_PARITY; |
eb26dfe8 | 2415 | if (up->bugs & UART_BUG_PARITY) |
aef9a7bd | 2416 | up->fifo_bug = true; |
eb26dfe8 | 2417 | } |
1da177e4 LT |
2418 | if (!(termios->c_cflag & PARODD)) |
2419 | cval |= UART_LCR_EPAR; | |
2420 | #ifdef CMSPAR | |
2421 | if (termios->c_cflag & CMSPAR) | |
2422 | cval |= UART_LCR_SPAR; | |
2423 | #endif | |
2424 | ||
2425 | /* | |
2426 | * Ask the core to calculate the divisor for us. | |
2427 | */ | |
24d481ec AV |
2428 | baud = uart_get_baud_rate(port, termios, old, |
2429 | port->uartclk / 16 / 0xffff, | |
2430 | port->uartclk / 16); | |
1da177e4 LT |
2431 | quot = serial8250_get_divisor(port, baud); |
2432 | ||
2433 | /* | |
4ba5e35d | 2434 | * Oxford Semi 952 rev B workaround |
1da177e4 | 2435 | */ |
4ba5e35d | 2436 | if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0) |
3e8d4e20 | 2437 | quot++; |
1da177e4 | 2438 | |
dfe42443 | 2439 | if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) { |
aef9a7bd YY |
2440 | /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */ |
2441 | if ((baud < 2400 && !up->dma) || up->fifo_bug) { | |
2442 | up->fcr &= ~UART_FCR_TRIGGER_MASK; | |
2443 | up->fcr |= UART_FCR_TRIGGER_1; | |
f9a9111b | 2444 | } |
1da177e4 LT |
2445 | } |
2446 | ||
2447 | /* | |
2448 | * MCR-based auto flow control. When AFE is enabled, RTS will be | |
2449 | * deasserted when the receive FIFO contains more characters than | |
2450 | * the trigger, or the MCR RTS bit is cleared. In the case where | |
2451 | * the remote UART is not using CTS auto flow control, we must | |
2452 | * have sufficient FIFO entries for the latency of the remote | |
a6eec92e | 2453 | * UART to respond. IOW, at least 32 bytes of FIFO. |
1da177e4 | 2454 | */ |
a6eec92e | 2455 | if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) { |
1da177e4 LT |
2456 | up->mcr &= ~UART_MCR_AFE; |
2457 | if (termios->c_cflag & CRTSCTS) | |
2458 | up->mcr |= UART_MCR_AFE; | |
2459 | } | |
2460 | ||
2461 | /* | |
2462 | * Ok, we're now changing the port state. Do it with | |
2463 | * interrupts disabled. | |
2464 | */ | |
d74d5d1b | 2465 | serial8250_rpm_get(up); |
dfe42443 | 2466 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 LT |
2467 | |
2468 | /* | |
2469 | * Update the per-port timeout. | |
2470 | */ | |
2471 | uart_update_timeout(port, termios->c_cflag, baud); | |
2472 | ||
dfe42443 | 2473 | port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; |
1da177e4 | 2474 | if (termios->c_iflag & INPCK) |
dfe42443 | 2475 | port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; |
ef8b9ddc | 2476 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
dfe42443 | 2477 | port->read_status_mask |= UART_LSR_BI; |
1da177e4 LT |
2478 | |
2479 | /* | |
2480 | * Characteres to ignore | |
2481 | */ | |
dfe42443 | 2482 | port->ignore_status_mask = 0; |
1da177e4 | 2483 | if (termios->c_iflag & IGNPAR) |
dfe42443 | 2484 | port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; |
1da177e4 | 2485 | if (termios->c_iflag & IGNBRK) { |
dfe42443 | 2486 | port->ignore_status_mask |= UART_LSR_BI; |
1da177e4 LT |
2487 | /* |
2488 | * If we're ignoring parity and break indicators, | |
2489 | * ignore overruns too (for real raw support). | |
2490 | */ | |
2491 | if (termios->c_iflag & IGNPAR) | |
dfe42443 | 2492 | port->ignore_status_mask |= UART_LSR_OE; |
1da177e4 LT |
2493 | } |
2494 | ||
2495 | /* | |
2496 | * ignore all characters if CREAD is not set | |
2497 | */ | |
2498 | if ((termios->c_cflag & CREAD) == 0) | |
dfe42443 | 2499 | port->ignore_status_mask |= UART_LSR_DR; |
1da177e4 LT |
2500 | |
2501 | /* | |
2502 | * CTS flow control flag and modem status interrupts | |
2503 | */ | |
f8b372a1 | 2504 | up->ier &= ~UART_IER_MSI; |
21c614a7 PA |
2505 | if (!(up->bugs & UART_BUG_NOMSR) && |
2506 | UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
1da177e4 LT |
2507 | up->ier |= UART_IER_MSI; |
2508 | if (up->capabilities & UART_CAP_UUE) | |
4539c24f SW |
2509 | up->ier |= UART_IER_UUE; |
2510 | if (up->capabilities & UART_CAP_RTOIE) | |
2511 | up->ier |= UART_IER_RTOIE; | |
1da177e4 | 2512 | |
4fd996a1 | 2513 | serial_port_out(port, UART_IER, up->ier); |
1da177e4 LT |
2514 | |
2515 | if (up->capabilities & UART_CAP_EFR) { | |
2516 | unsigned char efr = 0; | |
2517 | /* | |
2518 | * TI16C752/Startech hardware flow control. FIXME: | |
2519 | * - TI16C752 requires control thresholds to be set. | |
2520 | * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled. | |
2521 | */ | |
2522 | if (termios->c_cflag & CRTSCTS) | |
2523 | efr |= UART_EFR_CTS; | |
2524 | ||
4fd996a1 | 2525 | serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); |
dfe42443 | 2526 | if (port->flags & UPF_EXAR_EFR) |
4fd996a1 | 2527 | serial_port_out(port, UART_XR_EFR, efr); |
06315348 | 2528 | else |
4fd996a1 | 2529 | serial_port_out(port, UART_EFR, efr); |
1da177e4 LT |
2530 | } |
2531 | ||
255341c6 | 2532 | /* Workaround to enable 115200 baud on OMAP1510 internal ports */ |
54ec52b6 | 2533 | if (is_omap1510_8250(up)) { |
255341c6 JM |
2534 | if (baud == 115200) { |
2535 | quot = 1; | |
4fd996a1 | 2536 | serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1); |
255341c6 | 2537 | } else |
4fd996a1 | 2538 | serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0); |
255341c6 | 2539 | } |
255341c6 | 2540 | |
4fd996a1 PG |
2541 | /* |
2542 | * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2, | |
2543 | * otherwise just set DLAB | |
2544 | */ | |
2545 | if (up->capabilities & UART_NATSEMI) | |
2546 | serial_port_out(port, UART_LCR, 0xe0); | |
2547 | else | |
2548 | serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB); | |
1da177e4 | 2549 | |
b32b19b8 | 2550 | serial_dl_write(up, quot); |
1da177e4 | 2551 | |
45a7bd63 JS |
2552 | /* |
2553 | * XR17V35x UARTs have an extra fractional divisor register (DLD) | |
2554 | * | |
2555 | * We need to recalculate all of the registers, because DLM and DLL | |
2556 | * are already rounded to a whole integer. | |
2557 | * | |
2558 | * When recalculating we use a 32x clock instead of a 16x clock to | |
2559 | * allow 1-bit for rounding in the fractional part. | |
2560 | */ | |
2561 | if (up->port.type == PORT_XR17V35X) { | |
2562 | unsigned int baud_x32 = (port->uartclk * 2) / baud; | |
2563 | u16 quot = baud_x32 / 32; | |
2564 | u8 quot_frac = DIV_ROUND_CLOSEST(baud_x32 % 32, 2); | |
2565 | ||
2566 | serial_dl_write(up, quot); | |
2567 | serial_port_out(port, 0x2, quot_frac & 0xf); | |
2568 | } | |
2569 | ||
1da177e4 LT |
2570 | /* |
2571 | * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR | |
2572 | * is written without DLAB set, this mode will be disabled. | |
2573 | */ | |
dfe42443 | 2574 | if (port->type == PORT_16750) |
aef9a7bd | 2575 | serial_port_out(port, UART_FCR, up->fcr); |
1da177e4 | 2576 | |
4fd996a1 | 2577 | serial_port_out(port, UART_LCR, cval); /* reset DLAB */ |
1da177e4 | 2578 | up->lcr = cval; /* Save LCR */ |
dfe42443 | 2579 | if (port->type != PORT_16750) { |
4fd996a1 | 2580 | /* emulated UARTs (Lucent Venus 167x) need two steps */ |
aef9a7bd | 2581 | if (up->fcr & UART_FCR_ENABLE_FIFO) |
4fd996a1 | 2582 | serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO); |
aef9a7bd | 2583 | serial_port_out(port, UART_FCR, up->fcr); /* set fcr */ |
1da177e4 | 2584 | } |
dfe42443 PG |
2585 | serial8250_set_mctrl(port, port->mctrl); |
2586 | spin_unlock_irqrestore(&port->lock, flags); | |
d74d5d1b SAS |
2587 | serial8250_rpm_put(up); |
2588 | ||
e991a2bd AC |
2589 | /* Don't rewrite B0 */ |
2590 | if (tty_termios_baud_rate(termios)) | |
2591 | tty_termios_encode_baud_rate(termios, baud, baud); | |
1da177e4 | 2592 | } |
235dae5d PL |
2593 | EXPORT_SYMBOL(serial8250_do_set_termios); |
2594 | ||
2595 | static void | |
2596 | serial8250_set_termios(struct uart_port *port, struct ktermios *termios, | |
2597 | struct ktermios *old) | |
2598 | { | |
2599 | if (port->set_termios) | |
2600 | port->set_termios(port, termios, old); | |
2601 | else | |
2602 | serial8250_do_set_termios(port, termios, old); | |
2603 | } | |
1da177e4 | 2604 | |
dc77f161 | 2605 | static void |
a0821df6 | 2606 | serial8250_set_ldisc(struct uart_port *port, int new) |
dc77f161 | 2607 | { |
a0821df6 | 2608 | if (new == N_PPS) { |
dc77f161 RG |
2609 | port->flags |= UPF_HARDPPS_CD; |
2610 | serial8250_enable_ms(port); | |
2611 | } else | |
2612 | port->flags &= ~UPF_HARDPPS_CD; | |
2613 | } | |
2614 | ||
c161afe9 ML |
2615 | |
2616 | void serial8250_do_pm(struct uart_port *port, unsigned int state, | |
2617 | unsigned int oldstate) | |
1da177e4 | 2618 | { |
b1261c86 | 2619 | struct uart_8250_port *p = up_to_u8250p(port); |
1da177e4 LT |
2620 | |
2621 | serial8250_set_sleep(p, state != 0); | |
c161afe9 ML |
2622 | } |
2623 | EXPORT_SYMBOL(serial8250_do_pm); | |
1da177e4 | 2624 | |
c161afe9 ML |
2625 | static void |
2626 | serial8250_pm(struct uart_port *port, unsigned int state, | |
2627 | unsigned int oldstate) | |
2628 | { | |
2629 | if (port->pm) | |
2630 | port->pm(port, state, oldstate); | |
2631 | else | |
2632 | serial8250_do_pm(port, state, oldstate); | |
1da177e4 LT |
2633 | } |
2634 | ||
f2eda27d RK |
2635 | static unsigned int serial8250_port_size(struct uart_8250_port *pt) |
2636 | { | |
2637 | if (pt->port.iotype == UPIO_AU) | |
b2b13cdf | 2638 | return 0x1000; |
54ec52b6 | 2639 | if (is_omap1_8250(pt)) |
f2eda27d | 2640 | return 0x16 << pt->port.regshift; |
54ec52b6 | 2641 | |
f2eda27d RK |
2642 | return 8 << pt->port.regshift; |
2643 | } | |
2644 | ||
1da177e4 LT |
2645 | /* |
2646 | * Resource handling. | |
2647 | */ | |
2648 | static int serial8250_request_std_resource(struct uart_8250_port *up) | |
2649 | { | |
f2eda27d | 2650 | unsigned int size = serial8250_port_size(up); |
dfe42443 | 2651 | struct uart_port *port = &up->port; |
1da177e4 LT |
2652 | int ret = 0; |
2653 | ||
dfe42443 | 2654 | switch (port->iotype) { |
85835f44 | 2655 | case UPIO_AU: |
0b30d668 SS |
2656 | case UPIO_TSI: |
2657 | case UPIO_MEM32: | |
1da177e4 | 2658 | case UPIO_MEM: |
dfe42443 | 2659 | if (!port->mapbase) |
1da177e4 LT |
2660 | break; |
2661 | ||
dfe42443 | 2662 | if (!request_mem_region(port->mapbase, size, "serial")) { |
1da177e4 LT |
2663 | ret = -EBUSY; |
2664 | break; | |
2665 | } | |
2666 | ||
dfe42443 PG |
2667 | if (port->flags & UPF_IOREMAP) { |
2668 | port->membase = ioremap_nocache(port->mapbase, size); | |
2669 | if (!port->membase) { | |
2670 | release_mem_region(port->mapbase, size); | |
1da177e4 LT |
2671 | ret = -ENOMEM; |
2672 | } | |
2673 | } | |
2674 | break; | |
2675 | ||
2676 | case UPIO_HUB6: | |
2677 | case UPIO_PORT: | |
dfe42443 | 2678 | if (!request_region(port->iobase, size, "serial")) |
1da177e4 LT |
2679 | ret = -EBUSY; |
2680 | break; | |
2681 | } | |
2682 | return ret; | |
2683 | } | |
2684 | ||
2685 | static void serial8250_release_std_resource(struct uart_8250_port *up) | |
2686 | { | |
f2eda27d | 2687 | unsigned int size = serial8250_port_size(up); |
dfe42443 | 2688 | struct uart_port *port = &up->port; |
1da177e4 | 2689 | |
dfe42443 | 2690 | switch (port->iotype) { |
85835f44 | 2691 | case UPIO_AU: |
0b30d668 SS |
2692 | case UPIO_TSI: |
2693 | case UPIO_MEM32: | |
1da177e4 | 2694 | case UPIO_MEM: |
dfe42443 | 2695 | if (!port->mapbase) |
1da177e4 LT |
2696 | break; |
2697 | ||
dfe42443 PG |
2698 | if (port->flags & UPF_IOREMAP) { |
2699 | iounmap(port->membase); | |
2700 | port->membase = NULL; | |
1da177e4 LT |
2701 | } |
2702 | ||
dfe42443 | 2703 | release_mem_region(port->mapbase, size); |
1da177e4 LT |
2704 | break; |
2705 | ||
2706 | case UPIO_HUB6: | |
2707 | case UPIO_PORT: | |
dfe42443 | 2708 | release_region(port->iobase, size); |
1da177e4 LT |
2709 | break; |
2710 | } | |
2711 | } | |
2712 | ||
2713 | static int serial8250_request_rsa_resource(struct uart_8250_port *up) | |
2714 | { | |
2715 | unsigned long start = UART_RSA_BASE << up->port.regshift; | |
2716 | unsigned int size = 8 << up->port.regshift; | |
dfe42443 | 2717 | struct uart_port *port = &up->port; |
0b30d668 | 2718 | int ret = -EINVAL; |
1da177e4 | 2719 | |
dfe42443 | 2720 | switch (port->iotype) { |
1da177e4 LT |
2721 | case UPIO_HUB6: |
2722 | case UPIO_PORT: | |
dfe42443 | 2723 | start += port->iobase; |
0b30d668 SS |
2724 | if (request_region(start, size, "serial-rsa")) |
2725 | ret = 0; | |
2726 | else | |
1da177e4 LT |
2727 | ret = -EBUSY; |
2728 | break; | |
2729 | } | |
2730 | ||
2731 | return ret; | |
2732 | } | |
2733 | ||
2734 | static void serial8250_release_rsa_resource(struct uart_8250_port *up) | |
2735 | { | |
2736 | unsigned long offset = UART_RSA_BASE << up->port.regshift; | |
2737 | unsigned int size = 8 << up->port.regshift; | |
dfe42443 | 2738 | struct uart_port *port = &up->port; |
1da177e4 | 2739 | |
dfe42443 | 2740 | switch (port->iotype) { |
1da177e4 LT |
2741 | case UPIO_HUB6: |
2742 | case UPIO_PORT: | |
dfe42443 | 2743 | release_region(port->iobase + offset, size); |
1da177e4 LT |
2744 | break; |
2745 | } | |
2746 | } | |
2747 | ||
2748 | static void serial8250_release_port(struct uart_port *port) | |
2749 | { | |
b1261c86 | 2750 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 LT |
2751 | |
2752 | serial8250_release_std_resource(up); | |
dfe42443 | 2753 | if (port->type == PORT_RSA) |
1da177e4 LT |
2754 | serial8250_release_rsa_resource(up); |
2755 | } | |
2756 | ||
2757 | static int serial8250_request_port(struct uart_port *port) | |
2758 | { | |
b1261c86 | 2759 | struct uart_8250_port *up = up_to_u8250p(port); |
65ecc9c0 SY |
2760 | int ret; |
2761 | ||
2762 | if (port->type == PORT_8250_CIR) | |
2763 | return -ENODEV; | |
1da177e4 LT |
2764 | |
2765 | ret = serial8250_request_std_resource(up); | |
dfe42443 | 2766 | if (ret == 0 && port->type == PORT_RSA) { |
1da177e4 LT |
2767 | ret = serial8250_request_rsa_resource(up); |
2768 | if (ret < 0) | |
2769 | serial8250_release_std_resource(up); | |
2770 | } | |
2771 | ||
2772 | return ret; | |
2773 | } | |
2774 | ||
aef9a7bd YY |
2775 | static int fcr_get_rxtrig_bytes(struct uart_8250_port *up) |
2776 | { | |
2777 | const struct serial8250_config *conf_type = &uart_config[up->port.type]; | |
2778 | unsigned char bytes; | |
2779 | ||
2780 | bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)]; | |
2781 | ||
2782 | return bytes ? bytes : -EOPNOTSUPP; | |
2783 | } | |
2784 | ||
2785 | static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes) | |
2786 | { | |
2787 | const struct serial8250_config *conf_type = &uart_config[up->port.type]; | |
2788 | int i; | |
2789 | ||
2790 | if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)]) | |
2791 | return -EOPNOTSUPP; | |
2792 | ||
2793 | for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) { | |
2794 | if (bytes < conf_type->rxtrig_bytes[i]) | |
2795 | /* Use the nearest lower value */ | |
2796 | return (--i) << UART_FCR_R_TRIG_SHIFT; | |
2797 | } | |
2798 | ||
2799 | return UART_FCR_R_TRIG_11; | |
2800 | } | |
2801 | ||
2802 | static int do_get_rxtrig(struct tty_port *port) | |
2803 | { | |
2804 | struct uart_state *state = container_of(port, struct uart_state, port); | |
2805 | struct uart_port *uport = state->uart_port; | |
2806 | struct uart_8250_port *up = | |
2807 | container_of(uport, struct uart_8250_port, port); | |
2808 | ||
2809 | if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1) | |
2810 | return -EINVAL; | |
2811 | ||
2812 | return fcr_get_rxtrig_bytes(up); | |
2813 | } | |
2814 | ||
2815 | static int do_serial8250_get_rxtrig(struct tty_port *port) | |
2816 | { | |
2817 | int rxtrig_bytes; | |
2818 | ||
2819 | mutex_lock(&port->mutex); | |
2820 | rxtrig_bytes = do_get_rxtrig(port); | |
2821 | mutex_unlock(&port->mutex); | |
2822 | ||
2823 | return rxtrig_bytes; | |
2824 | } | |
2825 | ||
2826 | static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev, | |
2827 | struct device_attribute *attr, char *buf) | |
2828 | { | |
2829 | struct tty_port *port = dev_get_drvdata(dev); | |
2830 | int rxtrig_bytes; | |
2831 | ||
2832 | rxtrig_bytes = do_serial8250_get_rxtrig(port); | |
2833 | if (rxtrig_bytes < 0) | |
2834 | return rxtrig_bytes; | |
2835 | ||
2836 | return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes); | |
2837 | } | |
2838 | ||
2839 | static int do_set_rxtrig(struct tty_port *port, unsigned char bytes) | |
2840 | { | |
2841 | struct uart_state *state = container_of(port, struct uart_state, port); | |
2842 | struct uart_port *uport = state->uart_port; | |
2843 | struct uart_8250_port *up = | |
2844 | container_of(uport, struct uart_8250_port, port); | |
2845 | int rxtrig; | |
2846 | ||
2847 | if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 || | |
2848 | up->fifo_bug) | |
2849 | return -EINVAL; | |
2850 | ||
2851 | rxtrig = bytes_to_fcr_rxtrig(up, bytes); | |
2852 | if (rxtrig < 0) | |
2853 | return rxtrig; | |
2854 | ||
2855 | serial8250_clear_fifos(up); | |
2856 | up->fcr &= ~UART_FCR_TRIGGER_MASK; | |
2857 | up->fcr |= (unsigned char)rxtrig; | |
2858 | serial_out(up, UART_FCR, up->fcr); | |
2859 | return 0; | |
2860 | } | |
2861 | ||
2862 | static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes) | |
2863 | { | |
2864 | int ret; | |
2865 | ||
2866 | mutex_lock(&port->mutex); | |
2867 | ret = do_set_rxtrig(port, bytes); | |
2868 | mutex_unlock(&port->mutex); | |
2869 | ||
2870 | return ret; | |
2871 | } | |
2872 | ||
2873 | static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev, | |
2874 | struct device_attribute *attr, const char *buf, size_t count) | |
2875 | { | |
2876 | struct tty_port *port = dev_get_drvdata(dev); | |
2877 | unsigned char bytes; | |
2878 | int ret; | |
2879 | ||
2880 | if (!count) | |
2881 | return -EINVAL; | |
2882 | ||
2883 | ret = kstrtou8(buf, 10, &bytes); | |
2884 | if (ret < 0) | |
2885 | return ret; | |
2886 | ||
2887 | ret = do_serial8250_set_rxtrig(port, bytes); | |
2888 | if (ret < 0) | |
2889 | return ret; | |
2890 | ||
2891 | return count; | |
2892 | } | |
2893 | ||
2894 | static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP, | |
2895 | serial8250_get_attr_rx_trig_bytes, | |
2896 | serial8250_set_attr_rx_trig_bytes); | |
2897 | ||
2898 | static struct attribute *serial8250_dev_attrs[] = { | |
2899 | &dev_attr_rx_trig_bytes.attr, | |
2900 | NULL, | |
2901 | }; | |
2902 | ||
2903 | static struct attribute_group serial8250_dev_attr_group = { | |
2904 | .attrs = serial8250_dev_attrs, | |
2905 | }; | |
2906 | ||
2907 | static void register_dev_spec_attr_grp(struct uart_8250_port *up) | |
2908 | { | |
2909 | const struct serial8250_config *conf_type = &uart_config[up->port.type]; | |
2910 | ||
2911 | if (conf_type->rxtrig_bytes[0]) | |
2912 | up->port.attr_group = &serial8250_dev_attr_group; | |
2913 | } | |
2914 | ||
1da177e4 LT |
2915 | static void serial8250_config_port(struct uart_port *port, int flags) |
2916 | { | |
b1261c86 | 2917 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 LT |
2918 | int probeflags = PROBE_ANY; |
2919 | int ret; | |
2920 | ||
65ecc9c0 SY |
2921 | if (port->type == PORT_8250_CIR) |
2922 | return; | |
2923 | ||
1da177e4 LT |
2924 | /* |
2925 | * Find the region that we can probe for. This in turn | |
2926 | * tells us whether we can probe for the type of port. | |
2927 | */ | |
2928 | ret = serial8250_request_std_resource(up); | |
2929 | if (ret < 0) | |
2930 | return; | |
2931 | ||
2932 | ret = serial8250_request_rsa_resource(up); | |
2933 | if (ret < 0) | |
2934 | probeflags &= ~PROBE_RSA; | |
2935 | ||
dfe42443 | 2936 | if (port->iotype != up->cur_iotype) |
b8e7e40a AC |
2937 | set_io_from_upio(port); |
2938 | ||
1da177e4 LT |
2939 | if (flags & UART_CONFIG_TYPE) |
2940 | autoconfig(up, probeflags); | |
b2b13cdf | 2941 | |
b2b13cdf | 2942 | /* if access method is AU, it is a 16550 with a quirk */ |
dfe42443 | 2943 | if (port->type == PORT_16550A && port->iotype == UPIO_AU) |
b2b13cdf | 2944 | up->bugs |= UART_BUG_NOMSR; |
b2b13cdf | 2945 | |
3685f19e SW |
2946 | /* HW bugs may trigger IRQ while IIR == NO_INT */ |
2947 | if (port->type == PORT_TEGRA) | |
2948 | up->bugs |= UART_BUG_NOMSR; | |
2949 | ||
dfe42443 | 2950 | if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) |
1da177e4 LT |
2951 | autoconfig_irq(up); |
2952 | ||
dfe42443 | 2953 | if (port->type != PORT_RSA && probeflags & PROBE_RSA) |
1da177e4 | 2954 | serial8250_release_rsa_resource(up); |
dfe42443 | 2955 | if (port->type == PORT_UNKNOWN) |
1da177e4 | 2956 | serial8250_release_std_resource(up); |
dc96efb7 MS |
2957 | |
2958 | /* Fixme: probably not the best place for this */ | |
30fa96a3 MS |
2959 | if ((port->type == PORT_XR17V35X) || |
2960 | (port->type == PORT_XR17D15X)) | |
dc96efb7 | 2961 | port->handle_irq = exar_handle_irq; |
aef9a7bd YY |
2962 | |
2963 | register_dev_spec_attr_grp(up); | |
2964 | up->fcr = uart_config[up->port.type].fcr; | |
1da177e4 LT |
2965 | } |
2966 | ||
2967 | static int | |
2968 | serial8250_verify_port(struct uart_port *port, struct serial_struct *ser) | |
2969 | { | |
a62c4133 | 2970 | if (ser->irq >= nr_irqs || ser->irq < 0 || |
1da177e4 LT |
2971 | ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || |
2972 | ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS || | |
2973 | ser->type == PORT_STARTECH) | |
2974 | return -EINVAL; | |
2975 | return 0; | |
2976 | } | |
2977 | ||
e676253b RRD |
2978 | static int serial8250_ioctl(struct uart_port *port, unsigned int cmd, |
2979 | unsigned long arg) | |
2980 | { | |
2981 | struct uart_8250_port *up = | |
2982 | container_of(port, struct uart_8250_port, port); | |
2983 | int ret; | |
2984 | struct serial_rs485 rs485_config; | |
2985 | ||
2986 | if (!up->rs485_config) | |
2987 | return -ENOIOCTLCMD; | |
2988 | ||
2989 | switch (cmd) { | |
2990 | case TIOCSRS485: | |
2991 | if (copy_from_user(&rs485_config, (void __user *)arg, | |
2992 | sizeof(rs485_config))) | |
2993 | return -EFAULT; | |
2994 | ||
2995 | ret = up->rs485_config(up, &rs485_config); | |
2996 | if (ret) | |
2997 | return ret; | |
2998 | ||
2999 | memcpy(&up->rs485, &rs485_config, sizeof(rs485_config)); | |
3000 | ||
3001 | return 0; | |
3002 | case TIOCGRS485: | |
3003 | if (copy_to_user((void __user *)arg, &up->rs485, | |
3004 | sizeof(up->rs485))) | |
3005 | return -EFAULT; | |
3006 | return 0; | |
3007 | default: | |
3008 | break; | |
3009 | } | |
3010 | ||
3011 | return -ENOIOCTLCMD; | |
3012 | } | |
3013 | ||
1da177e4 LT |
3014 | static const char * |
3015 | serial8250_type(struct uart_port *port) | |
3016 | { | |
3017 | int type = port->type; | |
3018 | ||
3019 | if (type >= ARRAY_SIZE(uart_config)) | |
3020 | type = 0; | |
3021 | return uart_config[type].name; | |
3022 | } | |
3023 | ||
3024 | static struct uart_ops serial8250_pops = { | |
3025 | .tx_empty = serial8250_tx_empty, | |
3026 | .set_mctrl = serial8250_set_mctrl, | |
3027 | .get_mctrl = serial8250_get_mctrl, | |
3028 | .stop_tx = serial8250_stop_tx, | |
3029 | .start_tx = serial8250_start_tx, | |
234abab1 SAS |
3030 | .throttle = serial8250_throttle, |
3031 | .unthrottle = serial8250_unthrottle, | |
1da177e4 LT |
3032 | .stop_rx = serial8250_stop_rx, |
3033 | .enable_ms = serial8250_enable_ms, | |
3034 | .break_ctl = serial8250_break_ctl, | |
3035 | .startup = serial8250_startup, | |
3036 | .shutdown = serial8250_shutdown, | |
3037 | .set_termios = serial8250_set_termios, | |
dc77f161 | 3038 | .set_ldisc = serial8250_set_ldisc, |
1da177e4 LT |
3039 | .pm = serial8250_pm, |
3040 | .type = serial8250_type, | |
3041 | .release_port = serial8250_release_port, | |
3042 | .request_port = serial8250_request_port, | |
3043 | .config_port = serial8250_config_port, | |
3044 | .verify_port = serial8250_verify_port, | |
e676253b | 3045 | .ioctl = serial8250_ioctl, |
f2d937f3 JW |
3046 | #ifdef CONFIG_CONSOLE_POLL |
3047 | .poll_get_char = serial8250_get_poll_char, | |
3048 | .poll_put_char = serial8250_put_poll_char, | |
3049 | #endif | |
1da177e4 LT |
3050 | }; |
3051 | ||
3052 | static struct uart_8250_port serial8250_ports[UART_NR]; | |
3053 | ||
ae14a795 SAS |
3054 | /** |
3055 | * serial8250_get_port - retrieve struct uart_8250_port | |
3056 | * @line: serial line number | |
3057 | * | |
3058 | * This function retrieves struct uart_8250_port for the specific line. | |
3059 | * This struct *must* *not* be used to perform a 8250 or serial core operation | |
3060 | * which is not accessible otherwise. Its only purpose is to make the struct | |
3061 | * accessible to the runtime-pm callbacks for context suspend/restore. | |
3062 | * The lock assumption made here is none because runtime-pm suspend/resume | |
3063 | * callbacks should not be invoked if there is any operation performed on the | |
3064 | * port. | |
3065 | */ | |
3066 | struct uart_8250_port *serial8250_get_port(int line) | |
3067 | { | |
3068 | return &serial8250_ports[line]; | |
3069 | } | |
3070 | EXPORT_SYMBOL_GPL(serial8250_get_port); | |
3071 | ||
af7f3743 AC |
3072 | static void (*serial8250_isa_config)(int port, struct uart_port *up, |
3073 | unsigned short *capabilities); | |
3074 | ||
3075 | void serial8250_set_isa_configurator( | |
3076 | void (*v)(int port, struct uart_port *up, unsigned short *capabilities)) | |
3077 | { | |
3078 | serial8250_isa_config = v; | |
3079 | } | |
3080 | EXPORT_SYMBOL(serial8250_set_isa_configurator); | |
3081 | ||
1da177e4 LT |
3082 | static void __init serial8250_isa_init_ports(void) |
3083 | { | |
3084 | struct uart_8250_port *up; | |
3085 | static int first = 1; | |
4c0ebb80 | 3086 | int i, irqflag = 0; |
1da177e4 LT |
3087 | |
3088 | if (!first) | |
3089 | return; | |
3090 | first = 0; | |
3091 | ||
835d844d SY |
3092 | if (nr_uarts > UART_NR) |
3093 | nr_uarts = UART_NR; | |
3094 | ||
317a6842 | 3095 | for (i = 0; i < nr_uarts; i++) { |
1da177e4 | 3096 | struct uart_8250_port *up = &serial8250_ports[i]; |
dfe42443 | 3097 | struct uart_port *port = &up->port; |
1da177e4 | 3098 | |
dfe42443 PG |
3099 | port->line = i; |
3100 | spin_lock_init(&port->lock); | |
1da177e4 LT |
3101 | |
3102 | init_timer(&up->timer); | |
3103 | up->timer.function = serial8250_timeout; | |
835d844d | 3104 | up->cur_iotype = 0xFF; |
1da177e4 LT |
3105 | |
3106 | /* | |
3107 | * ALPHA_KLUDGE_MCR needs to be killed. | |
3108 | */ | |
3109 | up->mcr_mask = ~ALPHA_KLUDGE_MCR; | |
3110 | up->mcr_force = ALPHA_KLUDGE_MCR; | |
3111 | ||
dfe42443 | 3112 | port->ops = &serial8250_pops; |
1da177e4 LT |
3113 | } |
3114 | ||
4c0ebb80 AGR |
3115 | if (share_irqs) |
3116 | irqflag = IRQF_SHARED; | |
3117 | ||
44454bcd | 3118 | for (i = 0, up = serial8250_ports; |
a61c2d78 | 3119 | i < ARRAY_SIZE(old_serial_port) && i < nr_uarts; |
1da177e4 | 3120 | i++, up++) { |
dfe42443 PG |
3121 | struct uart_port *port = &up->port; |
3122 | ||
3123 | port->iobase = old_serial_port[i].port; | |
3124 | port->irq = irq_canonicalize(old_serial_port[i].irq); | |
3125 | port->irqflags = old_serial_port[i].irqflags; | |
3126 | port->uartclk = old_serial_port[i].baud_base * 16; | |
3127 | port->flags = old_serial_port[i].flags; | |
3128 | port->hub6 = old_serial_port[i].hub6; | |
3129 | port->membase = old_serial_port[i].iomem_base; | |
3130 | port->iotype = old_serial_port[i].io_type; | |
3131 | port->regshift = old_serial_port[i].iomem_reg_shift; | |
3132 | set_io_from_upio(port); | |
3133 | port->irqflags |= irqflag; | |
af7f3743 AC |
3134 | if (serial8250_isa_config != NULL) |
3135 | serial8250_isa_config(i, &up->port, &up->capabilities); | |
3136 | ||
1da177e4 LT |
3137 | } |
3138 | } | |
3139 | ||
b5d228cc SL |
3140 | static void |
3141 | serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type) | |
3142 | { | |
3143 | up->port.type = type; | |
9660497c HK |
3144 | if (!up->port.fifosize) |
3145 | up->port.fifosize = uart_config[type].fifo_size; | |
3146 | if (!up->tx_loadsz) | |
3147 | up->tx_loadsz = uart_config[type].tx_loadsz; | |
3148 | if (!up->capabilities) | |
3149 | up->capabilities = uart_config[type].flags; | |
b5d228cc SL |
3150 | } |
3151 | ||
1da177e4 LT |
3152 | static void __init |
3153 | serial8250_register_ports(struct uart_driver *drv, struct device *dev) | |
3154 | { | |
3155 | int i; | |
3156 | ||
b8e7e40a AC |
3157 | for (i = 0; i < nr_uarts; i++) { |
3158 | struct uart_8250_port *up = &serial8250_ports[i]; | |
b8e7e40a | 3159 | |
835d844d SY |
3160 | if (up->port.dev) |
3161 | continue; | |
1da177e4 LT |
3162 | |
3163 | up->port.dev = dev; | |
b5d228cc SL |
3164 | |
3165 | if (up->port.flags & UPF_FIXED_TYPE) | |
3166 | serial8250_init_fixed_type_port(up, up->port.type); | |
3167 | ||
1da177e4 LT |
3168 | uart_add_one_port(drv, &up->port); |
3169 | } | |
3170 | } | |
3171 | ||
3172 | #ifdef CONFIG_SERIAL_8250_CONSOLE | |
3173 | ||
d358788f RK |
3174 | static void serial8250_console_putchar(struct uart_port *port, int ch) |
3175 | { | |
b1261c86 | 3176 | struct uart_8250_port *up = up_to_u8250p(port); |
d358788f RK |
3177 | |
3178 | wait_for_xmitr(up, UART_LSR_THRE); | |
4fd996a1 | 3179 | serial_port_out(port, UART_TX, ch); |
d358788f RK |
3180 | } |
3181 | ||
1da177e4 LT |
3182 | /* |
3183 | * Print a string to the serial port trying not to disturb | |
3184 | * any possible real use of the port... | |
3185 | * | |
3186 | * The console_lock must be held when we get here. | |
3187 | */ | |
3188 | static void | |
3189 | serial8250_console_write(struct console *co, const char *s, unsigned int count) | |
3190 | { | |
3191 | struct uart_8250_port *up = &serial8250_ports[co->index]; | |
dfe42443 | 3192 | struct uart_port *port = &up->port; |
d8a5a8d7 | 3193 | unsigned long flags; |
1da177e4 | 3194 | unsigned int ier; |
d8a5a8d7 | 3195 | int locked = 1; |
1da177e4 | 3196 | |
78512ece AM |
3197 | touch_nmi_watchdog(); |
3198 | ||
d74d5d1b SAS |
3199 | serial8250_rpm_get(up); |
3200 | ||
ebade5e8 IM |
3201 | if (port->sysrq || oops_in_progress) |
3202 | locked = spin_trylock_irqsave(&port->lock, flags); | |
3203 | else | |
3204 | spin_lock_irqsave(&port->lock, flags); | |
d8a5a8d7 | 3205 | |
1da177e4 | 3206 | /* |
dc7bf130 | 3207 | * First save the IER then disable the interrupts |
1da177e4 | 3208 | */ |
4fd996a1 | 3209 | ier = serial_port_in(port, UART_IER); |
1da177e4 LT |
3210 | |
3211 | if (up->capabilities & UART_CAP_UUE) | |
4fd996a1 | 3212 | serial_port_out(port, UART_IER, UART_IER_UUE); |
1da177e4 | 3213 | else |
4fd996a1 | 3214 | serial_port_out(port, UART_IER, 0); |
1da177e4 | 3215 | |
dfe42443 | 3216 | uart_console_write(port, s, count, serial8250_console_putchar); |
1da177e4 LT |
3217 | |
3218 | /* | |
3219 | * Finally, wait for transmitter to become empty | |
3220 | * and restore the IER | |
3221 | */ | |
f91a3715 | 3222 | wait_for_xmitr(up, BOTH_EMPTY); |
4fd996a1 | 3223 | serial_port_out(port, UART_IER, ier); |
d8a5a8d7 | 3224 | |
ad4c2aa6 CM |
3225 | /* |
3226 | * The receive handling will happen properly because the | |
3227 | * receive ready bit will still be set; it is not cleared | |
3228 | * on read. However, modem control will not, we must | |
3229 | * call it if we have saved something in the saved flags | |
3230 | * while processing with interrupts off. | |
3231 | */ | |
3232 | if (up->msr_saved_flags) | |
3986fb2b | 3233 | serial8250_modem_status(up); |
ad4c2aa6 | 3234 | |
d8a5a8d7 | 3235 | if (locked) |
ebade5e8 | 3236 | spin_unlock_irqrestore(&port->lock, flags); |
d74d5d1b | 3237 | serial8250_rpm_put(up); |
1da177e4 LT |
3238 | } |
3239 | ||
118c0ace | 3240 | static int __init serial8250_console_setup(struct console *co, char *options) |
1da177e4 LT |
3241 | { |
3242 | struct uart_port *port; | |
3243 | int baud = 9600; | |
3244 | int bits = 8; | |
3245 | int parity = 'n'; | |
3246 | int flow = 'n'; | |
3247 | ||
3248 | /* | |
3249 | * Check whether an invalid uart number has been specified, and | |
3250 | * if so, search for the first available port that does have | |
3251 | * console support. | |
3252 | */ | |
317a6842 | 3253 | if (co->index >= nr_uarts) |
1da177e4 LT |
3254 | co->index = 0; |
3255 | port = &serial8250_ports[co->index].port; | |
3256 | if (!port->iobase && !port->membase) | |
3257 | return -ENODEV; | |
3258 | ||
3259 | if (options) | |
3260 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
3261 | ||
3262 | return uart_set_options(port, co, baud, parity, bits, flow); | |
3263 | } | |
3264 | ||
b6b1d877 | 3265 | static int serial8250_console_early_setup(void) |
18a8bd94 YL |
3266 | { |
3267 | return serial8250_find_port_for_earlycon(); | |
3268 | } | |
3269 | ||
1da177e4 LT |
3270 | static struct console serial8250_console = { |
3271 | .name = "ttyS", | |
3272 | .write = serial8250_console_write, | |
3273 | .device = uart_console_device, | |
3274 | .setup = serial8250_console_setup, | |
18a8bd94 | 3275 | .early_setup = serial8250_console_early_setup, |
a80c49db | 3276 | .flags = CON_PRINTBUFFER | CON_ANYTIME, |
1da177e4 LT |
3277 | .index = -1, |
3278 | .data = &serial8250_reg, | |
3279 | }; | |
3280 | ||
3281 | static int __init serial8250_console_init(void) | |
3282 | { | |
3283 | serial8250_isa_init_ports(); | |
3284 | register_console(&serial8250_console); | |
3285 | return 0; | |
3286 | } | |
3287 | console_initcall(serial8250_console_init); | |
3288 | ||
18a8bd94 | 3289 | int serial8250_find_port(struct uart_port *p) |
1da177e4 LT |
3290 | { |
3291 | int line; | |
3292 | struct uart_port *port; | |
3293 | ||
317a6842 | 3294 | for (line = 0; line < nr_uarts; line++) { |
1da177e4 | 3295 | port = &serial8250_ports[line].port; |
50aec3b5 | 3296 | if (uart_match_port(p, port)) |
1da177e4 LT |
3297 | return line; |
3298 | } | |
3299 | return -ENODEV; | |
3300 | } | |
3301 | ||
1da177e4 LT |
3302 | #define SERIAL8250_CONSOLE &serial8250_console |
3303 | #else | |
3304 | #define SERIAL8250_CONSOLE NULL | |
3305 | #endif | |
3306 | ||
3307 | static struct uart_driver serial8250_reg = { | |
3308 | .owner = THIS_MODULE, | |
3309 | .driver_name = "serial", | |
1da177e4 LT |
3310 | .dev_name = "ttyS", |
3311 | .major = TTY_MAJOR, | |
3312 | .minor = 64, | |
1da177e4 LT |
3313 | .cons = SERIAL8250_CONSOLE, |
3314 | }; | |
3315 | ||
d856c666 RK |
3316 | /* |
3317 | * early_serial_setup - early registration for 8250 ports | |
3318 | * | |
3319 | * Setup an 8250 port structure prior to console initialisation. Use | |
3320 | * after console initialisation will cause undefined behaviour. | |
3321 | */ | |
1da177e4 LT |
3322 | int __init early_serial_setup(struct uart_port *port) |
3323 | { | |
b430428a DD |
3324 | struct uart_port *p; |
3325 | ||
1da177e4 LT |
3326 | if (port->line >= ARRAY_SIZE(serial8250_ports)) |
3327 | return -ENODEV; | |
3328 | ||
3329 | serial8250_isa_init_ports(); | |
b430428a DD |
3330 | p = &serial8250_ports[port->line].port; |
3331 | p->iobase = port->iobase; | |
3332 | p->membase = port->membase; | |
3333 | p->irq = port->irq; | |
1c2f0493 | 3334 | p->irqflags = port->irqflags; |
b430428a DD |
3335 | p->uartclk = port->uartclk; |
3336 | p->fifosize = port->fifosize; | |
3337 | p->regshift = port->regshift; | |
3338 | p->iotype = port->iotype; | |
3339 | p->flags = port->flags; | |
3340 | p->mapbase = port->mapbase; | |
3341 | p->private_data = port->private_data; | |
125c97d8 HD |
3342 | p->type = port->type; |
3343 | p->line = port->line; | |
7d6a07d1 DD |
3344 | |
3345 | set_io_from_upio(p); | |
3346 | if (port->serial_in) | |
3347 | p->serial_in = port->serial_in; | |
3348 | if (port->serial_out) | |
3349 | p->serial_out = port->serial_out; | |
583d28e9 JI |
3350 | if (port->handle_irq) |
3351 | p->handle_irq = port->handle_irq; | |
3352 | else | |
3353 | p->handle_irq = serial8250_default_handle_irq; | |
7d6a07d1 | 3354 | |
1da177e4 LT |
3355 | return 0; |
3356 | } | |
3357 | ||
3358 | /** | |
3359 | * serial8250_suspend_port - suspend one serial port | |
3360 | * @line: serial line number | |
1da177e4 LT |
3361 | * |
3362 | * Suspend one serial port. | |
3363 | */ | |
3364 | void serial8250_suspend_port(int line) | |
3365 | { | |
3366 | uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port); | |
3367 | } | |
3368 | ||
3369 | /** | |
3370 | * serial8250_resume_port - resume one serial port | |
3371 | * @line: serial line number | |
1da177e4 LT |
3372 | * |
3373 | * Resume one serial port. | |
3374 | */ | |
3375 | void serial8250_resume_port(int line) | |
3376 | { | |
b5b82df6 | 3377 | struct uart_8250_port *up = &serial8250_ports[line]; |
dfe42443 | 3378 | struct uart_port *port = &up->port; |
b5b82df6 DW |
3379 | |
3380 | if (up->capabilities & UART_NATSEMI) { | |
b5b82df6 | 3381 | /* Ensure it's still in high speed mode */ |
4fd996a1 | 3382 | serial_port_out(port, UART_LCR, 0xE0); |
b5b82df6 | 3383 | |
0d0389e5 | 3384 | ns16550a_goto_highspeed(up); |
b5b82df6 | 3385 | |
4fd996a1 | 3386 | serial_port_out(port, UART_LCR, 0); |
dfe42443 | 3387 | port->uartclk = 921600*16; |
b5b82df6 | 3388 | } |
dfe42443 | 3389 | uart_resume_port(&serial8250_reg, port); |
1da177e4 LT |
3390 | } |
3391 | ||
3392 | /* | |
3393 | * Register a set of serial devices attached to a platform device. The | |
3394 | * list is terminated with a zero flags entry, which means we expect | |
3395 | * all entries to have at least UPF_BOOT_AUTOCONF set. | |
3396 | */ | |
9671f099 | 3397 | static int serial8250_probe(struct platform_device *dev) |
1da177e4 | 3398 | { |
574de559 | 3399 | struct plat_serial8250_port *p = dev_get_platdata(&dev->dev); |
2655a2c7 | 3400 | struct uart_8250_port uart; |
4c0ebb80 | 3401 | int ret, i, irqflag = 0; |
1da177e4 | 3402 | |
2655a2c7 | 3403 | memset(&uart, 0, sizeof(uart)); |
1da177e4 | 3404 | |
4c0ebb80 AGR |
3405 | if (share_irqs) |
3406 | irqflag = IRQF_SHARED; | |
3407 | ||
ec9f47cd | 3408 | for (i = 0; p && p->flags != 0; p++, i++) { |
2655a2c7 AC |
3409 | uart.port.iobase = p->iobase; |
3410 | uart.port.membase = p->membase; | |
3411 | uart.port.irq = p->irq; | |
3412 | uart.port.irqflags = p->irqflags; | |
3413 | uart.port.uartclk = p->uartclk; | |
3414 | uart.port.regshift = p->regshift; | |
3415 | uart.port.iotype = p->iotype; | |
3416 | uart.port.flags = p->flags; | |
3417 | uart.port.mapbase = p->mapbase; | |
3418 | uart.port.hub6 = p->hub6; | |
3419 | uart.port.private_data = p->private_data; | |
3420 | uart.port.type = p->type; | |
3421 | uart.port.serial_in = p->serial_in; | |
3422 | uart.port.serial_out = p->serial_out; | |
3423 | uart.port.handle_irq = p->handle_irq; | |
3424 | uart.port.handle_break = p->handle_break; | |
3425 | uart.port.set_termios = p->set_termios; | |
3426 | uart.port.pm = p->pm; | |
3427 | uart.port.dev = &dev->dev; | |
3428 | uart.port.irqflags |= irqflag; | |
3429 | ret = serial8250_register_8250_port(&uart); | |
ec9f47cd | 3430 | if (ret < 0) { |
3ae5eaec | 3431 | dev_err(&dev->dev, "unable to register port at index %d " |
4f640efb JB |
3432 | "(IO%lx MEM%llx IRQ%d): %d\n", i, |
3433 | p->iobase, (unsigned long long)p->mapbase, | |
3434 | p->irq, ret); | |
ec9f47cd | 3435 | } |
1da177e4 LT |
3436 | } |
3437 | return 0; | |
3438 | } | |
3439 | ||
3440 | /* | |
3441 | * Remove serial ports registered against a platform device. | |
3442 | */ | |
ae8d8a14 | 3443 | static int serial8250_remove(struct platform_device *dev) |
1da177e4 LT |
3444 | { |
3445 | int i; | |
3446 | ||
317a6842 | 3447 | for (i = 0; i < nr_uarts; i++) { |
1da177e4 LT |
3448 | struct uart_8250_port *up = &serial8250_ports[i]; |
3449 | ||
3ae5eaec | 3450 | if (up->port.dev == &dev->dev) |
1da177e4 LT |
3451 | serial8250_unregister_port(i); |
3452 | } | |
3453 | return 0; | |
3454 | } | |
3455 | ||
3ae5eaec | 3456 | static int serial8250_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 LT |
3457 | { |
3458 | int i; | |
3459 | ||
1da177e4 LT |
3460 | for (i = 0; i < UART_NR; i++) { |
3461 | struct uart_8250_port *up = &serial8250_ports[i]; | |
3462 | ||
3ae5eaec | 3463 | if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) |
1da177e4 LT |
3464 | uart_suspend_port(&serial8250_reg, &up->port); |
3465 | } | |
3466 | ||
3467 | return 0; | |
3468 | } | |
3469 | ||
3ae5eaec | 3470 | static int serial8250_resume(struct platform_device *dev) |
1da177e4 LT |
3471 | { |
3472 | int i; | |
3473 | ||
1da177e4 LT |
3474 | for (i = 0; i < UART_NR; i++) { |
3475 | struct uart_8250_port *up = &serial8250_ports[i]; | |
3476 | ||
3ae5eaec | 3477 | if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) |
b5b82df6 | 3478 | serial8250_resume_port(i); |
1da177e4 LT |
3479 | } |
3480 | ||
3481 | return 0; | |
3482 | } | |
3483 | ||
3ae5eaec | 3484 | static struct platform_driver serial8250_isa_driver = { |
1da177e4 | 3485 | .probe = serial8250_probe, |
2d47b716 | 3486 | .remove = serial8250_remove, |
1da177e4 LT |
3487 | .suspend = serial8250_suspend, |
3488 | .resume = serial8250_resume, | |
3ae5eaec RK |
3489 | .driver = { |
3490 | .name = "serial8250", | |
7493a314 | 3491 | .owner = THIS_MODULE, |
3ae5eaec | 3492 | }, |
1da177e4 LT |
3493 | }; |
3494 | ||
3495 | /* | |
3496 | * This "device" covers _all_ ISA 8250-compatible serial devices listed | |
3497 | * in the table in include/asm/serial.h | |
3498 | */ | |
3499 | static struct platform_device *serial8250_isa_devs; | |
3500 | ||
3501 | /* | |
2655a2c7 | 3502 | * serial8250_register_8250_port and serial8250_unregister_port allows for |
1da177e4 LT |
3503 | * 16x50 serial ports to be configured at run-time, to support PCMCIA |
3504 | * modems and PCI multiport cards. | |
3505 | */ | |
f392ecfa | 3506 | static DEFINE_MUTEX(serial_mutex); |
1da177e4 LT |
3507 | |
3508 | static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port) | |
3509 | { | |
3510 | int i; | |
3511 | ||
3512 | /* | |
3513 | * First, find a port entry which matches. | |
3514 | */ | |
317a6842 | 3515 | for (i = 0; i < nr_uarts; i++) |
1da177e4 LT |
3516 | if (uart_match_port(&serial8250_ports[i].port, port)) |
3517 | return &serial8250_ports[i]; | |
3518 | ||
59b3e898 SAS |
3519 | /* try line number first if still available */ |
3520 | i = port->line; | |
3521 | if (i < nr_uarts && serial8250_ports[i].port.type == PORT_UNKNOWN && | |
3522 | serial8250_ports[i].port.iobase == 0) | |
3523 | return &serial8250_ports[i]; | |
1da177e4 LT |
3524 | /* |
3525 | * We didn't find a matching entry, so look for the first | |
3526 | * free entry. We look for one which hasn't been previously | |
3527 | * used (indicated by zero iobase). | |
3528 | */ | |
317a6842 | 3529 | for (i = 0; i < nr_uarts; i++) |
1da177e4 LT |
3530 | if (serial8250_ports[i].port.type == PORT_UNKNOWN && |
3531 | serial8250_ports[i].port.iobase == 0) | |
3532 | return &serial8250_ports[i]; | |
3533 | ||
3534 | /* | |
3535 | * That also failed. Last resort is to find any entry which | |
3536 | * doesn't have a real port associated with it. | |
3537 | */ | |
317a6842 | 3538 | for (i = 0; i < nr_uarts; i++) |
1da177e4 LT |
3539 | if (serial8250_ports[i].port.type == PORT_UNKNOWN) |
3540 | return &serial8250_ports[i]; | |
3541 | ||
3542 | return NULL; | |
3543 | } | |
3544 | ||
3545 | /** | |
f73fa05b | 3546 | * serial8250_register_8250_port - register a serial port |
58bcd332 | 3547 | * @up: serial port template |
1da177e4 LT |
3548 | * |
3549 | * Configure the serial port specified by the request. If the | |
3550 | * port exists and is in use, it is hung up and unregistered | |
3551 | * first. | |
3552 | * | |
3553 | * The port is then probed and if necessary the IRQ is autodetected | |
3554 | * If this fails an error is returned. | |
3555 | * | |
3556 | * On success the port is ready to use and the line number is returned. | |
3557 | */ | |
f73fa05b | 3558 | int serial8250_register_8250_port(struct uart_8250_port *up) |
1da177e4 LT |
3559 | { |
3560 | struct uart_8250_port *uart; | |
3561 | int ret = -ENOSPC; | |
3562 | ||
f73fa05b | 3563 | if (up->port.uartclk == 0) |
1da177e4 LT |
3564 | return -EINVAL; |
3565 | ||
f392ecfa | 3566 | mutex_lock(&serial_mutex); |
1da177e4 | 3567 | |
f73fa05b | 3568 | uart = serial8250_find_match_or_unused(&up->port); |
65ecc9c0 | 3569 | if (uart && uart->port.type != PORT_8250_CIR) { |
835d844d SY |
3570 | if (uart->port.dev) |
3571 | uart_remove_one_port(&serial8250_reg, &uart->port); | |
1da177e4 | 3572 | |
f73fa05b MD |
3573 | uart->port.iobase = up->port.iobase; |
3574 | uart->port.membase = up->port.membase; | |
3575 | uart->port.irq = up->port.irq; | |
3576 | uart->port.irqflags = up->port.irqflags; | |
3577 | uart->port.uartclk = up->port.uartclk; | |
3578 | uart->port.fifosize = up->port.fifosize; | |
3579 | uart->port.regshift = up->port.regshift; | |
3580 | uart->port.iotype = up->port.iotype; | |
3581 | uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF; | |
a2d33d87 | 3582 | uart->bugs = up->bugs; |
f73fa05b MD |
3583 | uart->port.mapbase = up->port.mapbase; |
3584 | uart->port.private_data = up->port.private_data; | |
9660497c HK |
3585 | uart->port.fifosize = up->port.fifosize; |
3586 | uart->tx_loadsz = up->tx_loadsz; | |
3587 | uart->capabilities = up->capabilities; | |
e676253b RRD |
3588 | uart->rs485_config = up->rs485_config; |
3589 | uart->rs485 = up->rs485; | |
234abab1 SAS |
3590 | uart->port.throttle = up->port.throttle; |
3591 | uart->port.unthrottle = up->port.unthrottle; | |
9660497c | 3592 | |
6a3f45dc HK |
3593 | /* Take tx_loadsz from fifosize if it wasn't set separately */ |
3594 | if (uart->port.fifosize && !uart->tx_loadsz) | |
3595 | uart->tx_loadsz = uart->port.fifosize; | |
3596 | ||
f73fa05b MD |
3597 | if (up->port.dev) |
3598 | uart->port.dev = up->port.dev; | |
3599 | ||
3600 | if (up->port.flags & UPF_FIXED_TYPE) | |
3601 | serial8250_init_fixed_type_port(uart, up->port.type); | |
8e23fcc8 | 3602 | |
7d6a07d1 DD |
3603 | set_io_from_upio(&uart->port); |
3604 | /* Possibly override default I/O functions. */ | |
f73fa05b MD |
3605 | if (up->port.serial_in) |
3606 | uart->port.serial_in = up->port.serial_in; | |
3607 | if (up->port.serial_out) | |
3608 | uart->port.serial_out = up->port.serial_out; | |
3609 | if (up->port.handle_irq) | |
3610 | uart->port.handle_irq = up->port.handle_irq; | |
235dae5d | 3611 | /* Possibly override set_termios call */ |
f73fa05b MD |
3612 | if (up->port.set_termios) |
3613 | uart->port.set_termios = up->port.set_termios; | |
b99b121b SAS |
3614 | if (up->port.startup) |
3615 | uart->port.startup = up->port.startup; | |
3616 | if (up->port.shutdown) | |
3617 | uart->port.shutdown = up->port.shutdown; | |
f73fa05b MD |
3618 | if (up->port.pm) |
3619 | uart->port.pm = up->port.pm; | |
3620 | if (up->port.handle_break) | |
3621 | uart->port.handle_break = up->port.handle_break; | |
3622 | if (up->dl_read) | |
3623 | uart->dl_read = up->dl_read; | |
3624 | if (up->dl_write) | |
3625 | uart->dl_write = up->dl_write; | |
9ee4b83e HK |
3626 | if (up->dma) |
3627 | uart->dma = up->dma; | |
1da177e4 | 3628 | |
af7f3743 AC |
3629 | if (serial8250_isa_config != NULL) |
3630 | serial8250_isa_config(0, &uart->port, | |
3631 | &uart->capabilities); | |
3632 | ||
1da177e4 LT |
3633 | ret = uart_add_one_port(&serial8250_reg, &uart->port); |
3634 | if (ret == 0) | |
3635 | ret = uart->port.line; | |
3636 | } | |
f392ecfa | 3637 | mutex_unlock(&serial_mutex); |
1da177e4 LT |
3638 | |
3639 | return ret; | |
3640 | } | |
f73fa05b MD |
3641 | EXPORT_SYMBOL(serial8250_register_8250_port); |
3642 | ||
1da177e4 LT |
3643 | /** |
3644 | * serial8250_unregister_port - remove a 16x50 serial port at runtime | |
3645 | * @line: serial line number | |
3646 | * | |
3647 | * Remove one serial port. This may not be called from interrupt | |
3648 | * context. We hand the port back to the our control. | |
3649 | */ | |
3650 | void serial8250_unregister_port(int line) | |
3651 | { | |
3652 | struct uart_8250_port *uart = &serial8250_ports[line]; | |
3653 | ||
f392ecfa | 3654 | mutex_lock(&serial_mutex); |
1da177e4 LT |
3655 | uart_remove_one_port(&serial8250_reg, &uart->port); |
3656 | if (serial8250_isa_devs) { | |
3657 | uart->port.flags &= ~UPF_BOOT_AUTOCONF; | |
3658 | uart->port.type = PORT_UNKNOWN; | |
3659 | uart->port.dev = &serial8250_isa_devs->dev; | |
cb01ece3 | 3660 | uart->capabilities = uart_config[uart->port.type].flags; |
1da177e4 LT |
3661 | uart_add_one_port(&serial8250_reg, &uart->port); |
3662 | } else { | |
3663 | uart->port.dev = NULL; | |
3664 | } | |
f392ecfa | 3665 | mutex_unlock(&serial_mutex); |
1da177e4 LT |
3666 | } |
3667 | EXPORT_SYMBOL(serial8250_unregister_port); | |
3668 | ||
3669 | static int __init serial8250_init(void) | |
3670 | { | |
25db8ad5 | 3671 | int ret; |
1da177e4 | 3672 | |
835d844d | 3673 | serial8250_isa_init_ports(); |
a61c2d78 | 3674 | |
f1fb9bb8 | 3675 | printk(KERN_INFO "Serial: 8250/16550 driver, " |
a61c2d78 | 3676 | "%d ports, IRQ sharing %sabled\n", nr_uarts, |
1da177e4 LT |
3677 | share_irqs ? "en" : "dis"); |
3678 | ||
b70ac771 DM |
3679 | #ifdef CONFIG_SPARC |
3680 | ret = sunserial_register_minors(&serial8250_reg, UART_NR); | |
3681 | #else | |
3682 | serial8250_reg.nr = UART_NR; | |
1da177e4 | 3683 | ret = uart_register_driver(&serial8250_reg); |
b70ac771 | 3684 | #endif |
1da177e4 LT |
3685 | if (ret) |
3686 | goto out; | |
3687 | ||
835d844d SY |
3688 | ret = serial8250_pnp_init(); |
3689 | if (ret) | |
3690 | goto unreg_uart_drv; | |
3691 | ||
7493a314 DT |
3692 | serial8250_isa_devs = platform_device_alloc("serial8250", |
3693 | PLAT8250_DEV_LEGACY); | |
3694 | if (!serial8250_isa_devs) { | |
3695 | ret = -ENOMEM; | |
835d844d | 3696 | goto unreg_pnp; |
1da177e4 LT |
3697 | } |
3698 | ||
7493a314 DT |
3699 | ret = platform_device_add(serial8250_isa_devs); |
3700 | if (ret) | |
3701 | goto put_dev; | |
3702 | ||
1da177e4 LT |
3703 | serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev); |
3704 | ||
bc965a7f RK |
3705 | ret = platform_driver_register(&serial8250_isa_driver); |
3706 | if (ret == 0) | |
3707 | goto out; | |
1da177e4 | 3708 | |
bc965a7f | 3709 | platform_device_del(serial8250_isa_devs); |
25db8ad5 | 3710 | put_dev: |
7493a314 | 3711 | platform_device_put(serial8250_isa_devs); |
835d844d SY |
3712 | unreg_pnp: |
3713 | serial8250_pnp_exit(); | |
25db8ad5 | 3714 | unreg_uart_drv: |
b70ac771 DM |
3715 | #ifdef CONFIG_SPARC |
3716 | sunserial_unregister_minors(&serial8250_reg, UART_NR); | |
3717 | #else | |
1da177e4 | 3718 | uart_unregister_driver(&serial8250_reg); |
b70ac771 | 3719 | #endif |
25db8ad5 | 3720 | out: |
1da177e4 LT |
3721 | return ret; |
3722 | } | |
3723 | ||
3724 | static void __exit serial8250_exit(void) | |
3725 | { | |
3726 | struct platform_device *isa_dev = serial8250_isa_devs; | |
3727 | ||
3728 | /* | |
3729 | * This tells serial8250_unregister_port() not to re-register | |
3730 | * the ports (thereby making serial8250_isa_driver permanently | |
3731 | * in use.) | |
3732 | */ | |
3733 | serial8250_isa_devs = NULL; | |
3734 | ||
3ae5eaec | 3735 | platform_driver_unregister(&serial8250_isa_driver); |
1da177e4 LT |
3736 | platform_device_unregister(isa_dev); |
3737 | ||
835d844d SY |
3738 | serial8250_pnp_exit(); |
3739 | ||
b70ac771 DM |
3740 | #ifdef CONFIG_SPARC |
3741 | sunserial_unregister_minors(&serial8250_reg, UART_NR); | |
3742 | #else | |
1da177e4 | 3743 | uart_unregister_driver(&serial8250_reg); |
b70ac771 | 3744 | #endif |
1da177e4 LT |
3745 | } |
3746 | ||
3747 | module_init(serial8250_init); | |
3748 | module_exit(serial8250_exit); | |
3749 | ||
3750 | EXPORT_SYMBOL(serial8250_suspend_port); | |
3751 | EXPORT_SYMBOL(serial8250_resume_port); | |
3752 | ||
3753 | MODULE_LICENSE("GPL"); | |
d87a6d95 | 3754 | MODULE_DESCRIPTION("Generic 8250/16x50 serial driver"); |
1da177e4 LT |
3755 | |
3756 | module_param(share_irqs, uint, 0644); | |
3757 | MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices" | |
3758 | " (unsafe)"); | |
3759 | ||
a61c2d78 DJ |
3760 | module_param(nr_uarts, uint, 0644); |
3761 | MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")"); | |
3762 | ||
d41a4b51 CE |
3763 | module_param(skip_txen_test, uint, 0644); |
3764 | MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time"); | |
3765 | ||
1da177e4 LT |
3766 | #ifdef CONFIG_SERIAL_8250_RSA |
3767 | module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444); | |
3768 | MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA"); | |
3769 | #endif | |
3770 | MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR); | |
f2b8dfd9 | 3771 | |
9326b047 | 3772 | #ifdef CONFIG_SERIAL_8250_DEPRECATED_OPTIONS |
f2b8dfd9 JB |
3773 | #ifndef MODULE |
3774 | /* This module was renamed to 8250_core in 3.7. Keep the old "8250" name | |
3775 | * working as well for the module options so we don't break people. We | |
3776 | * need to keep the names identical and the convenient macros will happily | |
3777 | * refuse to let us do that by failing the build with redefinition errors | |
3778 | * of global variables. So we stick them inside a dummy function to avoid | |
3779 | * those conflicts. The options still get parsed, and the redefined | |
3780 | * MODULE_PARAM_PREFIX lets us keep the "8250." syntax alive. | |
3781 | * | |
3782 | * This is hacky. I'm sorry. | |
3783 | */ | |
3784 | static void __used s8250_options(void) | |
3785 | { | |
3786 | #undef MODULE_PARAM_PREFIX | |
9196d8ac | 3787 | #define MODULE_PARAM_PREFIX "8250_core." |
f2b8dfd9 JB |
3788 | |
3789 | module_param_cb(share_irqs, ¶m_ops_uint, &share_irqs, 0644); | |
3790 | module_param_cb(nr_uarts, ¶m_ops_uint, &nr_uarts, 0644); | |
3791 | module_param_cb(skip_txen_test, ¶m_ops_uint, &skip_txen_test, 0644); | |
3792 | #ifdef CONFIG_SERIAL_8250_RSA | |
3793 | __module_param_call(MODULE_PARAM_PREFIX, probe_rsa, | |
3794 | ¶m_array_ops, .arr = &__param_arr_probe_rsa, | |
3795 | 0444, -1); | |
3796 | #endif | |
3797 | } | |
3798 | #else | |
9196d8ac | 3799 | MODULE_ALIAS("8250_core"); |
f2b8dfd9 | 3800 | #endif |
f2b8dfd9 | 3801 | #endif |