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serial_core: Commonalize crlf when working w/ a non open console port
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250_core.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
1da177e4
LT		 13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
1da177e4
LT		 18
19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
1da177e4 29#include <linux/delay.h>
d052d1be 30#include <linux/platform_device.h>
1da177e4 31#include <linux/tty.h>
cd3ecad1 32#include <linux/ratelimit.h>
1da177e4
LT		 33#include <linux/tty_flip.h>
34#include <linux/serial_reg.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
78512ece 38#include <linux/nmi.h>
f392ecfa 39#include <linux/mutex.h>
5a0e3ad6 40#include <linux/slab.h>
6816383a
PG		 41#ifdef CONFIG_SPARC
42#include <linux/sunserialcore.h>
43#endif
1da177e4
LT		 44
45#include <asm/io.h>
46#include <asm/irq.h>
47
48#include "8250.h"
49
50/*
51 * Configuration:
40663cc7 52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 53 * is unsafe when used on edge-triggered interrupts.
54 */
408b664a 55static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 56
a61c2d78
DJ		 57static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
8440838b
DM		 59static struct uart_driver serial8250_reg;
60
61static int serial_index(struct uart_port *port)
62{
63 return (serial8250_reg.minor - 64) + port->line;
64}
65
d41a4b51
CE		 66static unsigned int skip_txen_test; /* force skip of txen test at init time */
67
1da177e4
LT		 68/*
69 * Debugging.
70 */
71#if 0
72#define DEBUG_AUTOCONF(fmt...) printk(fmt)
73#else
74#define DEBUG_AUTOCONF(fmt...) do { } while (0)
75#endif
76
77#if 0
78#define DEBUG_INTR(fmt...) printk(fmt)
79#else
80#define DEBUG_INTR(fmt...) do { } while (0)
81#endif
82
e7328ae1 83#define PASS_LIMIT 512
1da177e4 84
bca47613
DH		 85#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
86
87
1da177e4
LT		 88#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89#define CONFIG_SERIAL_DETECT_IRQ 1
90#endif
1da177e4
LT		 91#ifdef CONFIG_SERIAL_8250_MANY_PORTS
92#define CONFIG_SERIAL_MANY_PORTS 1
93#endif
94
95/*
96 * HUB6 is always on. This will be removed once the header
97 * files have been cleaned.
98 */
99#define CONFIG_HUB6 1
100
a4ed1e41 101#include <asm/serial.h>
1da177e4
LT		 102/*
103 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * standard enumeration mechanism. Platforms that can find all
105 * serial ports via mechanisms like ACPI or PCI need not supply it.
106 */
107#ifndef SERIAL_PORT_DFNS
108#define SERIAL_PORT_DFNS
109#endif
110
cb3592be 111static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
113};
114
026d02a2 115#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 116
117#ifdef CONFIG_SERIAL_8250_RSA
118
119#define PORT_RSA_MAX 4
120static unsigned long probe_rsa[PORT_RSA_MAX];
121static unsigned int probe_rsa_count;
122#endif /* CONFIG_SERIAL_8250_RSA */
123
1da177e4 124struct irq_info {
25db8ad5
AC		 125 struct hlist_node node;
126 int irq;
127 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 128 struct list_head *head;
129};
130
25db8ad5
AC		 131#define NR_IRQ_HASH 32 /* Can be adjusted later */
132static struct hlist_head irq_lists[NR_IRQ_HASH];
133static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 134
135/*
136 * Here we define the default xmit fifo size used for each type of UART.
137 */
138static const struct serial8250_config uart_config[] = {
139 [PORT_UNKNOWN] = {
140 .name = "unknown",
141 .fifo_size = 1,
142 .tx_loadsz = 1,
143 },
144 [PORT_8250] = {
145 .name = "8250",
146 .fifo_size = 1,
147 .tx_loadsz = 1,
148 },
149 [PORT_16450] = {
150 .name = "16450",
151 .fifo_size = 1,
152 .tx_loadsz = 1,
153 },
154 [PORT_16550] = {
155 .name = "16550",
156 .fifo_size = 1,
157 .tx_loadsz = 1,
158 },
159 [PORT_16550A] = {
160 .name = "16550A",
161 .fifo_size = 16,
162 .tx_loadsz = 16,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO,
165 },
166 [PORT_CIRRUS] = {
167 .name = "Cirrus",
168 .fifo_size = 1,
169 .tx_loadsz = 1,
170 },
171 [PORT_16650] = {
172 .name = "ST16650",
173 .fifo_size = 1,
174 .tx_loadsz = 1,
175 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
176 },
177 [PORT_16650V2] = {
178 .name = "ST16650V2",
179 .fifo_size = 32,
180 .tx_loadsz = 16,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
182 UART_FCR_T_TRIG_00,
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184 },
185 [PORT_16750] = {
186 .name = "TI16750",
187 .fifo_size = 64,
188 .tx_loadsz = 64,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
190 UART_FCR7_64BYTE,
191 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
192 },
193 [PORT_STARTECH] = {
194 .name = "Startech",
195 .fifo_size = 1,
196 .tx_loadsz = 1,
197 },
198 [PORT_16C950] = {
199 .name = "16C950/954",
200 .fifo_size = 128,
201 .tx_loadsz = 128,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
d0694e2a
PM		 203 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
1da177e4
LT		 205 },
206 [PORT_16654] = {
207 .name = "ST16654",
208 .fifo_size = 64,
209 .tx_loadsz = 32,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
211 UART_FCR_T_TRIG_10,
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
213 },
214 [PORT_16850] = {
215 .name = "XR16850",
216 .fifo_size = 128,
217 .tx_loadsz = 128,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220 },
221 [PORT_RSA] = {
222 .name = "RSA",
223 .fifo_size = 2048,
224 .tx_loadsz = 2048,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226 .flags = UART_CAP_FIFO,
227 },
228 [PORT_NS16550A] = {
229 .name = "NS16550A",
230 .fifo_size = 16,
231 .tx_loadsz = 16,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_NATSEMI,
234 },
235 [PORT_XSCALE] = {
236 .name = "XScale",
237 .fifo_size = 32,
238 .tx_loadsz = 32,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
4539c24f 240 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
1da177e4 241 },
6b06f191
DD		 242 [PORT_OCTEON] = {
243 .name = "OCTEON",
244 .fifo_size = 64,
245 .tx_loadsz = 64,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 247 .flags = UART_CAP_FIFO,
248 },
08e0992f
FF		 249 [PORT_AR7] = {
250 .name = "AR7",
251 .fifo_size = 16,
252 .tx_loadsz = 16,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
254 .flags = UART_CAP_FIFO | UART_CAP_AFE,
255 },
235dae5d
PL		 256 [PORT_U6_16550A] = {
257 .name = "U6_16550A",
258 .fifo_size = 64,
259 .tx_loadsz = 64,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
261 .flags = UART_CAP_FIFO | UART_CAP_AFE,
262 },
4539c24f
SW		 263 [PORT_TEGRA] = {
264 .name = "Tegra",
265 .fifo_size = 32,
266 .tx_loadsz = 8,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
268 UART_FCR_T_TRIG_01,
269 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
270 },
06315348
SH		 271 [PORT_XR17D15X] = {
272 .name = "XR17D15X",
273 .fifo_size = 64,
274 .tx_loadsz = 64,
275 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
81db0772
MS		 276 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
277 UART_CAP_SLEEP,
06315348 278 },
dc96efb7
MS		 279 [PORT_XR17V35X] = {
280 .name = "XR17V35X",
281 .fifo_size = 256,
282 .tx_loadsz = 256,
283 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
284 UART_FCR_T_TRIG_11,
285 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
286 UART_CAP_SLEEP,
287 },
7a514596
RS		 288 [PORT_LPC3220] = {
289 .name = "LPC3220",
290 .fifo_size = 64,
291 .tx_loadsz = 32,
292 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
293 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
294 .flags = UART_CAP_FIFO,
295 },
ebebd49a
SH		 296 [PORT_BRCM_TRUMANAGE] = {
297 .name = "TruManage",
298 .fifo_size = 1,
299 .tx_loadsz = 1024,
300 .flags = UART_CAP_HFIFO,
301 },
65ecc9c0
SY		 302 [PORT_8250_CIR] = {
303 .name = "CIR port"
e06c93ca
LFT		 304 },
305 [PORT_ALTR_16550_F32] = {
306 .name = "Altera 16550 FIFO32",
307 .fifo_size = 32,
308 .tx_loadsz = 32,
309 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
310 .flags = UART_CAP_FIFO | UART_CAP_AFE,
311 },
312 [PORT_ALTR_16550_F64] = {
313 .name = "Altera 16550 FIFO64",
314 .fifo_size = 64,
315 .tx_loadsz = 64,
316 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
317 .flags = UART_CAP_FIFO | UART_CAP_AFE,
318 },
319 [PORT_ALTR_16550_F128] = {
320 .name = "Altera 16550 FIFO128",
321 .fifo_size = 128,
322 .tx_loadsz = 128,
323 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
324 .flags = UART_CAP_FIFO | UART_CAP_AFE,
325 },
1da177e4
LT		 326};
327
cc419fa0 328/* Uart divisor latch read */
e8155629 329static int default_serial_dl_read(struct uart_8250_port *up)
cc419fa0
MD		 330{
331 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
332}
333
334/* Uart divisor latch write */
e8155629 335static void default_serial_dl_write(struct uart_8250_port *up, int value)
cc419fa0
MD		 336{
337 serial_out(up, UART_DLL, value & 0xff);
338 serial_out(up, UART_DLM, value >> 8 & 0xff);
339}
340
c420811f 341#if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
21c614a7 342
c420811f 343/* Au1x00/RT288x UART hardware has a weird register layout */
21c614a7
PA		 344static const u8 au_io_in_map[] = {
345 [UART_RX] = 0,
346 [UART_IER] = 2,
347 [UART_IIR] = 3,
348 [UART_LCR] = 5,
349 [UART_MCR] = 6,
350 [UART_LSR] = 7,
351 [UART_MSR] = 8,
352};
353
354static const u8 au_io_out_map[] = {
355 [UART_TX] = 1,
356 [UART_IER] = 2,
357 [UART_FCR] = 4,
358 [UART_LCR] = 5,
359 [UART_MCR] = 6,
360};
361
6b416031 362static unsigned int au_serial_in(struct uart_port *p, int offset)
21c614a7 363{
6b416031
MD		 364 offset = au_io_in_map[offset] << p->regshift;
365 return __raw_readl(p->membase + offset);
21c614a7
PA		 366}
367
6b416031 368static void au_serial_out(struct uart_port *p, int offset, int value)
21c614a7 369{
6b416031
MD		 370 offset = au_io_out_map[offset] << p->regshift;
371 __raw_writel(value, p->membase + offset);
372}
373
374/* Au1x00 haven't got a standard divisor latch */
375static int au_serial_dl_read(struct uart_8250_port *up)
376{
377 return __raw_readl(up->port.membase + 0x28);
378}
379
380static void au_serial_dl_write(struct uart_8250_port *up, int value)
381{
382 __raw_writel(value, up->port.membase + 0x28);
21c614a7
PA		 383}
384
6b416031
MD		 385#endif
386
7d6a07d1 387static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 388{
e8155629 389 offset = offset << p->regshift;
7d6a07d1
DD		 390 outb(p->hub6 - 1 + offset, p->iobase);
391 return inb(p->iobase + 1);
392}
1da177e4 393
7d6a07d1
DD		 394static void hub6_serial_out(struct uart_port *p, int offset, int value)
395{
e8155629 396 offset = offset << p->regshift;
7d6a07d1
DD		 397 outb(p->hub6 - 1 + offset, p->iobase);
398 outb(value, p->iobase + 1);
399}
1da177e4 400
7d6a07d1
DD		 401static unsigned int mem_serial_in(struct uart_port *p, int offset)
402{
e8155629 403 offset = offset << p->regshift;
7d6a07d1
DD		 404 return readb(p->membase + offset);
405}
1da177e4 406
7d6a07d1
DD		 407static void mem_serial_out(struct uart_port *p, int offset, int value)
408{
e8155629 409 offset = offset << p->regshift;
7d6a07d1
DD		 410 writeb(value, p->membase + offset);
411}
412
413static void mem32_serial_out(struct uart_port *p, int offset, int value)
414{
e8155629 415 offset = offset << p->regshift;
7d6a07d1
DD		 416 writel(value, p->membase + offset);
417}
418
419static unsigned int mem32_serial_in(struct uart_port *p, int offset)
420{
e8155629 421 offset = offset << p->regshift;
7d6a07d1
DD		 422 return readl(p->membase + offset);
423}
1da177e4 424
7d6a07d1
DD		 425static unsigned int io_serial_in(struct uart_port *p, int offset)
426{
e8155629 427 offset = offset << p->regshift;
7d6a07d1
DD		 428 return inb(p->iobase + offset);
429}
430
431static void io_serial_out(struct uart_port *p, int offset, int value)
432{
e8155629 433 offset = offset << p->regshift;
7d6a07d1
DD		 434 outb(value, p->iobase + offset);
435}
436
583d28e9 437static int serial8250_default_handle_irq(struct uart_port *port);
dc96efb7 438static int exar_handle_irq(struct uart_port *port);
583d28e9 439
7d6a07d1
DD		 440static void set_io_from_upio(struct uart_port *p)
441{
49d5741b
JI		 442 struct uart_8250_port *up =
443 container_of(p, struct uart_8250_port, port);
cc419fa0 444
e8155629
MD		 445 up->dl_read = default_serial_dl_read;
446 up->dl_write = default_serial_dl_write;
cc419fa0 447
7d6a07d1 448 switch (p->iotype) {
1da177e4 449 case UPIO_HUB6:
7d6a07d1
DD		 450 p->serial_in = hub6_serial_in;
451 p->serial_out = hub6_serial_out;
1da177e4
LT		 452 break;
453
454 case UPIO_MEM:
7d6a07d1
DD		 455 p->serial_in = mem_serial_in;
456 p->serial_out = mem_serial_out;
1da177e4
LT		 457 break;
458
459 case UPIO_MEM32:
7d6a07d1
DD		 460 p->serial_in = mem32_serial_in;
461 p->serial_out = mem32_serial_out;
1da177e4
LT		 462 break;
463
c420811f 464#if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
21c614a7 465 case UPIO_AU:
7d6a07d1
DD		 466 p->serial_in = au_serial_in;
467 p->serial_out = au_serial_out;
6b416031
MD		 468 up->dl_read = au_serial_dl_read;
469 up->dl_write = au_serial_dl_write;
21c614a7 470 break;
6b416031 471#endif
12bf3f24 472
1da177e4 473 default:
7d6a07d1
DD		 474 p->serial_in = io_serial_in;
475 p->serial_out = io_serial_out;
476 break;
1da177e4 477 }
b8e7e40a
AC		 478 /* Remember loaded iotype */
479 up->cur_iotype = p->iotype;
583d28e9 480 p->handle_irq = serial8250_default_handle_irq;
1da177e4
LT		 481}
482
40b36daa 483static void
55e4016d 484serial_port_out_sync(struct uart_port *p, int offset, int value)
40b36daa 485{
7d6a07d1 486 switch (p->iotype) {
40b36daa
AW		 487 case UPIO_MEM:
488 case UPIO_MEM32:
40b36daa 489 case UPIO_AU:
7d6a07d1
DD		 490 p->serial_out(p, offset, value);
491 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 492 break;
493 default:
7d6a07d1 494 p->serial_out(p, offset, value);
40b36daa
AW		 495 }
496}
497
1da177e4
LT		 498/*
499 * For the 16C950
500 */
501static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
502{
503 serial_out(up, UART_SCR, offset);
504 serial_out(up, UART_ICR, value);
505}
506
507static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
508{
509 unsigned int value;
510
511 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
512 serial_out(up, UART_SCR, offset);
513 value = serial_in(up, UART_ICR);
514 serial_icr_write(up, UART_ACR, up->acr);
515
516 return value;
517}
518
519/*
520 * FIFO support.
521 */
b5d674ab 522static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 523{
524 if (p->capabilities & UART_CAP_FIFO) {
0acf519f
PG		 525 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
526 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
1da177e4 527 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0acf519f 528 serial_out(p, UART_FCR, 0);
1da177e4
LT		 529 }
530}
531
0ad372b9
SM		 532void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
533{
534 unsigned char fcr;
535
536 serial8250_clear_fifos(p);
537 fcr = uart_config[p->port.type].fcr;
538 serial_out(p, UART_FCR, fcr);
539}
540EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
541
1da177e4
LT		 542/*
543 * IER sleep support. UARTs which have EFRs need the "extended
544 * capability" bit enabled. Note that on XR16C850s, we need to
545 * reset LCR to write to IER.
546 */
b5d674ab 547static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4 548{
dc96efb7
MS		 549 /*
550 * Exar UARTs have a SLEEP register that enables or disables
551 * each UART to enter sleep mode separately. On the XR17V35x the
552 * register is accessible to each UART at the UART_EXAR_SLEEP
553 * offset but the UART channel may only write to the corresponding
554 * bit.
555 */
81db0772
MS		 556 if ((p->port.type == PORT_XR17V35X) ||
557 (p->port.type == PORT_XR17D15X)) {
dc96efb7
MS		 558 serial_out(p, UART_EXAR_SLEEP, 0xff);
559 return;
560 }
561
1da177e4
LT		 562 if (p->capabilities & UART_CAP_SLEEP) {
563 if (p->capabilities & UART_CAP_EFR) {
0acf519f
PG		 564 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
565 serial_out(p, UART_EFR, UART_EFR_ECB);
566 serial_out(p, UART_LCR, 0);
1da177e4 567 }
0acf519f 568 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
1da177e4 569 if (p->capabilities & UART_CAP_EFR) {
0acf519f
PG		 570 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
571 serial_out(p, UART_EFR, 0);
572 serial_out(p, UART_LCR, 0);
1da177e4
LT		 573 }
574 }
575}
576
577#ifdef CONFIG_SERIAL_8250_RSA
578/*
579 * Attempts to turn on the RSA FIFO. Returns zero on failure.
580 * We set the port uart clock rate if we succeed.
581 */
582static int __enable_rsa(struct uart_8250_port *up)
583{
584 unsigned char mode;
585 int result;
586
0acf519f 587 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 588 result = mode & UART_RSA_MSR_FIFO;
589
590 if (!result) {
0acf519f
PG		 591 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
592 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 593 result = mode & UART_RSA_MSR_FIFO;
594 }
595
596 if (result)
597 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
598
599 return result;
600}
601
602static void enable_rsa(struct uart_8250_port *up)
603{
604 if (up->port.type == PORT_RSA) {
605 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
606 spin_lock_irq(&up->port.lock);
607 __enable_rsa(up);
608 spin_unlock_irq(&up->port.lock);
609 }
610 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
0acf519f 611 serial_out(up, UART_RSA_FRR, 0);
1da177e4
LT		 612 }
613}
614
615/*
616 * Attempts to turn off the RSA FIFO. Returns zero on failure.
617 * It is unknown why interrupts were disabled in here. However,
618 * the caller is expected to preserve this behaviour by grabbing
619 * the spinlock before calling this function.
620 */
621static void disable_rsa(struct uart_8250_port *up)
622{
623 unsigned char mode;
624 int result;
625
626 if (up->port.type == PORT_RSA &&
627 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
628 spin_lock_irq(&up->port.lock);
629
0acf519f 630 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 631 result = !(mode & UART_RSA_MSR_FIFO);
632
633 if (!result) {
0acf519f
PG		 634 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
635 mode = serial_in(up, UART_RSA_MSR);
1da177e4
LT		 636 result = !(mode & UART_RSA_MSR_FIFO);
637 }
638
639 if (result)
640 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
641 spin_unlock_irq(&up->port.lock);
642 }
643}
644#endif /* CONFIG_SERIAL_8250_RSA */
645
646/*
647 * This is a quickie test to see how big the FIFO is.
648 * It doesn't work at all the time, more's the pity.
649 */
650static int size_fifo(struct uart_8250_port *up)
651{
b32b19b8
JAH		 652 unsigned char old_fcr, old_mcr, old_lcr;
653 unsigned short old_dl;
1da177e4
LT		 654 int count;
655
0acf519f
PG		 656 old_lcr = serial_in(up, UART_LCR);
657 serial_out(up, UART_LCR, 0);
658 old_fcr = serial_in(up, UART_FCR);
659 old_mcr = serial_in(up, UART_MCR);
660 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1da177e4 661 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
0acf519f
PG		 662 serial_out(up, UART_MCR, UART_MCR_LOOP);
663 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8
JAH		 664 old_dl = serial_dl_read(up);
665 serial_dl_write(up, 0x0001);
0acf519f 666 serial_out(up, UART_LCR, 0x03);
1da177e4 667 for (count = 0; count < 256; count++)
0acf519f 668 serial_out(up, UART_TX, count);
1da177e4 669 mdelay(20);/* FIXME - schedule_timeout */
0acf519f 670 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
1da177e4 671 (count < 256); count++)
0acf519f
PG		 672 serial_in(up, UART_RX);
673 serial_out(up, UART_FCR, old_fcr);
674 serial_out(up, UART_MCR, old_mcr);
675 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8 676 serial_dl_write(up, old_dl);
0acf519f 677 serial_out(up, UART_LCR, old_lcr);
1da177e4
LT		 678
679 return count;
680}
681
682/*
683 * Read UART ID using the divisor method - set DLL and DLM to zero
684 * and the revision will be in DLL and device type in DLM. We
685 * preserve the device state across this.
686 */
687static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
688{
689 unsigned char old_dll, old_dlm, old_lcr;
690 unsigned int id;
691
0acf519f
PG		 692 old_lcr = serial_in(p, UART_LCR);
693 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4 694
0acf519f
PG		 695 old_dll = serial_in(p, UART_DLL);
696 old_dlm = serial_in(p, UART_DLM);
1da177e4 697
0acf519f
PG		 698 serial_out(p, UART_DLL, 0);
699 serial_out(p, UART_DLM, 0);
1da177e4 700
0acf519f 701 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
1da177e4 702
0acf519f
PG		 703 serial_out(p, UART_DLL, old_dll);
704 serial_out(p, UART_DLM, old_dlm);
705 serial_out(p, UART_LCR, old_lcr);
1da177e4
LT		 706
707 return id;
708}
709
710/*
711 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
712 * When this function is called we know it is at least a StarTech
713 * 16650 V2, but it might be one of several StarTech UARTs, or one of
714 * its clones. (We treat the broken original StarTech 16650 V1 as a
715 * 16550, and why not? Startech doesn't seem to even acknowledge its
716 * existence.)
bd71c182 717 *
1da177e4
LT		 718 * What evil have men's minds wrought...
719 */
720static void autoconfig_has_efr(struct uart_8250_port *up)
721{
722 unsigned int id1, id2, id3, rev;
723
724 /*
725 * Everything with an EFR has SLEEP
726 */
727 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
728
729 /*
730 * First we check to see if it's an Oxford Semiconductor UART.
731 *
732 * If we have to do this here because some non-National
733 * Semiconductor clone chips lock up if you try writing to the
734 * LSR register (which serial_icr_read does)
735 */
736
737 /*
738 * Check for Oxford Semiconductor 16C950.
739 *
740 * EFR [4] must be set else this test fails.
741 *
742 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
743 * claims that it's needed for 952 dual UART's (which are not
744 * recommended for new designs).
745 */
746 up->acr = 0;
662b083a 747 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 748 serial_out(up, UART_EFR, UART_EFR_ECB);
749 serial_out(up, UART_LCR, 0x00);
750 id1 = serial_icr_read(up, UART_ID1);
751 id2 = serial_icr_read(up, UART_ID2);
752 id3 = serial_icr_read(up, UART_ID3);
753 rev = serial_icr_read(up, UART_REV);
754
755 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
756
757 if (id1 == 0x16 && id2 == 0xC9 &&
758 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
759 up->port.type = PORT_16C950;
4ba5e35d
RK		 760
761 /*
762 * Enable work around for the Oxford Semiconductor 952 rev B
763 * chip which causes it to seriously miscalculate baud rates
764 * when DLL is 0.
765 */
766 if (id3 == 0x52 && rev == 0x01)
767 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 768 return;
769 }
bd71c182 770
1da177e4
LT		 771 /*
772 * We check for a XR16C850 by setting DLL and DLM to 0, and then
773 * reading back DLL and DLM. The chip type depends on the DLM
774 * value read back:
775 * 0x10 - XR16C850 and the DLL contains the chip revision.
776 * 0x12 - XR16C2850.
777 * 0x14 - XR16C854.
778 */
779 id1 = autoconfig_read_divisor_id(up);
780 DEBUG_AUTOCONF("850id=%04x ", id1);
781
782 id2 = id1 >> 8;
783 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 784 up->port.type = PORT_16850;
785 return;
786 }
787
788 /*
789 * It wasn't an XR16C850.
790 *
791 * We distinguish between the '654 and the '650 by counting
792 * how many bytes are in the FIFO. I'm using this for now,
793 * since that's the technique that was sent to me in the
794 * serial driver update, but I'm not convinced this works.
795 * I've had problems doing this in the past. -TYT
796 */
797 if (size_fifo(up) == 64)
798 up->port.type = PORT_16654;
799 else
800 up->port.type = PORT_16650V2;
801}
802
803/*
804 * We detected a chip without a FIFO. Only two fall into
805 * this category - the original 8250 and the 16450. The
806 * 16450 has a scratch register (accessible with LCR=0)
807 */
808static void autoconfig_8250(struct uart_8250_port *up)
809{
810 unsigned char scratch, status1, status2;
811
812 up->port.type = PORT_8250;
813
814 scratch = serial_in(up, UART_SCR);
0acf519f 815 serial_out(up, UART_SCR, 0xa5);
1da177e4 816 status1 = serial_in(up, UART_SCR);
0acf519f 817 serial_out(up, UART_SCR, 0x5a);
1da177e4 818 status2 = serial_in(up, UART_SCR);
0acf519f 819 serial_out(up, UART_SCR, scratch);
1da177e4
LT		 820
821 if (status1 == 0xa5 && status2 == 0x5a)
822 up->port.type = PORT_16450;
823}
824
825static int broken_efr(struct uart_8250_port *up)
826{
827 /*
828 * Exar ST16C2550 "A2" devices incorrectly detect as
829 * having an EFR, and report an ID of 0x0201. See
631dd1a8 830 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1da177e4
LT		 831 */
832 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
833 return 1;
834
835 return 0;
836}
837
0d0389e5
YK		 838static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
839{
840 unsigned char status;
841
842 status = serial_in(up, 0x04); /* EXCR2 */
843#define PRESL(x) ((x) & 0x30)
844 if (PRESL(status) == 0x10) {
845 /* already in high speed mode */
846 return 0;
847 } else {
848 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
849 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
0acf519f 850 serial_out(up, 0x04, status);
0d0389e5
YK		 851 }
852 return 1;
853}
854
1da177e4
LT		 855/*
856 * We know that the chip has FIFOs. Does it have an EFR? The
857 * EFR is located in the same register position as the IIR and
858 * we know the top two bits of the IIR are currently set. The
859 * EFR should contain zero. Try to read the EFR.
860 */
861static void autoconfig_16550a(struct uart_8250_port *up)
862{
863 unsigned char status1, status2;
864 unsigned int iersave;
865
866 up->port.type = PORT_16550A;
867 up->capabilities |= UART_CAP_FIFO;
868
dc96efb7
MS		 869 /*
870 * XR17V35x UARTs have an extra divisor register, DLD
871 * that gets enabled with when DLAB is set which will
872 * cause the device to incorrectly match and assign
873 * port type to PORT_16650. The EFR for this UART is
874 * found at offset 0x09. Instead check the Deice ID (DVID)
875 * register for a 2, 4 or 8 port UART.
876 */
b7a7e14f
MS		 877 if (up->port.flags & UPF_EXAR_EFR) {
878 status1 = serial_in(up, UART_EXAR_DVID);
879 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
dc96efb7
MS		 880 DEBUG_AUTOCONF("Exar XR17V35x ");
881 up->port.type = PORT_XR17V35X;
882 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
883 UART_CAP_SLEEP;
884
885 return;
886 }
887
888 }
889
1da177e4
LT		 890 /*
891 * Check for presence of the EFR when DLAB is set.
892 * Only ST16C650V1 UARTs pass this test.
893 */
0acf519f 894 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4 895 if (serial_in(up, UART_EFR) == 0) {
0acf519f 896 serial_out(up, UART_EFR, 0xA8);
1da177e4
LT		 897 if (serial_in(up, UART_EFR) != 0) {
898 DEBUG_AUTOCONF("EFRv1 ");
899 up->port.type = PORT_16650;
900 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
901 } else {
902 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
903 }
0acf519f 904 serial_out(up, UART_EFR, 0);
1da177e4
LT		 905 return;
906 }
907
908 /*
909 * Maybe it requires 0xbf to be written to the LCR.
910 * (other ST16C650V2 UARTs, TI16C752A, etc)
911 */
0acf519f 912 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 913 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
914 DEBUG_AUTOCONF("EFRv2 ");
915 autoconfig_has_efr(up);
916 return;
917 }
918
919 /*
920 * Check for a National Semiconductor SuperIO chip.
921 * Attempt to switch to bank 2, read the value of the LOOP bit
922 * from EXCR1. Switch back to bank 0, change it in MCR. Then
923 * switch back to bank 2, read it from EXCR1 again and check
924 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4 925 */
0acf519f 926 serial_out(up, UART_LCR, 0);
1da177e4 927 status1 = serial_in(up, UART_MCR);
0acf519f 928 serial_out(up, UART_LCR, 0xE0);
1da177e4
LT		 929 status2 = serial_in(up, 0x02); /* EXCR1 */
930
931 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
0acf519f
PG		 932 serial_out(up, UART_LCR, 0);
933 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
934 serial_out(up, UART_LCR, 0xE0);
1da177e4 935 status2 = serial_in(up, 0x02); /* EXCR1 */
0acf519f
PG		 936 serial_out(up, UART_LCR, 0);
937 serial_out(up, UART_MCR, status1);
1da177e4
LT		 938
939 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 940 unsigned short quot;
941
0acf519f 942 serial_out(up, UART_LCR, 0xE0);
857dde2e 943
b32b19b8 944 quot = serial_dl_read(up);
857dde2e
DW		 945 quot <<= 3;
946
0d0389e5
YK		 947 if (ns16550a_goto_highspeed(up))
948 serial_dl_write(up, quot);
857dde2e 949
0acf519f 950 serial_out(up, UART_LCR, 0);
1da177e4 951
857dde2e 952 up->port.uartclk = 921600*16;
1da177e4
LT		 953 up->port.type = PORT_NS16550A;
954 up->capabilities |= UART_NATSEMI;
955 return;
956 }
957 }
958
959 /*
960 * No EFR. Try to detect a TI16750, which only sets bit 5 of
961 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
962 * Try setting it with and without DLAB set. Cheap clones
963 * set bit 5 without DLAB set.
964 */
0acf519f
PG		 965 serial_out(up, UART_LCR, 0);
966 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1da177e4 967 status1 = serial_in(up, UART_IIR) >> 5;
0acf519f
PG		 968 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
969 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
970 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1da177e4 971 status2 = serial_in(up, UART_IIR) >> 5;
0acf519f
PG		 972 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
973 serial_out(up, UART_LCR, 0);
1da177e4
LT		 974
975 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
976
977 if (status1 == 6 && status2 == 7) {
978 up->port.type = PORT_16750;
979 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
980 return;
981 }
982
983 /*
984 * Try writing and reading the UART_IER_UUE bit (b6).
985 * If it works, this is probably one of the Xscale platform's
986 * internal UARTs.
987 * We're going to explicitly set the UUE bit to 0 before
988 * trying to write and read a 1 just to make sure it's not
989 * already a 1 and maybe locked there before we even start start.
990 */
991 iersave = serial_in(up, UART_IER);
0acf519f 992 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1da177e4
LT		 993 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
994 /*
995 * OK it's in a known zero state, try writing and reading
996 * without disturbing the current state of the other bits.
997 */
0acf519f 998 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1da177e4
LT		 999 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1000 /*
1001 * It's an Xscale.
1002 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1003 */
1004 DEBUG_AUTOCONF("Xscale ");
1005 up->port.type = PORT_XSCALE;
5568181f 1006 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1da177e4
LT		 1007 return;
1008 }
1009 } else {
1010 /*
1011 * If we got here we couldn't force the IER_UUE bit to 0.
1012 * Log it and continue.
1013 */
1014 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1015 }
0acf519f 1016 serial_out(up, UART_IER, iersave);
235dae5d 1017
06315348
SH		 1018 /*
1019 * Exar uarts have EFR in a weird location
1020 */
1021 if (up->port.flags & UPF_EXAR_EFR) {
81db0772 1022 DEBUG_AUTOCONF("Exar XR17D15x ");
06315348 1023 up->port.type = PORT_XR17D15X;
81db0772
MS		 1024 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1025 UART_CAP_SLEEP;
1026
1027 return;
06315348
SH		 1028 }
1029
235dae5d
PL		 1030 /*
1031 * We distinguish between 16550A and U6 16550A by counting
1032 * how many bytes are in the FIFO.
1033 */
1034 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1035 up->port.type = PORT_U6_16550A;
1036 up->capabilities |= UART_CAP_AFE;
1037 }
1da177e4
LT		 1038}
1039
1040/*
1041 * This routine is called by rs_init() to initialize a specific serial
1042 * port. It determines what type of UART chip this serial port is
1043 * using: 8250, 16450, 16550, 16550A. The important question is
1044 * whether or not this UART is a 16550A or not, since this will
1045 * determine whether or not we can use its FIFO features or not.
1046 */
1047static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1048{
1049 unsigned char status1, scratch, scratch2, scratch3;
1050 unsigned char save_lcr, save_mcr;
dfe42443 1051 struct uart_port *port = &up->port;
1da177e4 1052 unsigned long flags;
bd21f551 1053 unsigned int old_capabilities;
1da177e4 1054
dfe42443 1055 if (!port->iobase && !port->mapbase && !port->membase)
1da177e4
LT		 1056 return;
1057
80647b95 1058 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
dfe42443 1059 serial_index(port), port->iobase, port->membase);
1da177e4
LT		 1060
1061 /*
1062 * We really do need global IRQs disabled here - we're going to
1063 * be frobbing the chips IRQ enable register to see if it exists.
1064 */
dfe42443 1065 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 1066
1067 up->capabilities = 0;
4ba5e35d 1068 up->bugs = 0;
1da177e4 1069
dfe42443 1070 if (!(port->flags & UPF_BUGGY_UART)) {
1da177e4
LT		 1071 /*
1072 * Do a simple existence test first; if we fail this,
1073 * there's no point trying anything else.
bd71c182 1074 *
1da177e4
LT		 1075 * 0x80 is used as a nonsense port to prevent against
1076 * false positives due to ISA bus float. The
1077 * assumption is that 0x80 is a non-existent port;
1078 * which should be safe since include/asm/io.h also
1079 * makes this assumption.
1080 *
1081 * Note: this is safe as long as MCR bit 4 is clear
1082 * and the device is in "PC" mode.
1083 */
0acf519f
PG		 1084 scratch = serial_in(up, UART_IER);
1085 serial_out(up, UART_IER, 0);
1da177e4
LT		 1086#ifdef __i386__
1087 outb(0xff, 0x080);
1088#endif
48212008
TH		 1089 /*
1090 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1091 * 16C754B) allow only to modify them if an EFR bit is set.
1092 */
0acf519f
PG		 1093 scratch2 = serial_in(up, UART_IER) & 0x0f;
1094 serial_out(up, UART_IER, 0x0F);
1da177e4
LT		 1095#ifdef __i386__
1096 outb(0, 0x080);
1097#endif
0acf519f
PG		 1098 scratch3 = serial_in(up, UART_IER) & 0x0f;
1099 serial_out(up, UART_IER, scratch);
1da177e4
LT		 1100 if (scratch2 != 0 || scratch3 != 0x0F) {
1101 /*
1102 * We failed; there's nothing here
1103 */
bd21f551 1104 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1105 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1106 scratch2, scratch3);
1107 goto out;
1108 }
1109 }
1110
1111 save_mcr = serial_in(up, UART_MCR);
1112 save_lcr = serial_in(up, UART_LCR);
1113
bd71c182 1114 /*
1da177e4
LT		 1115 * Check to see if a UART is really there. Certain broken
1116 * internal modems based on the Rockwell chipset fail this
1117 * test, because they apparently don't implement the loopback
1118 * test mode. So this test is skipped on the COM 1 through
1119 * COM 4 ports. This *should* be safe, since no board
1120 * manufacturer would be stupid enough to design a board
1121 * that conflicts with COM 1-4 --- we hope!
1122 */
dfe42443 1123 if (!(port->flags & UPF_SKIP_TEST)) {
0acf519f
PG		 1124 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1125 status1 = serial_in(up, UART_MSR) & 0xF0;
1126 serial_out(up, UART_MCR, save_mcr);
1da177e4 1127 if (status1 != 0x90) {
bd21f551 1128 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1129 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1130 status1);
1131 goto out;
1132 }
1133 }
1134
1135 /*
1136 * We're pretty sure there's a port here. Lets find out what
1137 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1138 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1139 * determines what we test for next.
1140 *
1141 * We also initialise the EFR (if any) to zero for later. The
1142 * EFR occupies the same register location as the FCR and IIR.
1143 */
0acf519f
PG		 1144 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1145 serial_out(up, UART_EFR, 0);
1146 serial_out(up, UART_LCR, 0);
1da177e4 1147
0acf519f 1148 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1da177e4
LT		 1149 scratch = serial_in(up, UART_IIR) >> 6;
1150
1da177e4
LT		 1151 switch (scratch) {
1152 case 0:
1153 autoconfig_8250(up);
1154 break;
1155 case 1:
dfe42443 1156 port->type = PORT_UNKNOWN;
1da177e4
LT		 1157 break;
1158 case 2:
dfe42443 1159 port->type = PORT_16550;
1da177e4
LT		 1160 break;
1161 case 3:
1162 autoconfig_16550a(up);
1163 break;
1164 }
1165
1166#ifdef CONFIG_SERIAL_8250_RSA
1167 /*
1168 * Only probe for RSA ports if we got the region.
1169 */
dfe42443 1170 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1da177e4
LT		 1171 int i;
1172
1173 for (i = 0 ; i < probe_rsa_count; ++i) {
dfe42443
PG		 1174 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1175 port->type = PORT_RSA;
1da177e4
LT		 1176 break;
1177 }
1178 }
1179 }
1180#endif
21c614a7 1181
0acf519f 1182 serial_out(up, UART_LCR, save_lcr);
1da177e4 1183
dfe42443 1184 port->fifosize = uart_config[up->port.type].fifo_size;
bd21f551 1185 old_capabilities = up->capabilities;
dfe42443
PG		 1186 up->capabilities = uart_config[port->type].flags;
1187 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1da177e4 1188
dfe42443 1189 if (port->type == PORT_UNKNOWN)
bd21f551 1190 goto out_lock;
1da177e4
LT		 1191
1192 /*
1193 * Reset the UART.
1194 */
1195#ifdef CONFIG_SERIAL_8250_RSA
dfe42443 1196 if (port->type == PORT_RSA)
0acf519f 1197 serial_out(up, UART_RSA_FRR, 0);
1da177e4 1198#endif
0acf519f 1199 serial_out(up, UART_MCR, save_mcr);
1da177e4 1200 serial8250_clear_fifos(up);
40b36daa 1201 serial_in(up, UART_RX);
5c8c755c 1202 if (up->capabilities & UART_CAP_UUE)
0acf519f 1203 serial_out(up, UART_IER, UART_IER_UUE);
5c8c755c 1204 else
0acf519f 1205 serial_out(up, UART_IER, 0);
1da177e4 1206
bd21f551 1207out_lock:
dfe42443 1208 spin_unlock_irqrestore(&port->lock, flags);
bd21f551
FL		 1209 if (up->capabilities != old_capabilities) {
1210 printk(KERN_WARNING
1211 "ttyS%d: detected caps %08x should be %08x\n",
1212 serial_index(port), old_capabilities,
1213 up->capabilities);
1214 }
1215out:
1216 DEBUG_AUTOCONF("iir=%d ", scratch);
dfe42443 1217 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1da177e4
LT		 1218}
1219
1220static void autoconfig_irq(struct uart_8250_port *up)
1221{
dfe42443 1222 struct uart_port *port = &up->port;
1da177e4
LT		 1223 unsigned char save_mcr, save_ier;
1224 unsigned char save_ICP = 0;
1225 unsigned int ICP = 0;
1226 unsigned long irqs;
1227 int irq;
1228
dfe42443
PG		 1229 if (port->flags & UPF_FOURPORT) {
1230 ICP = (port->iobase & 0xfe0) | 0x1f;
1da177e4
LT		 1231 save_ICP = inb_p(ICP);
1232 outb_p(0x80, ICP);
0d263a26 1233 inb_p(ICP);
1da177e4
LT		 1234 }
1235
1236 /* forget possible initially masked and pending IRQ */
1237 probe_irq_off(probe_irq_on());
0acf519f
PG		 1238 save_mcr = serial_in(up, UART_MCR);
1239 save_ier = serial_in(up, UART_IER);
1240 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1241
1da177e4 1242 irqs = probe_irq_on();
0acf519f 1243 serial_out(up, UART_MCR, 0);
6f803cd0 1244 udelay(10);
dfe42443 1245 if (port->flags & UPF_FOURPORT) {
0acf519f 1246 serial_out(up, UART_MCR,
1da177e4
LT		 1247 UART_MCR_DTR | UART_MCR_RTS);
1248 } else {
0acf519f 1249 serial_out(up, UART_MCR,
1da177e4
LT		 1250 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1251 }
0acf519f 1252 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
0d263a26
PG		 1253 serial_in(up, UART_LSR);
1254 serial_in(up, UART_RX);
1255 serial_in(up, UART_IIR);
1256 serial_in(up, UART_MSR);
0acf519f 1257 serial_out(up, UART_TX, 0xFF);
6f803cd0 1258 udelay(20);
1da177e4
LT		 1259 irq = probe_irq_off(irqs);
1260
0acf519f
PG		 1261 serial_out(up, UART_MCR, save_mcr);
1262 serial_out(up, UART_IER, save_ier);
1da177e4 1263
dfe42443 1264 if (port->flags & UPF_FOURPORT)
1da177e4
LT		 1265 outb_p(save_ICP, ICP);
1266
dfe42443 1267 port->irq = (irq > 0) ? irq : 0;
1da177e4
LT		 1268}
1269
e763b90c
RK		 1270static inline void __stop_tx(struct uart_8250_port *p)
1271{
1272 if (p->ier & UART_IER_THRI) {
1273 p->ier &= ~UART_IER_THRI;
1274 serial_out(p, UART_IER, p->ier);
1275 }
1276}
1277
b129a8cc 1278static void serial8250_stop_tx(struct uart_port *port)
1da177e4 1279{
49d5741b
JI		 1280 struct uart_8250_port *up =
1281 container_of(port, struct uart_8250_port, port);
1da177e4 1282
e763b90c 1283 __stop_tx(up);
1da177e4
LT		 1284
1285 /*
e763b90c 1286 * We really want to stop the transmitter from sending.
1da177e4 1287 */
dfe42443 1288 if (port->type == PORT_16C950) {
1da177e4
LT		 1289 up->acr |= UART_ACR_TXDIS;
1290 serial_icr_write(up, UART_ACR, up->acr);
1291 }
1292}
1293
b129a8cc 1294static void serial8250_start_tx(struct uart_port *port)
1da177e4 1295{
49d5741b
JI		 1296 struct uart_8250_port *up =
1297 container_of(port, struct uart_8250_port, port);
1da177e4 1298
9ee4b83e
HK		 1299 if (up->dma && !serial8250_tx_dma(up)) {
1300 return;
1301 } else if (!(up->ier & UART_IER_THRI)) {
1da177e4 1302 up->ier |= UART_IER_THRI;
4fd996a1 1303 serial_port_out(port, UART_IER, up->ier);
55d3b282 1304
67f7654e 1305 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1306 unsigned char lsr;
55d3b282 1307 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1308 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
a205a56d 1309 if (lsr & UART_LSR_TEMT)
3986fb2b 1310 serial8250_tx_chars(up);
55d3b282 1311 }
1da177e4 1312 }
e763b90c 1313
1da177e4 1314 /*
e763b90c 1315 * Re-enable the transmitter if we disabled it.
1da177e4 1316 */
dfe42443 1317 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1318 up->acr &= ~UART_ACR_TXDIS;
1319 serial_icr_write(up, UART_ACR, up->acr);
1320 }
1321}
1322
1323static void serial8250_stop_rx(struct uart_port *port)
1324{
49d5741b
JI		 1325 struct uart_8250_port *up =
1326 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1327
1328 up->ier &= ~UART_IER_RLSI;
1329 up->port.read_status_mask &= ~UART_LSR_DR;
4fd996a1 1330 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 1331}
1332
1333static void serial8250_enable_ms(struct uart_port *port)
1334{
49d5741b
JI		 1335 struct uart_8250_port *up =
1336 container_of(port, struct uart_8250_port, port);
1da177e4 1337
21c614a7
PA		 1338 /* no MSR capabilities */
1339 if (up->bugs & UART_BUG_NOMSR)
1340 return;
1341
1da177e4 1342 up->ier |= UART_IER_MSI;
4fd996a1 1343 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 1344}
1345
0690f41f 1346/*
3986fb2b 1347 * serial8250_rx_chars: processes according to the passed in LSR
0690f41f
PG		 1348 * value, and returns the remaining LSR bits not handled
1349 * by this Rx routine.
1350 */
3986fb2b
PG		 1351unsigned char
1352serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1da177e4 1353{
dfe42443 1354 struct uart_port *port = &up->port;
0690f41f 1355 unsigned char ch;
1da177e4
LT		 1356 int max_count = 256;
1357 char flag;
1358
1359 do {
7500b1f6 1360 if (likely(lsr & UART_LSR_DR))
0acf519f 1361 ch = serial_in(up, UART_RX);
7500b1f6
AR		 1362 else
1363 /*
1364 * Intel 82571 has a Serial Over Lan device that will
1365 * set UART_LSR_BI without setting UART_LSR_DR when
1366 * it receives a break. To avoid reading from the
1367 * receive buffer without UART_LSR_DR bit set, we
1368 * just force the read character to be 0
1369 */
1370 ch = 0;
1371
1da177e4 1372 flag = TTY_NORMAL;
dfe42443 1373 port->icount.rx++;
1da177e4 1374
ad4c2aa6
CM		 1375 lsr |= up->lsr_saved_flags;
1376 up->lsr_saved_flags = 0;
1da177e4 1377
ad4c2aa6 1378 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1379 if (lsr & UART_LSR_BI) {
1380 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
dfe42443 1381 port->icount.brk++;
1da177e4
LT		 1382 /*
1383 * We do the SysRQ and SAK checking
1384 * here because otherwise the break
1385 * may get masked by ignore_status_mask
1386 * or read_status_mask.
1387 */
dfe42443 1388 if (uart_handle_break(port))
1da177e4
LT		 1389 goto ignore_char;
1390 } else if (lsr & UART_LSR_PE)
dfe42443 1391 port->icount.parity++;
1da177e4 1392 else if (lsr & UART_LSR_FE)
dfe42443 1393 port->icount.frame++;
1da177e4 1394 if (lsr & UART_LSR_OE)
dfe42443 1395 port->icount.overrun++;
1da177e4
LT		 1396
1397 /*
23907eb8 1398 * Mask off conditions which should be ignored.
1da177e4 1399 */
dfe42443 1400 lsr &= port->read_status_mask;
1da177e4
LT		 1401
1402 if (lsr & UART_LSR_BI) {
1403 DEBUG_INTR("handling break....");
1404 flag = TTY_BREAK;
1405 } else if (lsr & UART_LSR_PE)
1406 flag = TTY_PARITY;
1407 else if (lsr & UART_LSR_FE)
1408 flag = TTY_FRAME;
1409 }
dfe42443 1410 if (uart_handle_sysrq_char(port, ch))
1da177e4 1411 goto ignore_char;
05ab3014 1412
dfe42443 1413 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
05ab3014 1414
6f803cd0 1415ignore_char:
0acf519f 1416 lsr = serial_in(up, UART_LSR);
7500b1f6 1417 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
dfe42443 1418 spin_unlock(&port->lock);
2e124b4a 1419 tty_flip_buffer_push(&port->state->port);
dfe42443 1420 spin_lock(&port->lock);
0690f41f 1421 return lsr;
1da177e4 1422}
3986fb2b 1423EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1da177e4 1424
3986fb2b 1425void serial8250_tx_chars(struct uart_8250_port *up)
1da177e4 1426{
dfe42443
PG		 1427 struct uart_port *port = &up->port;
1428 struct circ_buf *xmit = &port->state->xmit;
1da177e4
LT		 1429 int count;
1430
dfe42443
PG		 1431 if (port->x_char) {
1432 serial_out(up, UART_TX, port->x_char);
1433 port->icount.tx++;
1434 port->x_char = 0;
1da177e4
LT		 1435 return;
1436 }
dfe42443
PG		 1437 if (uart_tx_stopped(port)) {
1438 serial8250_stop_tx(port);
b129a8cc
RK		 1439 return;
1440 }
1441 if (uart_circ_empty(xmit)) {
e763b90c 1442 __stop_tx(up);
1da177e4
LT		 1443 return;
1444 }
1445
1446 count = up->tx_loadsz;
1447 do {
1448 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1449 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
dfe42443 1450 port->icount.tx++;
1da177e4
LT		 1451 if (uart_circ_empty(xmit))
1452 break;
ebebd49a
SH		 1453 if (up->capabilities & UART_CAP_HFIFO) {
1454 if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1455 BOTH_EMPTY)
1456 break;
1457 }
1da177e4
LT		 1458 } while (--count > 0);
1459
1460 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
dfe42443 1461 uart_write_wakeup(port);
1da177e4
LT		 1462
1463 DEBUG_INTR("THRE...");
1464
1465 if (uart_circ_empty(xmit))
e763b90c 1466 __stop_tx(up);
1da177e4 1467}
3986fb2b 1468EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1da177e4 1469
3986fb2b 1470unsigned int serial8250_modem_status(struct uart_8250_port *up)
1da177e4 1471{
dfe42443 1472 struct uart_port *port = &up->port;
2af7cd68
RK		 1473 unsigned int status = serial_in(up, UART_MSR);
1474
ad4c2aa6
CM		 1475 status |= up->msr_saved_flags;
1476 up->msr_saved_flags = 0;
fdc30b3d 1477 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
dfe42443 1478 port->state != NULL) {
2af7cd68 1479 if (status & UART_MSR_TERI)
dfe42443 1480 port->icount.rng++;
2af7cd68 1481 if (status & UART_MSR_DDSR)
dfe42443 1482 port->icount.dsr++;
2af7cd68 1483 if (status & UART_MSR_DDCD)
dfe42443 1484 uart_handle_dcd_change(port, status & UART_MSR_DCD);
2af7cd68 1485 if (status & UART_MSR_DCTS)
dfe42443 1486 uart_handle_cts_change(port, status & UART_MSR_CTS);
2af7cd68 1487
dfe42443 1488 wake_up_interruptible(&port->state->port.delta_msr_wait);
2af7cd68 1489 }
1da177e4 1490
2af7cd68 1491 return status;
1da177e4 1492}
3986fb2b 1493EXPORT_SYMBOL_GPL(serial8250_modem_status);
1da177e4
LT		 1494
1495/*
1496 * This handles the interrupt from one port.
1497 */
86b21199 1498int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1da177e4 1499{
0690f41f 1500 unsigned char status;
4bf3631c 1501 unsigned long flags;
86b21199
PG		 1502 struct uart_8250_port *up =
1503 container_of(port, struct uart_8250_port, port);
9ee4b83e 1504 int dma_err = 0;
86b21199
PG		 1505
1506 if (iir & UART_IIR_NO_INT)
1507 return 0;
45e24601 1508
dfe42443 1509 spin_lock_irqsave(&port->lock, flags);
45e24601 1510
4fd996a1 1511 status = serial_port_in(port, UART_LSR);
1da177e4
LT		 1512
1513 DEBUG_INTR("status = %x...", status);
1514
9ee4b83e
HK		 1515 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1516 if (up->dma)
1517 dma_err = serial8250_rx_dma(up, iir);
1518
1519 if (!up->dma || dma_err)
1520 status = serial8250_rx_chars(up, status);
1521 }
3986fb2b 1522 serial8250_modem_status(up);
1da177e4 1523 if (status & UART_LSR_THRE)
3986fb2b 1524 serial8250_tx_chars(up);
45e24601 1525
dfe42443 1526 spin_unlock_irqrestore(&port->lock, flags);
86b21199 1527 return 1;
583d28e9 1528}
c7a1bdc5 1529EXPORT_SYMBOL_GPL(serial8250_handle_irq);
583d28e9
JI		 1530
1531static int serial8250_default_handle_irq(struct uart_port *port)
1532{
4fd996a1 1533 unsigned int iir = serial_port_in(port, UART_IIR);
583d28e9
JI		 1534
1535 return serial8250_handle_irq(port, iir);
1536}
1537
dc96efb7
MS		 1538/*
1539 * These Exar UARTs have an extra interrupt indicator that could
1540 * fire for a few unimplemented interrupts. One of which is a
1541 * wakeup event when coming out of sleep. Put this here just
1542 * to be on the safe side that these interrupts don't go unhandled.
1543 */
1544static int exar_handle_irq(struct uart_port *port)
1545{
1546 unsigned char int0, int1, int2, int3;
1547 unsigned int iir = serial_port_in(port, UART_IIR);
1548 int ret;
1549
1550 ret = serial8250_handle_irq(port, iir);
1551
30fa96a3
MS		 1552 if ((port->type == PORT_XR17V35X) ||
1553 (port->type == PORT_XR17D15X)) {
dc96efb7
MS		 1554 int0 = serial_port_in(port, 0x80);
1555 int1 = serial_port_in(port, 0x81);
1556 int2 = serial_port_in(port, 0x82);
1557 int3 = serial_port_in(port, 0x83);
1558 }
1559
1560 return ret;
1561}
1562
1da177e4
LT		 1563/*
1564 * This is the serial driver's interrupt routine.
1565 *
1566 * Arjan thinks the old way was overly complex, so it got simplified.
1567 * Alan disagrees, saying that need the complexity to handle the weird
1568 * nature of ISA shared interrupts. (This is a special exception.)
1569 *
1570 * In order to handle ISA shared interrupts properly, we need to check
1571 * that all ports have been serviced, and therefore the ISA interrupt
1572 * line has been de-asserted.
1573 *
1574 * This means we need to loop through all ports. checking that they
1575 * don't have an interrupt pending.
1576 */
7d12e780 1577static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1578{
1579 struct irq_info *i = dev_id;
1580 struct list_head *l, *end = NULL;
1581 int pass_counter = 0, handled = 0;
1582
1583 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1584
1585 spin_lock(&i->lock);
1586
1587 l = i->head;
1588 do {
1589 struct uart_8250_port *up;
583d28e9 1590 struct uart_port *port;
1da177e4
LT		 1591
1592 up = list_entry(l, struct uart_8250_port, list);
583d28e9 1593 port = &up->port;
1da177e4 1594
49b532f9 1595 if (port->handle_irq(port)) {
1da177e4 1596 handled = 1;
1da177e4
LT		 1597 end = NULL;
1598 } else if (end == NULL)
1599 end = l;
1600
1601 l = l->next;
1602
1603 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1604 /* If we hit this, we're dead. */
cd3ecad1
DD		 1605 printk_ratelimited(KERN_ERR
1606 "serial8250: too much work for irq%d\n", irq);
1da177e4
LT		 1607 break;
1608 }
1609 } while (l != end);
1610
1611 spin_unlock(&i->lock);
1612
1613 DEBUG_INTR("end.\n");
1614
1615 return IRQ_RETVAL(handled);
1616}
1617
1618/*
1619 * To support ISA shared interrupts, we need to have one interrupt
1620 * handler that ensures that the IRQ line has been deasserted
1621 * before returning. Failing to do this will result in the IRQ
1622 * line being stuck active, and, since ISA irqs are edge triggered,
1623 * no more IRQs will be seen.
1624 */
1625static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1626{
1627 spin_lock_irq(&i->lock);
1628
1629 if (!list_empty(i->head)) {
1630 if (i->head == &up->list)
1631 i->head = i->head->next;
1632 list_del(&up->list);
1633 } else {
1634 BUG_ON(i->head != &up->list);
1635 i->head = NULL;
1636 }
1da177e4 1637 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1638 /* List empty so throw away the hash node */
1639 if (i->head == NULL) {
1640 hlist_del(&i->node);
1641 kfree(i);
1642 }
1da177e4
LT		 1643}
1644
1645static int serial_link_irq_chain(struct uart_8250_port *up)
1646{
25db8ad5
AC		 1647 struct hlist_head *h;
1648 struct hlist_node *n;
1649 struct irq_info *i;
40663cc7 1650 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1651
25db8ad5
AC		 1652 mutex_lock(&hash_mutex);
1653
1654 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1655
1656 hlist_for_each(n, h) {
1657 i = hlist_entry(n, struct irq_info, node);
1658 if (i->irq == up->port.irq)
1659 break;
1660 }
1661
1662 if (n == NULL) {
1663 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1664 if (i == NULL) {
1665 mutex_unlock(&hash_mutex);
1666 return -ENOMEM;
1667 }
1668 spin_lock_init(&i->lock);
1669 i->irq = up->port.irq;
1670 hlist_add_head(&i->node, h);
1671 }
1672 mutex_unlock(&hash_mutex);
1673
1da177e4
LT		 1674 spin_lock_irq(&i->lock);
1675
1676 if (i->head) {
1677 list_add(&up->list, i->head);
1678 spin_unlock_irq(&i->lock);
1679
1680 ret = 0;
1681 } else {
1682 INIT_LIST_HEAD(&up->list);
1683 i->head = &up->list;
1684 spin_unlock_irq(&i->lock);
1c2f0493 1685 irq_flags |= up->port.irqflags;
1da177e4
LT		 1686 ret = request_irq(up->port.irq, serial8250_interrupt,
1687 irq_flags, "serial", i);
1688 if (ret < 0)
1689 serial_do_unlink(i, up);
1690 }
1691
1692 return ret;
1693}
1694
1695static void serial_unlink_irq_chain(struct uart_8250_port *up)
1696{
bd2fe272
PG		 1697 /*
1698 * yes, some broken gcc emit "warning: 'i' may be used uninitialized"
1699 * but no, we are not going to take a patch that assigns NULL below.
1700 */
25db8ad5
AC		 1701 struct irq_info *i;
1702 struct hlist_node *n;
1703 struct hlist_head *h;
1da177e4 1704
25db8ad5
AC		 1705 mutex_lock(&hash_mutex);
1706
1707 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1708
1709 hlist_for_each(n, h) {
1710 i = hlist_entry(n, struct irq_info, node);
1711 if (i->irq == up->port.irq)
1712 break;
1713 }
1714
1715 BUG_ON(n == NULL);
1da177e4
LT		 1716 BUG_ON(i->head == NULL);
1717
1718 if (list_empty(i->head))
1719 free_irq(up->port.irq, i);
1720
1721 serial_do_unlink(i, up);
25db8ad5 1722 mutex_unlock(&hash_mutex);
1da177e4
LT		 1723}
1724
1725/*
1726 * This function is used to handle ports that do not have an
1727 * interrupt. This doesn't work very well for 16450's, but gives
1728 * barely passable results for a 16550A. (Although at the expense
1729 * of much CPU overhead).
1730 */
1731static void serial8250_timeout(unsigned long data)
1732{
1733 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4 1734
a0431476 1735 up->port.handle_irq(&up->port);
54381067 1736 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
40b36daa
AW		 1737}
1738
1739static void serial8250_backup_timeout(unsigned long data)
1740{
1741 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1742 unsigned int iir, ier = 0, lsr;
1743 unsigned long flags;
40b36daa 1744
dbb3b1ca
AC		 1745 spin_lock_irqsave(&up->port.lock, flags);
1746
40b36daa
AW		 1747 /*
1748 * Must disable interrupts or else we risk racing with the interrupt
1749 * based handler.
1750 */
d4e33fac 1751 if (up->port.irq) {
40b36daa
AW		 1752 ier = serial_in(up, UART_IER);
1753 serial_out(up, UART_IER, 0);
1754 }
1da177e4 1755
40b36daa
AW		 1756 iir = serial_in(up, UART_IIR);
1757
1758 /*
1759 * This should be a safe test for anyone who doesn't trust the
1760 * IIR bits on their UART, but it's specifically designed for
1761 * the "Diva" UART used on the management processor on many HP
1762 * ia64 and parisc boxes.
1763 */
ad4c2aa6
CM		 1764 lsr = serial_in(up, UART_LSR);
1765 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
40b36daa 1766 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1767 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1768 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1769 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1770 iir |= UART_IIR_THRI;
1771 }
1772
1773 if (!(iir & UART_IIR_NO_INT))
3986fb2b 1774 serial8250_tx_chars(up);
40b36daa 1775
d4e33fac 1776 if (up->port.irq)
40b36daa
AW		 1777 serial_out(up, UART_IER, ier);
1778
dbb3b1ca
AC		 1779 spin_unlock_irqrestore(&up->port.lock, flags);
1780
40b36daa 1781 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0 1782 mod_timer(&up->timer,
54381067 1783 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1da177e4
LT		 1784}
1785
1786static unsigned int serial8250_tx_empty(struct uart_port *port)
1787{
49d5741b
JI		 1788 struct uart_8250_port *up =
1789 container_of(port, struct uart_8250_port, port);
1da177e4 1790 unsigned long flags;
ad4c2aa6 1791 unsigned int lsr;
1da177e4 1792
dfe42443 1793 spin_lock_irqsave(&port->lock, flags);
4fd996a1 1794 lsr = serial_port_in(port, UART_LSR);
ad4c2aa6 1795 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
dfe42443 1796 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 1797
bca47613 1798 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1799}
1800
1801static unsigned int serial8250_get_mctrl(struct uart_port *port)
1802{
49d5741b
JI		 1803 struct uart_8250_port *up =
1804 container_of(port, struct uart_8250_port, port);
2af7cd68 1805 unsigned int status;
1da177e4
LT		 1806 unsigned int ret;
1807
3986fb2b 1808 status = serial8250_modem_status(up);
1da177e4
LT		 1809
1810 ret = 0;
1811 if (status & UART_MSR_DCD)
1812 ret |= TIOCM_CAR;
1813 if (status & UART_MSR_RI)
1814 ret |= TIOCM_RNG;
1815 if (status & UART_MSR_DSR)
1816 ret |= TIOCM_DSR;
1817 if (status & UART_MSR_CTS)
1818 ret |= TIOCM_CTS;
1819 return ret;
1820}
1821
1822static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1823{
49d5741b
JI		 1824 struct uart_8250_port *up =
1825 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1826 unsigned char mcr = 0;
1827
1828 if (mctrl & TIOCM_RTS)
1829 mcr |= UART_MCR_RTS;
1830 if (mctrl & TIOCM_DTR)
1831 mcr |= UART_MCR_DTR;
1832 if (mctrl & TIOCM_OUT1)
1833 mcr |= UART_MCR_OUT1;
1834 if (mctrl & TIOCM_OUT2)
1835 mcr |= UART_MCR_OUT2;
1836 if (mctrl & TIOCM_LOOP)
1837 mcr |= UART_MCR_LOOP;
1838
1839 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1840
4fd996a1 1841 serial_port_out(port, UART_MCR, mcr);
1da177e4
LT		 1842}
1843
1844static void serial8250_break_ctl(struct uart_port *port, int break_state)
1845{
49d5741b
JI		 1846 struct uart_8250_port *up =
1847 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1848 unsigned long flags;
1849
dfe42443 1850 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 1851 if (break_state == -1)
1852 up->lcr |= UART_LCR_SBC;
1853 else
1854 up->lcr &= ~UART_LCR_SBC;
4fd996a1 1855 serial_port_out(port, UART_LCR, up->lcr);
dfe42443 1856 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1857}
1858
40b36daa
AW		 1859/*
1860 * Wait for transmitter & holding register to empty
1861 */
b5d674ab 1862static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1863{
1864 unsigned int status, tmout = 10000;
1865
1866 /* Wait up to 10ms for the character(s) to be sent. */
97d303b7 1867 for (;;) {
40b36daa
AW		 1868 status = serial_in(up, UART_LSR);
1869
ad4c2aa6 1870 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa 1871
97d303b7
DD		 1872 if ((status & bits) == bits)
1873 break;
40b36daa
AW		 1874 if (--tmout == 0)
1875 break;
1876 udelay(1);
97d303b7 1877 }
40b36daa
AW		 1878
1879 /* Wait up to 1s for flow control if necessary */
1880 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1881 unsigned int tmout;
1882 for (tmout = 1000000; tmout; tmout--) {
1883 unsigned int msr = serial_in(up, UART_MSR);
1884 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1885 if (msr & UART_MSR_CTS)
1886 break;
40b36daa
AW		 1887 udelay(1);
1888 touch_nmi_watchdog();
1889 }
1890 }
1891}
1892
f2d937f3
JW		 1893#ifdef CONFIG_CONSOLE_POLL
1894/*
1895 * Console polling routines for writing and reading from the uart while
1896 * in an interrupt or debug context.
1897 */
1898
1899static int serial8250_get_poll_char(struct uart_port *port)
1900{
4fd996a1 1901 unsigned char lsr = serial_port_in(port, UART_LSR);
f2d937f3 1902
f5316b4a
JW		 1903 if (!(lsr & UART_LSR_DR))
1904 return NO_POLL_CHAR;
f2d937f3 1905
4fd996a1 1906 return serial_port_in(port, UART_RX);
f2d937f3
JW		 1907}
1908
1909
1910static void serial8250_put_poll_char(struct uart_port *port,
1911 unsigned char c)
1912{
1913 unsigned int ier;
49d5741b
JI		 1914 struct uart_8250_port *up =
1915 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1916
1917 /*
1918 * First save the IER then disable the interrupts
1919 */
4fd996a1 1920 ier = serial_port_in(port, UART_IER);
f2d937f3 1921 if (up->capabilities & UART_CAP_UUE)
4fd996a1 1922 serial_port_out(port, UART_IER, UART_IER_UUE);
f2d937f3 1923 else
4fd996a1 1924 serial_port_out(port, UART_IER, 0);
f2d937f3
JW		 1925
1926 wait_for_xmitr(up, BOTH_EMPTY);
1927 /*
1928 * Send the character out.
f2d937f3 1929 */
4fd996a1 1930 serial_port_out(port, UART_TX, c);
f2d937f3
JW		 1931
1932 /*
1933 * Finally, wait for transmitter to become empty
1934 * and restore the IER
1935 */
1936 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 1937 serial_port_out(port, UART_IER, ier);
f2d937f3
JW		 1938}
1939
1940#endif /* CONFIG_CONSOLE_POLL */
1941
1da177e4
LT		 1942static int serial8250_startup(struct uart_port *port)
1943{
49d5741b
JI		 1944 struct uart_8250_port *up =
1945 container_of(port, struct uart_8250_port, port);
1da177e4 1946 unsigned long flags;
55d3b282 1947 unsigned char lsr, iir;
1da177e4
LT		 1948 int retval;
1949
65ecc9c0
SY		 1950 if (port->type == PORT_8250_CIR)
1951 return -ENODEV;
1952
9660497c
HK		 1953 if (!port->fifosize)
1954 port->fifosize = uart_config[port->type].fifo_size;
1955 if (!up->tx_loadsz)
1956 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1957 if (!up->capabilities)
1958 up->capabilities = uart_config[port->type].flags;
1da177e4
LT		 1959 up->mcr = 0;
1960
dfe42443 1961 if (port->iotype != up->cur_iotype)
b8e7e40a
AC		 1962 set_io_from_upio(port);
1963
dfe42443 1964 if (port->type == PORT_16C950) {
1da177e4
LT		 1965 /* Wake up and initialize UART */
1966 up->acr = 0;
4fd996a1
PG		 1967 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1968 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1969 serial_port_out(port, UART_IER, 0);
1970 serial_port_out(port, UART_LCR, 0);
1da177e4 1971 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
4fd996a1
PG		 1972 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1973 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1974 serial_port_out(port, UART_LCR, 0);
1da177e4
LT		 1975 }
1976
1977#ifdef CONFIG_SERIAL_8250_RSA
1978 /*
1979 * If this is an RSA port, see if we can kick it up to the
1980 * higher speed clock.
1981 */
1982 enable_rsa(up);
1983#endif
1984
1985 /*
1986 * Clear the FIFO buffers and disable them.
7f927fcc 1987 * (they will be reenabled in set_termios())
1da177e4
LT		 1988 */
1989 serial8250_clear_fifos(up);
1990
1991 /*
1992 * Clear the interrupt registers.
1993 */
4fd996a1
PG		 1994 serial_port_in(port, UART_LSR);
1995 serial_port_in(port, UART_RX);
1996 serial_port_in(port, UART_IIR);
1997 serial_port_in(port, UART_MSR);
1da177e4
LT		 1998
1999 /*
2000 * At this point, there's no way the LSR could still be 0xff;
2001 * if it is, then bail out, because there's likely no UART
2002 * here.
2003 */
dfe42443 2004 if (!(port->flags & UPF_BUGGY_UART) &&
4fd996a1 2005 (serial_port_in(port, UART_LSR) == 0xff)) {
7808a4c4 2006 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
dfe42443 2007 serial_index(port));
1da177e4
LT		 2008 return -ENODEV;
2009 }
2010
2011 /*
2012 * For a XR16C850, we need to set the trigger levels
2013 */
dfe42443 2014 if (port->type == PORT_16850) {
1da177e4
LT		 2015 unsigned char fctr;
2016
0acf519f 2017 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4 2018
0acf519f 2019 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
4fd996a1
PG		 2020 serial_port_out(port, UART_FCTR,
2021 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2022 serial_port_out(port, UART_TRG, UART_TRG_96);
2023 serial_port_out(port, UART_FCTR,
2024 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2025 serial_port_out(port, UART_TRG, UART_TRG_96);
1da177e4 2026
4fd996a1 2027 serial_port_out(port, UART_LCR, 0);
1da177e4
LT		 2028 }
2029
dfe42443 2030 if (port->irq) {
01c194d9 2031 unsigned char iir1;
40b36daa
AW		 2032 /*
2033 * Test for UARTs that do not reassert THRE when the
2034 * transmitter is idle and the interrupt has already
2035 * been cleared. Real 16550s should always reassert
2036 * this interrupt whenever the transmitter is idle and
2037 * the interrupt is enabled. Delays are necessary to
2038 * allow register changes to become visible.
2039 */
dfe42443 2040 spin_lock_irqsave(&port->lock, flags);
1c2f0493 2041 if (up->port.irqflags & IRQF_SHARED)
dfe42443 2042 disable_irq_nosync(port->irq);
40b36daa
AW		 2043
2044 wait_for_xmitr(up, UART_LSR_THRE);
55e4016d 2045 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
40b36daa 2046 udelay(1); /* allow THRE to set */
4fd996a1
PG		 2047 iir1 = serial_port_in(port, UART_IIR);
2048 serial_port_out(port, UART_IER, 0);
55e4016d 2049 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
40b36daa 2050 udelay(1); /* allow a working UART time to re-assert THRE */
4fd996a1
PG		 2051 iir = serial_port_in(port, UART_IIR);
2052 serial_port_out(port, UART_IER, 0);
40b36daa 2053
dfe42443
PG		 2054 if (port->irqflags & IRQF_SHARED)
2055 enable_irq(port->irq);
2056 spin_unlock_irqrestore(&port->lock, flags);
40b36daa
AW		 2057
2058 /*
bc02d15a
DW		 2059 * If the interrupt is not reasserted, or we otherwise
2060 * don't trust the iir, setup a timer to kick the UART
2061 * on a regular basis.
40b36daa 2062 */
bc02d15a
DW		 2063 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2064 up->port.flags & UPF_BUG_THRE) {
363f66fe 2065 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2066 pr_debug("ttyS%d - using backup timer\n",
2067 serial_index(port));
40b36daa
AW		 2068 }
2069 }
2070
363f66fe
WN		 2071 /*
2072 * The above check will only give an accurate result the first time
2073 * the port is opened so this value needs to be preserved.
2074 */
2075 if (up->bugs & UART_BUG_THRE) {
2076 up->timer.function = serial8250_backup_timeout;
2077 up->timer.data = (unsigned long)up;
2078 mod_timer(&up->timer, jiffies +
54381067 2079 uart_poll_timeout(port) + HZ / 5);
363f66fe
WN		 2080 }
2081
1da177e4
LT		 2082 /*
2083 * If the "interrupt" for this port doesn't correspond with any
2084 * hardware interrupt, we use a timer-based system. The original
2085 * driver used to do this with IRQ0.
2086 */
dfe42443 2087 if (!port->irq) {
1da177e4 2088 up->timer.data = (unsigned long)up;
54381067 2089 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
1da177e4
LT		 2090 } else {
2091 retval = serial_link_irq_chain(up);
2092 if (retval)
2093 return retval;
2094 }
2095
2096 /*
2097 * Now, initialize the UART
2098 */
4fd996a1 2099 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
1da177e4 2100
dfe42443 2101 spin_lock_irqsave(&port->lock, flags);
1da177e4 2102 if (up->port.flags & UPF_FOURPORT) {
d4e33fac 2103 if (!up->port.irq)
1da177e4
LT		 2104 up->port.mctrl |= TIOCM_OUT1;
2105 } else
2106 /*
2107 * Most PC uarts need OUT2 raised to enable interrupts.
2108 */
dfe42443 2109 if (port->irq)
1da177e4
LT		 2110 up->port.mctrl |= TIOCM_OUT2;
2111
dfe42443 2112 serial8250_set_mctrl(port, port->mctrl);
55d3b282 2113
b6adea33
MCC		 2114 /* Serial over Lan (SoL) hack:
2115 Intel 8257x Gigabit ethernet chips have a
2116 16550 emulation, to be used for Serial Over Lan.
2117 Those chips take a longer time than a normal
2118 serial device to signalize that a transmission
2119 data was queued. Due to that, the above test generally
2120 fails. One solution would be to delay the reading of
2121 iir. However, this is not reliable, since the timeout
2122 is variable. So, let's just don't test if we receive
2123 TX irq. This way, we'll never enable UART_BUG_TXEN.
2124 */
d41a4b51 2125 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2126 goto dont_test_tx_en;
2127
55d3b282
RK		 2128 /*
2129 * Do a quick test to see if we receive an
2130 * interrupt when we enable the TX irq.
2131 */
4fd996a1
PG		 2132 serial_port_out(port, UART_IER, UART_IER_THRI);
2133 lsr = serial_port_in(port, UART_LSR);
2134 iir = serial_port_in(port, UART_IIR);
2135 serial_port_out(port, UART_IER, 0);
55d3b282
RK		 2136
2137 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2138 if (!(up->bugs & UART_BUG_TXEN)) {
2139 up->bugs |= UART_BUG_TXEN;
55d3b282 2140 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2141 serial_index(port));
55d3b282
RK		 2142 }
2143 } else {
67f7654e 2144 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2145 }
2146
b6adea33 2147dont_test_tx_en:
dfe42443 2148 spin_unlock_irqrestore(&port->lock, flags);
1da177e4 2149
ad4c2aa6
CM		 2150 /*
2151 * Clear the interrupt registers again for luck, and clear the
2152 * saved flags to avoid getting false values from polling
2153 * routines or the previous session.
2154 */
4fd996a1
PG		 2155 serial_port_in(port, UART_LSR);
2156 serial_port_in(port, UART_RX);
2157 serial_port_in(port, UART_IIR);
2158 serial_port_in(port, UART_MSR);
ad4c2aa6
CM		 2159 up->lsr_saved_flags = 0;
2160 up->msr_saved_flags = 0;
2161
9ee4b83e
HK		 2162 /*
2163 * Request DMA channels for both RX and TX.
2164 */
2165 if (up->dma) {
2166 retval = serial8250_request_dma(up);
2167 if (retval) {
2168 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2169 serial_index(port));
2170 up->dma = NULL;
2171 }
2172 }
2173
1da177e4
LT		 2174 /*
2175 * Finally, enable interrupts. Note: Modem status interrupts
2176 * are set via set_termios(), which will be occurring imminently
2177 * anyway, so we don't enable them here.
2178 */
2179 up->ier = UART_IER_RLSI | UART_IER_RDI;
4fd996a1 2180 serial_port_out(port, UART_IER, up->ier);
1da177e4 2181
dfe42443 2182 if (port->flags & UPF_FOURPORT) {
1da177e4
LT		 2183 unsigned int icp;
2184 /*
2185 * Enable interrupts on the AST Fourport board
2186 */
dfe42443 2187 icp = (port->iobase & 0xfe0) | 0x01f;
1da177e4 2188 outb_p(0x80, icp);
0d263a26 2189 inb_p(icp);
1da177e4
LT		 2190 }
2191
1da177e4
LT		 2192 return 0;
2193}
2194
2195static void serial8250_shutdown(struct uart_port *port)
2196{
49d5741b
JI		 2197 struct uart_8250_port *up =
2198 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2199 unsigned long flags;
2200
2201 /*
2202 * Disable interrupts from this port
2203 */
2204 up->ier = 0;
4fd996a1 2205 serial_port_out(port, UART_IER, 0);
1da177e4 2206
9ee4b83e
HK		 2207 if (up->dma)
2208 serial8250_release_dma(up);
2209
dfe42443
PG		 2210 spin_lock_irqsave(&port->lock, flags);
2211 if (port->flags & UPF_FOURPORT) {
1da177e4 2212 /* reset interrupts on the AST Fourport board */
dfe42443
PG		 2213 inb((port->iobase & 0xfe0) | 0x1f);
2214 port->mctrl |= TIOCM_OUT1;
1da177e4 2215 } else
dfe42443 2216 port->mctrl &= ~TIOCM_OUT2;
1da177e4 2217
dfe42443
PG		 2218 serial8250_set_mctrl(port, port->mctrl);
2219 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 2220
2221 /*
2222 * Disable break condition and FIFOs
2223 */
4fd996a1
PG		 2224 serial_port_out(port, UART_LCR,
2225 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
1da177e4
LT		 2226 serial8250_clear_fifos(up);
2227
2228#ifdef CONFIG_SERIAL_8250_RSA
2229 /*
2230 * Reset the RSA board back to 115kbps compat mode.
2231 */
2232 disable_rsa(up);
2233#endif
2234
2235 /*
2236 * Read data port to reset things, and then unlink from
2237 * the IRQ chain.
2238 */
4fd996a1 2239 serial_port_in(port, UART_RX);
1da177e4 2240
40b36daa
AW		 2241 del_timer_sync(&up->timer);
2242 up->timer.function = serial8250_timeout;
dfe42443 2243 if (port->irq)
1da177e4
LT		 2244 serial_unlink_irq_chain(up);
2245}
2246
2247static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2248{
2249 unsigned int quot;
2250
2251 /*
2252 * Handle magic divisors for baud rates above baud_base on
2253 * SMSC SuperIO chips.
2254 */
2255 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2256 baud == (port->uartclk/4))
2257 quot = 0x8001;
2258 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2259 baud == (port->uartclk/8))
2260 quot = 0x8002;
2261 else
2262 quot = uart_get_divisor(port, baud);
2263
2264 return quot;
2265}
2266
235dae5d
PL		 2267void
2268serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2269 struct ktermios *old)
1da177e4 2270{
49d5741b
JI		 2271 struct uart_8250_port *up =
2272 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2273 unsigned char cval, fcr = 0;
2274 unsigned long flags;
2275 unsigned int baud, quot;
eb26dfe8 2276 int fifo_bug = 0;
1da177e4
LT		 2277
2278 switch (termios->c_cflag & CSIZE) {
2279 case CS5:
0a8b80c5 2280 cval = UART_LCR_WLEN5;
1da177e4
LT		 2281 break;
2282 case CS6:
0a8b80c5 2283 cval = UART_LCR_WLEN6;
1da177e4
LT		 2284 break;
2285 case CS7:
0a8b80c5 2286 cval = UART_LCR_WLEN7;
1da177e4
LT		 2287 break;
2288 default:
2289 case CS8:
0a8b80c5 2290 cval = UART_LCR_WLEN8;
1da177e4
LT		 2291 break;
2292 }
2293
2294 if (termios->c_cflag & CSTOPB)
0a8b80c5 2295 cval |= UART_LCR_STOP;
eb26dfe8 2296 if (termios->c_cflag & PARENB) {
1da177e4 2297 cval |= UART_LCR_PARITY;
eb26dfe8
AC		 2298 if (up->bugs & UART_BUG_PARITY)
2299 fifo_bug = 1;
2300 }
1da177e4
LT		 2301 if (!(termios->c_cflag & PARODD))
2302 cval |= UART_LCR_EPAR;
2303#ifdef CMSPAR
2304 if (termios->c_cflag & CMSPAR)
2305 cval |= UART_LCR_SPAR;
2306#endif
2307
2308 /*
2309 * Ask the core to calculate the divisor for us.
2310 */
24d481ec
AV		 2311 baud = uart_get_baud_rate(port, termios, old,
2312 port->uartclk / 16 / 0xffff,
2313 port->uartclk / 16);
1da177e4
LT		 2314 quot = serial8250_get_divisor(port, baud);
2315
2316 /*
4ba5e35d 2317 * Oxford Semi 952 rev B workaround
1da177e4 2318 */
4ba5e35d 2319 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2320 quot++;
1da177e4 2321
dfe42443 2322 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
f9a9111b 2323 fcr = uart_config[port->type].fcr;
2797f6fb 2324 if ((baud < 2400 && !up->dma) || fifo_bug) {
f9a9111b
CM		 2325 fcr &= ~UART_FCR_TRIGGER_MASK;
2326 fcr |= UART_FCR_TRIGGER_1;
2327 }
1da177e4
LT		 2328 }
2329
2330 /*
2331 * MCR-based auto flow control. When AFE is enabled, RTS will be
2332 * deasserted when the receive FIFO contains more characters than
2333 * the trigger, or the MCR RTS bit is cleared. In the case where
2334 * the remote UART is not using CTS auto flow control, we must
2335 * have sufficient FIFO entries for the latency of the remote
2336 * UART to respond. IOW, at least 32 bytes of FIFO.
2337 */
dfe42443 2338 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
1da177e4
LT		 2339 up->mcr &= ~UART_MCR_AFE;
2340 if (termios->c_cflag & CRTSCTS)
2341 up->mcr |= UART_MCR_AFE;
2342 }
2343
2344 /*
2345 * Ok, we're now changing the port state. Do it with
2346 * interrupts disabled.
2347 */
dfe42443 2348 spin_lock_irqsave(&port->lock, flags);
1da177e4
LT		 2349
2350 /*
2351 * Update the per-port timeout.
2352 */
2353 uart_update_timeout(port, termios->c_cflag, baud);
2354
dfe42443 2355 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1da177e4 2356 if (termios->c_iflag & INPCK)
dfe42443 2357 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1da177e4 2358 if (termios->c_iflag & (BRKINT | PARMRK))
dfe42443 2359 port->read_status_mask |= UART_LSR_BI;
1da177e4
LT		 2360
2361 /*
2362 * Characteres to ignore
2363 */
dfe42443 2364 port->ignore_status_mask = 0;
1da177e4 2365 if (termios->c_iflag & IGNPAR)
dfe42443 2366 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1da177e4 2367 if (termios->c_iflag & IGNBRK) {
dfe42443 2368 port->ignore_status_mask |= UART_LSR_BI;
1da177e4
LT		 2369 /*
2370 * If we're ignoring parity and break indicators,
2371 * ignore overruns too (for real raw support).
2372 */
2373 if (termios->c_iflag & IGNPAR)
dfe42443 2374 port->ignore_status_mask |= UART_LSR_OE;
1da177e4
LT		 2375 }
2376
2377 /*
2378 * ignore all characters if CREAD is not set
2379 */
2380 if ((termios->c_cflag & CREAD) == 0)
dfe42443 2381 port->ignore_status_mask |= UART_LSR_DR;
1da177e4
LT		 2382
2383 /*
2384 * CTS flow control flag and modem status interrupts
2385 */
f8b372a1 2386 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2387 if (!(up->bugs & UART_BUG_NOMSR) &&
2388 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2389 up->ier |= UART_IER_MSI;
2390 if (up->capabilities & UART_CAP_UUE)
4539c24f
SW		 2391 up->ier |= UART_IER_UUE;
2392 if (up->capabilities & UART_CAP_RTOIE)
2393 up->ier |= UART_IER_RTOIE;
1da177e4 2394
4fd996a1 2395 serial_port_out(port, UART_IER, up->ier);
1da177e4
LT		 2396
2397 if (up->capabilities & UART_CAP_EFR) {
2398 unsigned char efr = 0;
2399 /*
2400 * TI16C752/Startech hardware flow control. FIXME:
2401 * - TI16C752 requires control thresholds to be set.
2402 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2403 */
2404 if (termios->c_cflag & CRTSCTS)
2405 efr |= UART_EFR_CTS;
2406
4fd996a1 2407 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
dfe42443 2408 if (port->flags & UPF_EXAR_EFR)
4fd996a1 2409 serial_port_out(port, UART_XR_EFR, efr);
06315348 2410 else
4fd996a1 2411 serial_port_out(port, UART_EFR, efr);
1da177e4
LT		 2412 }
2413
255341c6 2414 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
54ec52b6 2415 if (is_omap1510_8250(up)) {
255341c6
JM		 2416 if (baud == 115200) {
2417 quot = 1;
4fd996a1 2418 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
255341c6 2419 } else
4fd996a1 2420 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
255341c6 2421 }
255341c6 2422
4fd996a1
PG		 2423 /*
2424 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2425 * otherwise just set DLAB
2426 */
2427 if (up->capabilities & UART_NATSEMI)
2428 serial_port_out(port, UART_LCR, 0xe0);
2429 else
2430 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
1da177e4 2431
b32b19b8 2432 serial_dl_write(up, quot);
1da177e4 2433
45a7bd63
JS		 2434 /*
2435 * XR17V35x UARTs have an extra fractional divisor register (DLD)
2436 *
2437 * We need to recalculate all of the registers, because DLM and DLL
2438 * are already rounded to a whole integer.
2439 *
2440 * When recalculating we use a 32x clock instead of a 16x clock to
2441 * allow 1-bit for rounding in the fractional part.
2442 */
2443 if (up->port.type == PORT_XR17V35X) {
2444 unsigned int baud_x32 = (port->uartclk * 2) / baud;
2445 u16 quot = baud_x32 / 32;
2446 u8 quot_frac = DIV_ROUND_CLOSEST(baud_x32 % 32, 2);
2447
2448 serial_dl_write(up, quot);
2449 serial_port_out(port, 0x2, quot_frac & 0xf);
2450 }
2451
1da177e4
LT		 2452 /*
2453 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2454 * is written without DLAB set, this mode will be disabled.
2455 */
dfe42443 2456 if (port->type == PORT_16750)
4fd996a1 2457 serial_port_out(port, UART_FCR, fcr);
1da177e4 2458
4fd996a1 2459 serial_port_out(port, UART_LCR, cval); /* reset DLAB */
1da177e4 2460 up->lcr = cval; /* Save LCR */
dfe42443 2461 if (port->type != PORT_16750) {
4fd996a1
PG		 2462 /* emulated UARTs (Lucent Venus 167x) need two steps */
2463 if (fcr & UART_FCR_ENABLE_FIFO)
2464 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2465 serial_port_out(port, UART_FCR, fcr); /* set fcr */
1da177e4 2466 }
dfe42443
PG		 2467 serial8250_set_mctrl(port, port->mctrl);
2468 spin_unlock_irqrestore(&port->lock, flags);
e991a2bd
AC		 2469 /* Don't rewrite B0 */
2470 if (tty_termios_baud_rate(termios))
2471 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4 2472}
235dae5d
PL		 2473EXPORT_SYMBOL(serial8250_do_set_termios);
2474
2475static void
2476serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2477 struct ktermios *old)
2478{
2479 if (port->set_termios)
2480 port->set_termios(port, termios, old);
2481 else
2482 serial8250_do_set_termios(port, termios, old);
2483}
1da177e4 2484
dc77f161 2485static void
a0821df6 2486serial8250_set_ldisc(struct uart_port *port, int new)
dc77f161 2487{
a0821df6 2488 if (new == N_PPS) {
dc77f161
RG		 2489 port->flags |= UPF_HARDPPS_CD;
2490 serial8250_enable_ms(port);
2491 } else
2492 port->flags &= ~UPF_HARDPPS_CD;
2493}
2494
c161afe9
ML		 2495
2496void serial8250_do_pm(struct uart_port *port, unsigned int state,
2497 unsigned int oldstate)
1da177e4 2498{
49d5741b
JI		 2499 struct uart_8250_port *p =
2500 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2501
2502 serial8250_set_sleep(p, state != 0);
c161afe9
ML		 2503}
2504EXPORT_SYMBOL(serial8250_do_pm);
1da177e4 2505
c161afe9
ML		 2506static void
2507serial8250_pm(struct uart_port *port, unsigned int state,
2508 unsigned int oldstate)
2509{
2510 if (port->pm)
2511 port->pm(port, state, oldstate);
2512 else
2513 serial8250_do_pm(port, state, oldstate);
1da177e4
LT		 2514}
2515
f2eda27d
RK		 2516static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2517{
2518 if (pt->port.iotype == UPIO_AU)
b2b13cdf 2519 return 0x1000;
54ec52b6 2520 if (is_omap1_8250(pt))
f2eda27d 2521 return 0x16 << pt->port.regshift;
54ec52b6 2522
f2eda27d
RK		 2523 return 8 << pt->port.regshift;
2524}
2525
1da177e4
LT		 2526/*
2527 * Resource handling.
2528 */
2529static int serial8250_request_std_resource(struct uart_8250_port *up)
2530{
f2eda27d 2531 unsigned int size = serial8250_port_size(up);
dfe42443 2532 struct uart_port *port = &up->port;
1da177e4
LT		 2533 int ret = 0;
2534
dfe42443 2535 switch (port->iotype) {
85835f44 2536 case UPIO_AU:
0b30d668
SS		 2537 case UPIO_TSI:
2538 case UPIO_MEM32:
1da177e4 2539 case UPIO_MEM:
dfe42443 2540 if (!port->mapbase)
1da177e4
LT		 2541 break;
2542
dfe42443 2543 if (!request_mem_region(port->mapbase, size, "serial")) {
1da177e4
LT		 2544 ret = -EBUSY;
2545 break;
2546 }
2547
dfe42443
PG		 2548 if (port->flags & UPF_IOREMAP) {
2549 port->membase = ioremap_nocache(port->mapbase, size);
2550 if (!port->membase) {
2551 release_mem_region(port->mapbase, size);
1da177e4
LT		 2552 ret = -ENOMEM;
2553 }
2554 }
2555 break;
2556
2557 case UPIO_HUB6:
2558 case UPIO_PORT:
dfe42443 2559 if (!request_region(port->iobase, size, "serial"))
1da177e4
LT		 2560 ret = -EBUSY;
2561 break;
2562 }
2563 return ret;
2564}
2565
2566static void serial8250_release_std_resource(struct uart_8250_port *up)
2567{
f2eda27d 2568 unsigned int size = serial8250_port_size(up);
dfe42443 2569 struct uart_port *port = &up->port;
1da177e4 2570
dfe42443 2571 switch (port->iotype) {
85835f44 2572 case UPIO_AU:
0b30d668
SS		 2573 case UPIO_TSI:
2574 case UPIO_MEM32:
1da177e4 2575 case UPIO_MEM:
dfe42443 2576 if (!port->mapbase)
1da177e4
LT		 2577 break;
2578
dfe42443
PG		 2579 if (port->flags & UPF_IOREMAP) {
2580 iounmap(port->membase);
2581 port->membase = NULL;
1da177e4
LT		 2582 }
2583
dfe42443 2584 release_mem_region(port->mapbase, size);
1da177e4
LT		 2585 break;
2586
2587 case UPIO_HUB6:
2588 case UPIO_PORT:
dfe42443 2589 release_region(port->iobase, size);
1da177e4
LT		 2590 break;
2591 }
2592}
2593
2594static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2595{
2596 unsigned long start = UART_RSA_BASE << up->port.regshift;
2597 unsigned int size = 8 << up->port.regshift;
dfe42443 2598 struct uart_port *port = &up->port;
0b30d668 2599 int ret = -EINVAL;
1da177e4 2600
dfe42443 2601 switch (port->iotype) {
1da177e4
LT		 2602 case UPIO_HUB6:
2603 case UPIO_PORT:
dfe42443 2604 start += port->iobase;
0b30d668
SS		 2605 if (request_region(start, size, "serial-rsa"))
2606 ret = 0;
2607 else
1da177e4
LT		 2608 ret = -EBUSY;
2609 break;
2610 }
2611
2612 return ret;
2613}
2614
2615static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2616{
2617 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2618 unsigned int size = 8 << up->port.regshift;
dfe42443 2619 struct uart_port *port = &up->port;
1da177e4 2620
dfe42443 2621 switch (port->iotype) {
1da177e4
LT		 2622 case UPIO_HUB6:
2623 case UPIO_PORT:
dfe42443 2624 release_region(port->iobase + offset, size);
1da177e4
LT		 2625 break;
2626 }
2627}
2628
2629static void serial8250_release_port(struct uart_port *port)
2630{
49d5741b
JI		 2631 struct uart_8250_port *up =
2632 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2633
2634 serial8250_release_std_resource(up);
dfe42443 2635 if (port->type == PORT_RSA)
1da177e4
LT		 2636 serial8250_release_rsa_resource(up);
2637}
2638
2639static int serial8250_request_port(struct uart_port *port)
2640{
49d5741b
JI		 2641 struct uart_8250_port *up =
2642 container_of(port, struct uart_8250_port, port);
65ecc9c0
SY		 2643 int ret;
2644
2645 if (port->type == PORT_8250_CIR)
2646 return -ENODEV;
1da177e4
LT		 2647
2648 ret = serial8250_request_std_resource(up);
dfe42443 2649 if (ret == 0 && port->type == PORT_RSA) {
1da177e4
LT		 2650 ret = serial8250_request_rsa_resource(up);
2651 if (ret < 0)
2652 serial8250_release_std_resource(up);
2653 }
2654
2655 return ret;
2656}
2657
2658static void serial8250_config_port(struct uart_port *port, int flags)
2659{
49d5741b
JI		 2660 struct uart_8250_port *up =
2661 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2662 int probeflags = PROBE_ANY;
2663 int ret;
2664
65ecc9c0
SY		 2665 if (port->type == PORT_8250_CIR)
2666 return;
2667
1da177e4
LT		 2668 /*
2669 * Find the region that we can probe for. This in turn
2670 * tells us whether we can probe for the type of port.
2671 */
2672 ret = serial8250_request_std_resource(up);
2673 if (ret < 0)
2674 return;
2675
2676 ret = serial8250_request_rsa_resource(up);
2677 if (ret < 0)
2678 probeflags &= ~PROBE_RSA;
2679
dfe42443 2680 if (port->iotype != up->cur_iotype)
b8e7e40a
AC		 2681 set_io_from_upio(port);
2682
1da177e4
LT		 2683 if (flags & UART_CONFIG_TYPE)
2684 autoconfig(up, probeflags);
b2b13cdf 2685
b2b13cdf 2686 /* if access method is AU, it is a 16550 with a quirk */
dfe42443 2687 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
b2b13cdf 2688 up->bugs |= UART_BUG_NOMSR;
b2b13cdf 2689
3685f19e
SW		 2690 /* HW bugs may trigger IRQ while IIR == NO_INT */
2691 if (port->type == PORT_TEGRA)
2692 up->bugs |= UART_BUG_NOMSR;
2693
dfe42443 2694 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
1da177e4
LT		 2695 autoconfig_irq(up);
2696
dfe42443 2697 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
1da177e4 2698 serial8250_release_rsa_resource(up);
dfe42443 2699 if (port->type == PORT_UNKNOWN)
1da177e4 2700 serial8250_release_std_resource(up);
dc96efb7
MS		 2701
2702 /* Fixme: probably not the best place for this */
30fa96a3
MS		 2703 if ((port->type == PORT_XR17V35X) ||
2704 (port->type == PORT_XR17D15X))
dc96efb7 2705 port->handle_irq = exar_handle_irq;
1da177e4
LT		 2706}
2707
2708static int
2709serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2710{
a62c4133 2711 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2712 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2713 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2714 ser->type == PORT_STARTECH)
2715 return -EINVAL;
2716 return 0;
2717}
2718
2719static const char *
2720serial8250_type(struct uart_port *port)
2721{
2722 int type = port->type;
2723
2724 if (type >= ARRAY_SIZE(uart_config))
2725 type = 0;
2726 return uart_config[type].name;
2727}
2728
2729static struct uart_ops serial8250_pops = {
2730 .tx_empty = serial8250_tx_empty,
2731 .set_mctrl = serial8250_set_mctrl,
2732 .get_mctrl = serial8250_get_mctrl,
2733 .stop_tx = serial8250_stop_tx,
2734 .start_tx = serial8250_start_tx,
2735 .stop_rx = serial8250_stop_rx,
2736 .enable_ms = serial8250_enable_ms,
2737 .break_ctl = serial8250_break_ctl,
2738 .startup = serial8250_startup,
2739 .shutdown = serial8250_shutdown,
2740 .set_termios = serial8250_set_termios,
dc77f161 2741 .set_ldisc = serial8250_set_ldisc,
1da177e4
LT		 2742 .pm = serial8250_pm,
2743 .type = serial8250_type,
2744 .release_port = serial8250_release_port,
2745 .request_port = serial8250_request_port,
2746 .config_port = serial8250_config_port,
2747 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2748#ifdef CONFIG_CONSOLE_POLL
2749 .poll_get_char = serial8250_get_poll_char,
2750 .poll_put_char = serial8250_put_poll_char,
2751#endif
1da177e4
LT		 2752};
2753
2754static struct uart_8250_port serial8250_ports[UART_NR];
2755
af7f3743
AC		 2756static void (*serial8250_isa_config)(int port, struct uart_port *up,
2757 unsigned short *capabilities);
2758
2759void serial8250_set_isa_configurator(
2760 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2761{
2762 serial8250_isa_config = v;
2763}
2764EXPORT_SYMBOL(serial8250_set_isa_configurator);
2765
1da177e4
LT		 2766static void __init serial8250_isa_init_ports(void)
2767{
2768 struct uart_8250_port *up;
2769 static int first = 1;
4c0ebb80 2770 int i, irqflag = 0;
1da177e4
LT		 2771
2772 if (!first)
2773 return;
2774 first = 0;
2775
835d844d
SY		 2776 if (nr_uarts > UART_NR)
2777 nr_uarts = UART_NR;
2778
317a6842 2779 for (i = 0; i < nr_uarts; i++) {
1da177e4 2780 struct uart_8250_port *up = &serial8250_ports[i];
dfe42443 2781 struct uart_port *port = &up->port;
1da177e4 2782
dfe42443
PG		 2783 port->line = i;
2784 spin_lock_init(&port->lock);
1da177e4
LT		 2785
2786 init_timer(&up->timer);
2787 up->timer.function = serial8250_timeout;
835d844d 2788 up->cur_iotype = 0xFF;
1da177e4
LT		 2789
2790 /*
2791 * ALPHA_KLUDGE_MCR needs to be killed.
2792 */
2793 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2794 up->mcr_force = ALPHA_KLUDGE_MCR;
2795
dfe42443 2796 port->ops = &serial8250_pops;
1da177e4
LT		 2797 }
2798
4c0ebb80
AGR		 2799 if (share_irqs)
2800 irqflag = IRQF_SHARED;
2801
44454bcd 2802 for (i = 0, up = serial8250_ports;
a61c2d78 2803 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4 2804 i++, up++) {
dfe42443
PG		 2805 struct uart_port *port = &up->port;
2806
2807 port->iobase = old_serial_port[i].port;
2808 port->irq = irq_canonicalize(old_serial_port[i].irq);
2809 port->irqflags = old_serial_port[i].irqflags;
2810 port->uartclk = old_serial_port[i].baud_base * 16;
2811 port->flags = old_serial_port[i].flags;
2812 port->hub6 = old_serial_port[i].hub6;
2813 port->membase = old_serial_port[i].iomem_base;
2814 port->iotype = old_serial_port[i].io_type;
2815 port->regshift = old_serial_port[i].iomem_reg_shift;
2816 set_io_from_upio(port);
2817 port->irqflags |= irqflag;
af7f3743
AC		 2818 if (serial8250_isa_config != NULL)
2819 serial8250_isa_config(i, &up->port, &up->capabilities);
2820
1da177e4
LT		 2821 }
2822}
2823
b5d228cc
SL		 2824static void
2825serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2826{
2827 up->port.type = type;
9660497c
HK		 2828 if (!up->port.fifosize)
2829 up->port.fifosize = uart_config[type].fifo_size;
2830 if (!up->tx_loadsz)
2831 up->tx_loadsz = uart_config[type].tx_loadsz;
2832 if (!up->capabilities)
2833 up->capabilities = uart_config[type].flags;
b5d228cc
SL		 2834}
2835
1da177e4
LT		 2836static void __init
2837serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2838{
2839 int i;
2840
b8e7e40a
AC		 2841 for (i = 0; i < nr_uarts; i++) {
2842 struct uart_8250_port *up = &serial8250_ports[i];
b8e7e40a 2843
835d844d
SY		 2844 if (up->port.dev)
2845 continue;
1da177e4
LT		 2846
2847 up->port.dev = dev;
b5d228cc
SL		 2848
2849 if (up->port.flags & UPF_FIXED_TYPE)
2850 serial8250_init_fixed_type_port(up, up->port.type);
2851
1da177e4
LT		 2852 uart_add_one_port(drv, &up->port);
2853 }
2854}
2855
2856#ifdef CONFIG_SERIAL_8250_CONSOLE
2857
d358788f
RK		 2858static void serial8250_console_putchar(struct uart_port *port, int ch)
2859{
49d5741b
JI		 2860 struct uart_8250_port *up =
2861 container_of(port, struct uart_8250_port, port);
d358788f
RK		 2862
2863 wait_for_xmitr(up, UART_LSR_THRE);
4fd996a1 2864 serial_port_out(port, UART_TX, ch);
d358788f
RK		 2865}
2866
1da177e4
LT		 2867/*
2868 * Print a string to the serial port trying not to disturb
2869 * any possible real use of the port...
2870 *
2871 * The console_lock must be held when we get here.
2872 */
2873static void
2874serial8250_console_write(struct console *co, const char *s, unsigned int count)
2875{
2876 struct uart_8250_port *up = &serial8250_ports[co->index];
dfe42443 2877 struct uart_port *port = &up->port;
d8a5a8d7 2878 unsigned long flags;
1da177e4 2879 unsigned int ier;
d8a5a8d7 2880 int locked = 1;
1da177e4 2881
78512ece
AM		 2882 touch_nmi_watchdog();
2883
ebade5e8
IM		 2884 if (port->sysrq || oops_in_progress)
2885 locked = spin_trylock_irqsave(&port->lock, flags);
2886 else
2887 spin_lock_irqsave(&port->lock, flags);
d8a5a8d7 2888
1da177e4 2889 /*
dc7bf130 2890 * First save the IER then disable the interrupts
1da177e4 2891 */
4fd996a1 2892 ier = serial_port_in(port, UART_IER);
1da177e4
LT		 2893
2894 if (up->capabilities & UART_CAP_UUE)
4fd996a1 2895 serial_port_out(port, UART_IER, UART_IER_UUE);
1da177e4 2896 else
4fd996a1 2897 serial_port_out(port, UART_IER, 0);
1da177e4 2898
dfe42443 2899 uart_console_write(port, s, count, serial8250_console_putchar);
1da177e4
LT		 2900
2901 /*
2902 * Finally, wait for transmitter to become empty
2903 * and restore the IER
2904 */
f91a3715 2905 wait_for_xmitr(up, BOTH_EMPTY);
4fd996a1 2906 serial_port_out(port, UART_IER, ier);
d8a5a8d7 2907
ad4c2aa6
CM		 2908 /*
2909 * The receive handling will happen properly because the
2910 * receive ready bit will still be set; it is not cleared
2911 * on read. However, modem control will not, we must
2912 * call it if we have saved something in the saved flags
2913 * while processing with interrupts off.
2914 */
2915 if (up->msr_saved_flags)
3986fb2b 2916 serial8250_modem_status(up);
ad4c2aa6 2917
d8a5a8d7 2918 if (locked)
ebade5e8 2919 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 2920}
2921
118c0ace 2922static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2923{
2924 struct uart_port *port;
2925 int baud = 9600;
2926 int bits = 8;
2927 int parity = 'n';
2928 int flow = 'n';
2929
2930 /*
2931 * Check whether an invalid uart number has been specified, and
2932 * if so, search for the first available port that does have
2933 * console support.
2934 */
317a6842 2935 if (co->index >= nr_uarts)
1da177e4
LT		 2936 co->index = 0;
2937 port = &serial8250_ports[co->index].port;
2938 if (!port->iobase && !port->membase)
2939 return -ENODEV;
2940
2941 if (options)
2942 uart_parse_options(options, &baud, &parity, &bits, &flow);
2943
2944 return uart_set_options(port, co, baud, parity, bits, flow);
2945}
2946
b6b1d877 2947static int serial8250_console_early_setup(void)
18a8bd94
YL		 2948{
2949 return serial8250_find_port_for_earlycon();
2950}
2951
1da177e4
LT		 2952static struct console serial8250_console = {
2953 .name = "ttyS",
2954 .write = serial8250_console_write,
2955 .device = uart_console_device,
2956 .setup = serial8250_console_setup,
18a8bd94 2957 .early_setup = serial8250_console_early_setup,
a80c49db 2958 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2959 .index = -1,
2960 .data = &serial8250_reg,
2961};
2962
2963static int __init serial8250_console_init(void)
2964{
2965 serial8250_isa_init_ports();
2966 register_console(&serial8250_console);
2967 return 0;
2968}
2969console_initcall(serial8250_console_init);
2970
18a8bd94 2971int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2972{
2973 int line;
2974 struct uart_port *port;
2975
317a6842 2976 for (line = 0; line < nr_uarts; line++) {
1da177e4 2977 port = &serial8250_ports[line].port;
50aec3b5 2978 if (uart_match_port(p, port))
1da177e4
LT		 2979 return line;
2980 }
2981 return -ENODEV;
2982}
2983
1da177e4
LT		 2984#define SERIAL8250_CONSOLE &serial8250_console
2985#else
2986#define SERIAL8250_CONSOLE NULL
2987#endif
2988
2989static struct uart_driver serial8250_reg = {
2990 .owner = THIS_MODULE,
2991 .driver_name = "serial",
1da177e4
LT		 2992 .dev_name = "ttyS",
2993 .major = TTY_MAJOR,
2994 .minor = 64,
1da177e4
LT		 2995 .cons = SERIAL8250_CONSOLE,
2996};
2997
d856c666
RK		 2998/*
2999 * early_serial_setup - early registration for 8250 ports
3000 *
3001 * Setup an 8250 port structure prior to console initialisation. Use
3002 * after console initialisation will cause undefined behaviour.
3003 */
1da177e4
LT		 3004int __init early_serial_setup(struct uart_port *port)
3005{
b430428a
DD		 3006 struct uart_port *p;
3007
1da177e4
LT		 3008 if (port->line >= ARRAY_SIZE(serial8250_ports))
3009 return -ENODEV;
3010
3011 serial8250_isa_init_ports();
b430428a
DD		 3012 p = &serial8250_ports[port->line].port;
3013 p->iobase = port->iobase;
3014 p->membase = port->membase;
3015 p->irq = port->irq;
1c2f0493 3016 p->irqflags = port->irqflags;
b430428a
DD		 3017 p->uartclk = port->uartclk;
3018 p->fifosize = port->fifosize;
3019 p->regshift = port->regshift;
3020 p->iotype = port->iotype;
3021 p->flags = port->flags;
3022 p->mapbase = port->mapbase;
3023 p->private_data = port->private_data;
125c97d8
HD		 3024 p->type = port->type;
3025 p->line = port->line;
7d6a07d1
DD		 3026
3027 set_io_from_upio(p);
3028 if (port->serial_in)
3029 p->serial_in = port->serial_in;
3030 if (port->serial_out)
3031 p->serial_out = port->serial_out;
583d28e9
JI		 3032 if (port->handle_irq)
3033 p->handle_irq = port->handle_irq;
3034 else
3035 p->handle_irq = serial8250_default_handle_irq;
7d6a07d1 3036
1da177e4
LT		 3037 return 0;
3038}
3039
3040/**
3041 * serial8250_suspend_port - suspend one serial port
3042 * @line: serial line number
1da177e4
LT		 3043 *
3044 * Suspend one serial port.
3045 */
3046void serial8250_suspend_port(int line)
3047{
3048 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3049}
3050
3051/**
3052 * serial8250_resume_port - resume one serial port
3053 * @line: serial line number
1da177e4
LT		 3054 *
3055 * Resume one serial port.
3056 */
3057void serial8250_resume_port(int line)
3058{
b5b82df6 3059 struct uart_8250_port *up = &serial8250_ports[line];
dfe42443 3060 struct uart_port *port = &up->port;
b5b82df6
DW		 3061
3062 if (up->capabilities & UART_NATSEMI) {
b5b82df6 3063 /* Ensure it's still in high speed mode */
4fd996a1 3064 serial_port_out(port, UART_LCR, 0xE0);
b5b82df6 3065
0d0389e5 3066 ns16550a_goto_highspeed(up);
b5b82df6 3067
4fd996a1 3068 serial_port_out(port, UART_LCR, 0);
dfe42443 3069 port->uartclk = 921600*16;
b5b82df6 3070 }
dfe42443 3071 uart_resume_port(&serial8250_reg, port);
1da177e4
LT		 3072}
3073
3074/*
3075 * Register a set of serial devices attached to a platform device. The
3076 * list is terminated with a zero flags entry, which means we expect
3077 * all entries to have at least UPF_BOOT_AUTOCONF set.
3078 */
9671f099 3079static int serial8250_probe(struct platform_device *dev)
1da177e4 3080{
574de559 3081 struct plat_serial8250_port *p = dev_get_platdata(&dev->dev);
2655a2c7 3082 struct uart_8250_port uart;
4c0ebb80 3083 int ret, i, irqflag = 0;
1da177e4 3084
2655a2c7 3085 memset(&uart, 0, sizeof(uart));
1da177e4 3086
4c0ebb80
AGR		 3087 if (share_irqs)
3088 irqflag = IRQF_SHARED;
3089
ec9f47cd 3090 for (i = 0; p && p->flags != 0; p++, i++) {
2655a2c7
AC		 3091 uart.port.iobase = p->iobase;
3092 uart.port.membase = p->membase;
3093 uart.port.irq = p->irq;
3094 uart.port.irqflags = p->irqflags;
3095 uart.port.uartclk = p->uartclk;
3096 uart.port.regshift = p->regshift;
3097 uart.port.iotype = p->iotype;
3098 uart.port.flags = p->flags;
3099 uart.port.mapbase = p->mapbase;
3100 uart.port.hub6 = p->hub6;
3101 uart.port.private_data = p->private_data;
3102 uart.port.type = p->type;
3103 uart.port.serial_in = p->serial_in;
3104 uart.port.serial_out = p->serial_out;
3105 uart.port.handle_irq = p->handle_irq;
3106 uart.port.handle_break = p->handle_break;
3107 uart.port.set_termios = p->set_termios;
3108 uart.port.pm = p->pm;
3109 uart.port.dev = &dev->dev;
3110 uart.port.irqflags |= irqflag;
3111 ret = serial8250_register_8250_port(&uart);
ec9f47cd 3112 if (ret < 0) {
3ae5eaec 3113 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 3114 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3115 p->iobase, (unsigned long long)p->mapbase,
3116 p->irq, ret);
ec9f47cd 3117 }
1da177e4
LT		 3118 }
3119 return 0;
3120}
3121
3122/*
3123 * Remove serial ports registered against a platform device.
3124 */
ae8d8a14 3125static int serial8250_remove(struct platform_device *dev)
1da177e4
LT		 3126{
3127 int i;
3128
317a6842 3129 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 3130 struct uart_8250_port *up = &serial8250_ports[i];
3131
3ae5eaec 3132 if (up->port.dev == &dev->dev)
1da177e4
LT		 3133 serial8250_unregister_port(i);
3134 }
3135 return 0;
3136}
3137
3ae5eaec 3138static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 3139{
3140 int i;
3141
1da177e4
LT		 3142 for (i = 0; i < UART_NR; i++) {
3143 struct uart_8250_port *up = &serial8250_ports[i];
3144
3ae5eaec 3145 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3146 uart_suspend_port(&serial8250_reg, &up->port);
3147 }
3148
3149 return 0;
3150}
3151
3ae5eaec 3152static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3153{
3154 int i;
3155
1da177e4
LT		 3156 for (i = 0; i < UART_NR; i++) {
3157 struct uart_8250_port *up = &serial8250_ports[i];
3158
3ae5eaec 3159 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3160 serial8250_resume_port(i);
1da177e4
LT		 3161 }
3162
3163 return 0;
3164}
3165
3ae5eaec 3166static struct platform_driver serial8250_isa_driver = {
1da177e4 3167 .probe = serial8250_probe,
2d47b716 3168 .remove = serial8250_remove,
1da177e4
LT		 3169 .suspend = serial8250_suspend,
3170 .resume = serial8250_resume,
3ae5eaec
RK		 3171 .driver = {
3172 .name = "serial8250",
7493a314 3173 .owner = THIS_MODULE,
3ae5eaec 3174 },
1da177e4
LT		 3175};
3176
3177/*
3178 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3179 * in the table in include/asm/serial.h
3180 */
3181static struct platform_device *serial8250_isa_devs;
3182
3183/*
2655a2c7 3184 * serial8250_register_8250_port and serial8250_unregister_port allows for
1da177e4
LT		 3185 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3186 * modems and PCI multiport cards.
3187 */
f392ecfa 3188static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3189
3190static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3191{
3192 int i;
3193
3194 /*
3195 * First, find a port entry which matches.
3196 */
317a6842 3197 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3198 if (uart_match_port(&serial8250_ports[i].port, port))
3199 return &serial8250_ports[i];
3200
3201 /*
3202 * We didn't find a matching entry, so look for the first
3203 * free entry. We look for one which hasn't been previously
3204 * used (indicated by zero iobase).
3205 */
317a6842 3206 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3207 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3208 serial8250_ports[i].port.iobase == 0)
3209 return &serial8250_ports[i];
3210
3211 /*
3212 * That also failed. Last resort is to find any entry which
3213 * doesn't have a real port associated with it.
3214 */
317a6842 3215 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3216 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3217 return &serial8250_ports[i];
3218
3219 return NULL;
3220}
3221
3222/**
f73fa05b 3223 * serial8250_register_8250_port - register a serial port
58bcd332 3224 * @up: serial port template
1da177e4
LT		 3225 *
3226 * Configure the serial port specified by the request. If the
3227 * port exists and is in use, it is hung up and unregistered
3228 * first.
3229 *
3230 * The port is then probed and if necessary the IRQ is autodetected
3231 * If this fails an error is returned.
3232 *
3233 * On success the port is ready to use and the line number is returned.
3234 */
f73fa05b 3235int serial8250_register_8250_port(struct uart_8250_port *up)
1da177e4
LT		 3236{
3237 struct uart_8250_port *uart;
3238 int ret = -ENOSPC;
3239
f73fa05b 3240 if (up->port.uartclk == 0)
1da177e4
LT		 3241 return -EINVAL;
3242
f392ecfa 3243 mutex_lock(&serial_mutex);
1da177e4 3244
f73fa05b 3245 uart = serial8250_find_match_or_unused(&up->port);
65ecc9c0 3246 if (uart && uart->port.type != PORT_8250_CIR) {
835d844d
SY		 3247 if (uart->port.dev)
3248 uart_remove_one_port(&serial8250_reg, &uart->port);
1da177e4 3249
f73fa05b
MD		 3250 uart->port.iobase = up->port.iobase;
3251 uart->port.membase = up->port.membase;
3252 uart->port.irq = up->port.irq;
3253 uart->port.irqflags = up->port.irqflags;
3254 uart->port.uartclk = up->port.uartclk;
3255 uart->port.fifosize = up->port.fifosize;
3256 uart->port.regshift = up->port.regshift;
3257 uart->port.iotype = up->port.iotype;
3258 uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF;
a2d33d87 3259 uart->bugs = up->bugs;
f73fa05b
MD		 3260 uart->port.mapbase = up->port.mapbase;
3261 uart->port.private_data = up->port.private_data;
9660497c
HK		 3262 uart->port.fifosize = up->port.fifosize;
3263 uart->tx_loadsz = up->tx_loadsz;
3264 uart->capabilities = up->capabilities;
3265
6a3f45dc
HK		 3266 /* Take tx_loadsz from fifosize if it wasn't set separately */
3267 if (uart->port.fifosize && !uart->tx_loadsz)
3268 uart->tx_loadsz = uart->port.fifosize;
3269
f73fa05b
MD		 3270 if (up->port.dev)
3271 uart->port.dev = up->port.dev;
3272
3273 if (up->port.flags & UPF_FIXED_TYPE)
3274 serial8250_init_fixed_type_port(uart, up->port.type);
8e23fcc8 3275
7d6a07d1
DD		 3276 set_io_from_upio(&uart->port);
3277 /* Possibly override default I/O functions. */
f73fa05b
MD		 3278 if (up->port.serial_in)
3279 uart->port.serial_in = up->port.serial_in;
3280 if (up->port.serial_out)
3281 uart->port.serial_out = up->port.serial_out;
3282 if (up->port.handle_irq)
3283 uart->port.handle_irq = up->port.handle_irq;
235dae5d 3284 /* Possibly override set_termios call */
f73fa05b
MD		 3285 if (up->port.set_termios)
3286 uart->port.set_termios = up->port.set_termios;
3287 if (up->port.pm)
3288 uart->port.pm = up->port.pm;
3289 if (up->port.handle_break)
3290 uart->port.handle_break = up->port.handle_break;
3291 if (up->dl_read)
3292 uart->dl_read = up->dl_read;
3293 if (up->dl_write)
3294 uart->dl_write = up->dl_write;
9ee4b83e
HK		 3295 if (up->dma)
3296 uart->dma = up->dma;
1da177e4 3297
af7f3743
AC		 3298 if (serial8250_isa_config != NULL)
3299 serial8250_isa_config(0, &uart->port,
3300 &uart->capabilities);
3301
1da177e4
LT		 3302 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3303 if (ret == 0)
3304 ret = uart->port.line;
3305 }
f392ecfa 3306 mutex_unlock(&serial_mutex);
1da177e4
LT		 3307
3308 return ret;
3309}
f73fa05b
MD		 3310EXPORT_SYMBOL(serial8250_register_8250_port);
3311
1da177e4
LT		 3312/**
3313 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3314 * @line: serial line number
3315 *
3316 * Remove one serial port. This may not be called from interrupt
3317 * context. We hand the port back to the our control.
3318 */
3319void serial8250_unregister_port(int line)
3320{
3321 struct uart_8250_port *uart = &serial8250_ports[line];
3322
f392ecfa 3323 mutex_lock(&serial_mutex);
1da177e4
LT		 3324 uart_remove_one_port(&serial8250_reg, &uart->port);
3325 if (serial8250_isa_devs) {
3326 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3327 uart->port.type = PORT_UNKNOWN;
3328 uart->port.dev = &serial8250_isa_devs->dev;
cb01ece3 3329 uart->capabilities = uart_config[uart->port.type].flags;
1da177e4
LT		 3330 uart_add_one_port(&serial8250_reg, &uart->port);
3331 } else {
3332 uart->port.dev = NULL;
3333 }
f392ecfa 3334 mutex_unlock(&serial_mutex);
1da177e4
LT		 3335}
3336EXPORT_SYMBOL(serial8250_unregister_port);
3337
3338static int __init serial8250_init(void)
3339{
25db8ad5 3340 int ret;
1da177e4 3341
835d844d 3342 serial8250_isa_init_ports();
a61c2d78 3343
f1fb9bb8 3344 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3345 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3346 share_irqs ? "en" : "dis");
3347
b70ac771
DM		 3348#ifdef CONFIG_SPARC
3349 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3350#else
3351 serial8250_reg.nr = UART_NR;
1da177e4 3352 ret = uart_register_driver(&serial8250_reg);
b70ac771 3353#endif
1da177e4
LT		 3354 if (ret)
3355 goto out;
3356
835d844d
SY		 3357 ret = serial8250_pnp_init();
3358 if (ret)
3359 goto unreg_uart_drv;
3360
7493a314
DT		 3361 serial8250_isa_devs = platform_device_alloc("serial8250",
3362 PLAT8250_DEV_LEGACY);
3363 if (!serial8250_isa_devs) {
3364 ret = -ENOMEM;
835d844d 3365 goto unreg_pnp;
1da177e4
LT		 3366 }
3367
7493a314
DT		 3368 ret = platform_device_add(serial8250_isa_devs);
3369 if (ret)
3370 goto put_dev;
3371
1da177e4
LT		 3372 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3373
bc965a7f
RK		 3374 ret = platform_driver_register(&serial8250_isa_driver);
3375 if (ret == 0)
3376 goto out;
1da177e4 3377
bc965a7f 3378 platform_device_del(serial8250_isa_devs);
25db8ad5 3379put_dev:
7493a314 3380 platform_device_put(serial8250_isa_devs);
835d844d
SY		 3381unreg_pnp:
3382 serial8250_pnp_exit();
25db8ad5 3383unreg_uart_drv:
b70ac771
DM		 3384#ifdef CONFIG_SPARC
3385 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3386#else
1da177e4 3387 uart_unregister_driver(&serial8250_reg);
b70ac771 3388#endif
25db8ad5 3389out:
1da177e4
LT		 3390 return ret;
3391}
3392
3393static void __exit serial8250_exit(void)
3394{
3395 struct platform_device *isa_dev = serial8250_isa_devs;
3396
3397 /*
3398 * This tells serial8250_unregister_port() not to re-register
3399 * the ports (thereby making serial8250_isa_driver permanently
3400 * in use.)
3401 */
3402 serial8250_isa_devs = NULL;
3403
3ae5eaec 3404 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3405 platform_device_unregister(isa_dev);
3406
835d844d
SY		 3407 serial8250_pnp_exit();
3408
b70ac771
DM		 3409#ifdef CONFIG_SPARC
3410 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3411#else
1da177e4 3412 uart_unregister_driver(&serial8250_reg);
b70ac771 3413#endif
1da177e4
LT		 3414}
3415
3416module_init(serial8250_init);
3417module_exit(serial8250_exit);
3418
3419EXPORT_SYMBOL(serial8250_suspend_port);
3420EXPORT_SYMBOL(serial8250_resume_port);
3421
3422MODULE_LICENSE("GPL");
d87a6d95 3423MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3424
3425module_param(share_irqs, uint, 0644);
3426MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3427 " (unsafe)");
3428
a61c2d78
DJ		 3429module_param(nr_uarts, uint, 0644);
3430MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3431
d41a4b51
CE		 3432module_param(skip_txen_test, uint, 0644);
3433MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3434
1da177e4
LT		 3435#ifdef CONFIG_SERIAL_8250_RSA
3436module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3437MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3438#endif
3439MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
f2b8dfd9 3440
9326b047 3441#ifdef CONFIG_SERIAL_8250_DEPRECATED_OPTIONS
f2b8dfd9
JB		 3442#ifndef MODULE
3443/* This module was renamed to 8250_core in 3.7. Keep the old "8250" name
3444 * working as well for the module options so we don't break people. We
3445 * need to keep the names identical and the convenient macros will happily
3446 * refuse to let us do that by failing the build with redefinition errors
3447 * of global variables. So we stick them inside a dummy function to avoid
3448 * those conflicts. The options still get parsed, and the redefined
3449 * MODULE_PARAM_PREFIX lets us keep the "8250." syntax alive.
3450 *
3451 * This is hacky. I'm sorry.
3452 */
3453static void __used s8250_options(void)
3454{
3455#undef MODULE_PARAM_PREFIX
9196d8ac 3456#define MODULE_PARAM_PREFIX "8250_core."
f2b8dfd9
JB		 3457
3458 module_param_cb(share_irqs, &param_ops_uint, &share_irqs, 0644);
3459 module_param_cb(nr_uarts, &param_ops_uint, &nr_uarts, 0644);
3460 module_param_cb(skip_txen_test, &param_ops_uint, &skip_txen_test, 0644);
3461#ifdef CONFIG_SERIAL_8250_RSA
3462 __module_param_call(MODULE_PARAM_PREFIX, probe_rsa,
3463 &param_array_ops, .arr = &__param_arr_probe_rsa,
3464 0444, -1);
3465#endif
3466}
3467#else
9196d8ac 3468MODULE_ALIAS("8250_core");
f2b8dfd9 3469#endif
f2b8dfd9 3470#endif
Linux kernel - Deliverables
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