Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for 8250/16550-type serial ports |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * | |
6 | * Copyright (C) 2001 Russell King. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
1da177e4 LT |
13 | * A note about mapbase / membase |
14 | * | |
15 | * mapbase is the physical address of the IO port. | |
16 | * membase is an 'ioremapped' cookie. | |
17 | */ | |
1da177e4 LT |
18 | |
19 | #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
20 | #define SUPPORT_SYSRQ | |
21 | #endif | |
22 | ||
23 | #include <linux/module.h> | |
24 | #include <linux/moduleparam.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/console.h> | |
28 | #include <linux/sysrq.h> | |
1da177e4 | 29 | #include <linux/delay.h> |
d052d1be | 30 | #include <linux/platform_device.h> |
1da177e4 | 31 | #include <linux/tty.h> |
cd3ecad1 | 32 | #include <linux/ratelimit.h> |
1da177e4 | 33 | #include <linux/tty_flip.h> |
1da177e4 LT |
34 | #include <linux/serial_core.h> |
35 | #include <linux/serial.h> | |
36 | #include <linux/serial_8250.h> | |
78512ece | 37 | #include <linux/nmi.h> |
f392ecfa | 38 | #include <linux/mutex.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
0b4af1d9 | 40 | #include <linux/uaccess.h> |
d74d5d1b | 41 | #include <linux/pm_runtime.h> |
6816383a PG |
42 | #ifdef CONFIG_SPARC |
43 | #include <linux/sunserialcore.h> | |
44 | #endif | |
1da177e4 LT |
45 | |
46 | #include <asm/io.h> | |
47 | #include <asm/irq.h> | |
48 | ||
49 | #include "8250.h" | |
50 | ||
51 | /* | |
52 | * Configuration: | |
40663cc7 | 53 | * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option |
1da177e4 LT |
54 | * is unsafe when used on edge-triggered interrupts. |
55 | */ | |
408b664a | 56 | static unsigned int share_irqs = SERIAL8250_SHARE_IRQS; |
1da177e4 | 57 | |
a61c2d78 DJ |
58 | static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS; |
59 | ||
8440838b DM |
60 | static struct uart_driver serial8250_reg; |
61 | ||
62 | static int serial_index(struct uart_port *port) | |
63 | { | |
64 | return (serial8250_reg.minor - 64) + port->line; | |
65 | } | |
66 | ||
d41a4b51 CE |
67 | static unsigned int skip_txen_test; /* force skip of txen test at init time */ |
68 | ||
1da177e4 LT |
69 | /* |
70 | * Debugging. | |
71 | */ | |
72 | #if 0 | |
73 | #define DEBUG_AUTOCONF(fmt...) printk(fmt) | |
74 | #else | |
75 | #define DEBUG_AUTOCONF(fmt...) do { } while (0) | |
76 | #endif | |
77 | ||
78 | #if 0 | |
79 | #define DEBUG_INTR(fmt...) printk(fmt) | |
80 | #else | |
81 | #define DEBUG_INTR(fmt...) do { } while (0) | |
82 | #endif | |
83 | ||
e7328ae1 | 84 | #define PASS_LIMIT 512 |
1da177e4 | 85 | |
bca47613 DH |
86 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
87 | ||
88 | ||
1da177e4 LT |
89 | #ifdef CONFIG_SERIAL_8250_DETECT_IRQ |
90 | #define CONFIG_SERIAL_DETECT_IRQ 1 | |
91 | #endif | |
1da177e4 LT |
92 | #ifdef CONFIG_SERIAL_8250_MANY_PORTS |
93 | #define CONFIG_SERIAL_MANY_PORTS 1 | |
94 | #endif | |
95 | ||
96 | /* | |
97 | * HUB6 is always on. This will be removed once the header | |
98 | * files have been cleaned. | |
99 | */ | |
100 | #define CONFIG_HUB6 1 | |
101 | ||
a4ed1e41 | 102 | #include <asm/serial.h> |
1da177e4 LT |
103 | /* |
104 | * SERIAL_PORT_DFNS tells us about built-in ports that have no | |
105 | * standard enumeration mechanism. Platforms that can find all | |
106 | * serial ports via mechanisms like ACPI or PCI need not supply it. | |
107 | */ | |
108 | #ifndef SERIAL_PORT_DFNS | |
109 | #define SERIAL_PORT_DFNS | |
110 | #endif | |
111 | ||
cb3592be | 112 | static const struct old_serial_port old_serial_port[] = { |
1da177e4 LT |
113 | SERIAL_PORT_DFNS /* defined in asm/serial.h */ |
114 | }; | |
115 | ||
026d02a2 | 116 | #define UART_NR CONFIG_SERIAL_8250_NR_UARTS |
1da177e4 LT |
117 | |
118 | #ifdef CONFIG_SERIAL_8250_RSA | |
119 | ||
120 | #define PORT_RSA_MAX 4 | |
121 | static unsigned long probe_rsa[PORT_RSA_MAX]; | |
122 | static unsigned int probe_rsa_count; | |
123 | #endif /* CONFIG_SERIAL_8250_RSA */ | |
124 | ||
1da177e4 | 125 | struct irq_info { |
25db8ad5 AC |
126 | struct hlist_node node; |
127 | int irq; | |
128 | spinlock_t lock; /* Protects list not the hash */ | |
1da177e4 LT |
129 | struct list_head *head; |
130 | }; | |
131 | ||
25db8ad5 AC |
132 | #define NR_IRQ_HASH 32 /* Can be adjusted later */ |
133 | static struct hlist_head irq_lists[NR_IRQ_HASH]; | |
134 | static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */ | |
1da177e4 LT |
135 | |
136 | /* | |
137 | * Here we define the default xmit fifo size used for each type of UART. | |
138 | */ | |
139 | static const struct serial8250_config uart_config[] = { | |
140 | [PORT_UNKNOWN] = { | |
141 | .name = "unknown", | |
142 | .fifo_size = 1, | |
143 | .tx_loadsz = 1, | |
144 | }, | |
145 | [PORT_8250] = { | |
146 | .name = "8250", | |
147 | .fifo_size = 1, | |
148 | .tx_loadsz = 1, | |
149 | }, | |
150 | [PORT_16450] = { | |
151 | .name = "16450", | |
152 | .fifo_size = 1, | |
153 | .tx_loadsz = 1, | |
154 | }, | |
155 | [PORT_16550] = { | |
156 | .name = "16550", | |
157 | .fifo_size = 1, | |
158 | .tx_loadsz = 1, | |
159 | }, | |
160 | [PORT_16550A] = { | |
161 | .name = "16550A", | |
162 | .fifo_size = 16, | |
163 | .tx_loadsz = 16, | |
164 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
aef9a7bd | 165 | .rxtrig_bytes = {1, 4, 8, 14}, |
1da177e4 LT |
166 | .flags = UART_CAP_FIFO, |
167 | }, | |
168 | [PORT_CIRRUS] = { | |
169 | .name = "Cirrus", | |
170 | .fifo_size = 1, | |
171 | .tx_loadsz = 1, | |
172 | }, | |
173 | [PORT_16650] = { | |
174 | .name = "ST16650", | |
175 | .fifo_size = 1, | |
176 | .tx_loadsz = 1, | |
177 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
178 | }, | |
179 | [PORT_16650V2] = { | |
180 | .name = "ST16650V2", | |
181 | .fifo_size = 32, | |
182 | .tx_loadsz = 16, | |
183 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
184 | UART_FCR_T_TRIG_00, | |
aef9a7bd | 185 | .rxtrig_bytes = {8, 16, 24, 28}, |
1da177e4 LT |
186 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, |
187 | }, | |
188 | [PORT_16750] = { | |
189 | .name = "TI16750", | |
190 | .fifo_size = 64, | |
191 | .tx_loadsz = 64, | |
192 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | | |
193 | UART_FCR7_64BYTE, | |
aef9a7bd | 194 | .rxtrig_bytes = {1, 16, 32, 56}, |
1da177e4 LT |
195 | .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, |
196 | }, | |
197 | [PORT_STARTECH] = { | |
198 | .name = "Startech", | |
199 | .fifo_size = 1, | |
200 | .tx_loadsz = 1, | |
201 | }, | |
202 | [PORT_16C950] = { | |
203 | .name = "16C950/954", | |
204 | .fifo_size = 128, | |
205 | .tx_loadsz = 128, | |
206 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
d0694e2a PM |
207 | /* UART_CAP_EFR breaks billionon CF bluetooth card. */ |
208 | .flags = UART_CAP_FIFO | UART_CAP_SLEEP, | |
1da177e4 LT |
209 | }, |
210 | [PORT_16654] = { | |
211 | .name = "ST16654", | |
212 | .fifo_size = 64, | |
213 | .tx_loadsz = 32, | |
214 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
215 | UART_FCR_T_TRIG_10, | |
aef9a7bd | 216 | .rxtrig_bytes = {8, 16, 56, 60}, |
1da177e4 LT |
217 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, |
218 | }, | |
219 | [PORT_16850] = { | |
220 | .name = "XR16850", | |
221 | .fifo_size = 128, | |
222 | .tx_loadsz = 128, | |
223 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
224 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |
225 | }, | |
226 | [PORT_RSA] = { | |
227 | .name = "RSA", | |
228 | .fifo_size = 2048, | |
229 | .tx_loadsz = 2048, | |
230 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11, | |
231 | .flags = UART_CAP_FIFO, | |
232 | }, | |
233 | [PORT_NS16550A] = { | |
234 | .name = "NS16550A", | |
235 | .fifo_size = 16, | |
236 | .tx_loadsz = 16, | |
237 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
238 | .flags = UART_CAP_FIFO | UART_NATSEMI, | |
239 | }, | |
240 | [PORT_XSCALE] = { | |
241 | .name = "XScale", | |
242 | .fifo_size = 32, | |
243 | .tx_loadsz = 32, | |
244 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
4539c24f | 245 | .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE, |
1da177e4 | 246 | }, |
6b06f191 DD |
247 | [PORT_OCTEON] = { |
248 | .name = "OCTEON", | |
249 | .fifo_size = 64, | |
250 | .tx_loadsz = 64, | |
251 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
bd71c182 TK |
252 | .flags = UART_CAP_FIFO, |
253 | }, | |
08e0992f FF |
254 | [PORT_AR7] = { |
255 | .name = "AR7", | |
256 | .fifo_size = 16, | |
257 | .tx_loadsz = 16, | |
258 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, | |
259 | .flags = UART_CAP_FIFO | UART_CAP_AFE, | |
260 | }, | |
235dae5d PL |
261 | [PORT_U6_16550A] = { |
262 | .name = "U6_16550A", | |
263 | .fifo_size = 64, | |
264 | .tx_loadsz = 64, | |
265 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
266 | .flags = UART_CAP_FIFO | UART_CAP_AFE, | |
267 | }, | |
4539c24f SW |
268 | [PORT_TEGRA] = { |
269 | .name = "Tegra", | |
270 | .fifo_size = 32, | |
271 | .tx_loadsz = 8, | |
272 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |
273 | UART_FCR_T_TRIG_01, | |
aef9a7bd | 274 | .rxtrig_bytes = {1, 4, 8, 14}, |
4539c24f SW |
275 | .flags = UART_CAP_FIFO | UART_CAP_RTOIE, |
276 | }, | |
06315348 SH |
277 | [PORT_XR17D15X] = { |
278 | .name = "XR17D15X", | |
279 | .fifo_size = 64, | |
280 | .tx_loadsz = 64, | |
281 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
81db0772 MS |
282 | .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR | |
283 | UART_CAP_SLEEP, | |
06315348 | 284 | }, |
dc96efb7 MS |
285 | [PORT_XR17V35X] = { |
286 | .name = "XR17V35X", | |
287 | .fifo_size = 256, | |
288 | .tx_loadsz = 256, | |
289 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 | | |
290 | UART_FCR_T_TRIG_11, | |
291 | .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR | | |
292 | UART_CAP_SLEEP, | |
293 | }, | |
7a514596 RS |
294 | [PORT_LPC3220] = { |
295 | .name = "LPC3220", | |
296 | .fifo_size = 64, | |
297 | .tx_loadsz = 32, | |
298 | .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO | | |
299 | UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00, | |
300 | .flags = UART_CAP_FIFO, | |
301 | }, | |
ebebd49a SH |
302 | [PORT_BRCM_TRUMANAGE] = { |
303 | .name = "TruManage", | |
304 | .fifo_size = 1, | |
305 | .tx_loadsz = 1024, | |
306 | .flags = UART_CAP_HFIFO, | |
307 | }, | |
65ecc9c0 SY |
308 | [PORT_8250_CIR] = { |
309 | .name = "CIR port" | |
e06c93ca LFT |
310 | }, |
311 | [PORT_ALTR_16550_F32] = { | |
312 | .name = "Altera 16550 FIFO32", | |
313 | .fifo_size = 32, | |
314 | .tx_loadsz = 32, | |
315 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
316 | .flags = UART_CAP_FIFO | UART_CAP_AFE, | |
317 | }, | |
318 | [PORT_ALTR_16550_F64] = { | |
319 | .name = "Altera 16550 FIFO64", | |
320 | .fifo_size = 64, | |
321 | .tx_loadsz = 64, | |
322 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
323 | .flags = UART_CAP_FIFO | UART_CAP_AFE, | |
324 | }, | |
325 | [PORT_ALTR_16550_F128] = { | |
326 | .name = "Altera 16550 FIFO128", | |
327 | .fifo_size = 128, | |
328 | .tx_loadsz = 128, | |
329 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |
330 | .flags = UART_CAP_FIFO | UART_CAP_AFE, | |
331 | }, | |
1da177e4 LT |
332 | }; |
333 | ||
cc419fa0 | 334 | /* Uart divisor latch read */ |
e8155629 | 335 | static int default_serial_dl_read(struct uart_8250_port *up) |
cc419fa0 MD |
336 | { |
337 | return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8; | |
338 | } | |
339 | ||
340 | /* Uart divisor latch write */ | |
e8155629 | 341 | static void default_serial_dl_write(struct uart_8250_port *up, int value) |
cc419fa0 MD |
342 | { |
343 | serial_out(up, UART_DLL, value & 0xff); | |
344 | serial_out(up, UART_DLM, value >> 8 & 0xff); | |
345 | } | |
346 | ||
c420811f | 347 | #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X) |
21c614a7 | 348 | |
c420811f | 349 | /* Au1x00/RT288x UART hardware has a weird register layout */ |
21c614a7 PA |
350 | static const u8 au_io_in_map[] = { |
351 | [UART_RX] = 0, | |
352 | [UART_IER] = 2, | |
353 | [UART_IIR] = 3, | |
354 | [UART_LCR] = 5, | |
355 | [UART_MCR] = 6, | |
356 | [UART_LSR] = 7, | |
357 | [UART_MSR] = 8, | |
358 | }; | |
359 | ||
360 | static const u8 au_io_out_map[] = { | |
361 | [UART_TX] = 1, | |
362 | [UART_IER] = 2, | |
363 | [UART_FCR] = 4, | |
364 | [UART_LCR] = 5, | |
365 | [UART_MCR] = 6, | |
366 | }; | |
367 | ||
6b416031 | 368 | static unsigned int au_serial_in(struct uart_port *p, int offset) |
21c614a7 | 369 | { |
6b416031 MD |
370 | offset = au_io_in_map[offset] << p->regshift; |
371 | return __raw_readl(p->membase + offset); | |
21c614a7 PA |
372 | } |
373 | ||
6b416031 | 374 | static void au_serial_out(struct uart_port *p, int offset, int value) |
21c614a7 | 375 | { |
6b416031 MD |
376 | offset = au_io_out_map[offset] << p->regshift; |
377 | __raw_writel(value, p->membase + offset); | |
378 | } | |
379 | ||
380 | /* Au1x00 haven't got a standard divisor latch */ | |
381 | static int au_serial_dl_read(struct uart_8250_port *up) | |
382 | { | |
383 | return __raw_readl(up->port.membase + 0x28); | |
384 | } | |
385 | ||
386 | static void au_serial_dl_write(struct uart_8250_port *up, int value) | |
387 | { | |
388 | __raw_writel(value, up->port.membase + 0x28); | |
21c614a7 PA |
389 | } |
390 | ||
6b416031 MD |
391 | #endif |
392 | ||
7d6a07d1 | 393 | static unsigned int hub6_serial_in(struct uart_port *p, int offset) |
1da177e4 | 394 | { |
e8155629 | 395 | offset = offset << p->regshift; |
7d6a07d1 DD |
396 | outb(p->hub6 - 1 + offset, p->iobase); |
397 | return inb(p->iobase + 1); | |
398 | } | |
1da177e4 | 399 | |
7d6a07d1 DD |
400 | static void hub6_serial_out(struct uart_port *p, int offset, int value) |
401 | { | |
e8155629 | 402 | offset = offset << p->regshift; |
7d6a07d1 DD |
403 | outb(p->hub6 - 1 + offset, p->iobase); |
404 | outb(value, p->iobase + 1); | |
405 | } | |
1da177e4 | 406 | |
7d6a07d1 DD |
407 | static unsigned int mem_serial_in(struct uart_port *p, int offset) |
408 | { | |
e8155629 | 409 | offset = offset << p->regshift; |
7d6a07d1 DD |
410 | return readb(p->membase + offset); |
411 | } | |
1da177e4 | 412 | |
7d6a07d1 DD |
413 | static void mem_serial_out(struct uart_port *p, int offset, int value) |
414 | { | |
e8155629 | 415 | offset = offset << p->regshift; |
7d6a07d1 DD |
416 | writeb(value, p->membase + offset); |
417 | } | |
418 | ||
419 | static void mem32_serial_out(struct uart_port *p, int offset, int value) | |
420 | { | |
e8155629 | 421 | offset = offset << p->regshift; |
7d6a07d1 DD |
422 | writel(value, p->membase + offset); |
423 | } | |
424 | ||
425 | static unsigned int mem32_serial_in(struct uart_port *p, int offset) | |
426 | { | |
e8155629 | 427 | offset = offset << p->regshift; |
7d6a07d1 DD |
428 | return readl(p->membase + offset); |
429 | } | |
1da177e4 | 430 | |
7d6a07d1 DD |
431 | static unsigned int io_serial_in(struct uart_port *p, int offset) |
432 | { | |
e8155629 | 433 | offset = offset << p->regshift; |
7d6a07d1 DD |
434 | return inb(p->iobase + offset); |
435 | } | |
436 | ||
437 | static void io_serial_out(struct uart_port *p, int offset, int value) | |
438 | { | |
e8155629 | 439 | offset = offset << p->regshift; |
7d6a07d1 DD |
440 | outb(value, p->iobase + offset); |
441 | } | |
442 | ||
583d28e9 | 443 | static int serial8250_default_handle_irq(struct uart_port *port); |
dc96efb7 | 444 | static int exar_handle_irq(struct uart_port *port); |
583d28e9 | 445 | |
7d6a07d1 DD |
446 | static void set_io_from_upio(struct uart_port *p) |
447 | { | |
b1261c86 | 448 | struct uart_8250_port *up = up_to_u8250p(p); |
cc419fa0 | 449 | |
e8155629 MD |
450 | up->dl_read = default_serial_dl_read; |
451 | up->dl_write = default_serial_dl_write; | |
cc419fa0 | 452 | |
7d6a07d1 | 453 | switch (p->iotype) { |
1da177e4 | 454 | case UPIO_HUB6: |
7d6a07d1 DD |
455 | p->serial_in = hub6_serial_in; |
456 | p->serial_out = hub6_serial_out; | |
1da177e4 LT |
457 | break; |
458 | ||
459 | case UPIO_MEM: | |
7d6a07d1 DD |
460 | p->serial_in = mem_serial_in; |
461 | p->serial_out = mem_serial_out; | |
1da177e4 LT |
462 | break; |
463 | ||
464 | case UPIO_MEM32: | |
7d6a07d1 DD |
465 | p->serial_in = mem32_serial_in; |
466 | p->serial_out = mem32_serial_out; | |
1da177e4 LT |
467 | break; |
468 | ||
c420811f | 469 | #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X) |
21c614a7 | 470 | case UPIO_AU: |
7d6a07d1 DD |
471 | p->serial_in = au_serial_in; |
472 | p->serial_out = au_serial_out; | |
6b416031 MD |
473 | up->dl_read = au_serial_dl_read; |
474 | up->dl_write = au_serial_dl_write; | |
21c614a7 | 475 | break; |
6b416031 | 476 | #endif |
12bf3f24 | 477 | |
1da177e4 | 478 | default: |
7d6a07d1 DD |
479 | p->serial_in = io_serial_in; |
480 | p->serial_out = io_serial_out; | |
481 | break; | |
1da177e4 | 482 | } |
b8e7e40a AC |
483 | /* Remember loaded iotype */ |
484 | up->cur_iotype = p->iotype; | |
583d28e9 | 485 | p->handle_irq = serial8250_default_handle_irq; |
1da177e4 LT |
486 | } |
487 | ||
40b36daa | 488 | static void |
55e4016d | 489 | serial_port_out_sync(struct uart_port *p, int offset, int value) |
40b36daa | 490 | { |
7d6a07d1 | 491 | switch (p->iotype) { |
40b36daa AW |
492 | case UPIO_MEM: |
493 | case UPIO_MEM32: | |
40b36daa | 494 | case UPIO_AU: |
7d6a07d1 DD |
495 | p->serial_out(p, offset, value); |
496 | p->serial_in(p, UART_LCR); /* safe, no side-effects */ | |
40b36daa AW |
497 | break; |
498 | default: | |
7d6a07d1 | 499 | p->serial_out(p, offset, value); |
40b36daa AW |
500 | } |
501 | } | |
502 | ||
1da177e4 LT |
503 | /* |
504 | * For the 16C950 | |
505 | */ | |
506 | static void serial_icr_write(struct uart_8250_port *up, int offset, int value) | |
507 | { | |
508 | serial_out(up, UART_SCR, offset); | |
509 | serial_out(up, UART_ICR, value); | |
510 | } | |
511 | ||
512 | static unsigned int serial_icr_read(struct uart_8250_port *up, int offset) | |
513 | { | |
514 | unsigned int value; | |
515 | ||
516 | serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); | |
517 | serial_out(up, UART_SCR, offset); | |
518 | value = serial_in(up, UART_ICR); | |
519 | serial_icr_write(up, UART_ACR, up->acr); | |
520 | ||
521 | return value; | |
522 | } | |
523 | ||
524 | /* | |
525 | * FIFO support. | |
526 | */ | |
b5d674ab | 527 | static void serial8250_clear_fifos(struct uart_8250_port *p) |
1da177e4 LT |
528 | { |
529 | if (p->capabilities & UART_CAP_FIFO) { | |
0acf519f PG |
530 | serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO); |
531 | serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO | | |
1da177e4 | 532 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); |
0acf519f | 533 | serial_out(p, UART_FCR, 0); |
1da177e4 LT |
534 | } |
535 | } | |
536 | ||
0ad372b9 SM |
537 | void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p) |
538 | { | |
0ad372b9 | 539 | serial8250_clear_fifos(p); |
aef9a7bd | 540 | serial_out(p, UART_FCR, p->fcr); |
0ad372b9 SM |
541 | } |
542 | EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos); | |
543 | ||
77285243 | 544 | void serial8250_rpm_get(struct uart_8250_port *p) |
d74d5d1b SAS |
545 | { |
546 | if (!(p->capabilities & UART_CAP_RPM)) | |
547 | return; | |
548 | pm_runtime_get_sync(p->port.dev); | |
549 | } | |
77285243 | 550 | EXPORT_SYMBOL_GPL(serial8250_rpm_get); |
d74d5d1b | 551 | |
77285243 | 552 | void serial8250_rpm_put(struct uart_8250_port *p) |
d74d5d1b SAS |
553 | { |
554 | if (!(p->capabilities & UART_CAP_RPM)) | |
555 | return; | |
556 | pm_runtime_mark_last_busy(p->port.dev); | |
557 | pm_runtime_put_autosuspend(p->port.dev); | |
558 | } | |
77285243 | 559 | EXPORT_SYMBOL_GPL(serial8250_rpm_put); |
d74d5d1b SAS |
560 | |
561 | /* | |
6a529aba | 562 | * These two wrappers ensure that enable_runtime_pm_tx() can be called more than |
d74d5d1b SAS |
563 | * once and disable_runtime_pm_tx() will still disable RPM because the fifo is |
564 | * empty and the HW can idle again. | |
565 | */ | |
566 | static void serial8250_rpm_get_tx(struct uart_8250_port *p) | |
567 | { | |
568 | unsigned char rpm_active; | |
569 | ||
570 | if (!(p->capabilities & UART_CAP_RPM)) | |
571 | return; | |
572 | ||
573 | rpm_active = xchg(&p->rpm_tx_active, 1); | |
574 | if (rpm_active) | |
575 | return; | |
576 | pm_runtime_get_sync(p->port.dev); | |
577 | } | |
578 | ||
579 | static void serial8250_rpm_put_tx(struct uart_8250_port *p) | |
580 | { | |
581 | unsigned char rpm_active; | |
582 | ||
583 | if (!(p->capabilities & UART_CAP_RPM)) | |
584 | return; | |
585 | ||
586 | rpm_active = xchg(&p->rpm_tx_active, 0); | |
587 | if (!rpm_active) | |
588 | return; | |
589 | pm_runtime_mark_last_busy(p->port.dev); | |
590 | pm_runtime_put_autosuspend(p->port.dev); | |
591 | } | |
592 | ||
1da177e4 LT |
593 | /* |
594 | * IER sleep support. UARTs which have EFRs need the "extended | |
595 | * capability" bit enabled. Note that on XR16C850s, we need to | |
596 | * reset LCR to write to IER. | |
597 | */ | |
b5d674ab | 598 | static void serial8250_set_sleep(struct uart_8250_port *p, int sleep) |
1da177e4 | 599 | { |
edf4edac | 600 | unsigned char lcr = 0, efr = 0; |
dc96efb7 MS |
601 | /* |
602 | * Exar UARTs have a SLEEP register that enables or disables | |
603 | * each UART to enter sleep mode separately. On the XR17V35x the | |
604 | * register is accessible to each UART at the UART_EXAR_SLEEP | |
605 | * offset but the UART channel may only write to the corresponding | |
606 | * bit. | |
607 | */ | |
d74d5d1b | 608 | serial8250_rpm_get(p); |
81db0772 MS |
609 | if ((p->port.type == PORT_XR17V35X) || |
610 | (p->port.type == PORT_XR17D15X)) { | |
b790f210 | 611 | serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0); |
d74d5d1b | 612 | goto out; |
dc96efb7 MS |
613 | } |
614 | ||
1da177e4 LT |
615 | if (p->capabilities & UART_CAP_SLEEP) { |
616 | if (p->capabilities & UART_CAP_EFR) { | |
edf4edac SS |
617 | lcr = serial_in(p, UART_LCR); |
618 | efr = serial_in(p, UART_EFR); | |
0acf519f PG |
619 | serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B); |
620 | serial_out(p, UART_EFR, UART_EFR_ECB); | |
621 | serial_out(p, UART_LCR, 0); | |
1da177e4 | 622 | } |
0acf519f | 623 | serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); |
1da177e4 | 624 | if (p->capabilities & UART_CAP_EFR) { |
0acf519f | 625 | serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B); |
edf4edac SS |
626 | serial_out(p, UART_EFR, efr); |
627 | serial_out(p, UART_LCR, lcr); | |
1da177e4 LT |
628 | } |
629 | } | |
d74d5d1b SAS |
630 | out: |
631 | serial8250_rpm_put(p); | |
1da177e4 LT |
632 | } |
633 | ||
634 | #ifdef CONFIG_SERIAL_8250_RSA | |
635 | /* | |
636 | * Attempts to turn on the RSA FIFO. Returns zero on failure. | |
637 | * We set the port uart clock rate if we succeed. | |
638 | */ | |
639 | static int __enable_rsa(struct uart_8250_port *up) | |
640 | { | |
641 | unsigned char mode; | |
642 | int result; | |
643 | ||
0acf519f | 644 | mode = serial_in(up, UART_RSA_MSR); |
1da177e4 LT |
645 | result = mode & UART_RSA_MSR_FIFO; |
646 | ||
647 | if (!result) { | |
0acf519f PG |
648 | serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); |
649 | mode = serial_in(up, UART_RSA_MSR); | |
1da177e4 LT |
650 | result = mode & UART_RSA_MSR_FIFO; |
651 | } | |
652 | ||
653 | if (result) | |
654 | up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; | |
655 | ||
656 | return result; | |
657 | } | |
658 | ||
659 | static void enable_rsa(struct uart_8250_port *up) | |
660 | { | |
661 | if (up->port.type == PORT_RSA) { | |
662 | if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { | |
663 | spin_lock_irq(&up->port.lock); | |
664 | __enable_rsa(up); | |
665 | spin_unlock_irq(&up->port.lock); | |
666 | } | |
667 | if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) | |
0acf519f | 668 | serial_out(up, UART_RSA_FRR, 0); |
1da177e4 LT |
669 | } |
670 | } | |
671 | ||
672 | /* | |
673 | * Attempts to turn off the RSA FIFO. Returns zero on failure. | |
674 | * It is unknown why interrupts were disabled in here. However, | |
675 | * the caller is expected to preserve this behaviour by grabbing | |
676 | * the spinlock before calling this function. | |
677 | */ | |
678 | static void disable_rsa(struct uart_8250_port *up) | |
679 | { | |
680 | unsigned char mode; | |
681 | int result; | |
682 | ||
683 | if (up->port.type == PORT_RSA && | |
684 | up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { | |
685 | spin_lock_irq(&up->port.lock); | |
686 | ||
0acf519f | 687 | mode = serial_in(up, UART_RSA_MSR); |
1da177e4 LT |
688 | result = !(mode & UART_RSA_MSR_FIFO); |
689 | ||
690 | if (!result) { | |
0acf519f PG |
691 | serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); |
692 | mode = serial_in(up, UART_RSA_MSR); | |
1da177e4 LT |
693 | result = !(mode & UART_RSA_MSR_FIFO); |
694 | } | |
695 | ||
696 | if (result) | |
697 | up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; | |
698 | spin_unlock_irq(&up->port.lock); | |
699 | } | |
700 | } | |
701 | #endif /* CONFIG_SERIAL_8250_RSA */ | |
702 | ||
703 | /* | |
704 | * This is a quickie test to see how big the FIFO is. | |
705 | * It doesn't work at all the time, more's the pity. | |
706 | */ | |
707 | static int size_fifo(struct uart_8250_port *up) | |
708 | { | |
b32b19b8 JAH |
709 | unsigned char old_fcr, old_mcr, old_lcr; |
710 | unsigned short old_dl; | |
1da177e4 LT |
711 | int count; |
712 | ||
0acf519f PG |
713 | old_lcr = serial_in(up, UART_LCR); |
714 | serial_out(up, UART_LCR, 0); | |
715 | old_fcr = serial_in(up, UART_FCR); | |
716 | old_mcr = serial_in(up, UART_MCR); | |
717 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
1da177e4 | 718 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); |
0acf519f PG |
719 | serial_out(up, UART_MCR, UART_MCR_LOOP); |
720 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
b32b19b8 JAH |
721 | old_dl = serial_dl_read(up); |
722 | serial_dl_write(up, 0x0001); | |
0acf519f | 723 | serial_out(up, UART_LCR, 0x03); |
1da177e4 | 724 | for (count = 0; count < 256; count++) |
0acf519f | 725 | serial_out(up, UART_TX, count); |
1da177e4 | 726 | mdelay(20);/* FIXME - schedule_timeout */ |
0acf519f | 727 | for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) && |
1da177e4 | 728 | (count < 256); count++) |
0acf519f PG |
729 | serial_in(up, UART_RX); |
730 | serial_out(up, UART_FCR, old_fcr); | |
731 | serial_out(up, UART_MCR, old_mcr); | |
732 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
b32b19b8 | 733 | serial_dl_write(up, old_dl); |
0acf519f | 734 | serial_out(up, UART_LCR, old_lcr); |
1da177e4 LT |
735 | |
736 | return count; | |
737 | } | |
738 | ||
739 | /* | |
740 | * Read UART ID using the divisor method - set DLL and DLM to zero | |
741 | * and the revision will be in DLL and device type in DLM. We | |
742 | * preserve the device state across this. | |
743 | */ | |
744 | static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) | |
745 | { | |
746 | unsigned char old_dll, old_dlm, old_lcr; | |
747 | unsigned int id; | |
748 | ||
0acf519f PG |
749 | old_lcr = serial_in(p, UART_LCR); |
750 | serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A); | |
1da177e4 | 751 | |
0acf519f PG |
752 | old_dll = serial_in(p, UART_DLL); |
753 | old_dlm = serial_in(p, UART_DLM); | |
1da177e4 | 754 | |
0acf519f PG |
755 | serial_out(p, UART_DLL, 0); |
756 | serial_out(p, UART_DLM, 0); | |
1da177e4 | 757 | |
0acf519f | 758 | id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8; |
1da177e4 | 759 | |
0acf519f PG |
760 | serial_out(p, UART_DLL, old_dll); |
761 | serial_out(p, UART_DLM, old_dlm); | |
762 | serial_out(p, UART_LCR, old_lcr); | |
1da177e4 LT |
763 | |
764 | return id; | |
765 | } | |
766 | ||
767 | /* | |
768 | * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's. | |
769 | * When this function is called we know it is at least a StarTech | |
770 | * 16650 V2, but it might be one of several StarTech UARTs, or one of | |
771 | * its clones. (We treat the broken original StarTech 16650 V1 as a | |
772 | * 16550, and why not? Startech doesn't seem to even acknowledge its | |
773 | * existence.) | |
bd71c182 | 774 | * |
1da177e4 LT |
775 | * What evil have men's minds wrought... |
776 | */ | |
777 | static void autoconfig_has_efr(struct uart_8250_port *up) | |
778 | { | |
779 | unsigned int id1, id2, id3, rev; | |
780 | ||
781 | /* | |
782 | * Everything with an EFR has SLEEP | |
783 | */ | |
784 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; | |
785 | ||
786 | /* | |
787 | * First we check to see if it's an Oxford Semiconductor UART. | |
788 | * | |
789 | * If we have to do this here because some non-National | |
790 | * Semiconductor clone chips lock up if you try writing to the | |
791 | * LSR register (which serial_icr_read does) | |
792 | */ | |
793 | ||
794 | /* | |
795 | * Check for Oxford Semiconductor 16C950. | |
796 | * | |
797 | * EFR [4] must be set else this test fails. | |
798 | * | |
799 | * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca) | |
800 | * claims that it's needed for 952 dual UART's (which are not | |
801 | * recommended for new designs). | |
802 | */ | |
803 | up->acr = 0; | |
662b083a | 804 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
1da177e4 LT |
805 | serial_out(up, UART_EFR, UART_EFR_ECB); |
806 | serial_out(up, UART_LCR, 0x00); | |
807 | id1 = serial_icr_read(up, UART_ID1); | |
808 | id2 = serial_icr_read(up, UART_ID2); | |
809 | id3 = serial_icr_read(up, UART_ID3); | |
810 | rev = serial_icr_read(up, UART_REV); | |
811 | ||
812 | DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev); | |
813 | ||
814 | if (id1 == 0x16 && id2 == 0xC9 && | |
815 | (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) { | |
816 | up->port.type = PORT_16C950; | |
4ba5e35d RK |
817 | |
818 | /* | |
819 | * Enable work around for the Oxford Semiconductor 952 rev B | |
820 | * chip which causes it to seriously miscalculate baud rates | |
821 | * when DLL is 0. | |
822 | */ | |
823 | if (id3 == 0x52 && rev == 0x01) | |
824 | up->bugs |= UART_BUG_QUOT; | |
1da177e4 LT |
825 | return; |
826 | } | |
bd71c182 | 827 | |
1da177e4 LT |
828 | /* |
829 | * We check for a XR16C850 by setting DLL and DLM to 0, and then | |
830 | * reading back DLL and DLM. The chip type depends on the DLM | |
831 | * value read back: | |
832 | * 0x10 - XR16C850 and the DLL contains the chip revision. | |
833 | * 0x12 - XR16C2850. | |
834 | * 0x14 - XR16C854. | |
835 | */ | |
836 | id1 = autoconfig_read_divisor_id(up); | |
837 | DEBUG_AUTOCONF("850id=%04x ", id1); | |
838 | ||
839 | id2 = id1 >> 8; | |
840 | if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) { | |
1da177e4 LT |
841 | up->port.type = PORT_16850; |
842 | return; | |
843 | } | |
844 | ||
845 | /* | |
846 | * It wasn't an XR16C850. | |
847 | * | |
848 | * We distinguish between the '654 and the '650 by counting | |
849 | * how many bytes are in the FIFO. I'm using this for now, | |
850 | * since that's the technique that was sent to me in the | |
851 | * serial driver update, but I'm not convinced this works. | |
852 | * I've had problems doing this in the past. -TYT | |
853 | */ | |
854 | if (size_fifo(up) == 64) | |
855 | up->port.type = PORT_16654; | |
856 | else | |
857 | up->port.type = PORT_16650V2; | |
858 | } | |
859 | ||
860 | /* | |
861 | * We detected a chip without a FIFO. Only two fall into | |
862 | * this category - the original 8250 and the 16450. The | |
863 | * 16450 has a scratch register (accessible with LCR=0) | |
864 | */ | |
865 | static void autoconfig_8250(struct uart_8250_port *up) | |
866 | { | |
867 | unsigned char scratch, status1, status2; | |
868 | ||
869 | up->port.type = PORT_8250; | |
870 | ||
871 | scratch = serial_in(up, UART_SCR); | |
0acf519f | 872 | serial_out(up, UART_SCR, 0xa5); |
1da177e4 | 873 | status1 = serial_in(up, UART_SCR); |
0acf519f | 874 | serial_out(up, UART_SCR, 0x5a); |
1da177e4 | 875 | status2 = serial_in(up, UART_SCR); |
0acf519f | 876 | serial_out(up, UART_SCR, scratch); |
1da177e4 LT |
877 | |
878 | if (status1 == 0xa5 && status2 == 0x5a) | |
879 | up->port.type = PORT_16450; | |
880 | } | |
881 | ||
882 | static int broken_efr(struct uart_8250_port *up) | |
883 | { | |
884 | /* | |
885 | * Exar ST16C2550 "A2" devices incorrectly detect as | |
886 | * having an EFR, and report an ID of 0x0201. See | |
631dd1a8 | 887 | * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html |
1da177e4 LT |
888 | */ |
889 | if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) | |
890 | return 1; | |
891 | ||
892 | return 0; | |
893 | } | |
894 | ||
0d0389e5 YK |
895 | static inline int ns16550a_goto_highspeed(struct uart_8250_port *up) |
896 | { | |
897 | unsigned char status; | |
898 | ||
899 | status = serial_in(up, 0x04); /* EXCR2 */ | |
900 | #define PRESL(x) ((x) & 0x30) | |
901 | if (PRESL(status) == 0x10) { | |
902 | /* already in high speed mode */ | |
903 | return 0; | |
904 | } else { | |
905 | status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */ | |
906 | status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */ | |
0acf519f | 907 | serial_out(up, 0x04, status); |
0d0389e5 YK |
908 | } |
909 | return 1; | |
910 | } | |
911 | ||
1da177e4 LT |
912 | /* |
913 | * We know that the chip has FIFOs. Does it have an EFR? The | |
914 | * EFR is located in the same register position as the IIR and | |
915 | * we know the top two bits of the IIR are currently set. The | |
916 | * EFR should contain zero. Try to read the EFR. | |
917 | */ | |
918 | static void autoconfig_16550a(struct uart_8250_port *up) | |
919 | { | |
920 | unsigned char status1, status2; | |
921 | unsigned int iersave; | |
922 | ||
923 | up->port.type = PORT_16550A; | |
924 | up->capabilities |= UART_CAP_FIFO; | |
925 | ||
dc96efb7 MS |
926 | /* |
927 | * XR17V35x UARTs have an extra divisor register, DLD | |
928 | * that gets enabled with when DLAB is set which will | |
929 | * cause the device to incorrectly match and assign | |
930 | * port type to PORT_16650. The EFR for this UART is | |
931 | * found at offset 0x09. Instead check the Deice ID (DVID) | |
932 | * register for a 2, 4 or 8 port UART. | |
933 | */ | |
b7a7e14f MS |
934 | if (up->port.flags & UPF_EXAR_EFR) { |
935 | status1 = serial_in(up, UART_EXAR_DVID); | |
936 | if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) { | |
dc96efb7 MS |
937 | DEBUG_AUTOCONF("Exar XR17V35x "); |
938 | up->port.type = PORT_XR17V35X; | |
939 | up->capabilities |= UART_CAP_AFE | UART_CAP_EFR | | |
940 | UART_CAP_SLEEP; | |
941 | ||
942 | return; | |
943 | } | |
944 | ||
945 | } | |
946 | ||
1da177e4 LT |
947 | /* |
948 | * Check for presence of the EFR when DLAB is set. | |
949 | * Only ST16C650V1 UARTs pass this test. | |
950 | */ | |
0acf519f | 951 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
1da177e4 | 952 | if (serial_in(up, UART_EFR) == 0) { |
0acf519f | 953 | serial_out(up, UART_EFR, 0xA8); |
1da177e4 LT |
954 | if (serial_in(up, UART_EFR) != 0) { |
955 | DEBUG_AUTOCONF("EFRv1 "); | |
956 | up->port.type = PORT_16650; | |
957 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; | |
958 | } else { | |
959 | DEBUG_AUTOCONF("Motorola 8xxx DUART "); | |
960 | } | |
0acf519f | 961 | serial_out(up, UART_EFR, 0); |
1da177e4 LT |
962 | return; |
963 | } | |
964 | ||
965 | /* | |
966 | * Maybe it requires 0xbf to be written to the LCR. | |
967 | * (other ST16C650V2 UARTs, TI16C752A, etc) | |
968 | */ | |
0acf519f | 969 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
1da177e4 LT |
970 | if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) { |
971 | DEBUG_AUTOCONF("EFRv2 "); | |
972 | autoconfig_has_efr(up); | |
973 | return; | |
974 | } | |
975 | ||
976 | /* | |
977 | * Check for a National Semiconductor SuperIO chip. | |
978 | * Attempt to switch to bank 2, read the value of the LOOP bit | |
979 | * from EXCR1. Switch back to bank 0, change it in MCR. Then | |
980 | * switch back to bank 2, read it from EXCR1 again and check | |
981 | * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2 | |
1da177e4 | 982 | */ |
0acf519f | 983 | serial_out(up, UART_LCR, 0); |
1da177e4 | 984 | status1 = serial_in(up, UART_MCR); |
0acf519f | 985 | serial_out(up, UART_LCR, 0xE0); |
1da177e4 LT |
986 | status2 = serial_in(up, 0x02); /* EXCR1 */ |
987 | ||
988 | if (!((status2 ^ status1) & UART_MCR_LOOP)) { | |
0acf519f PG |
989 | serial_out(up, UART_LCR, 0); |
990 | serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP); | |
991 | serial_out(up, UART_LCR, 0xE0); | |
1da177e4 | 992 | status2 = serial_in(up, 0x02); /* EXCR1 */ |
0acf519f PG |
993 | serial_out(up, UART_LCR, 0); |
994 | serial_out(up, UART_MCR, status1); | |
1da177e4 LT |
995 | |
996 | if ((status2 ^ status1) & UART_MCR_LOOP) { | |
857dde2e DW |
997 | unsigned short quot; |
998 | ||
0acf519f | 999 | serial_out(up, UART_LCR, 0xE0); |
857dde2e | 1000 | |
b32b19b8 | 1001 | quot = serial_dl_read(up); |
857dde2e DW |
1002 | quot <<= 3; |
1003 | ||
0d0389e5 YK |
1004 | if (ns16550a_goto_highspeed(up)) |
1005 | serial_dl_write(up, quot); | |
857dde2e | 1006 | |
0acf519f | 1007 | serial_out(up, UART_LCR, 0); |
1da177e4 | 1008 | |
857dde2e | 1009 | up->port.uartclk = 921600*16; |
1da177e4 LT |
1010 | up->port.type = PORT_NS16550A; |
1011 | up->capabilities |= UART_NATSEMI; | |
1012 | return; | |
1013 | } | |
1014 | } | |
1015 | ||
1016 | /* | |
1017 | * No EFR. Try to detect a TI16750, which only sets bit 5 of | |
1018 | * the IIR when 64 byte FIFO mode is enabled when DLAB is set. | |
1019 | * Try setting it with and without DLAB set. Cheap clones | |
1020 | * set bit 5 without DLAB set. | |
1021 | */ | |
0acf519f PG |
1022 | serial_out(up, UART_LCR, 0); |
1023 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); | |
1da177e4 | 1024 | status1 = serial_in(up, UART_IIR) >> 5; |
0acf519f PG |
1025 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); |
1026 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
1027 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); | |
1da177e4 | 1028 | status2 = serial_in(up, UART_IIR) >> 5; |
0acf519f PG |
1029 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); |
1030 | serial_out(up, UART_LCR, 0); | |
1da177e4 LT |
1031 | |
1032 | DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2); | |
1033 | ||
1034 | if (status1 == 6 && status2 == 7) { | |
1035 | up->port.type = PORT_16750; | |
1036 | up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; | |
1037 | return; | |
1038 | } | |
1039 | ||
1040 | /* | |
1041 | * Try writing and reading the UART_IER_UUE bit (b6). | |
1042 | * If it works, this is probably one of the Xscale platform's | |
1043 | * internal UARTs. | |
1044 | * We're going to explicitly set the UUE bit to 0 before | |
1045 | * trying to write and read a 1 just to make sure it's not | |
1046 | * already a 1 and maybe locked there before we even start start. | |
1047 | */ | |
1048 | iersave = serial_in(up, UART_IER); | |
0acf519f | 1049 | serial_out(up, UART_IER, iersave & ~UART_IER_UUE); |
1da177e4 LT |
1050 | if (!(serial_in(up, UART_IER) & UART_IER_UUE)) { |
1051 | /* | |
1052 | * OK it's in a known zero state, try writing and reading | |
1053 | * without disturbing the current state of the other bits. | |
1054 | */ | |
0acf519f | 1055 | serial_out(up, UART_IER, iersave | UART_IER_UUE); |
1da177e4 LT |
1056 | if (serial_in(up, UART_IER) & UART_IER_UUE) { |
1057 | /* | |
1058 | * It's an Xscale. | |
1059 | * We'll leave the UART_IER_UUE bit set to 1 (enabled). | |
1060 | */ | |
1061 | DEBUG_AUTOCONF("Xscale "); | |
1062 | up->port.type = PORT_XSCALE; | |
5568181f | 1063 | up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE; |
1da177e4 LT |
1064 | return; |
1065 | } | |
1066 | } else { | |
1067 | /* | |
1068 | * If we got here we couldn't force the IER_UUE bit to 0. | |
1069 | * Log it and continue. | |
1070 | */ | |
1071 | DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 "); | |
1072 | } | |
0acf519f | 1073 | serial_out(up, UART_IER, iersave); |
235dae5d | 1074 | |
06315348 SH |
1075 | /* |
1076 | * Exar uarts have EFR in a weird location | |
1077 | */ | |
1078 | if (up->port.flags & UPF_EXAR_EFR) { | |
81db0772 | 1079 | DEBUG_AUTOCONF("Exar XR17D15x "); |
06315348 | 1080 | up->port.type = PORT_XR17D15X; |
81db0772 MS |
1081 | up->capabilities |= UART_CAP_AFE | UART_CAP_EFR | |
1082 | UART_CAP_SLEEP; | |
1083 | ||
1084 | return; | |
06315348 SH |
1085 | } |
1086 | ||
235dae5d PL |
1087 | /* |
1088 | * We distinguish between 16550A and U6 16550A by counting | |
1089 | * how many bytes are in the FIFO. | |
1090 | */ | |
1091 | if (up->port.type == PORT_16550A && size_fifo(up) == 64) { | |
1092 | up->port.type = PORT_U6_16550A; | |
1093 | up->capabilities |= UART_CAP_AFE; | |
1094 | } | |
1da177e4 LT |
1095 | } |
1096 | ||
1097 | /* | |
1098 | * This routine is called by rs_init() to initialize a specific serial | |
1099 | * port. It determines what type of UART chip this serial port is | |
1100 | * using: 8250, 16450, 16550, 16550A. The important question is | |
1101 | * whether or not this UART is a 16550A or not, since this will | |
1102 | * determine whether or not we can use its FIFO features or not. | |
1103 | */ | |
1104 | static void autoconfig(struct uart_8250_port *up, unsigned int probeflags) | |
1105 | { | |
1106 | unsigned char status1, scratch, scratch2, scratch3; | |
1107 | unsigned char save_lcr, save_mcr; | |
dfe42443 | 1108 | struct uart_port *port = &up->port; |
1da177e4 | 1109 | unsigned long flags; |
bd21f551 | 1110 | unsigned int old_capabilities; |
1da177e4 | 1111 | |
dfe42443 | 1112 | if (!port->iobase && !port->mapbase && !port->membase) |
1da177e4 LT |
1113 | return; |
1114 | ||
80647b95 | 1115 | DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ", |
dfe42443 | 1116 | serial_index(port), port->iobase, port->membase); |
1da177e4 LT |
1117 | |
1118 | /* | |
1119 | * We really do need global IRQs disabled here - we're going to | |
1120 | * be frobbing the chips IRQ enable register to see if it exists. | |
1121 | */ | |
dfe42443 | 1122 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 LT |
1123 | |
1124 | up->capabilities = 0; | |
4ba5e35d | 1125 | up->bugs = 0; |
1da177e4 | 1126 | |
dfe42443 | 1127 | if (!(port->flags & UPF_BUGGY_UART)) { |
1da177e4 LT |
1128 | /* |
1129 | * Do a simple existence test first; if we fail this, | |
1130 | * there's no point trying anything else. | |
bd71c182 | 1131 | * |
1da177e4 LT |
1132 | * 0x80 is used as a nonsense port to prevent against |
1133 | * false positives due to ISA bus float. The | |
1134 | * assumption is that 0x80 is a non-existent port; | |
1135 | * which should be safe since include/asm/io.h also | |
1136 | * makes this assumption. | |
1137 | * | |
1138 | * Note: this is safe as long as MCR bit 4 is clear | |
1139 | * and the device is in "PC" mode. | |
1140 | */ | |
0acf519f PG |
1141 | scratch = serial_in(up, UART_IER); |
1142 | serial_out(up, UART_IER, 0); | |
1da177e4 LT |
1143 | #ifdef __i386__ |
1144 | outb(0xff, 0x080); | |
1145 | #endif | |
48212008 TH |
1146 | /* |
1147 | * Mask out IER[7:4] bits for test as some UARTs (e.g. TL | |
1148 | * 16C754B) allow only to modify them if an EFR bit is set. | |
1149 | */ | |
0acf519f PG |
1150 | scratch2 = serial_in(up, UART_IER) & 0x0f; |
1151 | serial_out(up, UART_IER, 0x0F); | |
1da177e4 LT |
1152 | #ifdef __i386__ |
1153 | outb(0, 0x080); | |
1154 | #endif | |
0acf519f PG |
1155 | scratch3 = serial_in(up, UART_IER) & 0x0f; |
1156 | serial_out(up, UART_IER, scratch); | |
1da177e4 LT |
1157 | if (scratch2 != 0 || scratch3 != 0x0F) { |
1158 | /* | |
1159 | * We failed; there's nothing here | |
1160 | */ | |
bd21f551 | 1161 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
1162 | DEBUG_AUTOCONF("IER test failed (%02x, %02x) ", |
1163 | scratch2, scratch3); | |
1164 | goto out; | |
1165 | } | |
1166 | } | |
1167 | ||
1168 | save_mcr = serial_in(up, UART_MCR); | |
1169 | save_lcr = serial_in(up, UART_LCR); | |
1170 | ||
bd71c182 | 1171 | /* |
1da177e4 LT |
1172 | * Check to see if a UART is really there. Certain broken |
1173 | * internal modems based on the Rockwell chipset fail this | |
1174 | * test, because they apparently don't implement the loopback | |
1175 | * test mode. So this test is skipped on the COM 1 through | |
1176 | * COM 4 ports. This *should* be safe, since no board | |
1177 | * manufacturer would be stupid enough to design a board | |
1178 | * that conflicts with COM 1-4 --- we hope! | |
1179 | */ | |
dfe42443 | 1180 | if (!(port->flags & UPF_SKIP_TEST)) { |
0acf519f PG |
1181 | serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A); |
1182 | status1 = serial_in(up, UART_MSR) & 0xF0; | |
1183 | serial_out(up, UART_MCR, save_mcr); | |
1da177e4 | 1184 | if (status1 != 0x90) { |
bd21f551 | 1185 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
1186 | DEBUG_AUTOCONF("LOOP test failed (%02x) ", |
1187 | status1); | |
1188 | goto out; | |
1189 | } | |
1190 | } | |
1191 | ||
1192 | /* | |
1193 | * We're pretty sure there's a port here. Lets find out what | |
1194 | * type of port it is. The IIR top two bits allows us to find | |
6f0d618f | 1195 | * out if it's 8250 or 16450, 16550, 16550A or later. This |
1da177e4 LT |
1196 | * determines what we test for next. |
1197 | * | |
1198 | * We also initialise the EFR (if any) to zero for later. The | |
1199 | * EFR occupies the same register location as the FCR and IIR. | |
1200 | */ | |
0acf519f PG |
1201 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
1202 | serial_out(up, UART_EFR, 0); | |
1203 | serial_out(up, UART_LCR, 0); | |
1da177e4 | 1204 | |
0acf519f | 1205 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); |
1da177e4 LT |
1206 | scratch = serial_in(up, UART_IIR) >> 6; |
1207 | ||
1da177e4 LT |
1208 | switch (scratch) { |
1209 | case 0: | |
1210 | autoconfig_8250(up); | |
1211 | break; | |
1212 | case 1: | |
dfe42443 | 1213 | port->type = PORT_UNKNOWN; |
1da177e4 LT |
1214 | break; |
1215 | case 2: | |
dfe42443 | 1216 | port->type = PORT_16550; |
1da177e4 LT |
1217 | break; |
1218 | case 3: | |
1219 | autoconfig_16550a(up); | |
1220 | break; | |
1221 | } | |
1222 | ||
1223 | #ifdef CONFIG_SERIAL_8250_RSA | |
1224 | /* | |
1225 | * Only probe for RSA ports if we got the region. | |
1226 | */ | |
dfe42443 | 1227 | if (port->type == PORT_16550A && probeflags & PROBE_RSA) { |
1da177e4 LT |
1228 | int i; |
1229 | ||
1230 | for (i = 0 ; i < probe_rsa_count; ++i) { | |
dfe42443 PG |
1231 | if (probe_rsa[i] == port->iobase && __enable_rsa(up)) { |
1232 | port->type = PORT_RSA; | |
1da177e4 LT |
1233 | break; |
1234 | } | |
1235 | } | |
1236 | } | |
1237 | #endif | |
21c614a7 | 1238 | |
0acf519f | 1239 | serial_out(up, UART_LCR, save_lcr); |
1da177e4 | 1240 | |
dfe42443 | 1241 | port->fifosize = uart_config[up->port.type].fifo_size; |
bd21f551 | 1242 | old_capabilities = up->capabilities; |
dfe42443 PG |
1243 | up->capabilities = uart_config[port->type].flags; |
1244 | up->tx_loadsz = uart_config[port->type].tx_loadsz; | |
1da177e4 | 1245 | |
dfe42443 | 1246 | if (port->type == PORT_UNKNOWN) |
bd21f551 | 1247 | goto out_lock; |
1da177e4 LT |
1248 | |
1249 | /* | |
1250 | * Reset the UART. | |
1251 | */ | |
1252 | #ifdef CONFIG_SERIAL_8250_RSA | |
dfe42443 | 1253 | if (port->type == PORT_RSA) |
0acf519f | 1254 | serial_out(up, UART_RSA_FRR, 0); |
1da177e4 | 1255 | #endif |
0acf519f | 1256 | serial_out(up, UART_MCR, save_mcr); |
1da177e4 | 1257 | serial8250_clear_fifos(up); |
40b36daa | 1258 | serial_in(up, UART_RX); |
5c8c755c | 1259 | if (up->capabilities & UART_CAP_UUE) |
0acf519f | 1260 | serial_out(up, UART_IER, UART_IER_UUE); |
5c8c755c | 1261 | else |
0acf519f | 1262 | serial_out(up, UART_IER, 0); |
1da177e4 | 1263 | |
bd21f551 | 1264 | out_lock: |
dfe42443 | 1265 | spin_unlock_irqrestore(&port->lock, flags); |
bd21f551 FL |
1266 | if (up->capabilities != old_capabilities) { |
1267 | printk(KERN_WARNING | |
1268 | "ttyS%d: detected caps %08x should be %08x\n", | |
1269 | serial_index(port), old_capabilities, | |
1270 | up->capabilities); | |
1271 | } | |
1272 | out: | |
1273 | DEBUG_AUTOCONF("iir=%d ", scratch); | |
dfe42443 | 1274 | DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name); |
1da177e4 LT |
1275 | } |
1276 | ||
1277 | static void autoconfig_irq(struct uart_8250_port *up) | |
1278 | { | |
dfe42443 | 1279 | struct uart_port *port = &up->port; |
1da177e4 LT |
1280 | unsigned char save_mcr, save_ier; |
1281 | unsigned char save_ICP = 0; | |
1282 | unsigned int ICP = 0; | |
1283 | unsigned long irqs; | |
1284 | int irq; | |
1285 | ||
dfe42443 PG |
1286 | if (port->flags & UPF_FOURPORT) { |
1287 | ICP = (port->iobase & 0xfe0) | 0x1f; | |
1da177e4 LT |
1288 | save_ICP = inb_p(ICP); |
1289 | outb_p(0x80, ICP); | |
0d263a26 | 1290 | inb_p(ICP); |
1da177e4 LT |
1291 | } |
1292 | ||
1293 | /* forget possible initially masked and pending IRQ */ | |
1294 | probe_irq_off(probe_irq_on()); | |
0acf519f PG |
1295 | save_mcr = serial_in(up, UART_MCR); |
1296 | save_ier = serial_in(up, UART_IER); | |
1297 | serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2); | |
bd71c182 | 1298 | |
1da177e4 | 1299 | irqs = probe_irq_on(); |
0acf519f | 1300 | serial_out(up, UART_MCR, 0); |
6f803cd0 | 1301 | udelay(10); |
dfe42443 | 1302 | if (port->flags & UPF_FOURPORT) { |
0acf519f | 1303 | serial_out(up, UART_MCR, |
1da177e4 LT |
1304 | UART_MCR_DTR | UART_MCR_RTS); |
1305 | } else { | |
0acf519f | 1306 | serial_out(up, UART_MCR, |
1da177e4 LT |
1307 | UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); |
1308 | } | |
0acf519f | 1309 | serial_out(up, UART_IER, 0x0f); /* enable all intrs */ |
0d263a26 PG |
1310 | serial_in(up, UART_LSR); |
1311 | serial_in(up, UART_RX); | |
1312 | serial_in(up, UART_IIR); | |
1313 | serial_in(up, UART_MSR); | |
0acf519f | 1314 | serial_out(up, UART_TX, 0xFF); |
6f803cd0 | 1315 | udelay(20); |
1da177e4 LT |
1316 | irq = probe_irq_off(irqs); |
1317 | ||
0acf519f PG |
1318 | serial_out(up, UART_MCR, save_mcr); |
1319 | serial_out(up, UART_IER, save_ier); | |
1da177e4 | 1320 | |
dfe42443 | 1321 | if (port->flags & UPF_FOURPORT) |
1da177e4 LT |
1322 | outb_p(save_ICP, ICP); |
1323 | ||
dfe42443 | 1324 | port->irq = (irq > 0) ? irq : 0; |
1da177e4 LT |
1325 | } |
1326 | ||
e763b90c RK |
1327 | static inline void __stop_tx(struct uart_8250_port *p) |
1328 | { | |
1329 | if (p->ier & UART_IER_THRI) { | |
1330 | p->ier &= ~UART_IER_THRI; | |
1331 | serial_out(p, UART_IER, p->ier); | |
d74d5d1b | 1332 | serial8250_rpm_put_tx(p); |
e763b90c RK |
1333 | } |
1334 | } | |
1335 | ||
b129a8cc | 1336 | static void serial8250_stop_tx(struct uart_port *port) |
1da177e4 | 1337 | { |
b1261c86 | 1338 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 | 1339 | |
d74d5d1b | 1340 | serial8250_rpm_get(up); |
e763b90c | 1341 | __stop_tx(up); |
1da177e4 LT |
1342 | |
1343 | /* | |
e763b90c | 1344 | * We really want to stop the transmitter from sending. |
1da177e4 | 1345 | */ |
dfe42443 | 1346 | if (port->type == PORT_16C950) { |
1da177e4 LT |
1347 | up->acr |= UART_ACR_TXDIS; |
1348 | serial_icr_write(up, UART_ACR, up->acr); | |
1349 | } | |
d74d5d1b | 1350 | serial8250_rpm_put(up); |
1da177e4 LT |
1351 | } |
1352 | ||
b129a8cc | 1353 | static void serial8250_start_tx(struct uart_port *port) |
1da177e4 | 1354 | { |
b1261c86 | 1355 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 | 1356 | |
d74d5d1b | 1357 | serial8250_rpm_get_tx(up); |
f1a297bb | 1358 | if (up->dma && !up->dma->tx_dma(up)) { |
9ee4b83e HK |
1359 | return; |
1360 | } else if (!(up->ier & UART_IER_THRI)) { | |
1da177e4 | 1361 | up->ier |= UART_IER_THRI; |
4fd996a1 | 1362 | serial_port_out(port, UART_IER, up->ier); |
55d3b282 | 1363 | |
67f7654e | 1364 | if (up->bugs & UART_BUG_TXEN) { |
68cb4f8e | 1365 | unsigned char lsr; |
55d3b282 | 1366 | lsr = serial_in(up, UART_LSR); |
ad4c2aa6 | 1367 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; |
a205a56d | 1368 | if (lsr & UART_LSR_TEMT) |
3986fb2b | 1369 | serial8250_tx_chars(up); |
55d3b282 | 1370 | } |
1da177e4 | 1371 | } |
e763b90c | 1372 | |
1da177e4 | 1373 | /* |
e763b90c | 1374 | * Re-enable the transmitter if we disabled it. |
1da177e4 | 1375 | */ |
dfe42443 | 1376 | if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { |
1da177e4 LT |
1377 | up->acr &= ~UART_ACR_TXDIS; |
1378 | serial_icr_write(up, UART_ACR, up->acr); | |
1379 | } | |
1380 | } | |
1381 | ||
234abab1 SAS |
1382 | static void serial8250_throttle(struct uart_port *port) |
1383 | { | |
1384 | port->throttle(port); | |
1385 | } | |
1386 | ||
1387 | static void serial8250_unthrottle(struct uart_port *port) | |
1388 | { | |
1389 | port->unthrottle(port); | |
1390 | } | |
1391 | ||
1da177e4 LT |
1392 | static void serial8250_stop_rx(struct uart_port *port) |
1393 | { | |
b1261c86 | 1394 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 | 1395 | |
d74d5d1b SAS |
1396 | serial8250_rpm_get(up); |
1397 | ||
9137568e | 1398 | up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); |
1da177e4 | 1399 | up->port.read_status_mask &= ~UART_LSR_DR; |
4fd996a1 | 1400 | serial_port_out(port, UART_IER, up->ier); |
d74d5d1b SAS |
1401 | |
1402 | serial8250_rpm_put(up); | |
1da177e4 LT |
1403 | } |
1404 | ||
1405 | static void serial8250_enable_ms(struct uart_port *port) | |
1406 | { | |
b1261c86 | 1407 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 | 1408 | |
21c614a7 PA |
1409 | /* no MSR capabilities */ |
1410 | if (up->bugs & UART_BUG_NOMSR) | |
1411 | return; | |
1412 | ||
1da177e4 | 1413 | up->ier |= UART_IER_MSI; |
d74d5d1b SAS |
1414 | |
1415 | serial8250_rpm_get(up); | |
4fd996a1 | 1416 | serial_port_out(port, UART_IER, up->ier); |
d74d5d1b | 1417 | serial8250_rpm_put(up); |
1da177e4 LT |
1418 | } |
1419 | ||
0690f41f | 1420 | /* |
3986fb2b | 1421 | * serial8250_rx_chars: processes according to the passed in LSR |
0690f41f PG |
1422 | * value, and returns the remaining LSR bits not handled |
1423 | * by this Rx routine. | |
1424 | */ | |
3986fb2b PG |
1425 | unsigned char |
1426 | serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr) | |
1da177e4 | 1427 | { |
dfe42443 | 1428 | struct uart_port *port = &up->port; |
0690f41f | 1429 | unsigned char ch; |
1da177e4 LT |
1430 | int max_count = 256; |
1431 | char flag; | |
1432 | ||
1433 | do { | |
7500b1f6 | 1434 | if (likely(lsr & UART_LSR_DR)) |
0acf519f | 1435 | ch = serial_in(up, UART_RX); |
7500b1f6 AR |
1436 | else |
1437 | /* | |
1438 | * Intel 82571 has a Serial Over Lan device that will | |
1439 | * set UART_LSR_BI without setting UART_LSR_DR when | |
1440 | * it receives a break. To avoid reading from the | |
1441 | * receive buffer without UART_LSR_DR bit set, we | |
1442 | * just force the read character to be 0 | |
1443 | */ | |
1444 | ch = 0; | |
1445 | ||
1da177e4 | 1446 | flag = TTY_NORMAL; |
dfe42443 | 1447 | port->icount.rx++; |
1da177e4 | 1448 | |
ad4c2aa6 CM |
1449 | lsr |= up->lsr_saved_flags; |
1450 | up->lsr_saved_flags = 0; | |
1da177e4 | 1451 | |
ad4c2aa6 | 1452 | if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { |
1da177e4 LT |
1453 | if (lsr & UART_LSR_BI) { |
1454 | lsr &= ~(UART_LSR_FE | UART_LSR_PE); | |
dfe42443 | 1455 | port->icount.brk++; |
1da177e4 LT |
1456 | /* |
1457 | * We do the SysRQ and SAK checking | |
1458 | * here because otherwise the break | |
1459 | * may get masked by ignore_status_mask | |
1460 | * or read_status_mask. | |
1461 | */ | |
dfe42443 | 1462 | if (uart_handle_break(port)) |
1da177e4 LT |
1463 | goto ignore_char; |
1464 | } else if (lsr & UART_LSR_PE) | |
dfe42443 | 1465 | port->icount.parity++; |
1da177e4 | 1466 | else if (lsr & UART_LSR_FE) |
dfe42443 | 1467 | port->icount.frame++; |
1da177e4 | 1468 | if (lsr & UART_LSR_OE) |
dfe42443 | 1469 | port->icount.overrun++; |
1da177e4 LT |
1470 | |
1471 | /* | |
23907eb8 | 1472 | * Mask off conditions which should be ignored. |
1da177e4 | 1473 | */ |
dfe42443 | 1474 | lsr &= port->read_status_mask; |
1da177e4 LT |
1475 | |
1476 | if (lsr & UART_LSR_BI) { | |
1477 | DEBUG_INTR("handling break...."); | |
1478 | flag = TTY_BREAK; | |
1479 | } else if (lsr & UART_LSR_PE) | |
1480 | flag = TTY_PARITY; | |
1481 | else if (lsr & UART_LSR_FE) | |
1482 | flag = TTY_FRAME; | |
1483 | } | |
dfe42443 | 1484 | if (uart_handle_sysrq_char(port, ch)) |
1da177e4 | 1485 | goto ignore_char; |
05ab3014 | 1486 | |
dfe42443 | 1487 | uart_insert_char(port, lsr, UART_LSR_OE, ch, flag); |
05ab3014 | 1488 | |
6f803cd0 | 1489 | ignore_char: |
0acf519f | 1490 | lsr = serial_in(up, UART_LSR); |
7500b1f6 | 1491 | } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0)); |
dfe42443 | 1492 | spin_unlock(&port->lock); |
2e124b4a | 1493 | tty_flip_buffer_push(&port->state->port); |
dfe42443 | 1494 | spin_lock(&port->lock); |
0690f41f | 1495 | return lsr; |
1da177e4 | 1496 | } |
3986fb2b | 1497 | EXPORT_SYMBOL_GPL(serial8250_rx_chars); |
1da177e4 | 1498 | |
3986fb2b | 1499 | void serial8250_tx_chars(struct uart_8250_port *up) |
1da177e4 | 1500 | { |
dfe42443 PG |
1501 | struct uart_port *port = &up->port; |
1502 | struct circ_buf *xmit = &port->state->xmit; | |
1da177e4 LT |
1503 | int count; |
1504 | ||
dfe42443 PG |
1505 | if (port->x_char) { |
1506 | serial_out(up, UART_TX, port->x_char); | |
1507 | port->icount.tx++; | |
1508 | port->x_char = 0; | |
1da177e4 LT |
1509 | return; |
1510 | } | |
dfe42443 PG |
1511 | if (uart_tx_stopped(port)) { |
1512 | serial8250_stop_tx(port); | |
b129a8cc RK |
1513 | return; |
1514 | } | |
1515 | if (uart_circ_empty(xmit)) { | |
e763b90c | 1516 | __stop_tx(up); |
1da177e4 LT |
1517 | return; |
1518 | } | |
1519 | ||
1520 | count = up->tx_loadsz; | |
1521 | do { | |
1522 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
1523 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
dfe42443 | 1524 | port->icount.tx++; |
1da177e4 LT |
1525 | if (uart_circ_empty(xmit)) |
1526 | break; | |
ebebd49a SH |
1527 | if (up->capabilities & UART_CAP_HFIFO) { |
1528 | if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) != | |
1529 | BOTH_EMPTY) | |
1530 | break; | |
1531 | } | |
1da177e4 LT |
1532 | } while (--count > 0); |
1533 | ||
1534 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
dfe42443 | 1535 | uart_write_wakeup(port); |
1da177e4 LT |
1536 | |
1537 | DEBUG_INTR("THRE..."); | |
1538 | ||
d74d5d1b | 1539 | /* |
6a529aba | 1540 | * With RPM enabled, we have to wait until the FIFO is empty before the |
d74d5d1b SAS |
1541 | * HW can go idle. So we get here once again with empty FIFO and disable |
1542 | * the interrupt and RPM in __stop_tx() | |
1543 | */ | |
1544 | if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM)) | |
e763b90c | 1545 | __stop_tx(up); |
1da177e4 | 1546 | } |
3986fb2b | 1547 | EXPORT_SYMBOL_GPL(serial8250_tx_chars); |
1da177e4 | 1548 | |
5435d20f | 1549 | /* Caller holds uart port lock */ |
3986fb2b | 1550 | unsigned int serial8250_modem_status(struct uart_8250_port *up) |
1da177e4 | 1551 | { |
dfe42443 | 1552 | struct uart_port *port = &up->port; |
2af7cd68 RK |
1553 | unsigned int status = serial_in(up, UART_MSR); |
1554 | ||
ad4c2aa6 CM |
1555 | status |= up->msr_saved_flags; |
1556 | up->msr_saved_flags = 0; | |
fdc30b3d | 1557 | if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && |
dfe42443 | 1558 | port->state != NULL) { |
2af7cd68 | 1559 | if (status & UART_MSR_TERI) |
dfe42443 | 1560 | port->icount.rng++; |
2af7cd68 | 1561 | if (status & UART_MSR_DDSR) |
dfe42443 | 1562 | port->icount.dsr++; |
2af7cd68 | 1563 | if (status & UART_MSR_DDCD) |
dfe42443 | 1564 | uart_handle_dcd_change(port, status & UART_MSR_DCD); |
2af7cd68 | 1565 | if (status & UART_MSR_DCTS) |
dfe42443 | 1566 | uart_handle_cts_change(port, status & UART_MSR_CTS); |
2af7cd68 | 1567 | |
dfe42443 | 1568 | wake_up_interruptible(&port->state->port.delta_msr_wait); |
2af7cd68 | 1569 | } |
1da177e4 | 1570 | |
2af7cd68 | 1571 | return status; |
1da177e4 | 1572 | } |
3986fb2b | 1573 | EXPORT_SYMBOL_GPL(serial8250_modem_status); |
1da177e4 LT |
1574 | |
1575 | /* | |
1576 | * This handles the interrupt from one port. | |
1577 | */ | |
86b21199 | 1578 | int serial8250_handle_irq(struct uart_port *port, unsigned int iir) |
1da177e4 | 1579 | { |
0690f41f | 1580 | unsigned char status; |
4bf3631c | 1581 | unsigned long flags; |
b1261c86 | 1582 | struct uart_8250_port *up = up_to_u8250p(port); |
9ee4b83e | 1583 | int dma_err = 0; |
86b21199 PG |
1584 | |
1585 | if (iir & UART_IIR_NO_INT) | |
1586 | return 0; | |
45e24601 | 1587 | |
dfe42443 | 1588 | spin_lock_irqsave(&port->lock, flags); |
45e24601 | 1589 | |
4fd996a1 | 1590 | status = serial_port_in(port, UART_LSR); |
1da177e4 LT |
1591 | |
1592 | DEBUG_INTR("status = %x...", status); | |
1593 | ||
9ee4b83e HK |
1594 | if (status & (UART_LSR_DR | UART_LSR_BI)) { |
1595 | if (up->dma) | |
f1a297bb | 1596 | dma_err = up->dma->rx_dma(up, iir); |
9ee4b83e HK |
1597 | |
1598 | if (!up->dma || dma_err) | |
1599 | status = serial8250_rx_chars(up, status); | |
1600 | } | |
3986fb2b | 1601 | serial8250_modem_status(up); |
b2202821 SAS |
1602 | if ((!up->dma || (up->dma && up->dma->tx_err)) && |
1603 | (status & UART_LSR_THRE)) | |
3986fb2b | 1604 | serial8250_tx_chars(up); |
45e24601 | 1605 | |
dfe42443 | 1606 | spin_unlock_irqrestore(&port->lock, flags); |
86b21199 | 1607 | return 1; |
583d28e9 | 1608 | } |
c7a1bdc5 | 1609 | EXPORT_SYMBOL_GPL(serial8250_handle_irq); |
583d28e9 JI |
1610 | |
1611 | static int serial8250_default_handle_irq(struct uart_port *port) | |
1612 | { | |
d74d5d1b SAS |
1613 | struct uart_8250_port *up = up_to_u8250p(port); |
1614 | unsigned int iir; | |
1615 | int ret; | |
1616 | ||
1617 | serial8250_rpm_get(up); | |
583d28e9 | 1618 | |
d74d5d1b SAS |
1619 | iir = serial_port_in(port, UART_IIR); |
1620 | ret = serial8250_handle_irq(port, iir); | |
1621 | ||
1622 | serial8250_rpm_put(up); | |
1623 | return ret; | |
583d28e9 JI |
1624 | } |
1625 | ||
dc96efb7 MS |
1626 | /* |
1627 | * These Exar UARTs have an extra interrupt indicator that could | |
1628 | * fire for a few unimplemented interrupts. One of which is a | |
1629 | * wakeup event when coming out of sleep. Put this here just | |
1630 | * to be on the safe side that these interrupts don't go unhandled. | |
1631 | */ | |
1632 | static int exar_handle_irq(struct uart_port *port) | |
1633 | { | |
1634 | unsigned char int0, int1, int2, int3; | |
1635 | unsigned int iir = serial_port_in(port, UART_IIR); | |
1636 | int ret; | |
1637 | ||
1638 | ret = serial8250_handle_irq(port, iir); | |
1639 | ||
30fa96a3 MS |
1640 | if ((port->type == PORT_XR17V35X) || |
1641 | (port->type == PORT_XR17D15X)) { | |
dc96efb7 MS |
1642 | int0 = serial_port_in(port, 0x80); |
1643 | int1 = serial_port_in(port, 0x81); | |
1644 | int2 = serial_port_in(port, 0x82); | |
1645 | int3 = serial_port_in(port, 0x83); | |
1646 | } | |
1647 | ||
1648 | return ret; | |
1649 | } | |
1650 | ||
1da177e4 LT |
1651 | /* |
1652 | * This is the serial driver's interrupt routine. | |
1653 | * | |
1654 | * Arjan thinks the old way was overly complex, so it got simplified. | |
1655 | * Alan disagrees, saying that need the complexity to handle the weird | |
1656 | * nature of ISA shared interrupts. (This is a special exception.) | |
1657 | * | |
1658 | * In order to handle ISA shared interrupts properly, we need to check | |
1659 | * that all ports have been serviced, and therefore the ISA interrupt | |
1660 | * line has been de-asserted. | |
1661 | * | |
1662 | * This means we need to loop through all ports. checking that they | |
1663 | * don't have an interrupt pending. | |
1664 | */ | |
7d12e780 | 1665 | static irqreturn_t serial8250_interrupt(int irq, void *dev_id) |
1da177e4 LT |
1666 | { |
1667 | struct irq_info *i = dev_id; | |
1668 | struct list_head *l, *end = NULL; | |
1669 | int pass_counter = 0, handled = 0; | |
1670 | ||
1671 | DEBUG_INTR("serial8250_interrupt(%d)...", irq); | |
1672 | ||
1673 | spin_lock(&i->lock); | |
1674 | ||
1675 | l = i->head; | |
1676 | do { | |
1677 | struct uart_8250_port *up; | |
583d28e9 | 1678 | struct uart_port *port; |
1da177e4 LT |
1679 | |
1680 | up = list_entry(l, struct uart_8250_port, list); | |
583d28e9 | 1681 | port = &up->port; |
1da177e4 | 1682 | |
49b532f9 | 1683 | if (port->handle_irq(port)) { |
1da177e4 | 1684 | handled = 1; |
1da177e4 LT |
1685 | end = NULL; |
1686 | } else if (end == NULL) | |
1687 | end = l; | |
1688 | ||
1689 | l = l->next; | |
1690 | ||
1691 | if (l == i->head && pass_counter++ > PASS_LIMIT) { | |
1692 | /* If we hit this, we're dead. */ | |
cd3ecad1 DD |
1693 | printk_ratelimited(KERN_ERR |
1694 | "serial8250: too much work for irq%d\n", irq); | |
1da177e4 LT |
1695 | break; |
1696 | } | |
1697 | } while (l != end); | |
1698 | ||
1699 | spin_unlock(&i->lock); | |
1700 | ||
1701 | DEBUG_INTR("end.\n"); | |
1702 | ||
1703 | return IRQ_RETVAL(handled); | |
1704 | } | |
1705 | ||
1706 | /* | |
1707 | * To support ISA shared interrupts, we need to have one interrupt | |
1708 | * handler that ensures that the IRQ line has been deasserted | |
1709 | * before returning. Failing to do this will result in the IRQ | |
1710 | * line being stuck active, and, since ISA irqs are edge triggered, | |
1711 | * no more IRQs will be seen. | |
1712 | */ | |
1713 | static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up) | |
1714 | { | |
1715 | spin_lock_irq(&i->lock); | |
1716 | ||
1717 | if (!list_empty(i->head)) { | |
1718 | if (i->head == &up->list) | |
1719 | i->head = i->head->next; | |
1720 | list_del(&up->list); | |
1721 | } else { | |
1722 | BUG_ON(i->head != &up->list); | |
1723 | i->head = NULL; | |
1724 | } | |
1da177e4 | 1725 | spin_unlock_irq(&i->lock); |
25db8ad5 AC |
1726 | /* List empty so throw away the hash node */ |
1727 | if (i->head == NULL) { | |
1728 | hlist_del(&i->node); | |
1729 | kfree(i); | |
1730 | } | |
1da177e4 LT |
1731 | } |
1732 | ||
1733 | static int serial_link_irq_chain(struct uart_8250_port *up) | |
1734 | { | |
25db8ad5 AC |
1735 | struct hlist_head *h; |
1736 | struct hlist_node *n; | |
1737 | struct irq_info *i; | |
40663cc7 | 1738 | int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0; |
1da177e4 | 1739 | |
25db8ad5 AC |
1740 | mutex_lock(&hash_mutex); |
1741 | ||
1742 | h = &irq_lists[up->port.irq % NR_IRQ_HASH]; | |
1743 | ||
1744 | hlist_for_each(n, h) { | |
1745 | i = hlist_entry(n, struct irq_info, node); | |
1746 | if (i->irq == up->port.irq) | |
1747 | break; | |
1748 | } | |
1749 | ||
1750 | if (n == NULL) { | |
1751 | i = kzalloc(sizeof(struct irq_info), GFP_KERNEL); | |
1752 | if (i == NULL) { | |
1753 | mutex_unlock(&hash_mutex); | |
1754 | return -ENOMEM; | |
1755 | } | |
1756 | spin_lock_init(&i->lock); | |
1757 | i->irq = up->port.irq; | |
1758 | hlist_add_head(&i->node, h); | |
1759 | } | |
1760 | mutex_unlock(&hash_mutex); | |
1761 | ||
1da177e4 LT |
1762 | spin_lock_irq(&i->lock); |
1763 | ||
1764 | if (i->head) { | |
1765 | list_add(&up->list, i->head); | |
1766 | spin_unlock_irq(&i->lock); | |
1767 | ||
1768 | ret = 0; | |
1769 | } else { | |
1770 | INIT_LIST_HEAD(&up->list); | |
1771 | i->head = &up->list; | |
1772 | spin_unlock_irq(&i->lock); | |
1c2f0493 | 1773 | irq_flags |= up->port.irqflags; |
1da177e4 LT |
1774 | ret = request_irq(up->port.irq, serial8250_interrupt, |
1775 | irq_flags, "serial", i); | |
1776 | if (ret < 0) | |
1777 | serial_do_unlink(i, up); | |
1778 | } | |
1779 | ||
1780 | return ret; | |
1781 | } | |
1782 | ||
1783 | static void serial_unlink_irq_chain(struct uart_8250_port *up) | |
1784 | { | |
bd2fe272 PG |
1785 | /* |
1786 | * yes, some broken gcc emit "warning: 'i' may be used uninitialized" | |
1787 | * but no, we are not going to take a patch that assigns NULL below. | |
1788 | */ | |
25db8ad5 AC |
1789 | struct irq_info *i; |
1790 | struct hlist_node *n; | |
1791 | struct hlist_head *h; | |
1da177e4 | 1792 | |
25db8ad5 AC |
1793 | mutex_lock(&hash_mutex); |
1794 | ||
1795 | h = &irq_lists[up->port.irq % NR_IRQ_HASH]; | |
1796 | ||
1797 | hlist_for_each(n, h) { | |
1798 | i = hlist_entry(n, struct irq_info, node); | |
1799 | if (i->irq == up->port.irq) | |
1800 | break; | |
1801 | } | |
1802 | ||
1803 | BUG_ON(n == NULL); | |
1da177e4 LT |
1804 | BUG_ON(i->head == NULL); |
1805 | ||
1806 | if (list_empty(i->head)) | |
1807 | free_irq(up->port.irq, i); | |
1808 | ||
1809 | serial_do_unlink(i, up); | |
25db8ad5 | 1810 | mutex_unlock(&hash_mutex); |
1da177e4 LT |
1811 | } |
1812 | ||
1813 | /* | |
1814 | * This function is used to handle ports that do not have an | |
1815 | * interrupt. This doesn't work very well for 16450's, but gives | |
1816 | * barely passable results for a 16550A. (Although at the expense | |
1817 | * of much CPU overhead). | |
1818 | */ | |
1819 | static void serial8250_timeout(unsigned long data) | |
1820 | { | |
1821 | struct uart_8250_port *up = (struct uart_8250_port *)data; | |
1da177e4 | 1822 | |
a0431476 | 1823 | up->port.handle_irq(&up->port); |
54381067 | 1824 | mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port)); |
40b36daa AW |
1825 | } |
1826 | ||
1827 | static void serial8250_backup_timeout(unsigned long data) | |
1828 | { | |
1829 | struct uart_8250_port *up = (struct uart_8250_port *)data; | |
ad4c2aa6 CM |
1830 | unsigned int iir, ier = 0, lsr; |
1831 | unsigned long flags; | |
40b36daa | 1832 | |
dbb3b1ca AC |
1833 | spin_lock_irqsave(&up->port.lock, flags); |
1834 | ||
40b36daa AW |
1835 | /* |
1836 | * Must disable interrupts or else we risk racing with the interrupt | |
1837 | * based handler. | |
1838 | */ | |
d4e33fac | 1839 | if (up->port.irq) { |
40b36daa AW |
1840 | ier = serial_in(up, UART_IER); |
1841 | serial_out(up, UART_IER, 0); | |
1842 | } | |
1da177e4 | 1843 | |
40b36daa AW |
1844 | iir = serial_in(up, UART_IIR); |
1845 | ||
1846 | /* | |
1847 | * This should be a safe test for anyone who doesn't trust the | |
1848 | * IIR bits on their UART, but it's specifically designed for | |
1849 | * the "Diva" UART used on the management processor on many HP | |
1850 | * ia64 and parisc boxes. | |
1851 | */ | |
ad4c2aa6 CM |
1852 | lsr = serial_in(up, UART_LSR); |
1853 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; | |
40b36daa | 1854 | if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) && |
ebd2c8f6 | 1855 | (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) && |
ad4c2aa6 | 1856 | (lsr & UART_LSR_THRE)) { |
40b36daa AW |
1857 | iir &= ~(UART_IIR_ID | UART_IIR_NO_INT); |
1858 | iir |= UART_IIR_THRI; | |
1859 | } | |
1860 | ||
1861 | if (!(iir & UART_IIR_NO_INT)) | |
3986fb2b | 1862 | serial8250_tx_chars(up); |
40b36daa | 1863 | |
d4e33fac | 1864 | if (up->port.irq) |
40b36daa AW |
1865 | serial_out(up, UART_IER, ier); |
1866 | ||
dbb3b1ca AC |
1867 | spin_unlock_irqrestore(&up->port.lock, flags); |
1868 | ||
40b36daa | 1869 | /* Standard timer interval plus 0.2s to keep the port running */ |
6f803cd0 | 1870 | mod_timer(&up->timer, |
54381067 | 1871 | jiffies + uart_poll_timeout(&up->port) + HZ / 5); |
1da177e4 LT |
1872 | } |
1873 | ||
1874 | static unsigned int serial8250_tx_empty(struct uart_port *port) | |
1875 | { | |
b1261c86 | 1876 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 | 1877 | unsigned long flags; |
ad4c2aa6 | 1878 | unsigned int lsr; |
1da177e4 | 1879 | |
d74d5d1b SAS |
1880 | serial8250_rpm_get(up); |
1881 | ||
dfe42443 | 1882 | spin_lock_irqsave(&port->lock, flags); |
4fd996a1 | 1883 | lsr = serial_port_in(port, UART_LSR); |
ad4c2aa6 | 1884 | up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; |
dfe42443 | 1885 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 | 1886 | |
d74d5d1b SAS |
1887 | serial8250_rpm_put(up); |
1888 | ||
bca47613 | 1889 | return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0; |
1da177e4 LT |
1890 | } |
1891 | ||
1892 | static unsigned int serial8250_get_mctrl(struct uart_port *port) | |
1893 | { | |
b1261c86 | 1894 | struct uart_8250_port *up = up_to_u8250p(port); |
2af7cd68 | 1895 | unsigned int status; |
1da177e4 LT |
1896 | unsigned int ret; |
1897 | ||
d74d5d1b | 1898 | serial8250_rpm_get(up); |
3986fb2b | 1899 | status = serial8250_modem_status(up); |
d74d5d1b | 1900 | serial8250_rpm_put(up); |
1da177e4 LT |
1901 | |
1902 | ret = 0; | |
1903 | if (status & UART_MSR_DCD) | |
1904 | ret |= TIOCM_CAR; | |
1905 | if (status & UART_MSR_RI) | |
1906 | ret |= TIOCM_RNG; | |
1907 | if (status & UART_MSR_DSR) | |
1908 | ret |= TIOCM_DSR; | |
1909 | if (status & UART_MSR_CTS) | |
1910 | ret |= TIOCM_CTS; | |
1911 | return ret; | |
1912 | } | |
1913 | ||
1914 | static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1915 | { | |
b1261c86 | 1916 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 LT |
1917 | unsigned char mcr = 0; |
1918 | ||
1919 | if (mctrl & TIOCM_RTS) | |
1920 | mcr |= UART_MCR_RTS; | |
1921 | if (mctrl & TIOCM_DTR) | |
1922 | mcr |= UART_MCR_DTR; | |
1923 | if (mctrl & TIOCM_OUT1) | |
1924 | mcr |= UART_MCR_OUT1; | |
1925 | if (mctrl & TIOCM_OUT2) | |
1926 | mcr |= UART_MCR_OUT2; | |
1927 | if (mctrl & TIOCM_LOOP) | |
1928 | mcr |= UART_MCR_LOOP; | |
1929 | ||
1930 | mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr; | |
1931 | ||
4fd996a1 | 1932 | serial_port_out(port, UART_MCR, mcr); |
1da177e4 LT |
1933 | } |
1934 | ||
1935 | static void serial8250_break_ctl(struct uart_port *port, int break_state) | |
1936 | { | |
b1261c86 | 1937 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 LT |
1938 | unsigned long flags; |
1939 | ||
d74d5d1b | 1940 | serial8250_rpm_get(up); |
dfe42443 | 1941 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 LT |
1942 | if (break_state == -1) |
1943 | up->lcr |= UART_LCR_SBC; | |
1944 | else | |
1945 | up->lcr &= ~UART_LCR_SBC; | |
4fd996a1 | 1946 | serial_port_out(port, UART_LCR, up->lcr); |
dfe42443 | 1947 | spin_unlock_irqrestore(&port->lock, flags); |
d74d5d1b | 1948 | serial8250_rpm_put(up); |
1da177e4 LT |
1949 | } |
1950 | ||
40b36daa AW |
1951 | /* |
1952 | * Wait for transmitter & holding register to empty | |
1953 | */ | |
b5d674ab | 1954 | static void wait_for_xmitr(struct uart_8250_port *up, int bits) |
40b36daa AW |
1955 | { |
1956 | unsigned int status, tmout = 10000; | |
1957 | ||
1958 | /* Wait up to 10ms for the character(s) to be sent. */ | |
97d303b7 | 1959 | for (;;) { |
40b36daa AW |
1960 | status = serial_in(up, UART_LSR); |
1961 | ||
ad4c2aa6 | 1962 | up->lsr_saved_flags |= status & LSR_SAVE_FLAGS; |
40b36daa | 1963 | |
97d303b7 DD |
1964 | if ((status & bits) == bits) |
1965 | break; | |
40b36daa AW |
1966 | if (--tmout == 0) |
1967 | break; | |
1968 | udelay(1); | |
97d303b7 | 1969 | } |
40b36daa AW |
1970 | |
1971 | /* Wait up to 1s for flow control if necessary */ | |
1972 | if (up->port.flags & UPF_CONS_FLOW) { | |
ad4c2aa6 CM |
1973 | unsigned int tmout; |
1974 | for (tmout = 1000000; tmout; tmout--) { | |
1975 | unsigned int msr = serial_in(up, UART_MSR); | |
1976 | up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; | |
1977 | if (msr & UART_MSR_CTS) | |
1978 | break; | |
40b36daa AW |
1979 | udelay(1); |
1980 | touch_nmi_watchdog(); | |
1981 | } | |
1982 | } | |
1983 | } | |
1984 | ||
f2d937f3 JW |
1985 | #ifdef CONFIG_CONSOLE_POLL |
1986 | /* | |
1987 | * Console polling routines for writing and reading from the uart while | |
1988 | * in an interrupt or debug context. | |
1989 | */ | |
1990 | ||
1991 | static int serial8250_get_poll_char(struct uart_port *port) | |
1992 | { | |
d74d5d1b SAS |
1993 | struct uart_8250_port *up = up_to_u8250p(port); |
1994 | unsigned char lsr; | |
1995 | int status; | |
f2d937f3 | 1996 | |
d74d5d1b | 1997 | serial8250_rpm_get(up); |
f2d937f3 | 1998 | |
d74d5d1b | 1999 | lsr = serial_port_in(port, UART_LSR); |
f2d937f3 | 2000 | |
d74d5d1b SAS |
2001 | if (!(lsr & UART_LSR_DR)) { |
2002 | status = NO_POLL_CHAR; | |
2003 | goto out; | |
2004 | } | |
f2d937f3 | 2005 | |
d74d5d1b SAS |
2006 | status = serial_port_in(port, UART_RX); |
2007 | out: | |
2008 | serial8250_rpm_put(up); | |
2009 | return status; | |
f2d937f3 JW |
2010 | } |
2011 | ||
2012 | ||
2013 | static void serial8250_put_poll_char(struct uart_port *port, | |
2014 | unsigned char c) | |
2015 | { | |
2016 | unsigned int ier; | |
b1261c86 | 2017 | struct uart_8250_port *up = up_to_u8250p(port); |
f2d937f3 | 2018 | |
d74d5d1b | 2019 | serial8250_rpm_get(up); |
f2d937f3 JW |
2020 | /* |
2021 | * First save the IER then disable the interrupts | |
2022 | */ | |
4fd996a1 | 2023 | ier = serial_port_in(port, UART_IER); |
f2d937f3 | 2024 | if (up->capabilities & UART_CAP_UUE) |
4fd996a1 | 2025 | serial_port_out(port, UART_IER, UART_IER_UUE); |
f2d937f3 | 2026 | else |
4fd996a1 | 2027 | serial_port_out(port, UART_IER, 0); |
f2d937f3 JW |
2028 | |
2029 | wait_for_xmitr(up, BOTH_EMPTY); | |
2030 | /* | |
2031 | * Send the character out. | |
f2d937f3 | 2032 | */ |
4fd996a1 | 2033 | serial_port_out(port, UART_TX, c); |
f2d937f3 JW |
2034 | |
2035 | /* | |
2036 | * Finally, wait for transmitter to become empty | |
2037 | * and restore the IER | |
2038 | */ | |
2039 | wait_for_xmitr(up, BOTH_EMPTY); | |
4fd996a1 | 2040 | serial_port_out(port, UART_IER, ier); |
d74d5d1b | 2041 | serial8250_rpm_put(up); |
f2d937f3 JW |
2042 | } |
2043 | ||
2044 | #endif /* CONFIG_CONSOLE_POLL */ | |
2045 | ||
b99b121b | 2046 | int serial8250_do_startup(struct uart_port *port) |
1da177e4 | 2047 | { |
b1261c86 | 2048 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 | 2049 | unsigned long flags; |
55d3b282 | 2050 | unsigned char lsr, iir; |
1da177e4 LT |
2051 | int retval; |
2052 | ||
65ecc9c0 SY |
2053 | if (port->type == PORT_8250_CIR) |
2054 | return -ENODEV; | |
2055 | ||
9660497c HK |
2056 | if (!port->fifosize) |
2057 | port->fifosize = uart_config[port->type].fifo_size; | |
2058 | if (!up->tx_loadsz) | |
2059 | up->tx_loadsz = uart_config[port->type].tx_loadsz; | |
2060 | if (!up->capabilities) | |
2061 | up->capabilities = uart_config[port->type].flags; | |
1da177e4 LT |
2062 | up->mcr = 0; |
2063 | ||
dfe42443 | 2064 | if (port->iotype != up->cur_iotype) |
b8e7e40a AC |
2065 | set_io_from_upio(port); |
2066 | ||
d74d5d1b | 2067 | serial8250_rpm_get(up); |
dfe42443 | 2068 | if (port->type == PORT_16C950) { |
1da177e4 LT |
2069 | /* Wake up and initialize UART */ |
2070 | up->acr = 0; | |
4fd996a1 PG |
2071 | serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); |
2072 | serial_port_out(port, UART_EFR, UART_EFR_ECB); | |
2073 | serial_port_out(port, UART_IER, 0); | |
2074 | serial_port_out(port, UART_LCR, 0); | |
1da177e4 | 2075 | serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ |
4fd996a1 PG |
2076 | serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); |
2077 | serial_port_out(port, UART_EFR, UART_EFR_ECB); | |
2078 | serial_port_out(port, UART_LCR, 0); | |
1da177e4 LT |
2079 | } |
2080 | ||
2081 | #ifdef CONFIG_SERIAL_8250_RSA | |
2082 | /* | |
2083 | * If this is an RSA port, see if we can kick it up to the | |
2084 | * higher speed clock. | |
2085 | */ | |
2086 | enable_rsa(up); | |
2087 | #endif | |
1da177e4 LT |
2088 | /* |
2089 | * Clear the FIFO buffers and disable them. | |
7f927fcc | 2090 | * (they will be reenabled in set_termios()) |
1da177e4 LT |
2091 | */ |
2092 | serial8250_clear_fifos(up); | |
2093 | ||
2094 | /* | |
2095 | * Clear the interrupt registers. | |
2096 | */ | |
0aa525d1 SAS |
2097 | if (serial_port_in(port, UART_LSR) & UART_LSR_DR) |
2098 | serial_port_in(port, UART_RX); | |
4fd996a1 PG |
2099 | serial_port_in(port, UART_IIR); |
2100 | serial_port_in(port, UART_MSR); | |
1da177e4 LT |
2101 | |
2102 | /* | |
2103 | * At this point, there's no way the LSR could still be 0xff; | |
2104 | * if it is, then bail out, because there's likely no UART | |
2105 | * here. | |
2106 | */ | |
dfe42443 | 2107 | if (!(port->flags & UPF_BUGGY_UART) && |
4fd996a1 | 2108 | (serial_port_in(port, UART_LSR) == 0xff)) { |
7808a4c4 | 2109 | printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n", |
dfe42443 | 2110 | serial_index(port)); |
d74d5d1b SAS |
2111 | retval = -ENODEV; |
2112 | goto out; | |
1da177e4 LT |
2113 | } |
2114 | ||
2115 | /* | |
2116 | * For a XR16C850, we need to set the trigger levels | |
2117 | */ | |
dfe42443 | 2118 | if (port->type == PORT_16850) { |
1da177e4 LT |
2119 | unsigned char fctr; |
2120 | ||
0acf519f | 2121 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
1da177e4 | 2122 | |
0acf519f | 2123 | fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX); |
4fd996a1 PG |
2124 | serial_port_out(port, UART_FCTR, |
2125 | fctr | UART_FCTR_TRGD | UART_FCTR_RX); | |
2126 | serial_port_out(port, UART_TRG, UART_TRG_96); | |
2127 | serial_port_out(port, UART_FCTR, | |
2128 | fctr | UART_FCTR_TRGD | UART_FCTR_TX); | |
2129 | serial_port_out(port, UART_TRG, UART_TRG_96); | |
1da177e4 | 2130 | |
4fd996a1 | 2131 | serial_port_out(port, UART_LCR, 0); |
1da177e4 LT |
2132 | } |
2133 | ||
dfe42443 | 2134 | if (port->irq) { |
01c194d9 | 2135 | unsigned char iir1; |
40b36daa AW |
2136 | /* |
2137 | * Test for UARTs that do not reassert THRE when the | |
2138 | * transmitter is idle and the interrupt has already | |
2139 | * been cleared. Real 16550s should always reassert | |
2140 | * this interrupt whenever the transmitter is idle and | |
2141 | * the interrupt is enabled. Delays are necessary to | |
2142 | * allow register changes to become visible. | |
2143 | */ | |
dfe42443 | 2144 | spin_lock_irqsave(&port->lock, flags); |
1c2f0493 | 2145 | if (up->port.irqflags & IRQF_SHARED) |
dfe42443 | 2146 | disable_irq_nosync(port->irq); |
40b36daa AW |
2147 | |
2148 | wait_for_xmitr(up, UART_LSR_THRE); | |
55e4016d | 2149 | serial_port_out_sync(port, UART_IER, UART_IER_THRI); |
40b36daa | 2150 | udelay(1); /* allow THRE to set */ |
4fd996a1 PG |
2151 | iir1 = serial_port_in(port, UART_IIR); |
2152 | serial_port_out(port, UART_IER, 0); | |
55e4016d | 2153 | serial_port_out_sync(port, UART_IER, UART_IER_THRI); |
40b36daa | 2154 | udelay(1); /* allow a working UART time to re-assert THRE */ |
4fd996a1 PG |
2155 | iir = serial_port_in(port, UART_IIR); |
2156 | serial_port_out(port, UART_IER, 0); | |
40b36daa | 2157 | |
dfe42443 PG |
2158 | if (port->irqflags & IRQF_SHARED) |
2159 | enable_irq(port->irq); | |
2160 | spin_unlock_irqrestore(&port->lock, flags); | |
40b36daa AW |
2161 | |
2162 | /* | |
bc02d15a DW |
2163 | * If the interrupt is not reasserted, or we otherwise |
2164 | * don't trust the iir, setup a timer to kick the UART | |
2165 | * on a regular basis. | |
40b36daa | 2166 | */ |
bc02d15a DW |
2167 | if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) || |
2168 | up->port.flags & UPF_BUG_THRE) { | |
363f66fe | 2169 | up->bugs |= UART_BUG_THRE; |
8440838b DM |
2170 | pr_debug("ttyS%d - using backup timer\n", |
2171 | serial_index(port)); | |
40b36daa AW |
2172 | } |
2173 | } | |
2174 | ||
363f66fe WN |
2175 | /* |
2176 | * The above check will only give an accurate result the first time | |
2177 | * the port is opened so this value needs to be preserved. | |
2178 | */ | |
2179 | if (up->bugs & UART_BUG_THRE) { | |
2180 | up->timer.function = serial8250_backup_timeout; | |
2181 | up->timer.data = (unsigned long)up; | |
2182 | mod_timer(&up->timer, jiffies + | |
54381067 | 2183 | uart_poll_timeout(port) + HZ / 5); |
363f66fe WN |
2184 | } |
2185 | ||
1da177e4 LT |
2186 | /* |
2187 | * If the "interrupt" for this port doesn't correspond with any | |
2188 | * hardware interrupt, we use a timer-based system. The original | |
2189 | * driver used to do this with IRQ0. | |
2190 | */ | |
dfe42443 | 2191 | if (!port->irq) { |
1da177e4 | 2192 | up->timer.data = (unsigned long)up; |
54381067 | 2193 | mod_timer(&up->timer, jiffies + uart_poll_timeout(port)); |
1da177e4 LT |
2194 | } else { |
2195 | retval = serial_link_irq_chain(up); | |
2196 | if (retval) | |
d74d5d1b | 2197 | goto out; |
1da177e4 LT |
2198 | } |
2199 | ||
2200 | /* | |
2201 | * Now, initialize the UART | |
2202 | */ | |
4fd996a1 | 2203 | serial_port_out(port, UART_LCR, UART_LCR_WLEN8); |
1da177e4 | 2204 | |
dfe42443 | 2205 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 | 2206 | if (up->port.flags & UPF_FOURPORT) { |
d4e33fac | 2207 | if (!up->port.irq) |
1da177e4 LT |
2208 | up->port.mctrl |= TIOCM_OUT1; |
2209 | } else | |
2210 | /* | |
2211 | * Most PC uarts need OUT2 raised to enable interrupts. | |
2212 | */ | |
dfe42443 | 2213 | if (port->irq) |
1da177e4 LT |
2214 | up->port.mctrl |= TIOCM_OUT2; |
2215 | ||
dfe42443 | 2216 | serial8250_set_mctrl(port, port->mctrl); |
55d3b282 | 2217 | |
b6adea33 MCC |
2218 | /* Serial over Lan (SoL) hack: |
2219 | Intel 8257x Gigabit ethernet chips have a | |
2220 | 16550 emulation, to be used for Serial Over Lan. | |
2221 | Those chips take a longer time than a normal | |
2222 | serial device to signalize that a transmission | |
2223 | data was queued. Due to that, the above test generally | |
2224 | fails. One solution would be to delay the reading of | |
2225 | iir. However, this is not reliable, since the timeout | |
2226 | is variable. So, let's just don't test if we receive | |
2227 | TX irq. This way, we'll never enable UART_BUG_TXEN. | |
2228 | */ | |
d41a4b51 | 2229 | if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST) |
b6adea33 MCC |
2230 | goto dont_test_tx_en; |
2231 | ||
55d3b282 RK |
2232 | /* |
2233 | * Do a quick test to see if we receive an | |
2234 | * interrupt when we enable the TX irq. | |
2235 | */ | |
4fd996a1 PG |
2236 | serial_port_out(port, UART_IER, UART_IER_THRI); |
2237 | lsr = serial_port_in(port, UART_LSR); | |
2238 | iir = serial_port_in(port, UART_IIR); | |
2239 | serial_port_out(port, UART_IER, 0); | |
55d3b282 RK |
2240 | |
2241 | if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) { | |
67f7654e RK |
2242 | if (!(up->bugs & UART_BUG_TXEN)) { |
2243 | up->bugs |= UART_BUG_TXEN; | |
55d3b282 | 2244 | pr_debug("ttyS%d - enabling bad tx status workarounds\n", |
8440838b | 2245 | serial_index(port)); |
55d3b282 RK |
2246 | } |
2247 | } else { | |
67f7654e | 2248 | up->bugs &= ~UART_BUG_TXEN; |
55d3b282 RK |
2249 | } |
2250 | ||
b6adea33 | 2251 | dont_test_tx_en: |
dfe42443 | 2252 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 | 2253 | |
ad4c2aa6 CM |
2254 | /* |
2255 | * Clear the interrupt registers again for luck, and clear the | |
2256 | * saved flags to avoid getting false values from polling | |
2257 | * routines or the previous session. | |
2258 | */ | |
0aa525d1 SAS |
2259 | if (serial_port_in(port, UART_LSR) & UART_LSR_DR) |
2260 | serial_port_in(port, UART_RX); | |
4fd996a1 PG |
2261 | serial_port_in(port, UART_IIR); |
2262 | serial_port_in(port, UART_MSR); | |
ad4c2aa6 CM |
2263 | up->lsr_saved_flags = 0; |
2264 | up->msr_saved_flags = 0; | |
2265 | ||
9ee4b83e HK |
2266 | /* |
2267 | * Request DMA channels for both RX and TX. | |
2268 | */ | |
2269 | if (up->dma) { | |
2270 | retval = serial8250_request_dma(up); | |
2271 | if (retval) { | |
2272 | pr_warn_ratelimited("ttyS%d - failed to request DMA\n", | |
2273 | serial_index(port)); | |
2274 | up->dma = NULL; | |
2275 | } | |
2276 | } | |
2277 | ||
1da177e4 LT |
2278 | /* |
2279 | * Finally, enable interrupts. Note: Modem status interrupts | |
2280 | * are set via set_termios(), which will be occurring imminently | |
2281 | * anyway, so we don't enable them here. | |
2282 | */ | |
2283 | up->ier = UART_IER_RLSI | UART_IER_RDI; | |
4fd996a1 | 2284 | serial_port_out(port, UART_IER, up->ier); |
1da177e4 | 2285 | |
dfe42443 | 2286 | if (port->flags & UPF_FOURPORT) { |
1da177e4 LT |
2287 | unsigned int icp; |
2288 | /* | |
2289 | * Enable interrupts on the AST Fourport board | |
2290 | */ | |
dfe42443 | 2291 | icp = (port->iobase & 0xfe0) | 0x01f; |
1da177e4 | 2292 | outb_p(0x80, icp); |
0d263a26 | 2293 | inb_p(icp); |
1da177e4 | 2294 | } |
d74d5d1b SAS |
2295 | retval = 0; |
2296 | out: | |
2297 | serial8250_rpm_put(up); | |
2298 | return retval; | |
1da177e4 | 2299 | } |
b99b121b | 2300 | EXPORT_SYMBOL_GPL(serial8250_do_startup); |
1da177e4 | 2301 | |
b99b121b SAS |
2302 | static int serial8250_startup(struct uart_port *port) |
2303 | { | |
2304 | if (port->startup) | |
2305 | return port->startup(port); | |
2306 | return serial8250_do_startup(port); | |
1da177e4 LT |
2307 | } |
2308 | ||
b99b121b | 2309 | void serial8250_do_shutdown(struct uart_port *port) |
1da177e4 | 2310 | { |
b1261c86 | 2311 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 LT |
2312 | unsigned long flags; |
2313 | ||
d74d5d1b | 2314 | serial8250_rpm_get(up); |
1da177e4 LT |
2315 | /* |
2316 | * Disable interrupts from this port | |
2317 | */ | |
2318 | up->ier = 0; | |
4fd996a1 | 2319 | serial_port_out(port, UART_IER, 0); |
1da177e4 | 2320 | |
9ee4b83e HK |
2321 | if (up->dma) |
2322 | serial8250_release_dma(up); | |
2323 | ||
dfe42443 PG |
2324 | spin_lock_irqsave(&port->lock, flags); |
2325 | if (port->flags & UPF_FOURPORT) { | |
1da177e4 | 2326 | /* reset interrupts on the AST Fourport board */ |
dfe42443 PG |
2327 | inb((port->iobase & 0xfe0) | 0x1f); |
2328 | port->mctrl |= TIOCM_OUT1; | |
1da177e4 | 2329 | } else |
dfe42443 | 2330 | port->mctrl &= ~TIOCM_OUT2; |
1da177e4 | 2331 | |
dfe42443 PG |
2332 | serial8250_set_mctrl(port, port->mctrl); |
2333 | spin_unlock_irqrestore(&port->lock, flags); | |
1da177e4 LT |
2334 | |
2335 | /* | |
2336 | * Disable break condition and FIFOs | |
2337 | */ | |
4fd996a1 PG |
2338 | serial_port_out(port, UART_LCR, |
2339 | serial_port_in(port, UART_LCR) & ~UART_LCR_SBC); | |
1da177e4 LT |
2340 | serial8250_clear_fifos(up); |
2341 | ||
2342 | #ifdef CONFIG_SERIAL_8250_RSA | |
2343 | /* | |
2344 | * Reset the RSA board back to 115kbps compat mode. | |
2345 | */ | |
2346 | disable_rsa(up); | |
2347 | #endif | |
2348 | ||
2349 | /* | |
2350 | * Read data port to reset things, and then unlink from | |
2351 | * the IRQ chain. | |
2352 | */ | |
0aa525d1 SAS |
2353 | if (serial_port_in(port, UART_LSR) & UART_LSR_DR) |
2354 | serial_port_in(port, UART_RX); | |
d74d5d1b | 2355 | serial8250_rpm_put(up); |
1da177e4 | 2356 | |
40b36daa AW |
2357 | del_timer_sync(&up->timer); |
2358 | up->timer.function = serial8250_timeout; | |
dfe42443 | 2359 | if (port->irq) |
1da177e4 LT |
2360 | serial_unlink_irq_chain(up); |
2361 | } | |
b99b121b SAS |
2362 | EXPORT_SYMBOL_GPL(serial8250_do_shutdown); |
2363 | ||
2364 | static void serial8250_shutdown(struct uart_port *port) | |
2365 | { | |
2366 | if (port->shutdown) | |
2367 | port->shutdown(port); | |
2368 | else | |
2369 | serial8250_do_shutdown(port); | |
2370 | } | |
1da177e4 LT |
2371 | |
2372 | static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud) | |
2373 | { | |
2374 | unsigned int quot; | |
2375 | ||
2376 | /* | |
2377 | * Handle magic divisors for baud rates above baud_base on | |
2378 | * SMSC SuperIO chips. | |
2379 | */ | |
2380 | if ((port->flags & UPF_MAGIC_MULTIPLIER) && | |
2381 | baud == (port->uartclk/4)) | |
2382 | quot = 0x8001; | |
2383 | else if ((port->flags & UPF_MAGIC_MULTIPLIER) && | |
2384 | baud == (port->uartclk/8)) | |
2385 | quot = 0x8002; | |
2386 | else | |
2387 | quot = uart_get_divisor(port, baud); | |
2388 | ||
2389 | return quot; | |
2390 | } | |
2391 | ||
235dae5d PL |
2392 | void |
2393 | serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios, | |
2394 | struct ktermios *old) | |
1da177e4 | 2395 | { |
b1261c86 | 2396 | struct uart_8250_port *up = up_to_u8250p(port); |
aef9a7bd | 2397 | unsigned char cval; |
1da177e4 LT |
2398 | unsigned long flags; |
2399 | unsigned int baud, quot; | |
2400 | ||
2401 | switch (termios->c_cflag & CSIZE) { | |
2402 | case CS5: | |
0a8b80c5 | 2403 | cval = UART_LCR_WLEN5; |
1da177e4 LT |
2404 | break; |
2405 | case CS6: | |
0a8b80c5 | 2406 | cval = UART_LCR_WLEN6; |
1da177e4 LT |
2407 | break; |
2408 | case CS7: | |
0a8b80c5 | 2409 | cval = UART_LCR_WLEN7; |
1da177e4 LT |
2410 | break; |
2411 | default: | |
2412 | case CS8: | |
0a8b80c5 | 2413 | cval = UART_LCR_WLEN8; |
1da177e4 LT |
2414 | break; |
2415 | } | |
2416 | ||
2417 | if (termios->c_cflag & CSTOPB) | |
0a8b80c5 | 2418 | cval |= UART_LCR_STOP; |
eb26dfe8 | 2419 | if (termios->c_cflag & PARENB) { |
1da177e4 | 2420 | cval |= UART_LCR_PARITY; |
eb26dfe8 | 2421 | if (up->bugs & UART_BUG_PARITY) |
aef9a7bd | 2422 | up->fifo_bug = true; |
eb26dfe8 | 2423 | } |
1da177e4 LT |
2424 | if (!(termios->c_cflag & PARODD)) |
2425 | cval |= UART_LCR_EPAR; | |
2426 | #ifdef CMSPAR | |
2427 | if (termios->c_cflag & CMSPAR) | |
2428 | cval |= UART_LCR_SPAR; | |
2429 | #endif | |
2430 | ||
2431 | /* | |
2432 | * Ask the core to calculate the divisor for us. | |
2433 | */ | |
24d481ec AV |
2434 | baud = uart_get_baud_rate(port, termios, old, |
2435 | port->uartclk / 16 / 0xffff, | |
2436 | port->uartclk / 16); | |
1da177e4 LT |
2437 | quot = serial8250_get_divisor(port, baud); |
2438 | ||
2439 | /* | |
4ba5e35d | 2440 | * Oxford Semi 952 rev B workaround |
1da177e4 | 2441 | */ |
4ba5e35d | 2442 | if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0) |
3e8d4e20 | 2443 | quot++; |
1da177e4 | 2444 | |
dfe42443 | 2445 | if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) { |
aef9a7bd YY |
2446 | /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */ |
2447 | if ((baud < 2400 && !up->dma) || up->fifo_bug) { | |
2448 | up->fcr &= ~UART_FCR_TRIGGER_MASK; | |
2449 | up->fcr |= UART_FCR_TRIGGER_1; | |
f9a9111b | 2450 | } |
1da177e4 LT |
2451 | } |
2452 | ||
2453 | /* | |
2454 | * MCR-based auto flow control. When AFE is enabled, RTS will be | |
2455 | * deasserted when the receive FIFO contains more characters than | |
2456 | * the trigger, or the MCR RTS bit is cleared. In the case where | |
2457 | * the remote UART is not using CTS auto flow control, we must | |
2458 | * have sufficient FIFO entries for the latency of the remote | |
a6eec92e | 2459 | * UART to respond. IOW, at least 32 bytes of FIFO. |
1da177e4 | 2460 | */ |
a6eec92e | 2461 | if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) { |
1da177e4 LT |
2462 | up->mcr &= ~UART_MCR_AFE; |
2463 | if (termios->c_cflag & CRTSCTS) | |
2464 | up->mcr |= UART_MCR_AFE; | |
2465 | } | |
2466 | ||
2467 | /* | |
2468 | * Ok, we're now changing the port state. Do it with | |
2469 | * interrupts disabled. | |
2470 | */ | |
d74d5d1b | 2471 | serial8250_rpm_get(up); |
dfe42443 | 2472 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 LT |
2473 | |
2474 | /* | |
2475 | * Update the per-port timeout. | |
2476 | */ | |
2477 | uart_update_timeout(port, termios->c_cflag, baud); | |
2478 | ||
dfe42443 | 2479 | port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; |
1da177e4 | 2480 | if (termios->c_iflag & INPCK) |
dfe42443 | 2481 | port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; |
ef8b9ddc | 2482 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
dfe42443 | 2483 | port->read_status_mask |= UART_LSR_BI; |
1da177e4 LT |
2484 | |
2485 | /* | |
2486 | * Characteres to ignore | |
2487 | */ | |
dfe42443 | 2488 | port->ignore_status_mask = 0; |
1da177e4 | 2489 | if (termios->c_iflag & IGNPAR) |
dfe42443 | 2490 | port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; |
1da177e4 | 2491 | if (termios->c_iflag & IGNBRK) { |
dfe42443 | 2492 | port->ignore_status_mask |= UART_LSR_BI; |
1da177e4 LT |
2493 | /* |
2494 | * If we're ignoring parity and break indicators, | |
2495 | * ignore overruns too (for real raw support). | |
2496 | */ | |
2497 | if (termios->c_iflag & IGNPAR) | |
dfe42443 | 2498 | port->ignore_status_mask |= UART_LSR_OE; |
1da177e4 LT |
2499 | } |
2500 | ||
2501 | /* | |
2502 | * ignore all characters if CREAD is not set | |
2503 | */ | |
2504 | if ((termios->c_cflag & CREAD) == 0) | |
dfe42443 | 2505 | port->ignore_status_mask |= UART_LSR_DR; |
1da177e4 LT |
2506 | |
2507 | /* | |
2508 | * CTS flow control flag and modem status interrupts | |
2509 | */ | |
f8b372a1 | 2510 | up->ier &= ~UART_IER_MSI; |
21c614a7 PA |
2511 | if (!(up->bugs & UART_BUG_NOMSR) && |
2512 | UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
1da177e4 LT |
2513 | up->ier |= UART_IER_MSI; |
2514 | if (up->capabilities & UART_CAP_UUE) | |
4539c24f SW |
2515 | up->ier |= UART_IER_UUE; |
2516 | if (up->capabilities & UART_CAP_RTOIE) | |
2517 | up->ier |= UART_IER_RTOIE; | |
1da177e4 | 2518 | |
4fd996a1 | 2519 | serial_port_out(port, UART_IER, up->ier); |
1da177e4 LT |
2520 | |
2521 | if (up->capabilities & UART_CAP_EFR) { | |
2522 | unsigned char efr = 0; | |
2523 | /* | |
2524 | * TI16C752/Startech hardware flow control. FIXME: | |
2525 | * - TI16C752 requires control thresholds to be set. | |
2526 | * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled. | |
2527 | */ | |
2528 | if (termios->c_cflag & CRTSCTS) | |
2529 | efr |= UART_EFR_CTS; | |
2530 | ||
4fd996a1 | 2531 | serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); |
dfe42443 | 2532 | if (port->flags & UPF_EXAR_EFR) |
4fd996a1 | 2533 | serial_port_out(port, UART_XR_EFR, efr); |
06315348 | 2534 | else |
4fd996a1 | 2535 | serial_port_out(port, UART_EFR, efr); |
1da177e4 LT |
2536 | } |
2537 | ||
255341c6 | 2538 | /* Workaround to enable 115200 baud on OMAP1510 internal ports */ |
54ec52b6 | 2539 | if (is_omap1510_8250(up)) { |
255341c6 JM |
2540 | if (baud == 115200) { |
2541 | quot = 1; | |
4fd996a1 | 2542 | serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1); |
255341c6 | 2543 | } else |
4fd996a1 | 2544 | serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0); |
255341c6 | 2545 | } |
255341c6 | 2546 | |
4fd996a1 PG |
2547 | /* |
2548 | * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2, | |
2549 | * otherwise just set DLAB | |
2550 | */ | |
2551 | if (up->capabilities & UART_NATSEMI) | |
2552 | serial_port_out(port, UART_LCR, 0xe0); | |
2553 | else | |
2554 | serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB); | |
1da177e4 | 2555 | |
b32b19b8 | 2556 | serial_dl_write(up, quot); |
1da177e4 | 2557 | |
45a7bd63 JS |
2558 | /* |
2559 | * XR17V35x UARTs have an extra fractional divisor register (DLD) | |
2560 | * | |
2561 | * We need to recalculate all of the registers, because DLM and DLL | |
2562 | * are already rounded to a whole integer. | |
2563 | * | |
2564 | * When recalculating we use a 32x clock instead of a 16x clock to | |
2565 | * allow 1-bit for rounding in the fractional part. | |
2566 | */ | |
2567 | if (up->port.type == PORT_XR17V35X) { | |
2568 | unsigned int baud_x32 = (port->uartclk * 2) / baud; | |
2569 | u16 quot = baud_x32 / 32; | |
2570 | u8 quot_frac = DIV_ROUND_CLOSEST(baud_x32 % 32, 2); | |
2571 | ||
2572 | serial_dl_write(up, quot); | |
2573 | serial_port_out(port, 0x2, quot_frac & 0xf); | |
2574 | } | |
2575 | ||
1da177e4 LT |
2576 | /* |
2577 | * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR | |
2578 | * is written without DLAB set, this mode will be disabled. | |
2579 | */ | |
dfe42443 | 2580 | if (port->type == PORT_16750) |
aef9a7bd | 2581 | serial_port_out(port, UART_FCR, up->fcr); |
1da177e4 | 2582 | |
4fd996a1 | 2583 | serial_port_out(port, UART_LCR, cval); /* reset DLAB */ |
1da177e4 | 2584 | up->lcr = cval; /* Save LCR */ |
dfe42443 | 2585 | if (port->type != PORT_16750) { |
4fd996a1 | 2586 | /* emulated UARTs (Lucent Venus 167x) need two steps */ |
aef9a7bd | 2587 | if (up->fcr & UART_FCR_ENABLE_FIFO) |
4fd996a1 | 2588 | serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO); |
aef9a7bd | 2589 | serial_port_out(port, UART_FCR, up->fcr); /* set fcr */ |
1da177e4 | 2590 | } |
dfe42443 PG |
2591 | serial8250_set_mctrl(port, port->mctrl); |
2592 | spin_unlock_irqrestore(&port->lock, flags); | |
d74d5d1b SAS |
2593 | serial8250_rpm_put(up); |
2594 | ||
e991a2bd AC |
2595 | /* Don't rewrite B0 */ |
2596 | if (tty_termios_baud_rate(termios)) | |
2597 | tty_termios_encode_baud_rate(termios, baud, baud); | |
1da177e4 | 2598 | } |
235dae5d PL |
2599 | EXPORT_SYMBOL(serial8250_do_set_termios); |
2600 | ||
2601 | static void | |
2602 | serial8250_set_termios(struct uart_port *port, struct ktermios *termios, | |
2603 | struct ktermios *old) | |
2604 | { | |
2605 | if (port->set_termios) | |
2606 | port->set_termios(port, termios, old); | |
2607 | else | |
2608 | serial8250_do_set_termios(port, termios, old); | |
2609 | } | |
1da177e4 | 2610 | |
dc77f161 | 2611 | static void |
732a84a0 | 2612 | serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios) |
dc77f161 | 2613 | { |
732a84a0 | 2614 | if (termios->c_line == N_PPS) { |
dc77f161 | 2615 | port->flags |= UPF_HARDPPS_CD; |
d41510ce | 2616 | spin_lock_irq(&port->lock); |
dc77f161 | 2617 | serial8250_enable_ms(port); |
d41510ce | 2618 | spin_unlock_irq(&port->lock); |
dc77f161 RG |
2619 | } else |
2620 | port->flags &= ~UPF_HARDPPS_CD; | |
2621 | } | |
2622 | ||
c161afe9 ML |
2623 | |
2624 | void serial8250_do_pm(struct uart_port *port, unsigned int state, | |
2625 | unsigned int oldstate) | |
1da177e4 | 2626 | { |
b1261c86 | 2627 | struct uart_8250_port *p = up_to_u8250p(port); |
1da177e4 LT |
2628 | |
2629 | serial8250_set_sleep(p, state != 0); | |
c161afe9 ML |
2630 | } |
2631 | EXPORT_SYMBOL(serial8250_do_pm); | |
1da177e4 | 2632 | |
c161afe9 ML |
2633 | static void |
2634 | serial8250_pm(struct uart_port *port, unsigned int state, | |
2635 | unsigned int oldstate) | |
2636 | { | |
2637 | if (port->pm) | |
2638 | port->pm(port, state, oldstate); | |
2639 | else | |
2640 | serial8250_do_pm(port, state, oldstate); | |
1da177e4 LT |
2641 | } |
2642 | ||
f2eda27d RK |
2643 | static unsigned int serial8250_port_size(struct uart_8250_port *pt) |
2644 | { | |
9b8777e3 JC |
2645 | if (pt->port.iotype == UPIO_AU) { |
2646 | if (pt->port.type == PORT_RT2880) | |
2647 | return 0x100; | |
b2b13cdf | 2648 | return 0x1000; |
9b8777e3 | 2649 | } |
54ec52b6 | 2650 | if (is_omap1_8250(pt)) |
f2eda27d | 2651 | return 0x16 << pt->port.regshift; |
54ec52b6 | 2652 | |
f2eda27d RK |
2653 | return 8 << pt->port.regshift; |
2654 | } | |
2655 | ||
1da177e4 LT |
2656 | /* |
2657 | * Resource handling. | |
2658 | */ | |
2659 | static int serial8250_request_std_resource(struct uart_8250_port *up) | |
2660 | { | |
f2eda27d | 2661 | unsigned int size = serial8250_port_size(up); |
dfe42443 | 2662 | struct uart_port *port = &up->port; |
1da177e4 LT |
2663 | int ret = 0; |
2664 | ||
dfe42443 | 2665 | switch (port->iotype) { |
85835f44 | 2666 | case UPIO_AU: |
0b30d668 SS |
2667 | case UPIO_TSI: |
2668 | case UPIO_MEM32: | |
1da177e4 | 2669 | case UPIO_MEM: |
dfe42443 | 2670 | if (!port->mapbase) |
1da177e4 LT |
2671 | break; |
2672 | ||
dfe42443 | 2673 | if (!request_mem_region(port->mapbase, size, "serial")) { |
1da177e4 LT |
2674 | ret = -EBUSY; |
2675 | break; | |
2676 | } | |
2677 | ||
dfe42443 PG |
2678 | if (port->flags & UPF_IOREMAP) { |
2679 | port->membase = ioremap_nocache(port->mapbase, size); | |
2680 | if (!port->membase) { | |
2681 | release_mem_region(port->mapbase, size); | |
1da177e4 LT |
2682 | ret = -ENOMEM; |
2683 | } | |
2684 | } | |
2685 | break; | |
2686 | ||
2687 | case UPIO_HUB6: | |
2688 | case UPIO_PORT: | |
dfe42443 | 2689 | if (!request_region(port->iobase, size, "serial")) |
1da177e4 LT |
2690 | ret = -EBUSY; |
2691 | break; | |
2692 | } | |
2693 | return ret; | |
2694 | } | |
2695 | ||
2696 | static void serial8250_release_std_resource(struct uart_8250_port *up) | |
2697 | { | |
f2eda27d | 2698 | unsigned int size = serial8250_port_size(up); |
dfe42443 | 2699 | struct uart_port *port = &up->port; |
1da177e4 | 2700 | |
dfe42443 | 2701 | switch (port->iotype) { |
85835f44 | 2702 | case UPIO_AU: |
0b30d668 SS |
2703 | case UPIO_TSI: |
2704 | case UPIO_MEM32: | |
1da177e4 | 2705 | case UPIO_MEM: |
dfe42443 | 2706 | if (!port->mapbase) |
1da177e4 LT |
2707 | break; |
2708 | ||
dfe42443 PG |
2709 | if (port->flags & UPF_IOREMAP) { |
2710 | iounmap(port->membase); | |
2711 | port->membase = NULL; | |
1da177e4 LT |
2712 | } |
2713 | ||
dfe42443 | 2714 | release_mem_region(port->mapbase, size); |
1da177e4 LT |
2715 | break; |
2716 | ||
2717 | case UPIO_HUB6: | |
2718 | case UPIO_PORT: | |
dfe42443 | 2719 | release_region(port->iobase, size); |
1da177e4 LT |
2720 | break; |
2721 | } | |
2722 | } | |
2723 | ||
2724 | static int serial8250_request_rsa_resource(struct uart_8250_port *up) | |
2725 | { | |
2726 | unsigned long start = UART_RSA_BASE << up->port.regshift; | |
2727 | unsigned int size = 8 << up->port.regshift; | |
dfe42443 | 2728 | struct uart_port *port = &up->port; |
0b30d668 | 2729 | int ret = -EINVAL; |
1da177e4 | 2730 | |
dfe42443 | 2731 | switch (port->iotype) { |
1da177e4 LT |
2732 | case UPIO_HUB6: |
2733 | case UPIO_PORT: | |
dfe42443 | 2734 | start += port->iobase; |
0b30d668 SS |
2735 | if (request_region(start, size, "serial-rsa")) |
2736 | ret = 0; | |
2737 | else | |
1da177e4 LT |
2738 | ret = -EBUSY; |
2739 | break; | |
2740 | } | |
2741 | ||
2742 | return ret; | |
2743 | } | |
2744 | ||
2745 | static void serial8250_release_rsa_resource(struct uart_8250_port *up) | |
2746 | { | |
2747 | unsigned long offset = UART_RSA_BASE << up->port.regshift; | |
2748 | unsigned int size = 8 << up->port.regshift; | |
dfe42443 | 2749 | struct uart_port *port = &up->port; |
1da177e4 | 2750 | |
dfe42443 | 2751 | switch (port->iotype) { |
1da177e4 LT |
2752 | case UPIO_HUB6: |
2753 | case UPIO_PORT: | |
dfe42443 | 2754 | release_region(port->iobase + offset, size); |
1da177e4 LT |
2755 | break; |
2756 | } | |
2757 | } | |
2758 | ||
2759 | static void serial8250_release_port(struct uart_port *port) | |
2760 | { | |
b1261c86 | 2761 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 LT |
2762 | |
2763 | serial8250_release_std_resource(up); | |
dfe42443 | 2764 | if (port->type == PORT_RSA) |
1da177e4 LT |
2765 | serial8250_release_rsa_resource(up); |
2766 | } | |
2767 | ||
2768 | static int serial8250_request_port(struct uart_port *port) | |
2769 | { | |
b1261c86 | 2770 | struct uart_8250_port *up = up_to_u8250p(port); |
65ecc9c0 SY |
2771 | int ret; |
2772 | ||
2773 | if (port->type == PORT_8250_CIR) | |
2774 | return -ENODEV; | |
1da177e4 LT |
2775 | |
2776 | ret = serial8250_request_std_resource(up); | |
dfe42443 | 2777 | if (ret == 0 && port->type == PORT_RSA) { |
1da177e4 LT |
2778 | ret = serial8250_request_rsa_resource(up); |
2779 | if (ret < 0) | |
2780 | serial8250_release_std_resource(up); | |
2781 | } | |
2782 | ||
2783 | return ret; | |
2784 | } | |
2785 | ||
aef9a7bd YY |
2786 | static int fcr_get_rxtrig_bytes(struct uart_8250_port *up) |
2787 | { | |
2788 | const struct serial8250_config *conf_type = &uart_config[up->port.type]; | |
2789 | unsigned char bytes; | |
2790 | ||
2791 | bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)]; | |
2792 | ||
2793 | return bytes ? bytes : -EOPNOTSUPP; | |
2794 | } | |
2795 | ||
2796 | static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes) | |
2797 | { | |
2798 | const struct serial8250_config *conf_type = &uart_config[up->port.type]; | |
2799 | int i; | |
2800 | ||
2801 | if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)]) | |
2802 | return -EOPNOTSUPP; | |
2803 | ||
2804 | for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) { | |
2805 | if (bytes < conf_type->rxtrig_bytes[i]) | |
2806 | /* Use the nearest lower value */ | |
2807 | return (--i) << UART_FCR_R_TRIG_SHIFT; | |
2808 | } | |
2809 | ||
2810 | return UART_FCR_R_TRIG_11; | |
2811 | } | |
2812 | ||
2813 | static int do_get_rxtrig(struct tty_port *port) | |
2814 | { | |
2815 | struct uart_state *state = container_of(port, struct uart_state, port); | |
2816 | struct uart_port *uport = state->uart_port; | |
2817 | struct uart_8250_port *up = | |
2818 | container_of(uport, struct uart_8250_port, port); | |
2819 | ||
2820 | if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1) | |
2821 | return -EINVAL; | |
2822 | ||
2823 | return fcr_get_rxtrig_bytes(up); | |
2824 | } | |
2825 | ||
2826 | static int do_serial8250_get_rxtrig(struct tty_port *port) | |
2827 | { | |
2828 | int rxtrig_bytes; | |
2829 | ||
2830 | mutex_lock(&port->mutex); | |
2831 | rxtrig_bytes = do_get_rxtrig(port); | |
2832 | mutex_unlock(&port->mutex); | |
2833 | ||
2834 | return rxtrig_bytes; | |
2835 | } | |
2836 | ||
2837 | static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev, | |
2838 | struct device_attribute *attr, char *buf) | |
2839 | { | |
2840 | struct tty_port *port = dev_get_drvdata(dev); | |
2841 | int rxtrig_bytes; | |
2842 | ||
2843 | rxtrig_bytes = do_serial8250_get_rxtrig(port); | |
2844 | if (rxtrig_bytes < 0) | |
2845 | return rxtrig_bytes; | |
2846 | ||
2847 | return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes); | |
2848 | } | |
2849 | ||
2850 | static int do_set_rxtrig(struct tty_port *port, unsigned char bytes) | |
2851 | { | |
2852 | struct uart_state *state = container_of(port, struct uart_state, port); | |
2853 | struct uart_port *uport = state->uart_port; | |
2854 | struct uart_8250_port *up = | |
2855 | container_of(uport, struct uart_8250_port, port); | |
2856 | int rxtrig; | |
2857 | ||
2858 | if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 || | |
2859 | up->fifo_bug) | |
2860 | return -EINVAL; | |
2861 | ||
2862 | rxtrig = bytes_to_fcr_rxtrig(up, bytes); | |
2863 | if (rxtrig < 0) | |
2864 | return rxtrig; | |
2865 | ||
2866 | serial8250_clear_fifos(up); | |
2867 | up->fcr &= ~UART_FCR_TRIGGER_MASK; | |
2868 | up->fcr |= (unsigned char)rxtrig; | |
2869 | serial_out(up, UART_FCR, up->fcr); | |
2870 | return 0; | |
2871 | } | |
2872 | ||
2873 | static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes) | |
2874 | { | |
2875 | int ret; | |
2876 | ||
2877 | mutex_lock(&port->mutex); | |
2878 | ret = do_set_rxtrig(port, bytes); | |
2879 | mutex_unlock(&port->mutex); | |
2880 | ||
2881 | return ret; | |
2882 | } | |
2883 | ||
2884 | static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev, | |
2885 | struct device_attribute *attr, const char *buf, size_t count) | |
2886 | { | |
2887 | struct tty_port *port = dev_get_drvdata(dev); | |
2888 | unsigned char bytes; | |
2889 | int ret; | |
2890 | ||
2891 | if (!count) | |
2892 | return -EINVAL; | |
2893 | ||
2894 | ret = kstrtou8(buf, 10, &bytes); | |
2895 | if (ret < 0) | |
2896 | return ret; | |
2897 | ||
2898 | ret = do_serial8250_set_rxtrig(port, bytes); | |
2899 | if (ret < 0) | |
2900 | return ret; | |
2901 | ||
2902 | return count; | |
2903 | } | |
2904 | ||
2905 | static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP, | |
2906 | serial8250_get_attr_rx_trig_bytes, | |
2907 | serial8250_set_attr_rx_trig_bytes); | |
2908 | ||
2909 | static struct attribute *serial8250_dev_attrs[] = { | |
2910 | &dev_attr_rx_trig_bytes.attr, | |
2911 | NULL, | |
2912 | }; | |
2913 | ||
2914 | static struct attribute_group serial8250_dev_attr_group = { | |
2915 | .attrs = serial8250_dev_attrs, | |
2916 | }; | |
2917 | ||
2918 | static void register_dev_spec_attr_grp(struct uart_8250_port *up) | |
2919 | { | |
2920 | const struct serial8250_config *conf_type = &uart_config[up->port.type]; | |
2921 | ||
2922 | if (conf_type->rxtrig_bytes[0]) | |
2923 | up->port.attr_group = &serial8250_dev_attr_group; | |
2924 | } | |
2925 | ||
1da177e4 LT |
2926 | static void serial8250_config_port(struct uart_port *port, int flags) |
2927 | { | |
b1261c86 | 2928 | struct uart_8250_port *up = up_to_u8250p(port); |
1da177e4 LT |
2929 | int probeflags = PROBE_ANY; |
2930 | int ret; | |
2931 | ||
65ecc9c0 SY |
2932 | if (port->type == PORT_8250_CIR) |
2933 | return; | |
2934 | ||
1da177e4 LT |
2935 | /* |
2936 | * Find the region that we can probe for. This in turn | |
2937 | * tells us whether we can probe for the type of port. | |
2938 | */ | |
2939 | ret = serial8250_request_std_resource(up); | |
2940 | if (ret < 0) | |
2941 | return; | |
2942 | ||
2943 | ret = serial8250_request_rsa_resource(up); | |
2944 | if (ret < 0) | |
2945 | probeflags &= ~PROBE_RSA; | |
2946 | ||
dfe42443 | 2947 | if (port->iotype != up->cur_iotype) |
b8e7e40a AC |
2948 | set_io_from_upio(port); |
2949 | ||
1da177e4 LT |
2950 | if (flags & UART_CONFIG_TYPE) |
2951 | autoconfig(up, probeflags); | |
b2b13cdf | 2952 | |
b2b13cdf | 2953 | /* if access method is AU, it is a 16550 with a quirk */ |
dfe42443 | 2954 | if (port->type == PORT_16550A && port->iotype == UPIO_AU) |
b2b13cdf | 2955 | up->bugs |= UART_BUG_NOMSR; |
b2b13cdf | 2956 | |
3685f19e SW |
2957 | /* HW bugs may trigger IRQ while IIR == NO_INT */ |
2958 | if (port->type == PORT_TEGRA) | |
2959 | up->bugs |= UART_BUG_NOMSR; | |
2960 | ||
dfe42443 | 2961 | if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) |
1da177e4 LT |
2962 | autoconfig_irq(up); |
2963 | ||
dfe42443 | 2964 | if (port->type != PORT_RSA && probeflags & PROBE_RSA) |
1da177e4 | 2965 | serial8250_release_rsa_resource(up); |
dfe42443 | 2966 | if (port->type == PORT_UNKNOWN) |
1da177e4 | 2967 | serial8250_release_std_resource(up); |
dc96efb7 MS |
2968 | |
2969 | /* Fixme: probably not the best place for this */ | |
30fa96a3 MS |
2970 | if ((port->type == PORT_XR17V35X) || |
2971 | (port->type == PORT_XR17D15X)) | |
dc96efb7 | 2972 | port->handle_irq = exar_handle_irq; |
aef9a7bd YY |
2973 | |
2974 | register_dev_spec_attr_grp(up); | |
2975 | up->fcr = uart_config[up->port.type].fcr; | |
1da177e4 LT |
2976 | } |
2977 | ||
2978 | static int | |
2979 | serial8250_verify_port(struct uart_port *port, struct serial_struct *ser) | |
2980 | { | |
a62c4133 | 2981 | if (ser->irq >= nr_irqs || ser->irq < 0 || |
1da177e4 LT |
2982 | ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || |
2983 | ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS || | |
2984 | ser->type == PORT_STARTECH) | |
2985 | return -EINVAL; | |
2986 | return 0; | |
2987 | } | |
2988 | ||
e676253b RRD |
2989 | static int serial8250_ioctl(struct uart_port *port, unsigned int cmd, |
2990 | unsigned long arg) | |
2991 | { | |
2992 | struct uart_8250_port *up = | |
2993 | container_of(port, struct uart_8250_port, port); | |
2994 | int ret; | |
2995 | struct serial_rs485 rs485_config; | |
2996 | ||
2997 | if (!up->rs485_config) | |
2998 | return -ENOIOCTLCMD; | |
2999 | ||
3000 | switch (cmd) { | |
3001 | case TIOCSRS485: | |
3002 | if (copy_from_user(&rs485_config, (void __user *)arg, | |
3003 | sizeof(rs485_config))) | |
3004 | return -EFAULT; | |
3005 | ||
3006 | ret = up->rs485_config(up, &rs485_config); | |
3007 | if (ret) | |
3008 | return ret; | |
3009 | ||
3010 | memcpy(&up->rs485, &rs485_config, sizeof(rs485_config)); | |
3011 | ||
3012 | return 0; | |
3013 | case TIOCGRS485: | |
3014 | if (copy_to_user((void __user *)arg, &up->rs485, | |
3015 | sizeof(up->rs485))) | |
3016 | return -EFAULT; | |
3017 | return 0; | |
3018 | default: | |
3019 | break; | |
3020 | } | |
3021 | ||
3022 | return -ENOIOCTLCMD; | |
3023 | } | |
3024 | ||
1da177e4 LT |
3025 | static const char * |
3026 | serial8250_type(struct uart_port *port) | |
3027 | { | |
3028 | int type = port->type; | |
3029 | ||
3030 | if (type >= ARRAY_SIZE(uart_config)) | |
3031 | type = 0; | |
3032 | return uart_config[type].name; | |
3033 | } | |
3034 | ||
3035 | static struct uart_ops serial8250_pops = { | |
3036 | .tx_empty = serial8250_tx_empty, | |
3037 | .set_mctrl = serial8250_set_mctrl, | |
3038 | .get_mctrl = serial8250_get_mctrl, | |
3039 | .stop_tx = serial8250_stop_tx, | |
3040 | .start_tx = serial8250_start_tx, | |
234abab1 SAS |
3041 | .throttle = serial8250_throttle, |
3042 | .unthrottle = serial8250_unthrottle, | |
1da177e4 LT |
3043 | .stop_rx = serial8250_stop_rx, |
3044 | .enable_ms = serial8250_enable_ms, | |
3045 | .break_ctl = serial8250_break_ctl, | |
3046 | .startup = serial8250_startup, | |
3047 | .shutdown = serial8250_shutdown, | |
3048 | .set_termios = serial8250_set_termios, | |
dc77f161 | 3049 | .set_ldisc = serial8250_set_ldisc, |
1da177e4 LT |
3050 | .pm = serial8250_pm, |
3051 | .type = serial8250_type, | |
3052 | .release_port = serial8250_release_port, | |
3053 | .request_port = serial8250_request_port, | |
3054 | .config_port = serial8250_config_port, | |
3055 | .verify_port = serial8250_verify_port, | |
e676253b | 3056 | .ioctl = serial8250_ioctl, |
f2d937f3 JW |
3057 | #ifdef CONFIG_CONSOLE_POLL |
3058 | .poll_get_char = serial8250_get_poll_char, | |
3059 | .poll_put_char = serial8250_put_poll_char, | |
3060 | #endif | |
1da177e4 LT |
3061 | }; |
3062 | ||
3063 | static struct uart_8250_port serial8250_ports[UART_NR]; | |
3064 | ||
ae14a795 SAS |
3065 | /** |
3066 | * serial8250_get_port - retrieve struct uart_8250_port | |
3067 | * @line: serial line number | |
3068 | * | |
3069 | * This function retrieves struct uart_8250_port for the specific line. | |
3070 | * This struct *must* *not* be used to perform a 8250 or serial core operation | |
3071 | * which is not accessible otherwise. Its only purpose is to make the struct | |
3072 | * accessible to the runtime-pm callbacks for context suspend/restore. | |
3073 | * The lock assumption made here is none because runtime-pm suspend/resume | |
3074 | * callbacks should not be invoked if there is any operation performed on the | |
3075 | * port. | |
3076 | */ | |
3077 | struct uart_8250_port *serial8250_get_port(int line) | |
3078 | { | |
3079 | return &serial8250_ports[line]; | |
3080 | } | |
3081 | EXPORT_SYMBOL_GPL(serial8250_get_port); | |
3082 | ||
af7f3743 AC |
3083 | static void (*serial8250_isa_config)(int port, struct uart_port *up, |
3084 | unsigned short *capabilities); | |
3085 | ||
3086 | void serial8250_set_isa_configurator( | |
3087 | void (*v)(int port, struct uart_port *up, unsigned short *capabilities)) | |
3088 | { | |
3089 | serial8250_isa_config = v; | |
3090 | } | |
3091 | EXPORT_SYMBOL(serial8250_set_isa_configurator); | |
3092 | ||
1da177e4 LT |
3093 | static void __init serial8250_isa_init_ports(void) |
3094 | { | |
3095 | struct uart_8250_port *up; | |
3096 | static int first = 1; | |
4c0ebb80 | 3097 | int i, irqflag = 0; |
1da177e4 LT |
3098 | |
3099 | if (!first) | |
3100 | return; | |
3101 | first = 0; | |
3102 | ||
835d844d SY |
3103 | if (nr_uarts > UART_NR) |
3104 | nr_uarts = UART_NR; | |
3105 | ||
317a6842 | 3106 | for (i = 0; i < nr_uarts; i++) { |
1da177e4 | 3107 | struct uart_8250_port *up = &serial8250_ports[i]; |
dfe42443 | 3108 | struct uart_port *port = &up->port; |
1da177e4 | 3109 | |
dfe42443 PG |
3110 | port->line = i; |
3111 | spin_lock_init(&port->lock); | |
1da177e4 LT |
3112 | |
3113 | init_timer(&up->timer); | |
3114 | up->timer.function = serial8250_timeout; | |
835d844d | 3115 | up->cur_iotype = 0xFF; |
1da177e4 LT |
3116 | |
3117 | /* | |
3118 | * ALPHA_KLUDGE_MCR needs to be killed. | |
3119 | */ | |
3120 | up->mcr_mask = ~ALPHA_KLUDGE_MCR; | |
3121 | up->mcr_force = ALPHA_KLUDGE_MCR; | |
3122 | ||
dfe42443 | 3123 | port->ops = &serial8250_pops; |
1da177e4 LT |
3124 | } |
3125 | ||
4c0ebb80 AGR |
3126 | if (share_irqs) |
3127 | irqflag = IRQF_SHARED; | |
3128 | ||
44454bcd | 3129 | for (i = 0, up = serial8250_ports; |
a61c2d78 | 3130 | i < ARRAY_SIZE(old_serial_port) && i < nr_uarts; |
1da177e4 | 3131 | i++, up++) { |
dfe42443 PG |
3132 | struct uart_port *port = &up->port; |
3133 | ||
3134 | port->iobase = old_serial_port[i].port; | |
3135 | port->irq = irq_canonicalize(old_serial_port[i].irq); | |
3136 | port->irqflags = old_serial_port[i].irqflags; | |
3137 | port->uartclk = old_serial_port[i].baud_base * 16; | |
3138 | port->flags = old_serial_port[i].flags; | |
3139 | port->hub6 = old_serial_port[i].hub6; | |
3140 | port->membase = old_serial_port[i].iomem_base; | |
3141 | port->iotype = old_serial_port[i].io_type; | |
3142 | port->regshift = old_serial_port[i].iomem_reg_shift; | |
3143 | set_io_from_upio(port); | |
3144 | port->irqflags |= irqflag; | |
af7f3743 AC |
3145 | if (serial8250_isa_config != NULL) |
3146 | serial8250_isa_config(i, &up->port, &up->capabilities); | |
3147 | ||
1da177e4 LT |
3148 | } |
3149 | } | |
3150 | ||
b5d228cc SL |
3151 | static void |
3152 | serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type) | |
3153 | { | |
3154 | up->port.type = type; | |
9660497c HK |
3155 | if (!up->port.fifosize) |
3156 | up->port.fifosize = uart_config[type].fifo_size; | |
3157 | if (!up->tx_loadsz) | |
3158 | up->tx_loadsz = uart_config[type].tx_loadsz; | |
3159 | if (!up->capabilities) | |
3160 | up->capabilities = uart_config[type].flags; | |
b5d228cc SL |
3161 | } |
3162 | ||
1da177e4 LT |
3163 | static void __init |
3164 | serial8250_register_ports(struct uart_driver *drv, struct device *dev) | |
3165 | { | |
3166 | int i; | |
3167 | ||
b8e7e40a AC |
3168 | for (i = 0; i < nr_uarts; i++) { |
3169 | struct uart_8250_port *up = &serial8250_ports[i]; | |
b8e7e40a | 3170 | |
835d844d SY |
3171 | if (up->port.dev) |
3172 | continue; | |
1da177e4 LT |
3173 | |
3174 | up->port.dev = dev; | |
b5d228cc SL |
3175 | |
3176 | if (up->port.flags & UPF_FIXED_TYPE) | |
3177 | serial8250_init_fixed_type_port(up, up->port.type); | |
3178 | ||
1da177e4 LT |
3179 | uart_add_one_port(drv, &up->port); |
3180 | } | |
3181 | } | |
3182 | ||
3183 | #ifdef CONFIG_SERIAL_8250_CONSOLE | |
3184 | ||
d358788f RK |
3185 | static void serial8250_console_putchar(struct uart_port *port, int ch) |
3186 | { | |
b1261c86 | 3187 | struct uart_8250_port *up = up_to_u8250p(port); |
d358788f RK |
3188 | |
3189 | wait_for_xmitr(up, UART_LSR_THRE); | |
4fd996a1 | 3190 | serial_port_out(port, UART_TX, ch); |
d358788f RK |
3191 | } |
3192 | ||
1da177e4 LT |
3193 | /* |
3194 | * Print a string to the serial port trying not to disturb | |
3195 | * any possible real use of the port... | |
3196 | * | |
3197 | * The console_lock must be held when we get here. | |
3198 | */ | |
3199 | static void | |
3200 | serial8250_console_write(struct console *co, const char *s, unsigned int count) | |
3201 | { | |
3202 | struct uart_8250_port *up = &serial8250_ports[co->index]; | |
dfe42443 | 3203 | struct uart_port *port = &up->port; |
d8a5a8d7 | 3204 | unsigned long flags; |
1da177e4 | 3205 | unsigned int ier; |
d8a5a8d7 | 3206 | int locked = 1; |
1da177e4 | 3207 | |
78512ece AM |
3208 | touch_nmi_watchdog(); |
3209 | ||
d74d5d1b SAS |
3210 | serial8250_rpm_get(up); |
3211 | ||
ebade5e8 IM |
3212 | if (port->sysrq || oops_in_progress) |
3213 | locked = spin_trylock_irqsave(&port->lock, flags); | |
3214 | else | |
3215 | spin_lock_irqsave(&port->lock, flags); | |
d8a5a8d7 | 3216 | |
1da177e4 | 3217 | /* |
dc7bf130 | 3218 | * First save the IER then disable the interrupts |
1da177e4 | 3219 | */ |
4fd996a1 | 3220 | ier = serial_port_in(port, UART_IER); |
1da177e4 LT |
3221 | |
3222 | if (up->capabilities & UART_CAP_UUE) | |
4fd996a1 | 3223 | serial_port_out(port, UART_IER, UART_IER_UUE); |
1da177e4 | 3224 | else |
4fd996a1 | 3225 | serial_port_out(port, UART_IER, 0); |
1da177e4 | 3226 | |
dfe42443 | 3227 | uart_console_write(port, s, count, serial8250_console_putchar); |
1da177e4 LT |
3228 | |
3229 | /* | |
3230 | * Finally, wait for transmitter to become empty | |
3231 | * and restore the IER | |
3232 | */ | |
f91a3715 | 3233 | wait_for_xmitr(up, BOTH_EMPTY); |
4fd996a1 | 3234 | serial_port_out(port, UART_IER, ier); |
d8a5a8d7 | 3235 | |
ad4c2aa6 CM |
3236 | /* |
3237 | * The receive handling will happen properly because the | |
3238 | * receive ready bit will still be set; it is not cleared | |
3239 | * on read. However, modem control will not, we must | |
3240 | * call it if we have saved something in the saved flags | |
3241 | * while processing with interrupts off. | |
3242 | */ | |
3243 | if (up->msr_saved_flags) | |
3986fb2b | 3244 | serial8250_modem_status(up); |
ad4c2aa6 | 3245 | |
d8a5a8d7 | 3246 | if (locked) |
ebade5e8 | 3247 | spin_unlock_irqrestore(&port->lock, flags); |
d74d5d1b | 3248 | serial8250_rpm_put(up); |
1da177e4 LT |
3249 | } |
3250 | ||
f31b5d27 | 3251 | static int serial8250_console_setup(struct console *co, char *options) |
1da177e4 LT |
3252 | { |
3253 | struct uart_port *port; | |
3254 | int baud = 9600; | |
3255 | int bits = 8; | |
3256 | int parity = 'n'; | |
3257 | int flow = 'n'; | |
3258 | ||
3259 | /* | |
3260 | * Check whether an invalid uart number has been specified, and | |
3261 | * if so, search for the first available port that does have | |
3262 | * console support. | |
3263 | */ | |
317a6842 | 3264 | if (co->index >= nr_uarts) |
1da177e4 LT |
3265 | co->index = 0; |
3266 | port = &serial8250_ports[co->index].port; | |
3267 | if (!port->iobase && !port->membase) | |
3268 | return -ENODEV; | |
3269 | ||
3270 | if (options) | |
3271 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
3272 | ||
3273 | return uart_set_options(port, co, baud, parity, bits, flow); | |
3274 | } | |
3275 | ||
b6b1d877 | 3276 | static int serial8250_console_early_setup(void) |
18a8bd94 YL |
3277 | { |
3278 | return serial8250_find_port_for_earlycon(); | |
3279 | } | |
3280 | ||
1da177e4 LT |
3281 | static struct console serial8250_console = { |
3282 | .name = "ttyS", | |
3283 | .write = serial8250_console_write, | |
3284 | .device = uart_console_device, | |
3285 | .setup = serial8250_console_setup, | |
18a8bd94 | 3286 | .early_setup = serial8250_console_early_setup, |
a80c49db | 3287 | .flags = CON_PRINTBUFFER | CON_ANYTIME, |
1da177e4 LT |
3288 | .index = -1, |
3289 | .data = &serial8250_reg, | |
3290 | }; | |
3291 | ||
3292 | static int __init serial8250_console_init(void) | |
3293 | { | |
3294 | serial8250_isa_init_ports(); | |
3295 | register_console(&serial8250_console); | |
3296 | return 0; | |
3297 | } | |
3298 | console_initcall(serial8250_console_init); | |
3299 | ||
18a8bd94 | 3300 | int serial8250_find_port(struct uart_port *p) |
1da177e4 LT |
3301 | { |
3302 | int line; | |
3303 | struct uart_port *port; | |
3304 | ||
317a6842 | 3305 | for (line = 0; line < nr_uarts; line++) { |
1da177e4 | 3306 | port = &serial8250_ports[line].port; |
50aec3b5 | 3307 | if (uart_match_port(p, port)) |
1da177e4 LT |
3308 | return line; |
3309 | } | |
3310 | return -ENODEV; | |
3311 | } | |
3312 | ||
1da177e4 LT |
3313 | #define SERIAL8250_CONSOLE &serial8250_console |
3314 | #else | |
3315 | #define SERIAL8250_CONSOLE NULL | |
3316 | #endif | |
3317 | ||
3318 | static struct uart_driver serial8250_reg = { | |
3319 | .owner = THIS_MODULE, | |
3320 | .driver_name = "serial", | |
1da177e4 LT |
3321 | .dev_name = "ttyS", |
3322 | .major = TTY_MAJOR, | |
3323 | .minor = 64, | |
1da177e4 LT |
3324 | .cons = SERIAL8250_CONSOLE, |
3325 | }; | |
3326 | ||
d856c666 RK |
3327 | /* |
3328 | * early_serial_setup - early registration for 8250 ports | |
3329 | * | |
3330 | * Setup an 8250 port structure prior to console initialisation. Use | |
3331 | * after console initialisation will cause undefined behaviour. | |
3332 | */ | |
1da177e4 LT |
3333 | int __init early_serial_setup(struct uart_port *port) |
3334 | { | |
b430428a DD |
3335 | struct uart_port *p; |
3336 | ||
1da177e4 LT |
3337 | if (port->line >= ARRAY_SIZE(serial8250_ports)) |
3338 | return -ENODEV; | |
3339 | ||
3340 | serial8250_isa_init_ports(); | |
b430428a DD |
3341 | p = &serial8250_ports[port->line].port; |
3342 | p->iobase = port->iobase; | |
3343 | p->membase = port->membase; | |
3344 | p->irq = port->irq; | |
1c2f0493 | 3345 | p->irqflags = port->irqflags; |
b430428a DD |
3346 | p->uartclk = port->uartclk; |
3347 | p->fifosize = port->fifosize; | |
3348 | p->regshift = port->regshift; | |
3349 | p->iotype = port->iotype; | |
3350 | p->flags = port->flags; | |
3351 | p->mapbase = port->mapbase; | |
3352 | p->private_data = port->private_data; | |
125c97d8 HD |
3353 | p->type = port->type; |
3354 | p->line = port->line; | |
7d6a07d1 DD |
3355 | |
3356 | set_io_from_upio(p); | |
3357 | if (port->serial_in) | |
3358 | p->serial_in = port->serial_in; | |
3359 | if (port->serial_out) | |
3360 | p->serial_out = port->serial_out; | |
583d28e9 JI |
3361 | if (port->handle_irq) |
3362 | p->handle_irq = port->handle_irq; | |
3363 | else | |
3364 | p->handle_irq = serial8250_default_handle_irq; | |
7d6a07d1 | 3365 | |
1da177e4 LT |
3366 | return 0; |
3367 | } | |
3368 | ||
3369 | /** | |
3370 | * serial8250_suspend_port - suspend one serial port | |
3371 | * @line: serial line number | |
1da177e4 LT |
3372 | * |
3373 | * Suspend one serial port. | |
3374 | */ | |
3375 | void serial8250_suspend_port(int line) | |
3376 | { | |
3377 | uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port); | |
3378 | } | |
3379 | ||
3380 | /** | |
3381 | * serial8250_resume_port - resume one serial port | |
3382 | * @line: serial line number | |
1da177e4 LT |
3383 | * |
3384 | * Resume one serial port. | |
3385 | */ | |
3386 | void serial8250_resume_port(int line) | |
3387 | { | |
b5b82df6 | 3388 | struct uart_8250_port *up = &serial8250_ports[line]; |
dfe42443 | 3389 | struct uart_port *port = &up->port; |
b5b82df6 DW |
3390 | |
3391 | if (up->capabilities & UART_NATSEMI) { | |
b5b82df6 | 3392 | /* Ensure it's still in high speed mode */ |
4fd996a1 | 3393 | serial_port_out(port, UART_LCR, 0xE0); |
b5b82df6 | 3394 | |
0d0389e5 | 3395 | ns16550a_goto_highspeed(up); |
b5b82df6 | 3396 | |
4fd996a1 | 3397 | serial_port_out(port, UART_LCR, 0); |
dfe42443 | 3398 | port->uartclk = 921600*16; |
b5b82df6 | 3399 | } |
dfe42443 | 3400 | uart_resume_port(&serial8250_reg, port); |
1da177e4 LT |
3401 | } |
3402 | ||
3403 | /* | |
3404 | * Register a set of serial devices attached to a platform device. The | |
3405 | * list is terminated with a zero flags entry, which means we expect | |
3406 | * all entries to have at least UPF_BOOT_AUTOCONF set. | |
3407 | */ | |
9671f099 | 3408 | static int serial8250_probe(struct platform_device *dev) |
1da177e4 | 3409 | { |
574de559 | 3410 | struct plat_serial8250_port *p = dev_get_platdata(&dev->dev); |
2655a2c7 | 3411 | struct uart_8250_port uart; |
4c0ebb80 | 3412 | int ret, i, irqflag = 0; |
1da177e4 | 3413 | |
2655a2c7 | 3414 | memset(&uart, 0, sizeof(uart)); |
1da177e4 | 3415 | |
4c0ebb80 AGR |
3416 | if (share_irqs) |
3417 | irqflag = IRQF_SHARED; | |
3418 | ||
ec9f47cd | 3419 | for (i = 0; p && p->flags != 0; p++, i++) { |
2655a2c7 AC |
3420 | uart.port.iobase = p->iobase; |
3421 | uart.port.membase = p->membase; | |
3422 | uart.port.irq = p->irq; | |
3423 | uart.port.irqflags = p->irqflags; | |
3424 | uart.port.uartclk = p->uartclk; | |
3425 | uart.port.regshift = p->regshift; | |
3426 | uart.port.iotype = p->iotype; | |
3427 | uart.port.flags = p->flags; | |
3428 | uart.port.mapbase = p->mapbase; | |
3429 | uart.port.hub6 = p->hub6; | |
3430 | uart.port.private_data = p->private_data; | |
3431 | uart.port.type = p->type; | |
3432 | uart.port.serial_in = p->serial_in; | |
3433 | uart.port.serial_out = p->serial_out; | |
3434 | uart.port.handle_irq = p->handle_irq; | |
3435 | uart.port.handle_break = p->handle_break; | |
3436 | uart.port.set_termios = p->set_termios; | |
3437 | uart.port.pm = p->pm; | |
3438 | uart.port.dev = &dev->dev; | |
3439 | uart.port.irqflags |= irqflag; | |
3440 | ret = serial8250_register_8250_port(&uart); | |
ec9f47cd | 3441 | if (ret < 0) { |
3ae5eaec | 3442 | dev_err(&dev->dev, "unable to register port at index %d " |
4f640efb JB |
3443 | "(IO%lx MEM%llx IRQ%d): %d\n", i, |
3444 | p->iobase, (unsigned long long)p->mapbase, | |
3445 | p->irq, ret); | |
ec9f47cd | 3446 | } |
1da177e4 LT |
3447 | } |
3448 | return 0; | |
3449 | } | |
3450 | ||
3451 | /* | |
3452 | * Remove serial ports registered against a platform device. | |
3453 | */ | |
ae8d8a14 | 3454 | static int serial8250_remove(struct platform_device *dev) |
1da177e4 LT |
3455 | { |
3456 | int i; | |
3457 | ||
317a6842 | 3458 | for (i = 0; i < nr_uarts; i++) { |
1da177e4 LT |
3459 | struct uart_8250_port *up = &serial8250_ports[i]; |
3460 | ||
3ae5eaec | 3461 | if (up->port.dev == &dev->dev) |
1da177e4 LT |
3462 | serial8250_unregister_port(i); |
3463 | } | |
3464 | return 0; | |
3465 | } | |
3466 | ||
3ae5eaec | 3467 | static int serial8250_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 LT |
3468 | { |
3469 | int i; | |
3470 | ||
1da177e4 LT |
3471 | for (i = 0; i < UART_NR; i++) { |
3472 | struct uart_8250_port *up = &serial8250_ports[i]; | |
3473 | ||
3ae5eaec | 3474 | if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) |
1da177e4 LT |
3475 | uart_suspend_port(&serial8250_reg, &up->port); |
3476 | } | |
3477 | ||
3478 | return 0; | |
3479 | } | |
3480 | ||
3ae5eaec | 3481 | static int serial8250_resume(struct platform_device *dev) |
1da177e4 LT |
3482 | { |
3483 | int i; | |
3484 | ||
1da177e4 LT |
3485 | for (i = 0; i < UART_NR; i++) { |
3486 | struct uart_8250_port *up = &serial8250_ports[i]; | |
3487 | ||
3ae5eaec | 3488 | if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) |
b5b82df6 | 3489 | serial8250_resume_port(i); |
1da177e4 LT |
3490 | } |
3491 | ||
3492 | return 0; | |
3493 | } | |
3494 | ||
3ae5eaec | 3495 | static struct platform_driver serial8250_isa_driver = { |
1da177e4 | 3496 | .probe = serial8250_probe, |
2d47b716 | 3497 | .remove = serial8250_remove, |
1da177e4 LT |
3498 | .suspend = serial8250_suspend, |
3499 | .resume = serial8250_resume, | |
3ae5eaec RK |
3500 | .driver = { |
3501 | .name = "serial8250", | |
7493a314 | 3502 | .owner = THIS_MODULE, |
3ae5eaec | 3503 | }, |
1da177e4 LT |
3504 | }; |
3505 | ||
3506 | /* | |
3507 | * This "device" covers _all_ ISA 8250-compatible serial devices listed | |
3508 | * in the table in include/asm/serial.h | |
3509 | */ | |
3510 | static struct platform_device *serial8250_isa_devs; | |
3511 | ||
3512 | /* | |
2655a2c7 | 3513 | * serial8250_register_8250_port and serial8250_unregister_port allows for |
1da177e4 LT |
3514 | * 16x50 serial ports to be configured at run-time, to support PCMCIA |
3515 | * modems and PCI multiport cards. | |
3516 | */ | |
f392ecfa | 3517 | static DEFINE_MUTEX(serial_mutex); |
1da177e4 LT |
3518 | |
3519 | static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port) | |
3520 | { | |
3521 | int i; | |
3522 | ||
3523 | /* | |
3524 | * First, find a port entry which matches. | |
3525 | */ | |
317a6842 | 3526 | for (i = 0; i < nr_uarts; i++) |
1da177e4 LT |
3527 | if (uart_match_port(&serial8250_ports[i].port, port)) |
3528 | return &serial8250_ports[i]; | |
3529 | ||
59b3e898 SAS |
3530 | /* try line number first if still available */ |
3531 | i = port->line; | |
3532 | if (i < nr_uarts && serial8250_ports[i].port.type == PORT_UNKNOWN && | |
3533 | serial8250_ports[i].port.iobase == 0) | |
3534 | return &serial8250_ports[i]; | |
1da177e4 LT |
3535 | /* |
3536 | * We didn't find a matching entry, so look for the first | |
3537 | * free entry. We look for one which hasn't been previously | |
3538 | * used (indicated by zero iobase). | |
3539 | */ | |
317a6842 | 3540 | for (i = 0; i < nr_uarts; i++) |
1da177e4 LT |
3541 | if (serial8250_ports[i].port.type == PORT_UNKNOWN && |
3542 | serial8250_ports[i].port.iobase == 0) | |
3543 | return &serial8250_ports[i]; | |
3544 | ||
3545 | /* | |
3546 | * That also failed. Last resort is to find any entry which | |
3547 | * doesn't have a real port associated with it. | |
3548 | */ | |
317a6842 | 3549 | for (i = 0; i < nr_uarts; i++) |
1da177e4 LT |
3550 | if (serial8250_ports[i].port.type == PORT_UNKNOWN) |
3551 | return &serial8250_ports[i]; | |
3552 | ||
3553 | return NULL; | |
3554 | } | |
3555 | ||
3556 | /** | |
f73fa05b | 3557 | * serial8250_register_8250_port - register a serial port |
58bcd332 | 3558 | * @up: serial port template |
1da177e4 LT |
3559 | * |
3560 | * Configure the serial port specified by the request. If the | |
3561 | * port exists and is in use, it is hung up and unregistered | |
3562 | * first. | |
3563 | * | |
3564 | * The port is then probed and if necessary the IRQ is autodetected | |
3565 | * If this fails an error is returned. | |
3566 | * | |
3567 | * On success the port is ready to use and the line number is returned. | |
3568 | */ | |
f73fa05b | 3569 | int serial8250_register_8250_port(struct uart_8250_port *up) |
1da177e4 LT |
3570 | { |
3571 | struct uart_8250_port *uart; | |
3572 | int ret = -ENOSPC; | |
3573 | ||
f73fa05b | 3574 | if (up->port.uartclk == 0) |
1da177e4 LT |
3575 | return -EINVAL; |
3576 | ||
f392ecfa | 3577 | mutex_lock(&serial_mutex); |
1da177e4 | 3578 | |
f73fa05b | 3579 | uart = serial8250_find_match_or_unused(&up->port); |
65ecc9c0 | 3580 | if (uart && uart->port.type != PORT_8250_CIR) { |
835d844d SY |
3581 | if (uart->port.dev) |
3582 | uart_remove_one_port(&serial8250_reg, &uart->port); | |
1da177e4 | 3583 | |
f73fa05b MD |
3584 | uart->port.iobase = up->port.iobase; |
3585 | uart->port.membase = up->port.membase; | |
3586 | uart->port.irq = up->port.irq; | |
3587 | uart->port.irqflags = up->port.irqflags; | |
3588 | uart->port.uartclk = up->port.uartclk; | |
3589 | uart->port.fifosize = up->port.fifosize; | |
3590 | uart->port.regshift = up->port.regshift; | |
3591 | uart->port.iotype = up->port.iotype; | |
3592 | uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF; | |
a2d33d87 | 3593 | uart->bugs = up->bugs; |
f73fa05b MD |
3594 | uart->port.mapbase = up->port.mapbase; |
3595 | uart->port.private_data = up->port.private_data; | |
9660497c HK |
3596 | uart->port.fifosize = up->port.fifosize; |
3597 | uart->tx_loadsz = up->tx_loadsz; | |
3598 | uart->capabilities = up->capabilities; | |
e676253b RRD |
3599 | uart->rs485_config = up->rs485_config; |
3600 | uart->rs485 = up->rs485; | |
234abab1 SAS |
3601 | uart->port.throttle = up->port.throttle; |
3602 | uart->port.unthrottle = up->port.unthrottle; | |
9660497c | 3603 | |
6a3f45dc HK |
3604 | /* Take tx_loadsz from fifosize if it wasn't set separately */ |
3605 | if (uart->port.fifosize && !uart->tx_loadsz) | |
3606 | uart->tx_loadsz = uart->port.fifosize; | |
3607 | ||
f73fa05b MD |
3608 | if (up->port.dev) |
3609 | uart->port.dev = up->port.dev; | |
3610 | ||
3611 | if (up->port.flags & UPF_FIXED_TYPE) | |
3612 | serial8250_init_fixed_type_port(uart, up->port.type); | |
8e23fcc8 | 3613 | |
7d6a07d1 DD |
3614 | set_io_from_upio(&uart->port); |
3615 | /* Possibly override default I/O functions. */ | |
f73fa05b MD |
3616 | if (up->port.serial_in) |
3617 | uart->port.serial_in = up->port.serial_in; | |
3618 | if (up->port.serial_out) | |
3619 | uart->port.serial_out = up->port.serial_out; | |
3620 | if (up->port.handle_irq) | |
3621 | uart->port.handle_irq = up->port.handle_irq; | |
235dae5d | 3622 | /* Possibly override set_termios call */ |
f73fa05b MD |
3623 | if (up->port.set_termios) |
3624 | uart->port.set_termios = up->port.set_termios; | |
b99b121b SAS |
3625 | if (up->port.startup) |
3626 | uart->port.startup = up->port.startup; | |
3627 | if (up->port.shutdown) | |
3628 | uart->port.shutdown = up->port.shutdown; | |
f73fa05b MD |
3629 | if (up->port.pm) |
3630 | uart->port.pm = up->port.pm; | |
3631 | if (up->port.handle_break) | |
3632 | uart->port.handle_break = up->port.handle_break; | |
3633 | if (up->dl_read) | |
3634 | uart->dl_read = up->dl_read; | |
3635 | if (up->dl_write) | |
3636 | uart->dl_write = up->dl_write; | |
f1a297bb | 3637 | if (up->dma) { |
9ee4b83e | 3638 | uart->dma = up->dma; |
f1a297bb SAS |
3639 | if (!uart->dma->tx_dma) |
3640 | uart->dma->tx_dma = serial8250_tx_dma; | |
3641 | if (!uart->dma->rx_dma) | |
3642 | uart->dma->rx_dma = serial8250_rx_dma; | |
3643 | } | |
1da177e4 | 3644 | |
af7f3743 AC |
3645 | if (serial8250_isa_config != NULL) |
3646 | serial8250_isa_config(0, &uart->port, | |
3647 | &uart->capabilities); | |
3648 | ||
1da177e4 LT |
3649 | ret = uart_add_one_port(&serial8250_reg, &uart->port); |
3650 | if (ret == 0) | |
3651 | ret = uart->port.line; | |
3652 | } | |
f392ecfa | 3653 | mutex_unlock(&serial_mutex); |
1da177e4 LT |
3654 | |
3655 | return ret; | |
3656 | } | |
f73fa05b MD |
3657 | EXPORT_SYMBOL(serial8250_register_8250_port); |
3658 | ||
1da177e4 LT |
3659 | /** |
3660 | * serial8250_unregister_port - remove a 16x50 serial port at runtime | |
3661 | * @line: serial line number | |
3662 | * | |
3663 | * Remove one serial port. This may not be called from interrupt | |
3664 | * context. We hand the port back to the our control. | |
3665 | */ | |
3666 | void serial8250_unregister_port(int line) | |
3667 | { | |
3668 | struct uart_8250_port *uart = &serial8250_ports[line]; | |
3669 | ||
f392ecfa | 3670 | mutex_lock(&serial_mutex); |
1da177e4 LT |
3671 | uart_remove_one_port(&serial8250_reg, &uart->port); |
3672 | if (serial8250_isa_devs) { | |
3673 | uart->port.flags &= ~UPF_BOOT_AUTOCONF; | |
3674 | uart->port.type = PORT_UNKNOWN; | |
3675 | uart->port.dev = &serial8250_isa_devs->dev; | |
cb01ece3 | 3676 | uart->capabilities = uart_config[uart->port.type].flags; |
1da177e4 LT |
3677 | uart_add_one_port(&serial8250_reg, &uart->port); |
3678 | } else { | |
3679 | uart->port.dev = NULL; | |
3680 | } | |
f392ecfa | 3681 | mutex_unlock(&serial_mutex); |
1da177e4 LT |
3682 | } |
3683 | EXPORT_SYMBOL(serial8250_unregister_port); | |
3684 | ||
3685 | static int __init serial8250_init(void) | |
3686 | { | |
25db8ad5 | 3687 | int ret; |
1da177e4 | 3688 | |
835d844d | 3689 | serial8250_isa_init_ports(); |
a61c2d78 | 3690 | |
f1fb9bb8 | 3691 | printk(KERN_INFO "Serial: 8250/16550 driver, " |
a61c2d78 | 3692 | "%d ports, IRQ sharing %sabled\n", nr_uarts, |
1da177e4 LT |
3693 | share_irqs ? "en" : "dis"); |
3694 | ||
b70ac771 DM |
3695 | #ifdef CONFIG_SPARC |
3696 | ret = sunserial_register_minors(&serial8250_reg, UART_NR); | |
3697 | #else | |
3698 | serial8250_reg.nr = UART_NR; | |
1da177e4 | 3699 | ret = uart_register_driver(&serial8250_reg); |
b70ac771 | 3700 | #endif |
1da177e4 LT |
3701 | if (ret) |
3702 | goto out; | |
3703 | ||
835d844d SY |
3704 | ret = serial8250_pnp_init(); |
3705 | if (ret) | |
3706 | goto unreg_uart_drv; | |
3707 | ||
7493a314 DT |
3708 | serial8250_isa_devs = platform_device_alloc("serial8250", |
3709 | PLAT8250_DEV_LEGACY); | |
3710 | if (!serial8250_isa_devs) { | |
3711 | ret = -ENOMEM; | |
835d844d | 3712 | goto unreg_pnp; |
1da177e4 LT |
3713 | } |
3714 | ||
7493a314 DT |
3715 | ret = platform_device_add(serial8250_isa_devs); |
3716 | if (ret) | |
3717 | goto put_dev; | |
3718 | ||
1da177e4 LT |
3719 | serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev); |
3720 | ||
bc965a7f RK |
3721 | ret = platform_driver_register(&serial8250_isa_driver); |
3722 | if (ret == 0) | |
3723 | goto out; | |
1da177e4 | 3724 | |
bc965a7f | 3725 | platform_device_del(serial8250_isa_devs); |
25db8ad5 | 3726 | put_dev: |
7493a314 | 3727 | platform_device_put(serial8250_isa_devs); |
835d844d SY |
3728 | unreg_pnp: |
3729 | serial8250_pnp_exit(); | |
25db8ad5 | 3730 | unreg_uart_drv: |
b70ac771 DM |
3731 | #ifdef CONFIG_SPARC |
3732 | sunserial_unregister_minors(&serial8250_reg, UART_NR); | |
3733 | #else | |
1da177e4 | 3734 | uart_unregister_driver(&serial8250_reg); |
b70ac771 | 3735 | #endif |
25db8ad5 | 3736 | out: |
1da177e4 LT |
3737 | return ret; |
3738 | } | |
3739 | ||
3740 | static void __exit serial8250_exit(void) | |
3741 | { | |
3742 | struct platform_device *isa_dev = serial8250_isa_devs; | |
3743 | ||
3744 | /* | |
3745 | * This tells serial8250_unregister_port() not to re-register | |
3746 | * the ports (thereby making serial8250_isa_driver permanently | |
3747 | * in use.) | |
3748 | */ | |
3749 | serial8250_isa_devs = NULL; | |
3750 | ||
3ae5eaec | 3751 | platform_driver_unregister(&serial8250_isa_driver); |
1da177e4 LT |
3752 | platform_device_unregister(isa_dev); |
3753 | ||
835d844d SY |
3754 | serial8250_pnp_exit(); |
3755 | ||
b70ac771 DM |
3756 | #ifdef CONFIG_SPARC |
3757 | sunserial_unregister_minors(&serial8250_reg, UART_NR); | |
3758 | #else | |
1da177e4 | 3759 | uart_unregister_driver(&serial8250_reg); |
b70ac771 | 3760 | #endif |
1da177e4 LT |
3761 | } |
3762 | ||
3763 | module_init(serial8250_init); | |
3764 | module_exit(serial8250_exit); | |
3765 | ||
3766 | EXPORT_SYMBOL(serial8250_suspend_port); | |
3767 | EXPORT_SYMBOL(serial8250_resume_port); | |
3768 | ||
3769 | MODULE_LICENSE("GPL"); | |
d87a6d95 | 3770 | MODULE_DESCRIPTION("Generic 8250/16x50 serial driver"); |
1da177e4 LT |
3771 | |
3772 | module_param(share_irqs, uint, 0644); | |
3773 | MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices" | |
3774 | " (unsafe)"); | |
3775 | ||
a61c2d78 DJ |
3776 | module_param(nr_uarts, uint, 0644); |
3777 | MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")"); | |
3778 | ||
d41a4b51 CE |
3779 | module_param(skip_txen_test, uint, 0644); |
3780 | MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time"); | |
3781 | ||
1da177e4 LT |
3782 | #ifdef CONFIG_SERIAL_8250_RSA |
3783 | module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444); | |
3784 | MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA"); | |
3785 | #endif | |
3786 | MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR); | |
f2b8dfd9 | 3787 | |
9326b047 | 3788 | #ifdef CONFIG_SERIAL_8250_DEPRECATED_OPTIONS |
f2b8dfd9 JB |
3789 | #ifndef MODULE |
3790 | /* This module was renamed to 8250_core in 3.7. Keep the old "8250" name | |
3791 | * working as well for the module options so we don't break people. We | |
3792 | * need to keep the names identical and the convenient macros will happily | |
3793 | * refuse to let us do that by failing the build with redefinition errors | |
3794 | * of global variables. So we stick them inside a dummy function to avoid | |
3795 | * those conflicts. The options still get parsed, and the redefined | |
3796 | * MODULE_PARAM_PREFIX lets us keep the "8250." syntax alive. | |
3797 | * | |
3798 | * This is hacky. I'm sorry. | |
3799 | */ | |
3800 | static void __used s8250_options(void) | |
3801 | { | |
3802 | #undef MODULE_PARAM_PREFIX | |
9196d8ac | 3803 | #define MODULE_PARAM_PREFIX "8250_core." |
f2b8dfd9 JB |
3804 | |
3805 | module_param_cb(share_irqs, ¶m_ops_uint, &share_irqs, 0644); | |
3806 | module_param_cb(nr_uarts, ¶m_ops_uint, &nr_uarts, 0644); | |
3807 | module_param_cb(skip_txen_test, ¶m_ops_uint, &skip_txen_test, 0644); | |
3808 | #ifdef CONFIG_SERIAL_8250_RSA | |
3809 | __module_param_call(MODULE_PARAM_PREFIX, probe_rsa, | |
3810 | ¶m_array_ops, .arr = &__param_arr_probe_rsa, | |
91f9d330 | 3811 | 0444, -1, 0); |
f2b8dfd9 JB |
3812 | #endif |
3813 | } | |
3814 | #else | |
9196d8ac | 3815 | MODULE_ALIAS("8250_core"); |
f2b8dfd9 | 3816 | #endif |
f2b8dfd9 | 3817 | #endif |