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tty/8250 Add XR17D15x devices to the exar_handle_irq override
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4
LT		 11 */
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
0ad372b9 20#include <linux/serial_reg.h>
1da177e4
LT		 21#include <linux/serial_core.h>
22#include <linux/8250_pci.h>
23#include <linux/bitops.h>
24
25#include <asm/byteorder.h>
26#include <asm/io.h>
27
28#include "8250.h"
29
30#undef SERIAL_DEBUG_PCI
31
1da177e4
LT		 32/*
33 * init function returns:
34 * > 0 - number of ports
35 * = 0 - use board->num_ports
36 * < 0 - error
37 */
38struct pci_serial_quirk {
39 u32 vendor;
40 u32 device;
41 u32 subvendor;
42 u32 subdevice;
5bf8f501 43 int (*probe)(struct pci_dev *dev);
1da177e4 44 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
2655a2c7 47 struct uart_8250_port *, int);
1da177e4
LT		 48 void (*exit)(struct pci_dev *dev);
49};
50
51#define PCI_NUM_BAR_RESOURCES 6
52
53struct serial_private {
70db3d91 54 struct pci_dev *dev;
1da177e4
LT		 55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59};
60
7808edcd 61static int pci_default_setup(struct serial_private*,
2655a2c7 62 const struct pciserial_board*, struct uart_8250_port *, int);
7808edcd 63
1da177e4
LT		 64static void moan_device(const char *str, struct pci_dev *dev)
65{
ad361c98
JP		 66 printk(KERN_WARNING
67 "%s: %s\n"
68 "Please send the output of lspci -vv, this\n"
69 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
70 "manufacturer and name of serial board or\n"
71 "modem board to rmk+serial@arm.linux.org.uk.\n",
1da177e4
LT		 72 pci_name(dev), str, dev->vendor, dev->device,
73 dev->subsystem_vendor, dev->subsystem_device);
74}
75
76static int
2655a2c7 77setup_port(struct serial_private *priv, struct uart_8250_port *port,
1da177e4
LT		 78 int bar, int offset, int regshift)
79{
70db3d91 80 struct pci_dev *dev = priv->dev;
1da177e4
LT		 81 unsigned long base, len;
82
83 if (bar >= PCI_NUM_BAR_RESOURCES)
84 return -EINVAL;
85
72ce9a83
RK		 86 base = pci_resource_start(dev, bar);
87
1da177e4 88 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 89 len = pci_resource_len(dev, bar);
90
91 if (!priv->remapped_bar[bar])
6f441fe9 92 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 93 if (!priv->remapped_bar[bar])
94 return -ENOMEM;
95
2655a2c7
AC		 96 port->port.iotype = UPIO_MEM;
97 port->port.iobase = 0;
98 port->port.mapbase = base + offset;
99 port->port.membase = priv->remapped_bar[bar] + offset;
100 port->port.regshift = regshift;
1da177e4 101 } else {
2655a2c7
AC		 102 port->port.iotype = UPIO_PORT;
103 port->port.iobase = base + offset;
104 port->port.mapbase = 0;
105 port->port.membase = NULL;
106 port->port.regshift = 0;
1da177e4
LT		 107 }
108 return 0;
109}
110
02c9b5cf
KJ		 111/*
112 * ADDI-DATA GmbH communication cards <info@addi-data.com>
113 */
114static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 115 const struct pciserial_board *board,
2655a2c7 116 struct uart_8250_port *port, int idx)
02c9b5cf
KJ		 117{
118 unsigned int bar = 0, offset = board->first_offset;
119 bar = FL_GET_BASE(board->flags);
120
121 if (idx < 2) {
122 offset += idx * board->uart_offset;
123 } else if ((idx >= 2) && (idx < 4)) {
124 bar += 1;
125 offset += ((idx - 2) * board->uart_offset);
126 } else if ((idx >= 4) && (idx < 6)) {
127 bar += 2;
128 offset += ((idx - 4) * board->uart_offset);
129 } else if (idx >= 6) {
130 bar += 3;
131 offset += ((idx - 6) * board->uart_offset);
132 }
133
134 return setup_port(priv, port, bar, offset, board->reg_shift);
135}
136
1da177e4
LT		 137/*
138 * AFAVLAB uses a different mixture of BARs and offsets
139 * Not that ugly ;) -- HW
140 */
141static int
975a1a7d 142afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 143 struct uart_8250_port *port, int idx)
1da177e4
LT		 144{
145 unsigned int bar, offset = board->first_offset;
5756ee99 146
1da177e4
LT		 147 bar = FL_GET_BASE(board->flags);
148 if (idx < 4)
149 bar += idx;
150 else {
151 bar = 4;
152 offset += (idx - 4) * board->uart_offset;
153 }
154
70db3d91 155 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 156}
157
158/*
159 * HP's Remote Management Console. The Diva chip came in several
160 * different versions. N-class, L2000 and A500 have two Diva chips, each
161 * with 3 UARTs (the third UART on the second chip is unused). Superdome
162 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
163 * one Diva chip, but it has been expanded to 5 UARTs.
164 */
61a116ef 165static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 166{
167 int rc = 0;
168
169 switch (dev->subsystem_device) {
170 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
171 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
172 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
173 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
174 rc = 3;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
177 rc = 2;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
180 rc = 4;
181 break;
182 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 183 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 184 rc = 1;
185 break;
186 }
187
188 return rc;
189}
190
191/*
192 * HP's Diva chip puts the 4th/5th serial port further out, and
193 * some serial ports are supposed to be hidden on certain models.
194 */
195static int
975a1a7d
RK		 196pci_hp_diva_setup(struct serial_private *priv,
197 const struct pciserial_board *board,
2655a2c7 198 struct uart_8250_port *port, int idx)
1da177e4
LT		 199{
200 unsigned int offset = board->first_offset;
201 unsigned int bar = FL_GET_BASE(board->flags);
202
70db3d91 203 switch (priv->dev->subsystem_device) {
1da177e4
LT		 204 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
205 if (idx == 3)
206 idx++;
207 break;
208 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
209 if (idx > 0)
210 idx++;
211 if (idx > 2)
212 idx++;
213 break;
214 }
215 if (idx > 2)
216 offset = 0x18;
217
218 offset += idx * board->uart_offset;
219
70db3d91 220 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 221}
222
223/*
224 * Added for EKF Intel i960 serial boards
225 */
61a116ef 226static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 227{
228 unsigned long oldval;
229
230 if (!(dev->subsystem_device & 0x1000))
231 return -ENODEV;
232
233 /* is firmware started? */
5756ee99
AC		 234 pci_read_config_dword(dev, 0x44, (void *)&oldval);
235 if (oldval == 0x00001000L) { /* RESET value */
1da177e4
LT		 236 printk(KERN_DEBUG "Local i960 firmware missing");
237 return -ENODEV;
238 }
239 return 0;
240}
241
242/*
243 * Some PCI serial cards using the PLX 9050 PCI interface chip require
244 * that the card interrupt be explicitly enabled or disabled. This
245 * seems to be mainly needed on card using the PLX which also use I/O
246 * mapped memory.
247 */
61a116ef 248static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 249{
250 u8 irq_config;
251 void __iomem *p;
252
253 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
254 moan_device("no memory in bar 0", dev);
255 return 0;
256 }
257
258 irq_config = 0x41;
add7b58e 259 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 260 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 261 irq_config = 0x43;
5756ee99 262
1da177e4 263 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 264 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 265 /*
266 * As the megawolf cards have the int pins active
267 * high, and have 2 UART chips, both ints must be
268 * enabled on the 9050. Also, the UARTS are set in
269 * 16450 mode by default, so we have to enable the
270 * 16C950 'enhanced' mode so that we can use the
271 * deep FIFOs
272 */
273 irq_config = 0x5b;
1da177e4
LT		 274 /*
275 * enable/disable interrupts
276 */
6f441fe9 277 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 278 if (p == NULL)
279 return -ENOMEM;
280 writel(irq_config, p + 0x4c);
281
282 /*
283 * Read the register back to ensure that it took effect.
284 */
285 readl(p + 0x4c);
286 iounmap(p);
287
288 return 0;
289}
290
ae8d8a14 291static void pci_plx9050_exit(struct pci_dev *dev)
1da177e4
LT		 292{
293 u8 __iomem *p;
294
295 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
296 return;
297
298 /*
299 * disable interrupts
300 */
6f441fe9 301 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 302 if (p != NULL) {
303 writel(0, p + 0x4c);
304
305 /*
306 * Read the register back to ensure that it took effect.
307 */
308 readl(p + 0x4c);
309 iounmap(p);
310 }
311}
312
04bf7e74
WP		 313#define NI8420_INT_ENABLE_REG 0x38
314#define NI8420_INT_ENABLE_BIT 0x2000
315
ae8d8a14 316static void pci_ni8420_exit(struct pci_dev *dev)
04bf7e74
WP		 317{
318 void __iomem *p;
319 unsigned long base, len;
320 unsigned int bar = 0;
321
322 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
323 moan_device("no memory in bar", dev);
324 return;
325 }
326
327 base = pci_resource_start(dev, bar);
328 len = pci_resource_len(dev, bar);
329 p = ioremap_nocache(base, len);
330 if (p == NULL)
331 return;
332
333 /* Disable the CPU Interrupt */
334 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
335 p + NI8420_INT_ENABLE_REG);
336 iounmap(p);
337}
338
339
46a0fac9
SB		 340/* MITE registers */
341#define MITE_IOWBSR1 0xc4
342#define MITE_IOWCR1 0xf4
343#define MITE_LCIMR1 0x08
344#define MITE_LCIMR2 0x10
345
346#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
347
ae8d8a14 348static void pci_ni8430_exit(struct pci_dev *dev)
46a0fac9
SB		 349{
350 void __iomem *p;
351 unsigned long base, len;
352 unsigned int bar = 0;
353
354 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
355 moan_device("no memory in bar", dev);
356 return;
357 }
358
359 base = pci_resource_start(dev, bar);
360 len = pci_resource_len(dev, bar);
361 p = ioremap_nocache(base, len);
362 if (p == NULL)
363 return;
364
365 /* Disable the CPU Interrupt */
366 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
367 iounmap(p);
368}
369
1da177e4
LT		 370/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
371static int
975a1a7d 372sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 373 struct uart_8250_port *port, int idx)
1da177e4
LT		 374{
375 unsigned int bar, offset = board->first_offset;
376
377 bar = 0;
378
379 if (idx < 4) {
380 /* first four channels map to 0, 0x100, 0x200, 0x300 */
381 offset += idx * board->uart_offset;
382 } else if (idx < 8) {
383 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
384 offset += idx * board->uart_offset + 0xC00;
385 } else /* we have only 8 ports on PMC-OCTALPRO */
386 return 1;
387
70db3d91 388 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 389}
390
391/*
392* This does initialization for PMC OCTALPRO cards:
393* maps the device memory, resets the UARTs (needed, bc
394* if the module is removed and inserted again, the card
395* is in the sleep mode) and enables global interrupt.
396*/
397
398/* global control register offset for SBS PMC-OctalPro */
399#define OCT_REG_CR_OFF 0x500
400
61a116ef 401static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 402{
403 u8 __iomem *p;
404
24ed3aba 405 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 406
407 if (p == NULL)
408 return -ENOMEM;
409 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 410 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 411 udelay(50);
5756ee99 412 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 413
414 /* Set bit-2 (INTENABLE) of Control Register */
415 writeb(0x4, p + OCT_REG_CR_OFF);
416 iounmap(p);
417
418 return 0;
419}
420
421/*
422 * Disables the global interrupt of PMC-OctalPro
423 */
424
ae8d8a14 425static void sbs_exit(struct pci_dev *dev)
1da177e4
LT		 426{
427 u8 __iomem *p;
428
24ed3aba 429 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 430 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
431 if (p != NULL)
1da177e4 432 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 433 iounmap(p);
434}
435
436/*
437 * SIIG serial cards have an PCI interface chip which also controls
438 * the UART clocking frequency. Each UART can be clocked independently
25985edc 439 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 440 * are stored in the EEPROM chip. It can cause problems because this
441 * version of serial driver doesn't support differently clocked UART's
442 * on single PCI card. To prevent this, initialization functions set
443 * high frequency clocking for all UART's on given card. It is safe (I
444 * hope) because it doesn't touch EEPROM settings to prevent conflicts
445 * with other OSes (like M$ DOS).
446 *
447 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 448 *
1da177e4
LT		 449 * There is two family of SIIG serial cards with different PCI
450 * interface chip and different configuration methods:
451 * - 10x cards have control registers in IO and/or memory space;
452 * - 20x cards have control registers in standard PCI configuration space.
453 *
67d74b87
RK		 454 * Note: all 10x cards have PCI device ids 0x10..
455 * all 20x cards have PCI device ids 0x20..
456 *
fbc0dc0d
AP		 457 * There are also Quartet Serial cards which use Oxford Semiconductor
458 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
459 *
1da177e4
LT		 460 * Note: some SIIG cards are probed by the parport_serial object.
461 */
462
463#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
464#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
465
466static int pci_siig10x_init(struct pci_dev *dev)
467{
468 u16 data;
469 void __iomem *p;
470
471 switch (dev->device & 0xfff8) {
472 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
473 data = 0xffdf;
474 break;
475 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
476 data = 0xf7ff;
477 break;
478 default: /* 1S1P, 4S */
479 data = 0xfffb;
480 break;
481 }
482
6f441fe9 483 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 484 if (p == NULL)
485 return -ENOMEM;
486
487 writew(readw(p + 0x28) & data, p + 0x28);
488 readw(p + 0x28);
489 iounmap(p);
490 return 0;
491}
492
493#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
494#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
495
496static int pci_siig20x_init(struct pci_dev *dev)
497{
498 u8 data;
499
500 /* Change clock frequency for the first UART. */
501 pci_read_config_byte(dev, 0x6f, &data);
502 pci_write_config_byte(dev, 0x6f, data & 0xef);
503
504 /* If this card has 2 UART, we have to do the same with second UART. */
505 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
506 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
507 pci_read_config_byte(dev, 0x73, &data);
508 pci_write_config_byte(dev, 0x73, data & 0xef);
509 }
510 return 0;
511}
512
67d74b87
RK		 513static int pci_siig_init(struct pci_dev *dev)
514{
515 unsigned int type = dev->device & 0xff00;
516
517 if (type == 0x1000)
518 return pci_siig10x_init(dev);
519 else if (type == 0x2000)
520 return pci_siig20x_init(dev);
521
522 moan_device("Unknown SIIG card", dev);
523 return -ENODEV;
524}
525
3ec9c594 526static int pci_siig_setup(struct serial_private *priv,
975a1a7d 527 const struct pciserial_board *board,
2655a2c7 528 struct uart_8250_port *port, int idx)
3ec9c594
AP		 529{
530 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
531
532 if (idx > 3) {
533 bar = 4;
534 offset = (idx - 4) * 8;
535 }
536
537 return setup_port(priv, port, bar, offset, 0);
538}
539
1da177e4
LT		 540/*
541 * Timedia has an explosion of boards, and to avoid the PCI table from
542 * growing *huge*, we use this function to collapse some 70 entries
543 * in the PCI table into one, for sanity's and compactness's sake.
544 */
e9422e09 545static const unsigned short timedia_single_port[] = {
1da177e4
LT		 546 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
547};
548
e9422e09 549static const unsigned short timedia_dual_port[] = {
1da177e4 550 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 551 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
552 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 553 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
554 0xD079, 0
555};
556
e9422e09 557static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 558 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
559 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 560 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
561 0xB157, 0
562};
563
e9422e09 564static const unsigned short timedia_eight_port[] = {
5756ee99 565 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 566 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
567};
568
cb3592be 569static const struct timedia_struct {
1da177e4 570 int num;
e9422e09 571 const unsigned short *ids;
1da177e4
LT		 572} timedia_data[] = {
573 { 1, timedia_single_port },
574 { 2, timedia_dual_port },
575 { 4, timedia_quad_port },
e9422e09 576 { 8, timedia_eight_port }
1da177e4
LT		 577};
578
b9b24558
FB		 579/*
580 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
581 * listing them individually, this driver merely grabs them all with
582 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
583 * and should be left free to be claimed by parport_serial instead.
584 */
585static int pci_timedia_probe(struct pci_dev *dev)
586{
587 /*
588 * Check the third digit of the subdevice ID
589 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
590 */
591 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
592 dev_info(&dev->dev,
593 "ignoring Timedia subdevice %04x for parport_serial\n",
594 dev->subsystem_device);
595 return -ENODEV;
596 }
597
598 return 0;
599}
600
61a116ef 601static int pci_timedia_init(struct pci_dev *dev)
1da177e4 602{
e9422e09 603 const unsigned short *ids;
1da177e4
LT		 604 int i, j;
605
e9422e09 606 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 607 ids = timedia_data[i].ids;
608 for (j = 0; ids[j]; j++)
609 if (dev->subsystem_device == ids[j])
610 return timedia_data[i].num;
611 }
612 return 0;
613}
614
615/*
616 * Timedia/SUNIX uses a mixture of BARs and offsets
617 * Ugh, this is ugly as all hell --- TYT
618 */
619static int
975a1a7d
RK		 620pci_timedia_setup(struct serial_private *priv,
621 const struct pciserial_board *board,
2655a2c7 622 struct uart_8250_port *port, int idx)
1da177e4
LT		 623{
624 unsigned int bar = 0, offset = board->first_offset;
625
626 switch (idx) {
627 case 0:
628 bar = 0;
629 break;
630 case 1:
631 offset = board->uart_offset;
632 bar = 0;
633 break;
634 case 2:
635 bar = 1;
636 break;
637 case 3:
638 offset = board->uart_offset;
c2cd6d3c 639 /* FALLTHROUGH */
1da177e4
LT		 640 case 4: /* BAR 2 */
641 case 5: /* BAR 3 */
642 case 6: /* BAR 4 */
643 case 7: /* BAR 5 */
644 bar = idx - 2;
645 }
646
70db3d91 647 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 648}
649
650/*
651 * Some Titan cards are also a little weird
652 */
653static int
70db3d91 654titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 655 const struct pciserial_board *board,
2655a2c7 656 struct uart_8250_port *port, int idx)
1da177e4
LT		 657{
658 unsigned int bar, offset = board->first_offset;
659
660 switch (idx) {
661 case 0:
662 bar = 1;
663 break;
664 case 1:
665 bar = 2;
666 break;
667 default:
668 bar = 4;
669 offset = (idx - 2) * board->uart_offset;
670 }
671
70db3d91 672 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 673}
674
61a116ef 675static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 676{
677 msleep(100);
678 return 0;
679}
680
04bf7e74
WP		 681static int pci_ni8420_init(struct pci_dev *dev)
682{
683 void __iomem *p;
684 unsigned long base, len;
685 unsigned int bar = 0;
686
687 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
688 moan_device("no memory in bar", dev);
689 return 0;
690 }
691
692 base = pci_resource_start(dev, bar);
693 len = pci_resource_len(dev, bar);
694 p = ioremap_nocache(base, len);
695 if (p == NULL)
696 return -ENOMEM;
697
698 /* Enable CPU Interrupt */
699 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
700 p + NI8420_INT_ENABLE_REG);
701
702 iounmap(p);
703 return 0;
704}
705
46a0fac9
SB		 706#define MITE_IOWBSR1_WSIZE 0xa
707#define MITE_IOWBSR1_WIN_OFFSET 0x800
708#define MITE_IOWBSR1_WENAB (1 << 7)
709#define MITE_LCIMR1_IO_IE_0 (1 << 24)
710#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
711#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
712
713static int pci_ni8430_init(struct pci_dev *dev)
714{
715 void __iomem *p;
716 unsigned long base, len;
717 u32 device_window;
718 unsigned int bar = 0;
719
720 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
721 moan_device("no memory in bar", dev);
722 return 0;
723 }
724
725 base = pci_resource_start(dev, bar);
726 len = pci_resource_len(dev, bar);
727 p = ioremap_nocache(base, len);
728 if (p == NULL)
729 return -ENOMEM;
730
731 /* Set device window address and size in BAR0 */
732 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
733 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
734 writel(device_window, p + MITE_IOWBSR1);
735
736 /* Set window access to go to RAMSEL IO address space */
737 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
738 p + MITE_IOWCR1);
739
740 /* Enable IO Bus Interrupt 0 */
741 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
742
743 /* Enable CPU Interrupt */
744 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
745
746 iounmap(p);
747 return 0;
748}
749
750/* UART Port Control Register */
751#define NI8430_PORTCON 0x0f
752#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
753
754static int
bf538fe4
AC		 755pci_ni8430_setup(struct serial_private *priv,
756 const struct pciserial_board *board,
2655a2c7 757 struct uart_8250_port *port, int idx)
46a0fac9
SB		 758{
759 void __iomem *p;
760 unsigned long base, len;
761 unsigned int bar, offset = board->first_offset;
762
763 if (idx >= board->num_ports)
764 return 1;
765
766 bar = FL_GET_BASE(board->flags);
767 offset += idx * board->uart_offset;
768
769 base = pci_resource_start(priv->dev, bar);
770 len = pci_resource_len(priv->dev, bar);
771 p = ioremap_nocache(base, len);
772
7c9d440e 773 /* enable the transceiver */
46a0fac9
SB		 774 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
775 p + offset + NI8430_PORTCON);
776
777 iounmap(p);
778
779 return setup_port(priv, port, bar, offset, board->reg_shift);
780}
781
7808edcd
NG		 782static int pci_netmos_9900_setup(struct serial_private *priv,
783 const struct pciserial_board *board,
2655a2c7 784 struct uart_8250_port *port, int idx)
7808edcd
NG		 785{
786 unsigned int bar;
787
788 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
789 /* netmos apparently orders BARs by datasheet layout, so serial
790 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
791 */
792 bar = 3 * idx;
793
794 return setup_port(priv, port, bar, 0, board->reg_shift);
795 } else {
796 return pci_default_setup(priv, board, port, idx);
797 }
798}
799
800/* the 99xx series comes with a range of device IDs and a variety
801 * of capabilities:
802 *
803 * 9900 has varying capabilities and can cascade to sub-controllers
804 * (cascading should be purely internal)
805 * 9904 is hardwired with 4 serial ports
806 * 9912 and 9922 are hardwired with 2 serial ports
807 */
808static int pci_netmos_9900_numports(struct pci_dev *dev)
809{
810 unsigned int c = dev->class;
811 unsigned int pi;
812 unsigned short sub_serports;
813
814 pi = (c & 0xff);
815
816 if (pi == 2) {
817 return 1;
818 } else if ((pi == 0) &&
819 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
820 /* two possibilities: 0x30ps encodes number of parallel and
821 * serial ports, or 0x1000 indicates *something*. This is not
822 * immediately obvious, since the 2s1p+4s configuration seems
823 * to offer all functionality on functions 0..2, while still
824 * advertising the same function 3 as the 4s+2s1p config.
825 */
826 sub_serports = dev->subsystem_device & 0xf;
827 if (sub_serports > 0) {
828 return sub_serports;
829 } else {
830 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
831 return 0;
832 }
833 }
834
835 moan_device("unknown NetMos/Mostech program interface", dev);
836 return 0;
837}
46a0fac9 838
61a116ef 839static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 840{
841 /* subdevice 0x00PS means <P> parallel, <S> serial */
842 unsigned int num_serial = dev->subsystem_device & 0xf;
843
ac6ec5b1
IS		 844 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
845 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 846 return 0;
7808edcd 847
25cf9bc1
JS		 848 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
849 dev->subsystem_device == 0x0299)
850 return 0;
851
7808edcd
NG		 852 switch (dev->device) { /* FALLTHROUGH on all */
853 case PCI_DEVICE_ID_NETMOS_9904:
854 case PCI_DEVICE_ID_NETMOS_9912:
855 case PCI_DEVICE_ID_NETMOS_9922:
856 case PCI_DEVICE_ID_NETMOS_9900:
857 num_serial = pci_netmos_9900_numports(dev);
858 break;
859
860 default:
861 if (num_serial == 0 ) {
862 moan_device("unknown NetMos/Mostech device", dev);
863 }
864 }
865
1da177e4
LT		 866 if (num_serial == 0)
867 return -ENODEV;
7808edcd 868
1da177e4
LT		 869 return num_serial;
870}
871
84f8c6fc 872/*
84f8c6fc
NV		 873 * These chips are available with optionally one parallel port and up to
874 * two serial ports. Unfortunately they all have the same product id.
875 *
876 * Basic configuration is done over a region of 32 I/O ports. The base
877 * ioport is called INTA or INTC, depending on docs/other drivers.
878 *
879 * The region of the 32 I/O ports is configured in POSIO0R...
880 */
881
882/* registers */
883#define ITE_887x_MISCR 0x9c
884#define ITE_887x_INTCBAR 0x78
885#define ITE_887x_UARTBAR 0x7c
886#define ITE_887x_PS0BAR 0x10
887#define ITE_887x_POSIO0 0x60
888
889/* I/O space size */
890#define ITE_887x_IOSIZE 32
891/* I/O space size (bits 26-24; 8 bytes = 011b) */
892#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
893/* I/O space size (bits 26-24; 32 bytes = 101b) */
894#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
895/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
896#define ITE_887x_POSIO_SPEED (3 << 29)
897/* enable IO_Space bit */
898#define ITE_887x_POSIO_ENABLE (1 << 31)
899
f79abb82 900static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 901{
902 /* inta_addr are the configuration addresses of the ITE */
903 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
904 0x200, 0x280, 0 };
905 int ret, i, type;
906 struct resource *iobase = NULL;
907 u32 miscr, uartbar, ioport;
908
909 /* search for the base-ioport */
910 i = 0;
911 while (inta_addr[i] && iobase == NULL) {
912 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
913 "ite887x");
914 if (iobase != NULL) {
915 /* write POSIO0R - speed | size | ioport */
916 pci_write_config_dword(dev, ITE_887x_POSIO0,
917 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
918 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
919 /* write INTCBAR - ioport */
5756ee99
AC		 920 pci_write_config_dword(dev, ITE_887x_INTCBAR,
921 inta_addr[i]);
84f8c6fc
NV		 922 ret = inb(inta_addr[i]);
923 if (ret != 0xff) {
924 /* ioport connected */
925 break;
926 }
927 release_region(iobase->start, ITE_887x_IOSIZE);
928 iobase = NULL;
929 }
930 i++;
931 }
932
933 if (!inta_addr[i]) {
934 printk(KERN_ERR "ite887x: could not find iobase\n");
935 return -ENODEV;
936 }
937
938 /* start of undocumented type checking (see parport_pc.c) */
939 type = inb(iobase->start + 0x18) & 0x0f;
940
941 switch (type) {
942 case 0x2: /* ITE8871 (1P) */
943 case 0xa: /* ITE8875 (1P) */
944 ret = 0;
945 break;
946 case 0xe: /* ITE8872 (2S1P) */
947 ret = 2;
948 break;
949 case 0x6: /* ITE8873 (1S) */
950 ret = 1;
951 break;
952 case 0x8: /* ITE8874 (2S) */
953 ret = 2;
954 break;
955 default:
956 moan_device("Unknown ITE887x", dev);
957 ret = -ENODEV;
958 }
959
960 /* configure all serial ports */
961 for (i = 0; i < ret; i++) {
962 /* read the I/O port from the device */
963 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
964 &ioport);
965 ioport &= 0x0000FF00; /* the actual base address */
966 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
967 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
968 ITE_887x_POSIO_IOSIZE_8 | ioport);
969
970 /* write the ioport to the UARTBAR */
971 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
972 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
973 uartbar |= (ioport << (16 * i)); /* set the ioport */
974 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
975
976 /* get current config */
977 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
978 /* disable interrupts (UARTx_Routing[3:0]) */
979 miscr &= ~(0xf << (12 - 4 * i));
980 /* activate the UART (UARTx_En) */
981 miscr |= 1 << (23 - i);
982 /* write new config with activated UART */
983 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
984 }
985
986 if (ret <= 0) {
987 /* the device has no UARTs if we get here */
988 release_region(iobase->start, ITE_887x_IOSIZE);
989 }
990
991 return ret;
992}
993
ae8d8a14 994static void pci_ite887x_exit(struct pci_dev *dev)
84f8c6fc
NV		 995{
996 u32 ioport;
997 /* the ioport is bit 0-15 in POSIO0R */
998 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
999 ioport &= 0xffff;
1000 release_region(ioport, ITE_887x_IOSIZE);
1001}
1002
9f2a036a
RK		 1003/*
1004 * Oxford Semiconductor Inc.
1005 * Check that device is part of the Tornado range of devices, then determine
1006 * the number of ports available on the device.
1007 */
1008static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1009{
1010 u8 __iomem *p;
1011 unsigned long deviceID;
1012 unsigned int number_uarts = 0;
1013
1014 /* OxSemi Tornado devices are all 0xCxxx */
1015 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1016 (dev->device & 0xF000) != 0xC000)
1017 return 0;
1018
1019 p = pci_iomap(dev, 0, 5);
1020 if (p == NULL)
1021 return -ENOMEM;
1022
1023 deviceID = ioread32(p);
1024 /* Tornado device */
1025 if (deviceID == 0x07000200) {
1026 number_uarts = ioread8(p + 4);
1027 printk(KERN_DEBUG
1028 "%d ports detected on Oxford PCI Express device\n",
1029 number_uarts);
1030 }
1031 pci_iounmap(dev, p);
1032 return number_uarts;
1033}
1034
eb26dfe8
AC		 1035static int pci_asix_setup(struct serial_private *priv,
1036 const struct pciserial_board *board,
1037 struct uart_8250_port *port, int idx)
1038{
1039 port->bugs |= UART_BUG_PARITY;
1040 return pci_default_setup(priv, board, port, idx);
1041}
1042
1043static int pci_default_setup(struct serial_private *priv,
975a1a7d 1044 const struct pciserial_board *board,
2655a2c7 1045 struct uart_8250_port *port, int idx)
1da177e4
LT		 1046{
1047 unsigned int bar, offset = board->first_offset, maxnr;
1048
1049 bar = FL_GET_BASE(board->flags);
1050 if (board->flags & FL_BASE_BARS)
1051 bar += idx;
1052 else
1053 offset += idx * board->uart_offset;
1054
2427ddd8
GKH		 1055 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1056 (board->reg_shift + 3);
1da177e4
LT		 1057
1058 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1059 return 1;
5756ee99 1060
70db3d91 1061 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 1062}
1063
095e24b0
DB		 1064static int
1065ce4100_serial_setup(struct serial_private *priv,
1066 const struct pciserial_board *board,
2655a2c7 1067 struct uart_8250_port *port, int idx)
095e24b0
DB		 1068{
1069 int ret;
1070
08ec212c 1071 ret = setup_port(priv, port, idx, 0, board->reg_shift);
2655a2c7
AC		 1072 port->port.iotype = UPIO_MEM32;
1073 port->port.type = PORT_XSCALE;
1074 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1075 port->port.regshift = 2;
095e24b0
DB		 1076
1077 return ret;
1078}
1079
d9a0fbfd
AP		 1080static int
1081pci_omegapci_setup(struct serial_private *priv,
1798ca13 1082 const struct pciserial_board *board,
2655a2c7 1083 struct uart_8250_port *port, int idx)
d9a0fbfd
AP		 1084{
1085 return setup_port(priv, port, 2, idx * 8, 0);
1086}
1087
b6adea33
MCC		 1088static int skip_tx_en_setup(struct serial_private *priv,
1089 const struct pciserial_board *board,
2655a2c7 1090 struct uart_8250_port *port, int idx)
b6adea33 1091{
2655a2c7 1092 port->port.flags |= UPF_NO_TXEN_TEST;
b6adea33
MCC		 1093 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1094 "[%04x:%04x] subsystem [%04x:%04x]\n",
1095 priv->dev->vendor,
1096 priv->dev->device,
1097 priv->dev->subsystem_vendor,
1098 priv->dev->subsystem_device);
1099
1100 return pci_default_setup(priv, board, port, idx);
1101}
1102
0ad372b9
SM		 1103static void kt_handle_break(struct uart_port *p)
1104{
1105 struct uart_8250_port *up =
1106 container_of(p, struct uart_8250_port, port);
1107 /*
1108 * On receipt of a BI, serial device in Intel ME (Intel
1109 * management engine) needs to have its fifos cleared for sane
1110 * SOL (Serial Over Lan) output.
1111 */
1112 serial8250_clear_and_reinit_fifos(up);
1113}
1114
1115static unsigned int kt_serial_in(struct uart_port *p, int offset)
1116{
1117 struct uart_8250_port *up =
1118 container_of(p, struct uart_8250_port, port);
1119 unsigned int val;
1120
1121 /*
1122 * When the Intel ME (management engine) gets reset its serial
1123 * port registers could return 0 momentarily. Functions like
1124 * serial8250_console_write, read and save the IER, perform
1125 * some operation and then restore it. In order to avoid
1126 * setting IER register inadvertently to 0, if the value read
1127 * is 0, double check with ier value in uart_8250_port and use
1128 * that instead. up->ier should be the same value as what is
1129 * currently configured.
1130 */
1131 val = inb(p->iobase + offset);
1132 if (offset == UART_IER) {
1133 if (val == 0)
1134 val = up->ier;
1135 }
1136 return val;
1137}
1138
bc02d15a
DW		 1139static int kt_serial_setup(struct serial_private *priv,
1140 const struct pciserial_board *board,
2655a2c7 1141 struct uart_8250_port *port, int idx)
bc02d15a 1142{
2655a2c7
AC		 1143 port->port.flags |= UPF_BUG_THRE;
1144 port->port.serial_in = kt_serial_in;
1145 port->port.handle_break = kt_handle_break;
bc02d15a
DW		 1146 return skip_tx_en_setup(priv, board, port, idx);
1147}
1148
eb7073db
TM		 1149static int pci_eg20t_init(struct pci_dev *dev)
1150{
1151#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1152 return -ENODEV;
1153#else
1154 return 0;
1155#endif
1156}
1157
06315348
SH		 1158static int
1159pci_xr17c154_setup(struct serial_private *priv,
1160 const struct pciserial_board *board,
2655a2c7 1161 struct uart_8250_port *port, int idx)
06315348 1162{
2655a2c7 1163 port->port.flags |= UPF_EXAR_EFR;
06315348
SH		 1164 return pci_default_setup(priv, board, port, idx);
1165}
1166
dc96efb7
MS		 1167static int
1168pci_xr17v35x_setup(struct serial_private *priv,
1169 const struct pciserial_board *board,
1170 struct uart_8250_port *port, int idx)
1171{
1172 u8 __iomem *p;
1173
1174 p = pci_ioremap_bar(priv->dev, 0);
1175
1176 port->port.flags |= UPF_EXAR_EFR;
1177
1178 /*
1179 * Setup Multipurpose Input/Output pins.
1180 */
1181 if (idx == 0) {
1182 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1183 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1184 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1185 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1186 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1187 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1188 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1189 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1190 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1191 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1192 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1193 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1194 }
f965b9c4
MS		 1195 writeb(0x00, p + UART_EXAR_8XMODE);
1196 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1197 writeb(128, p + UART_EXAR_TXTRG);
1198 writeb(128, p + UART_EXAR_RXTRG);
dc96efb7
MS		 1199 iounmap(p);
1200
1201 return pci_default_setup(priv, board, port, idx);
1202}
1203
6971c635
GA		 1204static int
1205pci_wch_ch353_setup(struct serial_private *priv,
1206 const struct pciserial_board *board,
1207 struct uart_8250_port *port, int idx)
1208{
1209 port->port.flags |= UPF_FIXED_TYPE;
1210 port->port.type = PORT_16550A;
06315348
SH		 1211 return pci_default_setup(priv, board, port, idx);
1212}
1213
1da177e4
LT		 1214#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1215#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1216#define PCI_DEVICE_ID_OCTPRO 0x0001
1217#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1218#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1219#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1220#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
26e8220a
FL		 1221#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1222#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
78d70d48 1223#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 1224#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 1225#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
66169ad1
YY		 1226#define PCI_DEVICE_ID_TITAN_200I 0x8028
1227#define PCI_DEVICE_ID_TITAN_400I 0x8048
1228#define PCI_DEVICE_ID_TITAN_800I 0x8088
1229#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1230#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1231#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1232#define PCI_DEVICE_ID_TITAN_100E 0xA010
1233#define PCI_DEVICE_ID_TITAN_200E 0xA012
1234#define PCI_DEVICE_ID_TITAN_400E 0xA013
1235#define PCI_DEVICE_ID_TITAN_800E 0xA014
1236#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1237#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1e9deb11
YY		 1238#define PCI_DEVICE_ID_TITAN_400V3 0xA310
1239#define PCI_DEVICE_ID_TITAN_410V3 0xA312
1240#define PCI_DEVICE_ID_TITAN_800V3 0xA314
1241#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
e847003f 1242#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 1243#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
d9a0fbfd 1244#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
bc02d15a 1245#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
27788c5f
AC		 1246#define PCI_VENDOR_ID_WCH 0x4348
1247#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1248#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1249#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
6683549e
AC		 1250#define PCI_VENDOR_ID_AGESTAR 0x5372
1251#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
eb26dfe8 1252#define PCI_VENDOR_ID_ASIX 0x9710
1da177e4 1253
b76c5a07
CB		 1254/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1255#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1256
1da177e4
LT		 1257/*
1258 * Master list of serial port init/setup/exit quirks.
1259 * This does not describe the general nature of the port.
1260 * (ie, baud base, number and location of ports, etc)
1261 *
1262 * This list is ordered alphabetically by vendor then device.
1263 * Specific entries must come before more generic entries.
1264 */
7a63ce5a 1265static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 1266 /*
1267 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1268 */
1269 {
1270 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1271 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1272 .subvendor = PCI_ANY_ID,
1273 .subdevice = PCI_ANY_ID,
1274 .setup = addidata_apci7800_setup,
1275 },
1da177e4 1276 /*
61a116ef 1277 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 1278 * It is not clear whether this applies to all products.
1279 */
1280 {
1281 .vendor = PCI_VENDOR_ID_AFAVLAB,
1282 .device = PCI_ANY_ID,
1283 .subvendor = PCI_ANY_ID,
1284 .subdevice = PCI_ANY_ID,
1285 .setup = afavlab_setup,
1286 },
1287 /*
1288 * HP Diva
1289 */
1290 {
1291 .vendor = PCI_VENDOR_ID_HP,
1292 .device = PCI_DEVICE_ID_HP_DIVA,
1293 .subvendor = PCI_ANY_ID,
1294 .subdevice = PCI_ANY_ID,
1295 .init = pci_hp_diva_init,
1296 .setup = pci_hp_diva_setup,
1297 },
1298 /*
1299 * Intel
1300 */
1301 {
1302 .vendor = PCI_VENDOR_ID_INTEL,
1303 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1304 .subvendor = 0xe4bf,
1305 .subdevice = PCI_ANY_ID,
1306 .init = pci_inteli960ni_init,
1307 .setup = pci_default_setup,
1308 },
b6adea33
MCC		 1309 {
1310 .vendor = PCI_VENDOR_ID_INTEL,
1311 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1312 .subvendor = PCI_ANY_ID,
1313 .subdevice = PCI_ANY_ID,
1314 .setup = skip_tx_en_setup,
1315 },
1316 {
1317 .vendor = PCI_VENDOR_ID_INTEL,
1318 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1319 .subvendor = PCI_ANY_ID,
1320 .subdevice = PCI_ANY_ID,
1321 .setup = skip_tx_en_setup,
1322 },
1323 {
1324 .vendor = PCI_VENDOR_ID_INTEL,
1325 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1326 .subvendor = PCI_ANY_ID,
1327 .subdevice = PCI_ANY_ID,
1328 .setup = skip_tx_en_setup,
1329 },
095e24b0
DB		 1330 {
1331 .vendor = PCI_VENDOR_ID_INTEL,
1332 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1333 .subvendor = PCI_ANY_ID,
1334 .subdevice = PCI_ANY_ID,
1335 .setup = ce4100_serial_setup,
1336 },
bc02d15a
DW		 1337 {
1338 .vendor = PCI_VENDOR_ID_INTEL,
1339 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1340 .subvendor = PCI_ANY_ID,
1341 .subdevice = PCI_ANY_ID,
1342 .setup = kt_serial_setup,
1343 },
84f8c6fc
NV		 1344 /*
1345 * ITE
1346 */
1347 {
1348 .vendor = PCI_VENDOR_ID_ITE,
1349 .device = PCI_DEVICE_ID_ITE_8872,
1350 .subvendor = PCI_ANY_ID,
1351 .subdevice = PCI_ANY_ID,
1352 .init = pci_ite887x_init,
1353 .setup = pci_default_setup,
2d47b716 1354 .exit = pci_ite887x_exit,
84f8c6fc 1355 },
46a0fac9
SB		 1356 /*
1357 * National Instruments
1358 */
04bf7e74
WP		 1359 {
1360 .vendor = PCI_VENDOR_ID_NI,
1361 .device = PCI_DEVICE_ID_NI_PCI23216,
1362 .subvendor = PCI_ANY_ID,
1363 .subdevice = PCI_ANY_ID,
1364 .init = pci_ni8420_init,
1365 .setup = pci_default_setup,
2d47b716 1366 .exit = pci_ni8420_exit,
04bf7e74
WP		 1367 },
1368 {
1369 .vendor = PCI_VENDOR_ID_NI,
1370 .device = PCI_DEVICE_ID_NI_PCI2328,
1371 .subvendor = PCI_ANY_ID,
1372 .subdevice = PCI_ANY_ID,
1373 .init = pci_ni8420_init,
1374 .setup = pci_default_setup,
2d47b716 1375 .exit = pci_ni8420_exit,
04bf7e74
WP		 1376 },
1377 {
1378 .vendor = PCI_VENDOR_ID_NI,
1379 .device = PCI_DEVICE_ID_NI_PCI2324,
1380 .subvendor = PCI_ANY_ID,
1381 .subdevice = PCI_ANY_ID,
1382 .init = pci_ni8420_init,
1383 .setup = pci_default_setup,
2d47b716 1384 .exit = pci_ni8420_exit,
04bf7e74
WP		 1385 },
1386 {
1387 .vendor = PCI_VENDOR_ID_NI,
1388 .device = PCI_DEVICE_ID_NI_PCI2322,
1389 .subvendor = PCI_ANY_ID,
1390 .subdevice = PCI_ANY_ID,
1391 .init = pci_ni8420_init,
1392 .setup = pci_default_setup,
2d47b716 1393 .exit = pci_ni8420_exit,
04bf7e74
WP		 1394 },
1395 {
1396 .vendor = PCI_VENDOR_ID_NI,
1397 .device = PCI_DEVICE_ID_NI_PCI2324I,
1398 .subvendor = PCI_ANY_ID,
1399 .subdevice = PCI_ANY_ID,
1400 .init = pci_ni8420_init,
1401 .setup = pci_default_setup,
2d47b716 1402 .exit = pci_ni8420_exit,
04bf7e74
WP		 1403 },
1404 {
1405 .vendor = PCI_VENDOR_ID_NI,
1406 .device = PCI_DEVICE_ID_NI_PCI2322I,
1407 .subvendor = PCI_ANY_ID,
1408 .subdevice = PCI_ANY_ID,
1409 .init = pci_ni8420_init,
1410 .setup = pci_default_setup,
2d47b716 1411 .exit = pci_ni8420_exit,
04bf7e74
WP		 1412 },
1413 {
1414 .vendor = PCI_VENDOR_ID_NI,
1415 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1416 .subvendor = PCI_ANY_ID,
1417 .subdevice = PCI_ANY_ID,
1418 .init = pci_ni8420_init,
1419 .setup = pci_default_setup,
2d47b716 1420 .exit = pci_ni8420_exit,
04bf7e74
WP		 1421 },
1422 {
1423 .vendor = PCI_VENDOR_ID_NI,
1424 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1425 .subvendor = PCI_ANY_ID,
1426 .subdevice = PCI_ANY_ID,
1427 .init = pci_ni8420_init,
1428 .setup = pci_default_setup,
2d47b716 1429 .exit = pci_ni8420_exit,
04bf7e74
WP		 1430 },
1431 {
1432 .vendor = PCI_VENDOR_ID_NI,
1433 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1434 .subvendor = PCI_ANY_ID,
1435 .subdevice = PCI_ANY_ID,
1436 .init = pci_ni8420_init,
1437 .setup = pci_default_setup,
2d47b716 1438 .exit = pci_ni8420_exit,
04bf7e74
WP		 1439 },
1440 {
1441 .vendor = PCI_VENDOR_ID_NI,
1442 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1443 .subvendor = PCI_ANY_ID,
1444 .subdevice = PCI_ANY_ID,
1445 .init = pci_ni8420_init,
1446 .setup = pci_default_setup,
2d47b716 1447 .exit = pci_ni8420_exit,
04bf7e74
WP		 1448 },
1449 {
1450 .vendor = PCI_VENDOR_ID_NI,
1451 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1452 .subvendor = PCI_ANY_ID,
1453 .subdevice = PCI_ANY_ID,
1454 .init = pci_ni8420_init,
1455 .setup = pci_default_setup,
2d47b716 1456 .exit = pci_ni8420_exit,
04bf7e74
WP		 1457 },
1458 {
1459 .vendor = PCI_VENDOR_ID_NI,
1460 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1461 .subvendor = PCI_ANY_ID,
1462 .subdevice = PCI_ANY_ID,
1463 .init = pci_ni8420_init,
1464 .setup = pci_default_setup,
2d47b716 1465 .exit = pci_ni8420_exit,
04bf7e74 1466 },
46a0fac9
SB		 1467 {
1468 .vendor = PCI_VENDOR_ID_NI,
1469 .device = PCI_ANY_ID,
1470 .subvendor = PCI_ANY_ID,
1471 .subdevice = PCI_ANY_ID,
1472 .init = pci_ni8430_init,
1473 .setup = pci_ni8430_setup,
2d47b716 1474 .exit = pci_ni8430_exit,
46a0fac9 1475 },
1da177e4
LT		 1476 /*
1477 * Panacom
1478 */
1479 {
1480 .vendor = PCI_VENDOR_ID_PANACOM,
1481 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1482 .subvendor = PCI_ANY_ID,
1483 .subdevice = PCI_ANY_ID,
1484 .init = pci_plx9050_init,
1485 .setup = pci_default_setup,
2d47b716 1486 .exit = pci_plx9050_exit,
5756ee99 1487 },
1da177e4
LT		 1488 {
1489 .vendor = PCI_VENDOR_ID_PANACOM,
1490 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1491 .subvendor = PCI_ANY_ID,
1492 .subdevice = PCI_ANY_ID,
1493 .init = pci_plx9050_init,
1494 .setup = pci_default_setup,
2d47b716 1495 .exit = pci_plx9050_exit,
1da177e4
LT		 1496 },
1497 /*
1498 * PLX
1499 */
48212008
TH		 1500 {
1501 .vendor = PCI_VENDOR_ID_PLX,
1502 .device = PCI_DEVICE_ID_PLX_9030,
1503 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1504 .subdevice = PCI_ANY_ID,
1505 .setup = pci_default_setup,
1506 },
add7b58e
BH		 1507 {
1508 .vendor = PCI_VENDOR_ID_PLX,
1509 .device = PCI_DEVICE_ID_PLX_9050,
1510 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1511 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1512 .init = pci_plx9050_init,
1513 .setup = pci_default_setup,
2d47b716 1514 .exit = pci_plx9050_exit,
add7b58e 1515 },
1da177e4
LT		 1516 {
1517 .vendor = PCI_VENDOR_ID_PLX,
1518 .device = PCI_DEVICE_ID_PLX_9050,
1519 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1520 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1521 .init = pci_plx9050_init,
1522 .setup = pci_default_setup,
2d47b716 1523 .exit = pci_plx9050_exit,
1da177e4 1524 },
b76c5a07
CB		 1525 {
1526 .vendor = PCI_VENDOR_ID_PLX,
1527 .device = PCI_DEVICE_ID_PLX_9050,
1528 .subvendor = PCI_VENDOR_ID_PLX,
1529 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1530 .init = pci_plx9050_init,
1531 .setup = pci_default_setup,
2d47b716 1532 .exit = pci_plx9050_exit,
b76c5a07 1533 },
1da177e4
LT		 1534 {
1535 .vendor = PCI_VENDOR_ID_PLX,
1536 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1537 .subvendor = PCI_VENDOR_ID_PLX,
1538 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1539 .init = pci_plx9050_init,
1540 .setup = pci_default_setup,
2d47b716 1541 .exit = pci_plx9050_exit,
1da177e4
LT		 1542 },
1543 /*
1544 * SBS Technologies, Inc., PMC-OCTALPRO 232
1545 */
1546 {
1547 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1548 .device = PCI_DEVICE_ID_OCTPRO,
1549 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1550 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1551 .init = sbs_init,
1552 .setup = sbs_setup,
2d47b716 1553 .exit = sbs_exit,
1da177e4
LT		 1554 },
1555 /*
1556 * SBS Technologies, Inc., PMC-OCTALPRO 422
1557 */
1558 {
1559 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1560 .device = PCI_DEVICE_ID_OCTPRO,
1561 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1562 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1563 .init = sbs_init,
1564 .setup = sbs_setup,
2d47b716 1565 .exit = sbs_exit,
1da177e4
LT		 1566 },
1567 /*
1568 * SBS Technologies, Inc., P-Octal 232
1569 */
1570 {
1571 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1572 .device = PCI_DEVICE_ID_OCTPRO,
1573 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1574 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1575 .init = sbs_init,
1576 .setup = sbs_setup,
2d47b716 1577 .exit = sbs_exit,
1da177e4
LT		 1578 },
1579 /*
1580 * SBS Technologies, Inc., P-Octal 422
1581 */
1582 {
1583 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1584 .device = PCI_DEVICE_ID_OCTPRO,
1585 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1586 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1587 .init = sbs_init,
1588 .setup = sbs_setup,
2d47b716 1589 .exit = sbs_exit,
1da177e4 1590 },
1da177e4 1591 /*
61a116ef 1592 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 1593 */
1594 {
1595 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 1596 .device = PCI_ANY_ID,
1da177e4
LT		 1597 .subvendor = PCI_ANY_ID,
1598 .subdevice = PCI_ANY_ID,
67d74b87 1599 .init = pci_siig_init,
3ec9c594 1600 .setup = pci_siig_setup,
1da177e4
LT		 1601 },
1602 /*
1603 * Titan cards
1604 */
1605 {
1606 .vendor = PCI_VENDOR_ID_TITAN,
1607 .device = PCI_DEVICE_ID_TITAN_400L,
1608 .subvendor = PCI_ANY_ID,
1609 .subdevice = PCI_ANY_ID,
1610 .setup = titan_400l_800l_setup,
1611 },
1612 {
1613 .vendor = PCI_VENDOR_ID_TITAN,
1614 .device = PCI_DEVICE_ID_TITAN_800L,
1615 .subvendor = PCI_ANY_ID,
1616 .subdevice = PCI_ANY_ID,
1617 .setup = titan_400l_800l_setup,
1618 },
1619 /*
1620 * Timedia cards
1621 */
1622 {
1623 .vendor = PCI_VENDOR_ID_TIMEDIA,
1624 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1625 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1626 .subdevice = PCI_ANY_ID,
b9b24558 1627 .probe = pci_timedia_probe,
1da177e4
LT		 1628 .init = pci_timedia_init,
1629 .setup = pci_timedia_setup,
1630 },
1631 {
1632 .vendor = PCI_VENDOR_ID_TIMEDIA,
1633 .device = PCI_ANY_ID,
1634 .subvendor = PCI_ANY_ID,
1635 .subdevice = PCI_ANY_ID,
1636 .setup = pci_timedia_setup,
1637 },
06315348
SH		 1638 /*
1639 * Exar cards
1640 */
1641 {
1642 .vendor = PCI_VENDOR_ID_EXAR,
1643 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1644 .subvendor = PCI_ANY_ID,
1645 .subdevice = PCI_ANY_ID,
1646 .setup = pci_xr17c154_setup,
1647 },
1648 {
1649 .vendor = PCI_VENDOR_ID_EXAR,
1650 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1651 .subvendor = PCI_ANY_ID,
1652 .subdevice = PCI_ANY_ID,
1653 .setup = pci_xr17c154_setup,
1654 },
1655 {
1656 .vendor = PCI_VENDOR_ID_EXAR,
1657 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1658 .subvendor = PCI_ANY_ID,
1659 .subdevice = PCI_ANY_ID,
1660 .setup = pci_xr17c154_setup,
1661 },
dc96efb7
MS		 1662 {
1663 .vendor = PCI_VENDOR_ID_EXAR,
1664 .device = PCI_DEVICE_ID_EXAR_XR17V352,
1665 .subvendor = PCI_ANY_ID,
1666 .subdevice = PCI_ANY_ID,
1667 .setup = pci_xr17v35x_setup,
1668 },
1669 {
1670 .vendor = PCI_VENDOR_ID_EXAR,
1671 .device = PCI_DEVICE_ID_EXAR_XR17V354,
1672 .subvendor = PCI_ANY_ID,
1673 .subdevice = PCI_ANY_ID,
1674 .setup = pci_xr17v35x_setup,
1675 },
1676 {
1677 .vendor = PCI_VENDOR_ID_EXAR,
1678 .device = PCI_DEVICE_ID_EXAR_XR17V358,
1679 .subvendor = PCI_ANY_ID,
1680 .subdevice = PCI_ANY_ID,
1681 .setup = pci_xr17v35x_setup,
1682 },
1da177e4
LT		 1683 /*
1684 * Xircom cards
1685 */
1686 {
1687 .vendor = PCI_VENDOR_ID_XIRCOM,
1688 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1689 .subvendor = PCI_ANY_ID,
1690 .subdevice = PCI_ANY_ID,
1691 .init = pci_xircom_init,
1692 .setup = pci_default_setup,
1693 },
1694 /*
61a116ef 1695 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 1696 */
1697 {
1698 .vendor = PCI_VENDOR_ID_NETMOS,
1699 .device = PCI_ANY_ID,
1700 .subvendor = PCI_ANY_ID,
1701 .subdevice = PCI_ANY_ID,
1702 .init = pci_netmos_init,
7808edcd 1703 .setup = pci_netmos_9900_setup,
1da177e4 1704 },
9f2a036a 1705 /*
aa273ae5 1706 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 1707 */
1708 {
1709 .vendor = PCI_VENDOR_ID_OXSEMI,
1710 .device = PCI_ANY_ID,
1711 .subvendor = PCI_ANY_ID,
1712 .subdevice = PCI_ANY_ID,
1713 .init = pci_oxsemi_tornado_init,
1714 .setup = pci_default_setup,
1715 },
1716 {
1717 .vendor = PCI_VENDOR_ID_MAINPINE,
1718 .device = PCI_ANY_ID,
1719 .subvendor = PCI_ANY_ID,
1720 .subdevice = PCI_ANY_ID,
1721 .init = pci_oxsemi_tornado_init,
1722 .setup = pci_default_setup,
1723 },
aa273ae5
SK		 1724 {
1725 .vendor = PCI_VENDOR_ID_DIGI,
1726 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1727 .subvendor = PCI_SUBVENDOR_ID_IBM,
1728 .subdevice = PCI_ANY_ID,
1729 .init = pci_oxsemi_tornado_init,
1730 .setup = pci_default_setup,
1731 },
eb7073db
TM		 1732 {
1733 .vendor = PCI_VENDOR_ID_INTEL,
1734 .device = 0x8811,
aaa10eb1
AP		 1735 .subvendor = PCI_ANY_ID,
1736 .subdevice = PCI_ANY_ID,
eb7073db 1737 .init = pci_eg20t_init,
64d91cfa 1738 .setup = pci_default_setup,
eb7073db
TM		 1739 },
1740 {
1741 .vendor = PCI_VENDOR_ID_INTEL,
1742 .device = 0x8812,
aaa10eb1
AP		 1743 .subvendor = PCI_ANY_ID,
1744 .subdevice = PCI_ANY_ID,
eb7073db 1745 .init = pci_eg20t_init,
64d91cfa 1746 .setup = pci_default_setup,
eb7073db
TM		 1747 },
1748 {
1749 .vendor = PCI_VENDOR_ID_INTEL,
1750 .device = 0x8813,
aaa10eb1
AP		 1751 .subvendor = PCI_ANY_ID,
1752 .subdevice = PCI_ANY_ID,
eb7073db 1753 .init = pci_eg20t_init,
64d91cfa 1754 .setup = pci_default_setup,
eb7073db
TM		 1755 },
1756 {
1757 .vendor = PCI_VENDOR_ID_INTEL,
1758 .device = 0x8814,
aaa10eb1
AP		 1759 .subvendor = PCI_ANY_ID,
1760 .subdevice = PCI_ANY_ID,
eb7073db 1761 .init = pci_eg20t_init,
64d91cfa 1762 .setup = pci_default_setup,
eb7073db
TM		 1763 },
1764 {
1765 .vendor = 0x10DB,
1766 .device = 0x8027,
aaa10eb1
AP		 1767 .subvendor = PCI_ANY_ID,
1768 .subdevice = PCI_ANY_ID,
eb7073db 1769 .init = pci_eg20t_init,
64d91cfa 1770 .setup = pci_default_setup,
eb7073db
TM		 1771 },
1772 {
1773 .vendor = 0x10DB,
1774 .device = 0x8028,
aaa10eb1
AP		 1775 .subvendor = PCI_ANY_ID,
1776 .subdevice = PCI_ANY_ID,
eb7073db 1777 .init = pci_eg20t_init,
64d91cfa 1778 .setup = pci_default_setup,
eb7073db
TM		 1779 },
1780 {
1781 .vendor = 0x10DB,
1782 .device = 0x8029,
aaa10eb1
AP		 1783 .subvendor = PCI_ANY_ID,
1784 .subdevice = PCI_ANY_ID,
eb7073db 1785 .init = pci_eg20t_init,
64d91cfa 1786 .setup = pci_default_setup,
eb7073db
TM		 1787 },
1788 {
1789 .vendor = 0x10DB,
1790 .device = 0x800C,
aaa10eb1
AP		 1791 .subvendor = PCI_ANY_ID,
1792 .subdevice = PCI_ANY_ID,
eb7073db 1793 .init = pci_eg20t_init,
64d91cfa 1794 .setup = pci_default_setup,
eb7073db
TM		 1795 },
1796 {
1797 .vendor = 0x10DB,
1798 .device = 0x800D,
aaa10eb1
AP		 1799 .subvendor = PCI_ANY_ID,
1800 .subdevice = PCI_ANY_ID,
eb7073db 1801 .init = pci_eg20t_init,
64d91cfa 1802 .setup = pci_default_setup,
eb7073db 1803 },
d9a0fbfd
AP		 1804 /*
1805 * Cronyx Omega PCI (PLX-chip based)
1806 */
1807 {
1808 .vendor = PCI_VENDOR_ID_PLX,
1809 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1810 .subvendor = PCI_ANY_ID,
1811 .subdevice = PCI_ANY_ID,
1812 .setup = pci_omegapci_setup,
eb26dfe8 1813 },
6971c635
GA		 1814 /* WCH CH353 2S1P card (16550 clone) */
1815 {
27788c5f
AC		 1816 .vendor = PCI_VENDOR_ID_WCH,
1817 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
1818 .subvendor = PCI_ANY_ID,
1819 .subdevice = PCI_ANY_ID,
1820 .setup = pci_wch_ch353_setup,
1821 },
1822 /* WCH CH353 4S card (16550 clone) */
1823 {
1824 .vendor = PCI_VENDOR_ID_WCH,
1825 .device = PCI_DEVICE_ID_WCH_CH353_4S,
1826 .subvendor = PCI_ANY_ID,
1827 .subdevice = PCI_ANY_ID,
1828 .setup = pci_wch_ch353_setup,
1829 },
1830 /* WCH CH353 2S1PF card (16550 clone) */
1831 {
1832 .vendor = PCI_VENDOR_ID_WCH,
1833 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
1834 .subvendor = PCI_ANY_ID,
1835 .subdevice = PCI_ANY_ID,
6971c635
GA		 1836 .setup = pci_wch_ch353_setup,
1837 },
eb26dfe8
AC		 1838 /*
1839 * ASIX devices with FIFO bug
1840 */
1841 {
1842 .vendor = PCI_VENDOR_ID_ASIX,
1843 .device = PCI_ANY_ID,
1844 .subvendor = PCI_ANY_ID,
1845 .subdevice = PCI_ANY_ID,
1846 .setup = pci_asix_setup,
1847 },
1da177e4
LT		 1848 /*
1849 * Default "match everything" terminator entry
1850 */
1851 {
1852 .vendor = PCI_ANY_ID,
1853 .device = PCI_ANY_ID,
1854 .subvendor = PCI_ANY_ID,
1855 .subdevice = PCI_ANY_ID,
1856 .setup = pci_default_setup,
1857 }
1858};
1859
1860static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1861{
1862 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1863}
1864
1865static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1866{
1867 struct pci_serial_quirk *quirk;
1868
1869 for (quirk = pci_serial_quirks; ; quirk++)
1870 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1871 quirk_id_matches(quirk->device, dev->device) &&
1872 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1873 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 1874 break;
1da177e4
LT		 1875 return quirk;
1876}
1877
dd68e88c 1878static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 1879 const struct pciserial_board *board)
1da177e4
LT		 1880{
1881 if (board->flags & FL_NOIRQ)
1882 return 0;
1883 else
1884 return dev->irq;
1885}
1886
1887/*
1888 * This is the configuration table for all of the PCI serial boards
1889 * which we support. It is directly indexed by the pci_board_num_t enum
1890 * value, which is encoded in the pci_device_id PCI probe table's
1891 * driver_data member.
1892 *
1893 * The makeup of these names are:
26e92861 1894 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 1895 *
26e92861
GH		 1896 * bn = PCI BAR number
1897 * bt = Index using PCI BARs
1898 * n = number of serial ports
1899 * baud = baud rate
1900 * offsetinhex = offset for each sequential port (in hex)
1da177e4 1901 *
26e92861 1902 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 1903 *
1da177e4
LT		 1904 * Please note: in theory if n = 1, _bt infix should make no difference.
1905 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1906 */
1907enum pci_board_num_t {
1908 pbn_default = 0,
1909
1910 pbn_b0_1_115200,
1911 pbn_b0_2_115200,
1912 pbn_b0_4_115200,
1913 pbn_b0_5_115200,
bf0df636 1914 pbn_b0_8_115200,
1da177e4
LT		 1915
1916 pbn_b0_1_921600,
1917 pbn_b0_2_921600,
1918 pbn_b0_4_921600,
1919
db1de159
DR		 1920 pbn_b0_2_1130000,
1921
fbc0dc0d
AP		 1922 pbn_b0_4_1152000,
1923
26e92861
GH		 1924 pbn_b0_2_1843200,
1925 pbn_b0_4_1843200,
1926
1927 pbn_b0_2_1843200_200,
1928 pbn_b0_4_1843200_200,
1929 pbn_b0_8_1843200_200,
1930
7106b4e3
LH		 1931 pbn_b0_1_4000000,
1932
1da177e4
LT		 1933 pbn_b0_bt_1_115200,
1934 pbn_b0_bt_2_115200,
ac6ec5b1 1935 pbn_b0_bt_4_115200,
1da177e4
LT		 1936 pbn_b0_bt_8_115200,
1937
1938 pbn_b0_bt_1_460800,
1939 pbn_b0_bt_2_460800,
1940 pbn_b0_bt_4_460800,
1941
1942 pbn_b0_bt_1_921600,
1943 pbn_b0_bt_2_921600,
1944 pbn_b0_bt_4_921600,
1945 pbn_b0_bt_8_921600,
1946
1947 pbn_b1_1_115200,
1948 pbn_b1_2_115200,
1949 pbn_b1_4_115200,
1950 pbn_b1_8_115200,
04bf7e74 1951 pbn_b1_16_115200,
1da177e4
LT		 1952
1953 pbn_b1_1_921600,
1954 pbn_b1_2_921600,
1955 pbn_b1_4_921600,
1956 pbn_b1_8_921600,
1957
26e92861
GH		 1958 pbn_b1_2_1250000,
1959
84f8c6fc 1960 pbn_b1_bt_1_115200,
04bf7e74
WP		 1961 pbn_b1_bt_2_115200,
1962 pbn_b1_bt_4_115200,
1963
1da177e4
LT		 1964 pbn_b1_bt_2_921600,
1965
1966 pbn_b1_1_1382400,
1967 pbn_b1_2_1382400,
1968 pbn_b1_4_1382400,
1969 pbn_b1_8_1382400,
1970
1971 pbn_b2_1_115200,
737c1756 1972 pbn_b2_2_115200,
a9cccd34 1973 pbn_b2_4_115200,
1da177e4
LT		 1974 pbn_b2_8_115200,
1975
1976 pbn_b2_1_460800,
1977 pbn_b2_4_460800,
1978 pbn_b2_8_460800,
1979 pbn_b2_16_460800,
1980
1981 pbn_b2_1_921600,
1982 pbn_b2_4_921600,
1983 pbn_b2_8_921600,
1984
e847003f
LB		 1985 pbn_b2_8_1152000,
1986
1da177e4
LT		 1987 pbn_b2_bt_1_115200,
1988 pbn_b2_bt_2_115200,
1989 pbn_b2_bt_4_115200,
1990
1991 pbn_b2_bt_2_921600,
1992 pbn_b2_bt_4_921600,
1993
d9004eb4 1994 pbn_b3_2_115200,
1da177e4
LT		 1995 pbn_b3_4_115200,
1996 pbn_b3_8_115200,
1997
66169ad1
YY		 1998 pbn_b4_bt_2_921600,
1999 pbn_b4_bt_4_921600,
2000 pbn_b4_bt_8_921600,
2001
1da177e4
LT		 2002 /*
2003 * Board-specific versions.
2004 */
2005 pbn_panacom,
2006 pbn_panacom2,
2007 pbn_panacom4,
2008 pbn_plx_romulus,
2009 pbn_oxsemi,
7106b4e3
LH		 2010 pbn_oxsemi_1_4000000,
2011 pbn_oxsemi_2_4000000,
2012 pbn_oxsemi_4_4000000,
2013 pbn_oxsemi_8_4000000,
1da177e4
LT		 2014 pbn_intel_i960,
2015 pbn_sgi_ioc3,
1da177e4
LT		 2016 pbn_computone_4,
2017 pbn_computone_6,
2018 pbn_computone_8,
2019 pbn_sbsxrsio,
2020 pbn_exar_XR17C152,
2021 pbn_exar_XR17C154,
2022 pbn_exar_XR17C158,
dc96efb7
MS		 2023 pbn_exar_XR17V352,
2024 pbn_exar_XR17V354,
2025 pbn_exar_XR17V358,
c68d2b15 2026 pbn_exar_ibm_saturn,
aa798505 2027 pbn_pasemi_1682M,
46a0fac9
SB		 2028 pbn_ni8430_2,
2029 pbn_ni8430_4,
2030 pbn_ni8430_8,
2031 pbn_ni8430_16,
1b62cbf2
KJ		 2032 pbn_ADDIDATA_PCIe_1_3906250,
2033 pbn_ADDIDATA_PCIe_2_3906250,
2034 pbn_ADDIDATA_PCIe_4_3906250,
2035 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 2036 pbn_ce4100_1_115200,
d9a0fbfd 2037 pbn_omegapci,
7808edcd 2038 pbn_NETMOS9900_2s_115200,
1da177e4
LT		 2039};
2040
2041/*
2042 * uart_offset - the space between channels
2043 * reg_shift - describes how the UART registers are mapped
2044 * to PCI memory by the card.
2045 * For example IER register on SBS, Inc. PMC-OctPro is located at
2046 * offset 0x10 from the UART base, while UART_IER is defined as 1
2047 * in include/linux/serial_reg.h,
2048 * see first lines of serial_in() and serial_out() in 8250.c
2049*/
2050
de88b340 2051static struct pciserial_board pci_boards[] = {
1da177e4
LT		 2052 [pbn_default] = {
2053 .flags = FL_BASE0,
2054 .num_ports = 1,
2055 .base_baud = 115200,
2056 .uart_offset = 8,
2057 },
2058 [pbn_b0_1_115200] = {
2059 .flags = FL_BASE0,
2060 .num_ports = 1,
2061 .base_baud = 115200,
2062 .uart_offset = 8,
2063 },
2064 [pbn_b0_2_115200] = {
2065 .flags = FL_BASE0,
2066 .num_ports = 2,
2067 .base_baud = 115200,
2068 .uart_offset = 8,
2069 },
2070 [pbn_b0_4_115200] = {
2071 .flags = FL_BASE0,
2072 .num_ports = 4,
2073 .base_baud = 115200,
2074 .uart_offset = 8,
2075 },
2076 [pbn_b0_5_115200] = {
2077 .flags = FL_BASE0,
2078 .num_ports = 5,
2079 .base_baud = 115200,
2080 .uart_offset = 8,
2081 },
bf0df636
AC		 2082 [pbn_b0_8_115200] = {
2083 .flags = FL_BASE0,
2084 .num_ports = 8,
2085 .base_baud = 115200,
2086 .uart_offset = 8,
2087 },
1da177e4
LT		 2088 [pbn_b0_1_921600] = {
2089 .flags = FL_BASE0,
2090 .num_ports = 1,
2091 .base_baud = 921600,
2092 .uart_offset = 8,
2093 },
2094 [pbn_b0_2_921600] = {
2095 .flags = FL_BASE0,
2096 .num_ports = 2,
2097 .base_baud = 921600,
2098 .uart_offset = 8,
2099 },
2100 [pbn_b0_4_921600] = {
2101 .flags = FL_BASE0,
2102 .num_ports = 4,
2103 .base_baud = 921600,
2104 .uart_offset = 8,
2105 },
db1de159
DR		 2106
2107 [pbn_b0_2_1130000] = {
2108 .flags = FL_BASE0,
2109 .num_ports = 2,
2110 .base_baud = 1130000,
2111 .uart_offset = 8,
2112 },
2113
fbc0dc0d
AP		 2114 [pbn_b0_4_1152000] = {
2115 .flags = FL_BASE0,
2116 .num_ports = 4,
2117 .base_baud = 1152000,
2118 .uart_offset = 8,
2119 },
1da177e4 2120
26e92861
GH		 2121 [pbn_b0_2_1843200] = {
2122 .flags = FL_BASE0,
2123 .num_ports = 2,
2124 .base_baud = 1843200,
2125 .uart_offset = 8,
2126 },
2127 [pbn_b0_4_1843200] = {
2128 .flags = FL_BASE0,
2129 .num_ports = 4,
2130 .base_baud = 1843200,
2131 .uart_offset = 8,
2132 },
2133
2134 [pbn_b0_2_1843200_200] = {
2135 .flags = FL_BASE0,
2136 .num_ports = 2,
2137 .base_baud = 1843200,
2138 .uart_offset = 0x200,
2139 },
2140 [pbn_b0_4_1843200_200] = {
2141 .flags = FL_BASE0,
2142 .num_ports = 4,
2143 .base_baud = 1843200,
2144 .uart_offset = 0x200,
2145 },
2146 [pbn_b0_8_1843200_200] = {
2147 .flags = FL_BASE0,
2148 .num_ports = 8,
2149 .base_baud = 1843200,
2150 .uart_offset = 0x200,
2151 },
7106b4e3
LH		 2152 [pbn_b0_1_4000000] = {
2153 .flags = FL_BASE0,
2154 .num_ports = 1,
2155 .base_baud = 4000000,
2156 .uart_offset = 8,
2157 },
26e92861 2158
1da177e4
LT		 2159 [pbn_b0_bt_1_115200] = {
2160 .flags = FL_BASE0|FL_BASE_BARS,
2161 .num_ports = 1,
2162 .base_baud = 115200,
2163 .uart_offset = 8,
2164 },
2165 [pbn_b0_bt_2_115200] = {
2166 .flags = FL_BASE0|FL_BASE_BARS,
2167 .num_ports = 2,
2168 .base_baud = 115200,
2169 .uart_offset = 8,
2170 },
ac6ec5b1
IS		 2171 [pbn_b0_bt_4_115200] = {
2172 .flags = FL_BASE0|FL_BASE_BARS,
2173 .num_ports = 4,
2174 .base_baud = 115200,
2175 .uart_offset = 8,
2176 },
1da177e4
LT		 2177 [pbn_b0_bt_8_115200] = {
2178 .flags = FL_BASE0|FL_BASE_BARS,
2179 .num_ports = 8,
2180 .base_baud = 115200,
2181 .uart_offset = 8,
2182 },
2183
2184 [pbn_b0_bt_1_460800] = {
2185 .flags = FL_BASE0|FL_BASE_BARS,
2186 .num_ports = 1,
2187 .base_baud = 460800,
2188 .uart_offset = 8,
2189 },
2190 [pbn_b0_bt_2_460800] = {
2191 .flags = FL_BASE0|FL_BASE_BARS,
2192 .num_ports = 2,
2193 .base_baud = 460800,
2194 .uart_offset = 8,
2195 },
2196 [pbn_b0_bt_4_460800] = {
2197 .flags = FL_BASE0|FL_BASE_BARS,
2198 .num_ports = 4,
2199 .base_baud = 460800,
2200 .uart_offset = 8,
2201 },
2202
2203 [pbn_b0_bt_1_921600] = {
2204 .flags = FL_BASE0|FL_BASE_BARS,
2205 .num_ports = 1,
2206 .base_baud = 921600,
2207 .uart_offset = 8,
2208 },
2209 [pbn_b0_bt_2_921600] = {
2210 .flags = FL_BASE0|FL_BASE_BARS,
2211 .num_ports = 2,
2212 .base_baud = 921600,
2213 .uart_offset = 8,
2214 },
2215 [pbn_b0_bt_4_921600] = {
2216 .flags = FL_BASE0|FL_BASE_BARS,
2217 .num_ports = 4,
2218 .base_baud = 921600,
2219 .uart_offset = 8,
2220 },
2221 [pbn_b0_bt_8_921600] = {
2222 .flags = FL_BASE0|FL_BASE_BARS,
2223 .num_ports = 8,
2224 .base_baud = 921600,
2225 .uart_offset = 8,
2226 },
2227
2228 [pbn_b1_1_115200] = {
2229 .flags = FL_BASE1,
2230 .num_ports = 1,
2231 .base_baud = 115200,
2232 .uart_offset = 8,
2233 },
2234 [pbn_b1_2_115200] = {
2235 .flags = FL_BASE1,
2236 .num_ports = 2,
2237 .base_baud = 115200,
2238 .uart_offset = 8,
2239 },
2240 [pbn_b1_4_115200] = {
2241 .flags = FL_BASE1,
2242 .num_ports = 4,
2243 .base_baud = 115200,
2244 .uart_offset = 8,
2245 },
2246 [pbn_b1_8_115200] = {
2247 .flags = FL_BASE1,
2248 .num_ports = 8,
2249 .base_baud = 115200,
2250 .uart_offset = 8,
2251 },
04bf7e74
WP		 2252 [pbn_b1_16_115200] = {
2253 .flags = FL_BASE1,
2254 .num_ports = 16,
2255 .base_baud = 115200,
2256 .uart_offset = 8,
2257 },
1da177e4
LT		 2258
2259 [pbn_b1_1_921600] = {
2260 .flags = FL_BASE1,
2261 .num_ports = 1,
2262 .base_baud = 921600,
2263 .uart_offset = 8,
2264 },
2265 [pbn_b1_2_921600] = {
2266 .flags = FL_BASE1,
2267 .num_ports = 2,
2268 .base_baud = 921600,
2269 .uart_offset = 8,
2270 },
2271 [pbn_b1_4_921600] = {
2272 .flags = FL_BASE1,
2273 .num_ports = 4,
2274 .base_baud = 921600,
2275 .uart_offset = 8,
2276 },
2277 [pbn_b1_8_921600] = {
2278 .flags = FL_BASE1,
2279 .num_ports = 8,
2280 .base_baud = 921600,
2281 .uart_offset = 8,
2282 },
26e92861
GH		 2283 [pbn_b1_2_1250000] = {
2284 .flags = FL_BASE1,
2285 .num_ports = 2,
2286 .base_baud = 1250000,
2287 .uart_offset = 8,
2288 },
1da177e4 2289
84f8c6fc
NV		 2290 [pbn_b1_bt_1_115200] = {
2291 .flags = FL_BASE1|FL_BASE_BARS,
2292 .num_ports = 1,
2293 .base_baud = 115200,
2294 .uart_offset = 8,
2295 },
04bf7e74
WP		 2296 [pbn_b1_bt_2_115200] = {
2297 .flags = FL_BASE1|FL_BASE_BARS,
2298 .num_ports = 2,
2299 .base_baud = 115200,
2300 .uart_offset = 8,
2301 },
2302 [pbn_b1_bt_4_115200] = {
2303 .flags = FL_BASE1|FL_BASE_BARS,
2304 .num_ports = 4,
2305 .base_baud = 115200,
2306 .uart_offset = 8,
2307 },
84f8c6fc 2308
1da177e4
LT		 2309 [pbn_b1_bt_2_921600] = {
2310 .flags = FL_BASE1|FL_BASE_BARS,
2311 .num_ports = 2,
2312 .base_baud = 921600,
2313 .uart_offset = 8,
2314 },
2315
2316 [pbn_b1_1_1382400] = {
2317 .flags = FL_BASE1,
2318 .num_ports = 1,
2319 .base_baud = 1382400,
2320 .uart_offset = 8,
2321 },
2322 [pbn_b1_2_1382400] = {
2323 .flags = FL_BASE1,
2324 .num_ports = 2,
2325 .base_baud = 1382400,
2326 .uart_offset = 8,
2327 },
2328 [pbn_b1_4_1382400] = {
2329 .flags = FL_BASE1,
2330 .num_ports = 4,
2331 .base_baud = 1382400,
2332 .uart_offset = 8,
2333 },
2334 [pbn_b1_8_1382400] = {
2335 .flags = FL_BASE1,
2336 .num_ports = 8,
2337 .base_baud = 1382400,
2338 .uart_offset = 8,
2339 },
2340
2341 [pbn_b2_1_115200] = {
2342 .flags = FL_BASE2,
2343 .num_ports = 1,
2344 .base_baud = 115200,
2345 .uart_offset = 8,
2346 },
737c1756
PH		 2347 [pbn_b2_2_115200] = {
2348 .flags = FL_BASE2,
2349 .num_ports = 2,
2350 .base_baud = 115200,
2351 .uart_offset = 8,
2352 },
a9cccd34
MF		 2353 [pbn_b2_4_115200] = {
2354 .flags = FL_BASE2,
2355 .num_ports = 4,
2356 .base_baud = 115200,
2357 .uart_offset = 8,
2358 },
1da177e4
LT		 2359 [pbn_b2_8_115200] = {
2360 .flags = FL_BASE2,
2361 .num_ports = 8,
2362 .base_baud = 115200,
2363 .uart_offset = 8,
2364 },
2365
2366 [pbn_b2_1_460800] = {
2367 .flags = FL_BASE2,
2368 .num_ports = 1,
2369 .base_baud = 460800,
2370 .uart_offset = 8,
2371 },
2372 [pbn_b2_4_460800] = {
2373 .flags = FL_BASE2,
2374 .num_ports = 4,
2375 .base_baud = 460800,
2376 .uart_offset = 8,
2377 },
2378 [pbn_b2_8_460800] = {
2379 .flags = FL_BASE2,
2380 .num_ports = 8,
2381 .base_baud = 460800,
2382 .uart_offset = 8,
2383 },
2384 [pbn_b2_16_460800] = {
2385 .flags = FL_BASE2,
2386 .num_ports = 16,
2387 .base_baud = 460800,
2388 .uart_offset = 8,
2389 },
2390
2391 [pbn_b2_1_921600] = {
2392 .flags = FL_BASE2,
2393 .num_ports = 1,
2394 .base_baud = 921600,
2395 .uart_offset = 8,
2396 },
2397 [pbn_b2_4_921600] = {
2398 .flags = FL_BASE2,
2399 .num_ports = 4,
2400 .base_baud = 921600,
2401 .uart_offset = 8,
2402 },
2403 [pbn_b2_8_921600] = {
2404 .flags = FL_BASE2,
2405 .num_ports = 8,
2406 .base_baud = 921600,
2407 .uart_offset = 8,
2408 },
2409
e847003f
LB		 2410 [pbn_b2_8_1152000] = {
2411 .flags = FL_BASE2,
2412 .num_ports = 8,
2413 .base_baud = 1152000,
2414 .uart_offset = 8,
2415 },
2416
1da177e4
LT		 2417 [pbn_b2_bt_1_115200] = {
2418 .flags = FL_BASE2|FL_BASE_BARS,
2419 .num_ports = 1,
2420 .base_baud = 115200,
2421 .uart_offset = 8,
2422 },
2423 [pbn_b2_bt_2_115200] = {
2424 .flags = FL_BASE2|FL_BASE_BARS,
2425 .num_ports = 2,
2426 .base_baud = 115200,
2427 .uart_offset = 8,
2428 },
2429 [pbn_b2_bt_4_115200] = {
2430 .flags = FL_BASE2|FL_BASE_BARS,
2431 .num_ports = 4,
2432 .base_baud = 115200,
2433 .uart_offset = 8,
2434 },
2435
2436 [pbn_b2_bt_2_921600] = {
2437 .flags = FL_BASE2|FL_BASE_BARS,
2438 .num_ports = 2,
2439 .base_baud = 921600,
2440 .uart_offset = 8,
2441 },
2442 [pbn_b2_bt_4_921600] = {
2443 .flags = FL_BASE2|FL_BASE_BARS,
2444 .num_ports = 4,
2445 .base_baud = 921600,
2446 .uart_offset = 8,
2447 },
2448
d9004eb4
ABL		 2449 [pbn_b3_2_115200] = {
2450 .flags = FL_BASE3,
2451 .num_ports = 2,
2452 .base_baud = 115200,
2453 .uart_offset = 8,
2454 },
1da177e4
LT		 2455 [pbn_b3_4_115200] = {
2456 .flags = FL_BASE3,
2457 .num_ports = 4,
2458 .base_baud = 115200,
2459 .uart_offset = 8,
2460 },
2461 [pbn_b3_8_115200] = {
2462 .flags = FL_BASE3,
2463 .num_ports = 8,
2464 .base_baud = 115200,
2465 .uart_offset = 8,
2466 },
2467
66169ad1
YY		 2468 [pbn_b4_bt_2_921600] = {
2469 .flags = FL_BASE4,
2470 .num_ports = 2,
2471 .base_baud = 921600,
2472 .uart_offset = 8,
2473 },
2474 [pbn_b4_bt_4_921600] = {
2475 .flags = FL_BASE4,
2476 .num_ports = 4,
2477 .base_baud = 921600,
2478 .uart_offset = 8,
2479 },
2480 [pbn_b4_bt_8_921600] = {
2481 .flags = FL_BASE4,
2482 .num_ports = 8,
2483 .base_baud = 921600,
2484 .uart_offset = 8,
2485 },
2486
1da177e4
LT		 2487 /*
2488 * Entries following this are board-specific.
2489 */
2490
2491 /*
2492 * Panacom - IOMEM
2493 */
2494 [pbn_panacom] = {
2495 .flags = FL_BASE2,
2496 .num_ports = 2,
2497 .base_baud = 921600,
2498 .uart_offset = 0x400,
2499 .reg_shift = 7,
2500 },
2501 [pbn_panacom2] = {
2502 .flags = FL_BASE2|FL_BASE_BARS,
2503 .num_ports = 2,
2504 .base_baud = 921600,
2505 .uart_offset = 0x400,
2506 .reg_shift = 7,
2507 },
2508 [pbn_panacom4] = {
2509 .flags = FL_BASE2|FL_BASE_BARS,
2510 .num_ports = 4,
2511 .base_baud = 921600,
2512 .uart_offset = 0x400,
2513 .reg_shift = 7,
2514 },
2515
2516 /* I think this entry is broken - the first_offset looks wrong --rmk */
2517 [pbn_plx_romulus] = {
2518 .flags = FL_BASE2,
2519 .num_ports = 4,
2520 .base_baud = 921600,
2521 .uart_offset = 8 << 2,
2522 .reg_shift = 2,
2523 .first_offset = 0x03,
2524 },
2525
2526 /*
2527 * This board uses the size of PCI Base region 0 to
2528 * signal now many ports are available
2529 */
2530 [pbn_oxsemi] = {
2531 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2532 .num_ports = 32,
2533 .base_baud = 115200,
2534 .uart_offset = 8,
2535 },
7106b4e3
LH		 2536 [pbn_oxsemi_1_4000000] = {
2537 .flags = FL_BASE0,
2538 .num_ports = 1,
2539 .base_baud = 4000000,
2540 .uart_offset = 0x200,
2541 .first_offset = 0x1000,
2542 },
2543 [pbn_oxsemi_2_4000000] = {
2544 .flags = FL_BASE0,
2545 .num_ports = 2,
2546 .base_baud = 4000000,
2547 .uart_offset = 0x200,
2548 .first_offset = 0x1000,
2549 },
2550 [pbn_oxsemi_4_4000000] = {
2551 .flags = FL_BASE0,
2552 .num_ports = 4,
2553 .base_baud = 4000000,
2554 .uart_offset = 0x200,
2555 .first_offset = 0x1000,
2556 },
2557 [pbn_oxsemi_8_4000000] = {
2558 .flags = FL_BASE0,
2559 .num_ports = 8,
2560 .base_baud = 4000000,
2561 .uart_offset = 0x200,
2562 .first_offset = 0x1000,
2563 },
2564
1da177e4
LT		 2565
2566 /*
2567 * EKF addition for i960 Boards form EKF with serial port.
2568 * Max 256 ports.
2569 */
2570 [pbn_intel_i960] = {
2571 .flags = FL_BASE0,
2572 .num_ports = 32,
2573 .base_baud = 921600,
2574 .uart_offset = 8 << 2,
2575 .reg_shift = 2,
2576 .first_offset = 0x10000,
2577 },
2578 [pbn_sgi_ioc3] = {
2579 .flags = FL_BASE0|FL_NOIRQ,
2580 .num_ports = 1,
2581 .base_baud = 458333,
2582 .uart_offset = 8,
2583 .reg_shift = 0,
2584 .first_offset = 0x20178,
2585 },
2586
1da177e4
LT		 2587 /*
2588 * Computone - uses IOMEM.
2589 */
2590 [pbn_computone_4] = {
2591 .flags = FL_BASE0,
2592 .num_ports = 4,
2593 .base_baud = 921600,
2594 .uart_offset = 0x40,
2595 .reg_shift = 2,
2596 .first_offset = 0x200,
2597 },
2598 [pbn_computone_6] = {
2599 .flags = FL_BASE0,
2600 .num_ports = 6,
2601 .base_baud = 921600,
2602 .uart_offset = 0x40,
2603 .reg_shift = 2,
2604 .first_offset = 0x200,
2605 },
2606 [pbn_computone_8] = {
2607 .flags = FL_BASE0,
2608 .num_ports = 8,
2609 .base_baud = 921600,
2610 .uart_offset = 0x40,
2611 .reg_shift = 2,
2612 .first_offset = 0x200,
2613 },
2614 [pbn_sbsxrsio] = {
2615 .flags = FL_BASE0,
2616 .num_ports = 8,
2617 .base_baud = 460800,
2618 .uart_offset = 256,
2619 .reg_shift = 4,
2620 },
2621 /*
2622 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2623 * Only basic 16550A support.
2624 * XR17C15[24] are not tested, but they should work.
2625 */
2626 [pbn_exar_XR17C152] = {
2627 .flags = FL_BASE0,
2628 .num_ports = 2,
2629 .base_baud = 921600,
2630 .uart_offset = 0x200,
2631 },
2632 [pbn_exar_XR17C154] = {
2633 .flags = FL_BASE0,
2634 .num_ports = 4,
2635 .base_baud = 921600,
2636 .uart_offset = 0x200,
2637 },
2638 [pbn_exar_XR17C158] = {
2639 .flags = FL_BASE0,
2640 .num_ports = 8,
2641 .base_baud = 921600,
2642 .uart_offset = 0x200,
2643 },
dc96efb7
MS		 2644 [pbn_exar_XR17V352] = {
2645 .flags = FL_BASE0,
2646 .num_ports = 2,
2647 .base_baud = 7812500,
2648 .uart_offset = 0x400,
2649 .reg_shift = 0,
2650 .first_offset = 0,
2651 },
2652 [pbn_exar_XR17V354] = {
2653 .flags = FL_BASE0,
2654 .num_ports = 4,
2655 .base_baud = 7812500,
2656 .uart_offset = 0x400,
2657 .reg_shift = 0,
2658 .first_offset = 0,
2659 },
2660 [pbn_exar_XR17V358] = {
2661 .flags = FL_BASE0,
2662 .num_ports = 8,
2663 .base_baud = 7812500,
2664 .uart_offset = 0x400,
2665 .reg_shift = 0,
2666 .first_offset = 0,
2667 },
c68d2b15
BH		 2668 [pbn_exar_ibm_saturn] = {
2669 .flags = FL_BASE0,
2670 .num_ports = 1,
2671 .base_baud = 921600,
2672 .uart_offset = 0x200,
2673 },
2674
aa798505
OJ		 2675 /*
2676 * PA Semi PWRficient PA6T-1682M on-chip UART
2677 */
2678 [pbn_pasemi_1682M] = {
2679 .flags = FL_BASE0,
2680 .num_ports = 1,
2681 .base_baud = 8333333,
2682 },
46a0fac9
SB		 2683 /*
2684 * National Instruments 843x
2685 */
2686 [pbn_ni8430_16] = {
2687 .flags = FL_BASE0,
2688 .num_ports = 16,
2689 .base_baud = 3686400,
2690 .uart_offset = 0x10,
2691 .first_offset = 0x800,
2692 },
2693 [pbn_ni8430_8] = {
2694 .flags = FL_BASE0,
2695 .num_ports = 8,
2696 .base_baud = 3686400,
2697 .uart_offset = 0x10,
2698 .first_offset = 0x800,
2699 },
2700 [pbn_ni8430_4] = {
2701 .flags = FL_BASE0,
2702 .num_ports = 4,
2703 .base_baud = 3686400,
2704 .uart_offset = 0x10,
2705 .first_offset = 0x800,
2706 },
2707 [pbn_ni8430_2] = {
2708 .flags = FL_BASE0,
2709 .num_ports = 2,
2710 .base_baud = 3686400,
2711 .uart_offset = 0x10,
2712 .first_offset = 0x800,
2713 },
1b62cbf2
KJ		 2714 /*
2715 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2716 */
2717 [pbn_ADDIDATA_PCIe_1_3906250] = {
2718 .flags = FL_BASE0,
2719 .num_ports = 1,
2720 .base_baud = 3906250,
2721 .uart_offset = 0x200,
2722 .first_offset = 0x1000,
2723 },
2724 [pbn_ADDIDATA_PCIe_2_3906250] = {
2725 .flags = FL_BASE0,
2726 .num_ports = 2,
2727 .base_baud = 3906250,
2728 .uart_offset = 0x200,
2729 .first_offset = 0x1000,
2730 },
2731 [pbn_ADDIDATA_PCIe_4_3906250] = {
2732 .flags = FL_BASE0,
2733 .num_ports = 4,
2734 .base_baud = 3906250,
2735 .uart_offset = 0x200,
2736 .first_offset = 0x1000,
2737 },
2738 [pbn_ADDIDATA_PCIe_8_3906250] = {
2739 .flags = FL_BASE0,
2740 .num_ports = 8,
2741 .base_baud = 3906250,
2742 .uart_offset = 0x200,
2743 .first_offset = 0x1000,
2744 },
095e24b0 2745 [pbn_ce4100_1_115200] = {
08ec212c
MB		 2746 .flags = FL_BASE_BARS,
2747 .num_ports = 2,
095e24b0
DB		 2748 .base_baud = 921600,
2749 .reg_shift = 2,
2750 },
d9a0fbfd
AP		 2751 [pbn_omegapci] = {
2752 .flags = FL_BASE0,
2753 .num_ports = 8,
2754 .base_baud = 115200,
2755 .uart_offset = 0x200,
2756 },
7808edcd
NG		 2757 [pbn_NETMOS9900_2s_115200] = {
2758 .flags = FL_BASE0,
2759 .num_ports = 2,
2760 .base_baud = 115200,
2761 },
1da177e4
LT		 2762};
2763
6971c635
GA		 2764static const struct pci_device_id blacklist[] = {
2765 /* softmodems */
5756ee99 2766 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 2767 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2768 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
6971c635
GA		 2769
2770 /* multi-io cards handled by parport_serial */
2771 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
436bbd43
CS		 2772};
2773
1da177e4
LT		 2774/*
2775 * Given a complete unknown PCI device, try to use some heuristics to
2776 * guess what the configuration might be, based on the pitiful PCI
2777 * serial specs. Returns 0 on success, 1 on failure.
2778 */
9671f099 2779static int
1c7c1fe5 2780serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 2781{
6971c635 2782 const struct pci_device_id *bldev;
1da177e4 2783 int num_iomem, num_port, first_port = -1, i;
5756ee99 2784
1da177e4
LT		 2785 /*
2786 * If it is not a communications device or the programming
2787 * interface is greater than 6, give up.
2788 *
2789 * (Should we try to make guesses for multiport serial devices
5756ee99 2790 * later?)
1da177e4
LT		 2791 */
2792 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2793 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2794 (dev->class & 0xff) > 6)
2795 return -ENODEV;
2796
436bbd43
CS		 2797 /*
2798 * Do not access blacklisted devices that are known not to
6971c635 2799 * feature serial ports or are handled by other modules.
436bbd43 2800 */
6971c635
GA		 2801 for (bldev = blacklist;
2802 bldev < blacklist + ARRAY_SIZE(blacklist);
2803 bldev++) {
2804 if (dev->vendor == bldev->vendor &&
2805 dev->device == bldev->device)
436bbd43
CS		 2806 return -ENODEV;
2807 }
2808
1da177e4
LT		 2809 num_iomem = num_port = 0;
2810 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2811 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2812 num_port++;
2813 if (first_port == -1)
2814 first_port = i;
2815 }
2816 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2817 num_iomem++;
2818 }
2819
2820 /*
2821 * If there is 1 or 0 iomem regions, and exactly one port,
2822 * use it. We guess the number of ports based on the IO
2823 * region size.
2824 */
2825 if (num_iomem <= 1 && num_port == 1) {
2826 board->flags = first_port;
2827 board->num_ports = pci_resource_len(dev, first_port) / 8;
2828 return 0;
2829 }
2830
2831 /*
2832 * Now guess if we've got a board which indexes by BARs.
2833 * Each IO BAR should be 8 bytes, and they should follow
2834 * consecutively.
2835 */
2836 first_port = -1;
2837 num_port = 0;
2838 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2839 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2840 pci_resource_len(dev, i) == 8 &&
2841 (first_port == -1 || (first_port + num_port) == i)) {
2842 num_port++;
2843 if (first_port == -1)
2844 first_port = i;
2845 }
2846 }
2847
2848 if (num_port > 1) {
2849 board->flags = first_port | FL_BASE_BARS;
2850 board->num_ports = num_port;
2851 return 0;
2852 }
2853
2854 return -ENODEV;
2855}
2856
2857static inline int
975a1a7d
RK		 2858serial_pci_matches(const struct pciserial_board *board,
2859 const struct pciserial_board *guessed)
1da177e4
LT		 2860{
2861 return
2862 board->num_ports == guessed->num_ports &&
2863 board->base_baud == guessed->base_baud &&
2864 board->uart_offset == guessed->uart_offset &&
2865 board->reg_shift == guessed->reg_shift &&
2866 board->first_offset == guessed->first_offset;
2867}
2868
241fc436 2869struct serial_private *
975a1a7d 2870pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 2871{
2655a2c7 2872 struct uart_8250_port uart;
1da177e4 2873 struct serial_private *priv;
1da177e4
LT		 2874 struct pci_serial_quirk *quirk;
2875 int rc, nr_ports, i;
2876
1da177e4
LT		 2877 nr_ports = board->num_ports;
2878
2879 /*
2880 * Find an init and setup quirks.
2881 */
2882 quirk = find_quirk(dev);
2883
2884 /*
2885 * Run the new-style initialization function.
2886 * The initialization function returns:
2887 * <0 - error
2888 * 0 - use board->num_ports
2889 * >0 - number of ports
2890 */
2891 if (quirk->init) {
2892 rc = quirk->init(dev);
241fc436
RK		 2893 if (rc < 0) {
2894 priv = ERR_PTR(rc);
2895 goto err_out;
2896 }
1da177e4
LT		 2897 if (rc)
2898 nr_ports = rc;
2899 }
2900
8f31bb39 2901 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 2902 sizeof(unsigned int) * nr_ports,
2903 GFP_KERNEL);
2904 if (!priv) {
241fc436
RK		 2905 priv = ERR_PTR(-ENOMEM);
2906 goto err_deinit;
1da177e4
LT		 2907 }
2908
70db3d91 2909 priv->dev = dev;
1da177e4 2910 priv->quirk = quirk;
1da177e4 2911
2655a2c7
AC		 2912 memset(&uart, 0, sizeof(uart));
2913 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2914 uart.port.uartclk = board->base_baud * 16;
2915 uart.port.irq = get_pci_irq(dev, board);
2916 uart.port.dev = &dev->dev;
72ce9a83 2917
1da177e4 2918 for (i = 0; i < nr_ports; i++) {
2655a2c7 2919 if (quirk->setup(priv, board, &uart, i))
1da177e4 2920 break;
72ce9a83 2921
1da177e4 2922#ifdef SERIAL_DEBUG_PCI
80647b95 2923 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2655a2c7 2924 uart.port.iobase, uart.port.irq, uart.port.iotype);
1da177e4 2925#endif
5756ee99 2926
2655a2c7 2927 priv->line[i] = serial8250_register_8250_port(&uart);
1da177e4
LT		 2928 if (priv->line[i] < 0) {
2929 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2930 break;
2931 }
2932 }
1da177e4 2933 priv->nr = i;
241fc436 2934 return priv;
1da177e4 2935
5756ee99 2936err_deinit:
1da177e4
LT		 2937 if (quirk->exit)
2938 quirk->exit(dev);
5756ee99 2939err_out:
241fc436 2940 return priv;
1da177e4 2941}
241fc436 2942EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 2943
241fc436 2944void pciserial_remove_ports(struct serial_private *priv)
1da177e4 2945{
056a8763
RK		 2946 struct pci_serial_quirk *quirk;
2947 int i;
1da177e4 2948
056a8763
RK		 2949 for (i = 0; i < priv->nr; i++)
2950 serial8250_unregister_port(priv->line[i]);
1da177e4 2951
056a8763
RK		 2952 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2953 if (priv->remapped_bar[i])
2954 iounmap(priv->remapped_bar[i]);
2955 priv->remapped_bar[i] = NULL;
2956 }
1da177e4 2957
056a8763
RK		 2958 /*
2959 * Find the exit quirks.
2960 */
241fc436 2961 quirk = find_quirk(priv->dev);
056a8763 2962 if (quirk->exit)
241fc436
RK		 2963 quirk->exit(priv->dev);
2964
2965 kfree(priv);
2966}
2967EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2968
2969void pciserial_suspend_ports(struct serial_private *priv)
2970{
2971 int i;
2972
2973 for (i = 0; i < priv->nr; i++)
2974 if (priv->line[i] >= 0)
2975 serial8250_suspend_port(priv->line[i]);
5f1a3895
DW		 2976
2977 /*
2978 * Ensure that every init quirk is properly torn down
2979 */
2980 if (priv->quirk->exit)
2981 priv->quirk->exit(priv->dev);
241fc436
RK		 2982}
2983EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2984
2985void pciserial_resume_ports(struct serial_private *priv)
2986{
2987 int i;
2988
2989 /*
2990 * Ensure that the board is correctly configured.
2991 */
2992 if (priv->quirk->init)
2993 priv->quirk->init(priv->dev);
2994
2995 for (i = 0; i < priv->nr; i++)
2996 if (priv->line[i] >= 0)
2997 serial8250_resume_port(priv->line[i]);
2998}
2999EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3000
3001/*
3002 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3003 * to the arrangement of serial ports on a PCI card.
3004 */
9671f099 3005static int
241fc436
RK		 3006pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3007{
5bf8f501 3008 struct pci_serial_quirk *quirk;
241fc436 3009 struct serial_private *priv;
975a1a7d
RK		 3010 const struct pciserial_board *board;
3011 struct pciserial_board tmp;
241fc436
RK		 3012 int rc;
3013
5bf8f501
FB		 3014 quirk = find_quirk(dev);
3015 if (quirk->probe) {
3016 rc = quirk->probe(dev);
3017 if (rc)
3018 return rc;
3019 }
3020
241fc436
RK		 3021 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3022 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
3023 ent->driver_data);
3024 return -EINVAL;
3025 }
3026
3027 board = &pci_boards[ent->driver_data];
3028
3029 rc = pci_enable_device(dev);
2807190b 3030 pci_save_state(dev);
241fc436
RK		 3031 if (rc)
3032 return rc;
3033
3034 if (ent->driver_data == pbn_default) {
3035 /*
3036 * Use a copy of the pci_board entry for this;
3037 * avoid changing entries in the table.
3038 */
3039 memcpy(&tmp, board, sizeof(struct pciserial_board));
3040 board = &tmp;
3041
3042 /*
3043 * We matched one of our class entries. Try to
3044 * determine the parameters of this board.
3045 */
975a1a7d 3046 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 3047 if (rc)
3048 goto disable;
3049 } else {
3050 /*
3051 * We matched an explicit entry. If we are able to
3052 * detect this boards settings with our heuristic,
3053 * then we no longer need this entry.
3054 */
3055 memcpy(&tmp, &pci_boards[pbn_default],
3056 sizeof(struct pciserial_board));
3057 rc = serial_pci_guess_board(dev, &tmp);
3058 if (rc == 0 && serial_pci_matches(board, &tmp))
3059 moan_device("Redundant entry in serial pci_table.",
3060 dev);
3061 }
3062
3063 priv = pciserial_init_ports(dev, board);
3064 if (!IS_ERR(priv)) {
3065 pci_set_drvdata(dev, priv);
3066 return 0;
3067 }
3068
3069 rc = PTR_ERR(priv);
1da177e4 3070
241fc436 3071 disable:
056a8763 3072 pci_disable_device(dev);
241fc436
RK		 3073 return rc;
3074}
1da177e4 3075
ae8d8a14 3076static void pciserial_remove_one(struct pci_dev *dev)
241fc436
RK		 3077{
3078 struct serial_private *priv = pci_get_drvdata(dev);
3079
3080 pci_set_drvdata(dev, NULL);
3081
3082 pciserial_remove_ports(priv);
3083
3084 pci_disable_device(dev);
1da177e4
LT		 3085}
3086
1d5e7996 3087#ifdef CONFIG_PM
1da177e4
LT		 3088static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3089{
3090 struct serial_private *priv = pci_get_drvdata(dev);
3091
241fc436
RK		 3092 if (priv)
3093 pciserial_suspend_ports(priv);
1da177e4 3094
1da177e4
LT		 3095 pci_save_state(dev);
3096 pci_set_power_state(dev, pci_choose_state(dev, state));
3097 return 0;
3098}
3099
3100static int pciserial_resume_one(struct pci_dev *dev)
3101{
ccb9d59e 3102 int err;
1da177e4
LT		 3103 struct serial_private *priv = pci_get_drvdata(dev);
3104
3105 pci_set_power_state(dev, PCI_D0);
3106 pci_restore_state(dev);
3107
3108 if (priv) {
1da177e4
LT		 3109 /*
3110 * The device may have been disabled. Re-enable it.
3111 */
ccb9d59e 3112 err = pci_enable_device(dev);
40836c48 3113 /* FIXME: We cannot simply error out here */
ccb9d59e 3114 if (err)
40836c48 3115 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
241fc436 3116 pciserial_resume_ports(priv);
1da177e4
LT		 3117 }
3118 return 0;
3119}
1d5e7996 3120#endif
1da177e4
LT		 3121
3122static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 3123 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3124 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3125 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3126 pbn_b2_8_921600 },
1da177e4
LT		 3127 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3128 PCI_SUBVENDOR_ID_CONNECT_TECH,
3129 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3130 pbn_b1_8_1382400 },
3131 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3132 PCI_SUBVENDOR_ID_CONNECT_TECH,
3133 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3134 pbn_b1_4_1382400 },
3135 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3136 PCI_SUBVENDOR_ID_CONNECT_TECH,
3137 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3138 pbn_b1_2_1382400 },
3139 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3140 PCI_SUBVENDOR_ID_CONNECT_TECH,
3141 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3142 pbn_b1_8_1382400 },
3143 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3144 PCI_SUBVENDOR_ID_CONNECT_TECH,
3145 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3146 pbn_b1_4_1382400 },
3147 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3148 PCI_SUBVENDOR_ID_CONNECT_TECH,
3149 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3150 pbn_b1_2_1382400 },
3151 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3152 PCI_SUBVENDOR_ID_CONNECT_TECH,
3153 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3154 pbn_b1_8_921600 },
3155 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3156 PCI_SUBVENDOR_ID_CONNECT_TECH,
3157 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3158 pbn_b1_8_921600 },
3159 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3160 PCI_SUBVENDOR_ID_CONNECT_TECH,
3161 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3162 pbn_b1_4_921600 },
3163 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3164 PCI_SUBVENDOR_ID_CONNECT_TECH,
3165 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3166 pbn_b1_4_921600 },
3167 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3168 PCI_SUBVENDOR_ID_CONNECT_TECH,
3169 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3170 pbn_b1_2_921600 },
3171 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3172 PCI_SUBVENDOR_ID_CONNECT_TECH,
3173 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3174 pbn_b1_8_921600 },
3175 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3176 PCI_SUBVENDOR_ID_CONNECT_TECH,
3177 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3178 pbn_b1_8_921600 },
3179 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3180 PCI_SUBVENDOR_ID_CONNECT_TECH,
3181 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3182 pbn_b1_4_921600 },
26e92861
GH		 3183 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3184 PCI_SUBVENDOR_ID_CONNECT_TECH,
3185 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3186 pbn_b1_2_1250000 },
3187 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3188 PCI_SUBVENDOR_ID_CONNECT_TECH,
3189 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3190 pbn_b0_2_1843200 },
3191 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3192 PCI_SUBVENDOR_ID_CONNECT_TECH,
3193 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3194 pbn_b0_4_1843200 },
85d1494e
YY		 3195 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3196 PCI_VENDOR_ID_AFAVLAB,
3197 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3198 pbn_b0_4_1152000 },
26e92861
GH		 3199 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3200 PCI_SUBVENDOR_ID_CONNECT_TECH,
3201 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3202 pbn_b0_2_1843200_200 },
3203 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3204 PCI_SUBVENDOR_ID_CONNECT_TECH,
3205 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3206 pbn_b0_4_1843200_200 },
3207 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3208 PCI_SUBVENDOR_ID_CONNECT_TECH,
3209 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3210 pbn_b0_8_1843200_200 },
3211 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3212 PCI_SUBVENDOR_ID_CONNECT_TECH,
3213 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3214 pbn_b0_2_1843200_200 },
3215 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3216 PCI_SUBVENDOR_ID_CONNECT_TECH,
3217 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3218 pbn_b0_4_1843200_200 },
3219 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3220 PCI_SUBVENDOR_ID_CONNECT_TECH,
3221 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3222 pbn_b0_8_1843200_200 },
3223 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3224 PCI_SUBVENDOR_ID_CONNECT_TECH,
3225 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3226 pbn_b0_2_1843200_200 },
3227 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3228 PCI_SUBVENDOR_ID_CONNECT_TECH,
3229 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3230 pbn_b0_4_1843200_200 },
3231 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3232 PCI_SUBVENDOR_ID_CONNECT_TECH,
3233 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3234 pbn_b0_8_1843200_200 },
3235 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3236 PCI_SUBVENDOR_ID_CONNECT_TECH,
3237 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3238 pbn_b0_2_1843200_200 },
3239 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3240 PCI_SUBVENDOR_ID_CONNECT_TECH,
3241 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3242 pbn_b0_4_1843200_200 },
3243 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3244 PCI_SUBVENDOR_ID_CONNECT_TECH,
3245 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3246 pbn_b0_8_1843200_200 },
c68d2b15
BH		 3247 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3248 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3249 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 3250
3251 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 3252 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3253 pbn_b2_bt_1_115200 },
3254 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 3255 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3256 pbn_b2_bt_2_115200 },
3257 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 3258 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3259 pbn_b2_bt_4_115200 },
3260 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 3261 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3262 pbn_b2_bt_2_115200 },
3263 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 3264 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3265 pbn_b2_bt_4_115200 },
3266 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 3267 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3268 pbn_b2_8_115200 },
e65f0f82
FL		 3269 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3270 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3271 pbn_b2_8_460800 },
1da177e4
LT		 3272 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3274 pbn_b2_8_115200 },
3275
3276 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3277 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3278 pbn_b2_bt_2_115200 },
3279 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3280 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3281 pbn_b2_bt_2_921600 },
3282 /*
3283 * VScom SPCOM800, from sl@s.pl
3284 */
5756ee99
AC		 3285 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3286 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3287 pbn_b2_8_921600 },
3288 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 3289 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3290 pbn_b2_4_921600 },
b76c5a07
CB		 3291 /* Unknown card - subdevice 0x1584 */
3292 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3293 PCI_VENDOR_ID_PLX,
3294 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3295 pbn_b0_4_115200 },
1da177e4
LT		 3296 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3297 PCI_SUBVENDOR_ID_KEYSPAN,
3298 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3299 pbn_panacom },
3300 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3301 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3302 pbn_panacom4 },
3303 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3304 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3305 pbn_panacom2 },
a9cccd34
MF		 3306 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3307 PCI_VENDOR_ID_ESDGMBH,
3308 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3309 pbn_b2_4_115200 },
1da177e4
LT		 3310 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3311 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3312 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 3313 pbn_b2_4_460800 },
3314 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3315 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3316 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 3317 pbn_b2_8_460800 },
3318 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3319 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3320 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 3321 pbn_b2_16_460800 },
3322 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3323 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3324 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 3325 pbn_b2_16_460800 },
3326 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3327 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 3328 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 3329 pbn_b2_4_460800 },
3330 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3331 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 3332 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 3333 pbn_b2_8_460800 },
add7b58e
BH		 3334 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3335 PCI_SUBVENDOR_ID_EXSYS,
3336 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
ee4cd1b2 3337 pbn_b2_4_115200 },
1da177e4
LT		 3338 /*
3339 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3340 * (Exoray@isys.ca)
3341 */
3342 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3343 0x10b5, 0x106a, 0, 0,
3344 pbn_plx_romulus },
3345 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3346 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3347 pbn_b1_4_115200 },
3348 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3349 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3350 pbn_b1_2_115200 },
3351 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3352 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3353 pbn_b1_8_115200 },
3354 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3355 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3356 pbn_b1_8_115200 },
3357 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 3358 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3359 0, 0,
1da177e4 3360 pbn_b0_4_921600 },
fbc0dc0d 3361 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 3362 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3363 0, 0,
fbc0dc0d 3364 pbn_b0_4_1152000 },
c9bd9d01
MP		 3365 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3366 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3367 pbn_b0_bt_2_921600 },
db1de159
DR		 3368
3369 /*
3370 * The below card is a little controversial since it is the
3371 * subject of a PCI vendor/device ID clash. (See
3372 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3373 * For now just used the hex ID 0x950a.
3374 */
39aced68 3375 { PCI_VENDOR_ID_OXSEMI, 0x950a,
26e8220a
FL		 3376 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
3377 0, 0, pbn_b0_2_115200 },
3378 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3379 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
3380 0, 0, pbn_b0_2_115200 },
db1de159
DR		 3381 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3382 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3383 pbn_b0_2_1130000 },
70fd8fde
AP		 3384 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3385 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3386 pbn_b0_1_921600 },
1da177e4
LT		 3387 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3388 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3389 pbn_b0_4_115200 },
3390 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3391 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3392 pbn_b0_bt_2_921600 },
e847003f
LB		 3393 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3394 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3395 pbn_b2_8_1152000 },
1da177e4 3396
7106b4e3
LH		 3397 /*
3398 * Oxford Semiconductor Inc. Tornado PCI express device range.
3399 */
3400 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3401 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3402 pbn_b0_1_4000000 },
3403 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3404 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3405 pbn_b0_1_4000000 },
3406 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3407 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3408 pbn_oxsemi_1_4000000 },
3409 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3410 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3411 pbn_oxsemi_1_4000000 },
3412 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3414 pbn_b0_1_4000000 },
3415 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3417 pbn_b0_1_4000000 },
3418 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3420 pbn_oxsemi_1_4000000 },
3421 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3423 pbn_oxsemi_1_4000000 },
3424 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3426 pbn_b0_1_4000000 },
3427 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3429 pbn_b0_1_4000000 },
3430 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3432 pbn_b0_1_4000000 },
3433 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3435 pbn_b0_1_4000000 },
3436 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3438 pbn_oxsemi_2_4000000 },
3439 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3441 pbn_oxsemi_2_4000000 },
3442 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3444 pbn_oxsemi_4_4000000 },
3445 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3446 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3447 pbn_oxsemi_4_4000000 },
3448 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3449 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3450 pbn_oxsemi_8_4000000 },
3451 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3452 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3453 pbn_oxsemi_8_4000000 },
3454 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3455 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3456 pbn_oxsemi_1_4000000 },
3457 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3458 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3459 pbn_oxsemi_1_4000000 },
3460 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3461 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3462 pbn_oxsemi_1_4000000 },
3463 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3464 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3465 pbn_oxsemi_1_4000000 },
3466 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3467 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3468 pbn_oxsemi_1_4000000 },
3469 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3471 pbn_oxsemi_1_4000000 },
3472 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3474 pbn_oxsemi_1_4000000 },
3475 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3477 pbn_oxsemi_1_4000000 },
3478 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3480 pbn_oxsemi_1_4000000 },
3481 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3482 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3483 pbn_oxsemi_1_4000000 },
3484 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3486 pbn_oxsemi_1_4000000 },
3487 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3489 pbn_oxsemi_1_4000000 },
3490 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3492 pbn_oxsemi_1_4000000 },
3493 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3494 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3495 pbn_oxsemi_1_4000000 },
3496 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3497 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3498 pbn_oxsemi_1_4000000 },
3499 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3500 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3501 pbn_oxsemi_1_4000000 },
3502 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3503 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3504 pbn_oxsemi_1_4000000 },
3505 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3507 pbn_oxsemi_1_4000000 },
3508 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3510 pbn_oxsemi_1_4000000 },
3511 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3513 pbn_oxsemi_1_4000000 },
3514 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3515 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3516 pbn_oxsemi_1_4000000 },
3517 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3518 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3519 pbn_oxsemi_1_4000000 },
3520 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3521 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3522 pbn_oxsemi_1_4000000 },
3523 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3525 pbn_oxsemi_1_4000000 },
3526 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3527 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3528 pbn_oxsemi_1_4000000 },
3529 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3530 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3531 pbn_oxsemi_1_4000000 },
b80de369
LH		 3532 /*
3533 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3534 */
3535 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3536 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3537 pbn_oxsemi_1_4000000 },
3538 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3539 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3540 pbn_oxsemi_2_4000000 },
3541 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3542 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3543 pbn_oxsemi_4_4000000 },
3544 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3545 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3546 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 3547
3548 /*
3549 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3550 */
3551 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3552 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3553 pbn_oxsemi_2_4000000 },
3554
1da177e4
LT		 3555 /*
3556 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3557 * from skokodyn@yahoo.com
3558 */
3559 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3560 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3561 pbn_sbsxrsio },
3562 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3563 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3564 pbn_sbsxrsio },
3565 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3566 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3567 pbn_sbsxrsio },
3568 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3569 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3570 pbn_sbsxrsio },
3571
3572 /*
3573 * Digitan DS560-558, from jimd@esoft.com
3574 */
3575 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 3576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3577 pbn_b1_1_115200 },
3578
3579 /*
3580 * Titan Electronic cards
3581 * The 400L and 800L have a custom setup quirk.
3582 */
3583 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 3584 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3585 pbn_b0_1_921600 },
3586 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 3587 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3588 pbn_b0_2_921600 },
3589 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 3590 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3591 pbn_b0_4_921600 },
3592 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 3593 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3594 pbn_b0_4_921600 },
3595 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3596 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3597 pbn_b1_1_921600 },
3598 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3599 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3600 pbn_b1_bt_2_921600 },
3601 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3603 pbn_b0_bt_4_921600 },
3604 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3605 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3606 pbn_b0_bt_8_921600 },
66169ad1
YY		 3607 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3608 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3609 pbn_b4_bt_2_921600 },
3610 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3611 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3612 pbn_b4_bt_4_921600 },
3613 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3614 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3615 pbn_b4_bt_8_921600 },
3616 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3617 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3618 pbn_b0_4_921600 },
3619 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3620 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3621 pbn_b0_4_921600 },
3622 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3624 pbn_b0_4_921600 },
3625 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3627 pbn_oxsemi_1_4000000 },
3628 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3630 pbn_oxsemi_2_4000000 },
3631 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3633 pbn_oxsemi_4_4000000 },
3634 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3636 pbn_oxsemi_8_4000000 },
3637 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3639 pbn_oxsemi_2_4000000 },
3640 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3642 pbn_oxsemi_2_4000000 },
1e9deb11
YY		 3643 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
3644 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3645 pbn_b0_4_921600 },
3646 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
3647 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3648 pbn_b0_4_921600 },
3649 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
3650 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3651 pbn_b0_4_921600 },
3652 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
3653 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3654 pbn_b0_4_921600 },
1da177e4
LT		 3655
3656 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3657 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3658 pbn_b2_1_460800 },
3659 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3660 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3661 pbn_b2_1_460800 },
3662 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3663 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3664 pbn_b2_1_460800 },
3665 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3666 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3667 pbn_b2_bt_2_921600 },
3668 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3669 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3670 pbn_b2_bt_2_921600 },
3671 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3672 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3673 pbn_b2_bt_2_921600 },
3674 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3675 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3676 pbn_b2_bt_4_921600 },
3677 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3678 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3679 pbn_b2_bt_4_921600 },
3680 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3681 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3682 pbn_b2_bt_4_921600 },
3683 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3684 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3685 pbn_b0_1_921600 },
3686 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3687 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3688 pbn_b0_1_921600 },
3689 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3690 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3691 pbn_b0_1_921600 },
3692 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3693 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3694 pbn_b0_bt_2_921600 },
3695 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3697 pbn_b0_bt_2_921600 },
3698 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3700 pbn_b0_bt_2_921600 },
3701 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3702 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3703 pbn_b0_bt_4_921600 },
3704 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3705 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3706 pbn_b0_bt_4_921600 },
3707 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3708 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3709 pbn_b0_bt_4_921600 },
3ec9c594
AP		 3710 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3711 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3712 pbn_b0_bt_8_921600 },
3713 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3714 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3715 pbn_b0_bt_8_921600 },
3716 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3717 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3718 pbn_b0_bt_8_921600 },
1da177e4
LT		 3719
3720 /*
3721 * Computone devices submitted by Doug McNash dmcnash@computone.com
3722 */
3723 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3724 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3725 0, 0, pbn_computone_4 },
3726 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3727 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3728 0, 0, pbn_computone_8 },
3729 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3730 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3731 0, 0, pbn_computone_6 },
3732
3733 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3734 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3735 pbn_oxsemi },
3736 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3737 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3738 pbn_b0_bt_1_921600 },
3739
3740 /*
3741 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3742 */
3743 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3744 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3745 pbn_b0_bt_8_115200 },
3746 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3747 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3748 pbn_b0_bt_8_115200 },
3749
3750 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3752 pbn_b0_bt_2_115200 },
3753 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3755 pbn_b0_bt_2_115200 },
3756 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3757 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3758 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 3759 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3760 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3761 pbn_b0_bt_2_115200 },
3762 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3763 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3764 pbn_b0_bt_2_115200 },
1da177e4
LT		 3765 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3766 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3767 pbn_b0_bt_4_460800 },
3768 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3769 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3770 pbn_b0_bt_4_460800 },
3771 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3772 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3773 pbn_b0_bt_2_460800 },
3774 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3775 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3776 pbn_b0_bt_2_460800 },
3777 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3778 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3779 pbn_b0_bt_2_460800 },
3780 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3781 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3782 pbn_b0_bt_1_115200 },
3783 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3785 pbn_b0_bt_1_460800 },
3786
1fb8cacc
RK		 3787 /*
3788 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3789 * Cards are identified by their subsystem vendor IDs, which
3790 * (in hex) match the model number.
3791 *
3792 * Note that JC140x are RS422/485 cards which require ox950
3793 * ACR = 0x10, and as such are not currently fully supported.
3794 */
3795 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3796 0x1204, 0x0004, 0, 0,
3797 pbn_b0_4_921600 },
3798 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3799 0x1208, 0x0004, 0, 0,
3800 pbn_b0_4_921600 },
3801/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3802 0x1402, 0x0002, 0, 0,
3803 pbn_b0_2_921600 }, */
3804/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3805 0x1404, 0x0004, 0, 0,
3806 pbn_b0_4_921600 }, */
3807 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3808 0x1208, 0x0004, 0, 0,
3809 pbn_b0_4_921600 },
3810
2a52fcb5
KY		 3811 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3812 0x1204, 0x0004, 0, 0,
3813 pbn_b0_4_921600 },
3814 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3815 0x1208, 0x0004, 0, 0,
3816 pbn_b0_4_921600 },
3817 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3818 0x1208, 0x0004, 0, 0,
3819 pbn_b0_4_921600 },
1da177e4
LT		 3820 /*
3821 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3822 */
3823 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3824 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3825 pbn_b1_1_1382400 },
3826
3827 /*
3828 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3829 */
3830 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3831 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3832 pbn_b1_1_1382400 },
3833
3834 /*
3835 * RAStel 2 port modem, gerg@moreton.com.au
3836 */
3837 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3838 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3839 pbn_b2_bt_2_115200 },
3840
3841 /*
3842 * EKF addition for i960 Boards form EKF with serial port
3843 */
3844 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3845 0xE4BF, PCI_ANY_ID, 0, 0,
3846 pbn_intel_i960 },
3847
3848 /*
3849 * Xircom Cardbus/Ethernet combos
3850 */
3851 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3853 pbn_b0_1_115200 },
3854 /*
3855 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3856 */
3857 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3858 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3859 pbn_b0_1_115200 },
3860
3861 /*
3862 * Untested PCI modems, sent in from various folks...
3863 */
3864
3865 /*
3866 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3867 */
3868 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3869 0x1048, 0x1500, 0, 0,
3870 pbn_b1_1_115200 },
3871
3872 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3873 0xFF00, 0, 0, 0,
3874 pbn_sgi_ioc3 },
3875
3876 /*
3877 * HP Diva card
3878 */
3879 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3880 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3881 pbn_b1_1_115200 },
3882 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3884 pbn_b0_5_115200 },
3885 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3887 pbn_b2_1_115200 },
3888
d9004eb4
ABL		 3889 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3891 pbn_b3_2_115200 },
1da177e4
LT		 3892 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3894 pbn_b3_4_115200 },
3895 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3897 pbn_b3_8_115200 },
3898
3899 /*
3900 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3901 */
3902 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3903 PCI_ANY_ID, PCI_ANY_ID,
3904 0,
3905 0, pbn_exar_XR17C152 },
3906 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3907 PCI_ANY_ID, PCI_ANY_ID,
3908 0,
3909 0, pbn_exar_XR17C154 },
3910 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3911 PCI_ANY_ID, PCI_ANY_ID,
3912 0,
3913 0, pbn_exar_XR17C158 },
dc96efb7
MS		 3914 /*
3915 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
3916 */
3917 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
3918 PCI_ANY_ID, PCI_ANY_ID,
3919 0,
3920 0, pbn_exar_XR17V352 },
3921 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
3922 PCI_ANY_ID, PCI_ANY_ID,
3923 0,
3924 0, pbn_exar_XR17V354 },
3925 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
3926 PCI_ANY_ID, PCI_ANY_ID,
3927 0,
3928 0, pbn_exar_XR17V358 },
1da177e4
LT		 3929
3930 /*
3931 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3932 */
3933 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3935 pbn_b0_1_115200 },
84f8c6fc
NV		 3936 /*
3937 * ITE
3938 */
3939 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3940 PCI_ANY_ID, PCI_ANY_ID,
3941 0, 0,
3942 pbn_b1_bt_1_115200 },
1da177e4 3943
737c1756
PH		 3944 /*
3945 * IntaShield IS-200
3946 */
3947 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3948 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3949 pbn_b2_2_115200 },
4b6f6ce9
IGP		 3950 /*
3951 * IntaShield IS-400
3952 */
3953 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3954 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3955 pbn_b2_4_115200 },
48212008
TH		 3956 /*
3957 * Perle PCI-RAS cards
3958 */
3959 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3960 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3961 0, 0, pbn_b2_4_921600 },
3962 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3963 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3964 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 3965
3966 /*
3967 * Mainpine series cards: Fairly standard layout but fools
3968 * parts of the autodetect in some cases and uses otherwise
3969 * unmatched communications subclasses in the PCI Express case
3970 */
3971
3972 { /* RockForceDUO */
3973 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3974 PCI_VENDOR_ID_MAINPINE, 0x0200,
3975 0, 0, pbn_b0_2_115200 },
3976 { /* RockForceQUATRO */
3977 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3978 PCI_VENDOR_ID_MAINPINE, 0x0300,
3979 0, 0, pbn_b0_4_115200 },
3980 { /* RockForceDUO+ */
3981 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3982 PCI_VENDOR_ID_MAINPINE, 0x0400,
3983 0, 0, pbn_b0_2_115200 },
3984 { /* RockForceQUATRO+ */
3985 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3986 PCI_VENDOR_ID_MAINPINE, 0x0500,
3987 0, 0, pbn_b0_4_115200 },
3988 { /* RockForce+ */
3989 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3990 PCI_VENDOR_ID_MAINPINE, 0x0600,
3991 0, 0, pbn_b0_2_115200 },
3992 { /* RockForce+ */
3993 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3994 PCI_VENDOR_ID_MAINPINE, 0x0700,
3995 0, 0, pbn_b0_4_115200 },
3996 { /* RockForceOCTO+ */
3997 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3998 PCI_VENDOR_ID_MAINPINE, 0x0800,
3999 0, 0, pbn_b0_8_115200 },
4000 { /* RockForceDUO+ */
4001 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4002 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4003 0, 0, pbn_b0_2_115200 },
4004 { /* RockForceQUARTRO+ */
4005 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4006 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4007 0, 0, pbn_b0_4_115200 },
4008 { /* RockForceOCTO+ */
4009 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4010 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4011 0, 0, pbn_b0_8_115200 },
4012 { /* RockForceD1 */
4013 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4014 PCI_VENDOR_ID_MAINPINE, 0x2000,
4015 0, 0, pbn_b0_1_115200 },
4016 { /* RockForceF1 */
4017 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4018 PCI_VENDOR_ID_MAINPINE, 0x2100,
4019 0, 0, pbn_b0_1_115200 },
4020 { /* RockForceD2 */
4021 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4022 PCI_VENDOR_ID_MAINPINE, 0x2200,
4023 0, 0, pbn_b0_2_115200 },
4024 { /* RockForceF2 */
4025 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4026 PCI_VENDOR_ID_MAINPINE, 0x2300,
4027 0, 0, pbn_b0_2_115200 },
4028 { /* RockForceD4 */
4029 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4030 PCI_VENDOR_ID_MAINPINE, 0x2400,
4031 0, 0, pbn_b0_4_115200 },
4032 { /* RockForceF4 */
4033 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4034 PCI_VENDOR_ID_MAINPINE, 0x2500,
4035 0, 0, pbn_b0_4_115200 },
4036 { /* RockForceD8 */
4037 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4038 PCI_VENDOR_ID_MAINPINE, 0x2600,
4039 0, 0, pbn_b0_8_115200 },
4040 { /* RockForceF8 */
4041 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4042 PCI_VENDOR_ID_MAINPINE, 0x2700,
4043 0, 0, pbn_b0_8_115200 },
4044 { /* IQ Express D1 */
4045 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4046 PCI_VENDOR_ID_MAINPINE, 0x3000,
4047 0, 0, pbn_b0_1_115200 },
4048 { /* IQ Express F1 */
4049 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4050 PCI_VENDOR_ID_MAINPINE, 0x3100,
4051 0, 0, pbn_b0_1_115200 },
4052 { /* IQ Express D2 */
4053 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4054 PCI_VENDOR_ID_MAINPINE, 0x3200,
4055 0, 0, pbn_b0_2_115200 },
4056 { /* IQ Express F2 */
4057 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4058 PCI_VENDOR_ID_MAINPINE, 0x3300,
4059 0, 0, pbn_b0_2_115200 },
4060 { /* IQ Express D4 */
4061 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4062 PCI_VENDOR_ID_MAINPINE, 0x3400,
4063 0, 0, pbn_b0_4_115200 },
4064 { /* IQ Express F4 */
4065 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4066 PCI_VENDOR_ID_MAINPINE, 0x3500,
4067 0, 0, pbn_b0_4_115200 },
4068 { /* IQ Express D8 */
4069 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4070 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4071 0, 0, pbn_b0_8_115200 },
4072 { /* IQ Express F8 */
4073 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4074 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4075 0, 0, pbn_b0_8_115200 },
4076
4077
aa798505
OJ		 4078 /*
4079 * PA Semi PA6T-1682M on-chip UART
4080 */
4081 { PCI_VENDOR_ID_PASEMI, 0xa004,
4082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4083 pbn_pasemi_1682M },
4084
46a0fac9
SB		 4085 /*
4086 * National Instruments
4087 */
04bf7e74
WP		 4088 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4089 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4090 pbn_b1_16_115200 },
4091 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4092 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4093 pbn_b1_8_115200 },
4094 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4095 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4096 pbn_b1_bt_4_115200 },
4097 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4098 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4099 pbn_b1_bt_2_115200 },
4100 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4101 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4102 pbn_b1_bt_4_115200 },
4103 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4104 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4105 pbn_b1_bt_2_115200 },
4106 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4108 pbn_b1_16_115200 },
4109 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4110 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4111 pbn_b1_8_115200 },
4112 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4113 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4114 pbn_b1_bt_4_115200 },
4115 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4116 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4117 pbn_b1_bt_2_115200 },
4118 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4119 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4120 pbn_b1_bt_4_115200 },
4121 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4123 pbn_b1_bt_2_115200 },
46a0fac9
SB		 4124 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4125 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4126 pbn_ni8430_2 },
4127 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4129 pbn_ni8430_2 },
4130 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4131 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4132 pbn_ni8430_4 },
4133 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4134 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4135 pbn_ni8430_4 },
4136 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4137 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4138 pbn_ni8430_8 },
4139 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4141 pbn_ni8430_8 },
4142 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4143 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4144 pbn_ni8430_16 },
4145 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4147 pbn_ni8430_16 },
4148 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4150 pbn_ni8430_2 },
4151 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4153 pbn_ni8430_2 },
4154 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4155 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4156 pbn_ni8430_4 },
4157 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4159 pbn_ni8430_4 },
4160
02c9b5cf
KJ		 4161 /*
4162 * ADDI-DATA GmbH communication cards <info@addi-data.com>
4163 */
4164 { PCI_VENDOR_ID_ADDIDATA,
4165 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4166 PCI_ANY_ID,
4167 PCI_ANY_ID,
4168 0,
4169 0,
4170 pbn_b0_4_115200 },
4171
4172 { PCI_VENDOR_ID_ADDIDATA,
4173 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4174 PCI_ANY_ID,
4175 PCI_ANY_ID,
4176 0,
4177 0,
4178 pbn_b0_2_115200 },
4179
4180 { PCI_VENDOR_ID_ADDIDATA,
4181 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4182 PCI_ANY_ID,
4183 PCI_ANY_ID,
4184 0,
4185 0,
4186 pbn_b0_1_115200 },
4187
4188 { PCI_VENDOR_ID_ADDIDATA_OLD,
4189 PCI_DEVICE_ID_ADDIDATA_APCI7800,
4190 PCI_ANY_ID,
4191 PCI_ANY_ID,
4192 0,
4193 0,
4194 pbn_b1_8_115200 },
4195
4196 { PCI_VENDOR_ID_ADDIDATA,
4197 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4198 PCI_ANY_ID,
4199 PCI_ANY_ID,
4200 0,
4201 0,
4202 pbn_b0_4_115200 },
4203
4204 { PCI_VENDOR_ID_ADDIDATA,
4205 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4206 PCI_ANY_ID,
4207 PCI_ANY_ID,
4208 0,
4209 0,
4210 pbn_b0_2_115200 },
4211
4212 { PCI_VENDOR_ID_ADDIDATA,
4213 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4214 PCI_ANY_ID,
4215 PCI_ANY_ID,
4216 0,
4217 0,
4218 pbn_b0_1_115200 },
4219
4220 { PCI_VENDOR_ID_ADDIDATA,
4221 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4222 PCI_ANY_ID,
4223 PCI_ANY_ID,
4224 0,
4225 0,
4226 pbn_b0_4_115200 },
4227
4228 { PCI_VENDOR_ID_ADDIDATA,
4229 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4230 PCI_ANY_ID,
4231 PCI_ANY_ID,
4232 0,
4233 0,
4234 pbn_b0_2_115200 },
4235
4236 { PCI_VENDOR_ID_ADDIDATA,
4237 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4238 PCI_ANY_ID,
4239 PCI_ANY_ID,
4240 0,
4241 0,
4242 pbn_b0_1_115200 },
4243
4244 { PCI_VENDOR_ID_ADDIDATA,
4245 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4246 PCI_ANY_ID,
4247 PCI_ANY_ID,
4248 0,
4249 0,
4250 pbn_b0_8_115200 },
4251
1b62cbf2
KJ		 4252 { PCI_VENDOR_ID_ADDIDATA,
4253 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4254 PCI_ANY_ID,
4255 PCI_ANY_ID,
4256 0,
4257 0,
4258 pbn_ADDIDATA_PCIe_4_3906250 },
4259
4260 { PCI_VENDOR_ID_ADDIDATA,
4261 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4262 PCI_ANY_ID,
4263 PCI_ANY_ID,
4264 0,
4265 0,
4266 pbn_ADDIDATA_PCIe_2_3906250 },
4267
4268 { PCI_VENDOR_ID_ADDIDATA,
4269 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4270 PCI_ANY_ID,
4271 PCI_ANY_ID,
4272 0,
4273 0,
4274 pbn_ADDIDATA_PCIe_1_3906250 },
4275
4276 { PCI_VENDOR_ID_ADDIDATA,
4277 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4278 PCI_ANY_ID,
4279 PCI_ANY_ID,
4280 0,
4281 0,
4282 pbn_ADDIDATA_PCIe_8_3906250 },
4283
25cf9bc1
JS		 4284 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4285 PCI_VENDOR_ID_IBM, 0x0299,
4286 0, 0, pbn_b0_bt_2_115200 },
4287
c4285b47
MB		 4288 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4289 0xA000, 0x1000,
4290 0, 0, pbn_b0_1_115200 },
4291
7808edcd
NG		 4292 /* the 9901 is a rebranded 9912 */
4293 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4294 0xA000, 0x1000,
4295 0, 0, pbn_b0_1_115200 },
4296
4297 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4298 0xA000, 0x1000,
4299 0, 0, pbn_b0_1_115200 },
4300
4301 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4302 0xA000, 0x1000,
4303 0, 0, pbn_b0_1_115200 },
4304
4305 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4306 0xA000, 0x1000,
4307 0, 0, pbn_b0_1_115200 },
4308
4309 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4310 0xA000, 0x3002,
4311 0, 0, pbn_NETMOS9900_2s_115200 },
4312
ac6ec5b1 4313 /*
44178176 4314 * Best Connectivity and Rosewill PCI Multi I/O cards
ac6ec5b1
IS		 4315 */
4316
4317 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4318 0xA000, 0x1000,
4319 0, 0, pbn_b0_1_115200 },
4320
44178176
ES		 4321 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4322 0xA000, 0x3002,
4323 0, 0, pbn_b0_bt_2_115200 },
4324
ac6ec5b1
IS		 4325 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4326 0xA000, 0x3004,
4327 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 4328 /* Intel CE4100 */
4329 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4330 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4331 pbn_ce4100_1_115200 },
4332
d9a0fbfd
AP		 4333 /*
4334 * Cronyx Omega PCI
4335 */
4336 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4337 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4338 pbn_omegapci },
ac6ec5b1 4339
6683549e
AC		 4340 /*
4341 * AgeStar as-prs2-009
4342 */
4343 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
4344 PCI_ANY_ID, PCI_ANY_ID,
4345 0, 0, pbn_b0_bt_2_115200 },
27788c5f
AC		 4346
4347 /*
4348 * WCH CH353 series devices: The 2S1P is handled by parport_serial
4349 * so not listed here.
4350 */
4351 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
4352 PCI_ANY_ID, PCI_ANY_ID,
4353 0, 0, pbn_b0_bt_4_115200 },
4354
4355 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
4356 PCI_ANY_ID, PCI_ANY_ID,
4357 0, 0, pbn_b0_bt_2_115200 },
4358
1da177e4
LT		 4359 /*
4360 * These entries match devices with class COMMUNICATION_SERIAL,
4361 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4362 */
4363 { PCI_ANY_ID, PCI_ANY_ID,
4364 PCI_ANY_ID, PCI_ANY_ID,
4365 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4366 0xffff00, pbn_default },
4367 { PCI_ANY_ID, PCI_ANY_ID,
4368 PCI_ANY_ID, PCI_ANY_ID,
4369 PCI_CLASS_COMMUNICATION_MODEM << 8,
4370 0xffff00, pbn_default },
4371 { PCI_ANY_ID, PCI_ANY_ID,
4372 PCI_ANY_ID, PCI_ANY_ID,
4373 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4374 0xffff00, pbn_default },
4375 { 0, }
4376};
4377
2807190b
MR		 4378static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4379 pci_channel_state_t state)
4380{
4381 struct serial_private *priv = pci_get_drvdata(dev);
4382
4383 if (state == pci_channel_io_perm_failure)
4384 return PCI_ERS_RESULT_DISCONNECT;
4385
4386 if (priv)
4387 pciserial_suspend_ports(priv);
4388
4389 pci_disable_device(dev);
4390
4391 return PCI_ERS_RESULT_NEED_RESET;
4392}
4393
4394static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4395{
4396 int rc;
4397
4398 rc = pci_enable_device(dev);
4399
4400 if (rc)
4401 return PCI_ERS_RESULT_DISCONNECT;
4402
4403 pci_restore_state(dev);
4404 pci_save_state(dev);
4405
4406 return PCI_ERS_RESULT_RECOVERED;
4407}
4408
4409static void serial8250_io_resume(struct pci_dev *dev)
4410{
4411 struct serial_private *priv = pci_get_drvdata(dev);
4412
4413 if (priv)
4414 pciserial_resume_ports(priv);
4415}
4416
1d352035 4417static const struct pci_error_handlers serial8250_err_handler = {
2807190b
MR		 4418 .error_detected = serial8250_io_error_detected,
4419 .slot_reset = serial8250_io_slot_reset,
4420 .resume = serial8250_io_resume,
4421};
4422
1da177e4
LT		 4423static struct pci_driver serial_pci_driver = {
4424 .name = "serial",
4425 .probe = pciserial_init_one,
2d47b716 4426 .remove = pciserial_remove_one,
1d5e7996 4427#ifdef CONFIG_PM
1da177e4
LT		 4428 .suspend = pciserial_suspend_one,
4429 .resume = pciserial_resume_one,
1d5e7996 4430#endif
1da177e4 4431 .id_table = serial_pci_tbl,
2807190b 4432 .err_handler = &serial8250_err_handler,
1da177e4
LT		 4433};
4434
15a12e83 4435module_pci_driver(serial_pci_driver);
1da177e4
LT		 4436
4437MODULE_LICENSE("GPL");
4438MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4439MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux kernel - Deliverables
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