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Revert "serial/8250_pci: setup-quirk workaround for the kt serial controller"
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4
LT		 11 */
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
20#include <linux/serial_core.h>
21#include <linux/8250_pci.h>
22#include <linux/bitops.h>
23
24#include <asm/byteorder.h>
25#include <asm/io.h>
26
27#include "8250.h"
28
29#undef SERIAL_DEBUG_PCI
30
1da177e4
LT		 31/*
32 * init function returns:
33 * > 0 - number of ports
34 * = 0 - use board->num_ports
35 * < 0 - error
36 */
37struct pci_serial_quirk {
38 u32 vendor;
39 u32 device;
40 u32 subvendor;
41 u32 subdevice;
5bf8f501 42 int (*probe)(struct pci_dev *dev);
1da177e4 43 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 44 int (*setup)(struct serial_private *,
45 const struct pciserial_board *,
05caac58 46 struct uart_port *, int);
1da177e4
LT		 47 void (*exit)(struct pci_dev *dev);
48};
49
50#define PCI_NUM_BAR_RESOURCES 6
51
52struct serial_private {
70db3d91 53 struct pci_dev *dev;
1da177e4
LT		 54 unsigned int nr;
55 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
56 struct pci_serial_quirk *quirk;
57 int line[0];
58};
59
7808edcd
NG		 60static int pci_default_setup(struct serial_private*,
61 const struct pciserial_board*, struct uart_port*, int);
62
1da177e4
LT		 63static void moan_device(const char *str, struct pci_dev *dev)
64{
ad361c98
JP		 65 printk(KERN_WARNING
66 "%s: %s\n"
67 "Please send the output of lspci -vv, this\n"
68 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
69 "manufacturer and name of serial board or\n"
70 "modem board to rmk+serial@arm.linux.org.uk.\n",
1da177e4
LT		 71 pci_name(dev), str, dev->vendor, dev->device,
72 dev->subsystem_vendor, dev->subsystem_device);
73}
74
75static int
70db3d91 76setup_port(struct serial_private *priv, struct uart_port *port,
1da177e4
LT		 77 int bar, int offset, int regshift)
78{
70db3d91 79 struct pci_dev *dev = priv->dev;
1da177e4
LT		 80 unsigned long base, len;
81
82 if (bar >= PCI_NUM_BAR_RESOURCES)
83 return -EINVAL;
84
72ce9a83
RK		 85 base = pci_resource_start(dev, bar);
86
1da177e4 87 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 88 len = pci_resource_len(dev, bar);
89
90 if (!priv->remapped_bar[bar])
6f441fe9 91 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 92 if (!priv->remapped_bar[bar])
93 return -ENOMEM;
94
95 port->iotype = UPIO_MEM;
72ce9a83 96 port->iobase = 0;
1da177e4
LT		 97 port->mapbase = base + offset;
98 port->membase = priv->remapped_bar[bar] + offset;
99 port->regshift = regshift;
100 } else {
1da177e4 101 port->iotype = UPIO_PORT;
72ce9a83
RK		 102 port->iobase = base + offset;
103 port->mapbase = 0;
104 port->membase = NULL;
105 port->regshift = 0;
1da177e4
LT		 106 }
107 return 0;
108}
109
02c9b5cf
KJ		 110/*
111 * ADDI-DATA GmbH communication cards <info@addi-data.com>
112 */
113static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 114 const struct pciserial_board *board,
02c9b5cf
KJ		 115 struct uart_port *port, int idx)
116{
117 unsigned int bar = 0, offset = board->first_offset;
118 bar = FL_GET_BASE(board->flags);
119
120 if (idx < 2) {
121 offset += idx * board->uart_offset;
122 } else if ((idx >= 2) && (idx < 4)) {
123 bar += 1;
124 offset += ((idx - 2) * board->uart_offset);
125 } else if ((idx >= 4) && (idx < 6)) {
126 bar += 2;
127 offset += ((idx - 4) * board->uart_offset);
128 } else if (idx >= 6) {
129 bar += 3;
130 offset += ((idx - 6) * board->uart_offset);
131 }
132
133 return setup_port(priv, port, bar, offset, board->reg_shift);
134}
135
1da177e4
LT		 136/*
137 * AFAVLAB uses a different mixture of BARs and offsets
138 * Not that ugly ;) -- HW
139 */
140static int
975a1a7d 141afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 142 struct uart_port *port, int idx)
143{
144 unsigned int bar, offset = board->first_offset;
5756ee99 145
1da177e4
LT		 146 bar = FL_GET_BASE(board->flags);
147 if (idx < 4)
148 bar += idx;
149 else {
150 bar = 4;
151 offset += (idx - 4) * board->uart_offset;
152 }
153
70db3d91 154 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 155}
156
157/*
158 * HP's Remote Management Console. The Diva chip came in several
159 * different versions. N-class, L2000 and A500 have two Diva chips, each
160 * with 3 UARTs (the third UART on the second chip is unused). Superdome
161 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
162 * one Diva chip, but it has been expanded to 5 UARTs.
163 */
61a116ef 164static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 165{
166 int rc = 0;
167
168 switch (dev->subsystem_device) {
169 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
170 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
171 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
172 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
173 rc = 3;
174 break;
175 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
176 rc = 2;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
179 rc = 4;
180 break;
181 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 182 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 183 rc = 1;
184 break;
185 }
186
187 return rc;
188}
189
190/*
191 * HP's Diva chip puts the 4th/5th serial port further out, and
192 * some serial ports are supposed to be hidden on certain models.
193 */
194static int
975a1a7d
RK		 195pci_hp_diva_setup(struct serial_private *priv,
196 const struct pciserial_board *board,
197 struct uart_port *port, int idx)
1da177e4
LT		 198{
199 unsigned int offset = board->first_offset;
200 unsigned int bar = FL_GET_BASE(board->flags);
201
70db3d91 202 switch (priv->dev->subsystem_device) {
1da177e4
LT		 203 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
204 if (idx == 3)
205 idx++;
206 break;
207 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
208 if (idx > 0)
209 idx++;
210 if (idx > 2)
211 idx++;
212 break;
213 }
214 if (idx > 2)
215 offset = 0x18;
216
217 offset += idx * board->uart_offset;
218
70db3d91 219 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 220}
221
222/*
223 * Added for EKF Intel i960 serial boards
224 */
61a116ef 225static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 226{
227 unsigned long oldval;
228
229 if (!(dev->subsystem_device & 0x1000))
230 return -ENODEV;
231
232 /* is firmware started? */
5756ee99
AC		 233 pci_read_config_dword(dev, 0x44, (void *)&oldval);
234 if (oldval == 0x00001000L) { /* RESET value */
1da177e4
LT		 235 printk(KERN_DEBUG "Local i960 firmware missing");
236 return -ENODEV;
237 }
238 return 0;
239}
240
241/*
242 * Some PCI serial cards using the PLX 9050 PCI interface chip require
243 * that the card interrupt be explicitly enabled or disabled. This
244 * seems to be mainly needed on card using the PLX which also use I/O
245 * mapped memory.
246 */
61a116ef 247static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 248{
249 u8 irq_config;
250 void __iomem *p;
251
252 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
253 moan_device("no memory in bar 0", dev);
254 return 0;
255 }
256
257 irq_config = 0x41;
add7b58e 258 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 259 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 260 irq_config = 0x43;
5756ee99 261
1da177e4 262 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 263 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 264 /*
265 * As the megawolf cards have the int pins active
266 * high, and have 2 UART chips, both ints must be
267 * enabled on the 9050. Also, the UARTS are set in
268 * 16450 mode by default, so we have to enable the
269 * 16C950 'enhanced' mode so that we can use the
270 * deep FIFOs
271 */
272 irq_config = 0x5b;
1da177e4
LT		 273 /*
274 * enable/disable interrupts
275 */
6f441fe9 276 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 277 if (p == NULL)
278 return -ENOMEM;
279 writel(irq_config, p + 0x4c);
280
281 /*
282 * Read the register back to ensure that it took effect.
283 */
284 readl(p + 0x4c);
285 iounmap(p);
286
287 return 0;
288}
289
290static void __devexit pci_plx9050_exit(struct pci_dev *dev)
291{
292 u8 __iomem *p;
293
294 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
295 return;
296
297 /*
298 * disable interrupts
299 */
6f441fe9 300 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 301 if (p != NULL) {
302 writel(0, p + 0x4c);
303
304 /*
305 * Read the register back to ensure that it took effect.
306 */
307 readl(p + 0x4c);
308 iounmap(p);
309 }
310}
311
04bf7e74
WP		 312#define NI8420_INT_ENABLE_REG 0x38
313#define NI8420_INT_ENABLE_BIT 0x2000
314
315static void __devexit pci_ni8420_exit(struct pci_dev *dev)
316{
317 void __iomem *p;
318 unsigned long base, len;
319 unsigned int bar = 0;
320
321 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
322 moan_device("no memory in bar", dev);
323 return;
324 }
325
326 base = pci_resource_start(dev, bar);
327 len = pci_resource_len(dev, bar);
328 p = ioremap_nocache(base, len);
329 if (p == NULL)
330 return;
331
332 /* Disable the CPU Interrupt */
333 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
334 p + NI8420_INT_ENABLE_REG);
335 iounmap(p);
336}
337
338
46a0fac9
SB		 339/* MITE registers */
340#define MITE_IOWBSR1 0xc4
341#define MITE_IOWCR1 0xf4
342#define MITE_LCIMR1 0x08
343#define MITE_LCIMR2 0x10
344
345#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
346
347static void __devexit pci_ni8430_exit(struct pci_dev *dev)
348{
349 void __iomem *p;
350 unsigned long base, len;
351 unsigned int bar = 0;
352
353 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
354 moan_device("no memory in bar", dev);
355 return;
356 }
357
358 base = pci_resource_start(dev, bar);
359 len = pci_resource_len(dev, bar);
360 p = ioremap_nocache(base, len);
361 if (p == NULL)
362 return;
363
364 /* Disable the CPU Interrupt */
365 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
366 iounmap(p);
367}
368
1da177e4
LT		 369/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
370static int
975a1a7d 371sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 372 struct uart_port *port, int idx)
373{
374 unsigned int bar, offset = board->first_offset;
375
376 bar = 0;
377
378 if (idx < 4) {
379 /* first four channels map to 0, 0x100, 0x200, 0x300 */
380 offset += idx * board->uart_offset;
381 } else if (idx < 8) {
382 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
383 offset += idx * board->uart_offset + 0xC00;
384 } else /* we have only 8 ports on PMC-OCTALPRO */
385 return 1;
386
70db3d91 387 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 388}
389
390/*
391* This does initialization for PMC OCTALPRO cards:
392* maps the device memory, resets the UARTs (needed, bc
393* if the module is removed and inserted again, the card
394* is in the sleep mode) and enables global interrupt.
395*/
396
397/* global control register offset for SBS PMC-OctalPro */
398#define OCT_REG_CR_OFF 0x500
399
61a116ef 400static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 401{
402 u8 __iomem *p;
403
24ed3aba 404 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 405
406 if (p == NULL)
407 return -ENOMEM;
408 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 409 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 410 udelay(50);
5756ee99 411 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 412
413 /* Set bit-2 (INTENABLE) of Control Register */
414 writeb(0x4, p + OCT_REG_CR_OFF);
415 iounmap(p);
416
417 return 0;
418}
419
420/*
421 * Disables the global interrupt of PMC-OctalPro
422 */
423
424static void __devexit sbs_exit(struct pci_dev *dev)
425{
426 u8 __iomem *p;
427
24ed3aba 428 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 429 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
430 if (p != NULL)
1da177e4 431 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 432 iounmap(p);
433}
434
435/*
436 * SIIG serial cards have an PCI interface chip which also controls
437 * the UART clocking frequency. Each UART can be clocked independently
25985edc 438 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 439 * are stored in the EEPROM chip. It can cause problems because this
440 * version of serial driver doesn't support differently clocked UART's
441 * on single PCI card. To prevent this, initialization functions set
442 * high frequency clocking for all UART's on given card. It is safe (I
443 * hope) because it doesn't touch EEPROM settings to prevent conflicts
444 * with other OSes (like M$ DOS).
445 *
446 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 447 *
1da177e4
LT		 448 * There is two family of SIIG serial cards with different PCI
449 * interface chip and different configuration methods:
450 * - 10x cards have control registers in IO and/or memory space;
451 * - 20x cards have control registers in standard PCI configuration space.
452 *
67d74b87
RK		 453 * Note: all 10x cards have PCI device ids 0x10..
454 * all 20x cards have PCI device ids 0x20..
455 *
fbc0dc0d
AP		 456 * There are also Quartet Serial cards which use Oxford Semiconductor
457 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
458 *
1da177e4
LT		 459 * Note: some SIIG cards are probed by the parport_serial object.
460 */
461
462#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
463#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
464
465static int pci_siig10x_init(struct pci_dev *dev)
466{
467 u16 data;
468 void __iomem *p;
469
470 switch (dev->device & 0xfff8) {
471 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
472 data = 0xffdf;
473 break;
474 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
475 data = 0xf7ff;
476 break;
477 default: /* 1S1P, 4S */
478 data = 0xfffb;
479 break;
480 }
481
6f441fe9 482 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 483 if (p == NULL)
484 return -ENOMEM;
485
486 writew(readw(p + 0x28) & data, p + 0x28);
487 readw(p + 0x28);
488 iounmap(p);
489 return 0;
490}
491
492#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
493#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
494
495static int pci_siig20x_init(struct pci_dev *dev)
496{
497 u8 data;
498
499 /* Change clock frequency for the first UART. */
500 pci_read_config_byte(dev, 0x6f, &data);
501 pci_write_config_byte(dev, 0x6f, data & 0xef);
502
503 /* If this card has 2 UART, we have to do the same with second UART. */
504 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
505 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
506 pci_read_config_byte(dev, 0x73, &data);
507 pci_write_config_byte(dev, 0x73, data & 0xef);
508 }
509 return 0;
510}
511
67d74b87
RK		 512static int pci_siig_init(struct pci_dev *dev)
513{
514 unsigned int type = dev->device & 0xff00;
515
516 if (type == 0x1000)
517 return pci_siig10x_init(dev);
518 else if (type == 0x2000)
519 return pci_siig20x_init(dev);
520
521 moan_device("Unknown SIIG card", dev);
522 return -ENODEV;
523}
524
3ec9c594 525static int pci_siig_setup(struct serial_private *priv,
975a1a7d 526 const struct pciserial_board *board,
3ec9c594
AP		 527 struct uart_port *port, int idx)
528{
529 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
530
531 if (idx > 3) {
532 bar = 4;
533 offset = (idx - 4) * 8;
534 }
535
536 return setup_port(priv, port, bar, offset, 0);
537}
538
1da177e4
LT		 539/*
540 * Timedia has an explosion of boards, and to avoid the PCI table from
541 * growing *huge*, we use this function to collapse some 70 entries
542 * in the PCI table into one, for sanity's and compactness's sake.
543 */
e9422e09 544static const unsigned short timedia_single_port[] = {
1da177e4
LT		 545 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
546};
547
e9422e09 548static const unsigned short timedia_dual_port[] = {
1da177e4 549 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 550 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
551 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 552 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
553 0xD079, 0
554};
555
e9422e09 556static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 557 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
558 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 559 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
560 0xB157, 0
561};
562
e9422e09 563static const unsigned short timedia_eight_port[] = {
5756ee99 564 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 565 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
566};
567
cb3592be 568static const struct timedia_struct {
1da177e4 569 int num;
e9422e09 570 const unsigned short *ids;
1da177e4
LT		 571} timedia_data[] = {
572 { 1, timedia_single_port },
573 { 2, timedia_dual_port },
574 { 4, timedia_quad_port },
e9422e09 575 { 8, timedia_eight_port }
1da177e4
LT		 576};
577
b9b24558
FB		 578/*
579 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
580 * listing them individually, this driver merely grabs them all with
581 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
582 * and should be left free to be claimed by parport_serial instead.
583 */
584static int pci_timedia_probe(struct pci_dev *dev)
585{
586 /*
587 * Check the third digit of the subdevice ID
588 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
589 */
590 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
591 dev_info(&dev->dev,
592 "ignoring Timedia subdevice %04x for parport_serial\n",
593 dev->subsystem_device);
594 return -ENODEV;
595 }
596
597 return 0;
598}
599
61a116ef 600static int pci_timedia_init(struct pci_dev *dev)
1da177e4 601{
e9422e09 602 const unsigned short *ids;
1da177e4
LT		 603 int i, j;
604
e9422e09 605 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 606 ids = timedia_data[i].ids;
607 for (j = 0; ids[j]; j++)
608 if (dev->subsystem_device == ids[j])
609 return timedia_data[i].num;
610 }
611 return 0;
612}
613
614/*
615 * Timedia/SUNIX uses a mixture of BARs and offsets
616 * Ugh, this is ugly as all hell --- TYT
617 */
618static int
975a1a7d
RK		 619pci_timedia_setup(struct serial_private *priv,
620 const struct pciserial_board *board,
1da177e4
LT		 621 struct uart_port *port, int idx)
622{
623 unsigned int bar = 0, offset = board->first_offset;
624
625 switch (idx) {
626 case 0:
627 bar = 0;
628 break;
629 case 1:
630 offset = board->uart_offset;
631 bar = 0;
632 break;
633 case 2:
634 bar = 1;
635 break;
636 case 3:
637 offset = board->uart_offset;
c2cd6d3c 638 /* FALLTHROUGH */
1da177e4
LT		 639 case 4: /* BAR 2 */
640 case 5: /* BAR 3 */
641 case 6: /* BAR 4 */
642 case 7: /* BAR 5 */
643 bar = idx - 2;
644 }
645
70db3d91 646 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 647}
648
649/*
650 * Some Titan cards are also a little weird
651 */
652static int
70db3d91 653titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 654 const struct pciserial_board *board,
1da177e4
LT		 655 struct uart_port *port, int idx)
656{
657 unsigned int bar, offset = board->first_offset;
658
659 switch (idx) {
660 case 0:
661 bar = 1;
662 break;
663 case 1:
664 bar = 2;
665 break;
666 default:
667 bar = 4;
668 offset = (idx - 2) * board->uart_offset;
669 }
670
70db3d91 671 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 672}
673
61a116ef 674static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 675{
676 msleep(100);
677 return 0;
678}
679
04bf7e74
WP		 680static int pci_ni8420_init(struct pci_dev *dev)
681{
682 void __iomem *p;
683 unsigned long base, len;
684 unsigned int bar = 0;
685
686 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
687 moan_device("no memory in bar", dev);
688 return 0;
689 }
690
691 base = pci_resource_start(dev, bar);
692 len = pci_resource_len(dev, bar);
693 p = ioremap_nocache(base, len);
694 if (p == NULL)
695 return -ENOMEM;
696
697 /* Enable CPU Interrupt */
698 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
699 p + NI8420_INT_ENABLE_REG);
700
701 iounmap(p);
702 return 0;
703}
704
46a0fac9
SB		 705#define MITE_IOWBSR1_WSIZE 0xa
706#define MITE_IOWBSR1_WIN_OFFSET 0x800
707#define MITE_IOWBSR1_WENAB (1 << 7)
708#define MITE_LCIMR1_IO_IE_0 (1 << 24)
709#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
710#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
711
712static int pci_ni8430_init(struct pci_dev *dev)
713{
714 void __iomem *p;
715 unsigned long base, len;
716 u32 device_window;
717 unsigned int bar = 0;
718
719 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
720 moan_device("no memory in bar", dev);
721 return 0;
722 }
723
724 base = pci_resource_start(dev, bar);
725 len = pci_resource_len(dev, bar);
726 p = ioremap_nocache(base, len);
727 if (p == NULL)
728 return -ENOMEM;
729
730 /* Set device window address and size in BAR0 */
731 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
732 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
733 writel(device_window, p + MITE_IOWBSR1);
734
735 /* Set window access to go to RAMSEL IO address space */
736 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
737 p + MITE_IOWCR1);
738
739 /* Enable IO Bus Interrupt 0 */
740 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
741
742 /* Enable CPU Interrupt */
743 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
744
745 iounmap(p);
746 return 0;
747}
748
749/* UART Port Control Register */
750#define NI8430_PORTCON 0x0f
751#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
752
753static int
bf538fe4
AC		 754pci_ni8430_setup(struct serial_private *priv,
755 const struct pciserial_board *board,
46a0fac9
SB		 756 struct uart_port *port, int idx)
757{
758 void __iomem *p;
759 unsigned long base, len;
760 unsigned int bar, offset = board->first_offset;
761
762 if (idx >= board->num_ports)
763 return 1;
764
765 bar = FL_GET_BASE(board->flags);
766 offset += idx * board->uart_offset;
767
768 base = pci_resource_start(priv->dev, bar);
769 len = pci_resource_len(priv->dev, bar);
770 p = ioremap_nocache(base, len);
771
7c9d440e 772 /* enable the transceiver */
46a0fac9
SB		 773 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
774 p + offset + NI8430_PORTCON);
775
776 iounmap(p);
777
778 return setup_port(priv, port, bar, offset, board->reg_shift);
779}
780
7808edcd
NG		 781static int pci_netmos_9900_setup(struct serial_private *priv,
782 const struct pciserial_board *board,
783 struct uart_port *port, int idx)
784{
785 unsigned int bar;
786
787 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
788 /* netmos apparently orders BARs by datasheet layout, so serial
789 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
790 */
791 bar = 3 * idx;
792
793 return setup_port(priv, port, bar, 0, board->reg_shift);
794 } else {
795 return pci_default_setup(priv, board, port, idx);
796 }
797}
798
799/* the 99xx series comes with a range of device IDs and a variety
800 * of capabilities:
801 *
802 * 9900 has varying capabilities and can cascade to sub-controllers
803 * (cascading should be purely internal)
804 * 9904 is hardwired with 4 serial ports
805 * 9912 and 9922 are hardwired with 2 serial ports
806 */
807static int pci_netmos_9900_numports(struct pci_dev *dev)
808{
809 unsigned int c = dev->class;
810 unsigned int pi;
811 unsigned short sub_serports;
812
813 pi = (c & 0xff);
814
815 if (pi == 2) {
816 return 1;
817 } else if ((pi == 0) &&
818 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
819 /* two possibilities: 0x30ps encodes number of parallel and
820 * serial ports, or 0x1000 indicates *something*. This is not
821 * immediately obvious, since the 2s1p+4s configuration seems
822 * to offer all functionality on functions 0..2, while still
823 * advertising the same function 3 as the 4s+2s1p config.
824 */
825 sub_serports = dev->subsystem_device & 0xf;
826 if (sub_serports > 0) {
827 return sub_serports;
828 } else {
829 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
830 return 0;
831 }
832 }
833
834 moan_device("unknown NetMos/Mostech program interface", dev);
835 return 0;
836}
46a0fac9 837
61a116ef 838static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 839{
840 /* subdevice 0x00PS means <P> parallel, <S> serial */
841 unsigned int num_serial = dev->subsystem_device & 0xf;
842
ac6ec5b1
IS		 843 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
844 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 845 return 0;
7808edcd 846
25cf9bc1
JS		 847 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
848 dev->subsystem_device == 0x0299)
849 return 0;
850
7808edcd
NG		 851 switch (dev->device) { /* FALLTHROUGH on all */
852 case PCI_DEVICE_ID_NETMOS_9904:
853 case PCI_DEVICE_ID_NETMOS_9912:
854 case PCI_DEVICE_ID_NETMOS_9922:
855 case PCI_DEVICE_ID_NETMOS_9900:
856 num_serial = pci_netmos_9900_numports(dev);
857 break;
858
859 default:
860 if (num_serial == 0 ) {
861 moan_device("unknown NetMos/Mostech device", dev);
862 }
863 }
864
1da177e4
LT		 865 if (num_serial == 0)
866 return -ENODEV;
7808edcd 867
1da177e4
LT		 868 return num_serial;
869}
870
84f8c6fc 871/*
84f8c6fc
NV		 872 * These chips are available with optionally one parallel port and up to
873 * two serial ports. Unfortunately they all have the same product id.
874 *
875 * Basic configuration is done over a region of 32 I/O ports. The base
876 * ioport is called INTA or INTC, depending on docs/other drivers.
877 *
878 * The region of the 32 I/O ports is configured in POSIO0R...
879 */
880
881/* registers */
882#define ITE_887x_MISCR 0x9c
883#define ITE_887x_INTCBAR 0x78
884#define ITE_887x_UARTBAR 0x7c
885#define ITE_887x_PS0BAR 0x10
886#define ITE_887x_POSIO0 0x60
887
888/* I/O space size */
889#define ITE_887x_IOSIZE 32
890/* I/O space size (bits 26-24; 8 bytes = 011b) */
891#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
892/* I/O space size (bits 26-24; 32 bytes = 101b) */
893#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
894/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
895#define ITE_887x_POSIO_SPEED (3 << 29)
896/* enable IO_Space bit */
897#define ITE_887x_POSIO_ENABLE (1 << 31)
898
f79abb82 899static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 900{
901 /* inta_addr are the configuration addresses of the ITE */
902 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
903 0x200, 0x280, 0 };
904 int ret, i, type;
905 struct resource *iobase = NULL;
906 u32 miscr, uartbar, ioport;
907
908 /* search for the base-ioport */
909 i = 0;
910 while (inta_addr[i] && iobase == NULL) {
911 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
912 "ite887x");
913 if (iobase != NULL) {
914 /* write POSIO0R - speed | size | ioport */
915 pci_write_config_dword(dev, ITE_887x_POSIO0,
916 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
917 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
918 /* write INTCBAR - ioport */
5756ee99
AC		 919 pci_write_config_dword(dev, ITE_887x_INTCBAR,
920 inta_addr[i]);
84f8c6fc
NV		 921 ret = inb(inta_addr[i]);
922 if (ret != 0xff) {
923 /* ioport connected */
924 break;
925 }
926 release_region(iobase->start, ITE_887x_IOSIZE);
927 iobase = NULL;
928 }
929 i++;
930 }
931
932 if (!inta_addr[i]) {
933 printk(KERN_ERR "ite887x: could not find iobase\n");
934 return -ENODEV;
935 }
936
937 /* start of undocumented type checking (see parport_pc.c) */
938 type = inb(iobase->start + 0x18) & 0x0f;
939
940 switch (type) {
941 case 0x2: /* ITE8871 (1P) */
942 case 0xa: /* ITE8875 (1P) */
943 ret = 0;
944 break;
945 case 0xe: /* ITE8872 (2S1P) */
946 ret = 2;
947 break;
948 case 0x6: /* ITE8873 (1S) */
949 ret = 1;
950 break;
951 case 0x8: /* ITE8874 (2S) */
952 ret = 2;
953 break;
954 default:
955 moan_device("Unknown ITE887x", dev);
956 ret = -ENODEV;
957 }
958
959 /* configure all serial ports */
960 for (i = 0; i < ret; i++) {
961 /* read the I/O port from the device */
962 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
963 &ioport);
964 ioport &= 0x0000FF00; /* the actual base address */
965 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
966 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
967 ITE_887x_POSIO_IOSIZE_8 | ioport);
968
969 /* write the ioport to the UARTBAR */
970 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
971 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
972 uartbar |= (ioport << (16 * i)); /* set the ioport */
973 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
974
975 /* get current config */
976 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
977 /* disable interrupts (UARTx_Routing[3:0]) */
978 miscr &= ~(0xf << (12 - 4 * i));
979 /* activate the UART (UARTx_En) */
980 miscr |= 1 << (23 - i);
981 /* write new config with activated UART */
982 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
983 }
984
985 if (ret <= 0) {
986 /* the device has no UARTs if we get here */
987 release_region(iobase->start, ITE_887x_IOSIZE);
988 }
989
990 return ret;
991}
992
993static void __devexit pci_ite887x_exit(struct pci_dev *dev)
994{
995 u32 ioport;
996 /* the ioport is bit 0-15 in POSIO0R */
997 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
998 ioport &= 0xffff;
999 release_region(ioport, ITE_887x_IOSIZE);
1000}
1001
9f2a036a
RK		 1002/*
1003 * Oxford Semiconductor Inc.
1004 * Check that device is part of the Tornado range of devices, then determine
1005 * the number of ports available on the device.
1006 */
1007static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008{
1009 u8 __iomem *p;
1010 unsigned long deviceID;
1011 unsigned int number_uarts = 0;
1012
1013 /* OxSemi Tornado devices are all 0xCxxx */
1014 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015 (dev->device & 0xF000) != 0xC000)
1016 return 0;
1017
1018 p = pci_iomap(dev, 0, 5);
1019 if (p == NULL)
1020 return -ENOMEM;
1021
1022 deviceID = ioread32(p);
1023 /* Tornado device */
1024 if (deviceID == 0x07000200) {
1025 number_uarts = ioread8(p + 4);
1026 printk(KERN_DEBUG
1027 "%d ports detected on Oxford PCI Express device\n",
1028 number_uarts);
1029 }
1030 pci_iounmap(dev, p);
1031 return number_uarts;
1032}
1033
1da177e4 1034static int
975a1a7d
RK		 1035pci_default_setup(struct serial_private *priv,
1036 const struct pciserial_board *board,
1da177e4
LT		 1037 struct uart_port *port, int idx)
1038{
1039 unsigned int bar, offset = board->first_offset, maxnr;
1040
1041 bar = FL_GET_BASE(board->flags);
1042 if (board->flags & FL_BASE_BARS)
1043 bar += idx;
1044 else
1045 offset += idx * board->uart_offset;
1046
2427ddd8
GKH		 1047 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1048 (board->reg_shift + 3);
1da177e4
LT		 1049
1050 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1051 return 1;
5756ee99 1052
70db3d91 1053 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 1054}
1055
095e24b0
DB		 1056static int
1057ce4100_serial_setup(struct serial_private *priv,
1058 const struct pciserial_board *board,
1059 struct uart_port *port, int idx)
1060{
1061 int ret;
1062
1063 ret = setup_port(priv, port, 0, 0, board->reg_shift);
1064 port->iotype = UPIO_MEM32;
1065 port->type = PORT_XSCALE;
1066 port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1067 port->regshift = 2;
1068
1069 return ret;
1070}
1071
d9a0fbfd
AP		 1072static int
1073pci_omegapci_setup(struct serial_private *priv,
1798ca13 1074 const struct pciserial_board *board,
d9a0fbfd
AP		 1075 struct uart_port *port, int idx)
1076{
1077 return setup_port(priv, port, 2, idx * 8, 0);
1078}
1079
b6adea33
MCC		 1080static int skip_tx_en_setup(struct serial_private *priv,
1081 const struct pciserial_board *board,
1082 struct uart_port *port, int idx)
1083{
1084 port->flags |= UPF_NO_TXEN_TEST;
1085 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1086 "[%04x:%04x] subsystem [%04x:%04x]\n",
1087 priv->dev->vendor,
1088 priv->dev->device,
1089 priv->dev->subsystem_vendor,
1090 priv->dev->subsystem_device);
1091
1092 return pci_default_setup(priv, board, port, idx);
1093}
1094
eb7073db
TM		 1095static int pci_eg20t_init(struct pci_dev *dev)
1096{
1097#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1098 return -ENODEV;
1099#else
1100 return 0;
1101#endif
1102}
1103
06315348
SH		 1104static int
1105pci_xr17c154_setup(struct serial_private *priv,
1106 const struct pciserial_board *board,
1107 struct uart_port *port, int idx)
1108{
1109 port->flags |= UPF_EXAR_EFR;
1110 return pci_default_setup(priv, board, port, idx);
1111}
1112
49b532f9 1113/* This should be in linux/pci_ids.h */
1da177e4
LT		 1114#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1115#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1116#define PCI_DEVICE_ID_OCTPRO 0x0001
1117#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1118#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1119#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1120#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
78d70d48 1121#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 1122#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 1123#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
66169ad1
YY		 1124#define PCI_DEVICE_ID_TITAN_200I 0x8028
1125#define PCI_DEVICE_ID_TITAN_400I 0x8048
1126#define PCI_DEVICE_ID_TITAN_800I 0x8088
1127#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1128#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1129#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1130#define PCI_DEVICE_ID_TITAN_100E 0xA010
1131#define PCI_DEVICE_ID_TITAN_200E 0xA012
1132#define PCI_DEVICE_ID_TITAN_400E 0xA013
1133#define PCI_DEVICE_ID_TITAN_800E 0xA014
1134#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1135#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1e9deb11
YY		 1136#define PCI_DEVICE_ID_TITAN_400V3 0xA310
1137#define PCI_DEVICE_ID_TITAN_410V3 0xA312
1138#define PCI_DEVICE_ID_TITAN_800V3 0xA314
1139#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
e847003f 1140#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 1141#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
d9a0fbfd 1142#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1da177e4 1143
b76c5a07
CB		 1144/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1145#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1146
1da177e4
LT		 1147/*
1148 * Master list of serial port init/setup/exit quirks.
1149 * This does not describe the general nature of the port.
1150 * (ie, baud base, number and location of ports, etc)
1151 *
1152 * This list is ordered alphabetically by vendor then device.
1153 * Specific entries must come before more generic entries.
1154 */
7a63ce5a 1155static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 1156 /*
1157 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1158 */
1159 {
1160 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1161 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1162 .subvendor = PCI_ANY_ID,
1163 .subdevice = PCI_ANY_ID,
1164 .setup = addidata_apci7800_setup,
1165 },
1da177e4 1166 /*
61a116ef 1167 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 1168 * It is not clear whether this applies to all products.
1169 */
1170 {
1171 .vendor = PCI_VENDOR_ID_AFAVLAB,
1172 .device = PCI_ANY_ID,
1173 .subvendor = PCI_ANY_ID,
1174 .subdevice = PCI_ANY_ID,
1175 .setup = afavlab_setup,
1176 },
1177 /*
1178 * HP Diva
1179 */
1180 {
1181 .vendor = PCI_VENDOR_ID_HP,
1182 .device = PCI_DEVICE_ID_HP_DIVA,
1183 .subvendor = PCI_ANY_ID,
1184 .subdevice = PCI_ANY_ID,
1185 .init = pci_hp_diva_init,
1186 .setup = pci_hp_diva_setup,
1187 },
1188 /*
1189 * Intel
1190 */
1191 {
1192 .vendor = PCI_VENDOR_ID_INTEL,
1193 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1194 .subvendor = 0xe4bf,
1195 .subdevice = PCI_ANY_ID,
1196 .init = pci_inteli960ni_init,
1197 .setup = pci_default_setup,
1198 },
b6adea33
MCC		 1199 {
1200 .vendor = PCI_VENDOR_ID_INTEL,
1201 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1202 .subvendor = PCI_ANY_ID,
1203 .subdevice = PCI_ANY_ID,
1204 .setup = skip_tx_en_setup,
1205 },
1206 {
1207 .vendor = PCI_VENDOR_ID_INTEL,
1208 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1209 .subvendor = PCI_ANY_ID,
1210 .subdevice = PCI_ANY_ID,
1211 .setup = skip_tx_en_setup,
1212 },
1213 {
1214 .vendor = PCI_VENDOR_ID_INTEL,
1215 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1216 .subvendor = PCI_ANY_ID,
1217 .subdevice = PCI_ANY_ID,
1218 .setup = skip_tx_en_setup,
1219 },
095e24b0
DB		 1220 {
1221 .vendor = PCI_VENDOR_ID_INTEL,
1222 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1223 .subvendor = PCI_ANY_ID,
1224 .subdevice = PCI_ANY_ID,
1225 .setup = ce4100_serial_setup,
1226 },
84f8c6fc
NV		 1227 /*
1228 * ITE
1229 */
1230 {
1231 .vendor = PCI_VENDOR_ID_ITE,
1232 .device = PCI_DEVICE_ID_ITE_8872,
1233 .subvendor = PCI_ANY_ID,
1234 .subdevice = PCI_ANY_ID,
1235 .init = pci_ite887x_init,
1236 .setup = pci_default_setup,
1237 .exit = __devexit_p(pci_ite887x_exit),
1238 },
46a0fac9
SB		 1239 /*
1240 * National Instruments
1241 */
04bf7e74
WP		 1242 {
1243 .vendor = PCI_VENDOR_ID_NI,
1244 .device = PCI_DEVICE_ID_NI_PCI23216,
1245 .subvendor = PCI_ANY_ID,
1246 .subdevice = PCI_ANY_ID,
1247 .init = pci_ni8420_init,
1248 .setup = pci_default_setup,
1249 .exit = __devexit_p(pci_ni8420_exit),
1250 },
1251 {
1252 .vendor = PCI_VENDOR_ID_NI,
1253 .device = PCI_DEVICE_ID_NI_PCI2328,
1254 .subvendor = PCI_ANY_ID,
1255 .subdevice = PCI_ANY_ID,
1256 .init = pci_ni8420_init,
1257 .setup = pci_default_setup,
1258 .exit = __devexit_p(pci_ni8420_exit),
1259 },
1260 {
1261 .vendor = PCI_VENDOR_ID_NI,
1262 .device = PCI_DEVICE_ID_NI_PCI2324,
1263 .subvendor = PCI_ANY_ID,
1264 .subdevice = PCI_ANY_ID,
1265 .init = pci_ni8420_init,
1266 .setup = pci_default_setup,
1267 .exit = __devexit_p(pci_ni8420_exit),
1268 },
1269 {
1270 .vendor = PCI_VENDOR_ID_NI,
1271 .device = PCI_DEVICE_ID_NI_PCI2322,
1272 .subvendor = PCI_ANY_ID,
1273 .subdevice = PCI_ANY_ID,
1274 .init = pci_ni8420_init,
1275 .setup = pci_default_setup,
1276 .exit = __devexit_p(pci_ni8420_exit),
1277 },
1278 {
1279 .vendor = PCI_VENDOR_ID_NI,
1280 .device = PCI_DEVICE_ID_NI_PCI2324I,
1281 .subvendor = PCI_ANY_ID,
1282 .subdevice = PCI_ANY_ID,
1283 .init = pci_ni8420_init,
1284 .setup = pci_default_setup,
1285 .exit = __devexit_p(pci_ni8420_exit),
1286 },
1287 {
1288 .vendor = PCI_VENDOR_ID_NI,
1289 .device = PCI_DEVICE_ID_NI_PCI2322I,
1290 .subvendor = PCI_ANY_ID,
1291 .subdevice = PCI_ANY_ID,
1292 .init = pci_ni8420_init,
1293 .setup = pci_default_setup,
1294 .exit = __devexit_p(pci_ni8420_exit),
1295 },
1296 {
1297 .vendor = PCI_VENDOR_ID_NI,
1298 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1299 .subvendor = PCI_ANY_ID,
1300 .subdevice = PCI_ANY_ID,
1301 .init = pci_ni8420_init,
1302 .setup = pci_default_setup,
1303 .exit = __devexit_p(pci_ni8420_exit),
1304 },
1305 {
1306 .vendor = PCI_VENDOR_ID_NI,
1307 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1308 .subvendor = PCI_ANY_ID,
1309 .subdevice = PCI_ANY_ID,
1310 .init = pci_ni8420_init,
1311 .setup = pci_default_setup,
1312 .exit = __devexit_p(pci_ni8420_exit),
1313 },
1314 {
1315 .vendor = PCI_VENDOR_ID_NI,
1316 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1317 .subvendor = PCI_ANY_ID,
1318 .subdevice = PCI_ANY_ID,
1319 .init = pci_ni8420_init,
1320 .setup = pci_default_setup,
1321 .exit = __devexit_p(pci_ni8420_exit),
1322 },
1323 {
1324 .vendor = PCI_VENDOR_ID_NI,
1325 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1326 .subvendor = PCI_ANY_ID,
1327 .subdevice = PCI_ANY_ID,
1328 .init = pci_ni8420_init,
1329 .setup = pci_default_setup,
1330 .exit = __devexit_p(pci_ni8420_exit),
1331 },
1332 {
1333 .vendor = PCI_VENDOR_ID_NI,
1334 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1335 .subvendor = PCI_ANY_ID,
1336 .subdevice = PCI_ANY_ID,
1337 .init = pci_ni8420_init,
1338 .setup = pci_default_setup,
1339 .exit = __devexit_p(pci_ni8420_exit),
1340 },
1341 {
1342 .vendor = PCI_VENDOR_ID_NI,
1343 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1344 .subvendor = PCI_ANY_ID,
1345 .subdevice = PCI_ANY_ID,
1346 .init = pci_ni8420_init,
1347 .setup = pci_default_setup,
1348 .exit = __devexit_p(pci_ni8420_exit),
1349 },
46a0fac9
SB		 1350 {
1351 .vendor = PCI_VENDOR_ID_NI,
1352 .device = PCI_ANY_ID,
1353 .subvendor = PCI_ANY_ID,
1354 .subdevice = PCI_ANY_ID,
1355 .init = pci_ni8430_init,
1356 .setup = pci_ni8430_setup,
1357 .exit = __devexit_p(pci_ni8430_exit),
1358 },
1da177e4
LT		 1359 /*
1360 * Panacom
1361 */
1362 {
1363 .vendor = PCI_VENDOR_ID_PANACOM,
1364 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1365 .subvendor = PCI_ANY_ID,
1366 .subdevice = PCI_ANY_ID,
1367 .init = pci_plx9050_init,
1368 .setup = pci_default_setup,
1369 .exit = __devexit_p(pci_plx9050_exit),
5756ee99 1370 },
1da177e4
LT		 1371 {
1372 .vendor = PCI_VENDOR_ID_PANACOM,
1373 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1374 .subvendor = PCI_ANY_ID,
1375 .subdevice = PCI_ANY_ID,
1376 .init = pci_plx9050_init,
1377 .setup = pci_default_setup,
1378 .exit = __devexit_p(pci_plx9050_exit),
1379 },
1380 /*
1381 * PLX
1382 */
48212008
TH		 1383 {
1384 .vendor = PCI_VENDOR_ID_PLX,
1385 .device = PCI_DEVICE_ID_PLX_9030,
1386 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1387 .subdevice = PCI_ANY_ID,
1388 .setup = pci_default_setup,
1389 },
add7b58e
BH		 1390 {
1391 .vendor = PCI_VENDOR_ID_PLX,
1392 .device = PCI_DEVICE_ID_PLX_9050,
1393 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1394 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1395 .init = pci_plx9050_init,
1396 .setup = pci_default_setup,
1397 .exit = __devexit_p(pci_plx9050_exit),
1398 },
1da177e4
LT		 1399 {
1400 .vendor = PCI_VENDOR_ID_PLX,
1401 .device = PCI_DEVICE_ID_PLX_9050,
1402 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1403 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1404 .init = pci_plx9050_init,
1405 .setup = pci_default_setup,
1406 .exit = __devexit_p(pci_plx9050_exit),
1407 },
b76c5a07
CB		 1408 {
1409 .vendor = PCI_VENDOR_ID_PLX,
1410 .device = PCI_DEVICE_ID_PLX_9050,
1411 .subvendor = PCI_VENDOR_ID_PLX,
1412 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1413 .init = pci_plx9050_init,
1414 .setup = pci_default_setup,
1415 .exit = __devexit_p(pci_plx9050_exit),
1416 },
1da177e4
LT		 1417 {
1418 .vendor = PCI_VENDOR_ID_PLX,
1419 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1420 .subvendor = PCI_VENDOR_ID_PLX,
1421 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1422 .init = pci_plx9050_init,
1423 .setup = pci_default_setup,
1424 .exit = __devexit_p(pci_plx9050_exit),
1425 },
1426 /*
1427 * SBS Technologies, Inc., PMC-OCTALPRO 232
1428 */
1429 {
1430 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1431 .device = PCI_DEVICE_ID_OCTPRO,
1432 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1433 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1434 .init = sbs_init,
1435 .setup = sbs_setup,
1436 .exit = __devexit_p(sbs_exit),
1437 },
1438 /*
1439 * SBS Technologies, Inc., PMC-OCTALPRO 422
1440 */
1441 {
1442 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1443 .device = PCI_DEVICE_ID_OCTPRO,
1444 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1445 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1446 .init = sbs_init,
1447 .setup = sbs_setup,
1448 .exit = __devexit_p(sbs_exit),
1449 },
1450 /*
1451 * SBS Technologies, Inc., P-Octal 232
1452 */
1453 {
1454 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1455 .device = PCI_DEVICE_ID_OCTPRO,
1456 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1457 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1458 .init = sbs_init,
1459 .setup = sbs_setup,
1460 .exit = __devexit_p(sbs_exit),
1461 },
1462 /*
1463 * SBS Technologies, Inc., P-Octal 422
1464 */
1465 {
1466 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1467 .device = PCI_DEVICE_ID_OCTPRO,
1468 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1469 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1470 .init = sbs_init,
1471 .setup = sbs_setup,
1472 .exit = __devexit_p(sbs_exit),
1473 },
1da177e4 1474 /*
61a116ef 1475 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 1476 */
1477 {
1478 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 1479 .device = PCI_ANY_ID,
1da177e4
LT		 1480 .subvendor = PCI_ANY_ID,
1481 .subdevice = PCI_ANY_ID,
67d74b87 1482 .init = pci_siig_init,
3ec9c594 1483 .setup = pci_siig_setup,
1da177e4
LT		 1484 },
1485 /*
1486 * Titan cards
1487 */
1488 {
1489 .vendor = PCI_VENDOR_ID_TITAN,
1490 .device = PCI_DEVICE_ID_TITAN_400L,
1491 .subvendor = PCI_ANY_ID,
1492 .subdevice = PCI_ANY_ID,
1493 .setup = titan_400l_800l_setup,
1494 },
1495 {
1496 .vendor = PCI_VENDOR_ID_TITAN,
1497 .device = PCI_DEVICE_ID_TITAN_800L,
1498 .subvendor = PCI_ANY_ID,
1499 .subdevice = PCI_ANY_ID,
1500 .setup = titan_400l_800l_setup,
1501 },
1502 /*
1503 * Timedia cards
1504 */
1505 {
1506 .vendor = PCI_VENDOR_ID_TIMEDIA,
1507 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1508 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1509 .subdevice = PCI_ANY_ID,
b9b24558 1510 .probe = pci_timedia_probe,
1da177e4
LT		 1511 .init = pci_timedia_init,
1512 .setup = pci_timedia_setup,
1513 },
1514 {
1515 .vendor = PCI_VENDOR_ID_TIMEDIA,
1516 .device = PCI_ANY_ID,
1517 .subvendor = PCI_ANY_ID,
1518 .subdevice = PCI_ANY_ID,
1519 .setup = pci_timedia_setup,
1520 },
06315348
SH		 1521 /*
1522 * Exar cards
1523 */
1524 {
1525 .vendor = PCI_VENDOR_ID_EXAR,
1526 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1527 .subvendor = PCI_ANY_ID,
1528 .subdevice = PCI_ANY_ID,
1529 .setup = pci_xr17c154_setup,
1530 },
1531 {
1532 .vendor = PCI_VENDOR_ID_EXAR,
1533 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1534 .subvendor = PCI_ANY_ID,
1535 .subdevice = PCI_ANY_ID,
1536 .setup = pci_xr17c154_setup,
1537 },
1538 {
1539 .vendor = PCI_VENDOR_ID_EXAR,
1540 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1541 .subvendor = PCI_ANY_ID,
1542 .subdevice = PCI_ANY_ID,
1543 .setup = pci_xr17c154_setup,
1544 },
1da177e4
LT		 1545 /*
1546 * Xircom cards
1547 */
1548 {
1549 .vendor = PCI_VENDOR_ID_XIRCOM,
1550 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1551 .subvendor = PCI_ANY_ID,
1552 .subdevice = PCI_ANY_ID,
1553 .init = pci_xircom_init,
1554 .setup = pci_default_setup,
1555 },
1556 /*
61a116ef 1557 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 1558 */
1559 {
1560 .vendor = PCI_VENDOR_ID_NETMOS,
1561 .device = PCI_ANY_ID,
1562 .subvendor = PCI_ANY_ID,
1563 .subdevice = PCI_ANY_ID,
1564 .init = pci_netmos_init,
7808edcd 1565 .setup = pci_netmos_9900_setup,
1da177e4 1566 },
9f2a036a 1567 /*
aa273ae5 1568 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 1569 */
1570 {
1571 .vendor = PCI_VENDOR_ID_OXSEMI,
1572 .device = PCI_ANY_ID,
1573 .subvendor = PCI_ANY_ID,
1574 .subdevice = PCI_ANY_ID,
1575 .init = pci_oxsemi_tornado_init,
1576 .setup = pci_default_setup,
1577 },
1578 {
1579 .vendor = PCI_VENDOR_ID_MAINPINE,
1580 .device = PCI_ANY_ID,
1581 .subvendor = PCI_ANY_ID,
1582 .subdevice = PCI_ANY_ID,
1583 .init = pci_oxsemi_tornado_init,
1584 .setup = pci_default_setup,
1585 },
aa273ae5
SK		 1586 {
1587 .vendor = PCI_VENDOR_ID_DIGI,
1588 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1589 .subvendor = PCI_SUBVENDOR_ID_IBM,
1590 .subdevice = PCI_ANY_ID,
1591 .init = pci_oxsemi_tornado_init,
1592 .setup = pci_default_setup,
1593 },
eb7073db
TM		 1594 {
1595 .vendor = PCI_VENDOR_ID_INTEL,
1596 .device = 0x8811,
1597 .init = pci_eg20t_init,
64d91cfa 1598 .setup = pci_default_setup,
eb7073db
TM		 1599 },
1600 {
1601 .vendor = PCI_VENDOR_ID_INTEL,
1602 .device = 0x8812,
1603 .init = pci_eg20t_init,
64d91cfa 1604 .setup = pci_default_setup,
eb7073db
TM		 1605 },
1606 {
1607 .vendor = PCI_VENDOR_ID_INTEL,
1608 .device = 0x8813,
1609 .init = pci_eg20t_init,
64d91cfa 1610 .setup = pci_default_setup,
eb7073db
TM		 1611 },
1612 {
1613 .vendor = PCI_VENDOR_ID_INTEL,
1614 .device = 0x8814,
1615 .init = pci_eg20t_init,
64d91cfa 1616 .setup = pci_default_setup,
eb7073db
TM		 1617 },
1618 {
1619 .vendor = 0x10DB,
1620 .device = 0x8027,
1621 .init = pci_eg20t_init,
64d91cfa 1622 .setup = pci_default_setup,
eb7073db
TM		 1623 },
1624 {
1625 .vendor = 0x10DB,
1626 .device = 0x8028,
1627 .init = pci_eg20t_init,
64d91cfa 1628 .setup = pci_default_setup,
eb7073db
TM		 1629 },
1630 {
1631 .vendor = 0x10DB,
1632 .device = 0x8029,
1633 .init = pci_eg20t_init,
64d91cfa 1634 .setup = pci_default_setup,
eb7073db
TM		 1635 },
1636 {
1637 .vendor = 0x10DB,
1638 .device = 0x800C,
1639 .init = pci_eg20t_init,
64d91cfa 1640 .setup = pci_default_setup,
eb7073db
TM		 1641 },
1642 {
1643 .vendor = 0x10DB,
1644 .device = 0x800D,
1645 .init = pci_eg20t_init,
64d91cfa 1646 .setup = pci_default_setup,
eb7073db 1647 },
d9a0fbfd
AP		 1648 /*
1649 * Cronyx Omega PCI (PLX-chip based)
1650 */
1651 {
1652 .vendor = PCI_VENDOR_ID_PLX,
1653 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1654 .subvendor = PCI_ANY_ID,
1655 .subdevice = PCI_ANY_ID,
1656 .setup = pci_omegapci_setup,
1657 },
1da177e4
LT		 1658 /*
1659 * Default "match everything" terminator entry
1660 */
1661 {
1662 .vendor = PCI_ANY_ID,
1663 .device = PCI_ANY_ID,
1664 .subvendor = PCI_ANY_ID,
1665 .subdevice = PCI_ANY_ID,
1666 .setup = pci_default_setup,
1667 }
1668};
1669
1670static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1671{
1672 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1673}
1674
1675static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1676{
1677 struct pci_serial_quirk *quirk;
1678
1679 for (quirk = pci_serial_quirks; ; quirk++)
1680 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1681 quirk_id_matches(quirk->device, dev->device) &&
1682 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1683 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 1684 break;
1da177e4
LT		 1685 return quirk;
1686}
1687
dd68e88c 1688static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 1689 const struct pciserial_board *board)
1da177e4
LT		 1690{
1691 if (board->flags & FL_NOIRQ)
1692 return 0;
1693 else
1694 return dev->irq;
1695}
1696
1697/*
1698 * This is the configuration table for all of the PCI serial boards
1699 * which we support. It is directly indexed by the pci_board_num_t enum
1700 * value, which is encoded in the pci_device_id PCI probe table's
1701 * driver_data member.
1702 *
1703 * The makeup of these names are:
26e92861 1704 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 1705 *
26e92861
GH		 1706 * bn = PCI BAR number
1707 * bt = Index using PCI BARs
1708 * n = number of serial ports
1709 * baud = baud rate
1710 * offsetinhex = offset for each sequential port (in hex)
1da177e4 1711 *
26e92861 1712 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 1713 *
1da177e4
LT		 1714 * Please note: in theory if n = 1, _bt infix should make no difference.
1715 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1716 */
1717enum pci_board_num_t {
1718 pbn_default = 0,
1719
1720 pbn_b0_1_115200,
1721 pbn_b0_2_115200,
1722 pbn_b0_4_115200,
1723 pbn_b0_5_115200,
bf0df636 1724 pbn_b0_8_115200,
1da177e4
LT		 1725
1726 pbn_b0_1_921600,
1727 pbn_b0_2_921600,
1728 pbn_b0_4_921600,
1729
db1de159
DR		 1730 pbn_b0_2_1130000,
1731
fbc0dc0d
AP		 1732 pbn_b0_4_1152000,
1733
26e92861
GH		 1734 pbn_b0_2_1843200,
1735 pbn_b0_4_1843200,
1736
1737 pbn_b0_2_1843200_200,
1738 pbn_b0_4_1843200_200,
1739 pbn_b0_8_1843200_200,
1740
7106b4e3
LH		 1741 pbn_b0_1_4000000,
1742
1da177e4
LT		 1743 pbn_b0_bt_1_115200,
1744 pbn_b0_bt_2_115200,
ac6ec5b1 1745 pbn_b0_bt_4_115200,
1da177e4
LT		 1746 pbn_b0_bt_8_115200,
1747
1748 pbn_b0_bt_1_460800,
1749 pbn_b0_bt_2_460800,
1750 pbn_b0_bt_4_460800,
1751
1752 pbn_b0_bt_1_921600,
1753 pbn_b0_bt_2_921600,
1754 pbn_b0_bt_4_921600,
1755 pbn_b0_bt_8_921600,
1756
1757 pbn_b1_1_115200,
1758 pbn_b1_2_115200,
1759 pbn_b1_4_115200,
1760 pbn_b1_8_115200,
04bf7e74 1761 pbn_b1_16_115200,
1da177e4
LT		 1762
1763 pbn_b1_1_921600,
1764 pbn_b1_2_921600,
1765 pbn_b1_4_921600,
1766 pbn_b1_8_921600,
1767
26e92861
GH		 1768 pbn_b1_2_1250000,
1769
84f8c6fc 1770 pbn_b1_bt_1_115200,
04bf7e74
WP		 1771 pbn_b1_bt_2_115200,
1772 pbn_b1_bt_4_115200,
1773
1da177e4
LT		 1774 pbn_b1_bt_2_921600,
1775
1776 pbn_b1_1_1382400,
1777 pbn_b1_2_1382400,
1778 pbn_b1_4_1382400,
1779 pbn_b1_8_1382400,
1780
1781 pbn_b2_1_115200,
737c1756 1782 pbn_b2_2_115200,
a9cccd34 1783 pbn_b2_4_115200,
1da177e4
LT		 1784 pbn_b2_8_115200,
1785
1786 pbn_b2_1_460800,
1787 pbn_b2_4_460800,
1788 pbn_b2_8_460800,
1789 pbn_b2_16_460800,
1790
1791 pbn_b2_1_921600,
1792 pbn_b2_4_921600,
1793 pbn_b2_8_921600,
1794
e847003f
LB		 1795 pbn_b2_8_1152000,
1796
1da177e4
LT		 1797 pbn_b2_bt_1_115200,
1798 pbn_b2_bt_2_115200,
1799 pbn_b2_bt_4_115200,
1800
1801 pbn_b2_bt_2_921600,
1802 pbn_b2_bt_4_921600,
1803
d9004eb4 1804 pbn_b3_2_115200,
1da177e4
LT		 1805 pbn_b3_4_115200,
1806 pbn_b3_8_115200,
1807
66169ad1
YY		 1808 pbn_b4_bt_2_921600,
1809 pbn_b4_bt_4_921600,
1810 pbn_b4_bt_8_921600,
1811
1da177e4
LT		 1812 /*
1813 * Board-specific versions.
1814 */
1815 pbn_panacom,
1816 pbn_panacom2,
1817 pbn_panacom4,
add7b58e 1818 pbn_exsys_4055,
1da177e4
LT		 1819 pbn_plx_romulus,
1820 pbn_oxsemi,
7106b4e3
LH		 1821 pbn_oxsemi_1_4000000,
1822 pbn_oxsemi_2_4000000,
1823 pbn_oxsemi_4_4000000,
1824 pbn_oxsemi_8_4000000,
1da177e4
LT		 1825 pbn_intel_i960,
1826 pbn_sgi_ioc3,
1da177e4
LT		 1827 pbn_computone_4,
1828 pbn_computone_6,
1829 pbn_computone_8,
1830 pbn_sbsxrsio,
1831 pbn_exar_XR17C152,
1832 pbn_exar_XR17C154,
1833 pbn_exar_XR17C158,
c68d2b15 1834 pbn_exar_ibm_saturn,
aa798505 1835 pbn_pasemi_1682M,
46a0fac9
SB		 1836 pbn_ni8430_2,
1837 pbn_ni8430_4,
1838 pbn_ni8430_8,
1839 pbn_ni8430_16,
1b62cbf2
KJ		 1840 pbn_ADDIDATA_PCIe_1_3906250,
1841 pbn_ADDIDATA_PCIe_2_3906250,
1842 pbn_ADDIDATA_PCIe_4_3906250,
1843 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 1844 pbn_ce4100_1_115200,
d9a0fbfd 1845 pbn_omegapci,
7808edcd 1846 pbn_NETMOS9900_2s_115200,
1da177e4
LT		 1847};
1848
1849/*
1850 * uart_offset - the space between channels
1851 * reg_shift - describes how the UART registers are mapped
1852 * to PCI memory by the card.
1853 * For example IER register on SBS, Inc. PMC-OctPro is located at
1854 * offset 0x10 from the UART base, while UART_IER is defined as 1
1855 * in include/linux/serial_reg.h,
1856 * see first lines of serial_in() and serial_out() in 8250.c
1857*/
1858
1c7c1fe5 1859static struct pciserial_board pci_boards[] __devinitdata = {
1da177e4
LT		 1860 [pbn_default] = {
1861 .flags = FL_BASE0,
1862 .num_ports = 1,
1863 .base_baud = 115200,
1864 .uart_offset = 8,
1865 },
1866 [pbn_b0_1_115200] = {
1867 .flags = FL_BASE0,
1868 .num_ports = 1,
1869 .base_baud = 115200,
1870 .uart_offset = 8,
1871 },
1872 [pbn_b0_2_115200] = {
1873 .flags = FL_BASE0,
1874 .num_ports = 2,
1875 .base_baud = 115200,
1876 .uart_offset = 8,
1877 },
1878 [pbn_b0_4_115200] = {
1879 .flags = FL_BASE0,
1880 .num_ports = 4,
1881 .base_baud = 115200,
1882 .uart_offset = 8,
1883 },
1884 [pbn_b0_5_115200] = {
1885 .flags = FL_BASE0,
1886 .num_ports = 5,
1887 .base_baud = 115200,
1888 .uart_offset = 8,
1889 },
bf0df636
AC		 1890 [pbn_b0_8_115200] = {
1891 .flags = FL_BASE0,
1892 .num_ports = 8,
1893 .base_baud = 115200,
1894 .uart_offset = 8,
1895 },
1da177e4
LT		 1896 [pbn_b0_1_921600] = {
1897 .flags = FL_BASE0,
1898 .num_ports = 1,
1899 .base_baud = 921600,
1900 .uart_offset = 8,
1901 },
1902 [pbn_b0_2_921600] = {
1903 .flags = FL_BASE0,
1904 .num_ports = 2,
1905 .base_baud = 921600,
1906 .uart_offset = 8,
1907 },
1908 [pbn_b0_4_921600] = {
1909 .flags = FL_BASE0,
1910 .num_ports = 4,
1911 .base_baud = 921600,
1912 .uart_offset = 8,
1913 },
db1de159
DR		 1914
1915 [pbn_b0_2_1130000] = {
1916 .flags = FL_BASE0,
1917 .num_ports = 2,
1918 .base_baud = 1130000,
1919 .uart_offset = 8,
1920 },
1921
fbc0dc0d
AP		 1922 [pbn_b0_4_1152000] = {
1923 .flags = FL_BASE0,
1924 .num_ports = 4,
1925 .base_baud = 1152000,
1926 .uart_offset = 8,
1927 },
1da177e4 1928
26e92861
GH		 1929 [pbn_b0_2_1843200] = {
1930 .flags = FL_BASE0,
1931 .num_ports = 2,
1932 .base_baud = 1843200,
1933 .uart_offset = 8,
1934 },
1935 [pbn_b0_4_1843200] = {
1936 .flags = FL_BASE0,
1937 .num_ports = 4,
1938 .base_baud = 1843200,
1939 .uart_offset = 8,
1940 },
1941
1942 [pbn_b0_2_1843200_200] = {
1943 .flags = FL_BASE0,
1944 .num_ports = 2,
1945 .base_baud = 1843200,
1946 .uart_offset = 0x200,
1947 },
1948 [pbn_b0_4_1843200_200] = {
1949 .flags = FL_BASE0,
1950 .num_ports = 4,
1951 .base_baud = 1843200,
1952 .uart_offset = 0x200,
1953 },
1954 [pbn_b0_8_1843200_200] = {
1955 .flags = FL_BASE0,
1956 .num_ports = 8,
1957 .base_baud = 1843200,
1958 .uart_offset = 0x200,
1959 },
7106b4e3
LH		 1960 [pbn_b0_1_4000000] = {
1961 .flags = FL_BASE0,
1962 .num_ports = 1,
1963 .base_baud = 4000000,
1964 .uart_offset = 8,
1965 },
26e92861 1966
1da177e4
LT		 1967 [pbn_b0_bt_1_115200] = {
1968 .flags = FL_BASE0|FL_BASE_BARS,
1969 .num_ports = 1,
1970 .base_baud = 115200,
1971 .uart_offset = 8,
1972 },
1973 [pbn_b0_bt_2_115200] = {
1974 .flags = FL_BASE0|FL_BASE_BARS,
1975 .num_ports = 2,
1976 .base_baud = 115200,
1977 .uart_offset = 8,
1978 },
ac6ec5b1
IS		 1979 [pbn_b0_bt_4_115200] = {
1980 .flags = FL_BASE0|FL_BASE_BARS,
1981 .num_ports = 4,
1982 .base_baud = 115200,
1983 .uart_offset = 8,
1984 },
1da177e4
LT		 1985 [pbn_b0_bt_8_115200] = {
1986 .flags = FL_BASE0|FL_BASE_BARS,
1987 .num_ports = 8,
1988 .base_baud = 115200,
1989 .uart_offset = 8,
1990 },
1991
1992 [pbn_b0_bt_1_460800] = {
1993 .flags = FL_BASE0|FL_BASE_BARS,
1994 .num_ports = 1,
1995 .base_baud = 460800,
1996 .uart_offset = 8,
1997 },
1998 [pbn_b0_bt_2_460800] = {
1999 .flags = FL_BASE0|FL_BASE_BARS,
2000 .num_ports = 2,
2001 .base_baud = 460800,
2002 .uart_offset = 8,
2003 },
2004 [pbn_b0_bt_4_460800] = {
2005 .flags = FL_BASE0|FL_BASE_BARS,
2006 .num_ports = 4,
2007 .base_baud = 460800,
2008 .uart_offset = 8,
2009 },
2010
2011 [pbn_b0_bt_1_921600] = {
2012 .flags = FL_BASE0|FL_BASE_BARS,
2013 .num_ports = 1,
2014 .base_baud = 921600,
2015 .uart_offset = 8,
2016 },
2017 [pbn_b0_bt_2_921600] = {
2018 .flags = FL_BASE0|FL_BASE_BARS,
2019 .num_ports = 2,
2020 .base_baud = 921600,
2021 .uart_offset = 8,
2022 },
2023 [pbn_b0_bt_4_921600] = {
2024 .flags = FL_BASE0|FL_BASE_BARS,
2025 .num_ports = 4,
2026 .base_baud = 921600,
2027 .uart_offset = 8,
2028 },
2029 [pbn_b0_bt_8_921600] = {
2030 .flags = FL_BASE0|FL_BASE_BARS,
2031 .num_ports = 8,
2032 .base_baud = 921600,
2033 .uart_offset = 8,
2034 },
2035
2036 [pbn_b1_1_115200] = {
2037 .flags = FL_BASE1,
2038 .num_ports = 1,
2039 .base_baud = 115200,
2040 .uart_offset = 8,
2041 },
2042 [pbn_b1_2_115200] = {
2043 .flags = FL_BASE1,
2044 .num_ports = 2,
2045 .base_baud = 115200,
2046 .uart_offset = 8,
2047 },
2048 [pbn_b1_4_115200] = {
2049 .flags = FL_BASE1,
2050 .num_ports = 4,
2051 .base_baud = 115200,
2052 .uart_offset = 8,
2053 },
2054 [pbn_b1_8_115200] = {
2055 .flags = FL_BASE1,
2056 .num_ports = 8,
2057 .base_baud = 115200,
2058 .uart_offset = 8,
2059 },
04bf7e74
WP		 2060 [pbn_b1_16_115200] = {
2061 .flags = FL_BASE1,
2062 .num_ports = 16,
2063 .base_baud = 115200,
2064 .uart_offset = 8,
2065 },
1da177e4
LT		 2066
2067 [pbn_b1_1_921600] = {
2068 .flags = FL_BASE1,
2069 .num_ports = 1,
2070 .base_baud = 921600,
2071 .uart_offset = 8,
2072 },
2073 [pbn_b1_2_921600] = {
2074 .flags = FL_BASE1,
2075 .num_ports = 2,
2076 .base_baud = 921600,
2077 .uart_offset = 8,
2078 },
2079 [pbn_b1_4_921600] = {
2080 .flags = FL_BASE1,
2081 .num_ports = 4,
2082 .base_baud = 921600,
2083 .uart_offset = 8,
2084 },
2085 [pbn_b1_8_921600] = {
2086 .flags = FL_BASE1,
2087 .num_ports = 8,
2088 .base_baud = 921600,
2089 .uart_offset = 8,
2090 },
26e92861
GH		 2091 [pbn_b1_2_1250000] = {
2092 .flags = FL_BASE1,
2093 .num_ports = 2,
2094 .base_baud = 1250000,
2095 .uart_offset = 8,
2096 },
1da177e4 2097
84f8c6fc
NV		 2098 [pbn_b1_bt_1_115200] = {
2099 .flags = FL_BASE1|FL_BASE_BARS,
2100 .num_ports = 1,
2101 .base_baud = 115200,
2102 .uart_offset = 8,
2103 },
04bf7e74
WP		 2104 [pbn_b1_bt_2_115200] = {
2105 .flags = FL_BASE1|FL_BASE_BARS,
2106 .num_ports = 2,
2107 .base_baud = 115200,
2108 .uart_offset = 8,
2109 },
2110 [pbn_b1_bt_4_115200] = {
2111 .flags = FL_BASE1|FL_BASE_BARS,
2112 .num_ports = 4,
2113 .base_baud = 115200,
2114 .uart_offset = 8,
2115 },
84f8c6fc 2116
1da177e4
LT		 2117 [pbn_b1_bt_2_921600] = {
2118 .flags = FL_BASE1|FL_BASE_BARS,
2119 .num_ports = 2,
2120 .base_baud = 921600,
2121 .uart_offset = 8,
2122 },
2123
2124 [pbn_b1_1_1382400] = {
2125 .flags = FL_BASE1,
2126 .num_ports = 1,
2127 .base_baud = 1382400,
2128 .uart_offset = 8,
2129 },
2130 [pbn_b1_2_1382400] = {
2131 .flags = FL_BASE1,
2132 .num_ports = 2,
2133 .base_baud = 1382400,
2134 .uart_offset = 8,
2135 },
2136 [pbn_b1_4_1382400] = {
2137 .flags = FL_BASE1,
2138 .num_ports = 4,
2139 .base_baud = 1382400,
2140 .uart_offset = 8,
2141 },
2142 [pbn_b1_8_1382400] = {
2143 .flags = FL_BASE1,
2144 .num_ports = 8,
2145 .base_baud = 1382400,
2146 .uart_offset = 8,
2147 },
2148
2149 [pbn_b2_1_115200] = {
2150 .flags = FL_BASE2,
2151 .num_ports = 1,
2152 .base_baud = 115200,
2153 .uart_offset = 8,
2154 },
737c1756
PH		 2155 [pbn_b2_2_115200] = {
2156 .flags = FL_BASE2,
2157 .num_ports = 2,
2158 .base_baud = 115200,
2159 .uart_offset = 8,
2160 },
a9cccd34
MF		 2161 [pbn_b2_4_115200] = {
2162 .flags = FL_BASE2,
2163 .num_ports = 4,
2164 .base_baud = 115200,
2165 .uart_offset = 8,
2166 },
1da177e4
LT		 2167 [pbn_b2_8_115200] = {
2168 .flags = FL_BASE2,
2169 .num_ports = 8,
2170 .base_baud = 115200,
2171 .uart_offset = 8,
2172 },
2173
2174 [pbn_b2_1_460800] = {
2175 .flags = FL_BASE2,
2176 .num_ports = 1,
2177 .base_baud = 460800,
2178 .uart_offset = 8,
2179 },
2180 [pbn_b2_4_460800] = {
2181 .flags = FL_BASE2,
2182 .num_ports = 4,
2183 .base_baud = 460800,
2184 .uart_offset = 8,
2185 },
2186 [pbn_b2_8_460800] = {
2187 .flags = FL_BASE2,
2188 .num_ports = 8,
2189 .base_baud = 460800,
2190 .uart_offset = 8,
2191 },
2192 [pbn_b2_16_460800] = {
2193 .flags = FL_BASE2,
2194 .num_ports = 16,
2195 .base_baud = 460800,
2196 .uart_offset = 8,
2197 },
2198
2199 [pbn_b2_1_921600] = {
2200 .flags = FL_BASE2,
2201 .num_ports = 1,
2202 .base_baud = 921600,
2203 .uart_offset = 8,
2204 },
2205 [pbn_b2_4_921600] = {
2206 .flags = FL_BASE2,
2207 .num_ports = 4,
2208 .base_baud = 921600,
2209 .uart_offset = 8,
2210 },
2211 [pbn_b2_8_921600] = {
2212 .flags = FL_BASE2,
2213 .num_ports = 8,
2214 .base_baud = 921600,
2215 .uart_offset = 8,
2216 },
2217
e847003f
LB		 2218 [pbn_b2_8_1152000] = {
2219 .flags = FL_BASE2,
2220 .num_ports = 8,
2221 .base_baud = 1152000,
2222 .uart_offset = 8,
2223 },
2224
1da177e4
LT		 2225 [pbn_b2_bt_1_115200] = {
2226 .flags = FL_BASE2|FL_BASE_BARS,
2227 .num_ports = 1,
2228 .base_baud = 115200,
2229 .uart_offset = 8,
2230 },
2231 [pbn_b2_bt_2_115200] = {
2232 .flags = FL_BASE2|FL_BASE_BARS,
2233 .num_ports = 2,
2234 .base_baud = 115200,
2235 .uart_offset = 8,
2236 },
2237 [pbn_b2_bt_4_115200] = {
2238 .flags = FL_BASE2|FL_BASE_BARS,
2239 .num_ports = 4,
2240 .base_baud = 115200,
2241 .uart_offset = 8,
2242 },
2243
2244 [pbn_b2_bt_2_921600] = {
2245 .flags = FL_BASE2|FL_BASE_BARS,
2246 .num_ports = 2,
2247 .base_baud = 921600,
2248 .uart_offset = 8,
2249 },
2250 [pbn_b2_bt_4_921600] = {
2251 .flags = FL_BASE2|FL_BASE_BARS,
2252 .num_ports = 4,
2253 .base_baud = 921600,
2254 .uart_offset = 8,
2255 },
2256
d9004eb4
ABL		 2257 [pbn_b3_2_115200] = {
2258 .flags = FL_BASE3,
2259 .num_ports = 2,
2260 .base_baud = 115200,
2261 .uart_offset = 8,
2262 },
1da177e4
LT		 2263 [pbn_b3_4_115200] = {
2264 .flags = FL_BASE3,
2265 .num_ports = 4,
2266 .base_baud = 115200,
2267 .uart_offset = 8,
2268 },
2269 [pbn_b3_8_115200] = {
2270 .flags = FL_BASE3,
2271 .num_ports = 8,
2272 .base_baud = 115200,
2273 .uart_offset = 8,
2274 },
2275
66169ad1
YY		 2276 [pbn_b4_bt_2_921600] = {
2277 .flags = FL_BASE4,
2278 .num_ports = 2,
2279 .base_baud = 921600,
2280 .uart_offset = 8,
2281 },
2282 [pbn_b4_bt_4_921600] = {
2283 .flags = FL_BASE4,
2284 .num_ports = 4,
2285 .base_baud = 921600,
2286 .uart_offset = 8,
2287 },
2288 [pbn_b4_bt_8_921600] = {
2289 .flags = FL_BASE4,
2290 .num_ports = 8,
2291 .base_baud = 921600,
2292 .uart_offset = 8,
2293 },
2294
1da177e4
LT		 2295 /*
2296 * Entries following this are board-specific.
2297 */
2298
2299 /*
2300 * Panacom - IOMEM
2301 */
2302 [pbn_panacom] = {
2303 .flags = FL_BASE2,
2304 .num_ports = 2,
2305 .base_baud = 921600,
2306 .uart_offset = 0x400,
2307 .reg_shift = 7,
2308 },
2309 [pbn_panacom2] = {
2310 .flags = FL_BASE2|FL_BASE_BARS,
2311 .num_ports = 2,
2312 .base_baud = 921600,
2313 .uart_offset = 0x400,
2314 .reg_shift = 7,
2315 },
2316 [pbn_panacom4] = {
2317 .flags = FL_BASE2|FL_BASE_BARS,
2318 .num_ports = 4,
2319 .base_baud = 921600,
2320 .uart_offset = 0x400,
2321 .reg_shift = 7,
2322 },
2323
add7b58e
BH		 2324 [pbn_exsys_4055] = {
2325 .flags = FL_BASE2,
2326 .num_ports = 4,
2327 .base_baud = 115200,
2328 .uart_offset = 8,
2329 },
2330
1da177e4
LT		 2331 /* I think this entry is broken - the first_offset looks wrong --rmk */
2332 [pbn_plx_romulus] = {
2333 .flags = FL_BASE2,
2334 .num_ports = 4,
2335 .base_baud = 921600,
2336 .uart_offset = 8 << 2,
2337 .reg_shift = 2,
2338 .first_offset = 0x03,
2339 },
2340
2341 /*
2342 * This board uses the size of PCI Base region 0 to
2343 * signal now many ports are available
2344 */
2345 [pbn_oxsemi] = {
2346 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2347 .num_ports = 32,
2348 .base_baud = 115200,
2349 .uart_offset = 8,
2350 },
7106b4e3
LH		 2351 [pbn_oxsemi_1_4000000] = {
2352 .flags = FL_BASE0,
2353 .num_ports = 1,
2354 .base_baud = 4000000,
2355 .uart_offset = 0x200,
2356 .first_offset = 0x1000,
2357 },
2358 [pbn_oxsemi_2_4000000] = {
2359 .flags = FL_BASE0,
2360 .num_ports = 2,
2361 .base_baud = 4000000,
2362 .uart_offset = 0x200,
2363 .first_offset = 0x1000,
2364 },
2365 [pbn_oxsemi_4_4000000] = {
2366 .flags = FL_BASE0,
2367 .num_ports = 4,
2368 .base_baud = 4000000,
2369 .uart_offset = 0x200,
2370 .first_offset = 0x1000,
2371 },
2372 [pbn_oxsemi_8_4000000] = {
2373 .flags = FL_BASE0,
2374 .num_ports = 8,
2375 .base_baud = 4000000,
2376 .uart_offset = 0x200,
2377 .first_offset = 0x1000,
2378 },
2379
1da177e4
LT		 2380
2381 /*
2382 * EKF addition for i960 Boards form EKF with serial port.
2383 * Max 256 ports.
2384 */
2385 [pbn_intel_i960] = {
2386 .flags = FL_BASE0,
2387 .num_ports = 32,
2388 .base_baud = 921600,
2389 .uart_offset = 8 << 2,
2390 .reg_shift = 2,
2391 .first_offset = 0x10000,
2392 },
2393 [pbn_sgi_ioc3] = {
2394 .flags = FL_BASE0|FL_NOIRQ,
2395 .num_ports = 1,
2396 .base_baud = 458333,
2397 .uart_offset = 8,
2398 .reg_shift = 0,
2399 .first_offset = 0x20178,
2400 },
2401
1da177e4
LT		 2402 /*
2403 * Computone - uses IOMEM.
2404 */
2405 [pbn_computone_4] = {
2406 .flags = FL_BASE0,
2407 .num_ports = 4,
2408 .base_baud = 921600,
2409 .uart_offset = 0x40,
2410 .reg_shift = 2,
2411 .first_offset = 0x200,
2412 },
2413 [pbn_computone_6] = {
2414 .flags = FL_BASE0,
2415 .num_ports = 6,
2416 .base_baud = 921600,
2417 .uart_offset = 0x40,
2418 .reg_shift = 2,
2419 .first_offset = 0x200,
2420 },
2421 [pbn_computone_8] = {
2422 .flags = FL_BASE0,
2423 .num_ports = 8,
2424 .base_baud = 921600,
2425 .uart_offset = 0x40,
2426 .reg_shift = 2,
2427 .first_offset = 0x200,
2428 },
2429 [pbn_sbsxrsio] = {
2430 .flags = FL_BASE0,
2431 .num_ports = 8,
2432 .base_baud = 460800,
2433 .uart_offset = 256,
2434 .reg_shift = 4,
2435 },
2436 /*
2437 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2438 * Only basic 16550A support.
2439 * XR17C15[24] are not tested, but they should work.
2440 */
2441 [pbn_exar_XR17C152] = {
2442 .flags = FL_BASE0,
2443 .num_ports = 2,
2444 .base_baud = 921600,
2445 .uart_offset = 0x200,
2446 },
2447 [pbn_exar_XR17C154] = {
2448 .flags = FL_BASE0,
2449 .num_ports = 4,
2450 .base_baud = 921600,
2451 .uart_offset = 0x200,
2452 },
2453 [pbn_exar_XR17C158] = {
2454 .flags = FL_BASE0,
2455 .num_ports = 8,
2456 .base_baud = 921600,
2457 .uart_offset = 0x200,
2458 },
c68d2b15
BH		 2459 [pbn_exar_ibm_saturn] = {
2460 .flags = FL_BASE0,
2461 .num_ports = 1,
2462 .base_baud = 921600,
2463 .uart_offset = 0x200,
2464 },
2465
aa798505
OJ		 2466 /*
2467 * PA Semi PWRficient PA6T-1682M on-chip UART
2468 */
2469 [pbn_pasemi_1682M] = {
2470 .flags = FL_BASE0,
2471 .num_ports = 1,
2472 .base_baud = 8333333,
2473 },
46a0fac9
SB		 2474 /*
2475 * National Instruments 843x
2476 */
2477 [pbn_ni8430_16] = {
2478 .flags = FL_BASE0,
2479 .num_ports = 16,
2480 .base_baud = 3686400,
2481 .uart_offset = 0x10,
2482 .first_offset = 0x800,
2483 },
2484 [pbn_ni8430_8] = {
2485 .flags = FL_BASE0,
2486 .num_ports = 8,
2487 .base_baud = 3686400,
2488 .uart_offset = 0x10,
2489 .first_offset = 0x800,
2490 },
2491 [pbn_ni8430_4] = {
2492 .flags = FL_BASE0,
2493 .num_ports = 4,
2494 .base_baud = 3686400,
2495 .uart_offset = 0x10,
2496 .first_offset = 0x800,
2497 },
2498 [pbn_ni8430_2] = {
2499 .flags = FL_BASE0,
2500 .num_ports = 2,
2501 .base_baud = 3686400,
2502 .uart_offset = 0x10,
2503 .first_offset = 0x800,
2504 },
1b62cbf2
KJ		 2505 /*
2506 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2507 */
2508 [pbn_ADDIDATA_PCIe_1_3906250] = {
2509 .flags = FL_BASE0,
2510 .num_ports = 1,
2511 .base_baud = 3906250,
2512 .uart_offset = 0x200,
2513 .first_offset = 0x1000,
2514 },
2515 [pbn_ADDIDATA_PCIe_2_3906250] = {
2516 .flags = FL_BASE0,
2517 .num_ports = 2,
2518 .base_baud = 3906250,
2519 .uart_offset = 0x200,
2520 .first_offset = 0x1000,
2521 },
2522 [pbn_ADDIDATA_PCIe_4_3906250] = {
2523 .flags = FL_BASE0,
2524 .num_ports = 4,
2525 .base_baud = 3906250,
2526 .uart_offset = 0x200,
2527 .first_offset = 0x1000,
2528 },
2529 [pbn_ADDIDATA_PCIe_8_3906250] = {
2530 .flags = FL_BASE0,
2531 .num_ports = 8,
2532 .base_baud = 3906250,
2533 .uart_offset = 0x200,
2534 .first_offset = 0x1000,
2535 },
095e24b0
DB		 2536 [pbn_ce4100_1_115200] = {
2537 .flags = FL_BASE0,
2538 .num_ports = 1,
2539 .base_baud = 921600,
2540 .reg_shift = 2,
2541 },
d9a0fbfd
AP		 2542 [pbn_omegapci] = {
2543 .flags = FL_BASE0,
2544 .num_ports = 8,
2545 .base_baud = 115200,
2546 .uart_offset = 0x200,
2547 },
7808edcd
NG		 2548 [pbn_NETMOS9900_2s_115200] = {
2549 .flags = FL_BASE0,
2550 .num_ports = 2,
2551 .base_baud = 115200,
2552 },
1da177e4
LT		 2553};
2554
436bbd43 2555static const struct pci_device_id softmodem_blacklist[] = {
5756ee99 2556 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 2557 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2558 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
436bbd43
CS		 2559};
2560
1da177e4
LT		 2561/*
2562 * Given a complete unknown PCI device, try to use some heuristics to
2563 * guess what the configuration might be, based on the pitiful PCI
2564 * serial specs. Returns 0 on success, 1 on failure.
2565 */
2566static int __devinit
1c7c1fe5 2567serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 2568{
436bbd43 2569 const struct pci_device_id *blacklist;
1da177e4 2570 int num_iomem, num_port, first_port = -1, i;
5756ee99 2571
1da177e4
LT		 2572 /*
2573 * If it is not a communications device or the programming
2574 * interface is greater than 6, give up.
2575 *
2576 * (Should we try to make guesses for multiport serial devices
5756ee99 2577 * later?)
1da177e4
LT		 2578 */
2579 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2580 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2581 (dev->class & 0xff) > 6)
2582 return -ENODEV;
2583
436bbd43
CS		 2584 /*
2585 * Do not access blacklisted devices that are known not to
2586 * feature serial ports.
2587 */
2588 for (blacklist = softmodem_blacklist;
2589 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2590 blacklist++) {
2591 if (dev->vendor == blacklist->vendor &&
2592 dev->device == blacklist->device)
2593 return -ENODEV;
2594 }
2595
1da177e4
LT		 2596 num_iomem = num_port = 0;
2597 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2598 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2599 num_port++;
2600 if (first_port == -1)
2601 first_port = i;
2602 }
2603 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2604 num_iomem++;
2605 }
2606
2607 /*
2608 * If there is 1 or 0 iomem regions, and exactly one port,
2609 * use it. We guess the number of ports based on the IO
2610 * region size.
2611 */
2612 if (num_iomem <= 1 && num_port == 1) {
2613 board->flags = first_port;
2614 board->num_ports = pci_resource_len(dev, first_port) / 8;
2615 return 0;
2616 }
2617
2618 /*
2619 * Now guess if we've got a board which indexes by BARs.
2620 * Each IO BAR should be 8 bytes, and they should follow
2621 * consecutively.
2622 */
2623 first_port = -1;
2624 num_port = 0;
2625 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2626 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2627 pci_resource_len(dev, i) == 8 &&
2628 (first_port == -1 || (first_port + num_port) == i)) {
2629 num_port++;
2630 if (first_port == -1)
2631 first_port = i;
2632 }
2633 }
2634
2635 if (num_port > 1) {
2636 board->flags = first_port | FL_BASE_BARS;
2637 board->num_ports = num_port;
2638 return 0;
2639 }
2640
2641 return -ENODEV;
2642}
2643
2644static inline int
975a1a7d
RK		 2645serial_pci_matches(const struct pciserial_board *board,
2646 const struct pciserial_board *guessed)
1da177e4
LT		 2647{
2648 return
2649 board->num_ports == guessed->num_ports &&
2650 board->base_baud == guessed->base_baud &&
2651 board->uart_offset == guessed->uart_offset &&
2652 board->reg_shift == guessed->reg_shift &&
2653 board->first_offset == guessed->first_offset;
2654}
2655
241fc436 2656struct serial_private *
975a1a7d 2657pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 2658{
72ce9a83 2659 struct uart_port serial_port;
1da177e4 2660 struct serial_private *priv;
1da177e4
LT		 2661 struct pci_serial_quirk *quirk;
2662 int rc, nr_ports, i;
2663
1da177e4
LT		 2664 nr_ports = board->num_ports;
2665
2666 /*
2667 * Find an init and setup quirks.
2668 */
2669 quirk = find_quirk(dev);
2670
2671 /*
2672 * Run the new-style initialization function.
2673 * The initialization function returns:
2674 * <0 - error
2675 * 0 - use board->num_ports
2676 * >0 - number of ports
2677 */
2678 if (quirk->init) {
2679 rc = quirk->init(dev);
241fc436
RK		 2680 if (rc < 0) {
2681 priv = ERR_PTR(rc);
2682 goto err_out;
2683 }
1da177e4
LT		 2684 if (rc)
2685 nr_ports = rc;
2686 }
2687
8f31bb39 2688 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 2689 sizeof(unsigned int) * nr_ports,
2690 GFP_KERNEL);
2691 if (!priv) {
241fc436
RK		 2692 priv = ERR_PTR(-ENOMEM);
2693 goto err_deinit;
1da177e4
LT		 2694 }
2695
70db3d91 2696 priv->dev = dev;
1da177e4 2697 priv->quirk = quirk;
1da177e4 2698
72ce9a83
RK		 2699 memset(&serial_port, 0, sizeof(struct uart_port));
2700 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2701 serial_port.uartclk = board->base_baud * 16;
2702 serial_port.irq = get_pci_irq(dev, board);
2703 serial_port.dev = &dev->dev;
2704
1da177e4 2705 for (i = 0; i < nr_ports; i++) {
70db3d91 2706 if (quirk->setup(priv, board, &serial_port, i))
1da177e4 2707 break;
72ce9a83 2708
1da177e4 2709#ifdef SERIAL_DEBUG_PCI
80647b95 2710 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
1da177e4
LT		 2711 serial_port.iobase, serial_port.irq, serial_port.iotype);
2712#endif
5756ee99 2713
1da177e4
LT		 2714 priv->line[i] = serial8250_register_port(&serial_port);
2715 if (priv->line[i] < 0) {
2716 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2717 break;
2718 }
2719 }
1da177e4 2720 priv->nr = i;
241fc436 2721 return priv;
1da177e4 2722
5756ee99 2723err_deinit:
1da177e4
LT		 2724 if (quirk->exit)
2725 quirk->exit(dev);
5756ee99 2726err_out:
241fc436 2727 return priv;
1da177e4 2728}
241fc436 2729EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 2730
241fc436 2731void pciserial_remove_ports(struct serial_private *priv)
1da177e4 2732{
056a8763
RK		 2733 struct pci_serial_quirk *quirk;
2734 int i;
1da177e4 2735
056a8763
RK		 2736 for (i = 0; i < priv->nr; i++)
2737 serial8250_unregister_port(priv->line[i]);
1da177e4 2738
056a8763
RK		 2739 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2740 if (priv->remapped_bar[i])
2741 iounmap(priv->remapped_bar[i]);
2742 priv->remapped_bar[i] = NULL;
2743 }
1da177e4 2744
056a8763
RK		 2745 /*
2746 * Find the exit quirks.
2747 */
241fc436 2748 quirk = find_quirk(priv->dev);
056a8763 2749 if (quirk->exit)
241fc436
RK		 2750 quirk->exit(priv->dev);
2751
2752 kfree(priv);
2753}
2754EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2755
2756void pciserial_suspend_ports(struct serial_private *priv)
2757{
2758 int i;
2759
2760 for (i = 0; i < priv->nr; i++)
2761 if (priv->line[i] >= 0)
2762 serial8250_suspend_port(priv->line[i]);
2763}
2764EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2765
2766void pciserial_resume_ports(struct serial_private *priv)
2767{
2768 int i;
2769
2770 /*
2771 * Ensure that the board is correctly configured.
2772 */
2773 if (priv->quirk->init)
2774 priv->quirk->init(priv->dev);
2775
2776 for (i = 0; i < priv->nr; i++)
2777 if (priv->line[i] >= 0)
2778 serial8250_resume_port(priv->line[i]);
2779}
2780EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2781
2782/*
2783 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2784 * to the arrangement of serial ports on a PCI card.
2785 */
2786static int __devinit
2787pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2788{
5bf8f501 2789 struct pci_serial_quirk *quirk;
241fc436 2790 struct serial_private *priv;
975a1a7d
RK		 2791 const struct pciserial_board *board;
2792 struct pciserial_board tmp;
241fc436
RK		 2793 int rc;
2794
5bf8f501
FB		 2795 quirk = find_quirk(dev);
2796 if (quirk->probe) {
2797 rc = quirk->probe(dev);
2798 if (rc)
2799 return rc;
2800 }
2801
241fc436
RK		 2802 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2803 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2804 ent->driver_data);
2805 return -EINVAL;
2806 }
2807
2808 board = &pci_boards[ent->driver_data];
2809
2810 rc = pci_enable_device(dev);
2807190b 2811 pci_save_state(dev);
241fc436
RK		 2812 if (rc)
2813 return rc;
2814
2815 if (ent->driver_data == pbn_default) {
2816 /*
2817 * Use a copy of the pci_board entry for this;
2818 * avoid changing entries in the table.
2819 */
2820 memcpy(&tmp, board, sizeof(struct pciserial_board));
2821 board = &tmp;
2822
2823 /*
2824 * We matched one of our class entries. Try to
2825 * determine the parameters of this board.
2826 */
975a1a7d 2827 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 2828 if (rc)
2829 goto disable;
2830 } else {
2831 /*
2832 * We matched an explicit entry. If we are able to
2833 * detect this boards settings with our heuristic,
2834 * then we no longer need this entry.
2835 */
2836 memcpy(&tmp, &pci_boards[pbn_default],
2837 sizeof(struct pciserial_board));
2838 rc = serial_pci_guess_board(dev, &tmp);
2839 if (rc == 0 && serial_pci_matches(board, &tmp))
2840 moan_device("Redundant entry in serial pci_table.",
2841 dev);
2842 }
2843
2844 priv = pciserial_init_ports(dev, board);
2845 if (!IS_ERR(priv)) {
2846 pci_set_drvdata(dev, priv);
2847 return 0;
2848 }
2849
2850 rc = PTR_ERR(priv);
1da177e4 2851
241fc436 2852 disable:
056a8763 2853 pci_disable_device(dev);
241fc436
RK		 2854 return rc;
2855}
1da177e4 2856
241fc436
RK		 2857static void __devexit pciserial_remove_one(struct pci_dev *dev)
2858{
2859 struct serial_private *priv = pci_get_drvdata(dev);
2860
2861 pci_set_drvdata(dev, NULL);
2862
2863 pciserial_remove_ports(priv);
2864
2865 pci_disable_device(dev);
1da177e4
LT		 2866}
2867
1d5e7996 2868#ifdef CONFIG_PM
1da177e4
LT		 2869static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2870{
2871 struct serial_private *priv = pci_get_drvdata(dev);
2872
241fc436
RK		 2873 if (priv)
2874 pciserial_suspend_ports(priv);
1da177e4 2875
1da177e4
LT		 2876 pci_save_state(dev);
2877 pci_set_power_state(dev, pci_choose_state(dev, state));
2878 return 0;
2879}
2880
2881static int pciserial_resume_one(struct pci_dev *dev)
2882{
ccb9d59e 2883 int err;
1da177e4
LT		 2884 struct serial_private *priv = pci_get_drvdata(dev);
2885
2886 pci_set_power_state(dev, PCI_D0);
2887 pci_restore_state(dev);
2888
2889 if (priv) {
1da177e4
LT		 2890 /*
2891 * The device may have been disabled. Re-enable it.
2892 */
ccb9d59e 2893 err = pci_enable_device(dev);
40836c48 2894 /* FIXME: We cannot simply error out here */
ccb9d59e 2895 if (err)
40836c48 2896 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
241fc436 2897 pciserial_resume_ports(priv);
1da177e4
LT		 2898 }
2899 return 0;
2900}
1d5e7996 2901#endif
1da177e4
LT		 2902
2903static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 2904 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2905 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2906 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2907 pbn_b2_8_921600 },
1da177e4
LT		 2908 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2909 PCI_SUBVENDOR_ID_CONNECT_TECH,
2910 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2911 pbn_b1_8_1382400 },
2912 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2913 PCI_SUBVENDOR_ID_CONNECT_TECH,
2914 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2915 pbn_b1_4_1382400 },
2916 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2917 PCI_SUBVENDOR_ID_CONNECT_TECH,
2918 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2919 pbn_b1_2_1382400 },
2920 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2921 PCI_SUBVENDOR_ID_CONNECT_TECH,
2922 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2923 pbn_b1_8_1382400 },
2924 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2925 PCI_SUBVENDOR_ID_CONNECT_TECH,
2926 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2927 pbn_b1_4_1382400 },
2928 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2929 PCI_SUBVENDOR_ID_CONNECT_TECH,
2930 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2931 pbn_b1_2_1382400 },
2932 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2933 PCI_SUBVENDOR_ID_CONNECT_TECH,
2934 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2935 pbn_b1_8_921600 },
2936 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2937 PCI_SUBVENDOR_ID_CONNECT_TECH,
2938 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2939 pbn_b1_8_921600 },
2940 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2941 PCI_SUBVENDOR_ID_CONNECT_TECH,
2942 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2943 pbn_b1_4_921600 },
2944 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2945 PCI_SUBVENDOR_ID_CONNECT_TECH,
2946 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2947 pbn_b1_4_921600 },
2948 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2949 PCI_SUBVENDOR_ID_CONNECT_TECH,
2950 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2951 pbn_b1_2_921600 },
2952 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2953 PCI_SUBVENDOR_ID_CONNECT_TECH,
2954 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2955 pbn_b1_8_921600 },
2956 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2957 PCI_SUBVENDOR_ID_CONNECT_TECH,
2958 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2959 pbn_b1_8_921600 },
2960 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2961 PCI_SUBVENDOR_ID_CONNECT_TECH,
2962 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2963 pbn_b1_4_921600 },
26e92861
GH		 2964 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2965 PCI_SUBVENDOR_ID_CONNECT_TECH,
2966 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2967 pbn_b1_2_1250000 },
2968 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2969 PCI_SUBVENDOR_ID_CONNECT_TECH,
2970 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2971 pbn_b0_2_1843200 },
2972 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2973 PCI_SUBVENDOR_ID_CONNECT_TECH,
2974 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2975 pbn_b0_4_1843200 },
85d1494e
YY		 2976 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2977 PCI_VENDOR_ID_AFAVLAB,
2978 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2979 pbn_b0_4_1152000 },
26e92861
GH		 2980 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2981 PCI_SUBVENDOR_ID_CONNECT_TECH,
2982 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2983 pbn_b0_2_1843200_200 },
2984 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2985 PCI_SUBVENDOR_ID_CONNECT_TECH,
2986 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2987 pbn_b0_4_1843200_200 },
2988 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2989 PCI_SUBVENDOR_ID_CONNECT_TECH,
2990 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2991 pbn_b0_8_1843200_200 },
2992 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2993 PCI_SUBVENDOR_ID_CONNECT_TECH,
2994 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2995 pbn_b0_2_1843200_200 },
2996 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2997 PCI_SUBVENDOR_ID_CONNECT_TECH,
2998 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2999 pbn_b0_4_1843200_200 },
3000 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3001 PCI_SUBVENDOR_ID_CONNECT_TECH,
3002 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3003 pbn_b0_8_1843200_200 },
3004 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3005 PCI_SUBVENDOR_ID_CONNECT_TECH,
3006 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3007 pbn_b0_2_1843200_200 },
3008 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3009 PCI_SUBVENDOR_ID_CONNECT_TECH,
3010 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3011 pbn_b0_4_1843200_200 },
3012 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3013 PCI_SUBVENDOR_ID_CONNECT_TECH,
3014 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3015 pbn_b0_8_1843200_200 },
3016 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3017 PCI_SUBVENDOR_ID_CONNECT_TECH,
3018 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3019 pbn_b0_2_1843200_200 },
3020 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3021 PCI_SUBVENDOR_ID_CONNECT_TECH,
3022 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3023 pbn_b0_4_1843200_200 },
3024 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3025 PCI_SUBVENDOR_ID_CONNECT_TECH,
3026 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3027 pbn_b0_8_1843200_200 },
c68d2b15
BH		 3028 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3029 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3030 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 3031
3032 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 3033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3034 pbn_b2_bt_1_115200 },
3035 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 3036 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3037 pbn_b2_bt_2_115200 },
3038 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 3039 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3040 pbn_b2_bt_4_115200 },
3041 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 3042 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3043 pbn_b2_bt_2_115200 },
3044 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 3045 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3046 pbn_b2_bt_4_115200 },
3047 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 3048 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3049 pbn_b2_8_115200 },
e65f0f82
FL		 3050 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3051 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3052 pbn_b2_8_460800 },
1da177e4
LT		 3053 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3054 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3055 pbn_b2_8_115200 },
3056
3057 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3059 pbn_b2_bt_2_115200 },
3060 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3062 pbn_b2_bt_2_921600 },
3063 /*
3064 * VScom SPCOM800, from sl@s.pl
3065 */
5756ee99
AC		 3066 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3067 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3068 pbn_b2_8_921600 },
3069 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 3070 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3071 pbn_b2_4_921600 },
b76c5a07
CB		 3072 /* Unknown card - subdevice 0x1584 */
3073 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3074 PCI_VENDOR_ID_PLX,
3075 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3076 pbn_b0_4_115200 },
1da177e4
LT		 3077 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3078 PCI_SUBVENDOR_ID_KEYSPAN,
3079 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3080 pbn_panacom },
3081 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3083 pbn_panacom4 },
3084 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3086 pbn_panacom2 },
a9cccd34
MF		 3087 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3088 PCI_VENDOR_ID_ESDGMBH,
3089 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3090 pbn_b2_4_115200 },
1da177e4
LT		 3091 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3092 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3093 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 3094 pbn_b2_4_460800 },
3095 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3096 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3097 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 3098 pbn_b2_8_460800 },
3099 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3100 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3101 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 3102 pbn_b2_16_460800 },
3103 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3104 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3105 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 3106 pbn_b2_16_460800 },
3107 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3108 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 3109 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 3110 pbn_b2_4_460800 },
3111 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3112 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 3113 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 3114 pbn_b2_8_460800 },
add7b58e
BH		 3115 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3116 PCI_SUBVENDOR_ID_EXSYS,
3117 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3118 pbn_exsys_4055 },
1da177e4
LT		 3119 /*
3120 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3121 * (Exoray@isys.ca)
3122 */
3123 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3124 0x10b5, 0x106a, 0, 0,
3125 pbn_plx_romulus },
3126 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3128 pbn_b1_4_115200 },
3129 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3131 pbn_b1_2_115200 },
3132 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3134 pbn_b1_8_115200 },
3135 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3137 pbn_b1_8_115200 },
3138 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 3139 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3140 0, 0,
1da177e4 3141 pbn_b0_4_921600 },
fbc0dc0d 3142 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 3143 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3144 0, 0,
fbc0dc0d 3145 pbn_b0_4_1152000 },
c9bd9d01
MP		 3146 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3148 pbn_b0_bt_2_921600 },
db1de159
DR		 3149
3150 /*
3151 * The below card is a little controversial since it is the
3152 * subject of a PCI vendor/device ID clash. (See
3153 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3154 * For now just used the hex ID 0x950a.
3155 */
39aced68
NV		 3156 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3157 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
3158 pbn_b0_2_115200 },
db1de159
DR		 3159 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3161 pbn_b0_2_1130000 },
70fd8fde
AP		 3162 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3163 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3164 pbn_b0_1_921600 },
1da177e4
LT		 3165 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3167 pbn_b0_4_115200 },
3168 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3170 pbn_b0_bt_2_921600 },
e847003f
LB		 3171 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3172 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3173 pbn_b2_8_1152000 },
1da177e4 3174
7106b4e3
LH		 3175 /*
3176 * Oxford Semiconductor Inc. Tornado PCI express device range.
3177 */
3178 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3179 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3180 pbn_b0_1_4000000 },
3181 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3182 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3183 pbn_b0_1_4000000 },
3184 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3185 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3186 pbn_oxsemi_1_4000000 },
3187 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3188 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3189 pbn_oxsemi_1_4000000 },
3190 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3191 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3192 pbn_b0_1_4000000 },
3193 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3194 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3195 pbn_b0_1_4000000 },
3196 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3197 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3198 pbn_oxsemi_1_4000000 },
3199 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3201 pbn_oxsemi_1_4000000 },
3202 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3204 pbn_b0_1_4000000 },
3205 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3206 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3207 pbn_b0_1_4000000 },
3208 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3210 pbn_b0_1_4000000 },
3211 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3212 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3213 pbn_b0_1_4000000 },
3214 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3215 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3216 pbn_oxsemi_2_4000000 },
3217 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3218 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3219 pbn_oxsemi_2_4000000 },
3220 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3221 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3222 pbn_oxsemi_4_4000000 },
3223 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3224 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3225 pbn_oxsemi_4_4000000 },
3226 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3227 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3228 pbn_oxsemi_8_4000000 },
3229 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3230 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3231 pbn_oxsemi_8_4000000 },
3232 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3233 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3234 pbn_oxsemi_1_4000000 },
3235 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3237 pbn_oxsemi_1_4000000 },
3238 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3239 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3240 pbn_oxsemi_1_4000000 },
3241 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3242 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3243 pbn_oxsemi_1_4000000 },
3244 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3245 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3246 pbn_oxsemi_1_4000000 },
3247 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3248 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3249 pbn_oxsemi_1_4000000 },
3250 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3251 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3252 pbn_oxsemi_1_4000000 },
3253 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3255 pbn_oxsemi_1_4000000 },
3256 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3258 pbn_oxsemi_1_4000000 },
3259 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3261 pbn_oxsemi_1_4000000 },
3262 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3264 pbn_oxsemi_1_4000000 },
3265 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3267 pbn_oxsemi_1_4000000 },
3268 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3270 pbn_oxsemi_1_4000000 },
3271 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3273 pbn_oxsemi_1_4000000 },
3274 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3275 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3276 pbn_oxsemi_1_4000000 },
3277 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3279 pbn_oxsemi_1_4000000 },
3280 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3282 pbn_oxsemi_1_4000000 },
3283 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3285 pbn_oxsemi_1_4000000 },
3286 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3288 pbn_oxsemi_1_4000000 },
3289 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3291 pbn_oxsemi_1_4000000 },
3292 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3294 pbn_oxsemi_1_4000000 },
3295 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3296 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3297 pbn_oxsemi_1_4000000 },
3298 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3300 pbn_oxsemi_1_4000000 },
3301 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3303 pbn_oxsemi_1_4000000 },
3304 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3306 pbn_oxsemi_1_4000000 },
3307 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3309 pbn_oxsemi_1_4000000 },
b80de369
LH		 3310 /*
3311 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3312 */
3313 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3314 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3315 pbn_oxsemi_1_4000000 },
3316 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3317 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3318 pbn_oxsemi_2_4000000 },
3319 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3320 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3321 pbn_oxsemi_4_4000000 },
3322 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3323 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3324 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 3325
3326 /*
3327 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3328 */
3329 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3330 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3331 pbn_oxsemi_2_4000000 },
3332
1da177e4
LT		 3333 /*
3334 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3335 * from skokodyn@yahoo.com
3336 */
3337 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3338 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3339 pbn_sbsxrsio },
3340 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3341 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3342 pbn_sbsxrsio },
3343 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3344 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3345 pbn_sbsxrsio },
3346 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3347 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3348 pbn_sbsxrsio },
3349
3350 /*
3351 * Digitan DS560-558, from jimd@esoft.com
3352 */
3353 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 3354 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3355 pbn_b1_1_115200 },
3356
3357 /*
3358 * Titan Electronic cards
3359 * The 400L and 800L have a custom setup quirk.
3360 */
3361 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 3362 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3363 pbn_b0_1_921600 },
3364 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 3365 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3366 pbn_b0_2_921600 },
3367 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 3368 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3369 pbn_b0_4_921600 },
3370 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 3371 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3372 pbn_b0_4_921600 },
3373 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3374 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3375 pbn_b1_1_921600 },
3376 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3377 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3378 pbn_b1_bt_2_921600 },
3379 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3380 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3381 pbn_b0_bt_4_921600 },
3382 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3384 pbn_b0_bt_8_921600 },
66169ad1
YY		 3385 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3387 pbn_b4_bt_2_921600 },
3388 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3389 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3390 pbn_b4_bt_4_921600 },
3391 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3392 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3393 pbn_b4_bt_8_921600 },
3394 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3395 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3396 pbn_b0_4_921600 },
3397 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3398 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3399 pbn_b0_4_921600 },
3400 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3401 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3402 pbn_b0_4_921600 },
3403 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3404 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3405 pbn_oxsemi_1_4000000 },
3406 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3407 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3408 pbn_oxsemi_2_4000000 },
3409 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3410 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3411 pbn_oxsemi_4_4000000 },
3412 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3414 pbn_oxsemi_8_4000000 },
3415 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3417 pbn_oxsemi_2_4000000 },
3418 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3420 pbn_oxsemi_2_4000000 },
1e9deb11
YY		 3421 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
3422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3423 pbn_b0_4_921600 },
3424 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
3425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3426 pbn_b0_4_921600 },
3427 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
3428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3429 pbn_b0_4_921600 },
3430 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
3431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3432 pbn_b0_4_921600 },
1da177e4
LT		 3433
3434 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3436 pbn_b2_1_460800 },
3437 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3439 pbn_b2_1_460800 },
3440 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3442 pbn_b2_1_460800 },
3443 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3445 pbn_b2_bt_2_921600 },
3446 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3448 pbn_b2_bt_2_921600 },
3449 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3451 pbn_b2_bt_2_921600 },
3452 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3454 pbn_b2_bt_4_921600 },
3455 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3457 pbn_b2_bt_4_921600 },
3458 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3460 pbn_b2_bt_4_921600 },
3461 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3463 pbn_b0_1_921600 },
3464 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3466 pbn_b0_1_921600 },
3467 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3469 pbn_b0_1_921600 },
3470 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3472 pbn_b0_bt_2_921600 },
3473 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3475 pbn_b0_bt_2_921600 },
3476 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3478 pbn_b0_bt_2_921600 },
3479 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3481 pbn_b0_bt_4_921600 },
3482 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3484 pbn_b0_bt_4_921600 },
3485 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3487 pbn_b0_bt_4_921600 },
3ec9c594
AP		 3488 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3490 pbn_b0_bt_8_921600 },
3491 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3493 pbn_b0_bt_8_921600 },
3494 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3496 pbn_b0_bt_8_921600 },
1da177e4
LT		 3497
3498 /*
3499 * Computone devices submitted by Doug McNash dmcnash@computone.com
3500 */
3501 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3502 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3503 0, 0, pbn_computone_4 },
3504 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3505 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3506 0, 0, pbn_computone_8 },
3507 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3508 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3509 0, 0, pbn_computone_6 },
3510
3511 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3513 pbn_oxsemi },
3514 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3515 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3516 pbn_b0_bt_1_921600 },
3517
3518 /*
3519 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3520 */
3521 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3522 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3523 pbn_b0_bt_8_115200 },
3524 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3525 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3526 pbn_b0_bt_8_115200 },
3527
3528 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3530 pbn_b0_bt_2_115200 },
3531 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3532 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3533 pbn_b0_bt_2_115200 },
3534 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3535 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3536 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 3537 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3538 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3539 pbn_b0_bt_2_115200 },
3540 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3541 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3542 pbn_b0_bt_2_115200 },
1da177e4
LT		 3543 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3544 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3545 pbn_b0_bt_4_460800 },
3546 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3548 pbn_b0_bt_4_460800 },
3549 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3550 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3551 pbn_b0_bt_2_460800 },
3552 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3553 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3554 pbn_b0_bt_2_460800 },
3555 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3556 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3557 pbn_b0_bt_2_460800 },
3558 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3559 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3560 pbn_b0_bt_1_115200 },
3561 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3562 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3563 pbn_b0_bt_1_460800 },
3564
1fb8cacc
RK		 3565 /*
3566 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3567 * Cards are identified by their subsystem vendor IDs, which
3568 * (in hex) match the model number.
3569 *
3570 * Note that JC140x are RS422/485 cards which require ox950
3571 * ACR = 0x10, and as such are not currently fully supported.
3572 */
3573 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3574 0x1204, 0x0004, 0, 0,
3575 pbn_b0_4_921600 },
3576 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3577 0x1208, 0x0004, 0, 0,
3578 pbn_b0_4_921600 },
3579/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3580 0x1402, 0x0002, 0, 0,
3581 pbn_b0_2_921600 }, */
3582/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3583 0x1404, 0x0004, 0, 0,
3584 pbn_b0_4_921600 }, */
3585 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3586 0x1208, 0x0004, 0, 0,
3587 pbn_b0_4_921600 },
3588
2a52fcb5
KY		 3589 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3590 0x1204, 0x0004, 0, 0,
3591 pbn_b0_4_921600 },
3592 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3593 0x1208, 0x0004, 0, 0,
3594 pbn_b0_4_921600 },
3595 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3596 0x1208, 0x0004, 0, 0,
3597 pbn_b0_4_921600 },
1da177e4
LT		 3598 /*
3599 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3600 */
3601 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3603 pbn_b1_1_1382400 },
3604
3605 /*
3606 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3607 */
3608 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3610 pbn_b1_1_1382400 },
3611
3612 /*
3613 * RAStel 2 port modem, gerg@moreton.com.au
3614 */
3615 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3617 pbn_b2_bt_2_115200 },
3618
3619 /*
3620 * EKF addition for i960 Boards form EKF with serial port
3621 */
3622 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3623 0xE4BF, PCI_ANY_ID, 0, 0,
3624 pbn_intel_i960 },
3625
3626 /*
3627 * Xircom Cardbus/Ethernet combos
3628 */
3629 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3631 pbn_b0_1_115200 },
3632 /*
3633 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3634 */
3635 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3637 pbn_b0_1_115200 },
3638
3639 /*
3640 * Untested PCI modems, sent in from various folks...
3641 */
3642
3643 /*
3644 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3645 */
3646 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3647 0x1048, 0x1500, 0, 0,
3648 pbn_b1_1_115200 },
3649
3650 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3651 0xFF00, 0, 0, 0,
3652 pbn_sgi_ioc3 },
3653
3654 /*
3655 * HP Diva card
3656 */
3657 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3658 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3659 pbn_b1_1_115200 },
3660 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3661 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3662 pbn_b0_5_115200 },
3663 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3664 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3665 pbn_b2_1_115200 },
3666
d9004eb4
ABL		 3667 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3669 pbn_b3_2_115200 },
1da177e4
LT		 3670 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3672 pbn_b3_4_115200 },
3673 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3675 pbn_b3_8_115200 },
3676
3677 /*
3678 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3679 */
3680 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3681 PCI_ANY_ID, PCI_ANY_ID,
3682 0,
3683 0, pbn_exar_XR17C152 },
3684 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3685 PCI_ANY_ID, PCI_ANY_ID,
3686 0,
3687 0, pbn_exar_XR17C154 },
3688 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3689 PCI_ANY_ID, PCI_ANY_ID,
3690 0,
3691 0, pbn_exar_XR17C158 },
3692
3693 /*
3694 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3695 */
3696 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3698 pbn_b0_1_115200 },
84f8c6fc
NV		 3699 /*
3700 * ITE
3701 */
3702 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3703 PCI_ANY_ID, PCI_ANY_ID,
3704 0, 0,
3705 pbn_b1_bt_1_115200 },
1da177e4 3706
737c1756
PH		 3707 /*
3708 * IntaShield IS-200
3709 */
3710 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3711 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3712 pbn_b2_2_115200 },
4b6f6ce9
IGP		 3713 /*
3714 * IntaShield IS-400
3715 */
3716 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3717 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3718 pbn_b2_4_115200 },
48212008
TH		 3719 /*
3720 * Perle PCI-RAS cards
3721 */
3722 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3723 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3724 0, 0, pbn_b2_4_921600 },
3725 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3726 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3727 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 3728
3729 /*
3730 * Mainpine series cards: Fairly standard layout but fools
3731 * parts of the autodetect in some cases and uses otherwise
3732 * unmatched communications subclasses in the PCI Express case
3733 */
3734
3735 { /* RockForceDUO */
3736 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3737 PCI_VENDOR_ID_MAINPINE, 0x0200,
3738 0, 0, pbn_b0_2_115200 },
3739 { /* RockForceQUATRO */
3740 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3741 PCI_VENDOR_ID_MAINPINE, 0x0300,
3742 0, 0, pbn_b0_4_115200 },
3743 { /* RockForceDUO+ */
3744 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3745 PCI_VENDOR_ID_MAINPINE, 0x0400,
3746 0, 0, pbn_b0_2_115200 },
3747 { /* RockForceQUATRO+ */
3748 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3749 PCI_VENDOR_ID_MAINPINE, 0x0500,
3750 0, 0, pbn_b0_4_115200 },
3751 { /* RockForce+ */
3752 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3753 PCI_VENDOR_ID_MAINPINE, 0x0600,
3754 0, 0, pbn_b0_2_115200 },
3755 { /* RockForce+ */
3756 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3757 PCI_VENDOR_ID_MAINPINE, 0x0700,
3758 0, 0, pbn_b0_4_115200 },
3759 { /* RockForceOCTO+ */
3760 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3761 PCI_VENDOR_ID_MAINPINE, 0x0800,
3762 0, 0, pbn_b0_8_115200 },
3763 { /* RockForceDUO+ */
3764 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3765 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3766 0, 0, pbn_b0_2_115200 },
3767 { /* RockForceQUARTRO+ */
3768 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3769 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3770 0, 0, pbn_b0_4_115200 },
3771 { /* RockForceOCTO+ */
3772 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3773 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3774 0, 0, pbn_b0_8_115200 },
3775 { /* RockForceD1 */
3776 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3777 PCI_VENDOR_ID_MAINPINE, 0x2000,
3778 0, 0, pbn_b0_1_115200 },
3779 { /* RockForceF1 */
3780 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3781 PCI_VENDOR_ID_MAINPINE, 0x2100,
3782 0, 0, pbn_b0_1_115200 },
3783 { /* RockForceD2 */
3784 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3785 PCI_VENDOR_ID_MAINPINE, 0x2200,
3786 0, 0, pbn_b0_2_115200 },
3787 { /* RockForceF2 */
3788 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3789 PCI_VENDOR_ID_MAINPINE, 0x2300,
3790 0, 0, pbn_b0_2_115200 },
3791 { /* RockForceD4 */
3792 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3793 PCI_VENDOR_ID_MAINPINE, 0x2400,
3794 0, 0, pbn_b0_4_115200 },
3795 { /* RockForceF4 */
3796 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3797 PCI_VENDOR_ID_MAINPINE, 0x2500,
3798 0, 0, pbn_b0_4_115200 },
3799 { /* RockForceD8 */
3800 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3801 PCI_VENDOR_ID_MAINPINE, 0x2600,
3802 0, 0, pbn_b0_8_115200 },
3803 { /* RockForceF8 */
3804 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3805 PCI_VENDOR_ID_MAINPINE, 0x2700,
3806 0, 0, pbn_b0_8_115200 },
3807 { /* IQ Express D1 */
3808 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3809 PCI_VENDOR_ID_MAINPINE, 0x3000,
3810 0, 0, pbn_b0_1_115200 },
3811 { /* IQ Express F1 */
3812 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3813 PCI_VENDOR_ID_MAINPINE, 0x3100,
3814 0, 0, pbn_b0_1_115200 },
3815 { /* IQ Express D2 */
3816 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3817 PCI_VENDOR_ID_MAINPINE, 0x3200,
3818 0, 0, pbn_b0_2_115200 },
3819 { /* IQ Express F2 */
3820 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3821 PCI_VENDOR_ID_MAINPINE, 0x3300,
3822 0, 0, pbn_b0_2_115200 },
3823 { /* IQ Express D4 */
3824 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3825 PCI_VENDOR_ID_MAINPINE, 0x3400,
3826 0, 0, pbn_b0_4_115200 },
3827 { /* IQ Express F4 */
3828 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3829 PCI_VENDOR_ID_MAINPINE, 0x3500,
3830 0, 0, pbn_b0_4_115200 },
3831 { /* IQ Express D8 */
3832 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3833 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3834 0, 0, pbn_b0_8_115200 },
3835 { /* IQ Express F8 */
3836 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3837 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3838 0, 0, pbn_b0_8_115200 },
3839
3840
aa798505
OJ		 3841 /*
3842 * PA Semi PA6T-1682M on-chip UART
3843 */
3844 { PCI_VENDOR_ID_PASEMI, 0xa004,
3845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3846 pbn_pasemi_1682M },
3847
46a0fac9
SB		 3848 /*
3849 * National Instruments
3850 */
04bf7e74
WP		 3851 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3852 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3853 pbn_b1_16_115200 },
3854 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3855 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3856 pbn_b1_8_115200 },
3857 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3858 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3859 pbn_b1_bt_4_115200 },
3860 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3861 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3862 pbn_b1_bt_2_115200 },
3863 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3864 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3865 pbn_b1_bt_4_115200 },
3866 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3867 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3868 pbn_b1_bt_2_115200 },
3869 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3870 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3871 pbn_b1_16_115200 },
3872 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3873 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3874 pbn_b1_8_115200 },
3875 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3876 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3877 pbn_b1_bt_4_115200 },
3878 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3879 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3880 pbn_b1_bt_2_115200 },
3881 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3882 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3883 pbn_b1_bt_4_115200 },
3884 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3885 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3886 pbn_b1_bt_2_115200 },
46a0fac9
SB		 3887 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3888 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3889 pbn_ni8430_2 },
3890 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3891 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3892 pbn_ni8430_2 },
3893 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3894 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3895 pbn_ni8430_4 },
3896 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3897 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3898 pbn_ni8430_4 },
3899 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3900 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3901 pbn_ni8430_8 },
3902 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3903 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3904 pbn_ni8430_8 },
3905 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3906 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3907 pbn_ni8430_16 },
3908 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3909 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3910 pbn_ni8430_16 },
3911 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3912 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3913 pbn_ni8430_2 },
3914 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3915 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3916 pbn_ni8430_2 },
3917 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3918 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3919 pbn_ni8430_4 },
3920 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3921 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3922 pbn_ni8430_4 },
3923
02c9b5cf
KJ		 3924 /*
3925 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3926 */
3927 { PCI_VENDOR_ID_ADDIDATA,
3928 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3929 PCI_ANY_ID,
3930 PCI_ANY_ID,
3931 0,
3932 0,
3933 pbn_b0_4_115200 },
3934
3935 { PCI_VENDOR_ID_ADDIDATA,
3936 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3937 PCI_ANY_ID,
3938 PCI_ANY_ID,
3939 0,
3940 0,
3941 pbn_b0_2_115200 },
3942
3943 { PCI_VENDOR_ID_ADDIDATA,
3944 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3945 PCI_ANY_ID,
3946 PCI_ANY_ID,
3947 0,
3948 0,
3949 pbn_b0_1_115200 },
3950
3951 { PCI_VENDOR_ID_ADDIDATA_OLD,
3952 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3953 PCI_ANY_ID,
3954 PCI_ANY_ID,
3955 0,
3956 0,
3957 pbn_b1_8_115200 },
3958
3959 { PCI_VENDOR_ID_ADDIDATA,
3960 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3961 PCI_ANY_ID,
3962 PCI_ANY_ID,
3963 0,
3964 0,
3965 pbn_b0_4_115200 },
3966
3967 { PCI_VENDOR_ID_ADDIDATA,
3968 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3969 PCI_ANY_ID,
3970 PCI_ANY_ID,
3971 0,
3972 0,
3973 pbn_b0_2_115200 },
3974
3975 { PCI_VENDOR_ID_ADDIDATA,
3976 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3977 PCI_ANY_ID,
3978 PCI_ANY_ID,
3979 0,
3980 0,
3981 pbn_b0_1_115200 },
3982
3983 { PCI_VENDOR_ID_ADDIDATA,
3984 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3985 PCI_ANY_ID,
3986 PCI_ANY_ID,
3987 0,
3988 0,
3989 pbn_b0_4_115200 },
3990
3991 { PCI_VENDOR_ID_ADDIDATA,
3992 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3993 PCI_ANY_ID,
3994 PCI_ANY_ID,
3995 0,
3996 0,
3997 pbn_b0_2_115200 },
3998
3999 { PCI_VENDOR_ID_ADDIDATA,
4000 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4001 PCI_ANY_ID,
4002 PCI_ANY_ID,
4003 0,
4004 0,
4005 pbn_b0_1_115200 },
4006
4007 { PCI_VENDOR_ID_ADDIDATA,
4008 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4009 PCI_ANY_ID,
4010 PCI_ANY_ID,
4011 0,
4012 0,
4013 pbn_b0_8_115200 },
4014
1b62cbf2
KJ		 4015 { PCI_VENDOR_ID_ADDIDATA,
4016 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4017 PCI_ANY_ID,
4018 PCI_ANY_ID,
4019 0,
4020 0,
4021 pbn_ADDIDATA_PCIe_4_3906250 },
4022
4023 { PCI_VENDOR_ID_ADDIDATA,
4024 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4025 PCI_ANY_ID,
4026 PCI_ANY_ID,
4027 0,
4028 0,
4029 pbn_ADDIDATA_PCIe_2_3906250 },
4030
4031 { PCI_VENDOR_ID_ADDIDATA,
4032 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4033 PCI_ANY_ID,
4034 PCI_ANY_ID,
4035 0,
4036 0,
4037 pbn_ADDIDATA_PCIe_1_3906250 },
4038
4039 { PCI_VENDOR_ID_ADDIDATA,
4040 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4041 PCI_ANY_ID,
4042 PCI_ANY_ID,
4043 0,
4044 0,
4045 pbn_ADDIDATA_PCIe_8_3906250 },
4046
25cf9bc1
JS		 4047 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4048 PCI_VENDOR_ID_IBM, 0x0299,
4049 0, 0, pbn_b0_bt_2_115200 },
4050
c4285b47
MB		 4051 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4052 0xA000, 0x1000,
4053 0, 0, pbn_b0_1_115200 },
4054
7808edcd
NG		 4055 /* the 9901 is a rebranded 9912 */
4056 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4057 0xA000, 0x1000,
4058 0, 0, pbn_b0_1_115200 },
4059
4060 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4061 0xA000, 0x1000,
4062 0, 0, pbn_b0_1_115200 },
4063
4064 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4065 0xA000, 0x1000,
4066 0, 0, pbn_b0_1_115200 },
4067
4068 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4069 0xA000, 0x1000,
4070 0, 0, pbn_b0_1_115200 },
4071
4072 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4073 0xA000, 0x3002,
4074 0, 0, pbn_NETMOS9900_2s_115200 },
4075
ac6ec5b1 4076 /*
44178176 4077 * Best Connectivity and Rosewill PCI Multi I/O cards
ac6ec5b1
IS		 4078 */
4079
4080 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4081 0xA000, 0x1000,
4082 0, 0, pbn_b0_1_115200 },
4083
44178176
ES		 4084 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4085 0xA000, 0x3002,
4086 0, 0, pbn_b0_bt_2_115200 },
4087
ac6ec5b1
IS		 4088 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4089 0xA000, 0x3004,
4090 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 4091 /* Intel CE4100 */
4092 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4094 pbn_ce4100_1_115200 },
4095
d9a0fbfd
AP		 4096 /*
4097 * Cronyx Omega PCI
4098 */
4099 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4100 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4101 pbn_omegapci },
ac6ec5b1 4102
1da177e4
LT		 4103 /*
4104 * These entries match devices with class COMMUNICATION_SERIAL,
4105 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4106 */
4107 { PCI_ANY_ID, PCI_ANY_ID,
4108 PCI_ANY_ID, PCI_ANY_ID,
4109 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4110 0xffff00, pbn_default },
4111 { PCI_ANY_ID, PCI_ANY_ID,
4112 PCI_ANY_ID, PCI_ANY_ID,
4113 PCI_CLASS_COMMUNICATION_MODEM << 8,
4114 0xffff00, pbn_default },
4115 { PCI_ANY_ID, PCI_ANY_ID,
4116 PCI_ANY_ID, PCI_ANY_ID,
4117 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4118 0xffff00, pbn_default },
4119 { 0, }
4120};
4121
2807190b
MR		 4122static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4123 pci_channel_state_t state)
4124{
4125 struct serial_private *priv = pci_get_drvdata(dev);
4126
4127 if (state == pci_channel_io_perm_failure)
4128 return PCI_ERS_RESULT_DISCONNECT;
4129
4130 if (priv)
4131 pciserial_suspend_ports(priv);
4132
4133 pci_disable_device(dev);
4134
4135 return PCI_ERS_RESULT_NEED_RESET;
4136}
4137
4138static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4139{
4140 int rc;
4141
4142 rc = pci_enable_device(dev);
4143
4144 if (rc)
4145 return PCI_ERS_RESULT_DISCONNECT;
4146
4147 pci_restore_state(dev);
4148 pci_save_state(dev);
4149
4150 return PCI_ERS_RESULT_RECOVERED;
4151}
4152
4153static void serial8250_io_resume(struct pci_dev *dev)
4154{
4155 struct serial_private *priv = pci_get_drvdata(dev);
4156
4157 if (priv)
4158 pciserial_resume_ports(priv);
4159}
4160
4161static struct pci_error_handlers serial8250_err_handler = {
4162 .error_detected = serial8250_io_error_detected,
4163 .slot_reset = serial8250_io_slot_reset,
4164 .resume = serial8250_io_resume,
4165};
4166
1da177e4
LT		 4167static struct pci_driver serial_pci_driver = {
4168 .name = "serial",
4169 .probe = pciserial_init_one,
4170 .remove = __devexit_p(pciserial_remove_one),
1d5e7996 4171#ifdef CONFIG_PM
1da177e4
LT		 4172 .suspend = pciserial_suspend_one,
4173 .resume = pciserial_resume_one,
1d5e7996 4174#endif
1da177e4 4175 .id_table = serial_pci_tbl,
2807190b 4176 .err_handler = &serial8250_err_handler,
1da177e4
LT		 4177};
4178
4179static int __init serial8250_pci_init(void)
4180{
4181 return pci_register_driver(&serial_pci_driver);
4182}
4183
4184static void __exit serial8250_pci_exit(void)
4185{
4186 pci_unregister_driver(&serial_pci_driver);
4187}
4188
4189module_init(serial8250_pci_init);
4190module_exit(serial8250_pci_exit);
4191
4192MODULE_LICENSE("GPL");
4193MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4194MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux kernel - Deliverables
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