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n_tty: Fix poll() when TIME_CHAR and MIN_CHAR == 0
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4 11 */
af8c5b8d 12#undef DEBUG
1da177e4 13#include <linux/module.h>
1da177e4 14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
0ad372b9 20#include <linux/serial_reg.h>
1da177e4
LT		 21#include <linux/serial_core.h>
22#include <linux/8250_pci.h>
23#include <linux/bitops.h>
24
25#include <asm/byteorder.h>
26#include <asm/io.h>
27
28#include "8250.h"
29
1da177e4
LT		 30/*
31 * init function returns:
32 * > 0 - number of ports
33 * = 0 - use board->num_ports
34 * < 0 - error
35 */
36struct pci_serial_quirk {
37 u32 vendor;
38 u32 device;
39 u32 subvendor;
40 u32 subdevice;
5bf8f501 41 int (*probe)(struct pci_dev *dev);
1da177e4 42 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 43 int (*setup)(struct serial_private *,
44 const struct pciserial_board *,
2655a2c7 45 struct uart_8250_port *, int);
1da177e4
LT		 46 void (*exit)(struct pci_dev *dev);
47};
48
49#define PCI_NUM_BAR_RESOURCES 6
50
51struct serial_private {
70db3d91 52 struct pci_dev *dev;
1da177e4
LT		 53 unsigned int nr;
54 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
55 struct pci_serial_quirk *quirk;
56 int line[0];
57};
58
7808edcd 59static int pci_default_setup(struct serial_private*,
2655a2c7 60 const struct pciserial_board*, struct uart_8250_port *, int);
7808edcd 61
1da177e4
LT		 62static void moan_device(const char *str, struct pci_dev *dev)
63{
af8c5b8d 64 dev_err(&dev->dev,
ad361c98
JP		 65 "%s: %s\n"
66 "Please send the output of lspci -vv, this\n"
67 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 "manufacturer and name of serial board or\n"
69 "modem board to rmk+serial@arm.linux.org.uk.\n",
1da177e4
LT		 70 pci_name(dev), str, dev->vendor, dev->device,
71 dev->subsystem_vendor, dev->subsystem_device);
72}
73
74static int
2655a2c7 75setup_port(struct serial_private *priv, struct uart_8250_port *port,
1da177e4
LT		 76 int bar, int offset, int regshift)
77{
70db3d91 78 struct pci_dev *dev = priv->dev;
1da177e4
LT		 79 unsigned long base, len;
80
81 if (bar >= PCI_NUM_BAR_RESOURCES)
82 return -EINVAL;
83
72ce9a83
RK		 84 base = pci_resource_start(dev, bar);
85
1da177e4 86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 87 len = pci_resource_len(dev, bar);
88
89 if (!priv->remapped_bar[bar])
6f441fe9 90 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 91 if (!priv->remapped_bar[bar])
92 return -ENOMEM;
93
2655a2c7
AC		 94 port->port.iotype = UPIO_MEM;
95 port->port.iobase = 0;
96 port->port.mapbase = base + offset;
97 port->port.membase = priv->remapped_bar[bar] + offset;
98 port->port.regshift = regshift;
1da177e4 99 } else {
2655a2c7
AC		 100 port->port.iotype = UPIO_PORT;
101 port->port.iobase = base + offset;
102 port->port.mapbase = 0;
103 port->port.membase = NULL;
104 port->port.regshift = 0;
1da177e4
LT		 105 }
106 return 0;
107}
108
02c9b5cf
KJ		 109/*
110 * ADDI-DATA GmbH communication cards <info@addi-data.com>
111 */
112static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 113 const struct pciserial_board *board,
2655a2c7 114 struct uart_8250_port *port, int idx)
02c9b5cf
KJ		 115{
116 unsigned int bar = 0, offset = board->first_offset;
117 bar = FL_GET_BASE(board->flags);
118
119 if (idx < 2) {
120 offset += idx * board->uart_offset;
121 } else if ((idx >= 2) && (idx < 4)) {
122 bar += 1;
123 offset += ((idx - 2) * board->uart_offset);
124 } else if ((idx >= 4) && (idx < 6)) {
125 bar += 2;
126 offset += ((idx - 4) * board->uart_offset);
127 } else if (idx >= 6) {
128 bar += 3;
129 offset += ((idx - 6) * board->uart_offset);
130 }
131
132 return setup_port(priv, port, bar, offset, board->reg_shift);
133}
134
1da177e4
LT		 135/*
136 * AFAVLAB uses a different mixture of BARs and offsets
137 * Not that ugly ;) -- HW
138 */
139static int
975a1a7d 140afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 141 struct uart_8250_port *port, int idx)
1da177e4
LT		 142{
143 unsigned int bar, offset = board->first_offset;
5756ee99 144
1da177e4
LT		 145 bar = FL_GET_BASE(board->flags);
146 if (idx < 4)
147 bar += idx;
148 else {
149 bar = 4;
150 offset += (idx - 4) * board->uart_offset;
151 }
152
70db3d91 153 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 154}
155
156/*
157 * HP's Remote Management Console. The Diva chip came in several
158 * different versions. N-class, L2000 and A500 have two Diva chips, each
159 * with 3 UARTs (the third UART on the second chip is unused). Superdome
160 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
161 * one Diva chip, but it has been expanded to 5 UARTs.
162 */
61a116ef 163static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 164{
165 int rc = 0;
166
167 switch (dev->subsystem_device) {
168 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
169 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
170 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
171 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
172 rc = 3;
173 break;
174 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
175 rc = 2;
176 break;
177 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
178 rc = 4;
179 break;
180 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 181 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 182 rc = 1;
183 break;
184 }
185
186 return rc;
187}
188
189/*
190 * HP's Diva chip puts the 4th/5th serial port further out, and
191 * some serial ports are supposed to be hidden on certain models.
192 */
193static int
975a1a7d
RK		 194pci_hp_diva_setup(struct serial_private *priv,
195 const struct pciserial_board *board,
2655a2c7 196 struct uart_8250_port *port, int idx)
1da177e4
LT		 197{
198 unsigned int offset = board->first_offset;
199 unsigned int bar = FL_GET_BASE(board->flags);
200
70db3d91 201 switch (priv->dev->subsystem_device) {
1da177e4
LT		 202 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
203 if (idx == 3)
204 idx++;
205 break;
206 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
207 if (idx > 0)
208 idx++;
209 if (idx > 2)
210 idx++;
211 break;
212 }
213 if (idx > 2)
214 offset = 0x18;
215
216 offset += idx * board->uart_offset;
217
70db3d91 218 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 219}
220
221/*
222 * Added for EKF Intel i960 serial boards
223 */
61a116ef 224static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 225{
226 unsigned long oldval;
227
228 if (!(dev->subsystem_device & 0x1000))
229 return -ENODEV;
230
231 /* is firmware started? */
5756ee99
AC		 232 pci_read_config_dword(dev, 0x44, (void *)&oldval);
233 if (oldval == 0x00001000L) { /* RESET value */
af8c5b8d 234 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
1da177e4
LT		 235 return -ENODEV;
236 }
237 return 0;
238}
239
240/*
241 * Some PCI serial cards using the PLX 9050 PCI interface chip require
242 * that the card interrupt be explicitly enabled or disabled. This
243 * seems to be mainly needed on card using the PLX which also use I/O
244 * mapped memory.
245 */
61a116ef 246static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 247{
248 u8 irq_config;
249 void __iomem *p;
250
251 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
252 moan_device("no memory in bar 0", dev);
253 return 0;
254 }
255
256 irq_config = 0x41;
add7b58e 257 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 258 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 259 irq_config = 0x43;
5756ee99 260
1da177e4 261 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 262 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 263 /*
264 * As the megawolf cards have the int pins active
265 * high, and have 2 UART chips, both ints must be
266 * enabled on the 9050. Also, the UARTS are set in
267 * 16450 mode by default, so we have to enable the
268 * 16C950 'enhanced' mode so that we can use the
269 * deep FIFOs
270 */
271 irq_config = 0x5b;
1da177e4
LT		 272 /*
273 * enable/disable interrupts
274 */
6f441fe9 275 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 276 if (p == NULL)
277 return -ENOMEM;
278 writel(irq_config, p + 0x4c);
279
280 /*
281 * Read the register back to ensure that it took effect.
282 */
283 readl(p + 0x4c);
284 iounmap(p);
285
286 return 0;
287}
288
ae8d8a14 289static void pci_plx9050_exit(struct pci_dev *dev)
1da177e4
LT		 290{
291 u8 __iomem *p;
292
293 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
294 return;
295
296 /*
297 * disable interrupts
298 */
6f441fe9 299 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 300 if (p != NULL) {
301 writel(0, p + 0x4c);
302
303 /*
304 * Read the register back to ensure that it took effect.
305 */
306 readl(p + 0x4c);
307 iounmap(p);
308 }
309}
310
04bf7e74
WP		 311#define NI8420_INT_ENABLE_REG 0x38
312#define NI8420_INT_ENABLE_BIT 0x2000
313
ae8d8a14 314static void pci_ni8420_exit(struct pci_dev *dev)
04bf7e74
WP		 315{
316 void __iomem *p;
317 unsigned long base, len;
318 unsigned int bar = 0;
319
320 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
321 moan_device("no memory in bar", dev);
322 return;
323 }
324
325 base = pci_resource_start(dev, bar);
326 len = pci_resource_len(dev, bar);
327 p = ioremap_nocache(base, len);
328 if (p == NULL)
329 return;
330
331 /* Disable the CPU Interrupt */
332 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
333 p + NI8420_INT_ENABLE_REG);
334 iounmap(p);
335}
336
337
46a0fac9
SB		 338/* MITE registers */
339#define MITE_IOWBSR1 0xc4
340#define MITE_IOWCR1 0xf4
341#define MITE_LCIMR1 0x08
342#define MITE_LCIMR2 0x10
343
344#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
345
ae8d8a14 346static void pci_ni8430_exit(struct pci_dev *dev)
46a0fac9
SB		 347{
348 void __iomem *p;
349 unsigned long base, len;
350 unsigned int bar = 0;
351
352 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
353 moan_device("no memory in bar", dev);
354 return;
355 }
356
357 base = pci_resource_start(dev, bar);
358 len = pci_resource_len(dev, bar);
359 p = ioremap_nocache(base, len);
360 if (p == NULL)
361 return;
362
363 /* Disable the CPU Interrupt */
364 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
365 iounmap(p);
366}
367
1da177e4
LT		 368/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
369static int
975a1a7d 370sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 371 struct uart_8250_port *port, int idx)
1da177e4
LT		 372{
373 unsigned int bar, offset = board->first_offset;
374
375 bar = 0;
376
377 if (idx < 4) {
378 /* first four channels map to 0, 0x100, 0x200, 0x300 */
379 offset += idx * board->uart_offset;
380 } else if (idx < 8) {
381 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
382 offset += idx * board->uart_offset + 0xC00;
383 } else /* we have only 8 ports on PMC-OCTALPRO */
384 return 1;
385
70db3d91 386 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 387}
388
389/*
390* This does initialization for PMC OCTALPRO cards:
391* maps the device memory, resets the UARTs (needed, bc
392* if the module is removed and inserted again, the card
393* is in the sleep mode) and enables global interrupt.
394*/
395
396/* global control register offset for SBS PMC-OctalPro */
397#define OCT_REG_CR_OFF 0x500
398
61a116ef 399static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 400{
401 u8 __iomem *p;
402
24ed3aba 403 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 404
405 if (p == NULL)
406 return -ENOMEM;
407 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 408 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 409 udelay(50);
5756ee99 410 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 411
412 /* Set bit-2 (INTENABLE) of Control Register */
413 writeb(0x4, p + OCT_REG_CR_OFF);
414 iounmap(p);
415
416 return 0;
417}
418
419/*
420 * Disables the global interrupt of PMC-OctalPro
421 */
422
ae8d8a14 423static void sbs_exit(struct pci_dev *dev)
1da177e4
LT		 424{
425 u8 __iomem *p;
426
24ed3aba 427 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 428 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
429 if (p != NULL)
1da177e4 430 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 431 iounmap(p);
432}
433
434/*
435 * SIIG serial cards have an PCI interface chip which also controls
436 * the UART clocking frequency. Each UART can be clocked independently
25985edc 437 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 438 * are stored in the EEPROM chip. It can cause problems because this
439 * version of serial driver doesn't support differently clocked UART's
440 * on single PCI card. To prevent this, initialization functions set
441 * high frequency clocking for all UART's on given card. It is safe (I
442 * hope) because it doesn't touch EEPROM settings to prevent conflicts
443 * with other OSes (like M$ DOS).
444 *
445 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 446 *
1da177e4
LT		 447 * There is two family of SIIG serial cards with different PCI
448 * interface chip and different configuration methods:
449 * - 10x cards have control registers in IO and/or memory space;
450 * - 20x cards have control registers in standard PCI configuration space.
451 *
67d74b87
RK		 452 * Note: all 10x cards have PCI device ids 0x10..
453 * all 20x cards have PCI device ids 0x20..
454 *
fbc0dc0d
AP		 455 * There are also Quartet Serial cards which use Oxford Semiconductor
456 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
457 *
1da177e4
LT		 458 * Note: some SIIG cards are probed by the parport_serial object.
459 */
460
461#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
462#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
463
464static int pci_siig10x_init(struct pci_dev *dev)
465{
466 u16 data;
467 void __iomem *p;
468
469 switch (dev->device & 0xfff8) {
470 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
471 data = 0xffdf;
472 break;
473 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
474 data = 0xf7ff;
475 break;
476 default: /* 1S1P, 4S */
477 data = 0xfffb;
478 break;
479 }
480
6f441fe9 481 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 482 if (p == NULL)
483 return -ENOMEM;
484
485 writew(readw(p + 0x28) & data, p + 0x28);
486 readw(p + 0x28);
487 iounmap(p);
488 return 0;
489}
490
491#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
492#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
493
494static int pci_siig20x_init(struct pci_dev *dev)
495{
496 u8 data;
497
498 /* Change clock frequency for the first UART. */
499 pci_read_config_byte(dev, 0x6f, &data);
500 pci_write_config_byte(dev, 0x6f, data & 0xef);
501
502 /* If this card has 2 UART, we have to do the same with second UART. */
503 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
504 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
505 pci_read_config_byte(dev, 0x73, &data);
506 pci_write_config_byte(dev, 0x73, data & 0xef);
507 }
508 return 0;
509}
510
67d74b87
RK		 511static int pci_siig_init(struct pci_dev *dev)
512{
513 unsigned int type = dev->device & 0xff00;
514
515 if (type == 0x1000)
516 return pci_siig10x_init(dev);
517 else if (type == 0x2000)
518 return pci_siig20x_init(dev);
519
520 moan_device("Unknown SIIG card", dev);
521 return -ENODEV;
522}
523
3ec9c594 524static int pci_siig_setup(struct serial_private *priv,
975a1a7d 525 const struct pciserial_board *board,
2655a2c7 526 struct uart_8250_port *port, int idx)
3ec9c594
AP		 527{
528 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
529
530 if (idx > 3) {
531 bar = 4;
532 offset = (idx - 4) * 8;
533 }
534
535 return setup_port(priv, port, bar, offset, 0);
536}
537
1da177e4
LT		 538/*
539 * Timedia has an explosion of boards, and to avoid the PCI table from
540 * growing *huge*, we use this function to collapse some 70 entries
541 * in the PCI table into one, for sanity's and compactness's sake.
542 */
e9422e09 543static const unsigned short timedia_single_port[] = {
1da177e4
LT		 544 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
545};
546
e9422e09 547static const unsigned short timedia_dual_port[] = {
1da177e4 548 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 549 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
550 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 551 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
552 0xD079, 0
553};
554
e9422e09 555static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 556 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
557 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 558 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
559 0xB157, 0
560};
561
e9422e09 562static const unsigned short timedia_eight_port[] = {
5756ee99 563 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 564 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
565};
566
cb3592be 567static const struct timedia_struct {
1da177e4 568 int num;
e9422e09 569 const unsigned short *ids;
1da177e4
LT		 570} timedia_data[] = {
571 { 1, timedia_single_port },
572 { 2, timedia_dual_port },
573 { 4, timedia_quad_port },
e9422e09 574 { 8, timedia_eight_port }
1da177e4
LT		 575};
576
b9b24558
FB		 577/*
578 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
579 * listing them individually, this driver merely grabs them all with
580 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
581 * and should be left free to be claimed by parport_serial instead.
582 */
583static int pci_timedia_probe(struct pci_dev *dev)
584{
585 /*
586 * Check the third digit of the subdevice ID
587 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
588 */
589 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
590 dev_info(&dev->dev,
591 "ignoring Timedia subdevice %04x for parport_serial\n",
592 dev->subsystem_device);
593 return -ENODEV;
594 }
595
596 return 0;
597}
598
61a116ef 599static int pci_timedia_init(struct pci_dev *dev)
1da177e4 600{
e9422e09 601 const unsigned short *ids;
1da177e4
LT		 602 int i, j;
603
e9422e09 604 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 605 ids = timedia_data[i].ids;
606 for (j = 0; ids[j]; j++)
607 if (dev->subsystem_device == ids[j])
608 return timedia_data[i].num;
609 }
610 return 0;
611}
612
613/*
614 * Timedia/SUNIX uses a mixture of BARs and offsets
615 * Ugh, this is ugly as all hell --- TYT
616 */
617static int
975a1a7d
RK		 618pci_timedia_setup(struct serial_private *priv,
619 const struct pciserial_board *board,
2655a2c7 620 struct uart_8250_port *port, int idx)
1da177e4
LT		 621{
622 unsigned int bar = 0, offset = board->first_offset;
623
624 switch (idx) {
625 case 0:
626 bar = 0;
627 break;
628 case 1:
629 offset = board->uart_offset;
630 bar = 0;
631 break;
632 case 2:
633 bar = 1;
634 break;
635 case 3:
636 offset = board->uart_offset;
c2cd6d3c 637 /* FALLTHROUGH */
1da177e4
LT		 638 case 4: /* BAR 2 */
639 case 5: /* BAR 3 */
640 case 6: /* BAR 4 */
641 case 7: /* BAR 5 */
642 bar = idx - 2;
643 }
644
70db3d91 645 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 646}
647
648/*
649 * Some Titan cards are also a little weird
650 */
651static int
70db3d91 652titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 653 const struct pciserial_board *board,
2655a2c7 654 struct uart_8250_port *port, int idx)
1da177e4
LT		 655{
656 unsigned int bar, offset = board->first_offset;
657
658 switch (idx) {
659 case 0:
660 bar = 1;
661 break;
662 case 1:
663 bar = 2;
664 break;
665 default:
666 bar = 4;
667 offset = (idx - 2) * board->uart_offset;
668 }
669
70db3d91 670 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 671}
672
61a116ef 673static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 674{
675 msleep(100);
676 return 0;
677}
678
04bf7e74
WP		 679static int pci_ni8420_init(struct pci_dev *dev)
680{
681 void __iomem *p;
682 unsigned long base, len;
683 unsigned int bar = 0;
684
685 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
686 moan_device("no memory in bar", dev);
687 return 0;
688 }
689
690 base = pci_resource_start(dev, bar);
691 len = pci_resource_len(dev, bar);
692 p = ioremap_nocache(base, len);
693 if (p == NULL)
694 return -ENOMEM;
695
696 /* Enable CPU Interrupt */
697 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
698 p + NI8420_INT_ENABLE_REG);
699
700 iounmap(p);
701 return 0;
702}
703
46a0fac9
SB		 704#define MITE_IOWBSR1_WSIZE 0xa
705#define MITE_IOWBSR1_WIN_OFFSET 0x800
706#define MITE_IOWBSR1_WENAB (1 << 7)
707#define MITE_LCIMR1_IO_IE_0 (1 << 24)
708#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
709#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
710
711static int pci_ni8430_init(struct pci_dev *dev)
712{
713 void __iomem *p;
714 unsigned long base, len;
715 u32 device_window;
716 unsigned int bar = 0;
717
718 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
719 moan_device("no memory in bar", dev);
720 return 0;
721 }
722
723 base = pci_resource_start(dev, bar);
724 len = pci_resource_len(dev, bar);
725 p = ioremap_nocache(base, len);
726 if (p == NULL)
727 return -ENOMEM;
728
729 /* Set device window address and size in BAR0 */
730 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
731 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
732 writel(device_window, p + MITE_IOWBSR1);
733
734 /* Set window access to go to RAMSEL IO address space */
735 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
736 p + MITE_IOWCR1);
737
738 /* Enable IO Bus Interrupt 0 */
739 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
740
741 /* Enable CPU Interrupt */
742 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
743
744 iounmap(p);
745 return 0;
746}
747
748/* UART Port Control Register */
749#define NI8430_PORTCON 0x0f
750#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
751
752static int
bf538fe4
AC		 753pci_ni8430_setup(struct serial_private *priv,
754 const struct pciserial_board *board,
2655a2c7 755 struct uart_8250_port *port, int idx)
46a0fac9
SB		 756{
757 void __iomem *p;
758 unsigned long base, len;
759 unsigned int bar, offset = board->first_offset;
760
761 if (idx >= board->num_ports)
762 return 1;
763
764 bar = FL_GET_BASE(board->flags);
765 offset += idx * board->uart_offset;
766
767 base = pci_resource_start(priv->dev, bar);
768 len = pci_resource_len(priv->dev, bar);
769 p = ioremap_nocache(base, len);
770
7c9d440e 771 /* enable the transceiver */
46a0fac9
SB		 772 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
773 p + offset + NI8430_PORTCON);
774
775 iounmap(p);
776
777 return setup_port(priv, port, bar, offset, board->reg_shift);
778}
779
7808edcd
NG		 780static int pci_netmos_9900_setup(struct serial_private *priv,
781 const struct pciserial_board *board,
2655a2c7 782 struct uart_8250_port *port, int idx)
7808edcd
NG		 783{
784 unsigned int bar;
785
786 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
787 /* netmos apparently orders BARs by datasheet layout, so serial
788 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
789 */
790 bar = 3 * idx;
791
792 return setup_port(priv, port, bar, 0, board->reg_shift);
793 } else {
794 return pci_default_setup(priv, board, port, idx);
795 }
796}
797
798/* the 99xx series comes with a range of device IDs and a variety
799 * of capabilities:
800 *
801 * 9900 has varying capabilities and can cascade to sub-controllers
802 * (cascading should be purely internal)
803 * 9904 is hardwired with 4 serial ports
804 * 9912 and 9922 are hardwired with 2 serial ports
805 */
806static int pci_netmos_9900_numports(struct pci_dev *dev)
807{
808 unsigned int c = dev->class;
809 unsigned int pi;
810 unsigned short sub_serports;
811
812 pi = (c & 0xff);
813
814 if (pi == 2) {
815 return 1;
816 } else if ((pi == 0) &&
817 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
818 /* two possibilities: 0x30ps encodes number of parallel and
819 * serial ports, or 0x1000 indicates *something*. This is not
820 * immediately obvious, since the 2s1p+4s configuration seems
821 * to offer all functionality on functions 0..2, while still
822 * advertising the same function 3 as the 4s+2s1p config.
823 */
824 sub_serports = dev->subsystem_device & 0xf;
825 if (sub_serports > 0) {
826 return sub_serports;
827 } else {
af8c5b8d 828 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
7808edcd
NG		 829 return 0;
830 }
831 }
832
833 moan_device("unknown NetMos/Mostech program interface", dev);
834 return 0;
835}
46a0fac9 836
61a116ef 837static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 838{
839 /* subdevice 0x00PS means <P> parallel, <S> serial */
840 unsigned int num_serial = dev->subsystem_device & 0xf;
841
ac6ec5b1
IS		 842 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
843 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 844 return 0;
7808edcd 845
25cf9bc1
JS		 846 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
847 dev->subsystem_device == 0x0299)
848 return 0;
849
7808edcd
NG		 850 switch (dev->device) { /* FALLTHROUGH on all */
851 case PCI_DEVICE_ID_NETMOS_9904:
852 case PCI_DEVICE_ID_NETMOS_9912:
853 case PCI_DEVICE_ID_NETMOS_9922:
854 case PCI_DEVICE_ID_NETMOS_9900:
855 num_serial = pci_netmos_9900_numports(dev);
856 break;
857
858 default:
859 if (num_serial == 0 ) {
860 moan_device("unknown NetMos/Mostech device", dev);
861 }
862 }
863
1da177e4
LT		 864 if (num_serial == 0)
865 return -ENODEV;
7808edcd 866
1da177e4
LT		 867 return num_serial;
868}
869
84f8c6fc 870/*
84f8c6fc
NV		 871 * These chips are available with optionally one parallel port and up to
872 * two serial ports. Unfortunately they all have the same product id.
873 *
874 * Basic configuration is done over a region of 32 I/O ports. The base
875 * ioport is called INTA or INTC, depending on docs/other drivers.
876 *
877 * The region of the 32 I/O ports is configured in POSIO0R...
878 */
879
880/* registers */
881#define ITE_887x_MISCR 0x9c
882#define ITE_887x_INTCBAR 0x78
883#define ITE_887x_UARTBAR 0x7c
884#define ITE_887x_PS0BAR 0x10
885#define ITE_887x_POSIO0 0x60
886
887/* I/O space size */
888#define ITE_887x_IOSIZE 32
889/* I/O space size (bits 26-24; 8 bytes = 011b) */
890#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
891/* I/O space size (bits 26-24; 32 bytes = 101b) */
892#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
893/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
894#define ITE_887x_POSIO_SPEED (3 << 29)
895/* enable IO_Space bit */
896#define ITE_887x_POSIO_ENABLE (1 << 31)
897
f79abb82 898static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 899{
900 /* inta_addr are the configuration addresses of the ITE */
901 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
902 0x200, 0x280, 0 };
903 int ret, i, type;
904 struct resource *iobase = NULL;
905 u32 miscr, uartbar, ioport;
906
907 /* search for the base-ioport */
908 i = 0;
909 while (inta_addr[i] && iobase == NULL) {
910 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
911 "ite887x");
912 if (iobase != NULL) {
913 /* write POSIO0R - speed | size | ioport */
914 pci_write_config_dword(dev, ITE_887x_POSIO0,
915 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
916 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
917 /* write INTCBAR - ioport */
5756ee99
AC		 918 pci_write_config_dword(dev, ITE_887x_INTCBAR,
919 inta_addr[i]);
84f8c6fc
NV		 920 ret = inb(inta_addr[i]);
921 if (ret != 0xff) {
922 /* ioport connected */
923 break;
924 }
925 release_region(iobase->start, ITE_887x_IOSIZE);
926 iobase = NULL;
927 }
928 i++;
929 }
930
931 if (!inta_addr[i]) {
af8c5b8d 932 dev_err(&dev->dev, "ite887x: could not find iobase\n");
84f8c6fc
NV		 933 return -ENODEV;
934 }
935
936 /* start of undocumented type checking (see parport_pc.c) */
937 type = inb(iobase->start + 0x18) & 0x0f;
938
939 switch (type) {
940 case 0x2: /* ITE8871 (1P) */
941 case 0xa: /* ITE8875 (1P) */
942 ret = 0;
943 break;
944 case 0xe: /* ITE8872 (2S1P) */
945 ret = 2;
946 break;
947 case 0x6: /* ITE8873 (1S) */
948 ret = 1;
949 break;
950 case 0x8: /* ITE8874 (2S) */
951 ret = 2;
952 break;
953 default:
954 moan_device("Unknown ITE887x", dev);
955 ret = -ENODEV;
956 }
957
958 /* configure all serial ports */
959 for (i = 0; i < ret; i++) {
960 /* read the I/O port from the device */
961 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
962 &ioport);
963 ioport &= 0x0000FF00; /* the actual base address */
964 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
965 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
966 ITE_887x_POSIO_IOSIZE_8 | ioport);
967
968 /* write the ioport to the UARTBAR */
969 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
970 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
971 uartbar |= (ioport << (16 * i)); /* set the ioport */
972 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
973
974 /* get current config */
975 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
976 /* disable interrupts (UARTx_Routing[3:0]) */
977 miscr &= ~(0xf << (12 - 4 * i));
978 /* activate the UART (UARTx_En) */
979 miscr |= 1 << (23 - i);
980 /* write new config with activated UART */
981 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
982 }
983
984 if (ret <= 0) {
985 /* the device has no UARTs if we get here */
986 release_region(iobase->start, ITE_887x_IOSIZE);
987 }
988
989 return ret;
990}
991
ae8d8a14 992static void pci_ite887x_exit(struct pci_dev *dev)
84f8c6fc
NV		 993{
994 u32 ioport;
995 /* the ioport is bit 0-15 in POSIO0R */
996 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
997 ioport &= 0xffff;
998 release_region(ioport, ITE_887x_IOSIZE);
999}
1000
9f2a036a
RK		 1001/*
1002 * Oxford Semiconductor Inc.
1003 * Check that device is part of the Tornado range of devices, then determine
1004 * the number of ports available on the device.
1005 */
1006static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1007{
1008 u8 __iomem *p;
1009 unsigned long deviceID;
1010 unsigned int number_uarts = 0;
1011
1012 /* OxSemi Tornado devices are all 0xCxxx */
1013 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1014 (dev->device & 0xF000) != 0xC000)
1015 return 0;
1016
1017 p = pci_iomap(dev, 0, 5);
1018 if (p == NULL)
1019 return -ENOMEM;
1020
1021 deviceID = ioread32(p);
1022 /* Tornado device */
1023 if (deviceID == 0x07000200) {
1024 number_uarts = ioread8(p + 4);
af8c5b8d 1025 dev_dbg(&dev->dev,
9f2a036a 1026 "%d ports detected on Oxford PCI Express device\n",
af8c5b8d 1027 number_uarts);
9f2a036a
RK		 1028 }
1029 pci_iounmap(dev, p);
1030 return number_uarts;
1031}
1032
eb26dfe8
AC		 1033static int pci_asix_setup(struct serial_private *priv,
1034 const struct pciserial_board *board,
1035 struct uart_8250_port *port, int idx)
1036{
1037 port->bugs |= UART_BUG_PARITY;
1038 return pci_default_setup(priv, board, port, idx);
1039}
1040
55c7c0fd
AC		 1041/* Quatech devices have their own extra interface features */
1042
1043struct quatech_feature {
1044 u16 devid;
1045 bool amcc;
1046};
1047
1048#define QPCR_TEST_FOR1 0x3F
1049#define QPCR_TEST_GET1 0x00
1050#define QPCR_TEST_FOR2 0x40
1051#define QPCR_TEST_GET2 0x40
1052#define QPCR_TEST_FOR3 0x80
1053#define QPCR_TEST_GET3 0x40
1054#define QPCR_TEST_FOR4 0xC0
1055#define QPCR_TEST_GET4 0x80
1056
1057#define QOPR_CLOCK_X1 0x0000
1058#define QOPR_CLOCK_X2 0x0001
1059#define QOPR_CLOCK_X4 0x0002
1060#define QOPR_CLOCK_X8 0x0003
1061#define QOPR_CLOCK_RATE_MASK 0x0003
1062
1063
1064static struct quatech_feature quatech_cards[] = {
1065 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1066 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1067 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1068 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1069 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1070 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1071 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1072 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1073 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1074 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1075 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1076 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1077 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1078 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1079 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1080 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1081 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1082 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1083 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1084 { 0, }
1085};
1086
1087static int pci_quatech_amcc(u16 devid)
1088{
1089 struct quatech_feature *qf = &quatech_cards[0];
1090 while (qf->devid) {
1091 if (qf->devid == devid)
1092 return qf->amcc;
1093 qf++;
1094 }
1095 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1096 return 0;
1097};
1098
1099static int pci_quatech_rqopr(struct uart_8250_port *port)
1100{
1101 unsigned long base = port->port.iobase;
1102 u8 LCR, val;
1103
1104 LCR = inb(base + UART_LCR);
1105 outb(0xBF, base + UART_LCR);
1106 val = inb(base + UART_SCR);
1107 outb(LCR, base + UART_LCR);
1108 return val;
1109}
1110
1111static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1112{
1113 unsigned long base = port->port.iobase;
1114 u8 LCR, val;
1115
1116 LCR = inb(base + UART_LCR);
1117 outb(0xBF, base + UART_LCR);
1118 val = inb(base + UART_SCR);
1119 outb(qopr, base + UART_SCR);
1120 outb(LCR, base + UART_LCR);
1121}
1122
1123static int pci_quatech_rqmcr(struct uart_8250_port *port)
1124{
1125 unsigned long base = port->port.iobase;
1126 u8 LCR, val, qmcr;
1127
1128 LCR = inb(base + UART_LCR);
1129 outb(0xBF, base + UART_LCR);
1130 val = inb(base + UART_SCR);
1131 outb(val | 0x10, base + UART_SCR);
1132 qmcr = inb(base + UART_MCR);
1133 outb(val, base + UART_SCR);
1134 outb(LCR, base + UART_LCR);
1135
1136 return qmcr;
1137}
1138
1139static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1140{
1141 unsigned long base = port->port.iobase;
1142 u8 LCR, val;
1143
1144 LCR = inb(base + UART_LCR);
1145 outb(0xBF, base + UART_LCR);
1146 val = inb(base + UART_SCR);
1147 outb(val | 0x10, base + UART_SCR);
1148 outb(qmcr, base + UART_MCR);
1149 outb(val, base + UART_SCR);
1150 outb(LCR, base + UART_LCR);
1151}
1152
1153static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1154{
1155 unsigned long base = port->port.iobase;
1156 u8 LCR, val;
1157
1158 LCR = inb(base + UART_LCR);
1159 outb(0xBF, base + UART_LCR);
1160 val = inb(base + UART_SCR);
1161 if (val & 0x20) {
1162 outb(0x80, UART_LCR);
1163 if (!(inb(UART_SCR) & 0x20)) {
1164 outb(LCR, base + UART_LCR);
1165 return 1;
1166 }
1167 }
1168 return 0;
1169}
1170
1171static int pci_quatech_test(struct uart_8250_port *port)
1172{
1173 u8 reg;
1174 u8 qopr = pci_quatech_rqopr(port);
1175 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1176 reg = pci_quatech_rqopr(port) & 0xC0;
1177 if (reg != QPCR_TEST_GET1)
1178 return -EINVAL;
1179 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1180 reg = pci_quatech_rqopr(port) & 0xC0;
1181 if (reg != QPCR_TEST_GET2)
1182 return -EINVAL;
1183 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1184 reg = pci_quatech_rqopr(port) & 0xC0;
1185 if (reg != QPCR_TEST_GET3)
1186 return -EINVAL;
1187 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1188 reg = pci_quatech_rqopr(port) & 0xC0;
1189 if (reg != QPCR_TEST_GET4)
1190 return -EINVAL;
1191
1192 pci_quatech_wqopr(port, qopr);
1193 return 0;
1194}
1195
1196static int pci_quatech_clock(struct uart_8250_port *port)
1197{
1198 u8 qopr, reg, set;
1199 unsigned long clock;
1200
1201 if (pci_quatech_test(port) < 0)
1202 return 1843200;
1203
1204 qopr = pci_quatech_rqopr(port);
1205
1206 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1207 reg = pci_quatech_rqopr(port);
1208 if (reg & QOPR_CLOCK_X8) {
1209 clock = 1843200;
1210 goto out;
1211 }
1212 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1213 reg = pci_quatech_rqopr(port);
1214 if (!(reg & QOPR_CLOCK_X8)) {
1215 clock = 1843200;
1216 goto out;
1217 }
1218 reg &= QOPR_CLOCK_X8;
1219 if (reg == QOPR_CLOCK_X2) {
1220 clock = 3685400;
1221 set = QOPR_CLOCK_X2;
1222 } else if (reg == QOPR_CLOCK_X4) {
1223 clock = 7372800;
1224 set = QOPR_CLOCK_X4;
1225 } else if (reg == QOPR_CLOCK_X8) {
1226 clock = 14745600;
1227 set = QOPR_CLOCK_X8;
1228 } else {
1229 clock = 1843200;
1230 set = QOPR_CLOCK_X1;
1231 }
1232 qopr &= ~QOPR_CLOCK_RATE_MASK;
1233 qopr |= set;
1234
1235out:
1236 pci_quatech_wqopr(port, qopr);
1237 return clock;
1238}
1239
1240static int pci_quatech_rs422(struct uart_8250_port *port)
1241{
1242 u8 qmcr;
1243 int rs422 = 0;
1244
1245 if (!pci_quatech_has_qmcr(port))
1246 return 0;
1247 qmcr = pci_quatech_rqmcr(port);
1248 pci_quatech_wqmcr(port, 0xFF);
1249 if (pci_quatech_rqmcr(port))
1250 rs422 = 1;
1251 pci_quatech_wqmcr(port, qmcr);
1252 return rs422;
1253}
1254
1255static int pci_quatech_init(struct pci_dev *dev)
1256{
1257 if (pci_quatech_amcc(dev->device)) {
1258 unsigned long base = pci_resource_start(dev, 0);
1259 if (base) {
1260 u32 tmp;
9c5320f8 1261 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
55c7c0fd
AC		 1262 tmp = inl(base + 0x3c);
1263 outl(tmp | 0x01000000, base + 0x3c);
9c5320f8 1264 outl(tmp &= ~0x01000000, base + 0x3c);
55c7c0fd
AC		 1265 }
1266 }
1267 return 0;
1268}
1269
1270static int pci_quatech_setup(struct serial_private *priv,
1271 const struct pciserial_board *board,
1272 struct uart_8250_port *port, int idx)
1273{
1274 /* Needed by pci_quatech calls below */
1275 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1276 /* Set up the clocking */
1277 port->port.uartclk = pci_quatech_clock(port);
1278 /* For now just warn about RS422 */
1279 if (pci_quatech_rs422(port))
1280 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1281 return pci_default_setup(priv, board, port, idx);
1282}
1283
d73dfc6a 1284static void pci_quatech_exit(struct pci_dev *dev)
55c7c0fd
AC		 1285{
1286}
1287
eb26dfe8 1288static int pci_default_setup(struct serial_private *priv,
975a1a7d 1289 const struct pciserial_board *board,
2655a2c7 1290 struct uart_8250_port *port, int idx)
1da177e4
LT		 1291{
1292 unsigned int bar, offset = board->first_offset, maxnr;
1293
1294 bar = FL_GET_BASE(board->flags);
1295 if (board->flags & FL_BASE_BARS)
1296 bar += idx;
1297 else
1298 offset += idx * board->uart_offset;
1299
2427ddd8
GKH		 1300 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1301 (board->reg_shift + 3);
1da177e4
LT		 1302
1303 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1304 return 1;
5756ee99 1305
70db3d91 1306 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 1307}
1308
94341475
AB		 1309static int pci_pericom_setup(struct serial_private *priv,
1310 const struct pciserial_board *board,
1311 struct uart_8250_port *port, int idx)
1312{
1313 unsigned int bar, offset = board->first_offset, maxnr;
1314
1315 bar = FL_GET_BASE(board->flags);
1316 if (board->flags & FL_BASE_BARS)
1317 bar += idx;
1318 else
1319 offset += idx * board->uart_offset;
1320
1321 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1322 (board->reg_shift + 3);
1323
1324 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1325 return 1;
1326
1327 port->port.uartclk = 14745600;
1328
1329 return setup_port(priv, port, bar, offset, board->reg_shift);
1330}
1331
095e24b0
DB		 1332static int
1333ce4100_serial_setup(struct serial_private *priv,
1334 const struct pciserial_board *board,
2655a2c7 1335 struct uart_8250_port *port, int idx)
095e24b0
DB		 1336{
1337 int ret;
1338
08ec212c 1339 ret = setup_port(priv, port, idx, 0, board->reg_shift);
2655a2c7
AC		 1340 port->port.iotype = UPIO_MEM32;
1341 port->port.type = PORT_XSCALE;
1342 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1343 port->port.regshift = 2;
095e24b0
DB		 1344
1345 return ret;
1346}
1347
b15e5691
HK		 1348#define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1349#define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1350
1351#define BYT_PRV_CLK 0x800
1352#define BYT_PRV_CLK_EN (1 << 0)
1353#define BYT_PRV_CLK_M_VAL_SHIFT 1
1354#define BYT_PRV_CLK_N_VAL_SHIFT 16
1355#define BYT_PRV_CLK_UPDATE (1 << 31)
1356
1357#define BYT_GENERAL_REG 0x808
1358#define BYT_GENERAL_DIS_RTS_N_OVERRIDE (1 << 3)
1359
1360#define BYT_TX_OVF_INT 0x820
1361#define BYT_TX_OVF_INT_MASK (1 << 1)
1362
1363static void
1364byt_set_termios(struct uart_port *p, struct ktermios *termios,
1365 struct ktermios *old)
1366{
1367 unsigned int baud = tty_termios_baud_rate(termios);
1368 unsigned int m = 6912;
1369 unsigned int n = 15625;
1370 u32 reg;
1371
1372 /* For baud rates 1M, 2M, 3M and 4M the dividers must be adjusted. */
1373 if (baud == 1000000 || baud == 2000000 || baud == 4000000) {
1374 m = 64;
1375 n = 100;
1376
1377 p->uartclk = 64000000;
1378 } else if (baud == 3000000) {
1379 m = 48;
1380 n = 100;
1381
1382 p->uartclk = 48000000;
1383 } else {
1384 p->uartclk = 44236800;
1385 }
1386
1387 /* Reset the clock */
1388 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1389 writel(reg, p->membase + BYT_PRV_CLK);
1390 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1391 writel(reg, p->membase + BYT_PRV_CLK);
1392
1393 /*
1394 * If auto-handshake mechanism is not enabled,
1395 * disable rts_n override
1396 */
1397 reg = readl(p->membase + BYT_GENERAL_REG);
1398 reg &= ~BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1399 if (termios->c_cflag & CRTSCTS)
1400 reg |= BYT_GENERAL_DIS_RTS_N_OVERRIDE;
1401 writel(reg, p->membase + BYT_GENERAL_REG);
1402
1403 serial8250_do_set_termios(p, termios, old);
1404}
1405
1406static bool byt_dma_filter(struct dma_chan *chan, void *param)
1407{
1408 return chan->chan_id == *(int *)param;
1409}
1410
1411static int
1412byt_serial_setup(struct serial_private *priv,
1413 const struct pciserial_board *board,
1414 struct uart_8250_port *port, int idx)
1415{
1416 struct uart_8250_dma *dma;
1417 int ret;
1418
1419 dma = devm_kzalloc(port->port.dev, sizeof(*dma), GFP_KERNEL);
1420 if (!dma)
1421 return -ENOMEM;
1422
1423 switch (priv->dev->device) {
1424 case PCI_DEVICE_ID_INTEL_BYT_UART1:
1425 dma->rx_chan_id = 3;
1426 dma->tx_chan_id = 2;
1427 break;
1428 case PCI_DEVICE_ID_INTEL_BYT_UART2:
1429 dma->rx_chan_id = 5;
1430 dma->tx_chan_id = 4;
1431 break;
1432 default:
1433 return -EINVAL;
1434 }
1435
1436 dma->rxconf.slave_id = dma->rx_chan_id;
1437 dma->rxconf.src_maxburst = 16;
1438
1439 dma->txconf.slave_id = dma->tx_chan_id;
1440 dma->txconf.dst_maxburst = 16;
1441
1442 dma->fn = byt_dma_filter;
1443 dma->rx_param = &dma->rx_chan_id;
1444 dma->tx_param = &dma->tx_chan_id;
1445
1446 ret = pci_default_setup(priv, board, port, idx);
1447 port->port.iotype = UPIO_MEM;
1448 port->port.type = PORT_16550A;
1449 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1450 port->port.set_termios = byt_set_termios;
1451 port->port.fifosize = 64;
1452 port->tx_loadsz = 64;
1453 port->dma = dma;
1454 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1455
1456 /* Disable Tx counter interrupts */
1457 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1458
1459 return ret;
1460}
1461
d9a0fbfd
AP		 1462static int
1463pci_omegapci_setup(struct serial_private *priv,
1798ca13 1464 const struct pciserial_board *board,
2655a2c7 1465 struct uart_8250_port *port, int idx)
d9a0fbfd
AP		 1466{
1467 return setup_port(priv, port, 2, idx * 8, 0);
1468}
1469
ebebd49a
SH		 1470static int
1471pci_brcm_trumanage_setup(struct serial_private *priv,
1472 const struct pciserial_board *board,
1473 struct uart_8250_port *port, int idx)
1474{
1475 int ret = pci_default_setup(priv, board, port, idx);
1476
1477 port->port.type = PORT_BRCM_TRUMANAGE;
1478 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1479 return ret;
1480}
1481
2c62a3c8
GKH		 1482static int pci_fintek_setup(struct serial_private *priv,
1483 const struct pciserial_board *board,
1484 struct uart_8250_port *port, int idx)
1485{
1486 struct pci_dev *pdev = priv->dev;
1487 unsigned long base;
1488 unsigned long iobase;
1489 unsigned long ciobase = 0;
1490 u8 config_base;
1491
1492 /*
1493 * We are supposed to be able to read these from the PCI config space,
1494 * but the values there don't seem to match what we need to use, so
1495 * just use these hard-coded values for now, as they are correct.
1496 */
1497 switch (idx) {
1498 case 0: iobase = 0xe000; config_base = 0x40; break;
1499 case 1: iobase = 0xe008; config_base = 0x48; break;
1500 case 2: iobase = 0xe010; config_base = 0x50; break;
1501 case 3: iobase = 0xe018; config_base = 0x58; break;
1502 case 4: iobase = 0xe020; config_base = 0x60; break;
1503 case 5: iobase = 0xe028; config_base = 0x68; break;
1504 case 6: iobase = 0xe030; config_base = 0x70; break;
1505 case 7: iobase = 0xe038; config_base = 0x78; break;
1506 case 8: iobase = 0xe040; config_base = 0x80; break;
1507 case 9: iobase = 0xe048; config_base = 0x88; break;
1508 case 10: iobase = 0xe050; config_base = 0x90; break;
1509 case 11: iobase = 0xe058; config_base = 0x98; break;
1510 default:
1511 /* Unknown number of ports, get out of here */
1512 return -EINVAL;
1513 }
1514
1515 if (idx < 4) {
1516 base = pci_resource_start(priv->dev, 3);
1517 ciobase = (int)(base + (0x8 * idx));
1518 }
1519
1520 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n",
1521 __func__, idx, iobase, ciobase, config_base);
1522
1523 /* Enable UART I/O port */
1524 pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1525
1526 /* Select 128-byte FIFO and 8x FIFO threshold */
1527 pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1528
1529 /* LSB UART */
1530 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1531
1532 /* MSB UART */
1533 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1534
1535 /* irq number, this usually fails, but the spec says to do it anyway. */
1536 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1537
1538 port->port.iotype = UPIO_PORT;
1539 port->port.iobase = iobase;
1540 port->port.mapbase = 0;
1541 port->port.membase = NULL;
1542 port->port.regshift = 0;
1543
1544 return 0;
1545}
1546
b6adea33
MCC		 1547static int skip_tx_en_setup(struct serial_private *priv,
1548 const struct pciserial_board *board,
2655a2c7 1549 struct uart_8250_port *port, int idx)
b6adea33 1550{
2655a2c7 1551 port->port.flags |= UPF_NO_TXEN_TEST;
af8c5b8d
GKH		 1552 dev_dbg(&priv->dev->dev,
1553 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1554 priv->dev->vendor, priv->dev->device,
1555 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
b6adea33
MCC		 1556
1557 return pci_default_setup(priv, board, port, idx);
1558}
1559
0ad372b9
SM		 1560static void kt_handle_break(struct uart_port *p)
1561{
1562 struct uart_8250_port *up =
1563 container_of(p, struct uart_8250_port, port);
1564 /*
1565 * On receipt of a BI, serial device in Intel ME (Intel
1566 * management engine) needs to have its fifos cleared for sane
1567 * SOL (Serial Over Lan) output.
1568 */
1569 serial8250_clear_and_reinit_fifos(up);
1570}
1571
1572static unsigned int kt_serial_in(struct uart_port *p, int offset)
1573{
1574 struct uart_8250_port *up =
1575 container_of(p, struct uart_8250_port, port);
1576 unsigned int val;
1577
1578 /*
1579 * When the Intel ME (management engine) gets reset its serial
1580 * port registers could return 0 momentarily. Functions like
1581 * serial8250_console_write, read and save the IER, perform
1582 * some operation and then restore it. In order to avoid
1583 * setting IER register inadvertently to 0, if the value read
1584 * is 0, double check with ier value in uart_8250_port and use
1585 * that instead. up->ier should be the same value as what is
1586 * currently configured.
1587 */
1588 val = inb(p->iobase + offset);
1589 if (offset == UART_IER) {
1590 if (val == 0)
1591 val = up->ier;
1592 }
1593 return val;
1594}
1595
bc02d15a
DW		 1596static int kt_serial_setup(struct serial_private *priv,
1597 const struct pciserial_board *board,
2655a2c7 1598 struct uart_8250_port *port, int idx)
bc02d15a 1599{
2655a2c7
AC		 1600 port->port.flags |= UPF_BUG_THRE;
1601 port->port.serial_in = kt_serial_in;
1602 port->port.handle_break = kt_handle_break;
bc02d15a
DW		 1603 return skip_tx_en_setup(priv, board, port, idx);
1604}
1605
eb7073db
TM		 1606static int pci_eg20t_init(struct pci_dev *dev)
1607{
1608#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1609 return -ENODEV;
1610#else
1611 return 0;
1612#endif
1613}
1614
06315348
SH		 1615static int
1616pci_xr17c154_setup(struct serial_private *priv,
1617 const struct pciserial_board *board,
2655a2c7 1618 struct uart_8250_port *port, int idx)
06315348 1619{
2655a2c7 1620 port->port.flags |= UPF_EXAR_EFR;
06315348
SH		 1621 return pci_default_setup(priv, board, port, idx);
1622}
1623
dc96efb7
MS		 1624static int
1625pci_xr17v35x_setup(struct serial_private *priv,
1626 const struct pciserial_board *board,
1627 struct uart_8250_port *port, int idx)
1628{
1629 u8 __iomem *p;
1630
1631 p = pci_ioremap_bar(priv->dev, 0);
13c3237d
MS		 1632 if (p == NULL)
1633 return -ENOMEM;
dc96efb7
MS		 1634
1635 port->port.flags |= UPF_EXAR_EFR;
1636
1637 /*
1638 * Setup Multipurpose Input/Output pins.
1639 */
1640 if (idx == 0) {
1641 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1642 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1643 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1644 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1645 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1646 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1647 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1648 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1649 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1650 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1651 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1652 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1653 }
f965b9c4
MS		 1654 writeb(0x00, p + UART_EXAR_8XMODE);
1655 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1656 writeb(128, p + UART_EXAR_TXTRG);
1657 writeb(128, p + UART_EXAR_RXTRG);
dc96efb7
MS		 1658 iounmap(p);
1659
1660 return pci_default_setup(priv, board, port, idx);
1661}
1662
14faa8cc
MS		 1663#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1664#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1665#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1666#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1667
1668static int
1669pci_fastcom335_setup(struct serial_private *priv,
1670 const struct pciserial_board *board,
1671 struct uart_8250_port *port, int idx)
1672{
1673 u8 __iomem *p;
1674
1675 p = pci_ioremap_bar(priv->dev, 0);
1676 if (p == NULL)
1677 return -ENOMEM;
1678
1679 port->port.flags |= UPF_EXAR_EFR;
1680
1681 /*
1682 * Setup Multipurpose Input/Output pins.
1683 */
1684 if (idx == 0) {
1685 switch (priv->dev->device) {
1686 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1687 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1688 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1689 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1690 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1691 break;
1692 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1693 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1694 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1695 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1696 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1697 break;
1698 }
1699 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1700 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1701 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1702 }
1703 writeb(0x00, p + UART_EXAR_8XMODE);
1704 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1705 writeb(32, p + UART_EXAR_TXTRG);
1706 writeb(32, p + UART_EXAR_RXTRG);
1707 iounmap(p);
1708
1709 return pci_default_setup(priv, board, port, idx);
1710}
1711
6971c635
GA		 1712static int
1713pci_wch_ch353_setup(struct serial_private *priv,
1714 const struct pciserial_board *board,
1715 struct uart_8250_port *port, int idx)
1716{
1717 port->port.flags |= UPF_FIXED_TYPE;
1718 port->port.type = PORT_16550A;
06315348
SH		 1719 return pci_default_setup(priv, board, port, idx);
1720}
1721
1da177e4
LT		 1722#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1723#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1724#define PCI_DEVICE_ID_OCTPRO 0x0001
1725#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1726#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1727#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1728#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
26e8220a
FL		 1729#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1730#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
78d70d48 1731#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 1732#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 1733#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
66169ad1
YY		 1734#define PCI_DEVICE_ID_TITAN_200I 0x8028
1735#define PCI_DEVICE_ID_TITAN_400I 0x8048
1736#define PCI_DEVICE_ID_TITAN_800I 0x8088
1737#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1738#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1739#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1740#define PCI_DEVICE_ID_TITAN_100E 0xA010
1741#define PCI_DEVICE_ID_TITAN_200E 0xA012
1742#define PCI_DEVICE_ID_TITAN_400E 0xA013
1743#define PCI_DEVICE_ID_TITAN_800E 0xA014
1744#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1745#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
48c0247d 1746#define PCI_DEVICE_ID_TITAN_200V3 0xA306
1e9deb11
YY		 1747#define PCI_DEVICE_ID_TITAN_400V3 0xA310
1748#define PCI_DEVICE_ID_TITAN_410V3 0xA312
1749#define PCI_DEVICE_ID_TITAN_800V3 0xA314
1750#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
e847003f 1751#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 1752#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
d9a0fbfd 1753#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
bc02d15a 1754#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
27788c5f 1755#define PCI_VENDOR_ID_WCH 0x4348
8b5c913f 1756#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
27788c5f
AC		 1757#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1758#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1759#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
6683549e
AC		 1760#define PCI_VENDOR_ID_AGESTAR 0x5372
1761#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
eb26dfe8 1762#define PCI_VENDOR_ID_ASIX 0x9710
14faa8cc
MS		 1763#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1764#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
b7b9041b 1765#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
ebebd49a 1766#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
57c1f0e9 1767#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
14faa8cc 1768
abd7baca
SC		 1769#define PCI_VENDOR_ID_SUNIX 0x1fd4
1770#define PCI_DEVICE_ID_SUNIX_1999 0x1999
1771
1da177e4 1772
b76c5a07
CB		 1773/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1774#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
d13402a4 1775#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
b76c5a07 1776
1da177e4
LT		 1777/*
1778 * Master list of serial port init/setup/exit quirks.
1779 * This does not describe the general nature of the port.
1780 * (ie, baud base, number and location of ports, etc)
1781 *
1782 * This list is ordered alphabetically by vendor then device.
1783 * Specific entries must come before more generic entries.
1784 */
7a63ce5a 1785static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 1786 /*
1787 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1788 */
1789 {
086231f7 1790 .vendor = PCI_VENDOR_ID_AMCC,
57c1f0e9 1791 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 1792 .subvendor = PCI_ANY_ID,
1793 .subdevice = PCI_ANY_ID,
1794 .setup = addidata_apci7800_setup,
1795 },
1da177e4 1796 /*
61a116ef 1797 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 1798 * It is not clear whether this applies to all products.
1799 */
1800 {
1801 .vendor = PCI_VENDOR_ID_AFAVLAB,
1802 .device = PCI_ANY_ID,
1803 .subvendor = PCI_ANY_ID,
1804 .subdevice = PCI_ANY_ID,
1805 .setup = afavlab_setup,
1806 },
1807 /*
1808 * HP Diva
1809 */
1810 {
1811 .vendor = PCI_VENDOR_ID_HP,
1812 .device = PCI_DEVICE_ID_HP_DIVA,
1813 .subvendor = PCI_ANY_ID,
1814 .subdevice = PCI_ANY_ID,
1815 .init = pci_hp_diva_init,
1816 .setup = pci_hp_diva_setup,
1817 },
1818 /*
1819 * Intel
1820 */
1821 {
1822 .vendor = PCI_VENDOR_ID_INTEL,
1823 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1824 .subvendor = 0xe4bf,
1825 .subdevice = PCI_ANY_ID,
1826 .init = pci_inteli960ni_init,
1827 .setup = pci_default_setup,
1828 },
b6adea33
MCC		 1829 {
1830 .vendor = PCI_VENDOR_ID_INTEL,
1831 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1832 .subvendor = PCI_ANY_ID,
1833 .subdevice = PCI_ANY_ID,
1834 .setup = skip_tx_en_setup,
1835 },
1836 {
1837 .vendor = PCI_VENDOR_ID_INTEL,
1838 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1839 .subvendor = PCI_ANY_ID,
1840 .subdevice = PCI_ANY_ID,
1841 .setup = skip_tx_en_setup,
1842 },
1843 {
1844 .vendor = PCI_VENDOR_ID_INTEL,
1845 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1846 .subvendor = PCI_ANY_ID,
1847 .subdevice = PCI_ANY_ID,
1848 .setup = skip_tx_en_setup,
1849 },
095e24b0
DB		 1850 {
1851 .vendor = PCI_VENDOR_ID_INTEL,
1852 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1853 .subvendor = PCI_ANY_ID,
1854 .subdevice = PCI_ANY_ID,
1855 .setup = ce4100_serial_setup,
1856 },
bc02d15a
DW		 1857 {
1858 .vendor = PCI_VENDOR_ID_INTEL,
1859 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1860 .subvendor = PCI_ANY_ID,
1861 .subdevice = PCI_ANY_ID,
1862 .setup = kt_serial_setup,
1863 },
b15e5691
HK		 1864 {
1865 .vendor = PCI_VENDOR_ID_INTEL,
1866 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
1867 .subvendor = PCI_ANY_ID,
1868 .subdevice = PCI_ANY_ID,
1869 .setup = byt_serial_setup,
1870 },
1871 {
1872 .vendor = PCI_VENDOR_ID_INTEL,
1873 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
1874 .subvendor = PCI_ANY_ID,
1875 .subdevice = PCI_ANY_ID,
1876 .setup = byt_serial_setup,
1877 },
84f8c6fc
NV		 1878 /*
1879 * ITE
1880 */
1881 {
1882 .vendor = PCI_VENDOR_ID_ITE,
1883 .device = PCI_DEVICE_ID_ITE_8872,
1884 .subvendor = PCI_ANY_ID,
1885 .subdevice = PCI_ANY_ID,
1886 .init = pci_ite887x_init,
1887 .setup = pci_default_setup,
2d47b716 1888 .exit = pci_ite887x_exit,
84f8c6fc 1889 },
46a0fac9
SB		 1890 /*
1891 * National Instruments
1892 */
04bf7e74
WP		 1893 {
1894 .vendor = PCI_VENDOR_ID_NI,
1895 .device = PCI_DEVICE_ID_NI_PCI23216,
1896 .subvendor = PCI_ANY_ID,
1897 .subdevice = PCI_ANY_ID,
1898 .init = pci_ni8420_init,
1899 .setup = pci_default_setup,
2d47b716 1900 .exit = pci_ni8420_exit,
04bf7e74
WP		 1901 },
1902 {
1903 .vendor = PCI_VENDOR_ID_NI,
1904 .device = PCI_DEVICE_ID_NI_PCI2328,
1905 .subvendor = PCI_ANY_ID,
1906 .subdevice = PCI_ANY_ID,
1907 .init = pci_ni8420_init,
1908 .setup = pci_default_setup,
2d47b716 1909 .exit = pci_ni8420_exit,
04bf7e74
WP		 1910 },
1911 {
1912 .vendor = PCI_VENDOR_ID_NI,
1913 .device = PCI_DEVICE_ID_NI_PCI2324,
1914 .subvendor = PCI_ANY_ID,
1915 .subdevice = PCI_ANY_ID,
1916 .init = pci_ni8420_init,
1917 .setup = pci_default_setup,
2d47b716 1918 .exit = pci_ni8420_exit,
04bf7e74
WP		 1919 },
1920 {
1921 .vendor = PCI_VENDOR_ID_NI,
1922 .device = PCI_DEVICE_ID_NI_PCI2322,
1923 .subvendor = PCI_ANY_ID,
1924 .subdevice = PCI_ANY_ID,
1925 .init = pci_ni8420_init,
1926 .setup = pci_default_setup,
2d47b716 1927 .exit = pci_ni8420_exit,
04bf7e74
WP		 1928 },
1929 {
1930 .vendor = PCI_VENDOR_ID_NI,
1931 .device = PCI_DEVICE_ID_NI_PCI2324I,
1932 .subvendor = PCI_ANY_ID,
1933 .subdevice = PCI_ANY_ID,
1934 .init = pci_ni8420_init,
1935 .setup = pci_default_setup,
2d47b716 1936 .exit = pci_ni8420_exit,
04bf7e74
WP		 1937 },
1938 {
1939 .vendor = PCI_VENDOR_ID_NI,
1940 .device = PCI_DEVICE_ID_NI_PCI2322I,
1941 .subvendor = PCI_ANY_ID,
1942 .subdevice = PCI_ANY_ID,
1943 .init = pci_ni8420_init,
1944 .setup = pci_default_setup,
2d47b716 1945 .exit = pci_ni8420_exit,
04bf7e74
WP		 1946 },
1947 {
1948 .vendor = PCI_VENDOR_ID_NI,
1949 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1950 .subvendor = PCI_ANY_ID,
1951 .subdevice = PCI_ANY_ID,
1952 .init = pci_ni8420_init,
1953 .setup = pci_default_setup,
2d47b716 1954 .exit = pci_ni8420_exit,
04bf7e74
WP		 1955 },
1956 {
1957 .vendor = PCI_VENDOR_ID_NI,
1958 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1959 .subvendor = PCI_ANY_ID,
1960 .subdevice = PCI_ANY_ID,
1961 .init = pci_ni8420_init,
1962 .setup = pci_default_setup,
2d47b716 1963 .exit = pci_ni8420_exit,
04bf7e74
WP		 1964 },
1965 {
1966 .vendor = PCI_VENDOR_ID_NI,
1967 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1968 .subvendor = PCI_ANY_ID,
1969 .subdevice = PCI_ANY_ID,
1970 .init = pci_ni8420_init,
1971 .setup = pci_default_setup,
2d47b716 1972 .exit = pci_ni8420_exit,
04bf7e74
WP		 1973 },
1974 {
1975 .vendor = PCI_VENDOR_ID_NI,
1976 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1977 .subvendor = PCI_ANY_ID,
1978 .subdevice = PCI_ANY_ID,
1979 .init = pci_ni8420_init,
1980 .setup = pci_default_setup,
2d47b716 1981 .exit = pci_ni8420_exit,
04bf7e74
WP		 1982 },
1983 {
1984 .vendor = PCI_VENDOR_ID_NI,
1985 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1986 .subvendor = PCI_ANY_ID,
1987 .subdevice = PCI_ANY_ID,
1988 .init = pci_ni8420_init,
1989 .setup = pci_default_setup,
2d47b716 1990 .exit = pci_ni8420_exit,
04bf7e74
WP		 1991 },
1992 {
1993 .vendor = PCI_VENDOR_ID_NI,
1994 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1995 .subvendor = PCI_ANY_ID,
1996 .subdevice = PCI_ANY_ID,
1997 .init = pci_ni8420_init,
1998 .setup = pci_default_setup,
2d47b716 1999 .exit = pci_ni8420_exit,
04bf7e74 2000 },
46a0fac9
SB		 2001 {
2002 .vendor = PCI_VENDOR_ID_NI,
2003 .device = PCI_ANY_ID,
2004 .subvendor = PCI_ANY_ID,
2005 .subdevice = PCI_ANY_ID,
2006 .init = pci_ni8430_init,
2007 .setup = pci_ni8430_setup,
2d47b716 2008 .exit = pci_ni8430_exit,
46a0fac9 2009 },
55c7c0fd
AC		 2010 /* Quatech */
2011 {
2012 .vendor = PCI_VENDOR_ID_QUATECH,
2013 .device = PCI_ANY_ID,
2014 .subvendor = PCI_ANY_ID,
2015 .subdevice = PCI_ANY_ID,
2016 .init = pci_quatech_init,
2017 .setup = pci_quatech_setup,
d73dfc6a 2018 .exit = pci_quatech_exit,
55c7c0fd 2019 },
1da177e4
LT		 2020 /*
2021 * Panacom
2022 */
2023 {
2024 .vendor = PCI_VENDOR_ID_PANACOM,
2025 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2026 .subvendor = PCI_ANY_ID,
2027 .subdevice = PCI_ANY_ID,
2028 .init = pci_plx9050_init,
2029 .setup = pci_default_setup,
2d47b716 2030 .exit = pci_plx9050_exit,
5756ee99 2031 },
1da177e4
LT		 2032 {
2033 .vendor = PCI_VENDOR_ID_PANACOM,
2034 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2035 .subvendor = PCI_ANY_ID,
2036 .subdevice = PCI_ANY_ID,
2037 .init = pci_plx9050_init,
2038 .setup = pci_default_setup,
2d47b716 2039 .exit = pci_plx9050_exit,
1da177e4 2040 },
94341475
AB		 2041 /*
2042 * Pericom
2043 */
2044 {
2045 .vendor = 0x12d8,
2046 .device = 0x7952,
2047 .subvendor = PCI_ANY_ID,
2048 .subdevice = PCI_ANY_ID,
2049 .setup = pci_pericom_setup,
2050 },
2051 {
2052 .vendor = 0x12d8,
2053 .device = 0x7954,
2054 .subvendor = PCI_ANY_ID,
2055 .subdevice = PCI_ANY_ID,
2056 .setup = pci_pericom_setup,
2057 },
2058 {
2059 .vendor = 0x12d8,
2060 .device = 0x7958,
2061 .subvendor = PCI_ANY_ID,
2062 .subdevice = PCI_ANY_ID,
2063 .setup = pci_pericom_setup,
2064 },
2065
1da177e4
LT		 2066 /*
2067 * PLX
2068 */
48212008
TH		 2069 {
2070 .vendor = PCI_VENDOR_ID_PLX,
2071 .device = PCI_DEVICE_ID_PLX_9030,
2072 .subvendor = PCI_SUBVENDOR_ID_PERLE,
2073 .subdevice = PCI_ANY_ID,
2074 .setup = pci_default_setup,
2075 },
add7b58e
BH		 2076 {
2077 .vendor = PCI_VENDOR_ID_PLX,
2078 .device = PCI_DEVICE_ID_PLX_9050,
2079 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2080 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2081 .init = pci_plx9050_init,
2082 .setup = pci_default_setup,
2d47b716 2083 .exit = pci_plx9050_exit,
add7b58e 2084 },
1da177e4
LT		 2085 {
2086 .vendor = PCI_VENDOR_ID_PLX,
2087 .device = PCI_DEVICE_ID_PLX_9050,
2088 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2089 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2090 .init = pci_plx9050_init,
2091 .setup = pci_default_setup,
2d47b716 2092 .exit = pci_plx9050_exit,
1da177e4
LT		 2093 },
2094 {
2095 .vendor = PCI_VENDOR_ID_PLX,
2096 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2097 .subvendor = PCI_VENDOR_ID_PLX,
2098 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2099 .init = pci_plx9050_init,
2100 .setup = pci_default_setup,
2d47b716 2101 .exit = pci_plx9050_exit,
1da177e4
LT		 2102 },
2103 /*
2104 * SBS Technologies, Inc., PMC-OCTALPRO 232
2105 */
2106 {
2107 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2108 .device = PCI_DEVICE_ID_OCTPRO,
2109 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2110 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2111 .init = sbs_init,
2112 .setup = sbs_setup,
2d47b716 2113 .exit = sbs_exit,
1da177e4
LT		 2114 },
2115 /*
2116 * SBS Technologies, Inc., PMC-OCTALPRO 422
2117 */
2118 {
2119 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2120 .device = PCI_DEVICE_ID_OCTPRO,
2121 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2122 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2123 .init = sbs_init,
2124 .setup = sbs_setup,
2d47b716 2125 .exit = sbs_exit,
1da177e4
LT		 2126 },
2127 /*
2128 * SBS Technologies, Inc., P-Octal 232
2129 */
2130 {
2131 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2132 .device = PCI_DEVICE_ID_OCTPRO,
2133 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2134 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2135 .init = sbs_init,
2136 .setup = sbs_setup,
2d47b716 2137 .exit = sbs_exit,
1da177e4
LT		 2138 },
2139 /*
2140 * SBS Technologies, Inc., P-Octal 422
2141 */
2142 {
2143 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2144 .device = PCI_DEVICE_ID_OCTPRO,
2145 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2146 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2147 .init = sbs_init,
2148 .setup = sbs_setup,
2d47b716 2149 .exit = sbs_exit,
1da177e4 2150 },
1da177e4 2151 /*
61a116ef 2152 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 2153 */
2154 {
2155 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 2156 .device = PCI_ANY_ID,
1da177e4
LT		 2157 .subvendor = PCI_ANY_ID,
2158 .subdevice = PCI_ANY_ID,
67d74b87 2159 .init = pci_siig_init,
3ec9c594 2160 .setup = pci_siig_setup,
1da177e4
LT		 2161 },
2162 /*
2163 * Titan cards
2164 */
2165 {
2166 .vendor = PCI_VENDOR_ID_TITAN,
2167 .device = PCI_DEVICE_ID_TITAN_400L,
2168 .subvendor = PCI_ANY_ID,
2169 .subdevice = PCI_ANY_ID,
2170 .setup = titan_400l_800l_setup,
2171 },
2172 {
2173 .vendor = PCI_VENDOR_ID_TITAN,
2174 .device = PCI_DEVICE_ID_TITAN_800L,
2175 .subvendor = PCI_ANY_ID,
2176 .subdevice = PCI_ANY_ID,
2177 .setup = titan_400l_800l_setup,
2178 },
2179 /*
2180 * Timedia cards
2181 */
2182 {
2183 .vendor = PCI_VENDOR_ID_TIMEDIA,
2184 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2185 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2186 .subdevice = PCI_ANY_ID,
b9b24558 2187 .probe = pci_timedia_probe,
1da177e4
LT		 2188 .init = pci_timedia_init,
2189 .setup = pci_timedia_setup,
2190 },
2191 {
2192 .vendor = PCI_VENDOR_ID_TIMEDIA,
2193 .device = PCI_ANY_ID,
2194 .subvendor = PCI_ANY_ID,
2195 .subdevice = PCI_ANY_ID,
2196 .setup = pci_timedia_setup,
2197 },
abd7baca
SC		 2198 /*
2199 * SUNIX (Timedia) cards
2200 * Do not "probe" for these cards as there is at least one combination
2201 * card that should be handled by parport_pc that doesn't match the
2202 * rule in pci_timedia_probe.
2203 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2204 * There are some boards with part number SER5037AL that report
2205 * subdevice ID 0x0002.
2206 */
2207 {
2208 .vendor = PCI_VENDOR_ID_SUNIX,
2209 .device = PCI_DEVICE_ID_SUNIX_1999,
2210 .subvendor = PCI_VENDOR_ID_SUNIX,
2211 .subdevice = PCI_ANY_ID,
2212 .init = pci_timedia_init,
2213 .setup = pci_timedia_setup,
2214 },
06315348
SH		 2215 /*
2216 * Exar cards
2217 */
2218 {
2219 .vendor = PCI_VENDOR_ID_EXAR,
2220 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2221 .subvendor = PCI_ANY_ID,
2222 .subdevice = PCI_ANY_ID,
2223 .setup = pci_xr17c154_setup,
2224 },
2225 {
2226 .vendor = PCI_VENDOR_ID_EXAR,
2227 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2228 .subvendor = PCI_ANY_ID,
2229 .subdevice = PCI_ANY_ID,
2230 .setup = pci_xr17c154_setup,
2231 },
2232 {
2233 .vendor = PCI_VENDOR_ID_EXAR,
2234 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2235 .subvendor = PCI_ANY_ID,
2236 .subdevice = PCI_ANY_ID,
2237 .setup = pci_xr17c154_setup,
2238 },
dc96efb7
MS		 2239 {
2240 .vendor = PCI_VENDOR_ID_EXAR,
2241 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2242 .subvendor = PCI_ANY_ID,
2243 .subdevice = PCI_ANY_ID,
2244 .setup = pci_xr17v35x_setup,
2245 },
2246 {
2247 .vendor = PCI_VENDOR_ID_EXAR,
2248 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2249 .subvendor = PCI_ANY_ID,
2250 .subdevice = PCI_ANY_ID,
2251 .setup = pci_xr17v35x_setup,
2252 },
2253 {
2254 .vendor = PCI_VENDOR_ID_EXAR,
2255 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2256 .subvendor = PCI_ANY_ID,
2257 .subdevice = PCI_ANY_ID,
2258 .setup = pci_xr17v35x_setup,
2259 },
1da177e4
LT		 2260 /*
2261 * Xircom cards
2262 */
2263 {
2264 .vendor = PCI_VENDOR_ID_XIRCOM,
2265 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2266 .subvendor = PCI_ANY_ID,
2267 .subdevice = PCI_ANY_ID,
2268 .init = pci_xircom_init,
2269 .setup = pci_default_setup,
2270 },
2271 /*
61a116ef 2272 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 2273 */
2274 {
2275 .vendor = PCI_VENDOR_ID_NETMOS,
2276 .device = PCI_ANY_ID,
2277 .subvendor = PCI_ANY_ID,
2278 .subdevice = PCI_ANY_ID,
2279 .init = pci_netmos_init,
7808edcd 2280 .setup = pci_netmos_9900_setup,
1da177e4 2281 },
9f2a036a 2282 /*
aa273ae5 2283 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 2284 */
2285 {
2286 .vendor = PCI_VENDOR_ID_OXSEMI,
2287 .device = PCI_ANY_ID,
2288 .subvendor = PCI_ANY_ID,
2289 .subdevice = PCI_ANY_ID,
2290 .init = pci_oxsemi_tornado_init,
2291 .setup = pci_default_setup,
2292 },
2293 {
2294 .vendor = PCI_VENDOR_ID_MAINPINE,
2295 .device = PCI_ANY_ID,
2296 .subvendor = PCI_ANY_ID,
2297 .subdevice = PCI_ANY_ID,
2298 .init = pci_oxsemi_tornado_init,
2299 .setup = pci_default_setup,
2300 },
aa273ae5
SK		 2301 {
2302 .vendor = PCI_VENDOR_ID_DIGI,
2303 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2304 .subvendor = PCI_SUBVENDOR_ID_IBM,
2305 .subdevice = PCI_ANY_ID,
2306 .init = pci_oxsemi_tornado_init,
2307 .setup = pci_default_setup,
2308 },
eb7073db
TM		 2309 {
2310 .vendor = PCI_VENDOR_ID_INTEL,
2311 .device = 0x8811,
aaa10eb1
AP		 2312 .subvendor = PCI_ANY_ID,
2313 .subdevice = PCI_ANY_ID,
eb7073db 2314 .init = pci_eg20t_init,
64d91cfa 2315 .setup = pci_default_setup,
eb7073db
TM		 2316 },
2317 {
2318 .vendor = PCI_VENDOR_ID_INTEL,
2319 .device = 0x8812,
aaa10eb1
AP		 2320 .subvendor = PCI_ANY_ID,
2321 .subdevice = PCI_ANY_ID,
eb7073db 2322 .init = pci_eg20t_init,
64d91cfa 2323 .setup = pci_default_setup,
eb7073db
TM		 2324 },
2325 {
2326 .vendor = PCI_VENDOR_ID_INTEL,
2327 .device = 0x8813,
aaa10eb1
AP		 2328 .subvendor = PCI_ANY_ID,
2329 .subdevice = PCI_ANY_ID,
eb7073db 2330 .init = pci_eg20t_init,
64d91cfa 2331 .setup = pci_default_setup,
eb7073db
TM		 2332 },
2333 {
2334 .vendor = PCI_VENDOR_ID_INTEL,
2335 .device = 0x8814,
aaa10eb1
AP		 2336 .subvendor = PCI_ANY_ID,
2337 .subdevice = PCI_ANY_ID,
eb7073db 2338 .init = pci_eg20t_init,
64d91cfa 2339 .setup = pci_default_setup,
eb7073db
TM		 2340 },
2341 {
2342 .vendor = 0x10DB,
2343 .device = 0x8027,
aaa10eb1
AP		 2344 .subvendor = PCI_ANY_ID,
2345 .subdevice = PCI_ANY_ID,
eb7073db 2346 .init = pci_eg20t_init,
64d91cfa 2347 .setup = pci_default_setup,
eb7073db
TM		 2348 },
2349 {
2350 .vendor = 0x10DB,
2351 .device = 0x8028,
aaa10eb1
AP		 2352 .subvendor = PCI_ANY_ID,
2353 .subdevice = PCI_ANY_ID,
eb7073db 2354 .init = pci_eg20t_init,
64d91cfa 2355 .setup = pci_default_setup,
eb7073db
TM		 2356 },
2357 {
2358 .vendor = 0x10DB,
2359 .device = 0x8029,
aaa10eb1
AP		 2360 .subvendor = PCI_ANY_ID,
2361 .subdevice = PCI_ANY_ID,
eb7073db 2362 .init = pci_eg20t_init,
64d91cfa 2363 .setup = pci_default_setup,
eb7073db
TM		 2364 },
2365 {
2366 .vendor = 0x10DB,
2367 .device = 0x800C,
aaa10eb1
AP		 2368 .subvendor = PCI_ANY_ID,
2369 .subdevice = PCI_ANY_ID,
eb7073db 2370 .init = pci_eg20t_init,
64d91cfa 2371 .setup = pci_default_setup,
eb7073db
TM		 2372 },
2373 {
2374 .vendor = 0x10DB,
2375 .device = 0x800D,
aaa10eb1
AP		 2376 .subvendor = PCI_ANY_ID,
2377 .subdevice = PCI_ANY_ID,
eb7073db 2378 .init = pci_eg20t_init,
64d91cfa 2379 .setup = pci_default_setup,
eb7073db 2380 },
d9a0fbfd
AP		 2381 /*
2382 * Cronyx Omega PCI (PLX-chip based)
2383 */
2384 {
2385 .vendor = PCI_VENDOR_ID_PLX,
2386 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2387 .subvendor = PCI_ANY_ID,
2388 .subdevice = PCI_ANY_ID,
2389 .setup = pci_omegapci_setup,
eb26dfe8 2390 },
6971c635
GA		 2391 /* WCH CH353 2S1P card (16550 clone) */
2392 {
27788c5f
AC		 2393 .vendor = PCI_VENDOR_ID_WCH,
2394 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2395 .subvendor = PCI_ANY_ID,
2396 .subdevice = PCI_ANY_ID,
2397 .setup = pci_wch_ch353_setup,
2398 },
2399 /* WCH CH353 4S card (16550 clone) */
2400 {
2401 .vendor = PCI_VENDOR_ID_WCH,
2402 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2403 .subvendor = PCI_ANY_ID,
2404 .subdevice = PCI_ANY_ID,
2405 .setup = pci_wch_ch353_setup,
2406 },
2407 /* WCH CH353 2S1PF card (16550 clone) */
2408 {
2409 .vendor = PCI_VENDOR_ID_WCH,
2410 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2411 .subvendor = PCI_ANY_ID,
2412 .subdevice = PCI_ANY_ID,
6971c635
GA		 2413 .setup = pci_wch_ch353_setup,
2414 },
8b5c913f
WY		 2415 /* WCH CH352 2S card (16550 clone) */
2416 {
2417 .vendor = PCI_VENDOR_ID_WCH,
2418 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2419 .subvendor = PCI_ANY_ID,
2420 .subdevice = PCI_ANY_ID,
2421 .setup = pci_wch_ch353_setup,
2422 },
eb26dfe8
AC		 2423 /*
2424 * ASIX devices with FIFO bug
2425 */
2426 {
2427 .vendor = PCI_VENDOR_ID_ASIX,
2428 .device = PCI_ANY_ID,
2429 .subvendor = PCI_ANY_ID,
2430 .subdevice = PCI_ANY_ID,
2431 .setup = pci_asix_setup,
2432 },
14faa8cc
MS		 2433 /*
2434 * Commtech, Inc. Fastcom adapters
2435 *
2436 */
2437 {
2438 .vendor = PCI_VENDOR_ID_COMMTECH,
2439 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2440 .subvendor = PCI_ANY_ID,
2441 .subdevice = PCI_ANY_ID,
2442 .setup = pci_fastcom335_setup,
2443 },
2444 {
2445 .vendor = PCI_VENDOR_ID_COMMTECH,
2446 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2447 .subvendor = PCI_ANY_ID,
2448 .subdevice = PCI_ANY_ID,
2449 .setup = pci_fastcom335_setup,
2450 },
2451 {
2452 .vendor = PCI_VENDOR_ID_COMMTECH,
2453 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2454 .subvendor = PCI_ANY_ID,
2455 .subdevice = PCI_ANY_ID,
2456 .setup = pci_fastcom335_setup,
2457 },
2458 {
2459 .vendor = PCI_VENDOR_ID_COMMTECH,
2460 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2461 .subvendor = PCI_ANY_ID,
2462 .subdevice = PCI_ANY_ID,
2463 .setup = pci_fastcom335_setup,
2464 },
2465 {
2466 .vendor = PCI_VENDOR_ID_COMMTECH,
2467 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2468 .subvendor = PCI_ANY_ID,
2469 .subdevice = PCI_ANY_ID,
2470 .setup = pci_xr17v35x_setup,
2471 },
2472 {
2473 .vendor = PCI_VENDOR_ID_COMMTECH,
2474 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2475 .subvendor = PCI_ANY_ID,
2476 .subdevice = PCI_ANY_ID,
2477 .setup = pci_xr17v35x_setup,
2478 },
2479 {
2480 .vendor = PCI_VENDOR_ID_COMMTECH,
2481 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2482 .subvendor = PCI_ANY_ID,
2483 .subdevice = PCI_ANY_ID,
2484 .setup = pci_xr17v35x_setup,
2485 },
ebebd49a
SH		 2486 /*
2487 * Broadcom TruManage (NetXtreme)
2488 */
2489 {
2490 .vendor = PCI_VENDOR_ID_BROADCOM,
2491 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2492 .subvendor = PCI_ANY_ID,
2493 .subdevice = PCI_ANY_ID,
2494 .setup = pci_brcm_trumanage_setup,
2495 },
2c62a3c8
GKH		 2496 {
2497 .vendor = 0x1c29,
2498 .device = 0x1104,
2499 .subvendor = PCI_ANY_ID,
2500 .subdevice = PCI_ANY_ID,
2501 .setup = pci_fintek_setup,
2502 },
2503 {
2504 .vendor = 0x1c29,
2505 .device = 0x1108,
2506 .subvendor = PCI_ANY_ID,
2507 .subdevice = PCI_ANY_ID,
2508 .setup = pci_fintek_setup,
2509 },
2510 {
2511 .vendor = 0x1c29,
2512 .device = 0x1112,
2513 .subvendor = PCI_ANY_ID,
2514 .subdevice = PCI_ANY_ID,
2515 .setup = pci_fintek_setup,
2516 },
ebebd49a 2517
1da177e4
LT		 2518 /*
2519 * Default "match everything" terminator entry
2520 */
2521 {
2522 .vendor = PCI_ANY_ID,
2523 .device = PCI_ANY_ID,
2524 .subvendor = PCI_ANY_ID,
2525 .subdevice = PCI_ANY_ID,
2526 .setup = pci_default_setup,
2527 }
2528};
2529
2530static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2531{
2532 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2533}
2534
2535static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2536{
2537 struct pci_serial_quirk *quirk;
2538
2539 for (quirk = pci_serial_quirks; ; quirk++)
2540 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2541 quirk_id_matches(quirk->device, dev->device) &&
2542 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2543 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 2544 break;
1da177e4
LT		 2545 return quirk;
2546}
2547
dd68e88c 2548static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 2549 const struct pciserial_board *board)
1da177e4
LT		 2550{
2551 if (board->flags & FL_NOIRQ)
2552 return 0;
2553 else
2554 return dev->irq;
2555}
2556
2557/*
2558 * This is the configuration table for all of the PCI serial boards
2559 * which we support. It is directly indexed by the pci_board_num_t enum
2560 * value, which is encoded in the pci_device_id PCI probe table's
2561 * driver_data member.
2562 *
2563 * The makeup of these names are:
26e92861 2564 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 2565 *
26e92861
GH		 2566 * bn = PCI BAR number
2567 * bt = Index using PCI BARs
2568 * n = number of serial ports
2569 * baud = baud rate
2570 * offsetinhex = offset for each sequential port (in hex)
1da177e4 2571 *
26e92861 2572 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 2573 *
1da177e4
LT		 2574 * Please note: in theory if n = 1, _bt infix should make no difference.
2575 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2576 */
2577enum pci_board_num_t {
2578 pbn_default = 0,
2579
2580 pbn_b0_1_115200,
2581 pbn_b0_2_115200,
2582 pbn_b0_4_115200,
2583 pbn_b0_5_115200,
bf0df636 2584 pbn_b0_8_115200,
1da177e4
LT		 2585
2586 pbn_b0_1_921600,
2587 pbn_b0_2_921600,
2588 pbn_b0_4_921600,
2589
db1de159
DR		 2590 pbn_b0_2_1130000,
2591
fbc0dc0d
AP		 2592 pbn_b0_4_1152000,
2593
14faa8cc
MS		 2594 pbn_b0_2_1152000_200,
2595 pbn_b0_4_1152000_200,
2596 pbn_b0_8_1152000_200,
2597
26e92861
GH		 2598 pbn_b0_2_1843200,
2599 pbn_b0_4_1843200,
2600
2601 pbn_b0_2_1843200_200,
2602 pbn_b0_4_1843200_200,
2603 pbn_b0_8_1843200_200,
2604
7106b4e3
LH		 2605 pbn_b0_1_4000000,
2606
1da177e4
LT		 2607 pbn_b0_bt_1_115200,
2608 pbn_b0_bt_2_115200,
ac6ec5b1 2609 pbn_b0_bt_4_115200,
1da177e4
LT		 2610 pbn_b0_bt_8_115200,
2611
2612 pbn_b0_bt_1_460800,
2613 pbn_b0_bt_2_460800,
2614 pbn_b0_bt_4_460800,
2615
2616 pbn_b0_bt_1_921600,
2617 pbn_b0_bt_2_921600,
2618 pbn_b0_bt_4_921600,
2619 pbn_b0_bt_8_921600,
2620
2621 pbn_b1_1_115200,
2622 pbn_b1_2_115200,
2623 pbn_b1_4_115200,
2624 pbn_b1_8_115200,
04bf7e74 2625 pbn_b1_16_115200,
1da177e4
LT		 2626
2627 pbn_b1_1_921600,
2628 pbn_b1_2_921600,
2629 pbn_b1_4_921600,
2630 pbn_b1_8_921600,
2631
26e92861
GH		 2632 pbn_b1_2_1250000,
2633
84f8c6fc 2634 pbn_b1_bt_1_115200,
04bf7e74
WP		 2635 pbn_b1_bt_2_115200,
2636 pbn_b1_bt_4_115200,
2637
1da177e4
LT		 2638 pbn_b1_bt_2_921600,
2639
2640 pbn_b1_1_1382400,
2641 pbn_b1_2_1382400,
2642 pbn_b1_4_1382400,
2643 pbn_b1_8_1382400,
2644
2645 pbn_b2_1_115200,
737c1756 2646 pbn_b2_2_115200,
a9cccd34 2647 pbn_b2_4_115200,
1da177e4
LT		 2648 pbn_b2_8_115200,
2649
2650 pbn_b2_1_460800,
2651 pbn_b2_4_460800,
2652 pbn_b2_8_460800,
2653 pbn_b2_16_460800,
2654
2655 pbn_b2_1_921600,
2656 pbn_b2_4_921600,
2657 pbn_b2_8_921600,
2658
e847003f
LB		 2659 pbn_b2_8_1152000,
2660
1da177e4
LT		 2661 pbn_b2_bt_1_115200,
2662 pbn_b2_bt_2_115200,
2663 pbn_b2_bt_4_115200,
2664
2665 pbn_b2_bt_2_921600,
2666 pbn_b2_bt_4_921600,
2667
d9004eb4 2668 pbn_b3_2_115200,
1da177e4
LT		 2669 pbn_b3_4_115200,
2670 pbn_b3_8_115200,
2671
66169ad1
YY		 2672 pbn_b4_bt_2_921600,
2673 pbn_b4_bt_4_921600,
2674 pbn_b4_bt_8_921600,
2675
1da177e4
LT		 2676 /*
2677 * Board-specific versions.
2678 */
2679 pbn_panacom,
2680 pbn_panacom2,
2681 pbn_panacom4,
2682 pbn_plx_romulus,
2683 pbn_oxsemi,
7106b4e3
LH		 2684 pbn_oxsemi_1_4000000,
2685 pbn_oxsemi_2_4000000,
2686 pbn_oxsemi_4_4000000,
2687 pbn_oxsemi_8_4000000,
1da177e4
LT		 2688 pbn_intel_i960,
2689 pbn_sgi_ioc3,
1da177e4
LT		 2690 pbn_computone_4,
2691 pbn_computone_6,
2692 pbn_computone_8,
2693 pbn_sbsxrsio,
2694 pbn_exar_XR17C152,
2695 pbn_exar_XR17C154,
2696 pbn_exar_XR17C158,
dc96efb7
MS		 2697 pbn_exar_XR17V352,
2698 pbn_exar_XR17V354,
2699 pbn_exar_XR17V358,
c68d2b15 2700 pbn_exar_ibm_saturn,
aa798505 2701 pbn_pasemi_1682M,
46a0fac9
SB		 2702 pbn_ni8430_2,
2703 pbn_ni8430_4,
2704 pbn_ni8430_8,
2705 pbn_ni8430_16,
1b62cbf2
KJ		 2706 pbn_ADDIDATA_PCIe_1_3906250,
2707 pbn_ADDIDATA_PCIe_2_3906250,
2708 pbn_ADDIDATA_PCIe_4_3906250,
2709 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 2710 pbn_ce4100_1_115200,
b15e5691 2711 pbn_byt,
d9a0fbfd 2712 pbn_omegapci,
7808edcd 2713 pbn_NETMOS9900_2s_115200,
ebebd49a 2714 pbn_brcm_trumanage,
2c62a3c8
GKH		 2715 pbn_fintek_4,
2716 pbn_fintek_8,
2717 pbn_fintek_12,
1da177e4
LT		 2718};
2719
2720/*
2721 * uart_offset - the space between channels
2722 * reg_shift - describes how the UART registers are mapped
2723 * to PCI memory by the card.
2724 * For example IER register on SBS, Inc. PMC-OctPro is located at
2725 * offset 0x10 from the UART base, while UART_IER is defined as 1
2726 * in include/linux/serial_reg.h,
2727 * see first lines of serial_in() and serial_out() in 8250.c
2728*/
2729
de88b340 2730static struct pciserial_board pci_boards[] = {
1da177e4
LT		 2731 [pbn_default] = {
2732 .flags = FL_BASE0,
2733 .num_ports = 1,
2734 .base_baud = 115200,
2735 .uart_offset = 8,
2736 },
2737 [pbn_b0_1_115200] = {
2738 .flags = FL_BASE0,
2739 .num_ports = 1,
2740 .base_baud = 115200,
2741 .uart_offset = 8,
2742 },
2743 [pbn_b0_2_115200] = {
2744 .flags = FL_BASE0,
2745 .num_ports = 2,
2746 .base_baud = 115200,
2747 .uart_offset = 8,
2748 },
2749 [pbn_b0_4_115200] = {
2750 .flags = FL_BASE0,
2751 .num_ports = 4,
2752 .base_baud = 115200,
2753 .uart_offset = 8,
2754 },
2755 [pbn_b0_5_115200] = {
2756 .flags = FL_BASE0,
2757 .num_ports = 5,
2758 .base_baud = 115200,
2759 .uart_offset = 8,
2760 },
bf0df636
AC		 2761 [pbn_b0_8_115200] = {
2762 .flags = FL_BASE0,
2763 .num_ports = 8,
2764 .base_baud = 115200,
2765 .uart_offset = 8,
2766 },
1da177e4
LT		 2767 [pbn_b0_1_921600] = {
2768 .flags = FL_BASE0,
2769 .num_ports = 1,
2770 .base_baud = 921600,
2771 .uart_offset = 8,
2772 },
2773 [pbn_b0_2_921600] = {
2774 .flags = FL_BASE0,
2775 .num_ports = 2,
2776 .base_baud = 921600,
2777 .uart_offset = 8,
2778 },
2779 [pbn_b0_4_921600] = {
2780 .flags = FL_BASE0,
2781 .num_ports = 4,
2782 .base_baud = 921600,
2783 .uart_offset = 8,
2784 },
db1de159
DR		 2785
2786 [pbn_b0_2_1130000] = {
2787 .flags = FL_BASE0,
2788 .num_ports = 2,
2789 .base_baud = 1130000,
2790 .uart_offset = 8,
2791 },
2792
fbc0dc0d
AP		 2793 [pbn_b0_4_1152000] = {
2794 .flags = FL_BASE0,
2795 .num_ports = 4,
2796 .base_baud = 1152000,
2797 .uart_offset = 8,
2798 },
1da177e4 2799
14faa8cc
MS		 2800 [pbn_b0_2_1152000_200] = {
2801 .flags = FL_BASE0,
2802 .num_ports = 2,
2803 .base_baud = 1152000,
2804 .uart_offset = 0x200,
2805 },
2806
2807 [pbn_b0_4_1152000_200] = {
2808 .flags = FL_BASE0,
2809 .num_ports = 4,
2810 .base_baud = 1152000,
2811 .uart_offset = 0x200,
2812 },
2813
2814 [pbn_b0_8_1152000_200] = {
2815 .flags = FL_BASE0,
4f7d67d0 2816 .num_ports = 8,
14faa8cc
MS		 2817 .base_baud = 1152000,
2818 .uart_offset = 0x200,
2819 },
2820
26e92861
GH		 2821 [pbn_b0_2_1843200] = {
2822 .flags = FL_BASE0,
2823 .num_ports = 2,
2824 .base_baud = 1843200,
2825 .uart_offset = 8,
2826 },
2827 [pbn_b0_4_1843200] = {
2828 .flags = FL_BASE0,
2829 .num_ports = 4,
2830 .base_baud = 1843200,
2831 .uart_offset = 8,
2832 },
2833
2834 [pbn_b0_2_1843200_200] = {
2835 .flags = FL_BASE0,
2836 .num_ports = 2,
2837 .base_baud = 1843200,
2838 .uart_offset = 0x200,
2839 },
2840 [pbn_b0_4_1843200_200] = {
2841 .flags = FL_BASE0,
2842 .num_ports = 4,
2843 .base_baud = 1843200,
2844 .uart_offset = 0x200,
2845 },
2846 [pbn_b0_8_1843200_200] = {
2847 .flags = FL_BASE0,
2848 .num_ports = 8,
2849 .base_baud = 1843200,
2850 .uart_offset = 0x200,
2851 },
7106b4e3
LH		 2852 [pbn_b0_1_4000000] = {
2853 .flags = FL_BASE0,
2854 .num_ports = 1,
2855 .base_baud = 4000000,
2856 .uart_offset = 8,
2857 },
26e92861 2858
1da177e4
LT		 2859 [pbn_b0_bt_1_115200] = {
2860 .flags = FL_BASE0|FL_BASE_BARS,
2861 .num_ports = 1,
2862 .base_baud = 115200,
2863 .uart_offset = 8,
2864 },
2865 [pbn_b0_bt_2_115200] = {
2866 .flags = FL_BASE0|FL_BASE_BARS,
2867 .num_ports = 2,
2868 .base_baud = 115200,
2869 .uart_offset = 8,
2870 },
ac6ec5b1
IS		 2871 [pbn_b0_bt_4_115200] = {
2872 .flags = FL_BASE0|FL_BASE_BARS,
2873 .num_ports = 4,
2874 .base_baud = 115200,
2875 .uart_offset = 8,
2876 },
1da177e4
LT		 2877 [pbn_b0_bt_8_115200] = {
2878 .flags = FL_BASE0|FL_BASE_BARS,
2879 .num_ports = 8,
2880 .base_baud = 115200,
2881 .uart_offset = 8,
2882 },
2883
2884 [pbn_b0_bt_1_460800] = {
2885 .flags = FL_BASE0|FL_BASE_BARS,
2886 .num_ports = 1,
2887 .base_baud = 460800,
2888 .uart_offset = 8,
2889 },
2890 [pbn_b0_bt_2_460800] = {
2891 .flags = FL_BASE0|FL_BASE_BARS,
2892 .num_ports = 2,
2893 .base_baud = 460800,
2894 .uart_offset = 8,
2895 },
2896 [pbn_b0_bt_4_460800] = {
2897 .flags = FL_BASE0|FL_BASE_BARS,
2898 .num_ports = 4,
2899 .base_baud = 460800,
2900 .uart_offset = 8,
2901 },
2902
2903 [pbn_b0_bt_1_921600] = {
2904 .flags = FL_BASE0|FL_BASE_BARS,
2905 .num_ports = 1,
2906 .base_baud = 921600,
2907 .uart_offset = 8,
2908 },
2909 [pbn_b0_bt_2_921600] = {
2910 .flags = FL_BASE0|FL_BASE_BARS,
2911 .num_ports = 2,
2912 .base_baud = 921600,
2913 .uart_offset = 8,
2914 },
2915 [pbn_b0_bt_4_921600] = {
2916 .flags = FL_BASE0|FL_BASE_BARS,
2917 .num_ports = 4,
2918 .base_baud = 921600,
2919 .uart_offset = 8,
2920 },
2921 [pbn_b0_bt_8_921600] = {
2922 .flags = FL_BASE0|FL_BASE_BARS,
2923 .num_ports = 8,
2924 .base_baud = 921600,
2925 .uart_offset = 8,
2926 },
2927
2928 [pbn_b1_1_115200] = {
2929 .flags = FL_BASE1,
2930 .num_ports = 1,
2931 .base_baud = 115200,
2932 .uart_offset = 8,
2933 },
2934 [pbn_b1_2_115200] = {
2935 .flags = FL_BASE1,
2936 .num_ports = 2,
2937 .base_baud = 115200,
2938 .uart_offset = 8,
2939 },
2940 [pbn_b1_4_115200] = {
2941 .flags = FL_BASE1,
2942 .num_ports = 4,
2943 .base_baud = 115200,
2944 .uart_offset = 8,
2945 },
2946 [pbn_b1_8_115200] = {
2947 .flags = FL_BASE1,
2948 .num_ports = 8,
2949 .base_baud = 115200,
2950 .uart_offset = 8,
2951 },
04bf7e74
WP		 2952 [pbn_b1_16_115200] = {
2953 .flags = FL_BASE1,
2954 .num_ports = 16,
2955 .base_baud = 115200,
2956 .uart_offset = 8,
2957 },
1da177e4
LT		 2958
2959 [pbn_b1_1_921600] = {
2960 .flags = FL_BASE1,
2961 .num_ports = 1,
2962 .base_baud = 921600,
2963 .uart_offset = 8,
2964 },
2965 [pbn_b1_2_921600] = {
2966 .flags = FL_BASE1,
2967 .num_ports = 2,
2968 .base_baud = 921600,
2969 .uart_offset = 8,
2970 },
2971 [pbn_b1_4_921600] = {
2972 .flags = FL_BASE1,
2973 .num_ports = 4,
2974 .base_baud = 921600,
2975 .uart_offset = 8,
2976 },
2977 [pbn_b1_8_921600] = {
2978 .flags = FL_BASE1,
2979 .num_ports = 8,
2980 .base_baud = 921600,
2981 .uart_offset = 8,
2982 },
26e92861
GH		 2983 [pbn_b1_2_1250000] = {
2984 .flags = FL_BASE1,
2985 .num_ports = 2,
2986 .base_baud = 1250000,
2987 .uart_offset = 8,
2988 },
1da177e4 2989
84f8c6fc
NV		 2990 [pbn_b1_bt_1_115200] = {
2991 .flags = FL_BASE1|FL_BASE_BARS,
2992 .num_ports = 1,
2993 .base_baud = 115200,
2994 .uart_offset = 8,
2995 },
04bf7e74
WP		 2996 [pbn_b1_bt_2_115200] = {
2997 .flags = FL_BASE1|FL_BASE_BARS,
2998 .num_ports = 2,
2999 .base_baud = 115200,
3000 .uart_offset = 8,
3001 },
3002 [pbn_b1_bt_4_115200] = {
3003 .flags = FL_BASE1|FL_BASE_BARS,
3004 .num_ports = 4,
3005 .base_baud = 115200,
3006 .uart_offset = 8,
3007 },
84f8c6fc 3008
1da177e4
LT		 3009 [pbn_b1_bt_2_921600] = {
3010 .flags = FL_BASE1|FL_BASE_BARS,
3011 .num_ports = 2,
3012 .base_baud = 921600,
3013 .uart_offset = 8,
3014 },
3015
3016 [pbn_b1_1_1382400] = {
3017 .flags = FL_BASE1,
3018 .num_ports = 1,
3019 .base_baud = 1382400,
3020 .uart_offset = 8,
3021 },
3022 [pbn_b1_2_1382400] = {
3023 .flags = FL_BASE1,
3024 .num_ports = 2,
3025 .base_baud = 1382400,
3026 .uart_offset = 8,
3027 },
3028 [pbn_b1_4_1382400] = {
3029 .flags = FL_BASE1,
3030 .num_ports = 4,
3031 .base_baud = 1382400,
3032 .uart_offset = 8,
3033 },
3034 [pbn_b1_8_1382400] = {
3035 .flags = FL_BASE1,
3036 .num_ports = 8,
3037 .base_baud = 1382400,
3038 .uart_offset = 8,
3039 },
3040
3041 [pbn_b2_1_115200] = {
3042 .flags = FL_BASE2,
3043 .num_ports = 1,
3044 .base_baud = 115200,
3045 .uart_offset = 8,
3046 },
737c1756
PH		 3047 [pbn_b2_2_115200] = {
3048 .flags = FL_BASE2,
3049 .num_ports = 2,
3050 .base_baud = 115200,
3051 .uart_offset = 8,
3052 },
a9cccd34
MF		 3053 [pbn_b2_4_115200] = {
3054 .flags = FL_BASE2,
3055 .num_ports = 4,
3056 .base_baud = 115200,
3057 .uart_offset = 8,
3058 },
1da177e4
LT		 3059 [pbn_b2_8_115200] = {
3060 .flags = FL_BASE2,
3061 .num_ports = 8,
3062 .base_baud = 115200,
3063 .uart_offset = 8,
3064 },
3065
3066 [pbn_b2_1_460800] = {
3067 .flags = FL_BASE2,
3068 .num_ports = 1,
3069 .base_baud = 460800,
3070 .uart_offset = 8,
3071 },
3072 [pbn_b2_4_460800] = {
3073 .flags = FL_BASE2,
3074 .num_ports = 4,
3075 .base_baud = 460800,
3076 .uart_offset = 8,
3077 },
3078 [pbn_b2_8_460800] = {
3079 .flags = FL_BASE2,
3080 .num_ports = 8,
3081 .base_baud = 460800,
3082 .uart_offset = 8,
3083 },
3084 [pbn_b2_16_460800] = {
3085 .flags = FL_BASE2,
3086 .num_ports = 16,
3087 .base_baud = 460800,
3088 .uart_offset = 8,
3089 },
3090
3091 [pbn_b2_1_921600] = {
3092 .flags = FL_BASE2,
3093 .num_ports = 1,
3094 .base_baud = 921600,
3095 .uart_offset = 8,
3096 },
3097 [pbn_b2_4_921600] = {
3098 .flags = FL_BASE2,
3099 .num_ports = 4,
3100 .base_baud = 921600,
3101 .uart_offset = 8,
3102 },
3103 [pbn_b2_8_921600] = {
3104 .flags = FL_BASE2,
3105 .num_ports = 8,
3106 .base_baud = 921600,
3107 .uart_offset = 8,
3108 },
3109
e847003f
LB		 3110 [pbn_b2_8_1152000] = {
3111 .flags = FL_BASE2,
3112 .num_ports = 8,
3113 .base_baud = 1152000,
3114 .uart_offset = 8,
3115 },
3116
1da177e4
LT		 3117 [pbn_b2_bt_1_115200] = {
3118 .flags = FL_BASE2|FL_BASE_BARS,
3119 .num_ports = 1,
3120 .base_baud = 115200,
3121 .uart_offset = 8,
3122 },
3123 [pbn_b2_bt_2_115200] = {
3124 .flags = FL_BASE2|FL_BASE_BARS,
3125 .num_ports = 2,
3126 .base_baud = 115200,
3127 .uart_offset = 8,
3128 },
3129 [pbn_b2_bt_4_115200] = {
3130 .flags = FL_BASE2|FL_BASE_BARS,
3131 .num_ports = 4,
3132 .base_baud = 115200,
3133 .uart_offset = 8,
3134 },
3135
3136 [pbn_b2_bt_2_921600] = {
3137 .flags = FL_BASE2|FL_BASE_BARS,
3138 .num_ports = 2,
3139 .base_baud = 921600,
3140 .uart_offset = 8,
3141 },
3142 [pbn_b2_bt_4_921600] = {
3143 .flags = FL_BASE2|FL_BASE_BARS,
3144 .num_ports = 4,
3145 .base_baud = 921600,
3146 .uart_offset = 8,
3147 },
3148
d9004eb4
ABL		 3149 [pbn_b3_2_115200] = {
3150 .flags = FL_BASE3,
3151 .num_ports = 2,
3152 .base_baud = 115200,
3153 .uart_offset = 8,
3154 },
1da177e4
LT		 3155 [pbn_b3_4_115200] = {
3156 .flags = FL_BASE3,
3157 .num_ports = 4,
3158 .base_baud = 115200,
3159 .uart_offset = 8,
3160 },
3161 [pbn_b3_8_115200] = {
3162 .flags = FL_BASE3,
3163 .num_ports = 8,
3164 .base_baud = 115200,
3165 .uart_offset = 8,
3166 },
3167
66169ad1
YY		 3168 [pbn_b4_bt_2_921600] = {
3169 .flags = FL_BASE4,
3170 .num_ports = 2,
3171 .base_baud = 921600,
3172 .uart_offset = 8,
3173 },
3174 [pbn_b4_bt_4_921600] = {
3175 .flags = FL_BASE4,
3176 .num_ports = 4,
3177 .base_baud = 921600,
3178 .uart_offset = 8,
3179 },
3180 [pbn_b4_bt_8_921600] = {
3181 .flags = FL_BASE4,
3182 .num_ports = 8,
3183 .base_baud = 921600,
3184 .uart_offset = 8,
3185 },
3186
1da177e4
LT		 3187 /*
3188 * Entries following this are board-specific.
3189 */
3190
3191 /*
3192 * Panacom - IOMEM
3193 */
3194 [pbn_panacom] = {
3195 .flags = FL_BASE2,
3196 .num_ports = 2,
3197 .base_baud = 921600,
3198 .uart_offset = 0x400,
3199 .reg_shift = 7,
3200 },
3201 [pbn_panacom2] = {
3202 .flags = FL_BASE2|FL_BASE_BARS,
3203 .num_ports = 2,
3204 .base_baud = 921600,
3205 .uart_offset = 0x400,
3206 .reg_shift = 7,
3207 },
3208 [pbn_panacom4] = {
3209 .flags = FL_BASE2|FL_BASE_BARS,
3210 .num_ports = 4,
3211 .base_baud = 921600,
3212 .uart_offset = 0x400,
3213 .reg_shift = 7,
3214 },
3215
3216 /* I think this entry is broken - the first_offset looks wrong --rmk */
3217 [pbn_plx_romulus] = {
3218 .flags = FL_BASE2,
3219 .num_ports = 4,
3220 .base_baud = 921600,
3221 .uart_offset = 8 << 2,
3222 .reg_shift = 2,
3223 .first_offset = 0x03,
3224 },
3225
3226 /*
3227 * This board uses the size of PCI Base region 0 to
3228 * signal now many ports are available
3229 */
3230 [pbn_oxsemi] = {
3231 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3232 .num_ports = 32,
3233 .base_baud = 115200,
3234 .uart_offset = 8,
3235 },
7106b4e3
LH		 3236 [pbn_oxsemi_1_4000000] = {
3237 .flags = FL_BASE0,
3238 .num_ports = 1,
3239 .base_baud = 4000000,
3240 .uart_offset = 0x200,
3241 .first_offset = 0x1000,
3242 },
3243 [pbn_oxsemi_2_4000000] = {
3244 .flags = FL_BASE0,
3245 .num_ports = 2,
3246 .base_baud = 4000000,
3247 .uart_offset = 0x200,
3248 .first_offset = 0x1000,
3249 },
3250 [pbn_oxsemi_4_4000000] = {
3251 .flags = FL_BASE0,
3252 .num_ports = 4,
3253 .base_baud = 4000000,
3254 .uart_offset = 0x200,
3255 .first_offset = 0x1000,
3256 },
3257 [pbn_oxsemi_8_4000000] = {
3258 .flags = FL_BASE0,
3259 .num_ports = 8,
3260 .base_baud = 4000000,
3261 .uart_offset = 0x200,
3262 .first_offset = 0x1000,
3263 },
3264
1da177e4
LT		 3265
3266 /*
3267 * EKF addition for i960 Boards form EKF with serial port.
3268 * Max 256 ports.
3269 */
3270 [pbn_intel_i960] = {
3271 .flags = FL_BASE0,
3272 .num_ports = 32,
3273 .base_baud = 921600,
3274 .uart_offset = 8 << 2,
3275 .reg_shift = 2,
3276 .first_offset = 0x10000,
3277 },
3278 [pbn_sgi_ioc3] = {
3279 .flags = FL_BASE0|FL_NOIRQ,
3280 .num_ports = 1,
3281 .base_baud = 458333,
3282 .uart_offset = 8,
3283 .reg_shift = 0,
3284 .first_offset = 0x20178,
3285 },
3286
1da177e4
LT		 3287 /*
3288 * Computone - uses IOMEM.
3289 */
3290 [pbn_computone_4] = {
3291 .flags = FL_BASE0,
3292 .num_ports = 4,
3293 .base_baud = 921600,
3294 .uart_offset = 0x40,
3295 .reg_shift = 2,
3296 .first_offset = 0x200,
3297 },
3298 [pbn_computone_6] = {
3299 .flags = FL_BASE0,
3300 .num_ports = 6,
3301 .base_baud = 921600,
3302 .uart_offset = 0x40,
3303 .reg_shift = 2,
3304 .first_offset = 0x200,
3305 },
3306 [pbn_computone_8] = {
3307 .flags = FL_BASE0,
3308 .num_ports = 8,
3309 .base_baud = 921600,
3310 .uart_offset = 0x40,
3311 .reg_shift = 2,
3312 .first_offset = 0x200,
3313 },
3314 [pbn_sbsxrsio] = {
3315 .flags = FL_BASE0,
3316 .num_ports = 8,
3317 .base_baud = 460800,
3318 .uart_offset = 256,
3319 .reg_shift = 4,
3320 },
3321 /*
3322 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3323 * Only basic 16550A support.
3324 * XR17C15[24] are not tested, but they should work.
3325 */
3326 [pbn_exar_XR17C152] = {
3327 .flags = FL_BASE0,
3328 .num_ports = 2,
3329 .base_baud = 921600,
3330 .uart_offset = 0x200,
3331 },
3332 [pbn_exar_XR17C154] = {
3333 .flags = FL_BASE0,
3334 .num_ports = 4,
3335 .base_baud = 921600,
3336 .uart_offset = 0x200,
3337 },
3338 [pbn_exar_XR17C158] = {
3339 .flags = FL_BASE0,
3340 .num_ports = 8,
3341 .base_baud = 921600,
3342 .uart_offset = 0x200,
3343 },
dc96efb7
MS		 3344 [pbn_exar_XR17V352] = {
3345 .flags = FL_BASE0,
3346 .num_ports = 2,
3347 .base_baud = 7812500,
3348 .uart_offset = 0x400,
3349 .reg_shift = 0,
3350 .first_offset = 0,
3351 },
3352 [pbn_exar_XR17V354] = {
3353 .flags = FL_BASE0,
3354 .num_ports = 4,
3355 .base_baud = 7812500,
3356 .uart_offset = 0x400,
3357 .reg_shift = 0,
3358 .first_offset = 0,
3359 },
3360 [pbn_exar_XR17V358] = {
3361 .flags = FL_BASE0,
3362 .num_ports = 8,
3363 .base_baud = 7812500,
3364 .uart_offset = 0x400,
3365 .reg_shift = 0,
3366 .first_offset = 0,
3367 },
c68d2b15
BH		 3368 [pbn_exar_ibm_saturn] = {
3369 .flags = FL_BASE0,
3370 .num_ports = 1,
3371 .base_baud = 921600,
3372 .uart_offset = 0x200,
3373 },
3374
aa798505
OJ		 3375 /*
3376 * PA Semi PWRficient PA6T-1682M on-chip UART
3377 */
3378 [pbn_pasemi_1682M] = {
3379 .flags = FL_BASE0,
3380 .num_ports = 1,
3381 .base_baud = 8333333,
3382 },
46a0fac9
SB		 3383 /*
3384 * National Instruments 843x
3385 */
3386 [pbn_ni8430_16] = {
3387 .flags = FL_BASE0,
3388 .num_ports = 16,
3389 .base_baud = 3686400,
3390 .uart_offset = 0x10,
3391 .first_offset = 0x800,
3392 },
3393 [pbn_ni8430_8] = {
3394 .flags = FL_BASE0,
3395 .num_ports = 8,
3396 .base_baud = 3686400,
3397 .uart_offset = 0x10,
3398 .first_offset = 0x800,
3399 },
3400 [pbn_ni8430_4] = {
3401 .flags = FL_BASE0,
3402 .num_ports = 4,
3403 .base_baud = 3686400,
3404 .uart_offset = 0x10,
3405 .first_offset = 0x800,
3406 },
3407 [pbn_ni8430_2] = {
3408 .flags = FL_BASE0,
3409 .num_ports = 2,
3410 .base_baud = 3686400,
3411 .uart_offset = 0x10,
3412 .first_offset = 0x800,
3413 },
1b62cbf2
KJ		 3414 /*
3415 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3416 */
3417 [pbn_ADDIDATA_PCIe_1_3906250] = {
3418 .flags = FL_BASE0,
3419 .num_ports = 1,
3420 .base_baud = 3906250,
3421 .uart_offset = 0x200,
3422 .first_offset = 0x1000,
3423 },
3424 [pbn_ADDIDATA_PCIe_2_3906250] = {
3425 .flags = FL_BASE0,
3426 .num_ports = 2,
3427 .base_baud = 3906250,
3428 .uart_offset = 0x200,
3429 .first_offset = 0x1000,
3430 },
3431 [pbn_ADDIDATA_PCIe_4_3906250] = {
3432 .flags = FL_BASE0,
3433 .num_ports = 4,
3434 .base_baud = 3906250,
3435 .uart_offset = 0x200,
3436 .first_offset = 0x1000,
3437 },
3438 [pbn_ADDIDATA_PCIe_8_3906250] = {
3439 .flags = FL_BASE0,
3440 .num_ports = 8,
3441 .base_baud = 3906250,
3442 .uart_offset = 0x200,
3443 .first_offset = 0x1000,
3444 },
095e24b0 3445 [pbn_ce4100_1_115200] = {
08ec212c
MB		 3446 .flags = FL_BASE_BARS,
3447 .num_ports = 2,
095e24b0
DB		 3448 .base_baud = 921600,
3449 .reg_shift = 2,
3450 },
b15e5691
HK		 3451 [pbn_byt] = {
3452 .flags = FL_BASE0,
3453 .num_ports = 1,
3454 .base_baud = 2764800,
3455 .uart_offset = 0x80,
3456 .reg_shift = 2,
3457 },
d9a0fbfd
AP		 3458 [pbn_omegapci] = {
3459 .flags = FL_BASE0,
3460 .num_ports = 8,
3461 .base_baud = 115200,
3462 .uart_offset = 0x200,
3463 },
7808edcd
NG		 3464 [pbn_NETMOS9900_2s_115200] = {
3465 .flags = FL_BASE0,
3466 .num_ports = 2,
3467 .base_baud = 115200,
3468 },
ebebd49a
SH		 3469 [pbn_brcm_trumanage] = {
3470 .flags = FL_BASE0,
3471 .num_ports = 1,
3472 .reg_shift = 2,
3473 .base_baud = 115200,
3474 },
2c62a3c8
GKH		 3475 [pbn_fintek_4] = {
3476 .num_ports = 4,
3477 .uart_offset = 8,
3478 .base_baud = 115200,
3479 .first_offset = 0x40,
3480 },
3481 [pbn_fintek_8] = {
3482 .num_ports = 8,
3483 .uart_offset = 8,
3484 .base_baud = 115200,
3485 .first_offset = 0x40,
3486 },
3487 [pbn_fintek_12] = {
3488 .num_ports = 12,
3489 .uart_offset = 8,
3490 .base_baud = 115200,
3491 .first_offset = 0x40,
3492 },
1da177e4
LT		 3493};
3494
6971c635
GA		 3495static const struct pci_device_id blacklist[] = {
3496 /* softmodems */
5756ee99 3497 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 3498 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3499 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
6971c635
GA		 3500
3501 /* multi-io cards handled by parport_serial */
3502 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
436bbd43
CS		 3503};
3504
1da177e4
LT		 3505/*
3506 * Given a complete unknown PCI device, try to use some heuristics to
3507 * guess what the configuration might be, based on the pitiful PCI
3508 * serial specs. Returns 0 on success, 1 on failure.
3509 */
9671f099 3510static int
1c7c1fe5 3511serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 3512{
6971c635 3513 const struct pci_device_id *bldev;
1da177e4 3514 int num_iomem, num_port, first_port = -1, i;
5756ee99 3515
1da177e4
LT		 3516 /*
3517 * If it is not a communications device or the programming
3518 * interface is greater than 6, give up.
3519 *
3520 * (Should we try to make guesses for multiport serial devices
5756ee99 3521 * later?)
1da177e4
LT		 3522 */
3523 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3524 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3525 (dev->class & 0xff) > 6)
3526 return -ENODEV;
3527
436bbd43
CS		 3528 /*
3529 * Do not access blacklisted devices that are known not to
6971c635 3530 * feature serial ports or are handled by other modules.
436bbd43 3531 */
6971c635
GA		 3532 for (bldev = blacklist;
3533 bldev < blacklist + ARRAY_SIZE(blacklist);
3534 bldev++) {
3535 if (dev->vendor == bldev->vendor &&
3536 dev->device == bldev->device)
436bbd43
CS		 3537 return -ENODEV;
3538 }
3539
1da177e4
LT		 3540 num_iomem = num_port = 0;
3541 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3542 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3543 num_port++;
3544 if (first_port == -1)
3545 first_port = i;
3546 }
3547 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3548 num_iomem++;
3549 }
3550
3551 /*
3552 * If there is 1 or 0 iomem regions, and exactly one port,
3553 * use it. We guess the number of ports based on the IO
3554 * region size.
3555 */
3556 if (num_iomem <= 1 && num_port == 1) {
3557 board->flags = first_port;
3558 board->num_ports = pci_resource_len(dev, first_port) / 8;
3559 return 0;
3560 }
3561
3562 /*
3563 * Now guess if we've got a board which indexes by BARs.
3564 * Each IO BAR should be 8 bytes, and they should follow
3565 * consecutively.
3566 */
3567 first_port = -1;
3568 num_port = 0;
3569 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3570 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3571 pci_resource_len(dev, i) == 8 &&
3572 (first_port == -1 || (first_port + num_port) == i)) {
3573 num_port++;
3574 if (first_port == -1)
3575 first_port = i;
3576 }
3577 }
3578
3579 if (num_port > 1) {
3580 board->flags = first_port | FL_BASE_BARS;
3581 board->num_ports = num_port;
3582 return 0;
3583 }
3584
3585 return -ENODEV;
3586}
3587
3588static inline int
975a1a7d
RK		 3589serial_pci_matches(const struct pciserial_board *board,
3590 const struct pciserial_board *guessed)
1da177e4
LT		 3591{
3592 return
3593 board->num_ports == guessed->num_ports &&
3594 board->base_baud == guessed->base_baud &&
3595 board->uart_offset == guessed->uart_offset &&
3596 board->reg_shift == guessed->reg_shift &&
3597 board->first_offset == guessed->first_offset;
3598}
3599
241fc436 3600struct serial_private *
975a1a7d 3601pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 3602{
2655a2c7 3603 struct uart_8250_port uart;
1da177e4 3604 struct serial_private *priv;
1da177e4
LT		 3605 struct pci_serial_quirk *quirk;
3606 int rc, nr_ports, i;
3607
1da177e4
LT		 3608 nr_ports = board->num_ports;
3609
3610 /*
3611 * Find an init and setup quirks.
3612 */
3613 quirk = find_quirk(dev);
3614
3615 /*
3616 * Run the new-style initialization function.
3617 * The initialization function returns:
3618 * <0 - error
3619 * 0 - use board->num_ports
3620 * >0 - number of ports
3621 */
3622 if (quirk->init) {
3623 rc = quirk->init(dev);
241fc436
RK		 3624 if (rc < 0) {
3625 priv = ERR_PTR(rc);
3626 goto err_out;
3627 }
1da177e4
LT		 3628 if (rc)
3629 nr_ports = rc;
3630 }
3631
8f31bb39 3632 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 3633 sizeof(unsigned int) * nr_ports,
3634 GFP_KERNEL);
3635 if (!priv) {
241fc436
RK		 3636 priv = ERR_PTR(-ENOMEM);
3637 goto err_deinit;
1da177e4
LT		 3638 }
3639
70db3d91 3640 priv->dev = dev;
1da177e4 3641 priv->quirk = quirk;
1da177e4 3642
2655a2c7
AC		 3643 memset(&uart, 0, sizeof(uart));
3644 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3645 uart.port.uartclk = board->base_baud * 16;
3646 uart.port.irq = get_pci_irq(dev, board);
3647 uart.port.dev = &dev->dev;
72ce9a83 3648
1da177e4 3649 for (i = 0; i < nr_ports; i++) {
2655a2c7 3650 if (quirk->setup(priv, board, &uart, i))
1da177e4 3651 break;
72ce9a83 3652
af8c5b8d
GKH		 3653 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3654 uart.port.iobase, uart.port.irq, uart.port.iotype);
5756ee99 3655
2655a2c7 3656 priv->line[i] = serial8250_register_8250_port(&uart);
1da177e4 3657 if (priv->line[i] < 0) {
af8c5b8d
GKH		 3658 dev_err(&dev->dev,
3659 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3660 uart.port.iobase, uart.port.irq,
3661 uart.port.iotype, priv->line[i]);
1da177e4
LT		 3662 break;
3663 }
3664 }
1da177e4 3665 priv->nr = i;
241fc436 3666 return priv;
1da177e4 3667
5756ee99 3668err_deinit:
1da177e4
LT		 3669 if (quirk->exit)
3670 quirk->exit(dev);
5756ee99 3671err_out:
241fc436 3672 return priv;
1da177e4 3673}
241fc436 3674EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 3675
241fc436 3676void pciserial_remove_ports(struct serial_private *priv)
1da177e4 3677{
056a8763
RK		 3678 struct pci_serial_quirk *quirk;
3679 int i;
1da177e4 3680
056a8763
RK		 3681 for (i = 0; i < priv->nr; i++)
3682 serial8250_unregister_port(priv->line[i]);
1da177e4 3683
056a8763
RK		 3684 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3685 if (priv->remapped_bar[i])
3686 iounmap(priv->remapped_bar[i]);
3687 priv->remapped_bar[i] = NULL;
3688 }
1da177e4 3689
056a8763
RK		 3690 /*
3691 * Find the exit quirks.
3692 */
241fc436 3693 quirk = find_quirk(priv->dev);
056a8763 3694 if (quirk->exit)
241fc436
RK		 3695 quirk->exit(priv->dev);
3696
3697 kfree(priv);
3698}
3699EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3700
3701void pciserial_suspend_ports(struct serial_private *priv)
3702{
3703 int i;
3704
3705 for (i = 0; i < priv->nr; i++)
3706 if (priv->line[i] >= 0)
3707 serial8250_suspend_port(priv->line[i]);
5f1a3895
DW		 3708
3709 /*
3710 * Ensure that every init quirk is properly torn down
3711 */
3712 if (priv->quirk->exit)
3713 priv->quirk->exit(priv->dev);
241fc436
RK		 3714}
3715EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3716
3717void pciserial_resume_ports(struct serial_private *priv)
3718{
3719 int i;
3720
3721 /*
3722 * Ensure that the board is correctly configured.
3723 */
3724 if (priv->quirk->init)
3725 priv->quirk->init(priv->dev);
3726
3727 for (i = 0; i < priv->nr; i++)
3728 if (priv->line[i] >= 0)
3729 serial8250_resume_port(priv->line[i]);
3730}
3731EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3732
3733/*
3734 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3735 * to the arrangement of serial ports on a PCI card.
3736 */
9671f099 3737static int
241fc436
RK		 3738pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3739{
5bf8f501 3740 struct pci_serial_quirk *quirk;
241fc436 3741 struct serial_private *priv;
975a1a7d
RK		 3742 const struct pciserial_board *board;
3743 struct pciserial_board tmp;
241fc436
RK		 3744 int rc;
3745
5bf8f501
FB		 3746 quirk = find_quirk(dev);
3747 if (quirk->probe) {
3748 rc = quirk->probe(dev);
3749 if (rc)
3750 return rc;
3751 }
3752
241fc436 3753 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
af8c5b8d 3754 dev_err(&dev->dev, "invalid driver_data: %ld\n",
241fc436
RK		 3755 ent->driver_data);
3756 return -EINVAL;
3757 }
3758
3759 board = &pci_boards[ent->driver_data];
3760
3761 rc = pci_enable_device(dev);
2807190b 3762 pci_save_state(dev);
241fc436
RK		 3763 if (rc)
3764 return rc;
3765
3766 if (ent->driver_data == pbn_default) {
3767 /*
3768 * Use a copy of the pci_board entry for this;
3769 * avoid changing entries in the table.
3770 */
3771 memcpy(&tmp, board, sizeof(struct pciserial_board));
3772 board = &tmp;
3773
3774 /*
3775 * We matched one of our class entries. Try to
3776 * determine the parameters of this board.
3777 */
975a1a7d 3778 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 3779 if (rc)
3780 goto disable;
3781 } else {
3782 /*
3783 * We matched an explicit entry. If we are able to
3784 * detect this boards settings with our heuristic,
3785 * then we no longer need this entry.
3786 */
3787 memcpy(&tmp, &pci_boards[pbn_default],
3788 sizeof(struct pciserial_board));
3789 rc = serial_pci_guess_board(dev, &tmp);
3790 if (rc == 0 && serial_pci_matches(board, &tmp))
3791 moan_device("Redundant entry in serial pci_table.",
3792 dev);
3793 }
3794
3795 priv = pciserial_init_ports(dev, board);
3796 if (!IS_ERR(priv)) {
3797 pci_set_drvdata(dev, priv);
3798 return 0;
3799 }
3800
3801 rc = PTR_ERR(priv);
1da177e4 3802
241fc436 3803 disable:
056a8763 3804 pci_disable_device(dev);
241fc436
RK		 3805 return rc;
3806}
1da177e4 3807
ae8d8a14 3808static void pciserial_remove_one(struct pci_dev *dev)
241fc436
RK		 3809{
3810 struct serial_private *priv = pci_get_drvdata(dev);
3811
241fc436
RK		 3812 pciserial_remove_ports(priv);
3813
3814 pci_disable_device(dev);
1da177e4
LT		 3815}
3816
1d5e7996 3817#ifdef CONFIG_PM
1da177e4
LT		 3818static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3819{
3820 struct serial_private *priv = pci_get_drvdata(dev);
3821
241fc436
RK		 3822 if (priv)
3823 pciserial_suspend_ports(priv);
1da177e4 3824
1da177e4
LT		 3825 pci_save_state(dev);
3826 pci_set_power_state(dev, pci_choose_state(dev, state));
3827 return 0;
3828}
3829
3830static int pciserial_resume_one(struct pci_dev *dev)
3831{
ccb9d59e 3832 int err;
1da177e4
LT		 3833 struct serial_private *priv = pci_get_drvdata(dev);
3834
3835 pci_set_power_state(dev, PCI_D0);
3836 pci_restore_state(dev);
3837
3838 if (priv) {
1da177e4
LT		 3839 /*
3840 * The device may have been disabled. Re-enable it.
3841 */
ccb9d59e 3842 err = pci_enable_device(dev);
40836c48 3843 /* FIXME: We cannot simply error out here */
ccb9d59e 3844 if (err)
af8c5b8d 3845 dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n");
241fc436 3846 pciserial_resume_ports(priv);
1da177e4
LT		 3847 }
3848 return 0;
3849}
1d5e7996 3850#endif
1da177e4
LT		 3851
3852static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 3853 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3854 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3855 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3856 pbn_b2_8_921600 },
1da177e4
LT		 3857 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3858 PCI_SUBVENDOR_ID_CONNECT_TECH,
3859 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3860 pbn_b1_8_1382400 },
3861 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3862 PCI_SUBVENDOR_ID_CONNECT_TECH,
3863 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3864 pbn_b1_4_1382400 },
3865 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3866 PCI_SUBVENDOR_ID_CONNECT_TECH,
3867 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3868 pbn_b1_2_1382400 },
3869 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3870 PCI_SUBVENDOR_ID_CONNECT_TECH,
3871 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3872 pbn_b1_8_1382400 },
3873 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3874 PCI_SUBVENDOR_ID_CONNECT_TECH,
3875 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3876 pbn_b1_4_1382400 },
3877 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3878 PCI_SUBVENDOR_ID_CONNECT_TECH,
3879 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3880 pbn_b1_2_1382400 },
3881 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3882 PCI_SUBVENDOR_ID_CONNECT_TECH,
3883 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3884 pbn_b1_8_921600 },
3885 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3886 PCI_SUBVENDOR_ID_CONNECT_TECH,
3887 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3888 pbn_b1_8_921600 },
3889 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3890 PCI_SUBVENDOR_ID_CONNECT_TECH,
3891 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3892 pbn_b1_4_921600 },
3893 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3894 PCI_SUBVENDOR_ID_CONNECT_TECH,
3895 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3896 pbn_b1_4_921600 },
3897 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3898 PCI_SUBVENDOR_ID_CONNECT_TECH,
3899 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3900 pbn_b1_2_921600 },
3901 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3902 PCI_SUBVENDOR_ID_CONNECT_TECH,
3903 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3904 pbn_b1_8_921600 },
3905 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3906 PCI_SUBVENDOR_ID_CONNECT_TECH,
3907 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3908 pbn_b1_8_921600 },
3909 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3910 PCI_SUBVENDOR_ID_CONNECT_TECH,
3911 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3912 pbn_b1_4_921600 },
26e92861
GH		 3913 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3914 PCI_SUBVENDOR_ID_CONNECT_TECH,
3915 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3916 pbn_b1_2_1250000 },
3917 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3918 PCI_SUBVENDOR_ID_CONNECT_TECH,
3919 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3920 pbn_b0_2_1843200 },
3921 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3922 PCI_SUBVENDOR_ID_CONNECT_TECH,
3923 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3924 pbn_b0_4_1843200 },
85d1494e
YY		 3925 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3926 PCI_VENDOR_ID_AFAVLAB,
3927 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3928 pbn_b0_4_1152000 },
26e92861
GH		 3929 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3930 PCI_SUBVENDOR_ID_CONNECT_TECH,
3931 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3932 pbn_b0_2_1843200_200 },
3933 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3934 PCI_SUBVENDOR_ID_CONNECT_TECH,
3935 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3936 pbn_b0_4_1843200_200 },
3937 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3938 PCI_SUBVENDOR_ID_CONNECT_TECH,
3939 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3940 pbn_b0_8_1843200_200 },
3941 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3942 PCI_SUBVENDOR_ID_CONNECT_TECH,
3943 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3944 pbn_b0_2_1843200_200 },
3945 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3946 PCI_SUBVENDOR_ID_CONNECT_TECH,
3947 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3948 pbn_b0_4_1843200_200 },
3949 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3950 PCI_SUBVENDOR_ID_CONNECT_TECH,
3951 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3952 pbn_b0_8_1843200_200 },
3953 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3954 PCI_SUBVENDOR_ID_CONNECT_TECH,
3955 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3956 pbn_b0_2_1843200_200 },
3957 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3958 PCI_SUBVENDOR_ID_CONNECT_TECH,
3959 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3960 pbn_b0_4_1843200_200 },
3961 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3962 PCI_SUBVENDOR_ID_CONNECT_TECH,
3963 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3964 pbn_b0_8_1843200_200 },
3965 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3966 PCI_SUBVENDOR_ID_CONNECT_TECH,
3967 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3968 pbn_b0_2_1843200_200 },
3969 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3970 PCI_SUBVENDOR_ID_CONNECT_TECH,
3971 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3972 pbn_b0_4_1843200_200 },
3973 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3974 PCI_SUBVENDOR_ID_CONNECT_TECH,
3975 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3976 pbn_b0_8_1843200_200 },
c68d2b15
BH		 3977 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3978 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3979 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 3980
3981 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 3982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3983 pbn_b2_bt_1_115200 },
3984 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 3985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3986 pbn_b2_bt_2_115200 },
3987 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 3988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3989 pbn_b2_bt_4_115200 },
3990 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 3991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3992 pbn_b2_bt_2_115200 },
3993 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 3994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3995 pbn_b2_bt_4_115200 },
3996 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 3997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3998 pbn_b2_8_115200 },
e65f0f82
FL		 3999 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4001 pbn_b2_8_460800 },
1da177e4
LT		 4002 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4004 pbn_b2_8_115200 },
4005
4006 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4007 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4008 pbn_b2_bt_2_115200 },
4009 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4010 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4011 pbn_b2_bt_2_921600 },
4012 /*
4013 * VScom SPCOM800, from sl@s.pl
4014 */
5756ee99
AC		 4015 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4016 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4017 pbn_b2_8_921600 },
4018 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 4019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 4020 pbn_b2_4_921600 },
b76c5a07
CB		 4021 /* Unknown card - subdevice 0x1584 */
4022 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4023 PCI_VENDOR_ID_PLX,
4024 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
d13402a4
SA		 4025 pbn_b2_4_115200 },
4026 /* Unknown card - subdevice 0x1588 */
4027 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4028 PCI_VENDOR_ID_PLX,
4029 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4030 pbn_b2_8_115200 },
1da177e4
LT		 4031 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4032 PCI_SUBVENDOR_ID_KEYSPAN,
4033 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4034 pbn_panacom },
4035 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4036 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4037 pbn_panacom4 },
4038 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4039 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4040 pbn_panacom2 },
a9cccd34
MF		 4041 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4042 PCI_VENDOR_ID_ESDGMBH,
4043 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4044 pbn_b2_4_115200 },
1da177e4
LT		 4045 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4046 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4047 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 4048 pbn_b2_4_460800 },
4049 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4050 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4051 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 4052 pbn_b2_8_460800 },
4053 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4054 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4055 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 4056 pbn_b2_16_460800 },
4057 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4058 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4059 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 4060 pbn_b2_16_460800 },
4061 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4062 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4063 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 4064 pbn_b2_4_460800 },
4065 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4066 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4067 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 4068 pbn_b2_8_460800 },
add7b58e
BH		 4069 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4070 PCI_SUBVENDOR_ID_EXSYS,
4071 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
ee4cd1b2 4072 pbn_b2_4_115200 },
1da177e4
LT		 4073 /*
4074 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4075 * (Exoray@isys.ca)
4076 */
4077 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4078 0x10b5, 0x106a, 0, 0,
4079 pbn_plx_romulus },
55c7c0fd
AC		 4080 /*
4081 * Quatech cards. These actually have configurable clocks but for
4082 * now we just use the default.
4083 *
4084 * 100 series are RS232, 200 series RS422,
4085 */
1da177e4
LT		 4086 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4088 pbn_b1_4_115200 },
4089 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4091 pbn_b1_2_115200 },
55c7c0fd
AC		 4092 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4094 pbn_b2_2_115200 },
4095 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4097 pbn_b1_2_115200 },
4098 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4100 pbn_b2_2_115200 },
4101 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4103 pbn_b1_4_115200 },
1da177e4
LT		 4104 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4106 pbn_b1_8_115200 },
4107 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4109 pbn_b1_8_115200 },
55c7c0fd
AC		 4110 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4112 pbn_b1_4_115200 },
4113 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4115 pbn_b1_2_115200 },
4116 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4118 pbn_b1_4_115200 },
4119 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4121 pbn_b1_2_115200 },
4122 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4124 pbn_b2_4_115200 },
4125 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4127 pbn_b2_2_115200 },
4128 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4130 pbn_b2_1_115200 },
4131 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4133 pbn_b2_4_115200 },
4134 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4136 pbn_b2_2_115200 },
4137 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4139 pbn_b2_1_115200 },
4140 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4142 pbn_b0_8_115200 },
4143
1da177e4 4144 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4145 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4146 0, 0,
1da177e4 4147 pbn_b0_4_921600 },
fbc0dc0d 4148 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4149 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4150 0, 0,
fbc0dc0d 4151 pbn_b0_4_1152000 },
c9bd9d01
MP		 4152 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4154 pbn_b0_bt_2_921600 },
db1de159
DR		 4155
4156 /*
4157 * The below card is a little controversial since it is the
4158 * subject of a PCI vendor/device ID clash. (See
4159 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4160 * For now just used the hex ID 0x950a.
4161 */
39aced68 4162 { PCI_VENDOR_ID_OXSEMI, 0x950a,
26e8220a
FL		 4163 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4164 0, 0, pbn_b0_2_115200 },
4165 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4166 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4167 0, 0, pbn_b0_2_115200 },
db1de159
DR		 4168 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4170 pbn_b0_2_1130000 },
70fd8fde
AP		 4171 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4172 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4173 pbn_b0_1_921600 },
1da177e4
LT		 4174 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4176 pbn_b0_4_115200 },
4177 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4178 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4179 pbn_b0_bt_2_921600 },
e847003f
LB		 4180 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4181 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4182 pbn_b2_8_1152000 },
1da177e4 4183
7106b4e3
LH		 4184 /*
4185 * Oxford Semiconductor Inc. Tornado PCI express device range.
4186 */
4187 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4188 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4189 pbn_b0_1_4000000 },
4190 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4191 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4192 pbn_b0_1_4000000 },
4193 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4194 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4195 pbn_oxsemi_1_4000000 },
4196 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4197 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4198 pbn_oxsemi_1_4000000 },
4199 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4201 pbn_b0_1_4000000 },
4202 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4204 pbn_b0_1_4000000 },
4205 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4206 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4207 pbn_oxsemi_1_4000000 },
4208 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4210 pbn_oxsemi_1_4000000 },
4211 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4212 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4213 pbn_b0_1_4000000 },
4214 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4215 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4216 pbn_b0_1_4000000 },
4217 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4218 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4219 pbn_b0_1_4000000 },
4220 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4221 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4222 pbn_b0_1_4000000 },
4223 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4224 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4225 pbn_oxsemi_2_4000000 },
4226 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4227 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4228 pbn_oxsemi_2_4000000 },
4229 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4230 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4231 pbn_oxsemi_4_4000000 },
4232 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4233 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4234 pbn_oxsemi_4_4000000 },
4235 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4237 pbn_oxsemi_8_4000000 },
4238 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4239 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4240 pbn_oxsemi_8_4000000 },
4241 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4242 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4243 pbn_oxsemi_1_4000000 },
4244 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4245 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4246 pbn_oxsemi_1_4000000 },
4247 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4248 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4249 pbn_oxsemi_1_4000000 },
4250 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4251 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4252 pbn_oxsemi_1_4000000 },
4253 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4255 pbn_oxsemi_1_4000000 },
4256 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4258 pbn_oxsemi_1_4000000 },
4259 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4261 pbn_oxsemi_1_4000000 },
4262 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4264 pbn_oxsemi_1_4000000 },
4265 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4267 pbn_oxsemi_1_4000000 },
4268 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4270 pbn_oxsemi_1_4000000 },
4271 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4273 pbn_oxsemi_1_4000000 },
4274 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4275 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4276 pbn_oxsemi_1_4000000 },
4277 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4279 pbn_oxsemi_1_4000000 },
4280 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4282 pbn_oxsemi_1_4000000 },
4283 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4285 pbn_oxsemi_1_4000000 },
4286 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4288 pbn_oxsemi_1_4000000 },
4289 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4291 pbn_oxsemi_1_4000000 },
4292 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4294 pbn_oxsemi_1_4000000 },
4295 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4296 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4297 pbn_oxsemi_1_4000000 },
4298 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4300 pbn_oxsemi_1_4000000 },
4301 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4303 pbn_oxsemi_1_4000000 },
4304 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4306 pbn_oxsemi_1_4000000 },
4307 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4309 pbn_oxsemi_1_4000000 },
4310 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4311 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312 pbn_oxsemi_1_4000000 },
4313 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4314 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4315 pbn_oxsemi_1_4000000 },
4316 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4317 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4318 pbn_oxsemi_1_4000000 },
b80de369
LH		 4319 /*
4320 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4321 */
4322 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4323 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4324 pbn_oxsemi_1_4000000 },
4325 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4326 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4327 pbn_oxsemi_2_4000000 },
4328 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4329 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4330 pbn_oxsemi_4_4000000 },
4331 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4332 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4333 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 4334
4335 /*
4336 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4337 */
4338 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4339 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4340 pbn_oxsemi_2_4000000 },
4341
1da177e4
LT		 4342 /*
4343 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4344 * from skokodyn@yahoo.com
4345 */
4346 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4347 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4348 pbn_sbsxrsio },
4349 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4350 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4351 pbn_sbsxrsio },
4352 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4353 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4354 pbn_sbsxrsio },
4355 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4356 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4357 pbn_sbsxrsio },
4358
4359 /*
4360 * Digitan DS560-558, from jimd@esoft.com
4361 */
4362 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 4363 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4364 pbn_b1_1_115200 },
4365
4366 /*
4367 * Titan Electronic cards
4368 * The 400L and 800L have a custom setup quirk.
4369 */
4370 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 4371 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4372 pbn_b0_1_921600 },
4373 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 4374 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4375 pbn_b0_2_921600 },
4376 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 4377 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4378 pbn_b0_4_921600 },
4379 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 4380 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4381 pbn_b0_4_921600 },
4382 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4384 pbn_b1_1_921600 },
4385 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4387 pbn_b1_bt_2_921600 },
4388 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4389 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4390 pbn_b0_bt_4_921600 },
4391 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4392 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4393 pbn_b0_bt_8_921600 },
66169ad1
YY		 4394 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4395 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4396 pbn_b4_bt_2_921600 },
4397 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4398 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4399 pbn_b4_bt_4_921600 },
4400 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4401 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4402 pbn_b4_bt_8_921600 },
4403 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4404 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4405 pbn_b0_4_921600 },
4406 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4407 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4408 pbn_b0_4_921600 },
4409 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4410 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4411 pbn_b0_4_921600 },
4412 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4413 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4414 pbn_oxsemi_1_4000000 },
4415 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4416 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4417 pbn_oxsemi_2_4000000 },
4418 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4419 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4420 pbn_oxsemi_4_4000000 },
4421 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4422 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4423 pbn_oxsemi_8_4000000 },
4424 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4425 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4426 pbn_oxsemi_2_4000000 },
4427 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4429 pbn_oxsemi_2_4000000 },
48c0247d
YY		 4430 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4431 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4432 pbn_b0_bt_2_921600 },
1e9deb11
YY		 4433 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4434 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4435 pbn_b0_4_921600 },
4436 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4437 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4438 pbn_b0_4_921600 },
4439 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4440 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4441 pbn_b0_4_921600 },
4442 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4443 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4444 pbn_b0_4_921600 },
1da177e4
LT		 4445
4446 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4448 pbn_b2_1_460800 },
4449 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451 pbn_b2_1_460800 },
4452 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454 pbn_b2_1_460800 },
4455 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457 pbn_b2_bt_2_921600 },
4458 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4460 pbn_b2_bt_2_921600 },
4461 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4462 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4463 pbn_b2_bt_2_921600 },
4464 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4465 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4466 pbn_b2_bt_4_921600 },
4467 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4468 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4469 pbn_b2_bt_4_921600 },
4470 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4471 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4472 pbn_b2_bt_4_921600 },
4473 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4474 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4475 pbn_b0_1_921600 },
4476 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4477 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4478 pbn_b0_1_921600 },
4479 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4480 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4481 pbn_b0_1_921600 },
4482 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4483 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4484 pbn_b0_bt_2_921600 },
4485 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4487 pbn_b0_bt_2_921600 },
4488 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4489 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4490 pbn_b0_bt_2_921600 },
4491 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4493 pbn_b0_bt_4_921600 },
4494 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4496 pbn_b0_bt_4_921600 },
4497 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4499 pbn_b0_bt_4_921600 },
3ec9c594
AP		 4500 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4501 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4502 pbn_b0_bt_8_921600 },
4503 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4504 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4505 pbn_b0_bt_8_921600 },
4506 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4508 pbn_b0_bt_8_921600 },
1da177e4
LT		 4509
4510 /*
4511 * Computone devices submitted by Doug McNash dmcnash@computone.com
4512 */
4513 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4514 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4515 0, 0, pbn_computone_4 },
4516 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4517 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4518 0, 0, pbn_computone_8 },
4519 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4520 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4521 0, 0, pbn_computone_6 },
4522
4523 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4525 pbn_oxsemi },
4526 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4527 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4528 pbn_b0_bt_1_921600 },
4529
abd7baca
SC		 4530 /*
4531 * SUNIX (TIMEDIA)
4532 */
4533 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4534 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4535 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4536 pbn_b0_bt_1_921600 },
4537
4538 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4539 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4540 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4541 pbn_b0_bt_1_921600 },
4542
1da177e4
LT		 4543 /*
4544 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4545 */
4546 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548 pbn_b0_bt_8_115200 },
4549 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4550 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4551 pbn_b0_bt_8_115200 },
4552
4553 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4554 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4555 pbn_b0_bt_2_115200 },
4556 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4557 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4558 pbn_b0_bt_2_115200 },
4559 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4560 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4561 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 4562 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4563 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4564 pbn_b0_bt_2_115200 },
4565 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4566 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4567 pbn_b0_bt_2_115200 },
1da177e4
LT		 4568 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4569 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4570 pbn_b0_bt_4_460800 },
4571 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4572 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4573 pbn_b0_bt_4_460800 },
4574 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4575 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4576 pbn_b0_bt_2_460800 },
4577 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4578 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4579 pbn_b0_bt_2_460800 },
4580 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4581 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4582 pbn_b0_bt_2_460800 },
4583 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4584 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4585 pbn_b0_bt_1_115200 },
4586 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4587 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4588 pbn_b0_bt_1_460800 },
4589
1fb8cacc
RK		 4590 /*
4591 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4592 * Cards are identified by their subsystem vendor IDs, which
4593 * (in hex) match the model number.
4594 *
4595 * Note that JC140x are RS422/485 cards which require ox950
4596 * ACR = 0x10, and as such are not currently fully supported.
4597 */
4598 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4599 0x1204, 0x0004, 0, 0,
4600 pbn_b0_4_921600 },
4601 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4602 0x1208, 0x0004, 0, 0,
4603 pbn_b0_4_921600 },
4604/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4605 0x1402, 0x0002, 0, 0,
4606 pbn_b0_2_921600 }, */
4607/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4608 0x1404, 0x0004, 0, 0,
4609 pbn_b0_4_921600 }, */
4610 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4611 0x1208, 0x0004, 0, 0,
4612 pbn_b0_4_921600 },
4613
2a52fcb5
KY		 4614 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4615 0x1204, 0x0004, 0, 0,
4616 pbn_b0_4_921600 },
4617 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4618 0x1208, 0x0004, 0, 0,
4619 pbn_b0_4_921600 },
4620 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4621 0x1208, 0x0004, 0, 0,
4622 pbn_b0_4_921600 },
1da177e4
LT		 4623 /*
4624 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4625 */
4626 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628 pbn_b1_1_1382400 },
4629
4630 /*
4631 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4632 */
4633 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635 pbn_b1_1_1382400 },
4636
4637 /*
4638 * RAStel 2 port modem, gerg@moreton.com.au
4639 */
4640 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642 pbn_b2_bt_2_115200 },
4643
4644 /*
4645 * EKF addition for i960 Boards form EKF with serial port
4646 */
4647 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4648 0xE4BF, PCI_ANY_ID, 0, 0,
4649 pbn_intel_i960 },
4650
4651 /*
4652 * Xircom Cardbus/Ethernet combos
4653 */
4654 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4655 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656 pbn_b0_1_115200 },
4657 /*
4658 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4659 */
4660 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4661 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662 pbn_b0_1_115200 },
4663
4664 /*
4665 * Untested PCI modems, sent in from various folks...
4666 */
4667
4668 /*
4669 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4670 */
4671 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4672 0x1048, 0x1500, 0, 0,
4673 pbn_b1_1_115200 },
4674
4675 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4676 0xFF00, 0, 0, 0,
4677 pbn_sgi_ioc3 },
4678
4679 /*
4680 * HP Diva card
4681 */
4682 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4683 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4684 pbn_b1_1_115200 },
4685 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687 pbn_b0_5_115200 },
4688 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4690 pbn_b2_1_115200 },
4691
d9004eb4
ABL		 4692 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4693 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4694 pbn_b3_2_115200 },
1da177e4
LT		 4695 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4697 pbn_b3_4_115200 },
4698 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4700 pbn_b3_8_115200 },
4701
4702 /*
4703 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4704 */
4705 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4706 PCI_ANY_ID, PCI_ANY_ID,
4707 0,
4708 0, pbn_exar_XR17C152 },
4709 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4710 PCI_ANY_ID, PCI_ANY_ID,
4711 0,
4712 0, pbn_exar_XR17C154 },
4713 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4714 PCI_ANY_ID, PCI_ANY_ID,
4715 0,
4716 0, pbn_exar_XR17C158 },
dc96efb7
MS		 4717 /*
4718 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4719 */
4720 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4721 PCI_ANY_ID, PCI_ANY_ID,
4722 0,
4723 0, pbn_exar_XR17V352 },
4724 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4725 PCI_ANY_ID, PCI_ANY_ID,
4726 0,
4727 0, pbn_exar_XR17V354 },
4728 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4729 PCI_ANY_ID, PCI_ANY_ID,
4730 0,
4731 0, pbn_exar_XR17V358 },
1da177e4
LT		 4732
4733 /*
4734 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4735 */
4736 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4738 pbn_b0_1_115200 },
84f8c6fc
NV		 4739 /*
4740 * ITE
4741 */
4742 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4743 PCI_ANY_ID, PCI_ANY_ID,
4744 0, 0,
4745 pbn_b1_bt_1_115200 },
1da177e4 4746
737c1756
PH		 4747 /*
4748 * IntaShield IS-200
4749 */
4750 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4751 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4752 pbn_b2_2_115200 },
4b6f6ce9
IGP		 4753 /*
4754 * IntaShield IS-400
4755 */
4756 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4757 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4758 pbn_b2_4_115200 },
48212008
TH		 4759 /*
4760 * Perle PCI-RAS cards
4761 */
4762 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4763 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4764 0, 0, pbn_b2_4_921600 },
4765 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4766 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4767 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 4768
4769 /*
4770 * Mainpine series cards: Fairly standard layout but fools
4771 * parts of the autodetect in some cases and uses otherwise
4772 * unmatched communications subclasses in the PCI Express case
4773 */
4774
4775 { /* RockForceDUO */
4776 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4777 PCI_VENDOR_ID_MAINPINE, 0x0200,
4778 0, 0, pbn_b0_2_115200 },
4779 { /* RockForceQUATRO */
4780 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4781 PCI_VENDOR_ID_MAINPINE, 0x0300,
4782 0, 0, pbn_b0_4_115200 },
4783 { /* RockForceDUO+ */
4784 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4785 PCI_VENDOR_ID_MAINPINE, 0x0400,
4786 0, 0, pbn_b0_2_115200 },
4787 { /* RockForceQUATRO+ */
4788 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4789 PCI_VENDOR_ID_MAINPINE, 0x0500,
4790 0, 0, pbn_b0_4_115200 },
4791 { /* RockForce+ */
4792 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4793 PCI_VENDOR_ID_MAINPINE, 0x0600,
4794 0, 0, pbn_b0_2_115200 },
4795 { /* RockForce+ */
4796 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4797 PCI_VENDOR_ID_MAINPINE, 0x0700,
4798 0, 0, pbn_b0_4_115200 },
4799 { /* RockForceOCTO+ */
4800 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4801 PCI_VENDOR_ID_MAINPINE, 0x0800,
4802 0, 0, pbn_b0_8_115200 },
4803 { /* RockForceDUO+ */
4804 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4805 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4806 0, 0, pbn_b0_2_115200 },
4807 { /* RockForceQUARTRO+ */
4808 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4809 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4810 0, 0, pbn_b0_4_115200 },
4811 { /* RockForceOCTO+ */
4812 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4813 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4814 0, 0, pbn_b0_8_115200 },
4815 { /* RockForceD1 */
4816 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4817 PCI_VENDOR_ID_MAINPINE, 0x2000,
4818 0, 0, pbn_b0_1_115200 },
4819 { /* RockForceF1 */
4820 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4821 PCI_VENDOR_ID_MAINPINE, 0x2100,
4822 0, 0, pbn_b0_1_115200 },
4823 { /* RockForceD2 */
4824 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4825 PCI_VENDOR_ID_MAINPINE, 0x2200,
4826 0, 0, pbn_b0_2_115200 },
4827 { /* RockForceF2 */
4828 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4829 PCI_VENDOR_ID_MAINPINE, 0x2300,
4830 0, 0, pbn_b0_2_115200 },
4831 { /* RockForceD4 */
4832 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4833 PCI_VENDOR_ID_MAINPINE, 0x2400,
4834 0, 0, pbn_b0_4_115200 },
4835 { /* RockForceF4 */
4836 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4837 PCI_VENDOR_ID_MAINPINE, 0x2500,
4838 0, 0, pbn_b0_4_115200 },
4839 { /* RockForceD8 */
4840 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4841 PCI_VENDOR_ID_MAINPINE, 0x2600,
4842 0, 0, pbn_b0_8_115200 },
4843 { /* RockForceF8 */
4844 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4845 PCI_VENDOR_ID_MAINPINE, 0x2700,
4846 0, 0, pbn_b0_8_115200 },
4847 { /* IQ Express D1 */
4848 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4849 PCI_VENDOR_ID_MAINPINE, 0x3000,
4850 0, 0, pbn_b0_1_115200 },
4851 { /* IQ Express F1 */
4852 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4853 PCI_VENDOR_ID_MAINPINE, 0x3100,
4854 0, 0, pbn_b0_1_115200 },
4855 { /* IQ Express D2 */
4856 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4857 PCI_VENDOR_ID_MAINPINE, 0x3200,
4858 0, 0, pbn_b0_2_115200 },
4859 { /* IQ Express F2 */
4860 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4861 PCI_VENDOR_ID_MAINPINE, 0x3300,
4862 0, 0, pbn_b0_2_115200 },
4863 { /* IQ Express D4 */
4864 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4865 PCI_VENDOR_ID_MAINPINE, 0x3400,
4866 0, 0, pbn_b0_4_115200 },
4867 { /* IQ Express F4 */
4868 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4869 PCI_VENDOR_ID_MAINPINE, 0x3500,
4870 0, 0, pbn_b0_4_115200 },
4871 { /* IQ Express D8 */
4872 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4873 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4874 0, 0, pbn_b0_8_115200 },
4875 { /* IQ Express F8 */
4876 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4877 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4878 0, 0, pbn_b0_8_115200 },
4879
4880
aa798505
OJ		 4881 /*
4882 * PA Semi PA6T-1682M on-chip UART
4883 */
4884 { PCI_VENDOR_ID_PASEMI, 0xa004,
4885 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4886 pbn_pasemi_1682M },
4887
46a0fac9
SB		 4888 /*
4889 * National Instruments
4890 */
04bf7e74
WP		 4891 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4892 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4893 pbn_b1_16_115200 },
4894 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4895 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4896 pbn_b1_8_115200 },
4897 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4898 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4899 pbn_b1_bt_4_115200 },
4900 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4902 pbn_b1_bt_2_115200 },
4903 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4905 pbn_b1_bt_4_115200 },
4906 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4908 pbn_b1_bt_2_115200 },
4909 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4911 pbn_b1_16_115200 },
4912 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4914 pbn_b1_8_115200 },
4915 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4917 pbn_b1_bt_4_115200 },
4918 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4920 pbn_b1_bt_2_115200 },
4921 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4923 pbn_b1_bt_4_115200 },
4924 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4925 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4926 pbn_b1_bt_2_115200 },
46a0fac9
SB		 4927 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4929 pbn_ni8430_2 },
4930 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4931 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4932 pbn_ni8430_2 },
4933 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4935 pbn_ni8430_4 },
4936 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4938 pbn_ni8430_4 },
4939 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4941 pbn_ni8430_8 },
4942 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4944 pbn_ni8430_8 },
4945 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4947 pbn_ni8430_16 },
4948 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4950 pbn_ni8430_16 },
4951 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4953 pbn_ni8430_2 },
4954 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4956 pbn_ni8430_2 },
4957 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4959 pbn_ni8430_4 },
4960 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4962 pbn_ni8430_4 },
4963
02c9b5cf
KJ		 4964 /*
4965 * ADDI-DATA GmbH communication cards <info@addi-data.com>
4966 */
4967 { PCI_VENDOR_ID_ADDIDATA,
4968 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4969 PCI_ANY_ID,
4970 PCI_ANY_ID,
4971 0,
4972 0,
4973 pbn_b0_4_115200 },
4974
4975 { PCI_VENDOR_ID_ADDIDATA,
4976 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4977 PCI_ANY_ID,
4978 PCI_ANY_ID,
4979 0,
4980 0,
4981 pbn_b0_2_115200 },
4982
4983 { PCI_VENDOR_ID_ADDIDATA,
4984 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4985 PCI_ANY_ID,
4986 PCI_ANY_ID,
4987 0,
4988 0,
4989 pbn_b0_1_115200 },
4990
086231f7 4991 { PCI_VENDOR_ID_AMCC,
57c1f0e9 4992 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 4993 PCI_ANY_ID,
4994 PCI_ANY_ID,
4995 0,
4996 0,
4997 pbn_b1_8_115200 },
4998
4999 { PCI_VENDOR_ID_ADDIDATA,
5000 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5001 PCI_ANY_ID,
5002 PCI_ANY_ID,
5003 0,
5004 0,
5005 pbn_b0_4_115200 },
5006
5007 { PCI_VENDOR_ID_ADDIDATA,
5008 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5009 PCI_ANY_ID,
5010 PCI_ANY_ID,
5011 0,
5012 0,
5013 pbn_b0_2_115200 },
5014
5015 { PCI_VENDOR_ID_ADDIDATA,
5016 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5017 PCI_ANY_ID,
5018 PCI_ANY_ID,
5019 0,
5020 0,
5021 pbn_b0_1_115200 },
5022
5023 { PCI_VENDOR_ID_ADDIDATA,
5024 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5025 PCI_ANY_ID,
5026 PCI_ANY_ID,
5027 0,
5028 0,
5029 pbn_b0_4_115200 },
5030
5031 { PCI_VENDOR_ID_ADDIDATA,
5032 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5033 PCI_ANY_ID,
5034 PCI_ANY_ID,
5035 0,
5036 0,
5037 pbn_b0_2_115200 },
5038
5039 { PCI_VENDOR_ID_ADDIDATA,
5040 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5041 PCI_ANY_ID,
5042 PCI_ANY_ID,
5043 0,
5044 0,
5045 pbn_b0_1_115200 },
5046
5047 { PCI_VENDOR_ID_ADDIDATA,
5048 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5049 PCI_ANY_ID,
5050 PCI_ANY_ID,
5051 0,
5052 0,
5053 pbn_b0_8_115200 },
5054
1b62cbf2
KJ		 5055 { PCI_VENDOR_ID_ADDIDATA,
5056 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5057 PCI_ANY_ID,
5058 PCI_ANY_ID,
5059 0,
5060 0,
5061 pbn_ADDIDATA_PCIe_4_3906250 },
5062
5063 { PCI_VENDOR_ID_ADDIDATA,
5064 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5065 PCI_ANY_ID,
5066 PCI_ANY_ID,
5067 0,
5068 0,
5069 pbn_ADDIDATA_PCIe_2_3906250 },
5070
5071 { PCI_VENDOR_ID_ADDIDATA,
5072 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5073 PCI_ANY_ID,
5074 PCI_ANY_ID,
5075 0,
5076 0,
5077 pbn_ADDIDATA_PCIe_1_3906250 },
5078
5079 { PCI_VENDOR_ID_ADDIDATA,
5080 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5081 PCI_ANY_ID,
5082 PCI_ANY_ID,
5083 0,
5084 0,
5085 pbn_ADDIDATA_PCIe_8_3906250 },
5086
25cf9bc1
JS		 5087 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5088 PCI_VENDOR_ID_IBM, 0x0299,
5089 0, 0, pbn_b0_bt_2_115200 },
5090
972ce085
SS		 5091 /*
5092 * other NetMos 9835 devices are most likely handled by the
5093 * parport_serial driver, check drivers/parport/parport_serial.c
5094 * before adding them here.
5095 */
5096
c4285b47
MB		 5097 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5098 0xA000, 0x1000,
5099 0, 0, pbn_b0_1_115200 },
5100
7808edcd
NG		 5101 /* the 9901 is a rebranded 9912 */
5102 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5103 0xA000, 0x1000,
5104 0, 0, pbn_b0_1_115200 },
5105
5106 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5107 0xA000, 0x1000,
5108 0, 0, pbn_b0_1_115200 },
5109
5110 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5111 0xA000, 0x1000,
5112 0, 0, pbn_b0_1_115200 },
5113
5114 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5115 0xA000, 0x1000,
5116 0, 0, pbn_b0_1_115200 },
5117
5118 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5119 0xA000, 0x3002,
5120 0, 0, pbn_NETMOS9900_2s_115200 },
5121
ac6ec5b1 5122 /*
44178176 5123 * Best Connectivity and Rosewill PCI Multi I/O cards
ac6ec5b1
IS		 5124 */
5125
5126 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5127 0xA000, 0x1000,
5128 0, 0, pbn_b0_1_115200 },
5129
44178176
ES		 5130 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5131 0xA000, 0x3002,
5132 0, 0, pbn_b0_bt_2_115200 },
5133
ac6ec5b1
IS		 5134 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5135 0xA000, 0x3004,
5136 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 5137 /* Intel CE4100 */
5138 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5140 pbn_ce4100_1_115200 },
b15e5691
HK		 5141 /* Intel BayTrail */
5142 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5143 PCI_ANY_ID, PCI_ANY_ID,
5144 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5145 pbn_byt },
5146 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5147 PCI_ANY_ID, PCI_ANY_ID,
5148 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5149 pbn_byt },
095e24b0 5150
d9a0fbfd
AP		 5151 /*
5152 * Cronyx Omega PCI
5153 */
5154 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5155 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5156 pbn_omegapci },
ac6ec5b1 5157
ebebd49a
SH		 5158 /*
5159 * Broadcom TruManage
5160 */
5161 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5163 pbn_brcm_trumanage },
5164
6683549e
AC		 5165 /*
5166 * AgeStar as-prs2-009
5167 */
5168 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5169 PCI_ANY_ID, PCI_ANY_ID,
5170 0, 0, pbn_b0_bt_2_115200 },
27788c5f
AC		 5171
5172 /*
5173 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5174 * so not listed here.
5175 */
5176 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5177 PCI_ANY_ID, PCI_ANY_ID,
5178 0, 0, pbn_b0_bt_4_115200 },
5179
5180 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5181 PCI_ANY_ID, PCI_ANY_ID,
5182 0, 0, pbn_b0_bt_2_115200 },
5183
8b5c913f
WY		 5184 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
5185 PCI_ANY_ID, PCI_ANY_ID,
5186 0, 0, pbn_b0_bt_2_115200 },
5187
14faa8cc
MS		 5188 /*
5189 * Commtech, Inc. Fastcom adapters
5190 */
5191 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5192 PCI_ANY_ID, PCI_ANY_ID,
5193 0,
5194 0, pbn_b0_2_1152000_200 },
5195 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5196 PCI_ANY_ID, PCI_ANY_ID,
5197 0,
5198 0, pbn_b0_4_1152000_200 },
5199 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5200 PCI_ANY_ID, PCI_ANY_ID,
5201 0,
5202 0, pbn_b0_4_1152000_200 },
5203 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5204 PCI_ANY_ID, PCI_ANY_ID,
5205 0,
5206 0, pbn_b0_8_1152000_200 },
5207 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5208 PCI_ANY_ID, PCI_ANY_ID,
5209 0,
5210 0, pbn_exar_XR17V352 },
5211 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5212 PCI_ANY_ID, PCI_ANY_ID,
5213 0,
5214 0, pbn_exar_XR17V354 },
5215 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5216 PCI_ANY_ID, PCI_ANY_ID,
5217 0,
5218 0, pbn_exar_XR17V358 },
5219
2c62a3c8
GKH		 5220 /* Fintek PCI serial cards */
5221 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5222 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5223 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5224
1da177e4
LT		 5225 /*
5226 * These entries match devices with class COMMUNICATION_SERIAL,
5227 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5228 */
5229 { PCI_ANY_ID, PCI_ANY_ID,
5230 PCI_ANY_ID, PCI_ANY_ID,
5231 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5232 0xffff00, pbn_default },
5233 { PCI_ANY_ID, PCI_ANY_ID,
5234 PCI_ANY_ID, PCI_ANY_ID,
5235 PCI_CLASS_COMMUNICATION_MODEM << 8,
5236 0xffff00, pbn_default },
5237 { PCI_ANY_ID, PCI_ANY_ID,
5238 PCI_ANY_ID, PCI_ANY_ID,
5239 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5240 0xffff00, pbn_default },
5241 { 0, }
5242};
5243
2807190b
MR		 5244static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5245 pci_channel_state_t state)
5246{
5247 struct serial_private *priv = pci_get_drvdata(dev);
5248
5249 if (state == pci_channel_io_perm_failure)
5250 return PCI_ERS_RESULT_DISCONNECT;
5251
5252 if (priv)
5253 pciserial_suspend_ports(priv);
5254
5255 pci_disable_device(dev);
5256
5257 return PCI_ERS_RESULT_NEED_RESET;
5258}
5259
5260static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5261{
5262 int rc;
5263
5264 rc = pci_enable_device(dev);
5265
5266 if (rc)
5267 return PCI_ERS_RESULT_DISCONNECT;
5268
5269 pci_restore_state(dev);
5270 pci_save_state(dev);
5271
5272 return PCI_ERS_RESULT_RECOVERED;
5273}
5274
5275static void serial8250_io_resume(struct pci_dev *dev)
5276{
5277 struct serial_private *priv = pci_get_drvdata(dev);
5278
5279 if (priv)
5280 pciserial_resume_ports(priv);
5281}
5282
1d352035 5283static const struct pci_error_handlers serial8250_err_handler = {
2807190b
MR		 5284 .error_detected = serial8250_io_error_detected,
5285 .slot_reset = serial8250_io_slot_reset,
5286 .resume = serial8250_io_resume,
5287};
5288
1da177e4
LT		 5289static struct pci_driver serial_pci_driver = {
5290 .name = "serial",
5291 .probe = pciserial_init_one,
2d47b716 5292 .remove = pciserial_remove_one,
1d5e7996 5293#ifdef CONFIG_PM
1da177e4
LT		 5294 .suspend = pciserial_suspend_one,
5295 .resume = pciserial_resume_one,
1d5e7996 5296#endif
1da177e4 5297 .id_table = serial_pci_tbl,
2807190b 5298 .err_handler = &serial8250_err_handler,
1da177e4
LT		 5299};
5300
15a12e83 5301module_pci_driver(serial_pci_driver);
1da177e4
LT		 5302
5303MODULE_LICENSE("GPL");
5304MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5305MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux kernel - Deliverables
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