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serial: Test/disable MSIs if switching from N_PPS
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4 11 */
af8c5b8d 12#undef DEBUG
1da177e4 13#include <linux/module.h>
1da177e4 14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
0ad372b9 20#include <linux/serial_reg.h>
1da177e4
LT		 21#include <linux/serial_core.h>
22#include <linux/8250_pci.h>
23#include <linux/bitops.h>
24
25#include <asm/byteorder.h>
26#include <asm/io.h>
27
9a1870ce
AS		 28#include <linux/dmaengine.h>
29#include <linux/platform_data/dma-dw.h>
30
1da177e4
LT		 31#include "8250.h"
32
1da177e4
LT		 33/*
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
37 * < 0 - error
38 */
39struct pci_serial_quirk {
40 u32 vendor;
41 u32 device;
42 u32 subvendor;
43 u32 subdevice;
5bf8f501 44 int (*probe)(struct pci_dev *dev);
1da177e4 45 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 46 int (*setup)(struct serial_private *,
47 const struct pciserial_board *,
2655a2c7 48 struct uart_8250_port *, int);
1da177e4
LT		 49 void (*exit)(struct pci_dev *dev);
50};
51
52#define PCI_NUM_BAR_RESOURCES 6
53
54struct serial_private {
70db3d91 55 struct pci_dev *dev;
1da177e4
LT		 56 unsigned int nr;
57 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
58 struct pci_serial_quirk *quirk;
59 int line[0];
60};
61
7808edcd 62static int pci_default_setup(struct serial_private*,
2655a2c7 63 const struct pciserial_board*, struct uart_8250_port *, int);
7808edcd 64
1da177e4
LT		 65static void moan_device(const char *str, struct pci_dev *dev)
66{
af8c5b8d 67 dev_err(&dev->dev,
ad361c98
JP		 68 "%s: %s\n"
69 "Please send the output of lspci -vv, this\n"
70 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
71 "manufacturer and name of serial board or\n"
72 "modem board to rmk+serial@arm.linux.org.uk.\n",
1da177e4
LT		 73 pci_name(dev), str, dev->vendor, dev->device,
74 dev->subsystem_vendor, dev->subsystem_device);
75}
76
77static int
2655a2c7 78setup_port(struct serial_private *priv, struct uart_8250_port *port,
1da177e4
LT		 79 int bar, int offset, int regshift)
80{
70db3d91 81 struct pci_dev *dev = priv->dev;
1da177e4
LT		 82
83 if (bar >= PCI_NUM_BAR_RESOURCES)
84 return -EINVAL;
85
86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4 87 if (!priv->remapped_bar[bar])
398a9db6 88 priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
1da177e4
LT		 89 if (!priv->remapped_bar[bar])
90 return -ENOMEM;
91
2655a2c7
AC		 92 port->port.iotype = UPIO_MEM;
93 port->port.iobase = 0;
398a9db6 94 port->port.mapbase = pci_resource_start(dev, bar) + offset;
2655a2c7
AC		 95 port->port.membase = priv->remapped_bar[bar] + offset;
96 port->port.regshift = regshift;
1da177e4 97 } else {
2655a2c7 98 port->port.iotype = UPIO_PORT;
398a9db6 99 port->port.iobase = pci_resource_start(dev, bar) + offset;
2655a2c7
AC		 100 port->port.mapbase = 0;
101 port->port.membase = NULL;
102 port->port.regshift = 0;
1da177e4
LT		 103 }
104 return 0;
105}
106
02c9b5cf
KJ		 107/*
108 * ADDI-DATA GmbH communication cards <info@addi-data.com>
109 */
110static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 111 const struct pciserial_board *board,
2655a2c7 112 struct uart_8250_port *port, int idx)
02c9b5cf
KJ		 113{
114 unsigned int bar = 0, offset = board->first_offset;
115 bar = FL_GET_BASE(board->flags);
116
117 if (idx < 2) {
118 offset += idx * board->uart_offset;
119 } else if ((idx >= 2) && (idx < 4)) {
120 bar += 1;
121 offset += ((idx - 2) * board->uart_offset);
122 } else if ((idx >= 4) && (idx < 6)) {
123 bar += 2;
124 offset += ((idx - 4) * board->uart_offset);
125 } else if (idx >= 6) {
126 bar += 3;
127 offset += ((idx - 6) * board->uart_offset);
128 }
129
130 return setup_port(priv, port, bar, offset, board->reg_shift);
131}
132
1da177e4
LT		 133/*
134 * AFAVLAB uses a different mixture of BARs and offsets
135 * Not that ugly ;) -- HW
136 */
137static int
975a1a7d 138afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 139 struct uart_8250_port *port, int idx)
1da177e4
LT		 140{
141 unsigned int bar, offset = board->first_offset;
5756ee99 142
1da177e4
LT		 143 bar = FL_GET_BASE(board->flags);
144 if (idx < 4)
145 bar += idx;
146 else {
147 bar = 4;
148 offset += (idx - 4) * board->uart_offset;
149 }
150
70db3d91 151 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 152}
153
154/*
155 * HP's Remote Management Console. The Diva chip came in several
156 * different versions. N-class, L2000 and A500 have two Diva chips, each
157 * with 3 UARTs (the third UART on the second chip is unused). Superdome
158 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
159 * one Diva chip, but it has been expanded to 5 UARTs.
160 */
61a116ef 161static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 162{
163 int rc = 0;
164
165 switch (dev->subsystem_device) {
166 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
167 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
168 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
169 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
170 rc = 3;
171 break;
172 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
173 rc = 2;
174 break;
175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
176 rc = 4;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 179 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 180 rc = 1;
181 break;
182 }
183
184 return rc;
185}
186
187/*
188 * HP's Diva chip puts the 4th/5th serial port further out, and
189 * some serial ports are supposed to be hidden on certain models.
190 */
191static int
975a1a7d
RK		 192pci_hp_diva_setup(struct serial_private *priv,
193 const struct pciserial_board *board,
2655a2c7 194 struct uart_8250_port *port, int idx)
1da177e4
LT		 195{
196 unsigned int offset = board->first_offset;
197 unsigned int bar = FL_GET_BASE(board->flags);
198
70db3d91 199 switch (priv->dev->subsystem_device) {
1da177e4
LT		 200 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
201 if (idx == 3)
202 idx++;
203 break;
204 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
205 if (idx > 0)
206 idx++;
207 if (idx > 2)
208 idx++;
209 break;
210 }
211 if (idx > 2)
212 offset = 0x18;
213
214 offset += idx * board->uart_offset;
215
70db3d91 216 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 217}
218
219/*
220 * Added for EKF Intel i960 serial boards
221 */
61a116ef 222static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 223{
224 unsigned long oldval;
225
226 if (!(dev->subsystem_device & 0x1000))
227 return -ENODEV;
228
229 /* is firmware started? */
5756ee99
AC		 230 pci_read_config_dword(dev, 0x44, (void *)&oldval);
231 if (oldval == 0x00001000L) { /* RESET value */
af8c5b8d 232 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
1da177e4
LT		 233 return -ENODEV;
234 }
235 return 0;
236}
237
238/*
239 * Some PCI serial cards using the PLX 9050 PCI interface chip require
240 * that the card interrupt be explicitly enabled or disabled. This
241 * seems to be mainly needed on card using the PLX which also use I/O
242 * mapped memory.
243 */
61a116ef 244static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 245{
246 u8 irq_config;
247 void __iomem *p;
248
249 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
250 moan_device("no memory in bar 0", dev);
251 return 0;
252 }
253
254 irq_config = 0x41;
add7b58e 255 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 256 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 257 irq_config = 0x43;
5756ee99 258
1da177e4 259 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 260 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 261 /*
262 * As the megawolf cards have the int pins active
263 * high, and have 2 UART chips, both ints must be
264 * enabled on the 9050. Also, the UARTS are set in
265 * 16450 mode by default, so we have to enable the
266 * 16C950 'enhanced' mode so that we can use the
267 * deep FIFOs
268 */
269 irq_config = 0x5b;
1da177e4
LT		 270 /*
271 * enable/disable interrupts
272 */
6f441fe9 273 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 274 if (p == NULL)
275 return -ENOMEM;
276 writel(irq_config, p + 0x4c);
277
278 /*
279 * Read the register back to ensure that it took effect.
280 */
281 readl(p + 0x4c);
282 iounmap(p);
283
284 return 0;
285}
286
ae8d8a14 287static void pci_plx9050_exit(struct pci_dev *dev)
1da177e4
LT		 288{
289 u8 __iomem *p;
290
291 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
292 return;
293
294 /*
295 * disable interrupts
296 */
6f441fe9 297 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 298 if (p != NULL) {
299 writel(0, p + 0x4c);
300
301 /*
302 * Read the register back to ensure that it took effect.
303 */
304 readl(p + 0x4c);
305 iounmap(p);
306 }
307}
308
04bf7e74
WP		 309#define NI8420_INT_ENABLE_REG 0x38
310#define NI8420_INT_ENABLE_BIT 0x2000
311
ae8d8a14 312static void pci_ni8420_exit(struct pci_dev *dev)
04bf7e74
WP		 313{
314 void __iomem *p;
04bf7e74
WP		 315 unsigned int bar = 0;
316
317 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
318 moan_device("no memory in bar", dev);
319 return;
320 }
321
398a9db6 322 p = pci_ioremap_bar(dev, bar);
04bf7e74
WP		 323 if (p == NULL)
324 return;
325
326 /* Disable the CPU Interrupt */
327 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
328 p + NI8420_INT_ENABLE_REG);
329 iounmap(p);
330}
331
332
46a0fac9
SB		 333/* MITE registers */
334#define MITE_IOWBSR1 0xc4
335#define MITE_IOWCR1 0xf4
336#define MITE_LCIMR1 0x08
337#define MITE_LCIMR2 0x10
338
339#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
340
ae8d8a14 341static void pci_ni8430_exit(struct pci_dev *dev)
46a0fac9
SB		 342{
343 void __iomem *p;
46a0fac9
SB		 344 unsigned int bar = 0;
345
346 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
347 moan_device("no memory in bar", dev);
348 return;
349 }
350
398a9db6 351 p = pci_ioremap_bar(dev, bar);
46a0fac9
SB		 352 if (p == NULL)
353 return;
354
355 /* Disable the CPU Interrupt */
356 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
357 iounmap(p);
358}
359
1da177e4
LT		 360/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
361static int
975a1a7d 362sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
2655a2c7 363 struct uart_8250_port *port, int idx)
1da177e4
LT		 364{
365 unsigned int bar, offset = board->first_offset;
366
367 bar = 0;
368
369 if (idx < 4) {
370 /* first four channels map to 0, 0x100, 0x200, 0x300 */
371 offset += idx * board->uart_offset;
372 } else if (idx < 8) {
373 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
374 offset += idx * board->uart_offset + 0xC00;
375 } else /* we have only 8 ports on PMC-OCTALPRO */
376 return 1;
377
70db3d91 378 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 379}
380
381/*
382* This does initialization for PMC OCTALPRO cards:
383* maps the device memory, resets the UARTs (needed, bc
384* if the module is removed and inserted again, the card
385* is in the sleep mode) and enables global interrupt.
386*/
387
388/* global control register offset for SBS PMC-OctalPro */
389#define OCT_REG_CR_OFF 0x500
390
61a116ef 391static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 392{
393 u8 __iomem *p;
394
24ed3aba 395 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 396
397 if (p == NULL)
398 return -ENOMEM;
399 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 400 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 401 udelay(50);
5756ee99 402 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 403
404 /* Set bit-2 (INTENABLE) of Control Register */
405 writeb(0x4, p + OCT_REG_CR_OFF);
406 iounmap(p);
407
408 return 0;
409}
410
411/*
412 * Disables the global interrupt of PMC-OctalPro
413 */
414
ae8d8a14 415static void sbs_exit(struct pci_dev *dev)
1da177e4
LT		 416{
417 u8 __iomem *p;
418
24ed3aba 419 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 420 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
421 if (p != NULL)
1da177e4 422 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 423 iounmap(p);
424}
425
426/*
427 * SIIG serial cards have an PCI interface chip which also controls
428 * the UART clocking frequency. Each UART can be clocked independently
25985edc 429 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 430 * are stored in the EEPROM chip. It can cause problems because this
431 * version of serial driver doesn't support differently clocked UART's
432 * on single PCI card. To prevent this, initialization functions set
433 * high frequency clocking for all UART's on given card. It is safe (I
434 * hope) because it doesn't touch EEPROM settings to prevent conflicts
435 * with other OSes (like M$ DOS).
436 *
437 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 438 *
1da177e4
LT		 439 * There is two family of SIIG serial cards with different PCI
440 * interface chip and different configuration methods:
441 * - 10x cards have control registers in IO and/or memory space;
442 * - 20x cards have control registers in standard PCI configuration space.
443 *
67d74b87
RK		 444 * Note: all 10x cards have PCI device ids 0x10..
445 * all 20x cards have PCI device ids 0x20..
446 *
fbc0dc0d
AP		 447 * There are also Quartet Serial cards which use Oxford Semiconductor
448 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
449 *
1da177e4
LT		 450 * Note: some SIIG cards are probed by the parport_serial object.
451 */
452
453#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
454#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
455
456static int pci_siig10x_init(struct pci_dev *dev)
457{
458 u16 data;
459 void __iomem *p;
460
461 switch (dev->device & 0xfff8) {
462 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
463 data = 0xffdf;
464 break;
465 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
466 data = 0xf7ff;
467 break;
468 default: /* 1S1P, 4S */
469 data = 0xfffb;
470 break;
471 }
472
6f441fe9 473 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 474 if (p == NULL)
475 return -ENOMEM;
476
477 writew(readw(p + 0x28) & data, p + 0x28);
478 readw(p + 0x28);
479 iounmap(p);
480 return 0;
481}
482
483#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
484#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
485
486static int pci_siig20x_init(struct pci_dev *dev)
487{
488 u8 data;
489
490 /* Change clock frequency for the first UART. */
491 pci_read_config_byte(dev, 0x6f, &data);
492 pci_write_config_byte(dev, 0x6f, data & 0xef);
493
494 /* If this card has 2 UART, we have to do the same with second UART. */
495 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
496 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
497 pci_read_config_byte(dev, 0x73, &data);
498 pci_write_config_byte(dev, 0x73, data & 0xef);
499 }
500 return 0;
501}
502
67d74b87
RK		 503static int pci_siig_init(struct pci_dev *dev)
504{
505 unsigned int type = dev->device & 0xff00;
506
507 if (type == 0x1000)
508 return pci_siig10x_init(dev);
509 else if (type == 0x2000)
510 return pci_siig20x_init(dev);
511
512 moan_device("Unknown SIIG card", dev);
513 return -ENODEV;
514}
515
3ec9c594 516static int pci_siig_setup(struct serial_private *priv,
975a1a7d 517 const struct pciserial_board *board,
2655a2c7 518 struct uart_8250_port *port, int idx)
3ec9c594
AP		 519{
520 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
521
522 if (idx > 3) {
523 bar = 4;
524 offset = (idx - 4) * 8;
525 }
526
527 return setup_port(priv, port, bar, offset, 0);
528}
529
1da177e4
LT		 530/*
531 * Timedia has an explosion of boards, and to avoid the PCI table from
532 * growing *huge*, we use this function to collapse some 70 entries
533 * in the PCI table into one, for sanity's and compactness's sake.
534 */
e9422e09 535static const unsigned short timedia_single_port[] = {
1da177e4
LT		 536 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
537};
538
e9422e09 539static const unsigned short timedia_dual_port[] = {
1da177e4 540 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 541 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
542 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 543 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
544 0xD079, 0
545};
546
e9422e09 547static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 548 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
549 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 550 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
551 0xB157, 0
552};
553
e9422e09 554static const unsigned short timedia_eight_port[] = {
5756ee99 555 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 556 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
557};
558
cb3592be 559static const struct timedia_struct {
1da177e4 560 int num;
e9422e09 561 const unsigned short *ids;
1da177e4
LT		 562} timedia_data[] = {
563 { 1, timedia_single_port },
564 { 2, timedia_dual_port },
565 { 4, timedia_quad_port },
e9422e09 566 { 8, timedia_eight_port }
1da177e4
LT		 567};
568
b9b24558
FB		 569/*
570 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
571 * listing them individually, this driver merely grabs them all with
572 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
573 * and should be left free to be claimed by parport_serial instead.
574 */
575static int pci_timedia_probe(struct pci_dev *dev)
576{
577 /*
578 * Check the third digit of the subdevice ID
579 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
580 */
581 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
582 dev_info(&dev->dev,
583 "ignoring Timedia subdevice %04x for parport_serial\n",
584 dev->subsystem_device);
585 return -ENODEV;
586 }
587
588 return 0;
589}
590
61a116ef 591static int pci_timedia_init(struct pci_dev *dev)
1da177e4 592{
e9422e09 593 const unsigned short *ids;
1da177e4
LT		 594 int i, j;
595
e9422e09 596 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 597 ids = timedia_data[i].ids;
598 for (j = 0; ids[j]; j++)
599 if (dev->subsystem_device == ids[j])
600 return timedia_data[i].num;
601 }
602 return 0;
603}
604
605/*
606 * Timedia/SUNIX uses a mixture of BARs and offsets
607 * Ugh, this is ugly as all hell --- TYT
608 */
609static int
975a1a7d
RK		 610pci_timedia_setup(struct serial_private *priv,
611 const struct pciserial_board *board,
2655a2c7 612 struct uart_8250_port *port, int idx)
1da177e4
LT		 613{
614 unsigned int bar = 0, offset = board->first_offset;
615
616 switch (idx) {
617 case 0:
618 bar = 0;
619 break;
620 case 1:
621 offset = board->uart_offset;
622 bar = 0;
623 break;
624 case 2:
625 bar = 1;
626 break;
627 case 3:
628 offset = board->uart_offset;
c2cd6d3c 629 /* FALLTHROUGH */
1da177e4
LT		 630 case 4: /* BAR 2 */
631 case 5: /* BAR 3 */
632 case 6: /* BAR 4 */
633 case 7: /* BAR 5 */
634 bar = idx - 2;
635 }
636
70db3d91 637 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 638}
639
640/*
641 * Some Titan cards are also a little weird
642 */
643static int
70db3d91 644titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 645 const struct pciserial_board *board,
2655a2c7 646 struct uart_8250_port *port, int idx)
1da177e4
LT		 647{
648 unsigned int bar, offset = board->first_offset;
649
650 switch (idx) {
651 case 0:
652 bar = 1;
653 break;
654 case 1:
655 bar = 2;
656 break;
657 default:
658 bar = 4;
659 offset = (idx - 2) * board->uart_offset;
660 }
661
70db3d91 662 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 663}
664
61a116ef 665static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 666{
667 msleep(100);
668 return 0;
669}
670
04bf7e74
WP		 671static int pci_ni8420_init(struct pci_dev *dev)
672{
673 void __iomem *p;
04bf7e74
WP		 674 unsigned int bar = 0;
675
676 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
677 moan_device("no memory in bar", dev);
678 return 0;
679 }
680
398a9db6 681 p = pci_ioremap_bar(dev, bar);
04bf7e74
WP		 682 if (p == NULL)
683 return -ENOMEM;
684
685 /* Enable CPU Interrupt */
686 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
687 p + NI8420_INT_ENABLE_REG);
688
689 iounmap(p);
690 return 0;
691}
692
46a0fac9
SB		 693#define MITE_IOWBSR1_WSIZE 0xa
694#define MITE_IOWBSR1_WIN_OFFSET 0x800
695#define MITE_IOWBSR1_WENAB (1 << 7)
696#define MITE_LCIMR1_IO_IE_0 (1 << 24)
697#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
698#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
699
700static int pci_ni8430_init(struct pci_dev *dev)
701{
702 void __iomem *p;
398a9db6 703 struct pci_bus_region region;
46a0fac9
SB		 704 u32 device_window;
705 unsigned int bar = 0;
706
707 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
708 moan_device("no memory in bar", dev);
709 return 0;
710 }
711
398a9db6 712 p = pci_ioremap_bar(dev, bar);
46a0fac9
SB		 713 if (p == NULL)
714 return -ENOMEM;
715
398a9db6
AS		 716 /*
717 * Set device window address and size in BAR0, while acknowledging that
718 * the resource structure may contain a translated address that differs
719 * from the address the device responds to.
720 */
721 pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
722 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
46a0fac9
SB		 723 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
724 writel(device_window, p + MITE_IOWBSR1);
725
726 /* Set window access to go to RAMSEL IO address space */
727 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
728 p + MITE_IOWCR1);
729
730 /* Enable IO Bus Interrupt 0 */
731 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
732
733 /* Enable CPU Interrupt */
734 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
735
736 iounmap(p);
737 return 0;
738}
739
740/* UART Port Control Register */
741#define NI8430_PORTCON 0x0f
742#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
743
744static int
bf538fe4
AC		 745pci_ni8430_setup(struct serial_private *priv,
746 const struct pciserial_board *board,
2655a2c7 747 struct uart_8250_port *port, int idx)
46a0fac9 748{
398a9db6 749 struct pci_dev *dev = priv->dev;
46a0fac9 750 void __iomem *p;
46a0fac9
SB		 751 unsigned int bar, offset = board->first_offset;
752
753 if (idx >= board->num_ports)
754 return 1;
755
756 bar = FL_GET_BASE(board->flags);
757 offset += idx * board->uart_offset;
758
398a9db6 759 p = pci_ioremap_bar(dev, bar);
5d14bba9
AS		 760 if (!p)
761 return -ENOMEM;
46a0fac9 762
7c9d440e 763 /* enable the transceiver */
46a0fac9
SB		 764 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
765 p + offset + NI8430_PORTCON);
766
767 iounmap(p);
768
769 return setup_port(priv, port, bar, offset, board->reg_shift);
770}
771
7808edcd
NG		 772static int pci_netmos_9900_setup(struct serial_private *priv,
773 const struct pciserial_board *board,
2655a2c7 774 struct uart_8250_port *port, int idx)
7808edcd
NG		 775{
776 unsigned int bar;
777
333c085e
DES		 778 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
779 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
7808edcd
NG		 780 /* netmos apparently orders BARs by datasheet layout, so serial
781 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
782 */
783 bar = 3 * idx;
784
785 return setup_port(priv, port, bar, 0, board->reg_shift);
786 } else {
787 return pci_default_setup(priv, board, port, idx);
788 }
789}
790
791/* the 99xx series comes with a range of device IDs and a variety
792 * of capabilities:
793 *
794 * 9900 has varying capabilities and can cascade to sub-controllers
795 * (cascading should be purely internal)
796 * 9904 is hardwired with 4 serial ports
797 * 9912 and 9922 are hardwired with 2 serial ports
798 */
799static int pci_netmos_9900_numports(struct pci_dev *dev)
800{
801 unsigned int c = dev->class;
802 unsigned int pi;
803 unsigned short sub_serports;
804
805 pi = (c & 0xff);
806
807 if (pi == 2) {
808 return 1;
809 } else if ((pi == 0) &&
810 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
811 /* two possibilities: 0x30ps encodes number of parallel and
812 * serial ports, or 0x1000 indicates *something*. This is not
813 * immediately obvious, since the 2s1p+4s configuration seems
814 * to offer all functionality on functions 0..2, while still
815 * advertising the same function 3 as the 4s+2s1p config.
816 */
817 sub_serports = dev->subsystem_device & 0xf;
818 if (sub_serports > 0) {
819 return sub_serports;
820 } else {
af8c5b8d 821 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
7808edcd
NG		 822 return 0;
823 }
824 }
825
826 moan_device("unknown NetMos/Mostech program interface", dev);
827 return 0;
828}
46a0fac9 829
61a116ef 830static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 831{
832 /* subdevice 0x00PS means <P> parallel, <S> serial */
833 unsigned int num_serial = dev->subsystem_device & 0xf;
834
ac6ec5b1
IS		 835 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
836 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 837 return 0;
7808edcd 838
25cf9bc1
JS		 839 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
840 dev->subsystem_device == 0x0299)
841 return 0;
842
7808edcd
NG		 843 switch (dev->device) { /* FALLTHROUGH on all */
844 case PCI_DEVICE_ID_NETMOS_9904:
845 case PCI_DEVICE_ID_NETMOS_9912:
846 case PCI_DEVICE_ID_NETMOS_9922:
847 case PCI_DEVICE_ID_NETMOS_9900:
848 num_serial = pci_netmos_9900_numports(dev);
849 break;
850
851 default:
852 if (num_serial == 0 ) {
853 moan_device("unknown NetMos/Mostech device", dev);
854 }
855 }
856
1da177e4
LT		 857 if (num_serial == 0)
858 return -ENODEV;
7808edcd 859
1da177e4
LT		 860 return num_serial;
861}
862
84f8c6fc 863/*
84f8c6fc
NV		 864 * These chips are available with optionally one parallel port and up to
865 * two serial ports. Unfortunately they all have the same product id.
866 *
867 * Basic configuration is done over a region of 32 I/O ports. The base
868 * ioport is called INTA or INTC, depending on docs/other drivers.
869 *
870 * The region of the 32 I/O ports is configured in POSIO0R...
871 */
872
873/* registers */
874#define ITE_887x_MISCR 0x9c
875#define ITE_887x_INTCBAR 0x78
876#define ITE_887x_UARTBAR 0x7c
877#define ITE_887x_PS0BAR 0x10
878#define ITE_887x_POSIO0 0x60
879
880/* I/O space size */
881#define ITE_887x_IOSIZE 32
882/* I/O space size (bits 26-24; 8 bytes = 011b) */
883#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
884/* I/O space size (bits 26-24; 32 bytes = 101b) */
885#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
886/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
887#define ITE_887x_POSIO_SPEED (3 << 29)
888/* enable IO_Space bit */
889#define ITE_887x_POSIO_ENABLE (1 << 31)
890
f79abb82 891static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 892{
893 /* inta_addr are the configuration addresses of the ITE */
894 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
895 0x200, 0x280, 0 };
896 int ret, i, type;
897 struct resource *iobase = NULL;
898 u32 miscr, uartbar, ioport;
899
900 /* search for the base-ioport */
901 i = 0;
902 while (inta_addr[i] && iobase == NULL) {
903 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
904 "ite887x");
905 if (iobase != NULL) {
906 /* write POSIO0R - speed | size | ioport */
907 pci_write_config_dword(dev, ITE_887x_POSIO0,
908 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
909 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
910 /* write INTCBAR - ioport */
5756ee99
AC		 911 pci_write_config_dword(dev, ITE_887x_INTCBAR,
912 inta_addr[i]);
84f8c6fc
NV		 913 ret = inb(inta_addr[i]);
914 if (ret != 0xff) {
915 /* ioport connected */
916 break;
917 }
918 release_region(iobase->start, ITE_887x_IOSIZE);
919 iobase = NULL;
920 }
921 i++;
922 }
923
924 if (!inta_addr[i]) {
af8c5b8d 925 dev_err(&dev->dev, "ite887x: could not find iobase\n");
84f8c6fc
NV		 926 return -ENODEV;
927 }
928
929 /* start of undocumented type checking (see parport_pc.c) */
930 type = inb(iobase->start + 0x18) & 0x0f;
931
932 switch (type) {
933 case 0x2: /* ITE8871 (1P) */
934 case 0xa: /* ITE8875 (1P) */
935 ret = 0;
936 break;
937 case 0xe: /* ITE8872 (2S1P) */
938 ret = 2;
939 break;
940 case 0x6: /* ITE8873 (1S) */
941 ret = 1;
942 break;
943 case 0x8: /* ITE8874 (2S) */
944 ret = 2;
945 break;
946 default:
947 moan_device("Unknown ITE887x", dev);
948 ret = -ENODEV;
949 }
950
951 /* configure all serial ports */
952 for (i = 0; i < ret; i++) {
953 /* read the I/O port from the device */
954 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
955 &ioport);
956 ioport &= 0x0000FF00; /* the actual base address */
957 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
958 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
959 ITE_887x_POSIO_IOSIZE_8 | ioport);
960
961 /* write the ioport to the UARTBAR */
962 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
963 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
964 uartbar |= (ioport << (16 * i)); /* set the ioport */
965 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
966
967 /* get current config */
968 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
969 /* disable interrupts (UARTx_Routing[3:0]) */
970 miscr &= ~(0xf << (12 - 4 * i));
971 /* activate the UART (UARTx_En) */
972 miscr |= 1 << (23 - i);
973 /* write new config with activated UART */
974 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
975 }
976
977 if (ret <= 0) {
978 /* the device has no UARTs if we get here */
979 release_region(iobase->start, ITE_887x_IOSIZE);
980 }
981
982 return ret;
983}
984
ae8d8a14 985static void pci_ite887x_exit(struct pci_dev *dev)
84f8c6fc
NV		 986{
987 u32 ioport;
988 /* the ioport is bit 0-15 in POSIO0R */
989 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
990 ioport &= 0xffff;
991 release_region(ioport, ITE_887x_IOSIZE);
992}
993
1bc8cde4
MS		 994/*
995 * EndRun Technologies.
996 * Determine the number of ports available on the device.
997 */
998#define PCI_VENDOR_ID_ENDRUN 0x7401
999#define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1000
1001static int pci_endrun_init(struct pci_dev *dev)
1002{
1003 u8 __iomem *p;
1004 unsigned long deviceID;
1005 unsigned int number_uarts = 0;
1006
1007 /* EndRun device is all 0xexxx */
1008 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1009 (dev->device & 0xf000) != 0xe000)
1010 return 0;
1011
1012 p = pci_iomap(dev, 0, 5);
1013 if (p == NULL)
1014 return -ENOMEM;
1015
1016 deviceID = ioread32(p);
1017 /* EndRun device */
1018 if (deviceID == 0x07000200) {
1019 number_uarts = ioread8(p + 4);
1020 dev_dbg(&dev->dev,
1021 "%d ports detected on EndRun PCI Express device\n",
1022 number_uarts);
1023 }
1024 pci_iounmap(dev, p);
1025 return number_uarts;
1026}
1027
9f2a036a
RK		 1028/*
1029 * Oxford Semiconductor Inc.
1030 * Check that device is part of the Tornado range of devices, then determine
1031 * the number of ports available on the device.
1032 */
1033static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1034{
1035 u8 __iomem *p;
1036 unsigned long deviceID;
1037 unsigned int number_uarts = 0;
1038
1039 /* OxSemi Tornado devices are all 0xCxxx */
1040 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1041 (dev->device & 0xF000) != 0xC000)
1042 return 0;
1043
1044 p = pci_iomap(dev, 0, 5);
1045 if (p == NULL)
1046 return -ENOMEM;
1047
1048 deviceID = ioread32(p);
1049 /* Tornado device */
1050 if (deviceID == 0x07000200) {
1051 number_uarts = ioread8(p + 4);
af8c5b8d 1052 dev_dbg(&dev->dev,
9f2a036a 1053 "%d ports detected on Oxford PCI Express device\n",
af8c5b8d 1054 number_uarts);
9f2a036a
RK		 1055 }
1056 pci_iounmap(dev, p);
1057 return number_uarts;
1058}
1059
eb26dfe8
AC		 1060static int pci_asix_setup(struct serial_private *priv,
1061 const struct pciserial_board *board,
1062 struct uart_8250_port *port, int idx)
1063{
1064 port->bugs |= UART_BUG_PARITY;
1065 return pci_default_setup(priv, board, port, idx);
1066}
1067
55c7c0fd
AC		 1068/* Quatech devices have their own extra interface features */
1069
1070struct quatech_feature {
1071 u16 devid;
1072 bool amcc;
1073};
1074
1075#define QPCR_TEST_FOR1 0x3F
1076#define QPCR_TEST_GET1 0x00
1077#define QPCR_TEST_FOR2 0x40
1078#define QPCR_TEST_GET2 0x40
1079#define QPCR_TEST_FOR3 0x80
1080#define QPCR_TEST_GET3 0x40
1081#define QPCR_TEST_FOR4 0xC0
1082#define QPCR_TEST_GET4 0x80
1083
1084#define QOPR_CLOCK_X1 0x0000
1085#define QOPR_CLOCK_X2 0x0001
1086#define QOPR_CLOCK_X4 0x0002
1087#define QOPR_CLOCK_X8 0x0003
1088#define QOPR_CLOCK_RATE_MASK 0x0003
1089
1090
1091static struct quatech_feature quatech_cards[] = {
1092 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1093 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1094 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1095 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1096 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1097 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1098 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1099 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1100 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1101 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1102 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1103 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1104 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1105 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1106 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1107 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1108 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1109 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1110 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1111 { 0, }
1112};
1113
1114static int pci_quatech_amcc(u16 devid)
1115{
1116 struct quatech_feature *qf = &quatech_cards[0];
1117 while (qf->devid) {
1118 if (qf->devid == devid)
1119 return qf->amcc;
1120 qf++;
1121 }
1122 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1123 return 0;
1124};
1125
1126static int pci_quatech_rqopr(struct uart_8250_port *port)
1127{
1128 unsigned long base = port->port.iobase;
1129 u8 LCR, val;
1130
1131 LCR = inb(base + UART_LCR);
1132 outb(0xBF, base + UART_LCR);
1133 val = inb(base + UART_SCR);
1134 outb(LCR, base + UART_LCR);
1135 return val;
1136}
1137
1138static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1139{
1140 unsigned long base = port->port.iobase;
1141 u8 LCR, val;
1142
1143 LCR = inb(base + UART_LCR);
1144 outb(0xBF, base + UART_LCR);
1145 val = inb(base + UART_SCR);
1146 outb(qopr, base + UART_SCR);
1147 outb(LCR, base + UART_LCR);
1148}
1149
1150static int pci_quatech_rqmcr(struct uart_8250_port *port)
1151{
1152 unsigned long base = port->port.iobase;
1153 u8 LCR, val, qmcr;
1154
1155 LCR = inb(base + UART_LCR);
1156 outb(0xBF, base + UART_LCR);
1157 val = inb(base + UART_SCR);
1158 outb(val | 0x10, base + UART_SCR);
1159 qmcr = inb(base + UART_MCR);
1160 outb(val, base + UART_SCR);
1161 outb(LCR, base + UART_LCR);
1162
1163 return qmcr;
1164}
1165
1166static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1167{
1168 unsigned long base = port->port.iobase;
1169 u8 LCR, val;
1170
1171 LCR = inb(base + UART_LCR);
1172 outb(0xBF, base + UART_LCR);
1173 val = inb(base + UART_SCR);
1174 outb(val | 0x10, base + UART_SCR);
1175 outb(qmcr, base + UART_MCR);
1176 outb(val, base + UART_SCR);
1177 outb(LCR, base + UART_LCR);
1178}
1179
1180static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1181{
1182 unsigned long base = port->port.iobase;
1183 u8 LCR, val;
1184
1185 LCR = inb(base + UART_LCR);
1186 outb(0xBF, base + UART_LCR);
1187 val = inb(base + UART_SCR);
1188 if (val & 0x20) {
1189 outb(0x80, UART_LCR);
1190 if (!(inb(UART_SCR) & 0x20)) {
1191 outb(LCR, base + UART_LCR);
1192 return 1;
1193 }
1194 }
1195 return 0;
1196}
1197
1198static int pci_quatech_test(struct uart_8250_port *port)
1199{
1200 u8 reg;
1201 u8 qopr = pci_quatech_rqopr(port);
1202 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1203 reg = pci_quatech_rqopr(port) & 0xC0;
1204 if (reg != QPCR_TEST_GET1)
1205 return -EINVAL;
1206 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1207 reg = pci_quatech_rqopr(port) & 0xC0;
1208 if (reg != QPCR_TEST_GET2)
1209 return -EINVAL;
1210 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1211 reg = pci_quatech_rqopr(port) & 0xC0;
1212 if (reg != QPCR_TEST_GET3)
1213 return -EINVAL;
1214 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1215 reg = pci_quatech_rqopr(port) & 0xC0;
1216 if (reg != QPCR_TEST_GET4)
1217 return -EINVAL;
1218
1219 pci_quatech_wqopr(port, qopr);
1220 return 0;
1221}
1222
1223static int pci_quatech_clock(struct uart_8250_port *port)
1224{
1225 u8 qopr, reg, set;
1226 unsigned long clock;
1227
1228 if (pci_quatech_test(port) < 0)
1229 return 1843200;
1230
1231 qopr = pci_quatech_rqopr(port);
1232
1233 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1234 reg = pci_quatech_rqopr(port);
1235 if (reg & QOPR_CLOCK_X8) {
1236 clock = 1843200;
1237 goto out;
1238 }
1239 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1240 reg = pci_quatech_rqopr(port);
1241 if (!(reg & QOPR_CLOCK_X8)) {
1242 clock = 1843200;
1243 goto out;
1244 }
1245 reg &= QOPR_CLOCK_X8;
1246 if (reg == QOPR_CLOCK_X2) {
1247 clock = 3685400;
1248 set = QOPR_CLOCK_X2;
1249 } else if (reg == QOPR_CLOCK_X4) {
1250 clock = 7372800;
1251 set = QOPR_CLOCK_X4;
1252 } else if (reg == QOPR_CLOCK_X8) {
1253 clock = 14745600;
1254 set = QOPR_CLOCK_X8;
1255 } else {
1256 clock = 1843200;
1257 set = QOPR_CLOCK_X1;
1258 }
1259 qopr &= ~QOPR_CLOCK_RATE_MASK;
1260 qopr |= set;
1261
1262out:
1263 pci_quatech_wqopr(port, qopr);
1264 return clock;
1265}
1266
1267static int pci_quatech_rs422(struct uart_8250_port *port)
1268{
1269 u8 qmcr;
1270 int rs422 = 0;
1271
1272 if (!pci_quatech_has_qmcr(port))
1273 return 0;
1274 qmcr = pci_quatech_rqmcr(port);
1275 pci_quatech_wqmcr(port, 0xFF);
1276 if (pci_quatech_rqmcr(port))
1277 rs422 = 1;
1278 pci_quatech_wqmcr(port, qmcr);
1279 return rs422;
1280}
1281
1282static int pci_quatech_init(struct pci_dev *dev)
1283{
1284 if (pci_quatech_amcc(dev->device)) {
1285 unsigned long base = pci_resource_start(dev, 0);
1286 if (base) {
1287 u32 tmp;
9c5320f8 1288 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
55c7c0fd
AC		 1289 tmp = inl(base + 0x3c);
1290 outl(tmp | 0x01000000, base + 0x3c);
9c5320f8 1291 outl(tmp &= ~0x01000000, base + 0x3c);
55c7c0fd
AC		 1292 }
1293 }
1294 return 0;
1295}
1296
1297static int pci_quatech_setup(struct serial_private *priv,
1298 const struct pciserial_board *board,
1299 struct uart_8250_port *port, int idx)
1300{
1301 /* Needed by pci_quatech calls below */
1302 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1303 /* Set up the clocking */
1304 port->port.uartclk = pci_quatech_clock(port);
1305 /* For now just warn about RS422 */
1306 if (pci_quatech_rs422(port))
1307 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1308 return pci_default_setup(priv, board, port, idx);
1309}
1310
d73dfc6a 1311static void pci_quatech_exit(struct pci_dev *dev)
55c7c0fd
AC		 1312{
1313}
1314
eb26dfe8 1315static int pci_default_setup(struct serial_private *priv,
975a1a7d 1316 const struct pciserial_board *board,
2655a2c7 1317 struct uart_8250_port *port, int idx)
1da177e4
LT		 1318{
1319 unsigned int bar, offset = board->first_offset, maxnr;
1320
1321 bar = FL_GET_BASE(board->flags);
1322 if (board->flags & FL_BASE_BARS)
1323 bar += idx;
1324 else
1325 offset += idx * board->uart_offset;
1326
2427ddd8
GKH		 1327 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1328 (board->reg_shift + 3);
1da177e4
LT		 1329
1330 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1331 return 1;
5756ee99 1332
70db3d91 1333 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 1334}
1335
94341475
AB		 1336static int pci_pericom_setup(struct serial_private *priv,
1337 const struct pciserial_board *board,
1338 struct uart_8250_port *port, int idx)
1339{
1340 unsigned int bar, offset = board->first_offset, maxnr;
1341
1342 bar = FL_GET_BASE(board->flags);
1343 if (board->flags & FL_BASE_BARS)
1344 bar += idx;
1345 else
1346 offset += idx * board->uart_offset;
1347
1348 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1349 (board->reg_shift + 3);
1350
1351 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1352 return 1;
1353
1354 port->port.uartclk = 14745600;
1355
1356 return setup_port(priv, port, bar, offset, board->reg_shift);
1357}
1358
095e24b0
DB		 1359static int
1360ce4100_serial_setup(struct serial_private *priv,
1361 const struct pciserial_board *board,
2655a2c7 1362 struct uart_8250_port *port, int idx)
095e24b0
DB		 1363{
1364 int ret;
1365
08ec212c 1366 ret = setup_port(priv, port, idx, 0, board->reg_shift);
2655a2c7
AC		 1367 port->port.iotype = UPIO_MEM32;
1368 port->port.type = PORT_XSCALE;
1369 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1370 port->port.regshift = 2;
095e24b0
DB		 1371
1372 return ret;
1373}
1374
b15e5691
HK		 1375#define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1376#define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1377
29897087
AC		 1378#define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
1379#define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
1380
b15e5691
HK		 1381#define BYT_PRV_CLK 0x800
1382#define BYT_PRV_CLK_EN (1 << 0)
1383#define BYT_PRV_CLK_M_VAL_SHIFT 1
1384#define BYT_PRV_CLK_N_VAL_SHIFT 16
1385#define BYT_PRV_CLK_UPDATE (1 << 31)
1386
b15e5691
HK		 1387#define BYT_TX_OVF_INT 0x820
1388#define BYT_TX_OVF_INT_MASK (1 << 1)
1389
1390static void
1391byt_set_termios(struct uart_port *p, struct ktermios *termios,
1392 struct ktermios *old)
1393{
1394 unsigned int baud = tty_termios_baud_rate(termios);
50825c57 1395 unsigned int m, n;
b15e5691
HK		 1396 u32 reg;
1397
50825c57
AS		 1398 /*
1399 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1400 * dividers must be adjusted.
1401 *
1402 * uartclk = (m / n) * 100 MHz, where m <= n
1403 */
1404 switch (baud) {
1405 case 500000:
1406 case 1000000:
1407 case 2000000:
1408 case 4000000:
b15e5691
HK		 1409 m = 64;
1410 n = 100;
b15e5691 1411 p->uartclk = 64000000;
50825c57
AS		 1412 break;
1413 case 3500000:
1414 m = 56;
1415 n = 100;
1416 p->uartclk = 56000000;
1417 break;
1418 case 1500000:
1419 case 3000000:
b15e5691
HK		 1420 m = 48;
1421 n = 100;
b15e5691 1422 p->uartclk = 48000000;
50825c57
AS		 1423 break;
1424 case 2500000:
1425 m = 40;
1426 n = 100;
1427 p->uartclk = 40000000;
1428 break;
1429 default:
41d3f099
AS		 1430 m = 2304;
1431 n = 3125;
1432 p->uartclk = 73728000;
b15e5691
HK		 1433 }
1434
1435 /* Reset the clock */
1436 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1437 writel(reg, p->membase + BYT_PRV_CLK);
1438 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1439 writel(reg, p->membase + BYT_PRV_CLK);
1440
b15e5691
HK		 1441 serial8250_do_set_termios(p, termios, old);
1442}
1443
1444static bool byt_dma_filter(struct dma_chan *chan, void *param)
1445{
9a1870ce
AS		 1446 struct dw_dma_slave *dws = param;
1447
1448 if (dws->dma_dev != chan->device->dev)
1449 return false;
1450
1451 chan->private = dws;
1452 return true;
b15e5691
HK		 1453}
1454
1455static int
1456byt_serial_setup(struct serial_private *priv,
1457 const struct pciserial_board *board,
1458 struct uart_8250_port *port, int idx)
1459{
9a1870ce
AS		 1460 struct pci_dev *pdev = priv->dev;
1461 struct device *dev = port->port.dev;
b15e5691 1462 struct uart_8250_dma *dma;
9a1870ce
AS		 1463 struct dw_dma_slave *tx_param, *rx_param;
1464 struct pci_dev *dma_dev;
b15e5691
HK		 1465 int ret;
1466
9a1870ce 1467 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
b15e5691
HK		 1468 if (!dma)
1469 return -ENOMEM;
1470
9a1870ce
AS		 1471 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1472 if (!tx_param)
1473 return -ENOMEM;
1474
1475 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1476 if (!rx_param)
1477 return -ENOMEM;
1478
1479 switch (pdev->device) {
b15e5691 1480 case PCI_DEVICE_ID_INTEL_BYT_UART1:
29897087 1481 case PCI_DEVICE_ID_INTEL_BSW_UART1:
9a1870ce
AS		 1482 rx_param->src_id = 3;
1483 tx_param->dst_id = 2;
b15e5691
HK		 1484 break;
1485 case PCI_DEVICE_ID_INTEL_BYT_UART2:
29897087 1486 case PCI_DEVICE_ID_INTEL_BSW_UART2:
9a1870ce
AS		 1487 rx_param->src_id = 5;
1488 tx_param->dst_id = 4;
b15e5691
HK		 1489 break;
1490 default:
1491 return -EINVAL;
1492 }
1493
9a1870ce
AS		 1494 rx_param->src_master = 1;
1495 rx_param->dst_master = 0;
1496
b15e5691
HK		 1497 dma->rxconf.src_maxburst = 16;
1498
9a1870ce
AS		 1499 tx_param->src_master = 1;
1500 tx_param->dst_master = 0;
1501
b15e5691
HK		 1502 dma->txconf.dst_maxburst = 16;
1503
9a1870ce
AS		 1504 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1505 rx_param->dma_dev = &dma_dev->dev;
1506 tx_param->dma_dev = &dma_dev->dev;
1507
b15e5691 1508 dma->fn = byt_dma_filter;
9a1870ce
AS		 1509 dma->rx_param = rx_param;
1510 dma->tx_param = tx_param;
b15e5691
HK		 1511
1512 ret = pci_default_setup(priv, board, port, idx);
1513 port->port.iotype = UPIO_MEM;
1514 port->port.type = PORT_16550A;
1515 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1516 port->port.set_termios = byt_set_termios;
1517 port->port.fifosize = 64;
1518 port->tx_loadsz = 64;
1519 port->dma = dma;
1520 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1521
1522 /* Disable Tx counter interrupts */
1523 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1524
1525 return ret;
1526}
1527
d9a0fbfd
AP		 1528static int
1529pci_omegapci_setup(struct serial_private *priv,
1798ca13 1530 const struct pciserial_board *board,
2655a2c7 1531 struct uart_8250_port *port, int idx)
d9a0fbfd
AP		 1532{
1533 return setup_port(priv, port, 2, idx * 8, 0);
1534}
1535
ebebd49a
SH		 1536static int
1537pci_brcm_trumanage_setup(struct serial_private *priv,
1538 const struct pciserial_board *board,
1539 struct uart_8250_port *port, int idx)
1540{
1541 int ret = pci_default_setup(priv, board, port, idx);
1542
1543 port->port.type = PORT_BRCM_TRUMANAGE;
1544 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1545 return ret;
1546}
1547
2c62a3c8
GKH		 1548static int pci_fintek_setup(struct serial_private *priv,
1549 const struct pciserial_board *board,
1550 struct uart_8250_port *port, int idx)
1551{
1552 struct pci_dev *pdev = priv->dev;
1553 unsigned long base;
1554 unsigned long iobase;
1555 unsigned long ciobase = 0;
1556 u8 config_base;
1557
1558 /*
1559 * We are supposed to be able to read these from the PCI config space,
1560 * but the values there don't seem to match what we need to use, so
1561 * just use these hard-coded values for now, as they are correct.
1562 */
1563 switch (idx) {
1564 case 0: iobase = 0xe000; config_base = 0x40; break;
1565 case 1: iobase = 0xe008; config_base = 0x48; break;
1566 case 2: iobase = 0xe010; config_base = 0x50; break;
1567 case 3: iobase = 0xe018; config_base = 0x58; break;
1568 case 4: iobase = 0xe020; config_base = 0x60; break;
1569 case 5: iobase = 0xe028; config_base = 0x68; break;
1570 case 6: iobase = 0xe030; config_base = 0x70; break;
1571 case 7: iobase = 0xe038; config_base = 0x78; break;
1572 case 8: iobase = 0xe040; config_base = 0x80; break;
1573 case 9: iobase = 0xe048; config_base = 0x88; break;
1574 case 10: iobase = 0xe050; config_base = 0x90; break;
1575 case 11: iobase = 0xe058; config_base = 0x98; break;
1576 default:
1577 /* Unknown number of ports, get out of here */
1578 return -EINVAL;
1579 }
1580
1581 if (idx < 4) {
1582 base = pci_resource_start(priv->dev, 3);
1583 ciobase = (int)(base + (0x8 * idx));
1584 }
1585
1586 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n",
1587 __func__, idx, iobase, ciobase, config_base);
1588
1589 /* Enable UART I/O port */
1590 pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1591
1592 /* Select 128-byte FIFO and 8x FIFO threshold */
1593 pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1594
1595 /* LSB UART */
1596 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1597
1598 /* MSB UART */
1599 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1600
1601 /* irq number, this usually fails, but the spec says to do it anyway. */
1602 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1603
1604 port->port.iotype = UPIO_PORT;
1605 port->port.iobase = iobase;
1606 port->port.mapbase = 0;
1607 port->port.membase = NULL;
1608 port->port.regshift = 0;
1609
1610 return 0;
1611}
1612
b6adea33
MCC		 1613static int skip_tx_en_setup(struct serial_private *priv,
1614 const struct pciserial_board *board,
2655a2c7 1615 struct uart_8250_port *port, int idx)
b6adea33 1616{
2655a2c7 1617 port->port.flags |= UPF_NO_TXEN_TEST;
af8c5b8d
GKH		 1618 dev_dbg(&priv->dev->dev,
1619 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1620 priv->dev->vendor, priv->dev->device,
1621 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
b6adea33
MCC		 1622
1623 return pci_default_setup(priv, board, port, idx);
1624}
1625
0ad372b9
SM		 1626static void kt_handle_break(struct uart_port *p)
1627{
b1261c86 1628 struct uart_8250_port *up = up_to_u8250p(p);
0ad372b9
SM		 1629 /*
1630 * On receipt of a BI, serial device in Intel ME (Intel
1631 * management engine) needs to have its fifos cleared for sane
1632 * SOL (Serial Over Lan) output.
1633 */
1634 serial8250_clear_and_reinit_fifos(up);
1635}
1636
1637static unsigned int kt_serial_in(struct uart_port *p, int offset)
1638{
b1261c86 1639 struct uart_8250_port *up = up_to_u8250p(p);
0ad372b9
SM		 1640 unsigned int val;
1641
1642 /*
1643 * When the Intel ME (management engine) gets reset its serial
1644 * port registers could return 0 momentarily. Functions like
1645 * serial8250_console_write, read and save the IER, perform
1646 * some operation and then restore it. In order to avoid
1647 * setting IER register inadvertently to 0, if the value read
1648 * is 0, double check with ier value in uart_8250_port and use
1649 * that instead. up->ier should be the same value as what is
1650 * currently configured.
1651 */
1652 val = inb(p->iobase + offset);
1653 if (offset == UART_IER) {
1654 if (val == 0)
1655 val = up->ier;
1656 }
1657 return val;
1658}
1659
bc02d15a
DW		 1660static int kt_serial_setup(struct serial_private *priv,
1661 const struct pciserial_board *board,
2655a2c7 1662 struct uart_8250_port *port, int idx)
bc02d15a 1663{
2655a2c7
AC		 1664 port->port.flags |= UPF_BUG_THRE;
1665 port->port.serial_in = kt_serial_in;
1666 port->port.handle_break = kt_handle_break;
bc02d15a
DW		 1667 return skip_tx_en_setup(priv, board, port, idx);
1668}
1669
eb7073db
TM		 1670static int pci_eg20t_init(struct pci_dev *dev)
1671{
1672#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1673 return -ENODEV;
1674#else
1675 return 0;
1676#endif
1677}
1678
06315348
SH		 1679static int
1680pci_xr17c154_setup(struct serial_private *priv,
1681 const struct pciserial_board *board,
2655a2c7 1682 struct uart_8250_port *port, int idx)
06315348 1683{
2655a2c7 1684 port->port.flags |= UPF_EXAR_EFR;
06315348
SH		 1685 return pci_default_setup(priv, board, port, idx);
1686}
1687
dc96efb7
MS		 1688static int
1689pci_xr17v35x_setup(struct serial_private *priv,
1690 const struct pciserial_board *board,
1691 struct uart_8250_port *port, int idx)
1692{
1693 u8 __iomem *p;
1694
1695 p = pci_ioremap_bar(priv->dev, 0);
13c3237d
MS		 1696 if (p == NULL)
1697 return -ENOMEM;
dc96efb7
MS		 1698
1699 port->port.flags |= UPF_EXAR_EFR;
1700
1701 /*
1702 * Setup Multipurpose Input/Output pins.
1703 */
1704 if (idx == 0) {
1705 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1706 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1707 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1708 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1709 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1710 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1711 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1712 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1713 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1714 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1715 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1716 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1717 }
f965b9c4
MS		 1718 writeb(0x00, p + UART_EXAR_8XMODE);
1719 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1720 writeb(128, p + UART_EXAR_TXTRG);
1721 writeb(128, p + UART_EXAR_RXTRG);
dc96efb7
MS		 1722 iounmap(p);
1723
1724 return pci_default_setup(priv, board, port, idx);
1725}
1726
14faa8cc
MS		 1727#define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1728#define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1729#define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1730#define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1731
1732static int
1733pci_fastcom335_setup(struct serial_private *priv,
1734 const struct pciserial_board *board,
1735 struct uart_8250_port *port, int idx)
1736{
1737 u8 __iomem *p;
1738
1739 p = pci_ioremap_bar(priv->dev, 0);
1740 if (p == NULL)
1741 return -ENOMEM;
1742
1743 port->port.flags |= UPF_EXAR_EFR;
1744
1745 /*
1746 * Setup Multipurpose Input/Output pins.
1747 */
1748 if (idx == 0) {
1749 switch (priv->dev->device) {
1750 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1751 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1752 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1753 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1754 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1755 break;
1756 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1757 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1758 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1759 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1760 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1761 break;
1762 }
1763 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1764 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1765 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1766 }
1767 writeb(0x00, p + UART_EXAR_8XMODE);
1768 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1769 writeb(32, p + UART_EXAR_TXTRG);
1770 writeb(32, p + UART_EXAR_RXTRG);
1771 iounmap(p);
1772
1773 return pci_default_setup(priv, board, port, idx);
1774}
1775
6971c635
GA		 1776static int
1777pci_wch_ch353_setup(struct serial_private *priv,
1778 const struct pciserial_board *board,
1779 struct uart_8250_port *port, int idx)
1780{
1781 port->port.flags |= UPF_FIXED_TYPE;
1782 port->port.type = PORT_16550A;
06315348
SH		 1783 return pci_default_setup(priv, board, port, idx);
1784}
1785
1da177e4
LT		 1786#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1787#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1788#define PCI_DEVICE_ID_OCTPRO 0x0001
1789#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1790#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1791#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1792#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
26e8220a
FL		 1793#define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1794#define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
78d70d48 1795#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 1796#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 1797#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
0c6d774c
TW		 1798#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1799#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
66169ad1
YY		 1800#define PCI_DEVICE_ID_TITAN_200I 0x8028
1801#define PCI_DEVICE_ID_TITAN_400I 0x8048
1802#define PCI_DEVICE_ID_TITAN_800I 0x8088
1803#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1804#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1805#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1806#define PCI_DEVICE_ID_TITAN_100E 0xA010
1807#define PCI_DEVICE_ID_TITAN_200E 0xA012
1808#define PCI_DEVICE_ID_TITAN_400E 0xA013
1809#define PCI_DEVICE_ID_TITAN_800E 0xA014
1810#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1811#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
48c0247d 1812#define PCI_DEVICE_ID_TITAN_200V3 0xA306
1e9deb11
YY		 1813#define PCI_DEVICE_ID_TITAN_400V3 0xA310
1814#define PCI_DEVICE_ID_TITAN_410V3 0xA312
1815#define PCI_DEVICE_ID_TITAN_800V3 0xA314
1816#define PCI_DEVICE_ID_TITAN_800V3B 0xA315
e847003f 1817#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 1818#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
d9a0fbfd 1819#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
bc02d15a 1820#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
27788c5f 1821#define PCI_VENDOR_ID_WCH 0x4348
8b5c913f 1822#define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
27788c5f
AC		 1823#define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1824#define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
feb58142 1825#define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
27788c5f 1826#define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
6683549e
AC		 1827#define PCI_VENDOR_ID_AGESTAR 0x5372
1828#define PCI_DEVICE_ID_AGESTAR_9375 0x6872
eb26dfe8 1829#define PCI_VENDOR_ID_ASIX 0x9710
14faa8cc
MS		 1830#define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1831#define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
b7b9041b 1832#define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
ebebd49a 1833#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
57c1f0e9 1834#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1ede7dcc 1835#define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
14faa8cc 1836
abd7baca
SC		 1837#define PCI_VENDOR_ID_SUNIX 0x1fd4
1838#define PCI_DEVICE_ID_SUNIX_1999 0x1999
1839
1da177e4 1840
b76c5a07
CB		 1841/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1842#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
d13402a4 1843#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
b76c5a07 1844
1da177e4
LT		 1845/*
1846 * Master list of serial port init/setup/exit quirks.
1847 * This does not describe the general nature of the port.
1848 * (ie, baud base, number and location of ports, etc)
1849 *
1850 * This list is ordered alphabetically by vendor then device.
1851 * Specific entries must come before more generic entries.
1852 */
7a63ce5a 1853static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 1854 /*
1855 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1856 */
1857 {
086231f7 1858 .vendor = PCI_VENDOR_ID_AMCC,
57c1f0e9 1859 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 1860 .subvendor = PCI_ANY_ID,
1861 .subdevice = PCI_ANY_ID,
1862 .setup = addidata_apci7800_setup,
1863 },
1da177e4 1864 /*
61a116ef 1865 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 1866 * It is not clear whether this applies to all products.
1867 */
1868 {
1869 .vendor = PCI_VENDOR_ID_AFAVLAB,
1870 .device = PCI_ANY_ID,
1871 .subvendor = PCI_ANY_ID,
1872 .subdevice = PCI_ANY_ID,
1873 .setup = afavlab_setup,
1874 },
1875 /*
1876 * HP Diva
1877 */
1878 {
1879 .vendor = PCI_VENDOR_ID_HP,
1880 .device = PCI_DEVICE_ID_HP_DIVA,
1881 .subvendor = PCI_ANY_ID,
1882 .subdevice = PCI_ANY_ID,
1883 .init = pci_hp_diva_init,
1884 .setup = pci_hp_diva_setup,
1885 },
1886 /*
1887 * Intel
1888 */
1889 {
1890 .vendor = PCI_VENDOR_ID_INTEL,
1891 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1892 .subvendor = 0xe4bf,
1893 .subdevice = PCI_ANY_ID,
1894 .init = pci_inteli960ni_init,
1895 .setup = pci_default_setup,
1896 },
b6adea33
MCC		 1897 {
1898 .vendor = PCI_VENDOR_ID_INTEL,
1899 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1900 .subvendor = PCI_ANY_ID,
1901 .subdevice = PCI_ANY_ID,
1902 .setup = skip_tx_en_setup,
1903 },
1904 {
1905 .vendor = PCI_VENDOR_ID_INTEL,
1906 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1907 .subvendor = PCI_ANY_ID,
1908 .subdevice = PCI_ANY_ID,
1909 .setup = skip_tx_en_setup,
1910 },
1911 {
1912 .vendor = PCI_VENDOR_ID_INTEL,
1913 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1914 .subvendor = PCI_ANY_ID,
1915 .subdevice = PCI_ANY_ID,
1916 .setup = skip_tx_en_setup,
1917 },
095e24b0
DB		 1918 {
1919 .vendor = PCI_VENDOR_ID_INTEL,
1920 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1921 .subvendor = PCI_ANY_ID,
1922 .subdevice = PCI_ANY_ID,
1923 .setup = ce4100_serial_setup,
1924 },
bc02d15a
DW		 1925 {
1926 .vendor = PCI_VENDOR_ID_INTEL,
1927 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1928 .subvendor = PCI_ANY_ID,
1929 .subdevice = PCI_ANY_ID,
1930 .setup = kt_serial_setup,
1931 },
b15e5691
HK		 1932 {
1933 .vendor = PCI_VENDOR_ID_INTEL,
1934 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
1935 .subvendor = PCI_ANY_ID,
1936 .subdevice = PCI_ANY_ID,
1937 .setup = byt_serial_setup,
1938 },
1939 {
1940 .vendor = PCI_VENDOR_ID_INTEL,
1941 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
1942 .subvendor = PCI_ANY_ID,
1943 .subdevice = PCI_ANY_ID,
1944 .setup = byt_serial_setup,
1945 },
1ede7dcc
BD		 1946 {
1947 .vendor = PCI_VENDOR_ID_INTEL,
1948 .device = PCI_DEVICE_ID_INTEL_QRK_UART,
1949 .subvendor = PCI_ANY_ID,
1950 .subdevice = PCI_ANY_ID,
1951 .setup = pci_default_setup,
1952 },
29897087
AC		 1953 {
1954 .vendor = PCI_VENDOR_ID_INTEL,
1955 .device = PCI_DEVICE_ID_INTEL_BSW_UART1,
1956 .subvendor = PCI_ANY_ID,
1957 .subdevice = PCI_ANY_ID,
1958 .setup = byt_serial_setup,
1959 },
1960 {
1961 .vendor = PCI_VENDOR_ID_INTEL,
1962 .device = PCI_DEVICE_ID_INTEL_BSW_UART2,
1963 .subvendor = PCI_ANY_ID,
1964 .subdevice = PCI_ANY_ID,
1965 .setup = byt_serial_setup,
1966 },
84f8c6fc
NV		 1967 /*
1968 * ITE
1969 */
1970 {
1971 .vendor = PCI_VENDOR_ID_ITE,
1972 .device = PCI_DEVICE_ID_ITE_8872,
1973 .subvendor = PCI_ANY_ID,
1974 .subdevice = PCI_ANY_ID,
1975 .init = pci_ite887x_init,
1976 .setup = pci_default_setup,
2d47b716 1977 .exit = pci_ite887x_exit,
84f8c6fc 1978 },
46a0fac9
SB		 1979 /*
1980 * National Instruments
1981 */
04bf7e74
WP		 1982 {
1983 .vendor = PCI_VENDOR_ID_NI,
1984 .device = PCI_DEVICE_ID_NI_PCI23216,
1985 .subvendor = PCI_ANY_ID,
1986 .subdevice = PCI_ANY_ID,
1987 .init = pci_ni8420_init,
1988 .setup = pci_default_setup,
2d47b716 1989 .exit = pci_ni8420_exit,
04bf7e74
WP		 1990 },
1991 {
1992 .vendor = PCI_VENDOR_ID_NI,
1993 .device = PCI_DEVICE_ID_NI_PCI2328,
1994 .subvendor = PCI_ANY_ID,
1995 .subdevice = PCI_ANY_ID,
1996 .init = pci_ni8420_init,
1997 .setup = pci_default_setup,
2d47b716 1998 .exit = pci_ni8420_exit,
04bf7e74
WP		 1999 },
2000 {
2001 .vendor = PCI_VENDOR_ID_NI,
2002 .device = PCI_DEVICE_ID_NI_PCI2324,
2003 .subvendor = PCI_ANY_ID,
2004 .subdevice = PCI_ANY_ID,
2005 .init = pci_ni8420_init,
2006 .setup = pci_default_setup,
2d47b716 2007 .exit = pci_ni8420_exit,
04bf7e74
WP		 2008 },
2009 {
2010 .vendor = PCI_VENDOR_ID_NI,
2011 .device = PCI_DEVICE_ID_NI_PCI2322,
2012 .subvendor = PCI_ANY_ID,
2013 .subdevice = PCI_ANY_ID,
2014 .init = pci_ni8420_init,
2015 .setup = pci_default_setup,
2d47b716 2016 .exit = pci_ni8420_exit,
04bf7e74
WP		 2017 },
2018 {
2019 .vendor = PCI_VENDOR_ID_NI,
2020 .device = PCI_DEVICE_ID_NI_PCI2324I,
2021 .subvendor = PCI_ANY_ID,
2022 .subdevice = PCI_ANY_ID,
2023 .init = pci_ni8420_init,
2024 .setup = pci_default_setup,
2d47b716 2025 .exit = pci_ni8420_exit,
04bf7e74
WP		 2026 },
2027 {
2028 .vendor = PCI_VENDOR_ID_NI,
2029 .device = PCI_DEVICE_ID_NI_PCI2322I,
2030 .subvendor = PCI_ANY_ID,
2031 .subdevice = PCI_ANY_ID,
2032 .init = pci_ni8420_init,
2033 .setup = pci_default_setup,
2d47b716 2034 .exit = pci_ni8420_exit,
04bf7e74
WP		 2035 },
2036 {
2037 .vendor = PCI_VENDOR_ID_NI,
2038 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2039 .subvendor = PCI_ANY_ID,
2040 .subdevice = PCI_ANY_ID,
2041 .init = pci_ni8420_init,
2042 .setup = pci_default_setup,
2d47b716 2043 .exit = pci_ni8420_exit,
04bf7e74
WP		 2044 },
2045 {
2046 .vendor = PCI_VENDOR_ID_NI,
2047 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2048 .subvendor = PCI_ANY_ID,
2049 .subdevice = PCI_ANY_ID,
2050 .init = pci_ni8420_init,
2051 .setup = pci_default_setup,
2d47b716 2052 .exit = pci_ni8420_exit,
04bf7e74
WP		 2053 },
2054 {
2055 .vendor = PCI_VENDOR_ID_NI,
2056 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2057 .subvendor = PCI_ANY_ID,
2058 .subdevice = PCI_ANY_ID,
2059 .init = pci_ni8420_init,
2060 .setup = pci_default_setup,
2d47b716 2061 .exit = pci_ni8420_exit,
04bf7e74
WP		 2062 },
2063 {
2064 .vendor = PCI_VENDOR_ID_NI,
2065 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2066 .subvendor = PCI_ANY_ID,
2067 .subdevice = PCI_ANY_ID,
2068 .init = pci_ni8420_init,
2069 .setup = pci_default_setup,
2d47b716 2070 .exit = pci_ni8420_exit,
04bf7e74
WP		 2071 },
2072 {
2073 .vendor = PCI_VENDOR_ID_NI,
2074 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2075 .subvendor = PCI_ANY_ID,
2076 .subdevice = PCI_ANY_ID,
2077 .init = pci_ni8420_init,
2078 .setup = pci_default_setup,
2d47b716 2079 .exit = pci_ni8420_exit,
04bf7e74
WP		 2080 },
2081 {
2082 .vendor = PCI_VENDOR_ID_NI,
2083 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2084 .subvendor = PCI_ANY_ID,
2085 .subdevice = PCI_ANY_ID,
2086 .init = pci_ni8420_init,
2087 .setup = pci_default_setup,
2d47b716 2088 .exit = pci_ni8420_exit,
04bf7e74 2089 },
46a0fac9
SB		 2090 {
2091 .vendor = PCI_VENDOR_ID_NI,
2092 .device = PCI_ANY_ID,
2093 .subvendor = PCI_ANY_ID,
2094 .subdevice = PCI_ANY_ID,
2095 .init = pci_ni8430_init,
2096 .setup = pci_ni8430_setup,
2d47b716 2097 .exit = pci_ni8430_exit,
46a0fac9 2098 },
55c7c0fd
AC		 2099 /* Quatech */
2100 {
2101 .vendor = PCI_VENDOR_ID_QUATECH,
2102 .device = PCI_ANY_ID,
2103 .subvendor = PCI_ANY_ID,
2104 .subdevice = PCI_ANY_ID,
2105 .init = pci_quatech_init,
2106 .setup = pci_quatech_setup,
d73dfc6a 2107 .exit = pci_quatech_exit,
55c7c0fd 2108 },
1da177e4
LT		 2109 /*
2110 * Panacom
2111 */
2112 {
2113 .vendor = PCI_VENDOR_ID_PANACOM,
2114 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2115 .subvendor = PCI_ANY_ID,
2116 .subdevice = PCI_ANY_ID,
2117 .init = pci_plx9050_init,
2118 .setup = pci_default_setup,
2d47b716 2119 .exit = pci_plx9050_exit,
5756ee99 2120 },
1da177e4
LT		 2121 {
2122 .vendor = PCI_VENDOR_ID_PANACOM,
2123 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2124 .subvendor = PCI_ANY_ID,
2125 .subdevice = PCI_ANY_ID,
2126 .init = pci_plx9050_init,
2127 .setup = pci_default_setup,
2d47b716 2128 .exit = pci_plx9050_exit,
1da177e4 2129 },
94341475
AB		 2130 /*
2131 * Pericom
2132 */
2133 {
2134 .vendor = 0x12d8,
2135 .device = 0x7952,
2136 .subvendor = PCI_ANY_ID,
2137 .subdevice = PCI_ANY_ID,
2138 .setup = pci_pericom_setup,
2139 },
2140 {
2141 .vendor = 0x12d8,
2142 .device = 0x7954,
2143 .subvendor = PCI_ANY_ID,
2144 .subdevice = PCI_ANY_ID,
2145 .setup = pci_pericom_setup,
2146 },
2147 {
2148 .vendor = 0x12d8,
2149 .device = 0x7958,
2150 .subvendor = PCI_ANY_ID,
2151 .subdevice = PCI_ANY_ID,
2152 .setup = pci_pericom_setup,
2153 },
2154
1da177e4
LT		 2155 /*
2156 * PLX
2157 */
48212008
TH		 2158 {
2159 .vendor = PCI_VENDOR_ID_PLX,
2160 .device = PCI_DEVICE_ID_PLX_9030,
2161 .subvendor = PCI_SUBVENDOR_ID_PERLE,
2162 .subdevice = PCI_ANY_ID,
2163 .setup = pci_default_setup,
2164 },
add7b58e
BH		 2165 {
2166 .vendor = PCI_VENDOR_ID_PLX,
2167 .device = PCI_DEVICE_ID_PLX_9050,
2168 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2169 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2170 .init = pci_plx9050_init,
2171 .setup = pci_default_setup,
2d47b716 2172 .exit = pci_plx9050_exit,
add7b58e 2173 },
1da177e4
LT		 2174 {
2175 .vendor = PCI_VENDOR_ID_PLX,
2176 .device = PCI_DEVICE_ID_PLX_9050,
2177 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2178 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2179 .init = pci_plx9050_init,
2180 .setup = pci_default_setup,
2d47b716 2181 .exit = pci_plx9050_exit,
1da177e4
LT		 2182 },
2183 {
2184 .vendor = PCI_VENDOR_ID_PLX,
2185 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2186 .subvendor = PCI_VENDOR_ID_PLX,
2187 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2188 .init = pci_plx9050_init,
2189 .setup = pci_default_setup,
2d47b716 2190 .exit = pci_plx9050_exit,
1da177e4
LT		 2191 },
2192 /*
2193 * SBS Technologies, Inc., PMC-OCTALPRO 232
2194 */
2195 {
2196 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2197 .device = PCI_DEVICE_ID_OCTPRO,
2198 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2199 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2200 .init = sbs_init,
2201 .setup = sbs_setup,
2d47b716 2202 .exit = sbs_exit,
1da177e4
LT		 2203 },
2204 /*
2205 * SBS Technologies, Inc., PMC-OCTALPRO 422
2206 */
2207 {
2208 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2209 .device = PCI_DEVICE_ID_OCTPRO,
2210 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2211 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2212 .init = sbs_init,
2213 .setup = sbs_setup,
2d47b716 2214 .exit = sbs_exit,
1da177e4
LT		 2215 },
2216 /*
2217 * SBS Technologies, Inc., P-Octal 232
2218 */
2219 {
2220 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2221 .device = PCI_DEVICE_ID_OCTPRO,
2222 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2223 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2224 .init = sbs_init,
2225 .setup = sbs_setup,
2d47b716 2226 .exit = sbs_exit,
1da177e4
LT		 2227 },
2228 /*
2229 * SBS Technologies, Inc., P-Octal 422
2230 */
2231 {
2232 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2233 .device = PCI_DEVICE_ID_OCTPRO,
2234 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2235 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2236 .init = sbs_init,
2237 .setup = sbs_setup,
2d47b716 2238 .exit = sbs_exit,
1da177e4 2239 },
1da177e4 2240 /*
61a116ef 2241 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 2242 */
2243 {
2244 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 2245 .device = PCI_ANY_ID,
1da177e4
LT		 2246 .subvendor = PCI_ANY_ID,
2247 .subdevice = PCI_ANY_ID,
67d74b87 2248 .init = pci_siig_init,
3ec9c594 2249 .setup = pci_siig_setup,
1da177e4
LT		 2250 },
2251 /*
2252 * Titan cards
2253 */
2254 {
2255 .vendor = PCI_VENDOR_ID_TITAN,
2256 .device = PCI_DEVICE_ID_TITAN_400L,
2257 .subvendor = PCI_ANY_ID,
2258 .subdevice = PCI_ANY_ID,
2259 .setup = titan_400l_800l_setup,
2260 },
2261 {
2262 .vendor = PCI_VENDOR_ID_TITAN,
2263 .device = PCI_DEVICE_ID_TITAN_800L,
2264 .subvendor = PCI_ANY_ID,
2265 .subdevice = PCI_ANY_ID,
2266 .setup = titan_400l_800l_setup,
2267 },
2268 /*
2269 * Timedia cards
2270 */
2271 {
2272 .vendor = PCI_VENDOR_ID_TIMEDIA,
2273 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2274 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2275 .subdevice = PCI_ANY_ID,
b9b24558 2276 .probe = pci_timedia_probe,
1da177e4
LT		 2277 .init = pci_timedia_init,
2278 .setup = pci_timedia_setup,
2279 },
2280 {
2281 .vendor = PCI_VENDOR_ID_TIMEDIA,
2282 .device = PCI_ANY_ID,
2283 .subvendor = PCI_ANY_ID,
2284 .subdevice = PCI_ANY_ID,
2285 .setup = pci_timedia_setup,
2286 },
abd7baca
SC		 2287 /*
2288 * SUNIX (Timedia) cards
2289 * Do not "probe" for these cards as there is at least one combination
2290 * card that should be handled by parport_pc that doesn't match the
2291 * rule in pci_timedia_probe.
2292 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2293 * There are some boards with part number SER5037AL that report
2294 * subdevice ID 0x0002.
2295 */
2296 {
2297 .vendor = PCI_VENDOR_ID_SUNIX,
2298 .device = PCI_DEVICE_ID_SUNIX_1999,
2299 .subvendor = PCI_VENDOR_ID_SUNIX,
2300 .subdevice = PCI_ANY_ID,
2301 .init = pci_timedia_init,
2302 .setup = pci_timedia_setup,
2303 },
06315348
SH		 2304 /*
2305 * Exar cards
2306 */
2307 {
2308 .vendor = PCI_VENDOR_ID_EXAR,
2309 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2310 .subvendor = PCI_ANY_ID,
2311 .subdevice = PCI_ANY_ID,
2312 .setup = pci_xr17c154_setup,
2313 },
2314 {
2315 .vendor = PCI_VENDOR_ID_EXAR,
2316 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2317 .subvendor = PCI_ANY_ID,
2318 .subdevice = PCI_ANY_ID,
2319 .setup = pci_xr17c154_setup,
2320 },
2321 {
2322 .vendor = PCI_VENDOR_ID_EXAR,
2323 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2324 .subvendor = PCI_ANY_ID,
2325 .subdevice = PCI_ANY_ID,
2326 .setup = pci_xr17c154_setup,
2327 },
dc96efb7
MS		 2328 {
2329 .vendor = PCI_VENDOR_ID_EXAR,
2330 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2331 .subvendor = PCI_ANY_ID,
2332 .subdevice = PCI_ANY_ID,
2333 .setup = pci_xr17v35x_setup,
2334 },
2335 {
2336 .vendor = PCI_VENDOR_ID_EXAR,
2337 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2338 .subvendor = PCI_ANY_ID,
2339 .subdevice = PCI_ANY_ID,
2340 .setup = pci_xr17v35x_setup,
2341 },
2342 {
2343 .vendor = PCI_VENDOR_ID_EXAR,
2344 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2345 .subvendor = PCI_ANY_ID,
2346 .subdevice = PCI_ANY_ID,
2347 .setup = pci_xr17v35x_setup,
2348 },
1da177e4
LT		 2349 /*
2350 * Xircom cards
2351 */
2352 {
2353 .vendor = PCI_VENDOR_ID_XIRCOM,
2354 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2355 .subvendor = PCI_ANY_ID,
2356 .subdevice = PCI_ANY_ID,
2357 .init = pci_xircom_init,
2358 .setup = pci_default_setup,
2359 },
2360 /*
61a116ef 2361 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 2362 */
2363 {
2364 .vendor = PCI_VENDOR_ID_NETMOS,
2365 .device = PCI_ANY_ID,
2366 .subvendor = PCI_ANY_ID,
2367 .subdevice = PCI_ANY_ID,
2368 .init = pci_netmos_init,
7808edcd 2369 .setup = pci_netmos_9900_setup,
1da177e4 2370 },
1bc8cde4
MS		 2371 /*
2372 * EndRun Technologies
2373 */
2374 {
2375 .vendor = PCI_VENDOR_ID_ENDRUN,
2376 .device = PCI_ANY_ID,
2377 .subvendor = PCI_ANY_ID,
2378 .subdevice = PCI_ANY_ID,
2379 .init = pci_endrun_init,
2380 .setup = pci_default_setup,
2381 },
9f2a036a 2382 /*
aa273ae5 2383 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 2384 */
2385 {
2386 .vendor = PCI_VENDOR_ID_OXSEMI,
2387 .device = PCI_ANY_ID,
2388 .subvendor = PCI_ANY_ID,
2389 .subdevice = PCI_ANY_ID,
2390 .init = pci_oxsemi_tornado_init,
2391 .setup = pci_default_setup,
2392 },
2393 {
2394 .vendor = PCI_VENDOR_ID_MAINPINE,
2395 .device = PCI_ANY_ID,
2396 .subvendor = PCI_ANY_ID,
2397 .subdevice = PCI_ANY_ID,
2398 .init = pci_oxsemi_tornado_init,
2399 .setup = pci_default_setup,
2400 },
aa273ae5
SK		 2401 {
2402 .vendor = PCI_VENDOR_ID_DIGI,
2403 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2404 .subvendor = PCI_SUBVENDOR_ID_IBM,
2405 .subdevice = PCI_ANY_ID,
2406 .init = pci_oxsemi_tornado_init,
2407 .setup = pci_default_setup,
2408 },
eb7073db
TM		 2409 {
2410 .vendor = PCI_VENDOR_ID_INTEL,
2411 .device = 0x8811,
aaa10eb1
AP		 2412 .subvendor = PCI_ANY_ID,
2413 .subdevice = PCI_ANY_ID,
eb7073db 2414 .init = pci_eg20t_init,
64d91cfa 2415 .setup = pci_default_setup,
eb7073db
TM		 2416 },
2417 {
2418 .vendor = PCI_VENDOR_ID_INTEL,
2419 .device = 0x8812,
aaa10eb1
AP		 2420 .subvendor = PCI_ANY_ID,
2421 .subdevice = PCI_ANY_ID,
eb7073db 2422 .init = pci_eg20t_init,
64d91cfa 2423 .setup = pci_default_setup,
eb7073db
TM		 2424 },
2425 {
2426 .vendor = PCI_VENDOR_ID_INTEL,
2427 .device = 0x8813,
aaa10eb1
AP		 2428 .subvendor = PCI_ANY_ID,
2429 .subdevice = PCI_ANY_ID,
eb7073db 2430 .init = pci_eg20t_init,
64d91cfa 2431 .setup = pci_default_setup,
eb7073db
TM		 2432 },
2433 {
2434 .vendor = PCI_VENDOR_ID_INTEL,
2435 .device = 0x8814,
aaa10eb1
AP		 2436 .subvendor = PCI_ANY_ID,
2437 .subdevice = PCI_ANY_ID,
eb7073db 2438 .init = pci_eg20t_init,
64d91cfa 2439 .setup = pci_default_setup,
eb7073db
TM		 2440 },
2441 {
2442 .vendor = 0x10DB,
2443 .device = 0x8027,
aaa10eb1
AP		 2444 .subvendor = PCI_ANY_ID,
2445 .subdevice = PCI_ANY_ID,
eb7073db 2446 .init = pci_eg20t_init,
64d91cfa 2447 .setup = pci_default_setup,
eb7073db
TM		 2448 },
2449 {
2450 .vendor = 0x10DB,
2451 .device = 0x8028,
aaa10eb1
AP		 2452 .subvendor = PCI_ANY_ID,
2453 .subdevice = PCI_ANY_ID,
eb7073db 2454 .init = pci_eg20t_init,
64d91cfa 2455 .setup = pci_default_setup,
eb7073db
TM		 2456 },
2457 {
2458 .vendor = 0x10DB,
2459 .device = 0x8029,
aaa10eb1
AP		 2460 .subvendor = PCI_ANY_ID,
2461 .subdevice = PCI_ANY_ID,
eb7073db 2462 .init = pci_eg20t_init,
64d91cfa 2463 .setup = pci_default_setup,
eb7073db
TM		 2464 },
2465 {
2466 .vendor = 0x10DB,
2467 .device = 0x800C,
aaa10eb1
AP		 2468 .subvendor = PCI_ANY_ID,
2469 .subdevice = PCI_ANY_ID,
eb7073db 2470 .init = pci_eg20t_init,
64d91cfa 2471 .setup = pci_default_setup,
eb7073db
TM		 2472 },
2473 {
2474 .vendor = 0x10DB,
2475 .device = 0x800D,
aaa10eb1
AP		 2476 .subvendor = PCI_ANY_ID,
2477 .subdevice = PCI_ANY_ID,
eb7073db 2478 .init = pci_eg20t_init,
64d91cfa 2479 .setup = pci_default_setup,
eb7073db 2480 },
d9a0fbfd
AP		 2481 /*
2482 * Cronyx Omega PCI (PLX-chip based)
2483 */
2484 {
2485 .vendor = PCI_VENDOR_ID_PLX,
2486 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2487 .subvendor = PCI_ANY_ID,
2488 .subdevice = PCI_ANY_ID,
2489 .setup = pci_omegapci_setup,
eb26dfe8 2490 },
feb58142
EG		 2491 /* WCH CH353 1S1P card (16550 clone) */
2492 {
2493 .vendor = PCI_VENDOR_ID_WCH,
2494 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2495 .subvendor = PCI_ANY_ID,
2496 .subdevice = PCI_ANY_ID,
2497 .setup = pci_wch_ch353_setup,
2498 },
6971c635
GA		 2499 /* WCH CH353 2S1P card (16550 clone) */
2500 {
27788c5f
AC		 2501 .vendor = PCI_VENDOR_ID_WCH,
2502 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2503 .subvendor = PCI_ANY_ID,
2504 .subdevice = PCI_ANY_ID,
2505 .setup = pci_wch_ch353_setup,
2506 },
2507 /* WCH CH353 4S card (16550 clone) */
2508 {
2509 .vendor = PCI_VENDOR_ID_WCH,
2510 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2511 .subvendor = PCI_ANY_ID,
2512 .subdevice = PCI_ANY_ID,
2513 .setup = pci_wch_ch353_setup,
2514 },
2515 /* WCH CH353 2S1PF card (16550 clone) */
2516 {
2517 .vendor = PCI_VENDOR_ID_WCH,
2518 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2519 .subvendor = PCI_ANY_ID,
2520 .subdevice = PCI_ANY_ID,
6971c635
GA		 2521 .setup = pci_wch_ch353_setup,
2522 },
8b5c913f
WY		 2523 /* WCH CH352 2S card (16550 clone) */
2524 {
2525 .vendor = PCI_VENDOR_ID_WCH,
2526 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2527 .subvendor = PCI_ANY_ID,
2528 .subdevice = PCI_ANY_ID,
2529 .setup = pci_wch_ch353_setup,
2530 },
eb26dfe8
AC		 2531 /*
2532 * ASIX devices with FIFO bug
2533 */
2534 {
2535 .vendor = PCI_VENDOR_ID_ASIX,
2536 .device = PCI_ANY_ID,
2537 .subvendor = PCI_ANY_ID,
2538 .subdevice = PCI_ANY_ID,
2539 .setup = pci_asix_setup,
2540 },
14faa8cc
MS		 2541 /*
2542 * Commtech, Inc. Fastcom adapters
2543 *
2544 */
2545 {
2546 .vendor = PCI_VENDOR_ID_COMMTECH,
2547 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2548 .subvendor = PCI_ANY_ID,
2549 .subdevice = PCI_ANY_ID,
2550 .setup = pci_fastcom335_setup,
2551 },
2552 {
2553 .vendor = PCI_VENDOR_ID_COMMTECH,
2554 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2555 .subvendor = PCI_ANY_ID,
2556 .subdevice = PCI_ANY_ID,
2557 .setup = pci_fastcom335_setup,
2558 },
2559 {
2560 .vendor = PCI_VENDOR_ID_COMMTECH,
2561 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2562 .subvendor = PCI_ANY_ID,
2563 .subdevice = PCI_ANY_ID,
2564 .setup = pci_fastcom335_setup,
2565 },
2566 {
2567 .vendor = PCI_VENDOR_ID_COMMTECH,
2568 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2569 .subvendor = PCI_ANY_ID,
2570 .subdevice = PCI_ANY_ID,
2571 .setup = pci_fastcom335_setup,
2572 },
2573 {
2574 .vendor = PCI_VENDOR_ID_COMMTECH,
2575 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2576 .subvendor = PCI_ANY_ID,
2577 .subdevice = PCI_ANY_ID,
2578 .setup = pci_xr17v35x_setup,
2579 },
2580 {
2581 .vendor = PCI_VENDOR_ID_COMMTECH,
2582 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2583 .subvendor = PCI_ANY_ID,
2584 .subdevice = PCI_ANY_ID,
2585 .setup = pci_xr17v35x_setup,
2586 },
2587 {
2588 .vendor = PCI_VENDOR_ID_COMMTECH,
2589 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2590 .subvendor = PCI_ANY_ID,
2591 .subdevice = PCI_ANY_ID,
2592 .setup = pci_xr17v35x_setup,
2593 },
ebebd49a
SH		 2594 /*
2595 * Broadcom TruManage (NetXtreme)
2596 */
2597 {
2598 .vendor = PCI_VENDOR_ID_BROADCOM,
2599 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2600 .subvendor = PCI_ANY_ID,
2601 .subdevice = PCI_ANY_ID,
2602 .setup = pci_brcm_trumanage_setup,
2603 },
2c62a3c8
GKH		 2604 {
2605 .vendor = 0x1c29,
2606 .device = 0x1104,
2607 .subvendor = PCI_ANY_ID,
2608 .subdevice = PCI_ANY_ID,
2609 .setup = pci_fintek_setup,
2610 },
2611 {
2612 .vendor = 0x1c29,
2613 .device = 0x1108,
2614 .subvendor = PCI_ANY_ID,
2615 .subdevice = PCI_ANY_ID,
2616 .setup = pci_fintek_setup,
2617 },
2618 {
2619 .vendor = 0x1c29,
2620 .device = 0x1112,
2621 .subvendor = PCI_ANY_ID,
2622 .subdevice = PCI_ANY_ID,
2623 .setup = pci_fintek_setup,
2624 },
ebebd49a 2625
1da177e4
LT		 2626 /*
2627 * Default "match everything" terminator entry
2628 */
2629 {
2630 .vendor = PCI_ANY_ID,
2631 .device = PCI_ANY_ID,
2632 .subvendor = PCI_ANY_ID,
2633 .subdevice = PCI_ANY_ID,
2634 .setup = pci_default_setup,
2635 }
2636};
2637
2638static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2639{
2640 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2641}
2642
2643static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2644{
2645 struct pci_serial_quirk *quirk;
2646
2647 for (quirk = pci_serial_quirks; ; quirk++)
2648 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2649 quirk_id_matches(quirk->device, dev->device) &&
2650 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2651 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 2652 break;
1da177e4
LT		 2653 return quirk;
2654}
2655
dd68e88c 2656static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 2657 const struct pciserial_board *board)
1da177e4
LT		 2658{
2659 if (board->flags & FL_NOIRQ)
2660 return 0;
2661 else
2662 return dev->irq;
2663}
2664
2665/*
2666 * This is the configuration table for all of the PCI serial boards
2667 * which we support. It is directly indexed by the pci_board_num_t enum
2668 * value, which is encoded in the pci_device_id PCI probe table's
2669 * driver_data member.
2670 *
2671 * The makeup of these names are:
26e92861 2672 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 2673 *
26e92861
GH		 2674 * bn = PCI BAR number
2675 * bt = Index using PCI BARs
2676 * n = number of serial ports
2677 * baud = baud rate
2678 * offsetinhex = offset for each sequential port (in hex)
1da177e4 2679 *
26e92861 2680 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 2681 *
1da177e4
LT		 2682 * Please note: in theory if n = 1, _bt infix should make no difference.
2683 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2684 */
2685enum pci_board_num_t {
2686 pbn_default = 0,
2687
2688 pbn_b0_1_115200,
2689 pbn_b0_2_115200,
2690 pbn_b0_4_115200,
2691 pbn_b0_5_115200,
bf0df636 2692 pbn_b0_8_115200,
1da177e4
LT		 2693
2694 pbn_b0_1_921600,
2695 pbn_b0_2_921600,
2696 pbn_b0_4_921600,
2697
db1de159
DR		 2698 pbn_b0_2_1130000,
2699
fbc0dc0d
AP		 2700 pbn_b0_4_1152000,
2701
14faa8cc
MS		 2702 pbn_b0_2_1152000_200,
2703 pbn_b0_4_1152000_200,
2704 pbn_b0_8_1152000_200,
2705
26e92861
GH		 2706 pbn_b0_2_1843200,
2707 pbn_b0_4_1843200,
2708
2709 pbn_b0_2_1843200_200,
2710 pbn_b0_4_1843200_200,
2711 pbn_b0_8_1843200_200,
2712
7106b4e3
LH		 2713 pbn_b0_1_4000000,
2714
1da177e4
LT		 2715 pbn_b0_bt_1_115200,
2716 pbn_b0_bt_2_115200,
ac6ec5b1 2717 pbn_b0_bt_4_115200,
1da177e4
LT		 2718 pbn_b0_bt_8_115200,
2719
2720 pbn_b0_bt_1_460800,
2721 pbn_b0_bt_2_460800,
2722 pbn_b0_bt_4_460800,
2723
2724 pbn_b0_bt_1_921600,
2725 pbn_b0_bt_2_921600,
2726 pbn_b0_bt_4_921600,
2727 pbn_b0_bt_8_921600,
2728
2729 pbn_b1_1_115200,
2730 pbn_b1_2_115200,
2731 pbn_b1_4_115200,
2732 pbn_b1_8_115200,
04bf7e74 2733 pbn_b1_16_115200,
1da177e4
LT		 2734
2735 pbn_b1_1_921600,
2736 pbn_b1_2_921600,
2737 pbn_b1_4_921600,
2738 pbn_b1_8_921600,
2739
26e92861
GH		 2740 pbn_b1_2_1250000,
2741
84f8c6fc 2742 pbn_b1_bt_1_115200,
04bf7e74
WP		 2743 pbn_b1_bt_2_115200,
2744 pbn_b1_bt_4_115200,
2745
1da177e4
LT		 2746 pbn_b1_bt_2_921600,
2747
2748 pbn_b1_1_1382400,
2749 pbn_b1_2_1382400,
2750 pbn_b1_4_1382400,
2751 pbn_b1_8_1382400,
2752
2753 pbn_b2_1_115200,
737c1756 2754 pbn_b2_2_115200,
a9cccd34 2755 pbn_b2_4_115200,
1da177e4
LT		 2756 pbn_b2_8_115200,
2757
2758 pbn_b2_1_460800,
2759 pbn_b2_4_460800,
2760 pbn_b2_8_460800,
2761 pbn_b2_16_460800,
2762
2763 pbn_b2_1_921600,
2764 pbn_b2_4_921600,
2765 pbn_b2_8_921600,
2766
e847003f
LB		 2767 pbn_b2_8_1152000,
2768
1da177e4
LT		 2769 pbn_b2_bt_1_115200,
2770 pbn_b2_bt_2_115200,
2771 pbn_b2_bt_4_115200,
2772
2773 pbn_b2_bt_2_921600,
2774 pbn_b2_bt_4_921600,
2775
d9004eb4 2776 pbn_b3_2_115200,
1da177e4
LT		 2777 pbn_b3_4_115200,
2778 pbn_b3_8_115200,
2779
66169ad1
YY		 2780 pbn_b4_bt_2_921600,
2781 pbn_b4_bt_4_921600,
2782 pbn_b4_bt_8_921600,
2783
1da177e4
LT		 2784 /*
2785 * Board-specific versions.
2786 */
2787 pbn_panacom,
2788 pbn_panacom2,
2789 pbn_panacom4,
2790 pbn_plx_romulus,
1bc8cde4 2791 pbn_endrun_2_4000000,
1da177e4 2792 pbn_oxsemi,
7106b4e3
LH		 2793 pbn_oxsemi_1_4000000,
2794 pbn_oxsemi_2_4000000,
2795 pbn_oxsemi_4_4000000,
2796 pbn_oxsemi_8_4000000,
1da177e4
LT		 2797 pbn_intel_i960,
2798 pbn_sgi_ioc3,
1da177e4
LT		 2799 pbn_computone_4,
2800 pbn_computone_6,
2801 pbn_computone_8,
2802 pbn_sbsxrsio,
2803 pbn_exar_XR17C152,
2804 pbn_exar_XR17C154,
2805 pbn_exar_XR17C158,
dc96efb7
MS		 2806 pbn_exar_XR17V352,
2807 pbn_exar_XR17V354,
2808 pbn_exar_XR17V358,
c68d2b15 2809 pbn_exar_ibm_saturn,
aa798505 2810 pbn_pasemi_1682M,
46a0fac9
SB		 2811 pbn_ni8430_2,
2812 pbn_ni8430_4,
2813 pbn_ni8430_8,
2814 pbn_ni8430_16,
1b62cbf2
KJ		 2815 pbn_ADDIDATA_PCIe_1_3906250,
2816 pbn_ADDIDATA_PCIe_2_3906250,
2817 pbn_ADDIDATA_PCIe_4_3906250,
2818 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 2819 pbn_ce4100_1_115200,
b15e5691 2820 pbn_byt,
1ede7dcc 2821 pbn_qrk,
d9a0fbfd 2822 pbn_omegapci,
7808edcd 2823 pbn_NETMOS9900_2s_115200,
ebebd49a 2824 pbn_brcm_trumanage,
2c62a3c8
GKH		 2825 pbn_fintek_4,
2826 pbn_fintek_8,
2827 pbn_fintek_12,
1da177e4
LT		 2828};
2829
2830/*
2831 * uart_offset - the space between channels
2832 * reg_shift - describes how the UART registers are mapped
2833 * to PCI memory by the card.
2834 * For example IER register on SBS, Inc. PMC-OctPro is located at
2835 * offset 0x10 from the UART base, while UART_IER is defined as 1
2836 * in include/linux/serial_reg.h,
2837 * see first lines of serial_in() and serial_out() in 8250.c
2838*/
2839
de88b340 2840static struct pciserial_board pci_boards[] = {
1da177e4
LT		 2841 [pbn_default] = {
2842 .flags = FL_BASE0,
2843 .num_ports = 1,
2844 .base_baud = 115200,
2845 .uart_offset = 8,
2846 },
2847 [pbn_b0_1_115200] = {
2848 .flags = FL_BASE0,
2849 .num_ports = 1,
2850 .base_baud = 115200,
2851 .uart_offset = 8,
2852 },
2853 [pbn_b0_2_115200] = {
2854 .flags = FL_BASE0,
2855 .num_ports = 2,
2856 .base_baud = 115200,
2857 .uart_offset = 8,
2858 },
2859 [pbn_b0_4_115200] = {
2860 .flags = FL_BASE0,
2861 .num_ports = 4,
2862 .base_baud = 115200,
2863 .uart_offset = 8,
2864 },
2865 [pbn_b0_5_115200] = {
2866 .flags = FL_BASE0,
2867 .num_ports = 5,
2868 .base_baud = 115200,
2869 .uart_offset = 8,
2870 },
bf0df636
AC		 2871 [pbn_b0_8_115200] = {
2872 .flags = FL_BASE0,
2873 .num_ports = 8,
2874 .base_baud = 115200,
2875 .uart_offset = 8,
2876 },
1da177e4
LT		 2877 [pbn_b0_1_921600] = {
2878 .flags = FL_BASE0,
2879 .num_ports = 1,
2880 .base_baud = 921600,
2881 .uart_offset = 8,
2882 },
2883 [pbn_b0_2_921600] = {
2884 .flags = FL_BASE0,
2885 .num_ports = 2,
2886 .base_baud = 921600,
2887 .uart_offset = 8,
2888 },
2889 [pbn_b0_4_921600] = {
2890 .flags = FL_BASE0,
2891 .num_ports = 4,
2892 .base_baud = 921600,
2893 .uart_offset = 8,
2894 },
db1de159
DR		 2895
2896 [pbn_b0_2_1130000] = {
2897 .flags = FL_BASE0,
2898 .num_ports = 2,
2899 .base_baud = 1130000,
2900 .uart_offset = 8,
2901 },
2902
fbc0dc0d
AP		 2903 [pbn_b0_4_1152000] = {
2904 .flags = FL_BASE0,
2905 .num_ports = 4,
2906 .base_baud = 1152000,
2907 .uart_offset = 8,
2908 },
1da177e4 2909
14faa8cc
MS		 2910 [pbn_b0_2_1152000_200] = {
2911 .flags = FL_BASE0,
2912 .num_ports = 2,
2913 .base_baud = 1152000,
2914 .uart_offset = 0x200,
2915 },
2916
2917 [pbn_b0_4_1152000_200] = {
2918 .flags = FL_BASE0,
2919 .num_ports = 4,
2920 .base_baud = 1152000,
2921 .uart_offset = 0x200,
2922 },
2923
2924 [pbn_b0_8_1152000_200] = {
2925 .flags = FL_BASE0,
4f7d67d0 2926 .num_ports = 8,
14faa8cc
MS		 2927 .base_baud = 1152000,
2928 .uart_offset = 0x200,
2929 },
2930
26e92861
GH		 2931 [pbn_b0_2_1843200] = {
2932 .flags = FL_BASE0,
2933 .num_ports = 2,
2934 .base_baud = 1843200,
2935 .uart_offset = 8,
2936 },
2937 [pbn_b0_4_1843200] = {
2938 .flags = FL_BASE0,
2939 .num_ports = 4,
2940 .base_baud = 1843200,
2941 .uart_offset = 8,
2942 },
2943
2944 [pbn_b0_2_1843200_200] = {
2945 .flags = FL_BASE0,
2946 .num_ports = 2,
2947 .base_baud = 1843200,
2948 .uart_offset = 0x200,
2949 },
2950 [pbn_b0_4_1843200_200] = {
2951 .flags = FL_BASE0,
2952 .num_ports = 4,
2953 .base_baud = 1843200,
2954 .uart_offset = 0x200,
2955 },
2956 [pbn_b0_8_1843200_200] = {
2957 .flags = FL_BASE0,
2958 .num_ports = 8,
2959 .base_baud = 1843200,
2960 .uart_offset = 0x200,
2961 },
7106b4e3
LH		 2962 [pbn_b0_1_4000000] = {
2963 .flags = FL_BASE0,
2964 .num_ports = 1,
2965 .base_baud = 4000000,
2966 .uart_offset = 8,
2967 },
26e92861 2968
1da177e4
LT		 2969 [pbn_b0_bt_1_115200] = {
2970 .flags = FL_BASE0|FL_BASE_BARS,
2971 .num_ports = 1,
2972 .base_baud = 115200,
2973 .uart_offset = 8,
2974 },
2975 [pbn_b0_bt_2_115200] = {
2976 .flags = FL_BASE0|FL_BASE_BARS,
2977 .num_ports = 2,
2978 .base_baud = 115200,
2979 .uart_offset = 8,
2980 },
ac6ec5b1
IS		 2981 [pbn_b0_bt_4_115200] = {
2982 .flags = FL_BASE0|FL_BASE_BARS,
2983 .num_ports = 4,
2984 .base_baud = 115200,
2985 .uart_offset = 8,
2986 },
1da177e4
LT		 2987 [pbn_b0_bt_8_115200] = {
2988 .flags = FL_BASE0|FL_BASE_BARS,
2989 .num_ports = 8,
2990 .base_baud = 115200,
2991 .uart_offset = 8,
2992 },
2993
2994 [pbn_b0_bt_1_460800] = {
2995 .flags = FL_BASE0|FL_BASE_BARS,
2996 .num_ports = 1,
2997 .base_baud = 460800,
2998 .uart_offset = 8,
2999 },
3000 [pbn_b0_bt_2_460800] = {
3001 .flags = FL_BASE0|FL_BASE_BARS,
3002 .num_ports = 2,
3003 .base_baud = 460800,
3004 .uart_offset = 8,
3005 },
3006 [pbn_b0_bt_4_460800] = {
3007 .flags = FL_BASE0|FL_BASE_BARS,
3008 .num_ports = 4,
3009 .base_baud = 460800,
3010 .uart_offset = 8,
3011 },
3012
3013 [pbn_b0_bt_1_921600] = {
3014 .flags = FL_BASE0|FL_BASE_BARS,
3015 .num_ports = 1,
3016 .base_baud = 921600,
3017 .uart_offset = 8,
3018 },
3019 [pbn_b0_bt_2_921600] = {
3020 .flags = FL_BASE0|FL_BASE_BARS,
3021 .num_ports = 2,
3022 .base_baud = 921600,
3023 .uart_offset = 8,
3024 },
3025 [pbn_b0_bt_4_921600] = {
3026 .flags = FL_BASE0|FL_BASE_BARS,
3027 .num_ports = 4,
3028 .base_baud = 921600,
3029 .uart_offset = 8,
3030 },
3031 [pbn_b0_bt_8_921600] = {
3032 .flags = FL_BASE0|FL_BASE_BARS,
3033 .num_ports = 8,
3034 .base_baud = 921600,
3035 .uart_offset = 8,
3036 },
3037
3038 [pbn_b1_1_115200] = {
3039 .flags = FL_BASE1,
3040 .num_ports = 1,
3041 .base_baud = 115200,
3042 .uart_offset = 8,
3043 },
3044 [pbn_b1_2_115200] = {
3045 .flags = FL_BASE1,
3046 .num_ports = 2,
3047 .base_baud = 115200,
3048 .uart_offset = 8,
3049 },
3050 [pbn_b1_4_115200] = {
3051 .flags = FL_BASE1,
3052 .num_ports = 4,
3053 .base_baud = 115200,
3054 .uart_offset = 8,
3055 },
3056 [pbn_b1_8_115200] = {
3057 .flags = FL_BASE1,
3058 .num_ports = 8,
3059 .base_baud = 115200,
3060 .uart_offset = 8,
3061 },
04bf7e74
WP		 3062 [pbn_b1_16_115200] = {
3063 .flags = FL_BASE1,
3064 .num_ports = 16,
3065 .base_baud = 115200,
3066 .uart_offset = 8,
3067 },
1da177e4
LT		 3068
3069 [pbn_b1_1_921600] = {
3070 .flags = FL_BASE1,
3071 .num_ports = 1,
3072 .base_baud = 921600,
3073 .uart_offset = 8,
3074 },
3075 [pbn_b1_2_921600] = {
3076 .flags = FL_BASE1,
3077 .num_ports = 2,
3078 .base_baud = 921600,
3079 .uart_offset = 8,
3080 },
3081 [pbn_b1_4_921600] = {
3082 .flags = FL_BASE1,
3083 .num_ports = 4,
3084 .base_baud = 921600,
3085 .uart_offset = 8,
3086 },
3087 [pbn_b1_8_921600] = {
3088 .flags = FL_BASE1,
3089 .num_ports = 8,
3090 .base_baud = 921600,
3091 .uart_offset = 8,
3092 },
26e92861
GH		 3093 [pbn_b1_2_1250000] = {
3094 .flags = FL_BASE1,
3095 .num_ports = 2,
3096 .base_baud = 1250000,
3097 .uart_offset = 8,
3098 },
1da177e4 3099
84f8c6fc
NV		 3100 [pbn_b1_bt_1_115200] = {
3101 .flags = FL_BASE1|FL_BASE_BARS,
3102 .num_ports = 1,
3103 .base_baud = 115200,
3104 .uart_offset = 8,
3105 },
04bf7e74
WP		 3106 [pbn_b1_bt_2_115200] = {
3107 .flags = FL_BASE1|FL_BASE_BARS,
3108 .num_ports = 2,
3109 .base_baud = 115200,
3110 .uart_offset = 8,
3111 },
3112 [pbn_b1_bt_4_115200] = {
3113 .flags = FL_BASE1|FL_BASE_BARS,
3114 .num_ports = 4,
3115 .base_baud = 115200,
3116 .uart_offset = 8,
3117 },
84f8c6fc 3118
1da177e4
LT		 3119 [pbn_b1_bt_2_921600] = {
3120 .flags = FL_BASE1|FL_BASE_BARS,
3121 .num_ports = 2,
3122 .base_baud = 921600,
3123 .uart_offset = 8,
3124 },
3125
3126 [pbn_b1_1_1382400] = {
3127 .flags = FL_BASE1,
3128 .num_ports = 1,
3129 .base_baud = 1382400,
3130 .uart_offset = 8,
3131 },
3132 [pbn_b1_2_1382400] = {
3133 .flags = FL_BASE1,
3134 .num_ports = 2,
3135 .base_baud = 1382400,
3136 .uart_offset = 8,
3137 },
3138 [pbn_b1_4_1382400] = {
3139 .flags = FL_BASE1,
3140 .num_ports = 4,
3141 .base_baud = 1382400,
3142 .uart_offset = 8,
3143 },
3144 [pbn_b1_8_1382400] = {
3145 .flags = FL_BASE1,
3146 .num_ports = 8,
3147 .base_baud = 1382400,
3148 .uart_offset = 8,
3149 },
3150
3151 [pbn_b2_1_115200] = {
3152 .flags = FL_BASE2,
3153 .num_ports = 1,
3154 .base_baud = 115200,
3155 .uart_offset = 8,
3156 },
737c1756
PH		 3157 [pbn_b2_2_115200] = {
3158 .flags = FL_BASE2,
3159 .num_ports = 2,
3160 .base_baud = 115200,
3161 .uart_offset = 8,
3162 },
a9cccd34
MF		 3163 [pbn_b2_4_115200] = {
3164 .flags = FL_BASE2,
3165 .num_ports = 4,
3166 .base_baud = 115200,
3167 .uart_offset = 8,
3168 },
1da177e4
LT		 3169 [pbn_b2_8_115200] = {
3170 .flags = FL_BASE2,
3171 .num_ports = 8,
3172 .base_baud = 115200,
3173 .uart_offset = 8,
3174 },
3175
3176 [pbn_b2_1_460800] = {
3177 .flags = FL_BASE2,
3178 .num_ports = 1,
3179 .base_baud = 460800,
3180 .uart_offset = 8,
3181 },
3182 [pbn_b2_4_460800] = {
3183 .flags = FL_BASE2,
3184 .num_ports = 4,
3185 .base_baud = 460800,
3186 .uart_offset = 8,
3187 },
3188 [pbn_b2_8_460800] = {
3189 .flags = FL_BASE2,
3190 .num_ports = 8,
3191 .base_baud = 460800,
3192 .uart_offset = 8,
3193 },
3194 [pbn_b2_16_460800] = {
3195 .flags = FL_BASE2,
3196 .num_ports = 16,
3197 .base_baud = 460800,
3198 .uart_offset = 8,
3199 },
3200
3201 [pbn_b2_1_921600] = {
3202 .flags = FL_BASE2,
3203 .num_ports = 1,
3204 .base_baud = 921600,
3205 .uart_offset = 8,
3206 },
3207 [pbn_b2_4_921600] = {
3208 .flags = FL_BASE2,
3209 .num_ports = 4,
3210 .base_baud = 921600,
3211 .uart_offset = 8,
3212 },
3213 [pbn_b2_8_921600] = {
3214 .flags = FL_BASE2,
3215 .num_ports = 8,
3216 .base_baud = 921600,
3217 .uart_offset = 8,
3218 },
3219
e847003f
LB		 3220 [pbn_b2_8_1152000] = {
3221 .flags = FL_BASE2,
3222 .num_ports = 8,
3223 .base_baud = 1152000,
3224 .uart_offset = 8,
3225 },
3226
1da177e4
LT		 3227 [pbn_b2_bt_1_115200] = {
3228 .flags = FL_BASE2|FL_BASE_BARS,
3229 .num_ports = 1,
3230 .base_baud = 115200,
3231 .uart_offset = 8,
3232 },
3233 [pbn_b2_bt_2_115200] = {
3234 .flags = FL_BASE2|FL_BASE_BARS,
3235 .num_ports = 2,
3236 .base_baud = 115200,
3237 .uart_offset = 8,
3238 },
3239 [pbn_b2_bt_4_115200] = {
3240 .flags = FL_BASE2|FL_BASE_BARS,
3241 .num_ports = 4,
3242 .base_baud = 115200,
3243 .uart_offset = 8,
3244 },
3245
3246 [pbn_b2_bt_2_921600] = {
3247 .flags = FL_BASE2|FL_BASE_BARS,
3248 .num_ports = 2,
3249 .base_baud = 921600,
3250 .uart_offset = 8,
3251 },
3252 [pbn_b2_bt_4_921600] = {
3253 .flags = FL_BASE2|FL_BASE_BARS,
3254 .num_ports = 4,
3255 .base_baud = 921600,
3256 .uart_offset = 8,
3257 },
3258
d9004eb4
ABL		 3259 [pbn_b3_2_115200] = {
3260 .flags = FL_BASE3,
3261 .num_ports = 2,
3262 .base_baud = 115200,
3263 .uart_offset = 8,
3264 },
1da177e4
LT		 3265 [pbn_b3_4_115200] = {
3266 .flags = FL_BASE3,
3267 .num_ports = 4,
3268 .base_baud = 115200,
3269 .uart_offset = 8,
3270 },
3271 [pbn_b3_8_115200] = {
3272 .flags = FL_BASE3,
3273 .num_ports = 8,
3274 .base_baud = 115200,
3275 .uart_offset = 8,
3276 },
3277
66169ad1
YY		 3278 [pbn_b4_bt_2_921600] = {
3279 .flags = FL_BASE4,
3280 .num_ports = 2,
3281 .base_baud = 921600,
3282 .uart_offset = 8,
3283 },
3284 [pbn_b4_bt_4_921600] = {
3285 .flags = FL_BASE4,
3286 .num_ports = 4,
3287 .base_baud = 921600,
3288 .uart_offset = 8,
3289 },
3290 [pbn_b4_bt_8_921600] = {
3291 .flags = FL_BASE4,
3292 .num_ports = 8,
3293 .base_baud = 921600,
3294 .uart_offset = 8,
3295 },
3296
1da177e4
LT		 3297 /*
3298 * Entries following this are board-specific.
3299 */
3300
3301 /*
3302 * Panacom - IOMEM
3303 */
3304 [pbn_panacom] = {
3305 .flags = FL_BASE2,
3306 .num_ports = 2,
3307 .base_baud = 921600,
3308 .uart_offset = 0x400,
3309 .reg_shift = 7,
3310 },
3311 [pbn_panacom2] = {
3312 .flags = FL_BASE2|FL_BASE_BARS,
3313 .num_ports = 2,
3314 .base_baud = 921600,
3315 .uart_offset = 0x400,
3316 .reg_shift = 7,
3317 },
3318 [pbn_panacom4] = {
3319 .flags = FL_BASE2|FL_BASE_BARS,
3320 .num_ports = 4,
3321 .base_baud = 921600,
3322 .uart_offset = 0x400,
3323 .reg_shift = 7,
3324 },
3325
3326 /* I think this entry is broken - the first_offset looks wrong --rmk */
3327 [pbn_plx_romulus] = {
3328 .flags = FL_BASE2,
3329 .num_ports = 4,
3330 .base_baud = 921600,
3331 .uart_offset = 8 << 2,
3332 .reg_shift = 2,
3333 .first_offset = 0x03,
3334 },
3335
1bc8cde4
MS		 3336 /*
3337 * EndRun Technologies
3338 * Uses the size of PCI Base region 0 to
3339 * signal now many ports are available
3340 * 2 port 952 Uart support
3341 */
3342 [pbn_endrun_2_4000000] = {
3343 .flags = FL_BASE0,
3344 .num_ports = 2,
3345 .base_baud = 4000000,
3346 .uart_offset = 0x200,
3347 .first_offset = 0x1000,
3348 },
3349
1da177e4
LT		 3350 /*
3351 * This board uses the size of PCI Base region 0 to
3352 * signal now many ports are available
3353 */
3354 [pbn_oxsemi] = {
3355 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3356 .num_ports = 32,
3357 .base_baud = 115200,
3358 .uart_offset = 8,
3359 },
7106b4e3
LH		 3360 [pbn_oxsemi_1_4000000] = {
3361 .flags = FL_BASE0,
3362 .num_ports = 1,
3363 .base_baud = 4000000,
3364 .uart_offset = 0x200,
3365 .first_offset = 0x1000,
3366 },
3367 [pbn_oxsemi_2_4000000] = {
3368 .flags = FL_BASE0,
3369 .num_ports = 2,
3370 .base_baud = 4000000,
3371 .uart_offset = 0x200,
3372 .first_offset = 0x1000,
3373 },
3374 [pbn_oxsemi_4_4000000] = {
3375 .flags = FL_BASE0,
3376 .num_ports = 4,
3377 .base_baud = 4000000,
3378 .uart_offset = 0x200,
3379 .first_offset = 0x1000,
3380 },
3381 [pbn_oxsemi_8_4000000] = {
3382 .flags = FL_BASE0,
3383 .num_ports = 8,
3384 .base_baud = 4000000,
3385 .uart_offset = 0x200,
3386 .first_offset = 0x1000,
3387 },
3388
1da177e4
LT		 3389
3390 /*
3391 * EKF addition for i960 Boards form EKF with serial port.
3392 * Max 256 ports.
3393 */
3394 [pbn_intel_i960] = {
3395 .flags = FL_BASE0,
3396 .num_ports = 32,
3397 .base_baud = 921600,
3398 .uart_offset = 8 << 2,
3399 .reg_shift = 2,
3400 .first_offset = 0x10000,
3401 },
3402 [pbn_sgi_ioc3] = {
3403 .flags = FL_BASE0|FL_NOIRQ,
3404 .num_ports = 1,
3405 .base_baud = 458333,
3406 .uart_offset = 8,
3407 .reg_shift = 0,
3408 .first_offset = 0x20178,
3409 },
3410
1da177e4
LT		 3411 /*
3412 * Computone - uses IOMEM.
3413 */
3414 [pbn_computone_4] = {
3415 .flags = FL_BASE0,
3416 .num_ports = 4,
3417 .base_baud = 921600,
3418 .uart_offset = 0x40,
3419 .reg_shift = 2,
3420 .first_offset = 0x200,
3421 },
3422 [pbn_computone_6] = {
3423 .flags = FL_BASE0,
3424 .num_ports = 6,
3425 .base_baud = 921600,
3426 .uart_offset = 0x40,
3427 .reg_shift = 2,
3428 .first_offset = 0x200,
3429 },
3430 [pbn_computone_8] = {
3431 .flags = FL_BASE0,
3432 .num_ports = 8,
3433 .base_baud = 921600,
3434 .uart_offset = 0x40,
3435 .reg_shift = 2,
3436 .first_offset = 0x200,
3437 },
3438 [pbn_sbsxrsio] = {
3439 .flags = FL_BASE0,
3440 .num_ports = 8,
3441 .base_baud = 460800,
3442 .uart_offset = 256,
3443 .reg_shift = 4,
3444 },
3445 /*
3446 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3447 * Only basic 16550A support.
3448 * XR17C15[24] are not tested, but they should work.
3449 */
3450 [pbn_exar_XR17C152] = {
3451 .flags = FL_BASE0,
3452 .num_ports = 2,
3453 .base_baud = 921600,
3454 .uart_offset = 0x200,
3455 },
3456 [pbn_exar_XR17C154] = {
3457 .flags = FL_BASE0,
3458 .num_ports = 4,
3459 .base_baud = 921600,
3460 .uart_offset = 0x200,
3461 },
3462 [pbn_exar_XR17C158] = {
3463 .flags = FL_BASE0,
3464 .num_ports = 8,
3465 .base_baud = 921600,
3466 .uart_offset = 0x200,
3467 },
dc96efb7
MS		 3468 [pbn_exar_XR17V352] = {
3469 .flags = FL_BASE0,
3470 .num_ports = 2,
3471 .base_baud = 7812500,
3472 .uart_offset = 0x400,
3473 .reg_shift = 0,
3474 .first_offset = 0,
3475 },
3476 [pbn_exar_XR17V354] = {
3477 .flags = FL_BASE0,
3478 .num_ports = 4,
3479 .base_baud = 7812500,
3480 .uart_offset = 0x400,
3481 .reg_shift = 0,
3482 .first_offset = 0,
3483 },
3484 [pbn_exar_XR17V358] = {
3485 .flags = FL_BASE0,
3486 .num_ports = 8,
3487 .base_baud = 7812500,
3488 .uart_offset = 0x400,
3489 .reg_shift = 0,
3490 .first_offset = 0,
3491 },
c68d2b15
BH		 3492 [pbn_exar_ibm_saturn] = {
3493 .flags = FL_BASE0,
3494 .num_ports = 1,
3495 .base_baud = 921600,
3496 .uart_offset = 0x200,
3497 },
3498
aa798505
OJ		 3499 /*
3500 * PA Semi PWRficient PA6T-1682M on-chip UART
3501 */
3502 [pbn_pasemi_1682M] = {
3503 .flags = FL_BASE0,
3504 .num_ports = 1,
3505 .base_baud = 8333333,
3506 },
46a0fac9
SB		 3507 /*
3508 * National Instruments 843x
3509 */
3510 [pbn_ni8430_16] = {
3511 .flags = FL_BASE0,
3512 .num_ports = 16,
3513 .base_baud = 3686400,
3514 .uart_offset = 0x10,
3515 .first_offset = 0x800,
3516 },
3517 [pbn_ni8430_8] = {
3518 .flags = FL_BASE0,
3519 .num_ports = 8,
3520 .base_baud = 3686400,
3521 .uart_offset = 0x10,
3522 .first_offset = 0x800,
3523 },
3524 [pbn_ni8430_4] = {
3525 .flags = FL_BASE0,
3526 .num_ports = 4,
3527 .base_baud = 3686400,
3528 .uart_offset = 0x10,
3529 .first_offset = 0x800,
3530 },
3531 [pbn_ni8430_2] = {
3532 .flags = FL_BASE0,
3533 .num_ports = 2,
3534 .base_baud = 3686400,
3535 .uart_offset = 0x10,
3536 .first_offset = 0x800,
3537 },
1b62cbf2
KJ		 3538 /*
3539 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3540 */
3541 [pbn_ADDIDATA_PCIe_1_3906250] = {
3542 .flags = FL_BASE0,
3543 .num_ports = 1,
3544 .base_baud = 3906250,
3545 .uart_offset = 0x200,
3546 .first_offset = 0x1000,
3547 },
3548 [pbn_ADDIDATA_PCIe_2_3906250] = {
3549 .flags = FL_BASE0,
3550 .num_ports = 2,
3551 .base_baud = 3906250,
3552 .uart_offset = 0x200,
3553 .first_offset = 0x1000,
3554 },
3555 [pbn_ADDIDATA_PCIe_4_3906250] = {
3556 .flags = FL_BASE0,
3557 .num_ports = 4,
3558 .base_baud = 3906250,
3559 .uart_offset = 0x200,
3560 .first_offset = 0x1000,
3561 },
3562 [pbn_ADDIDATA_PCIe_8_3906250] = {
3563 .flags = FL_BASE0,
3564 .num_ports = 8,
3565 .base_baud = 3906250,
3566 .uart_offset = 0x200,
3567 .first_offset = 0x1000,
3568 },
095e24b0 3569 [pbn_ce4100_1_115200] = {
08ec212c
MB		 3570 .flags = FL_BASE_BARS,
3571 .num_ports = 2,
095e24b0
DB		 3572 .base_baud = 921600,
3573 .reg_shift = 2,
3574 },
41d3f099
AS		 3575 /*
3576 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3577 * but is overridden by byt_set_termios.
3578 */
b15e5691
HK		 3579 [pbn_byt] = {
3580 .flags = FL_BASE0,
3581 .num_ports = 1,
3582 .base_baud = 2764800,
3583 .uart_offset = 0x80,
3584 .reg_shift = 2,
3585 },
1ede7dcc
BD		 3586 [pbn_qrk] = {
3587 .flags = FL_BASE0,
3588 .num_ports = 1,
3589 .base_baud = 2764800,
3590 .reg_shift = 2,
3591 },
d9a0fbfd
AP		 3592 [pbn_omegapci] = {
3593 .flags = FL_BASE0,
3594 .num_ports = 8,
3595 .base_baud = 115200,
3596 .uart_offset = 0x200,
3597 },
7808edcd
NG		 3598 [pbn_NETMOS9900_2s_115200] = {
3599 .flags = FL_BASE0,
3600 .num_ports = 2,
3601 .base_baud = 115200,
3602 },
ebebd49a
SH		 3603 [pbn_brcm_trumanage] = {
3604 .flags = FL_BASE0,
3605 .num_ports = 1,
3606 .reg_shift = 2,
3607 .base_baud = 115200,
3608 },
2c62a3c8
GKH		 3609 [pbn_fintek_4] = {
3610 .num_ports = 4,
3611 .uart_offset = 8,
3612 .base_baud = 115200,
3613 .first_offset = 0x40,
3614 },
3615 [pbn_fintek_8] = {
3616 .num_ports = 8,
3617 .uart_offset = 8,
3618 .base_baud = 115200,
3619 .first_offset = 0x40,
3620 },
3621 [pbn_fintek_12] = {
3622 .num_ports = 12,
3623 .uart_offset = 8,
3624 .base_baud = 115200,
3625 .first_offset = 0x40,
3626 },
1da177e4
LT		 3627};
3628
6971c635
GA		 3629static const struct pci_device_id blacklist[] = {
3630 /* softmodems */
5756ee99 3631 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 3632 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3633 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
6971c635
GA		 3634
3635 /* multi-io cards handled by parport_serial */
3636 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
feb58142 3637 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
436bbd43
CS		 3638};
3639
1da177e4
LT		 3640/*
3641 * Given a complete unknown PCI device, try to use some heuristics to
3642 * guess what the configuration might be, based on the pitiful PCI
3643 * serial specs. Returns 0 on success, 1 on failure.
3644 */
9671f099 3645static int
1c7c1fe5 3646serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 3647{
6971c635 3648 const struct pci_device_id *bldev;
1da177e4 3649 int num_iomem, num_port, first_port = -1, i;
5756ee99 3650
1da177e4
LT		 3651 /*
3652 * If it is not a communications device or the programming
3653 * interface is greater than 6, give up.
3654 *
3655 * (Should we try to make guesses for multiport serial devices
5756ee99 3656 * later?)
1da177e4
LT		 3657 */
3658 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3659 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3660 (dev->class & 0xff) > 6)
3661 return -ENODEV;
3662
436bbd43
CS		 3663 /*
3664 * Do not access blacklisted devices that are known not to
6971c635 3665 * feature serial ports or are handled by other modules.
436bbd43 3666 */
6971c635
GA		 3667 for (bldev = blacklist;
3668 bldev < blacklist + ARRAY_SIZE(blacklist);
3669 bldev++) {
3670 if (dev->vendor == bldev->vendor &&
3671 dev->device == bldev->device)
436bbd43
CS		 3672 return -ENODEV;
3673 }
3674
1da177e4
LT		 3675 num_iomem = num_port = 0;
3676 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3677 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3678 num_port++;
3679 if (first_port == -1)
3680 first_port = i;
3681 }
3682 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3683 num_iomem++;
3684 }
3685
3686 /*
3687 * If there is 1 or 0 iomem regions, and exactly one port,
3688 * use it. We guess the number of ports based on the IO
3689 * region size.
3690 */
3691 if (num_iomem <= 1 && num_port == 1) {
3692 board->flags = first_port;
3693 board->num_ports = pci_resource_len(dev, first_port) / 8;
3694 return 0;
3695 }
3696
3697 /*
3698 * Now guess if we've got a board which indexes by BARs.
3699 * Each IO BAR should be 8 bytes, and they should follow
3700 * consecutively.
3701 */
3702 first_port = -1;
3703 num_port = 0;
3704 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3705 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3706 pci_resource_len(dev, i) == 8 &&
3707 (first_port == -1 || (first_port + num_port) == i)) {
3708 num_port++;
3709 if (first_port == -1)
3710 first_port = i;
3711 }
3712 }
3713
3714 if (num_port > 1) {
3715 board->flags = first_port | FL_BASE_BARS;
3716 board->num_ports = num_port;
3717 return 0;
3718 }
3719
3720 return -ENODEV;
3721}
3722
3723static inline int
975a1a7d
RK		 3724serial_pci_matches(const struct pciserial_board *board,
3725 const struct pciserial_board *guessed)
1da177e4
LT		 3726{
3727 return
3728 board->num_ports == guessed->num_ports &&
3729 board->base_baud == guessed->base_baud &&
3730 board->uart_offset == guessed->uart_offset &&
3731 board->reg_shift == guessed->reg_shift &&
3732 board->first_offset == guessed->first_offset;
3733}
3734
241fc436 3735struct serial_private *
975a1a7d 3736pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 3737{
2655a2c7 3738 struct uart_8250_port uart;
1da177e4 3739 struct serial_private *priv;
1da177e4
LT		 3740 struct pci_serial_quirk *quirk;
3741 int rc, nr_ports, i;
3742
1da177e4
LT		 3743 nr_ports = board->num_ports;
3744
3745 /*
3746 * Find an init and setup quirks.
3747 */
3748 quirk = find_quirk(dev);
3749
3750 /*
3751 * Run the new-style initialization function.
3752 * The initialization function returns:
3753 * <0 - error
3754 * 0 - use board->num_ports
3755 * >0 - number of ports
3756 */
3757 if (quirk->init) {
3758 rc = quirk->init(dev);
241fc436
RK		 3759 if (rc < 0) {
3760 priv = ERR_PTR(rc);
3761 goto err_out;
3762 }
1da177e4
LT		 3763 if (rc)
3764 nr_ports = rc;
3765 }
3766
8f31bb39 3767 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 3768 sizeof(unsigned int) * nr_ports,
3769 GFP_KERNEL);
3770 if (!priv) {
241fc436
RK		 3771 priv = ERR_PTR(-ENOMEM);
3772 goto err_deinit;
1da177e4
LT		 3773 }
3774
70db3d91 3775 priv->dev = dev;
1da177e4 3776 priv->quirk = quirk;
1da177e4 3777
2655a2c7
AC		 3778 memset(&uart, 0, sizeof(uart));
3779 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3780 uart.port.uartclk = board->base_baud * 16;
3781 uart.port.irq = get_pci_irq(dev, board);
3782 uart.port.dev = &dev->dev;
72ce9a83 3783
1da177e4 3784 for (i = 0; i < nr_ports; i++) {
2655a2c7 3785 if (quirk->setup(priv, board, &uart, i))
1da177e4 3786 break;
72ce9a83 3787
af8c5b8d
GKH		 3788 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3789 uart.port.iobase, uart.port.irq, uart.port.iotype);
5756ee99 3790
2655a2c7 3791 priv->line[i] = serial8250_register_8250_port(&uart);
1da177e4 3792 if (priv->line[i] < 0) {
af8c5b8d
GKH		 3793 dev_err(&dev->dev,
3794 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3795 uart.port.iobase, uart.port.irq,
3796 uart.port.iotype, priv->line[i]);
1da177e4
LT		 3797 break;
3798 }
3799 }
1da177e4 3800 priv->nr = i;
241fc436 3801 return priv;
1da177e4 3802
5756ee99 3803err_deinit:
1da177e4
LT		 3804 if (quirk->exit)
3805 quirk->exit(dev);
5756ee99 3806err_out:
241fc436 3807 return priv;
1da177e4 3808}
241fc436 3809EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 3810
241fc436 3811void pciserial_remove_ports(struct serial_private *priv)
1da177e4 3812{
056a8763
RK		 3813 struct pci_serial_quirk *quirk;
3814 int i;
1da177e4 3815
056a8763
RK		 3816 for (i = 0; i < priv->nr; i++)
3817 serial8250_unregister_port(priv->line[i]);
1da177e4 3818
056a8763
RK		 3819 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3820 if (priv->remapped_bar[i])
3821 iounmap(priv->remapped_bar[i]);
3822 priv->remapped_bar[i] = NULL;
3823 }
1da177e4 3824
056a8763
RK		 3825 /*
3826 * Find the exit quirks.
3827 */
241fc436 3828 quirk = find_quirk(priv->dev);
056a8763 3829 if (quirk->exit)
241fc436
RK		 3830 quirk->exit(priv->dev);
3831
3832 kfree(priv);
3833}
3834EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3835
3836void pciserial_suspend_ports(struct serial_private *priv)
3837{
3838 int i;
3839
3840 for (i = 0; i < priv->nr; i++)
3841 if (priv->line[i] >= 0)
3842 serial8250_suspend_port(priv->line[i]);
5f1a3895
DW		 3843
3844 /*
3845 * Ensure that every init quirk is properly torn down
3846 */
3847 if (priv->quirk->exit)
3848 priv->quirk->exit(priv->dev);
241fc436
RK		 3849}
3850EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3851
3852void pciserial_resume_ports(struct serial_private *priv)
3853{
3854 int i;
3855
3856 /*
3857 * Ensure that the board is correctly configured.
3858 */
3859 if (priv->quirk->init)
3860 priv->quirk->init(priv->dev);
3861
3862 for (i = 0; i < priv->nr; i++)
3863 if (priv->line[i] >= 0)
3864 serial8250_resume_port(priv->line[i]);
3865}
3866EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3867
3868/*
3869 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3870 * to the arrangement of serial ports on a PCI card.
3871 */
9671f099 3872static int
241fc436
RK		 3873pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3874{
5bf8f501 3875 struct pci_serial_quirk *quirk;
241fc436 3876 struct serial_private *priv;
975a1a7d
RK		 3877 const struct pciserial_board *board;
3878 struct pciserial_board tmp;
241fc436
RK		 3879 int rc;
3880
5bf8f501
FB		 3881 quirk = find_quirk(dev);
3882 if (quirk->probe) {
3883 rc = quirk->probe(dev);
3884 if (rc)
3885 return rc;
3886 }
3887
241fc436 3888 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
af8c5b8d 3889 dev_err(&dev->dev, "invalid driver_data: %ld\n",
241fc436
RK		 3890 ent->driver_data);
3891 return -EINVAL;
3892 }
3893
3894 board = &pci_boards[ent->driver_data];
3895
3896 rc = pci_enable_device(dev);
2807190b 3897 pci_save_state(dev);
241fc436
RK		 3898 if (rc)
3899 return rc;
3900
3901 if (ent->driver_data == pbn_default) {
3902 /*
3903 * Use a copy of the pci_board entry for this;
3904 * avoid changing entries in the table.
3905 */
3906 memcpy(&tmp, board, sizeof(struct pciserial_board));
3907 board = &tmp;
3908
3909 /*
3910 * We matched one of our class entries. Try to
3911 * determine the parameters of this board.
3912 */
975a1a7d 3913 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 3914 if (rc)
3915 goto disable;
3916 } else {
3917 /*
3918 * We matched an explicit entry. If we are able to
3919 * detect this boards settings with our heuristic,
3920 * then we no longer need this entry.
3921 */
3922 memcpy(&tmp, &pci_boards[pbn_default],
3923 sizeof(struct pciserial_board));
3924 rc = serial_pci_guess_board(dev, &tmp);
3925 if (rc == 0 && serial_pci_matches(board, &tmp))
3926 moan_device("Redundant entry in serial pci_table.",
3927 dev);
3928 }
3929
3930 priv = pciserial_init_ports(dev, board);
3931 if (!IS_ERR(priv)) {
3932 pci_set_drvdata(dev, priv);
3933 return 0;
3934 }
3935
3936 rc = PTR_ERR(priv);
1da177e4 3937
241fc436 3938 disable:
056a8763 3939 pci_disable_device(dev);
241fc436
RK		 3940 return rc;
3941}
1da177e4 3942
ae8d8a14 3943static void pciserial_remove_one(struct pci_dev *dev)
241fc436
RK		 3944{
3945 struct serial_private *priv = pci_get_drvdata(dev);
3946
241fc436
RK		 3947 pciserial_remove_ports(priv);
3948
3949 pci_disable_device(dev);
1da177e4
LT		 3950}
3951
1d5e7996 3952#ifdef CONFIG_PM
1da177e4
LT		 3953static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3954{
3955 struct serial_private *priv = pci_get_drvdata(dev);
3956
241fc436
RK		 3957 if (priv)
3958 pciserial_suspend_ports(priv);
1da177e4 3959
1da177e4
LT		 3960 pci_save_state(dev);
3961 pci_set_power_state(dev, pci_choose_state(dev, state));
3962 return 0;
3963}
3964
3965static int pciserial_resume_one(struct pci_dev *dev)
3966{
ccb9d59e 3967 int err;
1da177e4
LT		 3968 struct serial_private *priv = pci_get_drvdata(dev);
3969
3970 pci_set_power_state(dev, PCI_D0);
3971 pci_restore_state(dev);
3972
3973 if (priv) {
1da177e4
LT		 3974 /*
3975 * The device may have been disabled. Re-enable it.
3976 */
ccb9d59e 3977 err = pci_enable_device(dev);
40836c48 3978 /* FIXME: We cannot simply error out here */
ccb9d59e 3979 if (err)
af8c5b8d 3980 dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n");
241fc436 3981 pciserial_resume_ports(priv);
1da177e4
LT		 3982 }
3983 return 0;
3984}
1d5e7996 3985#endif
1da177e4
LT		 3986
3987static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 3988 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3989 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3990 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3991 pbn_b2_8_921600 },
0c6d774c
TW		 3992 /* Advantech also use 0x3618 and 0xf618 */
3993 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
3994 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3995 pbn_b0_4_921600 },
3996 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
3997 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3998 pbn_b0_4_921600 },
1da177e4
LT		 3999 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4000 PCI_SUBVENDOR_ID_CONNECT_TECH,
4001 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4002 pbn_b1_8_1382400 },
4003 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4004 PCI_SUBVENDOR_ID_CONNECT_TECH,
4005 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4006 pbn_b1_4_1382400 },
4007 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4008 PCI_SUBVENDOR_ID_CONNECT_TECH,
4009 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4010 pbn_b1_2_1382400 },
4011 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4012 PCI_SUBVENDOR_ID_CONNECT_TECH,
4013 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4014 pbn_b1_8_1382400 },
4015 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4016 PCI_SUBVENDOR_ID_CONNECT_TECH,
4017 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4018 pbn_b1_4_1382400 },
4019 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4020 PCI_SUBVENDOR_ID_CONNECT_TECH,
4021 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4022 pbn_b1_2_1382400 },
4023 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4024 PCI_SUBVENDOR_ID_CONNECT_TECH,
4025 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4026 pbn_b1_8_921600 },
4027 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4028 PCI_SUBVENDOR_ID_CONNECT_TECH,
4029 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4030 pbn_b1_8_921600 },
4031 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4032 PCI_SUBVENDOR_ID_CONNECT_TECH,
4033 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4034 pbn_b1_4_921600 },
4035 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4036 PCI_SUBVENDOR_ID_CONNECT_TECH,
4037 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4038 pbn_b1_4_921600 },
4039 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4040 PCI_SUBVENDOR_ID_CONNECT_TECH,
4041 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4042 pbn_b1_2_921600 },
4043 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4044 PCI_SUBVENDOR_ID_CONNECT_TECH,
4045 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4046 pbn_b1_8_921600 },
4047 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4048 PCI_SUBVENDOR_ID_CONNECT_TECH,
4049 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4050 pbn_b1_8_921600 },
4051 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4052 PCI_SUBVENDOR_ID_CONNECT_TECH,
4053 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4054 pbn_b1_4_921600 },
26e92861
GH		 4055 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4056 PCI_SUBVENDOR_ID_CONNECT_TECH,
4057 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4058 pbn_b1_2_1250000 },
4059 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4060 PCI_SUBVENDOR_ID_CONNECT_TECH,
4061 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4062 pbn_b0_2_1843200 },
4063 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4064 PCI_SUBVENDOR_ID_CONNECT_TECH,
4065 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4066 pbn_b0_4_1843200 },
85d1494e
YY		 4067 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4068 PCI_VENDOR_ID_AFAVLAB,
4069 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4070 pbn_b0_4_1152000 },
26e92861
GH		 4071 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4072 PCI_SUBVENDOR_ID_CONNECT_TECH,
4073 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4074 pbn_b0_2_1843200_200 },
4075 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4076 PCI_SUBVENDOR_ID_CONNECT_TECH,
4077 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4078 pbn_b0_4_1843200_200 },
4079 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4080 PCI_SUBVENDOR_ID_CONNECT_TECH,
4081 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4082 pbn_b0_8_1843200_200 },
4083 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4084 PCI_SUBVENDOR_ID_CONNECT_TECH,
4085 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4086 pbn_b0_2_1843200_200 },
4087 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4088 PCI_SUBVENDOR_ID_CONNECT_TECH,
4089 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4090 pbn_b0_4_1843200_200 },
4091 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4092 PCI_SUBVENDOR_ID_CONNECT_TECH,
4093 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4094 pbn_b0_8_1843200_200 },
4095 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4096 PCI_SUBVENDOR_ID_CONNECT_TECH,
4097 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4098 pbn_b0_2_1843200_200 },
4099 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4100 PCI_SUBVENDOR_ID_CONNECT_TECH,
4101 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4102 pbn_b0_4_1843200_200 },
4103 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4104 PCI_SUBVENDOR_ID_CONNECT_TECH,
4105 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4106 pbn_b0_8_1843200_200 },
4107 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4108 PCI_SUBVENDOR_ID_CONNECT_TECH,
4109 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4110 pbn_b0_2_1843200_200 },
4111 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4112 PCI_SUBVENDOR_ID_CONNECT_TECH,
4113 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4114 pbn_b0_4_1843200_200 },
4115 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4116 PCI_SUBVENDOR_ID_CONNECT_TECH,
4117 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4118 pbn_b0_8_1843200_200 },
c68d2b15
BH		 4119 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4120 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4121 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 4122
4123 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 4124 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4125 pbn_b2_bt_1_115200 },
4126 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 4127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4128 pbn_b2_bt_2_115200 },
4129 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 4130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4131 pbn_b2_bt_4_115200 },
4132 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 4133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4134 pbn_b2_bt_2_115200 },
4135 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 4136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4137 pbn_b2_bt_4_115200 },
4138 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 4139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 4140 pbn_b2_8_115200 },
e65f0f82
FL		 4141 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4143 pbn_b2_8_460800 },
1da177e4
LT		 4144 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4145 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4146 pbn_b2_8_115200 },
4147
4148 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4150 pbn_b2_bt_2_115200 },
4151 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4153 pbn_b2_bt_2_921600 },
4154 /*
4155 * VScom SPCOM800, from sl@s.pl
4156 */
5756ee99
AC		 4157 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4159 pbn_b2_8_921600 },
4160 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 4161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 4162 pbn_b2_4_921600 },
b76c5a07
CB		 4163 /* Unknown card - subdevice 0x1584 */
4164 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4165 PCI_VENDOR_ID_PLX,
4166 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
d13402a4
SA		 4167 pbn_b2_4_115200 },
4168 /* Unknown card - subdevice 0x1588 */
4169 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4170 PCI_VENDOR_ID_PLX,
4171 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4172 pbn_b2_8_115200 },
1da177e4
LT		 4173 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4174 PCI_SUBVENDOR_ID_KEYSPAN,
4175 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4176 pbn_panacom },
4177 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4178 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4179 pbn_panacom4 },
4180 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4181 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4182 pbn_panacom2 },
a9cccd34
MF		 4183 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4184 PCI_VENDOR_ID_ESDGMBH,
4185 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4186 pbn_b2_4_115200 },
1da177e4
LT		 4187 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4188 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4189 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 4190 pbn_b2_4_460800 },
4191 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4192 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4193 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 4194 pbn_b2_8_460800 },
4195 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4196 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4197 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 4198 pbn_b2_16_460800 },
4199 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4200 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 4201 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 4202 pbn_b2_16_460800 },
4203 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4204 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4205 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 4206 pbn_b2_4_460800 },
4207 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4208 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 4209 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 4210 pbn_b2_8_460800 },
add7b58e
BH		 4211 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4212 PCI_SUBVENDOR_ID_EXSYS,
4213 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
ee4cd1b2 4214 pbn_b2_4_115200 },
1da177e4
LT		 4215 /*
4216 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4217 * (Exoray@isys.ca)
4218 */
4219 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4220 0x10b5, 0x106a, 0, 0,
4221 pbn_plx_romulus },
1bc8cde4
MS		 4222 /*
4223 * EndRun Technologies. PCI express device range.
4224 * EndRun PTP/1588 has 2 Native UARTs.
4225 */
4226 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4227 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4228 pbn_endrun_2_4000000 },
55c7c0fd
AC		 4229 /*
4230 * Quatech cards. These actually have configurable clocks but for
4231 * now we just use the default.
4232 *
4233 * 100 series are RS232, 200 series RS422,
4234 */
1da177e4
LT		 4235 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4237 pbn_b1_4_115200 },
4238 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4239 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4240 pbn_b1_2_115200 },
55c7c0fd
AC		 4241 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4242 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4243 pbn_b2_2_115200 },
4244 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4245 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4246 pbn_b1_2_115200 },
4247 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4248 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4249 pbn_b2_2_115200 },
4250 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4251 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4252 pbn_b1_4_115200 },
1da177e4
LT		 4253 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4255 pbn_b1_8_115200 },
4256 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4258 pbn_b1_8_115200 },
55c7c0fd
AC		 4259 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4261 pbn_b1_4_115200 },
4262 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4264 pbn_b1_2_115200 },
4265 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4267 pbn_b1_4_115200 },
4268 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4270 pbn_b1_2_115200 },
4271 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4273 pbn_b2_4_115200 },
4274 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4275 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4276 pbn_b2_2_115200 },
4277 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4279 pbn_b2_1_115200 },
4280 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4282 pbn_b2_4_115200 },
4283 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4285 pbn_b2_2_115200 },
4286 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4288 pbn_b2_1_115200 },
4289 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4291 pbn_b0_8_115200 },
4292
1da177e4 4293 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4294 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4295 0, 0,
1da177e4 4296 pbn_b0_4_921600 },
fbc0dc0d 4297 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 4298 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4299 0, 0,
fbc0dc0d 4300 pbn_b0_4_1152000 },
c9bd9d01
MP		 4301 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4303 pbn_b0_bt_2_921600 },
db1de159
DR		 4304
4305 /*
4306 * The below card is a little controversial since it is the
4307 * subject of a PCI vendor/device ID clash. (See
4308 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4309 * For now just used the hex ID 0x950a.
4310 */
39aced68 4311 { PCI_VENDOR_ID_OXSEMI, 0x950a,
26e8220a
FL		 4312 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4313 0, 0, pbn_b0_2_115200 },
4314 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4315 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4316 0, 0, pbn_b0_2_115200 },
db1de159
DR		 4317 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4319 pbn_b0_2_1130000 },
70fd8fde
AP		 4320 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4321 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4322 pbn_b0_1_921600 },
1da177e4
LT		 4323 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4325 pbn_b0_4_115200 },
4326 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4327 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4328 pbn_b0_bt_2_921600 },
e847003f
LB		 4329 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4330 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4331 pbn_b2_8_1152000 },
1da177e4 4332
7106b4e3
LH		 4333 /*
4334 * Oxford Semiconductor Inc. Tornado PCI express device range.
4335 */
4336 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4337 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4338 pbn_b0_1_4000000 },
4339 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4341 pbn_b0_1_4000000 },
4342 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4343 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4344 pbn_oxsemi_1_4000000 },
4345 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4346 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4347 pbn_oxsemi_1_4000000 },
4348 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4349 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4350 pbn_b0_1_4000000 },
4351 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4352 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4353 pbn_b0_1_4000000 },
4354 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4355 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4356 pbn_oxsemi_1_4000000 },
4357 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4358 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4359 pbn_oxsemi_1_4000000 },
4360 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4361 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4362 pbn_b0_1_4000000 },
4363 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4364 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4365 pbn_b0_1_4000000 },
4366 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4367 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4368 pbn_b0_1_4000000 },
4369 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4370 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4371 pbn_b0_1_4000000 },
4372 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4373 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4374 pbn_oxsemi_2_4000000 },
4375 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4376 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4377 pbn_oxsemi_2_4000000 },
4378 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4379 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4380 pbn_oxsemi_4_4000000 },
4381 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4382 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4383 pbn_oxsemi_4_4000000 },
4384 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4385 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4386 pbn_oxsemi_8_4000000 },
4387 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4388 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4389 pbn_oxsemi_8_4000000 },
4390 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4391 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4392 pbn_oxsemi_1_4000000 },
4393 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4395 pbn_oxsemi_1_4000000 },
4396 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4398 pbn_oxsemi_1_4000000 },
4399 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4401 pbn_oxsemi_1_4000000 },
4402 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4404 pbn_oxsemi_1_4000000 },
4405 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4407 pbn_oxsemi_1_4000000 },
4408 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4410 pbn_oxsemi_1_4000000 },
4411 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4413 pbn_oxsemi_1_4000000 },
4414 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4416 pbn_oxsemi_1_4000000 },
4417 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4419 pbn_oxsemi_1_4000000 },
4420 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4422 pbn_oxsemi_1_4000000 },
4423 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4425 pbn_oxsemi_1_4000000 },
4426 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4428 pbn_oxsemi_1_4000000 },
4429 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4431 pbn_oxsemi_1_4000000 },
4432 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4434 pbn_oxsemi_1_4000000 },
4435 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4437 pbn_oxsemi_1_4000000 },
4438 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4440 pbn_oxsemi_1_4000000 },
4441 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4443 pbn_oxsemi_1_4000000 },
4444 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4446 pbn_oxsemi_1_4000000 },
4447 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4449 pbn_oxsemi_1_4000000 },
4450 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4452 pbn_oxsemi_1_4000000 },
4453 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4455 pbn_oxsemi_1_4000000 },
4456 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4457 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4458 pbn_oxsemi_1_4000000 },
4459 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4460 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4461 pbn_oxsemi_1_4000000 },
4462 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4464 pbn_oxsemi_1_4000000 },
4465 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4466 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4467 pbn_oxsemi_1_4000000 },
b80de369
LH		 4468 /*
4469 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4470 */
4471 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4472 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4473 pbn_oxsemi_1_4000000 },
4474 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4475 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4476 pbn_oxsemi_2_4000000 },
4477 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4478 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4479 pbn_oxsemi_4_4000000 },
4480 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4481 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4482 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 4483
4484 /*
4485 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4486 */
4487 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4488 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4489 pbn_oxsemi_2_4000000 },
4490
1da177e4
LT		 4491 /*
4492 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4493 * from skokodyn@yahoo.com
4494 */
4495 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4496 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4497 pbn_sbsxrsio },
4498 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4499 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4500 pbn_sbsxrsio },
4501 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4502 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4503 pbn_sbsxrsio },
4504 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4505 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4506 pbn_sbsxrsio },
4507
4508 /*
4509 * Digitan DS560-558, from jimd@esoft.com
4510 */
4511 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4513 pbn_b1_1_115200 },
4514
4515 /*
4516 * Titan Electronic cards
4517 * The 400L and 800L have a custom setup quirk.
4518 */
4519 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 4520 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4521 pbn_b0_1_921600 },
4522 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 4523 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4524 pbn_b0_2_921600 },
4525 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 4526 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4527 pbn_b0_4_921600 },
4528 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 4529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 4530 pbn_b0_4_921600 },
4531 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4532 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4533 pbn_b1_1_921600 },
4534 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4535 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4536 pbn_b1_bt_2_921600 },
4537 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4538 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4539 pbn_b0_bt_4_921600 },
4540 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4541 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4542 pbn_b0_bt_8_921600 },
66169ad1
YY		 4543 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4544 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4545 pbn_b4_bt_2_921600 },
4546 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4548 pbn_b4_bt_4_921600 },
4549 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4550 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4551 pbn_b4_bt_8_921600 },
4552 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4553 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4554 pbn_b0_4_921600 },
4555 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4556 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4557 pbn_b0_4_921600 },
4558 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4559 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4560 pbn_b0_4_921600 },
4561 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4562 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4563 pbn_oxsemi_1_4000000 },
4564 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4565 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4566 pbn_oxsemi_2_4000000 },
4567 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4568 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4569 pbn_oxsemi_4_4000000 },
4570 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4571 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4572 pbn_oxsemi_8_4000000 },
4573 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4574 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4575 pbn_oxsemi_2_4000000 },
4576 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4577 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4578 pbn_oxsemi_2_4000000 },
48c0247d
YY		 4579 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4581 pbn_b0_bt_2_921600 },
1e9deb11
YY		 4582 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4584 pbn_b0_4_921600 },
4585 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587 pbn_b0_4_921600 },
4588 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590 pbn_b0_4_921600 },
4591 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 pbn_b0_4_921600 },
1da177e4
LT		 4594
4595 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4596 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4597 pbn_b2_1_460800 },
4598 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4599 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4600 pbn_b2_1_460800 },
4601 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4603 pbn_b2_1_460800 },
4604 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4605 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4606 pbn_b2_bt_2_921600 },
4607 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4608 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4609 pbn_b2_bt_2_921600 },
4610 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4611 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4612 pbn_b2_bt_2_921600 },
4613 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4614 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4615 pbn_b2_bt_4_921600 },
4616 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4617 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4618 pbn_b2_bt_4_921600 },
4619 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4620 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4621 pbn_b2_bt_4_921600 },
4622 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4624 pbn_b0_1_921600 },
4625 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4627 pbn_b0_1_921600 },
4628 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4630 pbn_b0_1_921600 },
4631 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4633 pbn_b0_bt_2_921600 },
4634 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4636 pbn_b0_bt_2_921600 },
4637 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639 pbn_b0_bt_2_921600 },
4640 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642 pbn_b0_bt_4_921600 },
4643 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4644 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4645 pbn_b0_bt_4_921600 },
4646 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4647 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4648 pbn_b0_bt_4_921600 },
3ec9c594
AP		 4649 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4650 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4651 pbn_b0_bt_8_921600 },
4652 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4654 pbn_b0_bt_8_921600 },
4655 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4657 pbn_b0_bt_8_921600 },
1da177e4
LT		 4658
4659 /*
4660 * Computone devices submitted by Doug McNash dmcnash@computone.com
4661 */
4662 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4663 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4664 0, 0, pbn_computone_4 },
4665 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4666 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4667 0, 0, pbn_computone_8 },
4668 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4669 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4670 0, 0, pbn_computone_6 },
4671
4672 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4673 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4674 pbn_oxsemi },
4675 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4676 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4677 pbn_b0_bt_1_921600 },
4678
abd7baca
SC		 4679 /*
4680 * SUNIX (TIMEDIA)
4681 */
4682 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4683 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4684 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4685 pbn_b0_bt_1_921600 },
4686
4687 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4688 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4689 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4690 pbn_b0_bt_1_921600 },
4691
1da177e4
LT		 4692 /*
4693 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4694 */
4695 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4696 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4697 pbn_b0_bt_8_115200 },
4698 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4699 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4700 pbn_b0_bt_8_115200 },
4701
4702 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4703 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4704 pbn_b0_bt_2_115200 },
4705 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4707 pbn_b0_bt_2_115200 },
4708 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 4711 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4713 pbn_b0_bt_2_115200 },
4714 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4716 pbn_b0_bt_2_115200 },
1da177e4
LT		 4717 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4719 pbn_b0_bt_4_460800 },
4720 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4722 pbn_b0_bt_4_460800 },
4723 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4724 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4725 pbn_b0_bt_2_460800 },
4726 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728 pbn_b0_bt_2_460800 },
4729 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4731 pbn_b0_bt_2_460800 },
4732 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734 pbn_b0_bt_1_115200 },
4735 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4736 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4737 pbn_b0_bt_1_460800 },
4738
1fb8cacc
RK		 4739 /*
4740 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4741 * Cards are identified by their subsystem vendor IDs, which
4742 * (in hex) match the model number.
4743 *
4744 * Note that JC140x are RS422/485 cards which require ox950
4745 * ACR = 0x10, and as such are not currently fully supported.
4746 */
4747 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4748 0x1204, 0x0004, 0, 0,
4749 pbn_b0_4_921600 },
4750 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4751 0x1208, 0x0004, 0, 0,
4752 pbn_b0_4_921600 },
4753/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4754 0x1402, 0x0002, 0, 0,
4755 pbn_b0_2_921600 }, */
4756/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4757 0x1404, 0x0004, 0, 0,
4758 pbn_b0_4_921600 }, */
4759 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4760 0x1208, 0x0004, 0, 0,
4761 pbn_b0_4_921600 },
4762
2a52fcb5
KY		 4763 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4764 0x1204, 0x0004, 0, 0,
4765 pbn_b0_4_921600 },
4766 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4767 0x1208, 0x0004, 0, 0,
4768 pbn_b0_4_921600 },
4769 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4770 0x1208, 0x0004, 0, 0,
4771 pbn_b0_4_921600 },
1da177e4
LT		 4772 /*
4773 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4774 */
4775 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4776 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4777 pbn_b1_1_1382400 },
4778
4779 /*
4780 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4781 */
4782 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4783 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4784 pbn_b1_1_1382400 },
4785
4786 /*
4787 * RAStel 2 port modem, gerg@moreton.com.au
4788 */
4789 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4791 pbn_b2_bt_2_115200 },
4792
4793 /*
4794 * EKF addition for i960 Boards form EKF with serial port
4795 */
4796 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4797 0xE4BF, PCI_ANY_ID, 0, 0,
4798 pbn_intel_i960 },
4799
4800 /*
4801 * Xircom Cardbus/Ethernet combos
4802 */
4803 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4805 pbn_b0_1_115200 },
4806 /*
4807 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4808 */
4809 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4811 pbn_b0_1_115200 },
4812
4813 /*
4814 * Untested PCI modems, sent in from various folks...
4815 */
4816
4817 /*
4818 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4819 */
4820 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4821 0x1048, 0x1500, 0, 0,
4822 pbn_b1_1_115200 },
4823
4824 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4825 0xFF00, 0, 0, 0,
4826 pbn_sgi_ioc3 },
4827
4828 /*
4829 * HP Diva card
4830 */
4831 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4832 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4833 pbn_b1_1_115200 },
4834 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4835 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4836 pbn_b0_5_115200 },
4837 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4838 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4839 pbn_b2_1_115200 },
4840
d9004eb4
ABL		 4841 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4842 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4843 pbn_b3_2_115200 },
1da177e4
LT		 4844 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4845 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4846 pbn_b3_4_115200 },
4847 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4848 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4849 pbn_b3_8_115200 },
4850
4851 /*
4852 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4853 */
4854 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4855 PCI_ANY_ID, PCI_ANY_ID,
4856 0,
4857 0, pbn_exar_XR17C152 },
4858 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4859 PCI_ANY_ID, PCI_ANY_ID,
4860 0,
4861 0, pbn_exar_XR17C154 },
4862 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4863 PCI_ANY_ID, PCI_ANY_ID,
4864 0,
4865 0, pbn_exar_XR17C158 },
dc96efb7
MS		 4866 /*
4867 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4868 */
4869 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4870 PCI_ANY_ID, PCI_ANY_ID,
4871 0,
4872 0, pbn_exar_XR17V352 },
4873 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4874 PCI_ANY_ID, PCI_ANY_ID,
4875 0,
4876 0, pbn_exar_XR17V354 },
4877 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4878 PCI_ANY_ID, PCI_ANY_ID,
4879 0,
4880 0, pbn_exar_XR17V358 },
1da177e4
LT		 4881
4882 /*
4883 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4884 */
4885 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4887 pbn_b0_1_115200 },
84f8c6fc
NV		 4888 /*
4889 * ITE
4890 */
4891 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4892 PCI_ANY_ID, PCI_ANY_ID,
4893 0, 0,
4894 pbn_b1_bt_1_115200 },
1da177e4 4895
737c1756
PH		 4896 /*
4897 * IntaShield IS-200
4898 */
4899 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4900 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4901 pbn_b2_2_115200 },
4b6f6ce9
IGP		 4902 /*
4903 * IntaShield IS-400
4904 */
4905 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4906 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4907 pbn_b2_4_115200 },
48212008
TH		 4908 /*
4909 * Perle PCI-RAS cards
4910 */
4911 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4912 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4913 0, 0, pbn_b2_4_921600 },
4914 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4915 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4916 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 4917
4918 /*
4919 * Mainpine series cards: Fairly standard layout but fools
4920 * parts of the autodetect in some cases and uses otherwise
4921 * unmatched communications subclasses in the PCI Express case
4922 */
4923
4924 { /* RockForceDUO */
4925 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4926 PCI_VENDOR_ID_MAINPINE, 0x0200,
4927 0, 0, pbn_b0_2_115200 },
4928 { /* RockForceQUATRO */
4929 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4930 PCI_VENDOR_ID_MAINPINE, 0x0300,
4931 0, 0, pbn_b0_4_115200 },
4932 { /* RockForceDUO+ */
4933 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4934 PCI_VENDOR_ID_MAINPINE, 0x0400,
4935 0, 0, pbn_b0_2_115200 },
4936 { /* RockForceQUATRO+ */
4937 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4938 PCI_VENDOR_ID_MAINPINE, 0x0500,
4939 0, 0, pbn_b0_4_115200 },
4940 { /* RockForce+ */
4941 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4942 PCI_VENDOR_ID_MAINPINE, 0x0600,
4943 0, 0, pbn_b0_2_115200 },
4944 { /* RockForce+ */
4945 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4946 PCI_VENDOR_ID_MAINPINE, 0x0700,
4947 0, 0, pbn_b0_4_115200 },
4948 { /* RockForceOCTO+ */
4949 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4950 PCI_VENDOR_ID_MAINPINE, 0x0800,
4951 0, 0, pbn_b0_8_115200 },
4952 { /* RockForceDUO+ */
4953 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4954 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4955 0, 0, pbn_b0_2_115200 },
4956 { /* RockForceQUARTRO+ */
4957 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4958 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4959 0, 0, pbn_b0_4_115200 },
4960 { /* RockForceOCTO+ */
4961 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4962 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4963 0, 0, pbn_b0_8_115200 },
4964 { /* RockForceD1 */
4965 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4966 PCI_VENDOR_ID_MAINPINE, 0x2000,
4967 0, 0, pbn_b0_1_115200 },
4968 { /* RockForceF1 */
4969 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4970 PCI_VENDOR_ID_MAINPINE, 0x2100,
4971 0, 0, pbn_b0_1_115200 },
4972 { /* RockForceD2 */
4973 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4974 PCI_VENDOR_ID_MAINPINE, 0x2200,
4975 0, 0, pbn_b0_2_115200 },
4976 { /* RockForceF2 */
4977 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4978 PCI_VENDOR_ID_MAINPINE, 0x2300,
4979 0, 0, pbn_b0_2_115200 },
4980 { /* RockForceD4 */
4981 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4982 PCI_VENDOR_ID_MAINPINE, 0x2400,
4983 0, 0, pbn_b0_4_115200 },
4984 { /* RockForceF4 */
4985 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4986 PCI_VENDOR_ID_MAINPINE, 0x2500,
4987 0, 0, pbn_b0_4_115200 },
4988 { /* RockForceD8 */
4989 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4990 PCI_VENDOR_ID_MAINPINE, 0x2600,
4991 0, 0, pbn_b0_8_115200 },
4992 { /* RockForceF8 */
4993 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4994 PCI_VENDOR_ID_MAINPINE, 0x2700,
4995 0, 0, pbn_b0_8_115200 },
4996 { /* IQ Express D1 */
4997 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4998 PCI_VENDOR_ID_MAINPINE, 0x3000,
4999 0, 0, pbn_b0_1_115200 },
5000 { /* IQ Express F1 */
5001 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5002 PCI_VENDOR_ID_MAINPINE, 0x3100,
5003 0, 0, pbn_b0_1_115200 },
5004 { /* IQ Express D2 */
5005 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5006 PCI_VENDOR_ID_MAINPINE, 0x3200,
5007 0, 0, pbn_b0_2_115200 },
5008 { /* IQ Express F2 */
5009 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5010 PCI_VENDOR_ID_MAINPINE, 0x3300,
5011 0, 0, pbn_b0_2_115200 },
5012 { /* IQ Express D4 */
5013 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5014 PCI_VENDOR_ID_MAINPINE, 0x3400,
5015 0, 0, pbn_b0_4_115200 },
5016 { /* IQ Express F4 */
5017 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5018 PCI_VENDOR_ID_MAINPINE, 0x3500,
5019 0, 0, pbn_b0_4_115200 },
5020 { /* IQ Express D8 */
5021 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5022 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5023 0, 0, pbn_b0_8_115200 },
5024 { /* IQ Express F8 */
5025 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5026 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5027 0, 0, pbn_b0_8_115200 },
5028
5029
aa798505
OJ		 5030 /*
5031 * PA Semi PA6T-1682M on-chip UART
5032 */
5033 { PCI_VENDOR_ID_PASEMI, 0xa004,
5034 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5035 pbn_pasemi_1682M },
5036
46a0fac9
SB		 5037 /*
5038 * National Instruments
5039 */
04bf7e74
WP		 5040 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5041 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5042 pbn_b1_16_115200 },
5043 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5044 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5045 pbn_b1_8_115200 },
5046 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5047 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5048 pbn_b1_bt_4_115200 },
5049 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5050 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5051 pbn_b1_bt_2_115200 },
5052 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5053 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5054 pbn_b1_bt_4_115200 },
5055 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5056 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5057 pbn_b1_bt_2_115200 },
5058 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5059 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5060 pbn_b1_16_115200 },
5061 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5062 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5063 pbn_b1_8_115200 },
5064 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5065 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5066 pbn_b1_bt_4_115200 },
5067 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5068 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5069 pbn_b1_bt_2_115200 },
5070 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5071 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5072 pbn_b1_bt_4_115200 },
5073 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5074 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5075 pbn_b1_bt_2_115200 },
46a0fac9
SB		 5076 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5077 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5078 pbn_ni8430_2 },
5079 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5080 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5081 pbn_ni8430_2 },
5082 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5083 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5084 pbn_ni8430_4 },
5085 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5086 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5087 pbn_ni8430_4 },
5088 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5089 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5090 pbn_ni8430_8 },
5091 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5092 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5093 pbn_ni8430_8 },
5094 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5095 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5096 pbn_ni8430_16 },
5097 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5098 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5099 pbn_ni8430_16 },
5100 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5101 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5102 pbn_ni8430_2 },
5103 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5104 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5105 pbn_ni8430_2 },
5106 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5108 pbn_ni8430_4 },
5109 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5110 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5111 pbn_ni8430_4 },
5112
02c9b5cf
KJ		 5113 /*
5114 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5115 */
5116 { PCI_VENDOR_ID_ADDIDATA,
5117 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5118 PCI_ANY_ID,
5119 PCI_ANY_ID,
5120 0,
5121 0,
5122 pbn_b0_4_115200 },
5123
5124 { PCI_VENDOR_ID_ADDIDATA,
5125 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5126 PCI_ANY_ID,
5127 PCI_ANY_ID,
5128 0,
5129 0,
5130 pbn_b0_2_115200 },
5131
5132 { PCI_VENDOR_ID_ADDIDATA,
5133 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5134 PCI_ANY_ID,
5135 PCI_ANY_ID,
5136 0,
5137 0,
5138 pbn_b0_1_115200 },
5139
086231f7 5140 { PCI_VENDOR_ID_AMCC,
57c1f0e9 5141 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
02c9b5cf
KJ		 5142 PCI_ANY_ID,
5143 PCI_ANY_ID,
5144 0,
5145 0,
5146 pbn_b1_8_115200 },
5147
5148 { PCI_VENDOR_ID_ADDIDATA,
5149 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5150 PCI_ANY_ID,
5151 PCI_ANY_ID,
5152 0,
5153 0,
5154 pbn_b0_4_115200 },
5155
5156 { PCI_VENDOR_ID_ADDIDATA,
5157 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5158 PCI_ANY_ID,
5159 PCI_ANY_ID,
5160 0,
5161 0,
5162 pbn_b0_2_115200 },
5163
5164 { PCI_VENDOR_ID_ADDIDATA,
5165 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5166 PCI_ANY_ID,
5167 PCI_ANY_ID,
5168 0,
5169 0,
5170 pbn_b0_1_115200 },
5171
5172 { PCI_VENDOR_ID_ADDIDATA,
5173 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5174 PCI_ANY_ID,
5175 PCI_ANY_ID,
5176 0,
5177 0,
5178 pbn_b0_4_115200 },
5179
5180 { PCI_VENDOR_ID_ADDIDATA,
5181 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5182 PCI_ANY_ID,
5183 PCI_ANY_ID,
5184 0,
5185 0,
5186 pbn_b0_2_115200 },
5187
5188 { PCI_VENDOR_ID_ADDIDATA,
5189 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5190 PCI_ANY_ID,
5191 PCI_ANY_ID,
5192 0,
5193 0,
5194 pbn_b0_1_115200 },
5195
5196 { PCI_VENDOR_ID_ADDIDATA,
5197 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5198 PCI_ANY_ID,
5199 PCI_ANY_ID,
5200 0,
5201 0,
5202 pbn_b0_8_115200 },
5203
1b62cbf2
KJ		 5204 { PCI_VENDOR_ID_ADDIDATA,
5205 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5206 PCI_ANY_ID,
5207 PCI_ANY_ID,
5208 0,
5209 0,
5210 pbn_ADDIDATA_PCIe_4_3906250 },
5211
5212 { PCI_VENDOR_ID_ADDIDATA,
5213 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5214 PCI_ANY_ID,
5215 PCI_ANY_ID,
5216 0,
5217 0,
5218 pbn_ADDIDATA_PCIe_2_3906250 },
5219
5220 { PCI_VENDOR_ID_ADDIDATA,
5221 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5222 PCI_ANY_ID,
5223 PCI_ANY_ID,
5224 0,
5225 0,
5226 pbn_ADDIDATA_PCIe_1_3906250 },
5227
5228 { PCI_VENDOR_ID_ADDIDATA,
5229 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5230 PCI_ANY_ID,
5231 PCI_ANY_ID,
5232 0,
5233 0,
5234 pbn_ADDIDATA_PCIe_8_3906250 },
5235
25cf9bc1
JS		 5236 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5237 PCI_VENDOR_ID_IBM, 0x0299,
5238 0, 0, pbn_b0_bt_2_115200 },
5239
972ce085
SS		 5240 /*
5241 * other NetMos 9835 devices are most likely handled by the
5242 * parport_serial driver, check drivers/parport/parport_serial.c
5243 * before adding them here.
5244 */
5245
c4285b47
MB		 5246 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5247 0xA000, 0x1000,
5248 0, 0, pbn_b0_1_115200 },
5249
7808edcd
NG		 5250 /* the 9901 is a rebranded 9912 */
5251 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5252 0xA000, 0x1000,
5253 0, 0, pbn_b0_1_115200 },
5254
5255 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5256 0xA000, 0x1000,
5257 0, 0, pbn_b0_1_115200 },
5258
5259 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5260 0xA000, 0x1000,
5261 0, 0, pbn_b0_1_115200 },
5262
5263 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5264 0xA000, 0x1000,
5265 0, 0, pbn_b0_1_115200 },
5266
5267 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5268 0xA000, 0x3002,
5269 0, 0, pbn_NETMOS9900_2s_115200 },
5270
ac6ec5b1 5271 /*
44178176 5272 * Best Connectivity and Rosewill PCI Multi I/O cards
ac6ec5b1
IS		 5273 */
5274
5275 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5276 0xA000, 0x1000,
5277 0, 0, pbn_b0_1_115200 },
5278
44178176
ES		 5279 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5280 0xA000, 0x3002,
5281 0, 0, pbn_b0_bt_2_115200 },
5282
ac6ec5b1
IS		 5283 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5284 0xA000, 0x3004,
5285 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 5286 /* Intel CE4100 */
5287 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5288 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5289 pbn_ce4100_1_115200 },
b15e5691
HK		 5290 /* Intel BayTrail */
5291 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5292 PCI_ANY_ID, PCI_ANY_ID,
5293 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5294 pbn_byt },
5295 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5296 PCI_ANY_ID, PCI_ANY_ID,
5297 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5298 pbn_byt },
29897087
AC		 5299 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5300 PCI_ANY_ID, PCI_ANY_ID,
5301 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5302 pbn_byt },
5303 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
b15e5691
HK		 5304 PCI_ANY_ID, PCI_ANY_ID,
5305 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5306 pbn_byt },
095e24b0 5307
1ede7dcc
BD		 5308 /*
5309 * Intel Quark x1000
5310 */
5311 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5313 pbn_qrk },
d9a0fbfd
AP		 5314 /*
5315 * Cronyx Omega PCI
5316 */
5317 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5319 pbn_omegapci },
ac6ec5b1 5320
ebebd49a
SH		 5321 /*
5322 * Broadcom TruManage
5323 */
5324 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5325 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5326 pbn_brcm_trumanage },
5327
6683549e
AC		 5328 /*
5329 * AgeStar as-prs2-009
5330 */
5331 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5332 PCI_ANY_ID, PCI_ANY_ID,
5333 0, 0, pbn_b0_bt_2_115200 },
27788c5f
AC		 5334
5335 /*
5336 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5337 * so not listed here.
5338 */
5339 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5340 PCI_ANY_ID, PCI_ANY_ID,
5341 0, 0, pbn_b0_bt_4_115200 },
5342
5343 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5344 PCI_ANY_ID, PCI_ANY_ID,
5345 0, 0, pbn_b0_bt_2_115200 },
5346
8b5c913f
WY		 5347 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH352_2S,
5348 PCI_ANY_ID, PCI_ANY_ID,
5349 0, 0, pbn_b0_bt_2_115200 },
5350
14faa8cc
MS		 5351 /*
5352 * Commtech, Inc. Fastcom adapters
5353 */
5354 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5355 PCI_ANY_ID, PCI_ANY_ID,
5356 0,
5357 0, pbn_b0_2_1152000_200 },
5358 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5359 PCI_ANY_ID, PCI_ANY_ID,
5360 0,
5361 0, pbn_b0_4_1152000_200 },
5362 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5363 PCI_ANY_ID, PCI_ANY_ID,
5364 0,
5365 0, pbn_b0_4_1152000_200 },
5366 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5367 PCI_ANY_ID, PCI_ANY_ID,
5368 0,
5369 0, pbn_b0_8_1152000_200 },
5370 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5371 PCI_ANY_ID, PCI_ANY_ID,
5372 0,
5373 0, pbn_exar_XR17V352 },
5374 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5375 PCI_ANY_ID, PCI_ANY_ID,
5376 0,
5377 0, pbn_exar_XR17V354 },
5378 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5379 PCI_ANY_ID, PCI_ANY_ID,
5380 0,
5381 0, pbn_exar_XR17V358 },
5382
2c62a3c8
GKH		 5383 /* Fintek PCI serial cards */
5384 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5385 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5386 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5387
1da177e4
LT		 5388 /*
5389 * These entries match devices with class COMMUNICATION_SERIAL,
5390 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5391 */
5392 { PCI_ANY_ID, PCI_ANY_ID,
5393 PCI_ANY_ID, PCI_ANY_ID,
5394 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5395 0xffff00, pbn_default },
5396 { PCI_ANY_ID, PCI_ANY_ID,
5397 PCI_ANY_ID, PCI_ANY_ID,
5398 PCI_CLASS_COMMUNICATION_MODEM << 8,
5399 0xffff00, pbn_default },
5400 { PCI_ANY_ID, PCI_ANY_ID,
5401 PCI_ANY_ID, PCI_ANY_ID,
5402 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5403 0xffff00, pbn_default },
5404 { 0, }
5405};
5406
2807190b
MR		 5407static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5408 pci_channel_state_t state)
5409{
5410 struct serial_private *priv = pci_get_drvdata(dev);
5411
5412 if (state == pci_channel_io_perm_failure)
5413 return PCI_ERS_RESULT_DISCONNECT;
5414
5415 if (priv)
5416 pciserial_suspend_ports(priv);
5417
5418 pci_disable_device(dev);
5419
5420 return PCI_ERS_RESULT_NEED_RESET;
5421}
5422
5423static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5424{
5425 int rc;
5426
5427 rc = pci_enable_device(dev);
5428
5429 if (rc)
5430 return PCI_ERS_RESULT_DISCONNECT;
5431
5432 pci_restore_state(dev);
5433 pci_save_state(dev);
5434
5435 return PCI_ERS_RESULT_RECOVERED;
5436}
5437
5438static void serial8250_io_resume(struct pci_dev *dev)
5439{
5440 struct serial_private *priv = pci_get_drvdata(dev);
5441
5442 if (priv)
5443 pciserial_resume_ports(priv);
5444}
5445
1d352035 5446static const struct pci_error_handlers serial8250_err_handler = {
2807190b
MR		 5447 .error_detected = serial8250_io_error_detected,
5448 .slot_reset = serial8250_io_slot_reset,
5449 .resume = serial8250_io_resume,
5450};
5451
1da177e4
LT		 5452static struct pci_driver serial_pci_driver = {
5453 .name = "serial",
5454 .probe = pciserial_init_one,
2d47b716 5455 .remove = pciserial_remove_one,
1d5e7996 5456#ifdef CONFIG_PM
1da177e4
LT		 5457 .suspend = pciserial_suspend_one,
5458 .resume = pciserial_resume_one,
1d5e7996 5459#endif
1da177e4 5460 .id_table = serial_pci_tbl,
2807190b 5461 .err_handler = &serial8250_err_handler,
1da177e4
LT		 5462};
5463
15a12e83 5464module_pci_driver(serial_pci_driver);
1da177e4
LT		 5465
5466MODULE_LICENSE("GPL");
5467MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5468MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux kernel - Deliverables
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