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8250_pci Add EEH support to the 8250 driver for IBM/Digi PCIe 2-port Adapter
[deliverable/linux.git] / drivers / tty / serial / 8250.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
1da177e4
LT		 13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
1da177e4
LT		 18
19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
1da177e4 29#include <linux/delay.h>
d052d1be 30#include <linux/platform_device.h>
1da177e4 31#include <linux/tty.h>
cd3ecad1 32#include <linux/ratelimit.h>
1da177e4
LT		 33#include <linux/tty_flip.h>
34#include <linux/serial_reg.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
78512ece 38#include <linux/nmi.h>
f392ecfa 39#include <linux/mutex.h>
5a0e3ad6 40#include <linux/slab.h>
1da177e4
LT		 41
42#include <asm/io.h>
43#include <asm/irq.h>
44
45#include "8250.h"
46
b70ac771
DM		 47#ifdef CONFIG_SPARC
48#include "suncore.h"
49#endif
50
1da177e4
LT		 51/*
52 * Configuration:
40663cc7 53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 54 * is unsafe when used on edge-triggered interrupts.
55 */
408b664a 56static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 57
a61c2d78
DJ		 58static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
8440838b
DM		 60static struct uart_driver serial8250_reg;
61
62static int serial_index(struct uart_port *port)
63{
64 return (serial8250_reg.minor - 64) + port->line;
65}
66
d41a4b51
CE		 67static unsigned int skip_txen_test; /* force skip of txen test at init time */
68
1da177e4
LT		 69/*
70 * Debugging.
71 */
72#if 0
73#define DEBUG_AUTOCONF(fmt...) printk(fmt)
74#else
75#define DEBUG_AUTOCONF(fmt...) do { } while (0)
76#endif
77
78#if 0
79#define DEBUG_INTR(fmt...) printk(fmt)
80#else
81#define DEBUG_INTR(fmt...) do { } while (0)
82#endif
83
84#define PASS_LIMIT 256
85
bca47613
DH		 86#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
87
88
1da177e4
LT		 89/*
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
93 */
94#define is_real_interrupt(irq) ((irq) != 0)
95
1da177e4
LT		 96#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97#define CONFIG_SERIAL_DETECT_IRQ 1
98#endif
1da177e4
LT		 99#ifdef CONFIG_SERIAL_8250_MANY_PORTS
100#define CONFIG_SERIAL_MANY_PORTS 1
101#endif
102
103/*
104 * HUB6 is always on. This will be removed once the header
105 * files have been cleaned.
106 */
107#define CONFIG_HUB6 1
108
a4ed1e41 109#include <asm/serial.h>
1da177e4
LT		 110/*
111 * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 * standard enumeration mechanism. Platforms that can find all
113 * serial ports via mechanisms like ACPI or PCI need not supply it.
114 */
115#ifndef SERIAL_PORT_DFNS
116#define SERIAL_PORT_DFNS
117#endif
118
cb3592be 119static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 120 SERIAL_PORT_DFNS /* defined in asm/serial.h */
121};
122
026d02a2 123#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 124
125#ifdef CONFIG_SERIAL_8250_RSA
126
127#define PORT_RSA_MAX 4
128static unsigned long probe_rsa[PORT_RSA_MAX];
129static unsigned int probe_rsa_count;
130#endif /* CONFIG_SERIAL_8250_RSA */
131
132struct uart_8250_port {
133 struct uart_port port;
134 struct timer_list timer; /* "no irq" timer */
135 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 136 unsigned short capabilities; /* port capabilities */
137 unsigned short bugs; /* port bugs */
1da177e4 138 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 139 unsigned char acr;
140 unsigned char ier;
141 unsigned char lcr;
142 unsigned char mcr;
143 unsigned char mcr_mask; /* mask of user bits */
144 unsigned char mcr_force; /* mask of forced bits */
b8e7e40a 145 unsigned char cur_iotype; /* Running I/O type */
ad4c2aa6
CM		 146
147 /*
148 * Some bits in registers are cleared on a read, so they must
149 * be saved whenever the register is read but the bits will not
150 * be immediately processed.
151 */
152#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
153 unsigned char lsr_saved_flags;
154#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
155 unsigned char msr_saved_flags;
1da177e4
LT		 156};
157
158struct irq_info {
25db8ad5
AC		 159 struct hlist_node node;
160 int irq;
161 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 162 struct list_head *head;
163};
164
25db8ad5
AC		 165#define NR_IRQ_HASH 32 /* Can be adjusted later */
166static struct hlist_head irq_lists[NR_IRQ_HASH];
167static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 168
169/*
170 * Here we define the default xmit fifo size used for each type of UART.
171 */
172static const struct serial8250_config uart_config[] = {
173 [PORT_UNKNOWN] = {
174 .name = "unknown",
175 .fifo_size = 1,
176 .tx_loadsz = 1,
177 },
178 [PORT_8250] = {
179 .name = "8250",
180 .fifo_size = 1,
181 .tx_loadsz = 1,
182 },
183 [PORT_16450] = {
184 .name = "16450",
185 .fifo_size = 1,
186 .tx_loadsz = 1,
187 },
188 [PORT_16550] = {
189 .name = "16550",
190 .fifo_size = 1,
191 .tx_loadsz = 1,
192 },
193 [PORT_16550A] = {
194 .name = "16550A",
195 .fifo_size = 16,
196 .tx_loadsz = 16,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
198 .flags = UART_CAP_FIFO,
199 },
200 [PORT_CIRRUS] = {
201 .name = "Cirrus",
202 .fifo_size = 1,
203 .tx_loadsz = 1,
204 },
205 [PORT_16650] = {
206 .name = "ST16650",
207 .fifo_size = 1,
208 .tx_loadsz = 1,
209 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
210 },
211 [PORT_16650V2] = {
212 .name = "ST16650V2",
213 .fifo_size = 32,
214 .tx_loadsz = 16,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
216 UART_FCR_T_TRIG_00,
217 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
218 },
219 [PORT_16750] = {
220 .name = "TI16750",
221 .fifo_size = 64,
222 .tx_loadsz = 64,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
224 UART_FCR7_64BYTE,
225 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
226 },
227 [PORT_STARTECH] = {
228 .name = "Startech",
229 .fifo_size = 1,
230 .tx_loadsz = 1,
231 },
232 [PORT_16C950] = {
233 .name = "16C950/954",
234 .fifo_size = 128,
235 .tx_loadsz = 128,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
d0694e2a
PM		 237 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
238 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
1da177e4
LT		 239 },
240 [PORT_16654] = {
241 .name = "ST16654",
242 .fifo_size = 64,
243 .tx_loadsz = 32,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
245 UART_FCR_T_TRIG_10,
246 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
247 },
248 [PORT_16850] = {
249 .name = "XR16850",
250 .fifo_size = 128,
251 .tx_loadsz = 128,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
254 },
255 [PORT_RSA] = {
256 .name = "RSA",
257 .fifo_size = 2048,
258 .tx_loadsz = 2048,
259 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
260 .flags = UART_CAP_FIFO,
261 },
262 [PORT_NS16550A] = {
263 .name = "NS16550A",
264 .fifo_size = 16,
265 .tx_loadsz = 16,
266 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
267 .flags = UART_CAP_FIFO | UART_NATSEMI,
268 },
269 [PORT_XSCALE] = {
270 .name = "XScale",
271 .fifo_size = 32,
272 .tx_loadsz = 32,
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
4539c24f 274 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
1da177e4 275 },
bd71c182
TK		 276 [PORT_RM9000] = {
277 .name = "RM9000",
278 .fifo_size = 16,
279 .tx_loadsz = 16,
280 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 281 .flags = UART_CAP_FIFO,
282 },
283 [PORT_OCTEON] = {
284 .name = "OCTEON",
285 .fifo_size = 64,
286 .tx_loadsz = 64,
287 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 288 .flags = UART_CAP_FIFO,
289 },
08e0992f
FF		 290 [PORT_AR7] = {
291 .name = "AR7",
292 .fifo_size = 16,
293 .tx_loadsz = 16,
294 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
295 .flags = UART_CAP_FIFO | UART_CAP_AFE,
296 },
235dae5d
PL		 297 [PORT_U6_16550A] = {
298 .name = "U6_16550A",
299 .fifo_size = 64,
300 .tx_loadsz = 64,
301 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
302 .flags = UART_CAP_FIFO | UART_CAP_AFE,
303 },
4539c24f
SW		 304 [PORT_TEGRA] = {
305 .name = "Tegra",
306 .fifo_size = 32,
307 .tx_loadsz = 8,
308 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
309 UART_FCR_T_TRIG_01,
310 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
311 },
1da177e4
LT		 312};
313
12bf3f24 314#if defined(CONFIG_MIPS_ALCHEMY)
21c614a7
PA		 315
316/* Au1x00 UART hardware has a weird register layout */
317static const u8 au_io_in_map[] = {
318 [UART_RX] = 0,
319 [UART_IER] = 2,
320 [UART_IIR] = 3,
321 [UART_LCR] = 5,
322 [UART_MCR] = 6,
323 [UART_LSR] = 7,
324 [UART_MSR] = 8,
325};
326
327static const u8 au_io_out_map[] = {
328 [UART_TX] = 1,
329 [UART_IER] = 2,
330 [UART_FCR] = 4,
331 [UART_LCR] = 5,
332 [UART_MCR] = 6,
333};
334
335/* sane hardware needs no mapping */
7d6a07d1 336static inline int map_8250_in_reg(struct uart_port *p, int offset)
21c614a7 337{
7d6a07d1 338 if (p->iotype != UPIO_AU)
21c614a7
PA		 339 return offset;
340 return au_io_in_map[offset];
341}
342
7d6a07d1 343static inline int map_8250_out_reg(struct uart_port *p, int offset)
21c614a7 344{
7d6a07d1 345 if (p->iotype != UPIO_AU)
21c614a7
PA		 346 return offset;
347 return au_io_out_map[offset];
348}
349
6f803cd0 350#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 351
352static const u8
353 regmap_in[8] = {
354 [UART_RX] = 0x00,
355 [UART_IER] = 0x0c,
356 [UART_IIR] = 0x14,
357 [UART_LCR] = 0x1c,
358 [UART_MCR] = 0x20,
359 [UART_LSR] = 0x24,
360 [UART_MSR] = 0x28,
361 [UART_SCR] = 0x2c
362 },
363 regmap_out[8] = {
364 [UART_TX] = 0x04,
365 [UART_IER] = 0x0c,
366 [UART_FCR] = 0x18,
367 [UART_LCR] = 0x1c,
368 [UART_MCR] = 0x20,
369 [UART_LSR] = 0x24,
370 [UART_MSR] = 0x28,
371 [UART_SCR] = 0x2c
372 };
373
7d6a07d1 374static inline int map_8250_in_reg(struct uart_port *p, int offset)
bd71c182 375{
7d6a07d1 376 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 377 return offset;
378 return regmap_in[offset];
379}
380
7d6a07d1 381static inline int map_8250_out_reg(struct uart_port *p, int offset)
bd71c182 382{
7d6a07d1 383 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 384 return offset;
385 return regmap_out[offset];
386}
387
21c614a7
PA		 388#else
389
390/* sane hardware needs no mapping */
391#define map_8250_in_reg(up, offset) (offset)
392#define map_8250_out_reg(up, offset) (offset)
393
394#endif
395
7d6a07d1 396static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 397{
7d6a07d1
DD		 398 offset = map_8250_in_reg(p, offset) << p->regshift;
399 outb(p->hub6 - 1 + offset, p->iobase);
400 return inb(p->iobase + 1);
401}
1da177e4 402
7d6a07d1
DD		 403static void hub6_serial_out(struct uart_port *p, int offset, int value)
404{
405 offset = map_8250_out_reg(p, offset) << p->regshift;
406 outb(p->hub6 - 1 + offset, p->iobase);
407 outb(value, p->iobase + 1);
408}
1da177e4 409
7d6a07d1
DD		 410static unsigned int mem_serial_in(struct uart_port *p, int offset)
411{
412 offset = map_8250_in_reg(p, offset) << p->regshift;
413 return readb(p->membase + offset);
414}
1da177e4 415
7d6a07d1
DD		 416static void mem_serial_out(struct uart_port *p, int offset, int value)
417{
418 offset = map_8250_out_reg(p, offset) << p->regshift;
419 writeb(value, p->membase + offset);
420}
421
422static void mem32_serial_out(struct uart_port *p, int offset, int value)
423{
424 offset = map_8250_out_reg(p, offset) << p->regshift;
425 writel(value, p->membase + offset);
426}
427
428static unsigned int mem32_serial_in(struct uart_port *p, int offset)
429{
430 offset = map_8250_in_reg(p, offset) << p->regshift;
431 return readl(p->membase + offset);
432}
1da177e4 433
7d6a07d1
DD		 434static unsigned int au_serial_in(struct uart_port *p, int offset)
435{
436 offset = map_8250_in_reg(p, offset) << p->regshift;
437 return __raw_readl(p->membase + offset);
438}
439
440static void au_serial_out(struct uart_port *p, int offset, int value)
441{
442 offset = map_8250_out_reg(p, offset) << p->regshift;
443 __raw_writel(value, p->membase + offset);
444}
21c614a7 445
7d6a07d1
DD		 446static unsigned int tsi_serial_in(struct uart_port *p, int offset)
447{
448 unsigned int tmp;
449 offset = map_8250_in_reg(p, offset) << p->regshift;
450 if (offset == UART_IIR) {
451 tmp = readl(p->membase + (UART_IIR & ~3));
452 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
453 } else
454 return readb(p->membase + offset);
455}
3be91ec7 456
7d6a07d1
DD		 457static void tsi_serial_out(struct uart_port *p, int offset, int value)
458{
459 offset = map_8250_out_reg(p, offset) << p->regshift;
460 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
461 writeb(value, p->membase + offset);
1da177e4
LT		 462}
463
a3ae0fc3
JI		 464/* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */
465static inline void dwapb_save_out_value(struct uart_port *p, int offset,
466 int value)
467{
468 struct uart_8250_port *up =
469 container_of(p, struct uart_8250_port, port);
470
471 if (offset == UART_LCR)
472 up->lcr = value;
473}
474
475/* Read the IER to ensure any interrupt is cleared before returning from ISR. */
476static inline void dwapb_check_clear_ier(struct uart_port *p, int offset)
477{
478 if (offset == UART_TX || offset == UART_IER)
479 p->serial_in(p, UART_IER);
480}
481
7d6a07d1 482static void dwapb_serial_out(struct uart_port *p, int offset, int value)
1da177e4 483{
beab697a 484 int save_offset = offset;
7d6a07d1 485 offset = map_8250_out_reg(p, offset) << p->regshift;
a3ae0fc3 486 dwapb_save_out_value(p, save_offset, value);
7d6a07d1 487 writeb(value, p->membase + offset);
a3ae0fc3
JI		 488 dwapb_check_clear_ier(p, save_offset);
489}
490
491static void dwapb32_serial_out(struct uart_port *p, int offset, int value)
492{
493 int save_offset = offset;
494 offset = map_8250_out_reg(p, offset) << p->regshift;
495 dwapb_save_out_value(p, save_offset, value);
496 writel(value, p->membase + offset);
497 dwapb_check_clear_ier(p, save_offset);
7d6a07d1 498}
1da177e4 499
7d6a07d1
DD		 500static unsigned int io_serial_in(struct uart_port *p, int offset)
501{
502 offset = map_8250_in_reg(p, offset) << p->regshift;
503 return inb(p->iobase + offset);
504}
505
506static void io_serial_out(struct uart_port *p, int offset, int value)
507{
508 offset = map_8250_out_reg(p, offset) << p->regshift;
509 outb(value, p->iobase + offset);
510}
511
512static void set_io_from_upio(struct uart_port *p)
513{
49d5741b
JI		 514 struct uart_8250_port *up =
515 container_of(p, struct uart_8250_port, port);
7d6a07d1 516 switch (p->iotype) {
1da177e4 517 case UPIO_HUB6:
7d6a07d1
DD		 518 p->serial_in = hub6_serial_in;
519 p->serial_out = hub6_serial_out;
1da177e4
LT		 520 break;
521
522 case UPIO_MEM:
7d6a07d1
DD		 523 p->serial_in = mem_serial_in;
524 p->serial_out = mem_serial_out;
1da177e4
LT		 525 break;
526
bd71c182 527 case UPIO_RM9000:
1da177e4 528 case UPIO_MEM32:
7d6a07d1
DD		 529 p->serial_in = mem32_serial_in;
530 p->serial_out = mem32_serial_out;
1da177e4
LT		 531 break;
532
21c614a7 533 case UPIO_AU:
7d6a07d1
DD		 534 p->serial_in = au_serial_in;
535 p->serial_out = au_serial_out;
21c614a7 536 break;
12bf3f24 537
3be91ec7 538 case UPIO_TSI:
7d6a07d1
DD		 539 p->serial_in = tsi_serial_in;
540 p->serial_out = tsi_serial_out;
3be91ec7 541 break;
21c614a7 542
beab697a 543 case UPIO_DWAPB:
7d6a07d1
DD		 544 p->serial_in = mem_serial_in;
545 p->serial_out = dwapb_serial_out;
beab697a
MSJ		 546 break;
547
a3ae0fc3
JI		 548 case UPIO_DWAPB32:
549 p->serial_in = mem32_serial_in;
550 p->serial_out = dwapb32_serial_out;
551 break;
552
1da177e4 553 default:
7d6a07d1
DD		 554 p->serial_in = io_serial_in;
555 p->serial_out = io_serial_out;
556 break;
1da177e4 557 }
b8e7e40a
AC		 558 /* Remember loaded iotype */
559 up->cur_iotype = p->iotype;
1da177e4
LT		 560}
561
40b36daa
AW		 562static void
563serial_out_sync(struct uart_8250_port *up, int offset, int value)
564{
7d6a07d1
DD		 565 struct uart_port *p = &up->port;
566 switch (p->iotype) {
40b36daa
AW		 567 case UPIO_MEM:
568 case UPIO_MEM32:
40b36daa 569 case UPIO_AU:
beab697a 570 case UPIO_DWAPB:
a3ae0fc3 571 case UPIO_DWAPB32:
7d6a07d1
DD		 572 p->serial_out(p, offset, value);
573 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 574 break;
575 default:
7d6a07d1 576 p->serial_out(p, offset, value);
40b36daa
AW		 577 }
578}
579
7d6a07d1
DD		 580#define serial_in(up, offset) \
581 (up->port.serial_in(&(up)->port, (offset)))
582#define serial_out(up, offset, value) \
583 (up->port.serial_out(&(up)->port, (offset), (value)))
1da177e4
LT		 584/*
585 * We used to support using pause I/O for certain machines. We
586 * haven't supported this for a while, but just in case it's badly
587 * needed for certain old 386 machines, I've left these #define's
588 * in....
589 */
590#define serial_inp(up, offset) serial_in(up, offset)
591#define serial_outp(up, offset, value) serial_out(up, offset, value)
592
b32b19b8
JAH		 593/* Uart divisor latch read */
594static inline int _serial_dl_read(struct uart_8250_port *up)
595{
596 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
597}
598
599/* Uart divisor latch write */
600static inline void _serial_dl_write(struct uart_8250_port *up, int value)
601{
602 serial_outp(up, UART_DLL, value & 0xff);
603 serial_outp(up, UART_DLM, value >> 8 & 0xff);
604}
605
12bf3f24 606#if defined(CONFIG_MIPS_ALCHEMY)
b32b19b8
JAH		 607/* Au1x00 haven't got a standard divisor latch */
608static int serial_dl_read(struct uart_8250_port *up)
609{
610 if (up->port.iotype == UPIO_AU)
611 return __raw_readl(up->port.membase + 0x28);
612 else
613 return _serial_dl_read(up);
614}
615
616static void serial_dl_write(struct uart_8250_port *up, int value)
617{
618 if (up->port.iotype == UPIO_AU)
619 __raw_writel(value, up->port.membase + 0x28);
620 else
621 _serial_dl_write(up, value);
622}
6f803cd0 623#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 624static int serial_dl_read(struct uart_8250_port *up)
625{
626 return (up->port.iotype == UPIO_RM9000) ?
627 (((__raw_readl(up->port.membase + 0x10) << 8) |
628 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
629 _serial_dl_read(up);
630}
631
632static void serial_dl_write(struct uart_8250_port *up, int value)
633{
634 if (up->port.iotype == UPIO_RM9000) {
635 __raw_writel(value, up->port.membase + 0x08);
636 __raw_writel(value >> 8, up->port.membase + 0x10);
637 } else {
638 _serial_dl_write(up, value);
639 }
640}
b32b19b8
JAH		 641#else
642#define serial_dl_read(up) _serial_dl_read(up)
643#define serial_dl_write(up, value) _serial_dl_write(up, value)
644#endif
1da177e4
LT		 645
646/*
647 * For the 16C950
648 */
649static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
650{
651 serial_out(up, UART_SCR, offset);
652 serial_out(up, UART_ICR, value);
653}
654
655static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
656{
657 unsigned int value;
658
659 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
660 serial_out(up, UART_SCR, offset);
661 value = serial_in(up, UART_ICR);
662 serial_icr_write(up, UART_ACR, up->acr);
663
664 return value;
665}
666
667/*
668 * FIFO support.
669 */
b5d674ab 670static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 671{
672 if (p->capabilities & UART_CAP_FIFO) {
673 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
674 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
675 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
676 serial_outp(p, UART_FCR, 0);
677 }
678}
679
680/*
681 * IER sleep support. UARTs which have EFRs need the "extended
682 * capability" bit enabled. Note that on XR16C850s, we need to
683 * reset LCR to write to IER.
684 */
b5d674ab 685static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4
LT		 686{
687 if (p->capabilities & UART_CAP_SLEEP) {
688 if (p->capabilities & UART_CAP_EFR) {
662b083a 689 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 690 serial_outp(p, UART_EFR, UART_EFR_ECB);
691 serial_outp(p, UART_LCR, 0);
692 }
693 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
694 if (p->capabilities & UART_CAP_EFR) {
662b083a 695 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 696 serial_outp(p, UART_EFR, 0);
697 serial_outp(p, UART_LCR, 0);
698 }
699 }
700}
701
702#ifdef CONFIG_SERIAL_8250_RSA
703/*
704 * Attempts to turn on the RSA FIFO. Returns zero on failure.
705 * We set the port uart clock rate if we succeed.
706 */
707static int __enable_rsa(struct uart_8250_port *up)
708{
709 unsigned char mode;
710 int result;
711
712 mode = serial_inp(up, UART_RSA_MSR);
713 result = mode & UART_RSA_MSR_FIFO;
714
715 if (!result) {
716 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
717 mode = serial_inp(up, UART_RSA_MSR);
718 result = mode & UART_RSA_MSR_FIFO;
719 }
720
721 if (result)
722 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
723
724 return result;
725}
726
727static void enable_rsa(struct uart_8250_port *up)
728{
729 if (up->port.type == PORT_RSA) {
730 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
731 spin_lock_irq(&up->port.lock);
732 __enable_rsa(up);
733 spin_unlock_irq(&up->port.lock);
734 }
735 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
736 serial_outp(up, UART_RSA_FRR, 0);
737 }
738}
739
740/*
741 * Attempts to turn off the RSA FIFO. Returns zero on failure.
742 * It is unknown why interrupts were disabled in here. However,
743 * the caller is expected to preserve this behaviour by grabbing
744 * the spinlock before calling this function.
745 */
746static void disable_rsa(struct uart_8250_port *up)
747{
748 unsigned char mode;
749 int result;
750
751 if (up->port.type == PORT_RSA &&
752 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
753 spin_lock_irq(&up->port.lock);
754
755 mode = serial_inp(up, UART_RSA_MSR);
756 result = !(mode & UART_RSA_MSR_FIFO);
757
758 if (!result) {
759 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
760 mode = serial_inp(up, UART_RSA_MSR);
761 result = !(mode & UART_RSA_MSR_FIFO);
762 }
763
764 if (result)
765 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
766 spin_unlock_irq(&up->port.lock);
767 }
768}
769#endif /* CONFIG_SERIAL_8250_RSA */
770
771/*
772 * This is a quickie test to see how big the FIFO is.
773 * It doesn't work at all the time, more's the pity.
774 */
775static int size_fifo(struct uart_8250_port *up)
776{
b32b19b8
JAH		 777 unsigned char old_fcr, old_mcr, old_lcr;
778 unsigned short old_dl;
1da177e4
LT		 779 int count;
780
781 old_lcr = serial_inp(up, UART_LCR);
782 serial_outp(up, UART_LCR, 0);
783 old_fcr = serial_inp(up, UART_FCR);
784 old_mcr = serial_inp(up, UART_MCR);
785 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
786 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
787 serial_outp(up, UART_MCR, UART_MCR_LOOP);
662b083a 788 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8
JAH		 789 old_dl = serial_dl_read(up);
790 serial_dl_write(up, 0x0001);
1da177e4
LT		 791 serial_outp(up, UART_LCR, 0x03);
792 for (count = 0; count < 256; count++)
793 serial_outp(up, UART_TX, count);
794 mdelay(20);/* FIXME - schedule_timeout */
795 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
796 (count < 256); count++)
797 serial_inp(up, UART_RX);
798 serial_outp(up, UART_FCR, old_fcr);
799 serial_outp(up, UART_MCR, old_mcr);
662b083a 800 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8 801 serial_dl_write(up, old_dl);
1da177e4
LT		 802 serial_outp(up, UART_LCR, old_lcr);
803
804 return count;
805}
806
807/*
808 * Read UART ID using the divisor method - set DLL and DLM to zero
809 * and the revision will be in DLL and device type in DLM. We
810 * preserve the device state across this.
811 */
812static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
813{
814 unsigned char old_dll, old_dlm, old_lcr;
815 unsigned int id;
816
817 old_lcr = serial_inp(p, UART_LCR);
662b083a 818 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 819
820 old_dll = serial_inp(p, UART_DLL);
821 old_dlm = serial_inp(p, UART_DLM);
822
823 serial_outp(p, UART_DLL, 0);
824 serial_outp(p, UART_DLM, 0);
825
826 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
827
828 serial_outp(p, UART_DLL, old_dll);
829 serial_outp(p, UART_DLM, old_dlm);
830 serial_outp(p, UART_LCR, old_lcr);
831
832 return id;
833}
834
835/*
836 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
837 * When this function is called we know it is at least a StarTech
838 * 16650 V2, but it might be one of several StarTech UARTs, or one of
839 * its clones. (We treat the broken original StarTech 16650 V1 as a
840 * 16550, and why not? Startech doesn't seem to even acknowledge its
841 * existence.)
bd71c182 842 *
1da177e4
LT		 843 * What evil have men's minds wrought...
844 */
845static void autoconfig_has_efr(struct uart_8250_port *up)
846{
847 unsigned int id1, id2, id3, rev;
848
849 /*
850 * Everything with an EFR has SLEEP
851 */
852 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
853
854 /*
855 * First we check to see if it's an Oxford Semiconductor UART.
856 *
857 * If we have to do this here because some non-National
858 * Semiconductor clone chips lock up if you try writing to the
859 * LSR register (which serial_icr_read does)
860 */
861
862 /*
863 * Check for Oxford Semiconductor 16C950.
864 *
865 * EFR [4] must be set else this test fails.
866 *
867 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
868 * claims that it's needed for 952 dual UART's (which are not
869 * recommended for new designs).
870 */
871 up->acr = 0;
662b083a 872 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 873 serial_out(up, UART_EFR, UART_EFR_ECB);
874 serial_out(up, UART_LCR, 0x00);
875 id1 = serial_icr_read(up, UART_ID1);
876 id2 = serial_icr_read(up, UART_ID2);
877 id3 = serial_icr_read(up, UART_ID3);
878 rev = serial_icr_read(up, UART_REV);
879
880 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
881
882 if (id1 == 0x16 && id2 == 0xC9 &&
883 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
884 up->port.type = PORT_16C950;
4ba5e35d
RK		 885
886 /*
887 * Enable work around for the Oxford Semiconductor 952 rev B
888 * chip which causes it to seriously miscalculate baud rates
889 * when DLL is 0.
890 */
891 if (id3 == 0x52 && rev == 0x01)
892 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 893 return;
894 }
bd71c182 895
1da177e4
LT		 896 /*
897 * We check for a XR16C850 by setting DLL and DLM to 0, and then
898 * reading back DLL and DLM. The chip type depends on the DLM
899 * value read back:
900 * 0x10 - XR16C850 and the DLL contains the chip revision.
901 * 0x12 - XR16C2850.
902 * 0x14 - XR16C854.
903 */
904 id1 = autoconfig_read_divisor_id(up);
905 DEBUG_AUTOCONF("850id=%04x ", id1);
906
907 id2 = id1 >> 8;
908 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 909 up->port.type = PORT_16850;
910 return;
911 }
912
913 /*
914 * It wasn't an XR16C850.
915 *
916 * We distinguish between the '654 and the '650 by counting
917 * how many bytes are in the FIFO. I'm using this for now,
918 * since that's the technique that was sent to me in the
919 * serial driver update, but I'm not convinced this works.
920 * I've had problems doing this in the past. -TYT
921 */
922 if (size_fifo(up) == 64)
923 up->port.type = PORT_16654;
924 else
925 up->port.type = PORT_16650V2;
926}
927
928/*
929 * We detected a chip without a FIFO. Only two fall into
930 * this category - the original 8250 and the 16450. The
931 * 16450 has a scratch register (accessible with LCR=0)
932 */
933static void autoconfig_8250(struct uart_8250_port *up)
934{
935 unsigned char scratch, status1, status2;
936
937 up->port.type = PORT_8250;
938
939 scratch = serial_in(up, UART_SCR);
940 serial_outp(up, UART_SCR, 0xa5);
941 status1 = serial_in(up, UART_SCR);
942 serial_outp(up, UART_SCR, 0x5a);
943 status2 = serial_in(up, UART_SCR);
944 serial_outp(up, UART_SCR, scratch);
945
946 if (status1 == 0xa5 && status2 == 0x5a)
947 up->port.type = PORT_16450;
948}
949
950static int broken_efr(struct uart_8250_port *up)
951{
952 /*
953 * Exar ST16C2550 "A2" devices incorrectly detect as
954 * having an EFR, and report an ID of 0x0201. See
631dd1a8 955 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1da177e4
LT		 956 */
957 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
958 return 1;
959
960 return 0;
961}
962
0d0389e5
YK		 963static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
964{
965 unsigned char status;
966
967 status = serial_in(up, 0x04); /* EXCR2 */
968#define PRESL(x) ((x) & 0x30)
969 if (PRESL(status) == 0x10) {
970 /* already in high speed mode */
971 return 0;
972 } else {
973 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
974 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
975 serial_outp(up, 0x04, status);
976 }
977 return 1;
978}
979
1da177e4
LT		 980/*
981 * We know that the chip has FIFOs. Does it have an EFR? The
982 * EFR is located in the same register position as the IIR and
983 * we know the top two bits of the IIR are currently set. The
984 * EFR should contain zero. Try to read the EFR.
985 */
986static void autoconfig_16550a(struct uart_8250_port *up)
987{
988 unsigned char status1, status2;
989 unsigned int iersave;
990
991 up->port.type = PORT_16550A;
992 up->capabilities |= UART_CAP_FIFO;
993
994 /*
995 * Check for presence of the EFR when DLAB is set.
996 * Only ST16C650V1 UARTs pass this test.
997 */
662b083a 998 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 999 if (serial_in(up, UART_EFR) == 0) {
1000 serial_outp(up, UART_EFR, 0xA8);
1001 if (serial_in(up, UART_EFR) != 0) {
1002 DEBUG_AUTOCONF("EFRv1 ");
1003 up->port.type = PORT_16650;
1004 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1005 } else {
1006 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1007 }
1008 serial_outp(up, UART_EFR, 0);
1009 return;
1010 }
1011
1012 /*
1013 * Maybe it requires 0xbf to be written to the LCR.
1014 * (other ST16C650V2 UARTs, TI16C752A, etc)
1015 */
662b083a 1016 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 1017 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1018 DEBUG_AUTOCONF("EFRv2 ");
1019 autoconfig_has_efr(up);
1020 return;
1021 }
1022
1023 /*
1024 * Check for a National Semiconductor SuperIO chip.
1025 * Attempt to switch to bank 2, read the value of the LOOP bit
1026 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1027 * switch back to bank 2, read it from EXCR1 again and check
1028 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 1029 */
1030 serial_outp(up, UART_LCR, 0);
1031 status1 = serial_in(up, UART_MCR);
1032 serial_outp(up, UART_LCR, 0xE0);
1033 status2 = serial_in(up, 0x02); /* EXCR1 */
1034
1035 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1036 serial_outp(up, UART_LCR, 0);
1037 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
1038 serial_outp(up, UART_LCR, 0xE0);
1039 status2 = serial_in(up, 0x02); /* EXCR1 */
1040 serial_outp(up, UART_LCR, 0);
1041 serial_outp(up, UART_MCR, status1);
1042
1043 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 1044 unsigned short quot;
1045
1da177e4 1046 serial_outp(up, UART_LCR, 0xE0);
857dde2e 1047
b32b19b8 1048 quot = serial_dl_read(up);
857dde2e
DW		 1049 quot <<= 3;
1050
0d0389e5
YK		 1051 if (ns16550a_goto_highspeed(up))
1052 serial_dl_write(up, quot);
857dde2e 1053
1da177e4 1054 serial_outp(up, UART_LCR, 0);
1da177e4 1055
857dde2e 1056 up->port.uartclk = 921600*16;
1da177e4
LT		 1057 up->port.type = PORT_NS16550A;
1058 up->capabilities |= UART_NATSEMI;
1059 return;
1060 }
1061 }
1062
1063 /*
1064 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1065 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1066 * Try setting it with and without DLAB set. Cheap clones
1067 * set bit 5 without DLAB set.
1068 */
1069 serial_outp(up, UART_LCR, 0);
1070 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1071 status1 = serial_in(up, UART_IIR) >> 5;
1072 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
662b083a 1073 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 1074 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1075 status2 = serial_in(up, UART_IIR) >> 5;
1076 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1077 serial_outp(up, UART_LCR, 0);
1078
1079 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1080
1081 if (status1 == 6 && status2 == 7) {
1082 up->port.type = PORT_16750;
1083 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1084 return;
1085 }
1086
1087 /*
1088 * Try writing and reading the UART_IER_UUE bit (b6).
1089 * If it works, this is probably one of the Xscale platform's
1090 * internal UARTs.
1091 * We're going to explicitly set the UUE bit to 0 before
1092 * trying to write and read a 1 just to make sure it's not
1093 * already a 1 and maybe locked there before we even start start.
1094 */
1095 iersave = serial_in(up, UART_IER);
1096 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1097 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1098 /*
1099 * OK it's in a known zero state, try writing and reading
1100 * without disturbing the current state of the other bits.
1101 */
1102 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1103 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1104 /*
1105 * It's an Xscale.
1106 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1107 */
1108 DEBUG_AUTOCONF("Xscale ");
1109 up->port.type = PORT_XSCALE;
1110 up->capabilities |= UART_CAP_UUE;
1111 return;
1112 }
1113 } else {
1114 /*
1115 * If we got here we couldn't force the IER_UUE bit to 0.
1116 * Log it and continue.
1117 */
1118 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1119 }
1120 serial_outp(up, UART_IER, iersave);
235dae5d
PL		 1121
1122 /*
1123 * We distinguish between 16550A and U6 16550A by counting
1124 * how many bytes are in the FIFO.
1125 */
1126 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1127 up->port.type = PORT_U6_16550A;
1128 up->capabilities |= UART_CAP_AFE;
1129 }
1da177e4
LT		 1130}
1131
1132/*
1133 * This routine is called by rs_init() to initialize a specific serial
1134 * port. It determines what type of UART chip this serial port is
1135 * using: 8250, 16450, 16550, 16550A. The important question is
1136 * whether or not this UART is a 16550A or not, since this will
1137 * determine whether or not we can use its FIFO features or not.
1138 */
1139static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1140{
1141 unsigned char status1, scratch, scratch2, scratch3;
1142 unsigned char save_lcr, save_mcr;
1143 unsigned long flags;
1144
1145 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1146 return;
1147
80647b95 1148 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
8440838b 1149 serial_index(&up->port), up->port.iobase, up->port.membase);
1da177e4
LT		 1150
1151 /*
1152 * We really do need global IRQs disabled here - we're going to
1153 * be frobbing the chips IRQ enable register to see if it exists.
1154 */
1155 spin_lock_irqsave(&up->port.lock, flags);
1da177e4
LT		 1156
1157 up->capabilities = 0;
4ba5e35d 1158 up->bugs = 0;
1da177e4
LT		 1159
1160 if (!(up->port.flags & UPF_BUGGY_UART)) {
1161 /*
1162 * Do a simple existence test first; if we fail this,
1163 * there's no point trying anything else.
bd71c182 1164 *
1da177e4
LT		 1165 * 0x80 is used as a nonsense port to prevent against
1166 * false positives due to ISA bus float. The
1167 * assumption is that 0x80 is a non-existent port;
1168 * which should be safe since include/asm/io.h also
1169 * makes this assumption.
1170 *
1171 * Note: this is safe as long as MCR bit 4 is clear
1172 * and the device is in "PC" mode.
1173 */
1174 scratch = serial_inp(up, UART_IER);
1175 serial_outp(up, UART_IER, 0);
1176#ifdef __i386__
1177 outb(0xff, 0x080);
1178#endif
48212008
TH		 1179 /*
1180 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1181 * 16C754B) allow only to modify them if an EFR bit is set.
1182 */
1183 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1184 serial_outp(up, UART_IER, 0x0F);
1185#ifdef __i386__
1186 outb(0, 0x080);
1187#endif
48212008 1188 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1189 serial_outp(up, UART_IER, scratch);
1190 if (scratch2 != 0 || scratch3 != 0x0F) {
1191 /*
1192 * We failed; there's nothing here
1193 */
1194 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1195 scratch2, scratch3);
1196 goto out;
1197 }
1198 }
1199
1200 save_mcr = serial_in(up, UART_MCR);
1201 save_lcr = serial_in(up, UART_LCR);
1202
bd71c182 1203 /*
1da177e4
LT		 1204 * Check to see if a UART is really there. Certain broken
1205 * internal modems based on the Rockwell chipset fail this
1206 * test, because they apparently don't implement the loopback
1207 * test mode. So this test is skipped on the COM 1 through
1208 * COM 4 ports. This *should* be safe, since no board
1209 * manufacturer would be stupid enough to design a board
1210 * that conflicts with COM 1-4 --- we hope!
1211 */
1212 if (!(up->port.flags & UPF_SKIP_TEST)) {
1213 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1214 status1 = serial_inp(up, UART_MSR) & 0xF0;
1215 serial_outp(up, UART_MCR, save_mcr);
1216 if (status1 != 0x90) {
1217 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1218 status1);
1219 goto out;
1220 }
1221 }
1222
1223 /*
1224 * We're pretty sure there's a port here. Lets find out what
1225 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1226 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1227 * determines what we test for next.
1228 *
1229 * We also initialise the EFR (if any) to zero for later. The
1230 * EFR occupies the same register location as the FCR and IIR.
1231 */
662b083a 1232 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 1233 serial_outp(up, UART_EFR, 0);
1234 serial_outp(up, UART_LCR, 0);
1235
1236 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1237 scratch = serial_in(up, UART_IIR) >> 6;
1238
1239 DEBUG_AUTOCONF("iir=%d ", scratch);
1240
1241 switch (scratch) {
1242 case 0:
1243 autoconfig_8250(up);
1244 break;
1245 case 1:
1246 up->port.type = PORT_UNKNOWN;
1247 break;
1248 case 2:
1249 up->port.type = PORT_16550;
1250 break;
1251 case 3:
1252 autoconfig_16550a(up);
1253 break;
1254 }
1255
1256#ifdef CONFIG_SERIAL_8250_RSA
1257 /*
1258 * Only probe for RSA ports if we got the region.
1259 */
1260 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1261 int i;
1262
1263 for (i = 0 ; i < probe_rsa_count; ++i) {
1264 if (probe_rsa[i] == up->port.iobase &&
1265 __enable_rsa(up)) {
1266 up->port.type = PORT_RSA;
1267 break;
1268 }
1269 }
1270 }
1271#endif
21c614a7 1272
1da177e4
LT		 1273 serial_outp(up, UART_LCR, save_lcr);
1274
1275 if (up->capabilities != uart_config[up->port.type].flags) {
1276 printk(KERN_WARNING
1277 "ttyS%d: detected caps %08x should be %08x\n",
8440838b
DM		 1278 serial_index(&up->port), up->capabilities,
1279 uart_config[up->port.type].flags);
1da177e4
LT		 1280 }
1281
1282 up->port.fifosize = uart_config[up->port.type].fifo_size;
1283 up->capabilities = uart_config[up->port.type].flags;
1284 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1285
1286 if (up->port.type == PORT_UNKNOWN)
1287 goto out;
1288
1289 /*
1290 * Reset the UART.
1291 */
1292#ifdef CONFIG_SERIAL_8250_RSA
1293 if (up->port.type == PORT_RSA)
1294 serial_outp(up, UART_RSA_FRR, 0);
1295#endif
1296 serial_outp(up, UART_MCR, save_mcr);
1297 serial8250_clear_fifos(up);
40b36daa 1298 serial_in(up, UART_RX);
5c8c755c
LB		 1299 if (up->capabilities & UART_CAP_UUE)
1300 serial_outp(up, UART_IER, UART_IER_UUE);
1301 else
1302 serial_outp(up, UART_IER, 0);
1da177e4 1303
bd71c182 1304 out:
1da177e4 1305 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1306 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1307}
1308
1309static void autoconfig_irq(struct uart_8250_port *up)
1310{
1311 unsigned char save_mcr, save_ier;
1312 unsigned char save_ICP = 0;
1313 unsigned int ICP = 0;
1314 unsigned long irqs;
1315 int irq;
1316
1317 if (up->port.flags & UPF_FOURPORT) {
1318 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1319 save_ICP = inb_p(ICP);
1320 outb_p(0x80, ICP);
1321 (void) inb_p(ICP);
1322 }
1323
1324 /* forget possible initially masked and pending IRQ */
1325 probe_irq_off(probe_irq_on());
1326 save_mcr = serial_inp(up, UART_MCR);
1327 save_ier = serial_inp(up, UART_IER);
1328 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1329
1da177e4
LT		 1330 irqs = probe_irq_on();
1331 serial_outp(up, UART_MCR, 0);
6f803cd0
AC		 1332 udelay(10);
1333 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 1334 serial_outp(up, UART_MCR,
1335 UART_MCR_DTR | UART_MCR_RTS);
1336 } else {
1337 serial_outp(up, UART_MCR,
1338 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1339 }
1340 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1341 (void)serial_inp(up, UART_LSR);
1342 (void)serial_inp(up, UART_RX);
1343 (void)serial_inp(up, UART_IIR);
1344 (void)serial_inp(up, UART_MSR);
1345 serial_outp(up, UART_TX, 0xFF);
6f803cd0 1346 udelay(20);
1da177e4
LT		 1347 irq = probe_irq_off(irqs);
1348
1349 serial_outp(up, UART_MCR, save_mcr);
1350 serial_outp(up, UART_IER, save_ier);
1351
1352 if (up->port.flags & UPF_FOURPORT)
1353 outb_p(save_ICP, ICP);
1354
1355 up->port.irq = (irq > 0) ? irq : 0;
1356}
1357
e763b90c
RK		 1358static inline void __stop_tx(struct uart_8250_port *p)
1359{
1360 if (p->ier & UART_IER_THRI) {
1361 p->ier &= ~UART_IER_THRI;
1362 serial_out(p, UART_IER, p->ier);
1363 }
1364}
1365
b129a8cc 1366static void serial8250_stop_tx(struct uart_port *port)
1da177e4 1367{
49d5741b
JI		 1368 struct uart_8250_port *up =
1369 container_of(port, struct uart_8250_port, port);
1da177e4 1370
e763b90c 1371 __stop_tx(up);
1da177e4
LT		 1372
1373 /*
e763b90c 1374 * We really want to stop the transmitter from sending.
1da177e4 1375 */
e763b90c 1376 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1377 up->acr |= UART_ACR_TXDIS;
1378 serial_icr_write(up, UART_ACR, up->acr);
1379 }
1380}
1381
55d3b282
RK		 1382static void transmit_chars(struct uart_8250_port *up);
1383
b129a8cc 1384static void serial8250_start_tx(struct uart_port *port)
1da177e4 1385{
49d5741b
JI		 1386 struct uart_8250_port *up =
1387 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1388
1389 if (!(up->ier & UART_IER_THRI)) {
1390 up->ier |= UART_IER_THRI;
1391 serial_out(up, UART_IER, up->ier);
55d3b282 1392
67f7654e 1393 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1394 unsigned char lsr;
55d3b282 1395 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1396 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
bd71c182 1397 if ((up->port.type == PORT_RM9000) ?
68cb4f8e
IJ		 1398 (lsr & UART_LSR_THRE) :
1399 (lsr & UART_LSR_TEMT))
55d3b282
RK		 1400 transmit_chars(up);
1401 }
1da177e4 1402 }
e763b90c 1403
1da177e4 1404 /*
e763b90c 1405 * Re-enable the transmitter if we disabled it.
1da177e4 1406 */
e763b90c 1407 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1408 up->acr &= ~UART_ACR_TXDIS;
1409 serial_icr_write(up, UART_ACR, up->acr);
1410 }
1411}
1412
1413static void serial8250_stop_rx(struct uart_port *port)
1414{
49d5741b
JI		 1415 struct uart_8250_port *up =
1416 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1417
1418 up->ier &= ~UART_IER_RLSI;
1419 up->port.read_status_mask &= ~UART_LSR_DR;
1420 serial_out(up, UART_IER, up->ier);
1421}
1422
1423static void serial8250_enable_ms(struct uart_port *port)
1424{
49d5741b
JI		 1425 struct uart_8250_port *up =
1426 container_of(port, struct uart_8250_port, port);
1da177e4 1427
21c614a7
PA		 1428 /* no MSR capabilities */
1429 if (up->bugs & UART_BUG_NOMSR)
1430 return;
1431
1da177e4
LT		 1432 up->ier |= UART_IER_MSI;
1433 serial_out(up, UART_IER, up->ier);
1434}
1435
5f873bae
SW		 1436/*
1437 * Clear the Tegra rx fifo after a break
1438 *
1439 * FIXME: This needs to become a port specific callback once we have a
1440 * framework for this
1441 */
1442static void clear_rx_fifo(struct uart_8250_port *up)
1443{
1444 unsigned int status, tmout = 10000;
1445 do {
1446 status = serial_in(up, UART_LSR);
1447 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1448 status = serial_in(up, UART_RX);
1449 else
1450 break;
1451 if (--tmout == 0)
1452 break;
1453 udelay(1);
1454 } while (1);
1455}
1456
ea8874dc 1457static void
cc79aa9d 1458receive_chars(struct uart_8250_port *up, unsigned int *status)
1da177e4 1459{
ebd2c8f6 1460 struct tty_struct *tty = up->port.state->port.tty;
1da177e4
LT		 1461 unsigned char ch, lsr = *status;
1462 int max_count = 256;
1463 char flag;
1464
1465 do {
7500b1f6
AR		 1466 if (likely(lsr & UART_LSR_DR))
1467 ch = serial_inp(up, UART_RX);
1468 else
1469 /*
1470 * Intel 82571 has a Serial Over Lan device that will
1471 * set UART_LSR_BI without setting UART_LSR_DR when
1472 * it receives a break. To avoid reading from the
1473 * receive buffer without UART_LSR_DR bit set, we
1474 * just force the read character to be 0
1475 */
1476 ch = 0;
1477
1da177e4
LT		 1478 flag = TTY_NORMAL;
1479 up->port.icount.rx++;
1480
ad4c2aa6
CM		 1481 lsr |= up->lsr_saved_flags;
1482 up->lsr_saved_flags = 0;
1da177e4 1483
ad4c2aa6 1484 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1485 /*
1486 * For statistics only
1487 */
1488 if (lsr & UART_LSR_BI) {
1489 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1490 up->port.icount.brk++;
5f873bae
SW		 1491 /*
1492 * If tegra port then clear the rx fifo to
1493 * accept another break/character.
1494 */
1495 if (up->port.type == PORT_TEGRA)
1496 clear_rx_fifo(up);
1497
1da177e4
LT		 1498 /*
1499 * We do the SysRQ and SAK checking
1500 * here because otherwise the break
1501 * may get masked by ignore_status_mask
1502 * or read_status_mask.
1503 */
1504 if (uart_handle_break(&up->port))
1505 goto ignore_char;
1506 } else if (lsr & UART_LSR_PE)
1507 up->port.icount.parity++;
1508 else if (lsr & UART_LSR_FE)
1509 up->port.icount.frame++;
1510 if (lsr & UART_LSR_OE)
1511 up->port.icount.overrun++;
1512
1513 /*
23907eb8 1514 * Mask off conditions which should be ignored.
1da177e4
LT		 1515 */
1516 lsr &= up->port.read_status_mask;
1517
1518 if (lsr & UART_LSR_BI) {
1519 DEBUG_INTR("handling break....");
1520 flag = TTY_BREAK;
1521 } else if (lsr & UART_LSR_PE)
1522 flag = TTY_PARITY;
1523 else if (lsr & UART_LSR_FE)
1524 flag = TTY_FRAME;
1525 }
7d12e780 1526 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1527 goto ignore_char;
05ab3014
RK		 1528
1529 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1530
6f803cd0 1531ignore_char:
1da177e4 1532 lsr = serial_inp(up, UART_LSR);
7500b1f6 1533 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1da177e4
LT		 1534 spin_unlock(&up->port.lock);
1535 tty_flip_buffer_push(tty);
1536 spin_lock(&up->port.lock);
1537 *status = lsr;
1538}
1539
ea8874dc 1540static void transmit_chars(struct uart_8250_port *up)
1da177e4 1541{
ebd2c8f6 1542 struct circ_buf *xmit = &up->port.state->xmit;
1da177e4
LT		 1543 int count;
1544
1545 if (up->port.x_char) {
1546 serial_outp(up, UART_TX, up->port.x_char);
1547 up->port.icount.tx++;
1548 up->port.x_char = 0;
1549 return;
1550 }
b129a8cc
RK		 1551 if (uart_tx_stopped(&up->port)) {
1552 serial8250_stop_tx(&up->port);
1553 return;
1554 }
1555 if (uart_circ_empty(xmit)) {
e763b90c 1556 __stop_tx(up);
1da177e4
LT		 1557 return;
1558 }
1559
1560 count = up->tx_loadsz;
1561 do {
1562 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1563 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1564 up->port.icount.tx++;
1565 if (uart_circ_empty(xmit))
1566 break;
1567 } while (--count > 0);
1568
1569 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1570 uart_write_wakeup(&up->port);
1571
1572 DEBUG_INTR("THRE...");
1573
1574 if (uart_circ_empty(xmit))
e763b90c 1575 __stop_tx(up);
1da177e4
LT		 1576}
1577
2af7cd68 1578static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1579{
2af7cd68
RK		 1580 unsigned int status = serial_in(up, UART_MSR);
1581
ad4c2aa6
CM		 1582 status |= up->msr_saved_flags;
1583 up->msr_saved_flags = 0;
fdc30b3d 1584 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
ebd2c8f6 1585 up->port.state != NULL) {
2af7cd68
RK		 1586 if (status & UART_MSR_TERI)
1587 up->port.icount.rng++;
1588 if (status & UART_MSR_DDSR)
1589 up->port.icount.dsr++;
1590 if (status & UART_MSR_DDCD)
1591 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1592 if (status & UART_MSR_DCTS)
1593 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1594
bdc04e31 1595 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
2af7cd68 1596 }
1da177e4 1597
2af7cd68 1598 return status;
1da177e4
LT		 1599}
1600
1601/*
1602 * This handles the interrupt from one port.
1603 */
b5d674ab 1604static void serial8250_handle_port(struct uart_8250_port *up)
1da177e4 1605{
45e24601 1606 unsigned int status;
4bf3631c 1607 unsigned long flags;
45e24601 1608
4bf3631c 1609 spin_lock_irqsave(&up->port.lock, flags);
45e24601
RK		 1610
1611 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1612
1613 DEBUG_INTR("status = %x...", status);
1614
7500b1f6 1615 if (status & (UART_LSR_DR | UART_LSR_BI))
7d12e780 1616 receive_chars(up, &status);
1da177e4
LT		 1617 check_modem_status(up);
1618 if (status & UART_LSR_THRE)
1619 transmit_chars(up);
45e24601 1620
4bf3631c 1621 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1622}
1623
1624/*
1625 * This is the serial driver's interrupt routine.
1626 *
1627 * Arjan thinks the old way was overly complex, so it got simplified.
1628 * Alan disagrees, saying that need the complexity to handle the weird
1629 * nature of ISA shared interrupts. (This is a special exception.)
1630 *
1631 * In order to handle ISA shared interrupts properly, we need to check
1632 * that all ports have been serviced, and therefore the ISA interrupt
1633 * line has been de-asserted.
1634 *
1635 * This means we need to loop through all ports. checking that they
1636 * don't have an interrupt pending.
1637 */
7d12e780 1638static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1639{
1640 struct irq_info *i = dev_id;
1641 struct list_head *l, *end = NULL;
1642 int pass_counter = 0, handled = 0;
1643
1644 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1645
1646 spin_lock(&i->lock);
1647
1648 l = i->head;
1649 do {
1650 struct uart_8250_port *up;
1651 unsigned int iir;
1652
1653 up = list_entry(l, struct uart_8250_port, list);
1654
1655 iir = serial_in(up, UART_IIR);
1656 if (!(iir & UART_IIR_NO_INT)) {
7d12e780 1657 serial8250_handle_port(up);
1da177e4
LT		 1658
1659 handled = 1;
1660
beab697a 1661 end = NULL;
a3ae0fc3
JI		 1662 } else if ((up->port.iotype == UPIO_DWAPB ||
1663 up->port.iotype == UPIO_DWAPB32) &&
beab697a
MSJ		 1664 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1665 /* The DesignWare APB UART has an Busy Detect (0x07)
25985edc 1666 * interrupt meaning an LCR write attempt occurred while the
beab697a
MSJ		 1667 * UART was busy. The interrupt must be cleared by reading
1668 * the UART status register (USR) and the LCR re-written. */
1669 unsigned int status;
1670 status = *(volatile u32 *)up->port.private_data;
1671 serial_out(up, UART_LCR, up->lcr);
1672
1673 handled = 1;
1674
1da177e4
LT		 1675 end = NULL;
1676 } else if (end == NULL)
1677 end = l;
1678
1679 l = l->next;
1680
1681 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1682 /* If we hit this, we're dead. */
cd3ecad1
DD		 1683 printk_ratelimited(KERN_ERR
1684 "serial8250: too much work for irq%d\n", irq);
1da177e4
LT		 1685 break;
1686 }
1687 } while (l != end);
1688
1689 spin_unlock(&i->lock);
1690
1691 DEBUG_INTR("end.\n");
1692
1693 return IRQ_RETVAL(handled);
1694}
1695
1696/*
1697 * To support ISA shared interrupts, we need to have one interrupt
1698 * handler that ensures that the IRQ line has been deasserted
1699 * before returning. Failing to do this will result in the IRQ
1700 * line being stuck active, and, since ISA irqs are edge triggered,
1701 * no more IRQs will be seen.
1702 */
1703static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1704{
1705 spin_lock_irq(&i->lock);
1706
1707 if (!list_empty(i->head)) {
1708 if (i->head == &up->list)
1709 i->head = i->head->next;
1710 list_del(&up->list);
1711 } else {
1712 BUG_ON(i->head != &up->list);
1713 i->head = NULL;
1714 }
1da177e4 1715 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1716 /* List empty so throw away the hash node */
1717 if (i->head == NULL) {
1718 hlist_del(&i->node);
1719 kfree(i);
1720 }
1da177e4
LT		 1721}
1722
1723static int serial_link_irq_chain(struct uart_8250_port *up)
1724{
25db8ad5
AC		 1725 struct hlist_head *h;
1726 struct hlist_node *n;
1727 struct irq_info *i;
40663cc7 1728 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1729
25db8ad5
AC		 1730 mutex_lock(&hash_mutex);
1731
1732 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1733
1734 hlist_for_each(n, h) {
1735 i = hlist_entry(n, struct irq_info, node);
1736 if (i->irq == up->port.irq)
1737 break;
1738 }
1739
1740 if (n == NULL) {
1741 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1742 if (i == NULL) {
1743 mutex_unlock(&hash_mutex);
1744 return -ENOMEM;
1745 }
1746 spin_lock_init(&i->lock);
1747 i->irq = up->port.irq;
1748 hlist_add_head(&i->node, h);
1749 }
1750 mutex_unlock(&hash_mutex);
1751
1da177e4
LT		 1752 spin_lock_irq(&i->lock);
1753
1754 if (i->head) {
1755 list_add(&up->list, i->head);
1756 spin_unlock_irq(&i->lock);
1757
1758 ret = 0;
1759 } else {
1760 INIT_LIST_HEAD(&up->list);
1761 i->head = &up->list;
1762 spin_unlock_irq(&i->lock);
1c2f0493 1763 irq_flags |= up->port.irqflags;
1da177e4
LT		 1764 ret = request_irq(up->port.irq, serial8250_interrupt,
1765 irq_flags, "serial", i);
1766 if (ret < 0)
1767 serial_do_unlink(i, up);
1768 }
1769
1770 return ret;
1771}
1772
1773static void serial_unlink_irq_chain(struct uart_8250_port *up)
1774{
25db8ad5
AC		 1775 struct irq_info *i;
1776 struct hlist_node *n;
1777 struct hlist_head *h;
1da177e4 1778
25db8ad5
AC		 1779 mutex_lock(&hash_mutex);
1780
1781 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1782
1783 hlist_for_each(n, h) {
1784 i = hlist_entry(n, struct irq_info, node);
1785 if (i->irq == up->port.irq)
1786 break;
1787 }
1788
1789 BUG_ON(n == NULL);
1da177e4
LT		 1790 BUG_ON(i->head == NULL);
1791
1792 if (list_empty(i->head))
1793 free_irq(up->port.irq, i);
1794
1795 serial_do_unlink(i, up);
25db8ad5 1796 mutex_unlock(&hash_mutex);
1da177e4
LT		 1797}
1798
1799/*
1800 * This function is used to handle ports that do not have an
1801 * interrupt. This doesn't work very well for 16450's, but gives
1802 * barely passable results for a 16550A. (Although at the expense
1803 * of much CPU overhead).
1804 */
1805static void serial8250_timeout(unsigned long data)
1806{
1807 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4
LT		 1808 unsigned int iir;
1809
1810 iir = serial_in(up, UART_IIR);
45e24601 1811 if (!(iir & UART_IIR_NO_INT))
7d12e780 1812 serial8250_handle_port(up);
54381067 1813 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
40b36daa
AW		 1814}
1815
1816static void serial8250_backup_timeout(unsigned long data)
1817{
1818 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1819 unsigned int iir, ier = 0, lsr;
1820 unsigned long flags;
40b36daa
AW		 1821
1822 /*
1823 * Must disable interrupts or else we risk racing with the interrupt
1824 * based handler.
1825 */
1826 if (is_real_interrupt(up->port.irq)) {
1827 ier = serial_in(up, UART_IER);
1828 serial_out(up, UART_IER, 0);
1829 }
1da177e4 1830
40b36daa
AW		 1831 iir = serial_in(up, UART_IIR);
1832
1833 /*
1834 * This should be a safe test for anyone who doesn't trust the
1835 * IIR bits on their UART, but it's specifically designed for
1836 * the "Diva" UART used on the management processor on many HP
1837 * ia64 and parisc boxes.
1838 */
ad4c2aa6
CM		 1839 spin_lock_irqsave(&up->port.lock, flags);
1840 lsr = serial_in(up, UART_LSR);
1841 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1842 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa 1843 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1844 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1845 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1846 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1847 iir |= UART_IIR_THRI;
1848 }
1849
1850 if (!(iir & UART_IIR_NO_INT))
1851 serial8250_handle_port(up);
1852
1853 if (is_real_interrupt(up->port.irq))
1854 serial_out(up, UART_IER, ier);
1855
1856 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0 1857 mod_timer(&up->timer,
54381067 1858 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1da177e4
LT		 1859}
1860
1861static unsigned int serial8250_tx_empty(struct uart_port *port)
1862{
49d5741b
JI		 1863 struct uart_8250_port *up =
1864 container_of(port, struct uart_8250_port, port);
1da177e4 1865 unsigned long flags;
ad4c2aa6 1866 unsigned int lsr;
1da177e4
LT		 1867
1868 spin_lock_irqsave(&up->port.lock, flags);
ad4c2aa6
CM		 1869 lsr = serial_in(up, UART_LSR);
1870 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1da177e4
LT		 1871 spin_unlock_irqrestore(&up->port.lock, flags);
1872
bca47613 1873 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1874}
1875
1876static unsigned int serial8250_get_mctrl(struct uart_port *port)
1877{
49d5741b
JI		 1878 struct uart_8250_port *up =
1879 container_of(port, struct uart_8250_port, port);
2af7cd68 1880 unsigned int status;
1da177e4
LT		 1881 unsigned int ret;
1882
2af7cd68 1883 status = check_modem_status(up);
1da177e4
LT		 1884
1885 ret = 0;
1886 if (status & UART_MSR_DCD)
1887 ret |= TIOCM_CAR;
1888 if (status & UART_MSR_RI)
1889 ret |= TIOCM_RNG;
1890 if (status & UART_MSR_DSR)
1891 ret |= TIOCM_DSR;
1892 if (status & UART_MSR_CTS)
1893 ret |= TIOCM_CTS;
1894 return ret;
1895}
1896
1897static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1898{
49d5741b
JI		 1899 struct uart_8250_port *up =
1900 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1901 unsigned char mcr = 0;
1902
1903 if (mctrl & TIOCM_RTS)
1904 mcr |= UART_MCR_RTS;
1905 if (mctrl & TIOCM_DTR)
1906 mcr |= UART_MCR_DTR;
1907 if (mctrl & TIOCM_OUT1)
1908 mcr |= UART_MCR_OUT1;
1909 if (mctrl & TIOCM_OUT2)
1910 mcr |= UART_MCR_OUT2;
1911 if (mctrl & TIOCM_LOOP)
1912 mcr |= UART_MCR_LOOP;
1913
1914 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1915
1916 serial_out(up, UART_MCR, mcr);
1917}
1918
1919static void serial8250_break_ctl(struct uart_port *port, int break_state)
1920{
49d5741b
JI		 1921 struct uart_8250_port *up =
1922 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1923 unsigned long flags;
1924
1925 spin_lock_irqsave(&up->port.lock, flags);
1926 if (break_state == -1)
1927 up->lcr |= UART_LCR_SBC;
1928 else
1929 up->lcr &= ~UART_LCR_SBC;
1930 serial_out(up, UART_LCR, up->lcr);
1931 spin_unlock_irqrestore(&up->port.lock, flags);
1932}
1933
40b36daa
AW		 1934/*
1935 * Wait for transmitter & holding register to empty
1936 */
b5d674ab 1937static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1938{
1939 unsigned int status, tmout = 10000;
1940
1941 /* Wait up to 10ms for the character(s) to be sent. */
97d303b7 1942 for (;;) {
40b36daa
AW		 1943 status = serial_in(up, UART_LSR);
1944
ad4c2aa6 1945 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa 1946
97d303b7
DD		 1947 if ((status & bits) == bits)
1948 break;
40b36daa
AW		 1949 if (--tmout == 0)
1950 break;
1951 udelay(1);
97d303b7 1952 }
40b36daa
AW		 1953
1954 /* Wait up to 1s for flow control if necessary */
1955 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1956 unsigned int tmout;
1957 for (tmout = 1000000; tmout; tmout--) {
1958 unsigned int msr = serial_in(up, UART_MSR);
1959 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1960 if (msr & UART_MSR_CTS)
1961 break;
40b36daa
AW		 1962 udelay(1);
1963 touch_nmi_watchdog();
1964 }
1965 }
1966}
1967
f2d937f3
JW		 1968#ifdef CONFIG_CONSOLE_POLL
1969/*
1970 * Console polling routines for writing and reading from the uart while
1971 * in an interrupt or debug context.
1972 */
1973
1974static int serial8250_get_poll_char(struct uart_port *port)
1975{
49d5741b
JI		 1976 struct uart_8250_port *up =
1977 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1978 unsigned char lsr = serial_inp(up, UART_LSR);
1979
f5316b4a
JW		 1980 if (!(lsr & UART_LSR_DR))
1981 return NO_POLL_CHAR;
f2d937f3
JW		 1982
1983 return serial_inp(up, UART_RX);
1984}
1985
1986
1987static void serial8250_put_poll_char(struct uart_port *port,
1988 unsigned char c)
1989{
1990 unsigned int ier;
49d5741b
JI		 1991 struct uart_8250_port *up =
1992 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1993
1994 /*
1995 * First save the IER then disable the interrupts
1996 */
1997 ier = serial_in(up, UART_IER);
1998 if (up->capabilities & UART_CAP_UUE)
1999 serial_out(up, UART_IER, UART_IER_UUE);
2000 else
2001 serial_out(up, UART_IER, 0);
2002
2003 wait_for_xmitr(up, BOTH_EMPTY);
2004 /*
2005 * Send the character out.
2006 * If a LF, also do CR...
2007 */
2008 serial_out(up, UART_TX, c);
2009 if (c == 10) {
2010 wait_for_xmitr(up, BOTH_EMPTY);
2011 serial_out(up, UART_TX, 13);
2012 }
2013
2014 /*
2015 * Finally, wait for transmitter to become empty
2016 * and restore the IER
2017 */
2018 wait_for_xmitr(up, BOTH_EMPTY);
2019 serial_out(up, UART_IER, ier);
2020}
2021
2022#endif /* CONFIG_CONSOLE_POLL */
2023
1da177e4
LT		 2024static int serial8250_startup(struct uart_port *port)
2025{
49d5741b
JI		 2026 struct uart_8250_port *up =
2027 container_of(port, struct uart_8250_port, port);
1da177e4 2028 unsigned long flags;
55d3b282 2029 unsigned char lsr, iir;
1da177e4
LT		 2030 int retval;
2031
e4f05af1
OP		 2032 up->port.fifosize = uart_config[up->port.type].fifo_size;
2033 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1da177e4
LT		 2034 up->capabilities = uart_config[up->port.type].flags;
2035 up->mcr = 0;
2036
b8e7e40a
AC		 2037 if (up->port.iotype != up->cur_iotype)
2038 set_io_from_upio(port);
2039
1da177e4
LT		 2040 if (up->port.type == PORT_16C950) {
2041 /* Wake up and initialize UART */
2042 up->acr = 0;
662b083a 2043 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 2044 serial_outp(up, UART_EFR, UART_EFR_ECB);
2045 serial_outp(up, UART_IER, 0);
2046 serial_outp(up, UART_LCR, 0);
2047 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2048 serial_outp(up, UART_LCR, 0xBF);
2049 serial_outp(up, UART_EFR, UART_EFR_ECB);
2050 serial_outp(up, UART_LCR, 0);
2051 }
2052
2053#ifdef CONFIG_SERIAL_8250_RSA
2054 /*
2055 * If this is an RSA port, see if we can kick it up to the
2056 * higher speed clock.
2057 */
2058 enable_rsa(up);
2059#endif
2060
2061 /*
2062 * Clear the FIFO buffers and disable them.
7f927fcc 2063 * (they will be reenabled in set_termios())
1da177e4
LT		 2064 */
2065 serial8250_clear_fifos(up);
2066
2067 /*
2068 * Clear the interrupt registers.
2069 */
2070 (void) serial_inp(up, UART_LSR);
2071 (void) serial_inp(up, UART_RX);
2072 (void) serial_inp(up, UART_IIR);
2073 (void) serial_inp(up, UART_MSR);
2074
2075 /*
2076 * At this point, there's no way the LSR could still be 0xff;
2077 * if it is, then bail out, because there's likely no UART
2078 * here.
2079 */
2080 if (!(up->port.flags & UPF_BUGGY_UART) &&
2081 (serial_inp(up, UART_LSR) == 0xff)) {
8440838b
DM		 2082 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2083 serial_index(&up->port));
1da177e4
LT		 2084 return -ENODEV;
2085 }
2086
2087 /*
2088 * For a XR16C850, we need to set the trigger levels
2089 */
2090 if (up->port.type == PORT_16850) {
2091 unsigned char fctr;
2092
662b083a 2093 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 2094
2095 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2096 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2097 serial_outp(up, UART_TRG, UART_TRG_96);
2098 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2099 serial_outp(up, UART_TRG, UART_TRG_96);
2100
2101 serial_outp(up, UART_LCR, 0);
2102 }
2103
40b36daa 2104 if (is_real_interrupt(up->port.irq)) {
01c194d9 2105 unsigned char iir1;
40b36daa
AW		 2106 /*
2107 * Test for UARTs that do not reassert THRE when the
2108 * transmitter is idle and the interrupt has already
2109 * been cleared. Real 16550s should always reassert
2110 * this interrupt whenever the transmitter is idle and
2111 * the interrupt is enabled. Delays are necessary to
2112 * allow register changes to become visible.
2113 */
c389d27b 2114 spin_lock_irqsave(&up->port.lock, flags);
1c2f0493 2115 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2116 disable_irq_nosync(up->port.irq);
40b36daa
AW		 2117
2118 wait_for_xmitr(up, UART_LSR_THRE);
2119 serial_out_sync(up, UART_IER, UART_IER_THRI);
2120 udelay(1); /* allow THRE to set */
01c194d9 2121 iir1 = serial_in(up, UART_IIR);
40b36daa
AW		 2122 serial_out(up, UART_IER, 0);
2123 serial_out_sync(up, UART_IER, UART_IER_THRI);
2124 udelay(1); /* allow a working UART time to re-assert THRE */
2125 iir = serial_in(up, UART_IIR);
2126 serial_out(up, UART_IER, 0);
2127
1c2f0493 2128 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2129 enable_irq(up->port.irq);
c389d27b 2130 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa
AW		 2131
2132 /*
2133 * If the interrupt is not reasserted, setup a timer to
2134 * kick the UART on a regular basis.
2135 */
01c194d9 2136 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
363f66fe 2137 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2138 pr_debug("ttyS%d - using backup timer\n",
2139 serial_index(port));
40b36daa
AW		 2140 }
2141 }
2142
363f66fe
WN		 2143 /*
2144 * The above check will only give an accurate result the first time
2145 * the port is opened so this value needs to be preserved.
2146 */
2147 if (up->bugs & UART_BUG_THRE) {
2148 up->timer.function = serial8250_backup_timeout;
2149 up->timer.data = (unsigned long)up;
2150 mod_timer(&up->timer, jiffies +
54381067 2151 uart_poll_timeout(port) + HZ / 5);
363f66fe
WN		 2152 }
2153
1da177e4
LT		 2154 /*
2155 * If the "interrupt" for this port doesn't correspond with any
2156 * hardware interrupt, we use a timer-based system. The original
2157 * driver used to do this with IRQ0.
2158 */
2159 if (!is_real_interrupt(up->port.irq)) {
1da177e4 2160 up->timer.data = (unsigned long)up;
54381067 2161 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
1da177e4
LT		 2162 } else {
2163 retval = serial_link_irq_chain(up);
2164 if (retval)
2165 return retval;
2166 }
2167
2168 /*
2169 * Now, initialize the UART
2170 */
2171 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2172
2173 spin_lock_irqsave(&up->port.lock, flags);
2174 if (up->port.flags & UPF_FOURPORT) {
2175 if (!is_real_interrupt(up->port.irq))
2176 up->port.mctrl |= TIOCM_OUT1;
2177 } else
2178 /*
2179 * Most PC uarts need OUT2 raised to enable interrupts.
2180 */
2181 if (is_real_interrupt(up->port.irq))
2182 up->port.mctrl |= TIOCM_OUT2;
2183
2184 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282 2185
b6adea33
MCC		 2186 /* Serial over Lan (SoL) hack:
2187 Intel 8257x Gigabit ethernet chips have a
2188 16550 emulation, to be used for Serial Over Lan.
2189 Those chips take a longer time than a normal
2190 serial device to signalize that a transmission
2191 data was queued. Due to that, the above test generally
2192 fails. One solution would be to delay the reading of
2193 iir. However, this is not reliable, since the timeout
2194 is variable. So, let's just don't test if we receive
2195 TX irq. This way, we'll never enable UART_BUG_TXEN.
2196 */
d41a4b51 2197 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2198 goto dont_test_tx_en;
2199
55d3b282
RK		 2200 /*
2201 * Do a quick test to see if we receive an
2202 * interrupt when we enable the TX irq.
2203 */
2204 serial_outp(up, UART_IER, UART_IER_THRI);
2205 lsr = serial_in(up, UART_LSR);
2206 iir = serial_in(up, UART_IIR);
2207 serial_outp(up, UART_IER, 0);
2208
2209 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2210 if (!(up->bugs & UART_BUG_TXEN)) {
2211 up->bugs |= UART_BUG_TXEN;
55d3b282 2212 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2213 serial_index(port));
55d3b282
RK		 2214 }
2215 } else {
67f7654e 2216 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2217 }
2218
b6adea33 2219dont_test_tx_en:
1da177e4
LT		 2220 spin_unlock_irqrestore(&up->port.lock, flags);
2221
ad4c2aa6
CM		 2222 /*
2223 * Clear the interrupt registers again for luck, and clear the
2224 * saved flags to avoid getting false values from polling
2225 * routines or the previous session.
2226 */
2227 serial_inp(up, UART_LSR);
2228 serial_inp(up, UART_RX);
2229 serial_inp(up, UART_IIR);
2230 serial_inp(up, UART_MSR);
2231 up->lsr_saved_flags = 0;
2232 up->msr_saved_flags = 0;
2233
1da177e4
LT		 2234 /*
2235 * Finally, enable interrupts. Note: Modem status interrupts
2236 * are set via set_termios(), which will be occurring imminently
2237 * anyway, so we don't enable them here.
2238 */
2239 up->ier = UART_IER_RLSI | UART_IER_RDI;
2240 serial_outp(up, UART_IER, up->ier);
2241
2242 if (up->port.flags & UPF_FOURPORT) {
2243 unsigned int icp;
2244 /*
2245 * Enable interrupts on the AST Fourport board
2246 */
2247 icp = (up->port.iobase & 0xfe0) | 0x01f;
2248 outb_p(0x80, icp);
2249 (void) inb_p(icp);
2250 }
2251
1da177e4
LT		 2252 return 0;
2253}
2254
2255static void serial8250_shutdown(struct uart_port *port)
2256{
49d5741b
JI		 2257 struct uart_8250_port *up =
2258 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2259 unsigned long flags;
2260
2261 /*
2262 * Disable interrupts from this port
2263 */
2264 up->ier = 0;
2265 serial_outp(up, UART_IER, 0);
2266
2267 spin_lock_irqsave(&up->port.lock, flags);
2268 if (up->port.flags & UPF_FOURPORT) {
2269 /* reset interrupts on the AST Fourport board */
2270 inb((up->port.iobase & 0xfe0) | 0x1f);
2271 up->port.mctrl |= TIOCM_OUT1;
2272 } else
2273 up->port.mctrl &= ~TIOCM_OUT2;
2274
2275 serial8250_set_mctrl(&up->port, up->port.mctrl);
2276 spin_unlock_irqrestore(&up->port.lock, flags);
2277
2278 /*
2279 * Disable break condition and FIFOs
2280 */
2281 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2282 serial8250_clear_fifos(up);
2283
2284#ifdef CONFIG_SERIAL_8250_RSA
2285 /*
2286 * Reset the RSA board back to 115kbps compat mode.
2287 */
2288 disable_rsa(up);
2289#endif
2290
2291 /*
2292 * Read data port to reset things, and then unlink from
2293 * the IRQ chain.
2294 */
2295 (void) serial_in(up, UART_RX);
2296
40b36daa
AW		 2297 del_timer_sync(&up->timer);
2298 up->timer.function = serial8250_timeout;
2299 if (is_real_interrupt(up->port.irq))
1da177e4
LT		 2300 serial_unlink_irq_chain(up);
2301}
2302
2303static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2304{
2305 unsigned int quot;
2306
2307 /*
2308 * Handle magic divisors for baud rates above baud_base on
2309 * SMSC SuperIO chips.
2310 */
2311 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2312 baud == (port->uartclk/4))
2313 quot = 0x8001;
2314 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2315 baud == (port->uartclk/8))
2316 quot = 0x8002;
2317 else
2318 quot = uart_get_divisor(port, baud);
2319
2320 return quot;
2321}
2322
235dae5d
PL		 2323void
2324serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2325 struct ktermios *old)
1da177e4 2326{
49d5741b
JI		 2327 struct uart_8250_port *up =
2328 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2329 unsigned char cval, fcr = 0;
2330 unsigned long flags;
2331 unsigned int baud, quot;
2332
2333 switch (termios->c_cflag & CSIZE) {
2334 case CS5:
0a8b80c5 2335 cval = UART_LCR_WLEN5;
1da177e4
LT		 2336 break;
2337 case CS6:
0a8b80c5 2338 cval = UART_LCR_WLEN6;
1da177e4
LT		 2339 break;
2340 case CS7:
0a8b80c5 2341 cval = UART_LCR_WLEN7;
1da177e4
LT		 2342 break;
2343 default:
2344 case CS8:
0a8b80c5 2345 cval = UART_LCR_WLEN8;
1da177e4
LT		 2346 break;
2347 }
2348
2349 if (termios->c_cflag & CSTOPB)
0a8b80c5 2350 cval |= UART_LCR_STOP;
1da177e4
LT		 2351 if (termios->c_cflag & PARENB)
2352 cval |= UART_LCR_PARITY;
2353 if (!(termios->c_cflag & PARODD))
2354 cval |= UART_LCR_EPAR;
2355#ifdef CMSPAR
2356 if (termios->c_cflag & CMSPAR)
2357 cval |= UART_LCR_SPAR;
2358#endif
2359
2360 /*
2361 * Ask the core to calculate the divisor for us.
2362 */
24d481ec
AV		 2363 baud = uart_get_baud_rate(port, termios, old,
2364 port->uartclk / 16 / 0xffff,
2365 port->uartclk / 16);
1da177e4
LT		 2366 quot = serial8250_get_divisor(port, baud);
2367
2368 /*
4ba5e35d 2369 * Oxford Semi 952 rev B workaround
1da177e4 2370 */
4ba5e35d 2371 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2372 quot++;
1da177e4
LT		 2373
2374 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2375 if (baud < 2400)
2376 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2377 else
2378 fcr = uart_config[up->port.type].fcr;
2379 }
2380
2381 /*
2382 * MCR-based auto flow control. When AFE is enabled, RTS will be
2383 * deasserted when the receive FIFO contains more characters than
2384 * the trigger, or the MCR RTS bit is cleared. In the case where
2385 * the remote UART is not using CTS auto flow control, we must
2386 * have sufficient FIFO entries for the latency of the remote
2387 * UART to respond. IOW, at least 32 bytes of FIFO.
2388 */
2389 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2390 up->mcr &= ~UART_MCR_AFE;
2391 if (termios->c_cflag & CRTSCTS)
2392 up->mcr |= UART_MCR_AFE;
2393 }
2394
2395 /*
2396 * Ok, we're now changing the port state. Do it with
2397 * interrupts disabled.
2398 */
2399 spin_lock_irqsave(&up->port.lock, flags);
2400
2401 /*
2402 * Update the per-port timeout.
2403 */
2404 uart_update_timeout(port, termios->c_cflag, baud);
2405
2406 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2407 if (termios->c_iflag & INPCK)
2408 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2409 if (termios->c_iflag & (BRKINT | PARMRK))
2410 up->port.read_status_mask |= UART_LSR_BI;
2411
2412 /*
2413 * Characteres to ignore
2414 */
2415 up->port.ignore_status_mask = 0;
2416 if (termios->c_iflag & IGNPAR)
2417 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2418 if (termios->c_iflag & IGNBRK) {
2419 up->port.ignore_status_mask |= UART_LSR_BI;
2420 /*
2421 * If we're ignoring parity and break indicators,
2422 * ignore overruns too (for real raw support).
2423 */
2424 if (termios->c_iflag & IGNPAR)
2425 up->port.ignore_status_mask |= UART_LSR_OE;
2426 }
2427
2428 /*
2429 * ignore all characters if CREAD is not set
2430 */
2431 if ((termios->c_cflag & CREAD) == 0)
2432 up->port.ignore_status_mask |= UART_LSR_DR;
2433
2434 /*
2435 * CTS flow control flag and modem status interrupts
2436 */
f8b372a1 2437 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2438 if (!(up->bugs & UART_BUG_NOMSR) &&
2439 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2440 up->ier |= UART_IER_MSI;
2441 if (up->capabilities & UART_CAP_UUE)
4539c24f
SW		 2442 up->ier |= UART_IER_UUE;
2443 if (up->capabilities & UART_CAP_RTOIE)
2444 up->ier |= UART_IER_RTOIE;
1da177e4
LT		 2445
2446 serial_out(up, UART_IER, up->ier);
2447
2448 if (up->capabilities & UART_CAP_EFR) {
2449 unsigned char efr = 0;
2450 /*
2451 * TI16C752/Startech hardware flow control. FIXME:
2452 * - TI16C752 requires control thresholds to be set.
2453 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2454 */
2455 if (termios->c_cflag & CRTSCTS)
2456 efr |= UART_EFR_CTS;
2457
662b083a 2458 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 2459 serial_outp(up, UART_EFR, efr);
2460 }
2461
f2eda27d 2462#ifdef CONFIG_ARCH_OMAP
255341c6 2463 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
5668545a 2464 if (cpu_is_omap1510() && is_omap_port(up)) {
255341c6
JM		 2465 if (baud == 115200) {
2466 quot = 1;
2467 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2468 } else
2469 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2470 }
2471#endif
2472
1da177e4
LT		 2473 if (up->capabilities & UART_NATSEMI) {
2474 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2475 serial_outp(up, UART_LCR, 0xe0);
2476 } else {
2477 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2478 }
2479
b32b19b8 2480 serial_dl_write(up, quot);
1da177e4
LT		 2481
2482 /*
2483 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2484 * is written without DLAB set, this mode will be disabled.
2485 */
2486 if (up->port.type == PORT_16750)
2487 serial_outp(up, UART_FCR, fcr);
2488
2489 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2490 up->lcr = cval; /* Save LCR */
2491 if (up->port.type != PORT_16750) {
2492 if (fcr & UART_FCR_ENABLE_FIFO) {
2493 /* emulated UARTs (Lucent Venus 167x) need two steps */
2494 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2495 }
2496 serial_outp(up, UART_FCR, fcr); /* set fcr */
2497 }
2498 serial8250_set_mctrl(&up->port, up->port.mctrl);
2499 spin_unlock_irqrestore(&up->port.lock, flags);
e991a2bd
AC		 2500 /* Don't rewrite B0 */
2501 if (tty_termios_baud_rate(termios))
2502 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4 2503}
235dae5d
PL		 2504EXPORT_SYMBOL(serial8250_do_set_termios);
2505
2506static void
2507serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2508 struct ktermios *old)
2509{
2510 if (port->set_termios)
2511 port->set_termios(port, termios, old);
2512 else
2513 serial8250_do_set_termios(port, termios, old);
2514}
1da177e4 2515
dc77f161 2516static void
a0821df6 2517serial8250_set_ldisc(struct uart_port *port, int new)
dc77f161 2518{
a0821df6 2519 if (new == N_PPS) {
dc77f161
RG		 2520 port->flags |= UPF_HARDPPS_CD;
2521 serial8250_enable_ms(port);
2522 } else
2523 port->flags &= ~UPF_HARDPPS_CD;
2524}
2525
c161afe9
ML		 2526
2527void serial8250_do_pm(struct uart_port *port, unsigned int state,
2528 unsigned int oldstate)
1da177e4 2529{
49d5741b
JI		 2530 struct uart_8250_port *p =
2531 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2532
2533 serial8250_set_sleep(p, state != 0);
c161afe9
ML		 2534}
2535EXPORT_SYMBOL(serial8250_do_pm);
1da177e4 2536
c161afe9
ML		 2537static void
2538serial8250_pm(struct uart_port *port, unsigned int state,
2539 unsigned int oldstate)
2540{
2541 if (port->pm)
2542 port->pm(port, state, oldstate);
2543 else
2544 serial8250_do_pm(port, state, oldstate);
1da177e4
LT		 2545}
2546
f2eda27d
RK		 2547static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2548{
2549 if (pt->port.iotype == UPIO_AU)
b2b13cdf 2550 return 0x1000;
f2eda27d
RK		 2551#ifdef CONFIG_ARCH_OMAP
2552 if (is_omap_port(pt))
2553 return 0x16 << pt->port.regshift;
2554#endif
2555 return 8 << pt->port.regshift;
2556}
2557
1da177e4
LT		 2558/*
2559 * Resource handling.
2560 */
2561static int serial8250_request_std_resource(struct uart_8250_port *up)
2562{
f2eda27d 2563 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2564 int ret = 0;
2565
2566 switch (up->port.iotype) {
85835f44 2567 case UPIO_AU:
0b30d668
SS		 2568 case UPIO_TSI:
2569 case UPIO_MEM32:
1da177e4 2570 case UPIO_MEM:
beab697a 2571 case UPIO_DWAPB:
a3ae0fc3 2572 case UPIO_DWAPB32:
1da177e4
LT		 2573 if (!up->port.mapbase)
2574 break;
2575
2576 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2577 ret = -EBUSY;
2578 break;
2579 }
2580
2581 if (up->port.flags & UPF_IOREMAP) {
6f441fe9
AC		 2582 up->port.membase = ioremap_nocache(up->port.mapbase,
2583 size);
1da177e4
LT		 2584 if (!up->port.membase) {
2585 release_mem_region(up->port.mapbase, size);
2586 ret = -ENOMEM;
2587 }
2588 }
2589 break;
2590
2591 case UPIO_HUB6:
2592 case UPIO_PORT:
2593 if (!request_region(up->port.iobase, size, "serial"))
2594 ret = -EBUSY;
2595 break;
2596 }
2597 return ret;
2598}
2599
2600static void serial8250_release_std_resource(struct uart_8250_port *up)
2601{
f2eda27d 2602 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2603
2604 switch (up->port.iotype) {
85835f44 2605 case UPIO_AU:
0b30d668
SS		 2606 case UPIO_TSI:
2607 case UPIO_MEM32:
1da177e4 2608 case UPIO_MEM:
beab697a 2609 case UPIO_DWAPB:
a3ae0fc3 2610 case UPIO_DWAPB32:
1da177e4
LT		 2611 if (!up->port.mapbase)
2612 break;
2613
2614 if (up->port.flags & UPF_IOREMAP) {
2615 iounmap(up->port.membase);
2616 up->port.membase = NULL;
2617 }
2618
2619 release_mem_region(up->port.mapbase, size);
2620 break;
2621
2622 case UPIO_HUB6:
2623 case UPIO_PORT:
2624 release_region(up->port.iobase, size);
2625 break;
2626 }
2627}
2628
2629static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2630{
2631 unsigned long start = UART_RSA_BASE << up->port.regshift;
2632 unsigned int size = 8 << up->port.regshift;
0b30d668 2633 int ret = -EINVAL;
1da177e4
LT		 2634
2635 switch (up->port.iotype) {
1da177e4
LT		 2636 case UPIO_HUB6:
2637 case UPIO_PORT:
2638 start += up->port.iobase;
0b30d668
SS		 2639 if (request_region(start, size, "serial-rsa"))
2640 ret = 0;
2641 else
1da177e4
LT		 2642 ret = -EBUSY;
2643 break;
2644 }
2645
2646 return ret;
2647}
2648
2649static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2650{
2651 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2652 unsigned int size = 8 << up->port.regshift;
2653
2654 switch (up->port.iotype) {
1da177e4
LT		 2655 case UPIO_HUB6:
2656 case UPIO_PORT:
2657 release_region(up->port.iobase + offset, size);
2658 break;
2659 }
2660}
2661
2662static void serial8250_release_port(struct uart_port *port)
2663{
49d5741b
JI		 2664 struct uart_8250_port *up =
2665 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2666
2667 serial8250_release_std_resource(up);
2668 if (up->port.type == PORT_RSA)
2669 serial8250_release_rsa_resource(up);
2670}
2671
2672static int serial8250_request_port(struct uart_port *port)
2673{
49d5741b
JI		 2674 struct uart_8250_port *up =
2675 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2676 int ret = 0;
2677
2678 ret = serial8250_request_std_resource(up);
2679 if (ret == 0 && up->port.type == PORT_RSA) {
2680 ret = serial8250_request_rsa_resource(up);
2681 if (ret < 0)
2682 serial8250_release_std_resource(up);
2683 }
2684
2685 return ret;
2686}
2687
2688static void serial8250_config_port(struct uart_port *port, int flags)
2689{
49d5741b
JI		 2690 struct uart_8250_port *up =
2691 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2692 int probeflags = PROBE_ANY;
2693 int ret;
2694
1da177e4
LT		 2695 /*
2696 * Find the region that we can probe for. This in turn
2697 * tells us whether we can probe for the type of port.
2698 */
2699 ret = serial8250_request_std_resource(up);
2700 if (ret < 0)
2701 return;
2702
2703 ret = serial8250_request_rsa_resource(up);
2704 if (ret < 0)
2705 probeflags &= ~PROBE_RSA;
2706
b8e7e40a
AC		 2707 if (up->port.iotype != up->cur_iotype)
2708 set_io_from_upio(port);
2709
1da177e4
LT		 2710 if (flags & UART_CONFIG_TYPE)
2711 autoconfig(up, probeflags);
b2b13cdf 2712
b2b13cdf
ML		 2713 /* if access method is AU, it is a 16550 with a quirk */
2714 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2715 up->bugs |= UART_BUG_NOMSR;
b2b13cdf 2716
1da177e4
LT		 2717 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2718 autoconfig_irq(up);
2719
2720 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2721 serial8250_release_rsa_resource(up);
2722 if (up->port.type == PORT_UNKNOWN)
2723 serial8250_release_std_resource(up);
2724}
2725
2726static int
2727serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2728{
a62c4133 2729 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2730 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2731 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2732 ser->type == PORT_STARTECH)
2733 return -EINVAL;
2734 return 0;
2735}
2736
2737static const char *
2738serial8250_type(struct uart_port *port)
2739{
2740 int type = port->type;
2741
2742 if (type >= ARRAY_SIZE(uart_config))
2743 type = 0;
2744 return uart_config[type].name;
2745}
2746
2747static struct uart_ops serial8250_pops = {
2748 .tx_empty = serial8250_tx_empty,
2749 .set_mctrl = serial8250_set_mctrl,
2750 .get_mctrl = serial8250_get_mctrl,
2751 .stop_tx = serial8250_stop_tx,
2752 .start_tx = serial8250_start_tx,
2753 .stop_rx = serial8250_stop_rx,
2754 .enable_ms = serial8250_enable_ms,
2755 .break_ctl = serial8250_break_ctl,
2756 .startup = serial8250_startup,
2757 .shutdown = serial8250_shutdown,
2758 .set_termios = serial8250_set_termios,
dc77f161 2759 .set_ldisc = serial8250_set_ldisc,
1da177e4
LT		 2760 .pm = serial8250_pm,
2761 .type = serial8250_type,
2762 .release_port = serial8250_release_port,
2763 .request_port = serial8250_request_port,
2764 .config_port = serial8250_config_port,
2765 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2766#ifdef CONFIG_CONSOLE_POLL
2767 .poll_get_char = serial8250_get_poll_char,
2768 .poll_put_char = serial8250_put_poll_char,
2769#endif
1da177e4
LT		 2770};
2771
2772static struct uart_8250_port serial8250_ports[UART_NR];
2773
af7f3743
AC		 2774static void (*serial8250_isa_config)(int port, struct uart_port *up,
2775 unsigned short *capabilities);
2776
2777void serial8250_set_isa_configurator(
2778 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2779{
2780 serial8250_isa_config = v;
2781}
2782EXPORT_SYMBOL(serial8250_set_isa_configurator);
2783
1da177e4
LT		 2784static void __init serial8250_isa_init_ports(void)
2785{
2786 struct uart_8250_port *up;
2787 static int first = 1;
4c0ebb80 2788 int i, irqflag = 0;
1da177e4
LT		 2789
2790 if (!first)
2791 return;
2792 first = 0;
2793
a61c2d78 2794 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2795 struct uart_8250_port *up = &serial8250_ports[i];
2796
2797 up->port.line = i;
2798 spin_lock_init(&up->port.lock);
2799
2800 init_timer(&up->timer);
2801 up->timer.function = serial8250_timeout;
2802
2803 /*
2804 * ALPHA_KLUDGE_MCR needs to be killed.
2805 */
2806 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2807 up->mcr_force = ALPHA_KLUDGE_MCR;
2808
2809 up->port.ops = &serial8250_pops;
2810 }
2811
4c0ebb80
AGR		 2812 if (share_irqs)
2813 irqflag = IRQF_SHARED;
2814
44454bcd 2815 for (i = 0, up = serial8250_ports;
a61c2d78 2816 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2817 i++, up++) {
2818 up->port.iobase = old_serial_port[i].port;
2819 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
1c2f0493 2820 up->port.irqflags = old_serial_port[i].irqflags;
1da177e4
LT		 2821 up->port.uartclk = old_serial_port[i].baud_base * 16;
2822 up->port.flags = old_serial_port[i].flags;
2823 up->port.hub6 = old_serial_port[i].hub6;
2824 up->port.membase = old_serial_port[i].iomem_base;
2825 up->port.iotype = old_serial_port[i].io_type;
2826 up->port.regshift = old_serial_port[i].iomem_reg_shift;
7d6a07d1 2827 set_io_from_upio(&up->port);
4c0ebb80 2828 up->port.irqflags |= irqflag;
af7f3743
AC		 2829 if (serial8250_isa_config != NULL)
2830 serial8250_isa_config(i, &up->port, &up->capabilities);
2831
1da177e4
LT		 2832 }
2833}
2834
b5d228cc
SL		 2835static void
2836serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2837{
2838 up->port.type = type;
2839 up->port.fifosize = uart_config[type].fifo_size;
2840 up->capabilities = uart_config[type].flags;
2841 up->tx_loadsz = uart_config[type].tx_loadsz;
2842}
2843
1da177e4
LT		 2844static void __init
2845serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2846{
2847 int i;
2848
b8e7e40a
AC		 2849 for (i = 0; i < nr_uarts; i++) {
2850 struct uart_8250_port *up = &serial8250_ports[i];
2851 up->cur_iotype = 0xFF;
2852 }
2853
1da177e4
LT		 2854 serial8250_isa_init_ports();
2855
a61c2d78 2856 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2857 struct uart_8250_port *up = &serial8250_ports[i];
2858
2859 up->port.dev = dev;
b5d228cc
SL		 2860
2861 if (up->port.flags & UPF_FIXED_TYPE)
2862 serial8250_init_fixed_type_port(up, up->port.type);
2863
1da177e4
LT		 2864 uart_add_one_port(drv, &up->port);
2865 }
2866}
2867
2868#ifdef CONFIG_SERIAL_8250_CONSOLE
2869
d358788f
RK		 2870static void serial8250_console_putchar(struct uart_port *port, int ch)
2871{
49d5741b
JI		 2872 struct uart_8250_port *up =
2873 container_of(port, struct uart_8250_port, port);
d358788f
RK		 2874
2875 wait_for_xmitr(up, UART_LSR_THRE);
2876 serial_out(up, UART_TX, ch);
2877}
2878
1da177e4
LT		 2879/*
2880 * Print a string to the serial port trying not to disturb
2881 * any possible real use of the port...
2882 *
2883 * The console_lock must be held when we get here.
2884 */
2885static void
2886serial8250_console_write(struct console *co, const char *s, unsigned int count)
2887{
2888 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2889 unsigned long flags;
1da177e4 2890 unsigned int ier;
d8a5a8d7 2891 int locked = 1;
1da177e4 2892
78512ece
AM		 2893 touch_nmi_watchdog();
2894
68aa2c0d
AM		 2895 local_irq_save(flags);
2896 if (up->port.sysrq) {
2897 /* serial8250_handle_port() already took the lock */
2898 locked = 0;
2899 } else if (oops_in_progress) {
2900 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2901 } else
68aa2c0d 2902 spin_lock(&up->port.lock);
d8a5a8d7 2903
1da177e4 2904 /*
dc7bf130 2905 * First save the IER then disable the interrupts
1da177e4
LT		 2906 */
2907 ier = serial_in(up, UART_IER);
2908
2909 if (up->capabilities & UART_CAP_UUE)
2910 serial_out(up, UART_IER, UART_IER_UUE);
2911 else
2912 serial_out(up, UART_IER, 0);
2913
d358788f 2914 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2915
2916 /*
2917 * Finally, wait for transmitter to become empty
2918 * and restore the IER
2919 */
f91a3715 2920 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2921 serial_out(up, UART_IER, ier);
d8a5a8d7 2922
ad4c2aa6
CM		 2923 /*
2924 * The receive handling will happen properly because the
2925 * receive ready bit will still be set; it is not cleared
2926 * on read. However, modem control will not, we must
2927 * call it if we have saved something in the saved flags
2928 * while processing with interrupts off.
2929 */
2930 if (up->msr_saved_flags)
2931 check_modem_status(up);
2932
d8a5a8d7 2933 if (locked)
68aa2c0d
AM		 2934 spin_unlock(&up->port.lock);
2935 local_irq_restore(flags);
1da177e4
LT		 2936}
2937
118c0ace 2938static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2939{
2940 struct uart_port *port;
2941 int baud = 9600;
2942 int bits = 8;
2943 int parity = 'n';
2944 int flow = 'n';
2945
2946 /*
2947 * Check whether an invalid uart number has been specified, and
2948 * if so, search for the first available port that does have
2949 * console support.
2950 */
a61c2d78 2951 if (co->index >= nr_uarts)
1da177e4
LT		 2952 co->index = 0;
2953 port = &serial8250_ports[co->index].port;
2954 if (!port->iobase && !port->membase)
2955 return -ENODEV;
2956
2957 if (options)
2958 uart_parse_options(options, &baud, &parity, &bits, &flow);
2959
2960 return uart_set_options(port, co, baud, parity, bits, flow);
2961}
2962
b6b1d877 2963static int serial8250_console_early_setup(void)
18a8bd94
YL		 2964{
2965 return serial8250_find_port_for_earlycon();
2966}
2967
1da177e4
LT		 2968static struct console serial8250_console = {
2969 .name = "ttyS",
2970 .write = serial8250_console_write,
2971 .device = uart_console_device,
2972 .setup = serial8250_console_setup,
18a8bd94 2973 .early_setup = serial8250_console_early_setup,
a80c49db 2974 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2975 .index = -1,
2976 .data = &serial8250_reg,
2977};
2978
2979static int __init serial8250_console_init(void)
2980{
05d81d22
EB		 2981 if (nr_uarts > UART_NR)
2982 nr_uarts = UART_NR;
2983
1da177e4
LT		 2984 serial8250_isa_init_ports();
2985 register_console(&serial8250_console);
2986 return 0;
2987}
2988console_initcall(serial8250_console_init);
2989
18a8bd94 2990int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2991{
2992 int line;
2993 struct uart_port *port;
2994
a61c2d78 2995 for (line = 0; line < nr_uarts; line++) {
1da177e4 2996 port = &serial8250_ports[line].port;
50aec3b5 2997 if (uart_match_port(p, port))
1da177e4
LT		 2998 return line;
2999 }
3000 return -ENODEV;
3001}
3002
1da177e4
LT		 3003#define SERIAL8250_CONSOLE &serial8250_console
3004#else
3005#define SERIAL8250_CONSOLE NULL
3006#endif
3007
3008static struct uart_driver serial8250_reg = {
3009 .owner = THIS_MODULE,
3010 .driver_name = "serial",
1da177e4
LT		 3011 .dev_name = "ttyS",
3012 .major = TTY_MAJOR,
3013 .minor = 64,
1da177e4
LT		 3014 .cons = SERIAL8250_CONSOLE,
3015};
3016
d856c666
RK		 3017/*
3018 * early_serial_setup - early registration for 8250 ports
3019 *
3020 * Setup an 8250 port structure prior to console initialisation. Use
3021 * after console initialisation will cause undefined behaviour.
3022 */
1da177e4
LT		 3023int __init early_serial_setup(struct uart_port *port)
3024{
b430428a
DD		 3025 struct uart_port *p;
3026
1da177e4
LT		 3027 if (port->line >= ARRAY_SIZE(serial8250_ports))
3028 return -ENODEV;
3029
3030 serial8250_isa_init_ports();
b430428a
DD		 3031 p = &serial8250_ports[port->line].port;
3032 p->iobase = port->iobase;
3033 p->membase = port->membase;
3034 p->irq = port->irq;
1c2f0493 3035 p->irqflags = port->irqflags;
b430428a
DD		 3036 p->uartclk = port->uartclk;
3037 p->fifosize = port->fifosize;
3038 p->regshift = port->regshift;
3039 p->iotype = port->iotype;
3040 p->flags = port->flags;
3041 p->mapbase = port->mapbase;
3042 p->private_data = port->private_data;
125c97d8
HD		 3043 p->type = port->type;
3044 p->line = port->line;
7d6a07d1
DD		 3045
3046 set_io_from_upio(p);
3047 if (port->serial_in)
3048 p->serial_in = port->serial_in;
3049 if (port->serial_out)
3050 p->serial_out = port->serial_out;
3051
1da177e4
LT		 3052 return 0;
3053}
3054
3055/**
3056 * serial8250_suspend_port - suspend one serial port
3057 * @line: serial line number
1da177e4
LT		 3058 *
3059 * Suspend one serial port.
3060 */
3061void serial8250_suspend_port(int line)
3062{
3063 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3064}
3065
3066/**
3067 * serial8250_resume_port - resume one serial port
3068 * @line: serial line number
1da177e4
LT		 3069 *
3070 * Resume one serial port.
3071 */
3072void serial8250_resume_port(int line)
3073{
b5b82df6
DW		 3074 struct uart_8250_port *up = &serial8250_ports[line];
3075
3076 if (up->capabilities & UART_NATSEMI) {
b5b82df6
DW		 3077 /* Ensure it's still in high speed mode */
3078 serial_outp(up, UART_LCR, 0xE0);
3079
0d0389e5 3080 ns16550a_goto_highspeed(up);
b5b82df6
DW		 3081
3082 serial_outp(up, UART_LCR, 0);
95926d2d 3083 up->port.uartclk = 921600*16;
b5b82df6
DW		 3084 }
3085 uart_resume_port(&serial8250_reg, &up->port);
1da177e4
LT		 3086}
3087
3088/*
3089 * Register a set of serial devices attached to a platform device. The
3090 * list is terminated with a zero flags entry, which means we expect
3091 * all entries to have at least UPF_BOOT_AUTOCONF set.
3092 */
3ae5eaec 3093static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 3094{
3ae5eaec 3095 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 3096 struct uart_port port;
4c0ebb80 3097 int ret, i, irqflag = 0;
1da177e4
LT		 3098
3099 memset(&port, 0, sizeof(struct uart_port));
3100
4c0ebb80
AGR		 3101 if (share_irqs)
3102 irqflag = IRQF_SHARED;
3103
ec9f47cd 3104 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 3105 port.iobase = p->iobase;
3106 port.membase = p->membase;
3107 port.irq = p->irq;
1c2f0493 3108 port.irqflags = p->irqflags;
74a19741
WN		 3109 port.uartclk = p->uartclk;
3110 port.regshift = p->regshift;
3111 port.iotype = p->iotype;
3112 port.flags = p->flags;
3113 port.mapbase = p->mapbase;
3114 port.hub6 = p->hub6;
3115 port.private_data = p->private_data;
8e23fcc8 3116 port.type = p->type;
7d6a07d1
DD		 3117 port.serial_in = p->serial_in;
3118 port.serial_out = p->serial_out;
235dae5d 3119 port.set_termios = p->set_termios;
c161afe9 3120 port.pm = p->pm;
74a19741 3121 port.dev = &dev->dev;
4c0ebb80 3122 port.irqflags |= irqflag;
ec9f47cd
RK		 3123 ret = serial8250_register_port(&port);
3124 if (ret < 0) {
3ae5eaec 3125 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 3126 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3127 p->iobase, (unsigned long long)p->mapbase,
3128 p->irq, ret);
ec9f47cd 3129 }
1da177e4
LT		 3130 }
3131 return 0;
3132}
3133
3134/*
3135 * Remove serial ports registered against a platform device.
3136 */
3ae5eaec 3137static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 3138{
3139 int i;
3140
a61c2d78 3141 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 3142 struct uart_8250_port *up = &serial8250_ports[i];
3143
3ae5eaec 3144 if (up->port.dev == &dev->dev)
1da177e4
LT		 3145 serial8250_unregister_port(i);
3146 }
3147 return 0;
3148}
3149
3ae5eaec 3150static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 3151{
3152 int i;
3153
1da177e4
LT		 3154 for (i = 0; i < UART_NR; i++) {
3155 struct uart_8250_port *up = &serial8250_ports[i];
3156
3ae5eaec 3157 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3158 uart_suspend_port(&serial8250_reg, &up->port);
3159 }
3160
3161 return 0;
3162}
3163
3ae5eaec 3164static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3165{
3166 int i;
3167
1da177e4
LT		 3168 for (i = 0; i < UART_NR; i++) {
3169 struct uart_8250_port *up = &serial8250_ports[i];
3170
3ae5eaec 3171 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3172 serial8250_resume_port(i);
1da177e4
LT		 3173 }
3174
3175 return 0;
3176}
3177
3ae5eaec 3178static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 3179 .probe = serial8250_probe,
3180 .remove = __devexit_p(serial8250_remove),
3181 .suspend = serial8250_suspend,
3182 .resume = serial8250_resume,
3ae5eaec
RK		 3183 .driver = {
3184 .name = "serial8250",
7493a314 3185 .owner = THIS_MODULE,
3ae5eaec 3186 },
1da177e4
LT		 3187};
3188
3189/*
3190 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3191 * in the table in include/asm/serial.h
3192 */
3193static struct platform_device *serial8250_isa_devs;
3194
3195/*
3196 * serial8250_register_port and serial8250_unregister_port allows for
3197 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3198 * modems and PCI multiport cards.
3199 */
f392ecfa 3200static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3201
3202static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3203{
3204 int i;
3205
3206 /*
3207 * First, find a port entry which matches.
3208 */
a61c2d78 3209 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3210 if (uart_match_port(&serial8250_ports[i].port, port))
3211 return &serial8250_ports[i];
3212
3213 /*
3214 * We didn't find a matching entry, so look for the first
3215 * free entry. We look for one which hasn't been previously
3216 * used (indicated by zero iobase).
3217 */
a61c2d78 3218 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3219 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3220 serial8250_ports[i].port.iobase == 0)
3221 return &serial8250_ports[i];
3222
3223 /*
3224 * That also failed. Last resort is to find any entry which
3225 * doesn't have a real port associated with it.
3226 */
a61c2d78 3227 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3228 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3229 return &serial8250_ports[i];
3230
3231 return NULL;
3232}
3233
3234/**
3235 * serial8250_register_port - register a serial port
3236 * @port: serial port template
3237 *
3238 * Configure the serial port specified by the request. If the
3239 * port exists and is in use, it is hung up and unregistered
3240 * first.
3241 *
3242 * The port is then probed and if necessary the IRQ is autodetected
3243 * If this fails an error is returned.
3244 *
3245 * On success the port is ready to use and the line number is returned.
3246 */
3247int serial8250_register_port(struct uart_port *port)
3248{
3249 struct uart_8250_port *uart;
3250 int ret = -ENOSPC;
3251
3252 if (port->uartclk == 0)
3253 return -EINVAL;
3254
f392ecfa 3255 mutex_lock(&serial_mutex);
1da177e4
LT		 3256
3257 uart = serial8250_find_match_or_unused(port);
3258 if (uart) {
3259 uart_remove_one_port(&serial8250_reg, &uart->port);
3260
74a19741
WN		 3261 uart->port.iobase = port->iobase;
3262 uart->port.membase = port->membase;
3263 uart->port.irq = port->irq;
1c2f0493 3264 uart->port.irqflags = port->irqflags;
74a19741
WN		 3265 uart->port.uartclk = port->uartclk;
3266 uart->port.fifosize = port->fifosize;
3267 uart->port.regshift = port->regshift;
3268 uart->port.iotype = port->iotype;
3269 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3270 uart->port.mapbase = port->mapbase;
3271 uart->port.private_data = port->private_data;
1da177e4
LT		 3272 if (port->dev)
3273 uart->port.dev = port->dev;
8e23fcc8 3274
b5d228cc
SL		 3275 if (port->flags & UPF_FIXED_TYPE)
3276 serial8250_init_fixed_type_port(uart, port->type);
8e23fcc8 3277
7d6a07d1
DD		 3278 set_io_from_upio(&uart->port);
3279 /* Possibly override default I/O functions. */
3280 if (port->serial_in)
3281 uart->port.serial_in = port->serial_in;
3282 if (port->serial_out)
3283 uart->port.serial_out = port->serial_out;
235dae5d
PL		 3284 /* Possibly override set_termios call */
3285 if (port->set_termios)
3286 uart->port.set_termios = port->set_termios;
c161afe9
ML		 3287 if (port->pm)
3288 uart->port.pm = port->pm;
1da177e4 3289
af7f3743
AC		 3290 if (serial8250_isa_config != NULL)
3291 serial8250_isa_config(0, &uart->port,
3292 &uart->capabilities);
3293
1da177e4
LT		 3294 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3295 if (ret == 0)
3296 ret = uart->port.line;
3297 }
f392ecfa 3298 mutex_unlock(&serial_mutex);
1da177e4
LT		 3299
3300 return ret;
3301}
3302EXPORT_SYMBOL(serial8250_register_port);
3303
3304/**
3305 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3306 * @line: serial line number
3307 *
3308 * Remove one serial port. This may not be called from interrupt
3309 * context. We hand the port back to the our control.
3310 */
3311void serial8250_unregister_port(int line)
3312{
3313 struct uart_8250_port *uart = &serial8250_ports[line];
3314
f392ecfa 3315 mutex_lock(&serial_mutex);
1da177e4
LT		 3316 uart_remove_one_port(&serial8250_reg, &uart->port);
3317 if (serial8250_isa_devs) {
3318 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3319 uart->port.type = PORT_UNKNOWN;
3320 uart->port.dev = &serial8250_isa_devs->dev;
3321 uart_add_one_port(&serial8250_reg, &uart->port);
3322 } else {
3323 uart->port.dev = NULL;
3324 }
f392ecfa 3325 mutex_unlock(&serial_mutex);
1da177e4
LT		 3326}
3327EXPORT_SYMBOL(serial8250_unregister_port);
3328
3329static int __init serial8250_init(void)
3330{
25db8ad5 3331 int ret;
1da177e4 3332
a61c2d78
DJ		 3333 if (nr_uarts > UART_NR)
3334 nr_uarts = UART_NR;
3335
f1fb9bb8 3336 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3337 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3338 share_irqs ? "en" : "dis");
3339
b70ac771
DM		 3340#ifdef CONFIG_SPARC
3341 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3342#else
3343 serial8250_reg.nr = UART_NR;
1da177e4 3344 ret = uart_register_driver(&serial8250_reg);
b70ac771 3345#endif
1da177e4
LT		 3346 if (ret)
3347 goto out;
3348
7493a314
DT		 3349 serial8250_isa_devs = platform_device_alloc("serial8250",
3350 PLAT8250_DEV_LEGACY);
3351 if (!serial8250_isa_devs) {
3352 ret = -ENOMEM;
bc965a7f 3353 goto unreg_uart_drv;
1da177e4
LT		 3354 }
3355
7493a314
DT		 3356 ret = platform_device_add(serial8250_isa_devs);
3357 if (ret)
3358 goto put_dev;
3359
1da177e4
LT		 3360 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3361
bc965a7f
RK		 3362 ret = platform_driver_register(&serial8250_isa_driver);
3363 if (ret == 0)
3364 goto out;
1da177e4 3365
bc965a7f 3366 platform_device_del(serial8250_isa_devs);
25db8ad5 3367put_dev:
7493a314 3368 platform_device_put(serial8250_isa_devs);
25db8ad5 3369unreg_uart_drv:
b70ac771
DM		 3370#ifdef CONFIG_SPARC
3371 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3372#else
1da177e4 3373 uart_unregister_driver(&serial8250_reg);
b70ac771 3374#endif
25db8ad5 3375out:
1da177e4
LT		 3376 return ret;
3377}
3378
3379static void __exit serial8250_exit(void)
3380{
3381 struct platform_device *isa_dev = serial8250_isa_devs;
3382
3383 /*
3384 * This tells serial8250_unregister_port() not to re-register
3385 * the ports (thereby making serial8250_isa_driver permanently
3386 * in use.)
3387 */
3388 serial8250_isa_devs = NULL;
3389
3ae5eaec 3390 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3391 platform_device_unregister(isa_dev);
3392
b70ac771
DM		 3393#ifdef CONFIG_SPARC
3394 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3395#else
1da177e4 3396 uart_unregister_driver(&serial8250_reg);
b70ac771 3397#endif
1da177e4
LT		 3398}
3399
3400module_init(serial8250_init);
3401module_exit(serial8250_exit);
3402
3403EXPORT_SYMBOL(serial8250_suspend_port);
3404EXPORT_SYMBOL(serial8250_resume_port);
3405
3406MODULE_LICENSE("GPL");
d87a6d95 3407MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3408
3409module_param(share_irqs, uint, 0644);
3410MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3411 " (unsafe)");
3412
a61c2d78
DJ		 3413module_param(nr_uarts, uint, 0644);
3414MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3415
d41a4b51
CE		 3416module_param(skip_txen_test, uint, 0644);
3417MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3418
1da177e4
LT		 3419#ifdef CONFIG_SERIAL_8250_RSA
3420module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3421MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3422#endif
3423MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux kernel - Deliverables
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