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Merge branch 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / tty / serial / 8250.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
1da177e4
LT		 15 * A note about mapbase / membase
16 *
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
19 */
1da177e4
LT		 20
21#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
24
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/ioport.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
1da177e4 31#include <linux/delay.h>
d052d1be 32#include <linux/platform_device.h>
1da177e4 33#include <linux/tty.h>
cd3ecad1 34#include <linux/ratelimit.h>
1da177e4
LT		 35#include <linux/tty_flip.h>
36#include <linux/serial_reg.h>
37#include <linux/serial_core.h>
38#include <linux/serial.h>
39#include <linux/serial_8250.h>
78512ece 40#include <linux/nmi.h>
f392ecfa 41#include <linux/mutex.h>
5a0e3ad6 42#include <linux/slab.h>
1da177e4
LT		 43
44#include <asm/io.h>
45#include <asm/irq.h>
46
47#include "8250.h"
48
b70ac771
DM		 49#ifdef CONFIG_SPARC
50#include "suncore.h"
51#endif
52
1da177e4
LT		 53/*
54 * Configuration:
40663cc7 55 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 56 * is unsafe when used on edge-triggered interrupts.
57 */
408b664a 58static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 59
a61c2d78
DJ		 60static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
61
8440838b
DM		 62static struct uart_driver serial8250_reg;
63
64static int serial_index(struct uart_port *port)
65{
66 return (serial8250_reg.minor - 64) + port->line;
67}
68
d41a4b51
CE		 69static unsigned int skip_txen_test; /* force skip of txen test at init time */
70
1da177e4
LT		 71/*
72 * Debugging.
73 */
74#if 0
75#define DEBUG_AUTOCONF(fmt...) printk(fmt)
76#else
77#define DEBUG_AUTOCONF(fmt...) do { } while (0)
78#endif
79
80#if 0
81#define DEBUG_INTR(fmt...) printk(fmt)
82#else
83#define DEBUG_INTR(fmt...) do { } while (0)
84#endif
85
86#define PASS_LIMIT 256
87
bca47613
DH		 88#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
89
90
1da177e4
LT		 91/*
92 * We default to IRQ0 for the "no irq" hack. Some
93 * machine types want others as well - they're free
94 * to redefine this in their header file.
95 */
96#define is_real_interrupt(irq) ((irq) != 0)
97
1da177e4
LT		 98#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
99#define CONFIG_SERIAL_DETECT_IRQ 1
100#endif
1da177e4
LT		 101#ifdef CONFIG_SERIAL_8250_MANY_PORTS
102#define CONFIG_SERIAL_MANY_PORTS 1
103#endif
104
105/*
106 * HUB6 is always on. This will be removed once the header
107 * files have been cleaned.
108 */
109#define CONFIG_HUB6 1
110
a4ed1e41 111#include <asm/serial.h>
1da177e4
LT		 112/*
113 * SERIAL_PORT_DFNS tells us about built-in ports that have no
114 * standard enumeration mechanism. Platforms that can find all
115 * serial ports via mechanisms like ACPI or PCI need not supply it.
116 */
117#ifndef SERIAL_PORT_DFNS
118#define SERIAL_PORT_DFNS
119#endif
120
cb3592be 121static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 122 SERIAL_PORT_DFNS /* defined in asm/serial.h */
123};
124
026d02a2 125#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 126
127#ifdef CONFIG_SERIAL_8250_RSA
128
129#define PORT_RSA_MAX 4
130static unsigned long probe_rsa[PORT_RSA_MAX];
131static unsigned int probe_rsa_count;
132#endif /* CONFIG_SERIAL_8250_RSA */
133
134struct uart_8250_port {
135 struct uart_port port;
136 struct timer_list timer; /* "no irq" timer */
137 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 138 unsigned short capabilities; /* port capabilities */
139 unsigned short bugs; /* port bugs */
1da177e4 140 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 141 unsigned char acr;
142 unsigned char ier;
143 unsigned char lcr;
144 unsigned char mcr;
145 unsigned char mcr_mask; /* mask of user bits */
146 unsigned char mcr_force; /* mask of forced bits */
b8e7e40a 147 unsigned char cur_iotype; /* Running I/O type */
ad4c2aa6
CM		 148
149 /*
150 * Some bits in registers are cleared on a read, so they must
151 * be saved whenever the register is read but the bits will not
152 * be immediately processed.
153 */
154#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
155 unsigned char lsr_saved_flags;
156#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
157 unsigned char msr_saved_flags;
1da177e4
LT		 158};
159
160struct irq_info {
25db8ad5
AC		 161 struct hlist_node node;
162 int irq;
163 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 164 struct list_head *head;
165};
166
25db8ad5
AC		 167#define NR_IRQ_HASH 32 /* Can be adjusted later */
168static struct hlist_head irq_lists[NR_IRQ_HASH];
169static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 170
171/*
172 * Here we define the default xmit fifo size used for each type of UART.
173 */
174static const struct serial8250_config uart_config[] = {
175 [PORT_UNKNOWN] = {
176 .name = "unknown",
177 .fifo_size = 1,
178 .tx_loadsz = 1,
179 },
180 [PORT_8250] = {
181 .name = "8250",
182 .fifo_size = 1,
183 .tx_loadsz = 1,
184 },
185 [PORT_16450] = {
186 .name = "16450",
187 .fifo_size = 1,
188 .tx_loadsz = 1,
189 },
190 [PORT_16550] = {
191 .name = "16550",
192 .fifo_size = 1,
193 .tx_loadsz = 1,
194 },
195 [PORT_16550A] = {
196 .name = "16550A",
197 .fifo_size = 16,
198 .tx_loadsz = 16,
199 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
200 .flags = UART_CAP_FIFO,
201 },
202 [PORT_CIRRUS] = {
203 .name = "Cirrus",
204 .fifo_size = 1,
205 .tx_loadsz = 1,
206 },
207 [PORT_16650] = {
208 .name = "ST16650",
209 .fifo_size = 1,
210 .tx_loadsz = 1,
211 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
212 },
213 [PORT_16650V2] = {
214 .name = "ST16650V2",
215 .fifo_size = 32,
216 .tx_loadsz = 16,
217 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
218 UART_FCR_T_TRIG_00,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220 },
221 [PORT_16750] = {
222 .name = "TI16750",
223 .fifo_size = 64,
224 .tx_loadsz = 64,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
226 UART_FCR7_64BYTE,
227 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
228 },
229 [PORT_STARTECH] = {
230 .name = "Startech",
231 .fifo_size = 1,
232 .tx_loadsz = 1,
233 },
234 [PORT_16C950] = {
235 .name = "16C950/954",
236 .fifo_size = 128,
237 .tx_loadsz = 128,
238 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
d0694e2a
PM		 239 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
240 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
1da177e4
LT		 241 },
242 [PORT_16654] = {
243 .name = "ST16654",
244 .fifo_size = 64,
245 .tx_loadsz = 32,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
247 UART_FCR_T_TRIG_10,
248 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
249 },
250 [PORT_16850] = {
251 .name = "XR16850",
252 .fifo_size = 128,
253 .tx_loadsz = 128,
254 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
255 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
256 },
257 [PORT_RSA] = {
258 .name = "RSA",
259 .fifo_size = 2048,
260 .tx_loadsz = 2048,
261 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
262 .flags = UART_CAP_FIFO,
263 },
264 [PORT_NS16550A] = {
265 .name = "NS16550A",
266 .fifo_size = 16,
267 .tx_loadsz = 16,
268 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
269 .flags = UART_CAP_FIFO | UART_NATSEMI,
270 },
271 [PORT_XSCALE] = {
272 .name = "XScale",
273 .fifo_size = 32,
274 .tx_loadsz = 32,
275 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
276 .flags = UART_CAP_FIFO | UART_CAP_UUE,
277 },
bd71c182
TK		 278 [PORT_RM9000] = {
279 .name = "RM9000",
280 .fifo_size = 16,
281 .tx_loadsz = 16,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 283 .flags = UART_CAP_FIFO,
284 },
285 [PORT_OCTEON] = {
286 .name = "OCTEON",
287 .fifo_size = 64,
288 .tx_loadsz = 64,
289 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 290 .flags = UART_CAP_FIFO,
291 },
08e0992f
FF		 292 [PORT_AR7] = {
293 .name = "AR7",
294 .fifo_size = 16,
295 .tx_loadsz = 16,
296 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
297 .flags = UART_CAP_FIFO | UART_CAP_AFE,
298 },
235dae5d
PL		 299 [PORT_U6_16550A] = {
300 .name = "U6_16550A",
301 .fifo_size = 64,
302 .tx_loadsz = 64,
303 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
304 .flags = UART_CAP_FIFO | UART_CAP_AFE,
305 },
1da177e4
LT		 306};
307
12bf3f24 308#if defined(CONFIG_MIPS_ALCHEMY)
21c614a7
PA		 309
310/* Au1x00 UART hardware has a weird register layout */
311static const u8 au_io_in_map[] = {
312 [UART_RX] = 0,
313 [UART_IER] = 2,
314 [UART_IIR] = 3,
315 [UART_LCR] = 5,
316 [UART_MCR] = 6,
317 [UART_LSR] = 7,
318 [UART_MSR] = 8,
319};
320
321static const u8 au_io_out_map[] = {
322 [UART_TX] = 1,
323 [UART_IER] = 2,
324 [UART_FCR] = 4,
325 [UART_LCR] = 5,
326 [UART_MCR] = 6,
327};
328
329/* sane hardware needs no mapping */
7d6a07d1 330static inline int map_8250_in_reg(struct uart_port *p, int offset)
21c614a7 331{
7d6a07d1 332 if (p->iotype != UPIO_AU)
21c614a7
PA		 333 return offset;
334 return au_io_in_map[offset];
335}
336
7d6a07d1 337static inline int map_8250_out_reg(struct uart_port *p, int offset)
21c614a7 338{
7d6a07d1 339 if (p->iotype != UPIO_AU)
21c614a7
PA		 340 return offset;
341 return au_io_out_map[offset];
342}
343
6f803cd0 344#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 345
346static const u8
347 regmap_in[8] = {
348 [UART_RX] = 0x00,
349 [UART_IER] = 0x0c,
350 [UART_IIR] = 0x14,
351 [UART_LCR] = 0x1c,
352 [UART_MCR] = 0x20,
353 [UART_LSR] = 0x24,
354 [UART_MSR] = 0x28,
355 [UART_SCR] = 0x2c
356 },
357 regmap_out[8] = {
358 [UART_TX] = 0x04,
359 [UART_IER] = 0x0c,
360 [UART_FCR] = 0x18,
361 [UART_LCR] = 0x1c,
362 [UART_MCR] = 0x20,
363 [UART_LSR] = 0x24,
364 [UART_MSR] = 0x28,
365 [UART_SCR] = 0x2c
366 };
367
7d6a07d1 368static inline int map_8250_in_reg(struct uart_port *p, int offset)
bd71c182 369{
7d6a07d1 370 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 371 return offset;
372 return regmap_in[offset];
373}
374
7d6a07d1 375static inline int map_8250_out_reg(struct uart_port *p, int offset)
bd71c182 376{
7d6a07d1 377 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 378 return offset;
379 return regmap_out[offset];
380}
381
21c614a7
PA		 382#else
383
384/* sane hardware needs no mapping */
385#define map_8250_in_reg(up, offset) (offset)
386#define map_8250_out_reg(up, offset) (offset)
387
388#endif
389
7d6a07d1 390static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 391{
7d6a07d1
DD		 392 offset = map_8250_in_reg(p, offset) << p->regshift;
393 outb(p->hub6 - 1 + offset, p->iobase);
394 return inb(p->iobase + 1);
395}
1da177e4 396
7d6a07d1
DD		 397static void hub6_serial_out(struct uart_port *p, int offset, int value)
398{
399 offset = map_8250_out_reg(p, offset) << p->regshift;
400 outb(p->hub6 - 1 + offset, p->iobase);
401 outb(value, p->iobase + 1);
402}
1da177e4 403
7d6a07d1
DD		 404static unsigned int mem_serial_in(struct uart_port *p, int offset)
405{
406 offset = map_8250_in_reg(p, offset) << p->regshift;
407 return readb(p->membase + offset);
408}
1da177e4 409
7d6a07d1
DD		 410static void mem_serial_out(struct uart_port *p, int offset, int value)
411{
412 offset = map_8250_out_reg(p, offset) << p->regshift;
413 writeb(value, p->membase + offset);
414}
415
416static void mem32_serial_out(struct uart_port *p, int offset, int value)
417{
418 offset = map_8250_out_reg(p, offset) << p->regshift;
419 writel(value, p->membase + offset);
420}
421
422static unsigned int mem32_serial_in(struct uart_port *p, int offset)
423{
424 offset = map_8250_in_reg(p, offset) << p->regshift;
425 return readl(p->membase + offset);
426}
1da177e4 427
7d6a07d1
DD		 428static unsigned int au_serial_in(struct uart_port *p, int offset)
429{
430 offset = map_8250_in_reg(p, offset) << p->regshift;
431 return __raw_readl(p->membase + offset);
432}
433
434static void au_serial_out(struct uart_port *p, int offset, int value)
435{
436 offset = map_8250_out_reg(p, offset) << p->regshift;
437 __raw_writel(value, p->membase + offset);
438}
21c614a7 439
7d6a07d1
DD		 440static unsigned int tsi_serial_in(struct uart_port *p, int offset)
441{
442 unsigned int tmp;
443 offset = map_8250_in_reg(p, offset) << p->regshift;
444 if (offset == UART_IIR) {
445 tmp = readl(p->membase + (UART_IIR & ~3));
446 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
447 } else
448 return readb(p->membase + offset);
449}
3be91ec7 450
7d6a07d1
DD		 451static void tsi_serial_out(struct uart_port *p, int offset, int value)
452{
453 offset = map_8250_out_reg(p, offset) << p->regshift;
454 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
455 writeb(value, p->membase + offset);
1da177e4
LT		 456}
457
a3ae0fc3
JI		 458/* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */
459static inline void dwapb_save_out_value(struct uart_port *p, int offset,
460 int value)
461{
462 struct uart_8250_port *up =
463 container_of(p, struct uart_8250_port, port);
464
465 if (offset == UART_LCR)
466 up->lcr = value;
467}
468
469/* Read the IER to ensure any interrupt is cleared before returning from ISR. */
470static inline void dwapb_check_clear_ier(struct uart_port *p, int offset)
471{
472 if (offset == UART_TX || offset == UART_IER)
473 p->serial_in(p, UART_IER);
474}
475
7d6a07d1 476static void dwapb_serial_out(struct uart_port *p, int offset, int value)
1da177e4 477{
beab697a 478 int save_offset = offset;
7d6a07d1 479 offset = map_8250_out_reg(p, offset) << p->regshift;
a3ae0fc3 480 dwapb_save_out_value(p, save_offset, value);
7d6a07d1 481 writeb(value, p->membase + offset);
a3ae0fc3
JI		 482 dwapb_check_clear_ier(p, save_offset);
483}
484
485static void dwapb32_serial_out(struct uart_port *p, int offset, int value)
486{
487 int save_offset = offset;
488 offset = map_8250_out_reg(p, offset) << p->regshift;
489 dwapb_save_out_value(p, save_offset, value);
490 writel(value, p->membase + offset);
491 dwapb_check_clear_ier(p, save_offset);
7d6a07d1 492}
1da177e4 493
7d6a07d1
DD		 494static unsigned int io_serial_in(struct uart_port *p, int offset)
495{
496 offset = map_8250_in_reg(p, offset) << p->regshift;
497 return inb(p->iobase + offset);
498}
499
500static void io_serial_out(struct uart_port *p, int offset, int value)
501{
502 offset = map_8250_out_reg(p, offset) << p->regshift;
503 outb(value, p->iobase + offset);
504}
505
506static void set_io_from_upio(struct uart_port *p)
507{
49d5741b
JI		 508 struct uart_8250_port *up =
509 container_of(p, struct uart_8250_port, port);
7d6a07d1 510 switch (p->iotype) {
1da177e4 511 case UPIO_HUB6:
7d6a07d1
DD		 512 p->serial_in = hub6_serial_in;
513 p->serial_out = hub6_serial_out;
1da177e4
LT		 514 break;
515
516 case UPIO_MEM:
7d6a07d1
DD		 517 p->serial_in = mem_serial_in;
518 p->serial_out = mem_serial_out;
1da177e4
LT		 519 break;
520
bd71c182 521 case UPIO_RM9000:
1da177e4 522 case UPIO_MEM32:
7d6a07d1
DD		 523 p->serial_in = mem32_serial_in;
524 p->serial_out = mem32_serial_out;
1da177e4
LT		 525 break;
526
21c614a7 527 case UPIO_AU:
7d6a07d1
DD		 528 p->serial_in = au_serial_in;
529 p->serial_out = au_serial_out;
21c614a7 530 break;
12bf3f24 531
3be91ec7 532 case UPIO_TSI:
7d6a07d1
DD		 533 p->serial_in = tsi_serial_in;
534 p->serial_out = tsi_serial_out;
3be91ec7 535 break;
21c614a7 536
beab697a 537 case UPIO_DWAPB:
7d6a07d1
DD		 538 p->serial_in = mem_serial_in;
539 p->serial_out = dwapb_serial_out;
beab697a
MSJ		 540 break;
541
a3ae0fc3
JI		 542 case UPIO_DWAPB32:
543 p->serial_in = mem32_serial_in;
544 p->serial_out = dwapb32_serial_out;
545 break;
546
1da177e4 547 default:
7d6a07d1
DD		 548 p->serial_in = io_serial_in;
549 p->serial_out = io_serial_out;
550 break;
1da177e4 551 }
b8e7e40a
AC		 552 /* Remember loaded iotype */
553 up->cur_iotype = p->iotype;
1da177e4
LT		 554}
555
40b36daa
AW		 556static void
557serial_out_sync(struct uart_8250_port *up, int offset, int value)
558{
7d6a07d1
DD		 559 struct uart_port *p = &up->port;
560 switch (p->iotype) {
40b36daa
AW		 561 case UPIO_MEM:
562 case UPIO_MEM32:
40b36daa 563 case UPIO_AU:
beab697a 564 case UPIO_DWAPB:
a3ae0fc3 565 case UPIO_DWAPB32:
7d6a07d1
DD		 566 p->serial_out(p, offset, value);
567 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 568 break;
569 default:
7d6a07d1 570 p->serial_out(p, offset, value);
40b36daa
AW		 571 }
572}
573
7d6a07d1
DD		 574#define serial_in(up, offset) \
575 (up->port.serial_in(&(up)->port, (offset)))
576#define serial_out(up, offset, value) \
577 (up->port.serial_out(&(up)->port, (offset), (value)))
1da177e4
LT		 578/*
579 * We used to support using pause I/O for certain machines. We
580 * haven't supported this for a while, but just in case it's badly
581 * needed for certain old 386 machines, I've left these #define's
582 * in....
583 */
584#define serial_inp(up, offset) serial_in(up, offset)
585#define serial_outp(up, offset, value) serial_out(up, offset, value)
586
b32b19b8
JAH		 587/* Uart divisor latch read */
588static inline int _serial_dl_read(struct uart_8250_port *up)
589{
590 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
591}
592
593/* Uart divisor latch write */
594static inline void _serial_dl_write(struct uart_8250_port *up, int value)
595{
596 serial_outp(up, UART_DLL, value & 0xff);
597 serial_outp(up, UART_DLM, value >> 8 & 0xff);
598}
599
12bf3f24 600#if defined(CONFIG_MIPS_ALCHEMY)
b32b19b8
JAH		 601/* Au1x00 haven't got a standard divisor latch */
602static int serial_dl_read(struct uart_8250_port *up)
603{
604 if (up->port.iotype == UPIO_AU)
605 return __raw_readl(up->port.membase + 0x28);
606 else
607 return _serial_dl_read(up);
608}
609
610static void serial_dl_write(struct uart_8250_port *up, int value)
611{
612 if (up->port.iotype == UPIO_AU)
613 __raw_writel(value, up->port.membase + 0x28);
614 else
615 _serial_dl_write(up, value);
616}
6f803cd0 617#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 618static int serial_dl_read(struct uart_8250_port *up)
619{
620 return (up->port.iotype == UPIO_RM9000) ?
621 (((__raw_readl(up->port.membase + 0x10) << 8) |
622 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
623 _serial_dl_read(up);
624}
625
626static void serial_dl_write(struct uart_8250_port *up, int value)
627{
628 if (up->port.iotype == UPIO_RM9000) {
629 __raw_writel(value, up->port.membase + 0x08);
630 __raw_writel(value >> 8, up->port.membase + 0x10);
631 } else {
632 _serial_dl_write(up, value);
633 }
634}
b32b19b8
JAH		 635#else
636#define serial_dl_read(up) _serial_dl_read(up)
637#define serial_dl_write(up, value) _serial_dl_write(up, value)
638#endif
1da177e4
LT		 639
640/*
641 * For the 16C950
642 */
643static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
644{
645 serial_out(up, UART_SCR, offset);
646 serial_out(up, UART_ICR, value);
647}
648
649static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
650{
651 unsigned int value;
652
653 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
654 serial_out(up, UART_SCR, offset);
655 value = serial_in(up, UART_ICR);
656 serial_icr_write(up, UART_ACR, up->acr);
657
658 return value;
659}
660
661/*
662 * FIFO support.
663 */
b5d674ab 664static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 665{
666 if (p->capabilities & UART_CAP_FIFO) {
667 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
668 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
669 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
670 serial_outp(p, UART_FCR, 0);
671 }
672}
673
674/*
675 * IER sleep support. UARTs which have EFRs need the "extended
676 * capability" bit enabled. Note that on XR16C850s, we need to
677 * reset LCR to write to IER.
678 */
b5d674ab 679static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4
LT		 680{
681 if (p->capabilities & UART_CAP_SLEEP) {
682 if (p->capabilities & UART_CAP_EFR) {
662b083a 683 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 684 serial_outp(p, UART_EFR, UART_EFR_ECB);
685 serial_outp(p, UART_LCR, 0);
686 }
687 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
688 if (p->capabilities & UART_CAP_EFR) {
662b083a 689 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 690 serial_outp(p, UART_EFR, 0);
691 serial_outp(p, UART_LCR, 0);
692 }
693 }
694}
695
696#ifdef CONFIG_SERIAL_8250_RSA
697/*
698 * Attempts to turn on the RSA FIFO. Returns zero on failure.
699 * We set the port uart clock rate if we succeed.
700 */
701static int __enable_rsa(struct uart_8250_port *up)
702{
703 unsigned char mode;
704 int result;
705
706 mode = serial_inp(up, UART_RSA_MSR);
707 result = mode & UART_RSA_MSR_FIFO;
708
709 if (!result) {
710 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
711 mode = serial_inp(up, UART_RSA_MSR);
712 result = mode & UART_RSA_MSR_FIFO;
713 }
714
715 if (result)
716 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
717
718 return result;
719}
720
721static void enable_rsa(struct uart_8250_port *up)
722{
723 if (up->port.type == PORT_RSA) {
724 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
725 spin_lock_irq(&up->port.lock);
726 __enable_rsa(up);
727 spin_unlock_irq(&up->port.lock);
728 }
729 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
730 serial_outp(up, UART_RSA_FRR, 0);
731 }
732}
733
734/*
735 * Attempts to turn off the RSA FIFO. Returns zero on failure.
736 * It is unknown why interrupts were disabled in here. However,
737 * the caller is expected to preserve this behaviour by grabbing
738 * the spinlock before calling this function.
739 */
740static void disable_rsa(struct uart_8250_port *up)
741{
742 unsigned char mode;
743 int result;
744
745 if (up->port.type == PORT_RSA &&
746 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
747 spin_lock_irq(&up->port.lock);
748
749 mode = serial_inp(up, UART_RSA_MSR);
750 result = !(mode & UART_RSA_MSR_FIFO);
751
752 if (!result) {
753 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
754 mode = serial_inp(up, UART_RSA_MSR);
755 result = !(mode & UART_RSA_MSR_FIFO);
756 }
757
758 if (result)
759 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
760 spin_unlock_irq(&up->port.lock);
761 }
762}
763#endif /* CONFIG_SERIAL_8250_RSA */
764
765/*
766 * This is a quickie test to see how big the FIFO is.
767 * It doesn't work at all the time, more's the pity.
768 */
769static int size_fifo(struct uart_8250_port *up)
770{
b32b19b8
JAH		 771 unsigned char old_fcr, old_mcr, old_lcr;
772 unsigned short old_dl;
1da177e4
LT		 773 int count;
774
775 old_lcr = serial_inp(up, UART_LCR);
776 serial_outp(up, UART_LCR, 0);
777 old_fcr = serial_inp(up, UART_FCR);
778 old_mcr = serial_inp(up, UART_MCR);
779 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
780 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
781 serial_outp(up, UART_MCR, UART_MCR_LOOP);
662b083a 782 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8
JAH		 783 old_dl = serial_dl_read(up);
784 serial_dl_write(up, 0x0001);
1da177e4
LT		 785 serial_outp(up, UART_LCR, 0x03);
786 for (count = 0; count < 256; count++)
787 serial_outp(up, UART_TX, count);
788 mdelay(20);/* FIXME - schedule_timeout */
789 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
790 (count < 256); count++)
791 serial_inp(up, UART_RX);
792 serial_outp(up, UART_FCR, old_fcr);
793 serial_outp(up, UART_MCR, old_mcr);
662b083a 794 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8 795 serial_dl_write(up, old_dl);
1da177e4
LT		 796 serial_outp(up, UART_LCR, old_lcr);
797
798 return count;
799}
800
801/*
802 * Read UART ID using the divisor method - set DLL and DLM to zero
803 * and the revision will be in DLL and device type in DLM. We
804 * preserve the device state across this.
805 */
806static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
807{
808 unsigned char old_dll, old_dlm, old_lcr;
809 unsigned int id;
810
811 old_lcr = serial_inp(p, UART_LCR);
662b083a 812 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 813
814 old_dll = serial_inp(p, UART_DLL);
815 old_dlm = serial_inp(p, UART_DLM);
816
817 serial_outp(p, UART_DLL, 0);
818 serial_outp(p, UART_DLM, 0);
819
820 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
821
822 serial_outp(p, UART_DLL, old_dll);
823 serial_outp(p, UART_DLM, old_dlm);
824 serial_outp(p, UART_LCR, old_lcr);
825
826 return id;
827}
828
829/*
830 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
831 * When this function is called we know it is at least a StarTech
832 * 16650 V2, but it might be one of several StarTech UARTs, or one of
833 * its clones. (We treat the broken original StarTech 16650 V1 as a
834 * 16550, and why not? Startech doesn't seem to even acknowledge its
835 * existence.)
bd71c182 836 *
1da177e4
LT		 837 * What evil have men's minds wrought...
838 */
839static void autoconfig_has_efr(struct uart_8250_port *up)
840{
841 unsigned int id1, id2, id3, rev;
842
843 /*
844 * Everything with an EFR has SLEEP
845 */
846 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
847
848 /*
849 * First we check to see if it's an Oxford Semiconductor UART.
850 *
851 * If we have to do this here because some non-National
852 * Semiconductor clone chips lock up if you try writing to the
853 * LSR register (which serial_icr_read does)
854 */
855
856 /*
857 * Check for Oxford Semiconductor 16C950.
858 *
859 * EFR [4] must be set else this test fails.
860 *
861 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
862 * claims that it's needed for 952 dual UART's (which are not
863 * recommended for new designs).
864 */
865 up->acr = 0;
662b083a 866 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 867 serial_out(up, UART_EFR, UART_EFR_ECB);
868 serial_out(up, UART_LCR, 0x00);
869 id1 = serial_icr_read(up, UART_ID1);
870 id2 = serial_icr_read(up, UART_ID2);
871 id3 = serial_icr_read(up, UART_ID3);
872 rev = serial_icr_read(up, UART_REV);
873
874 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
875
876 if (id1 == 0x16 && id2 == 0xC9 &&
877 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
878 up->port.type = PORT_16C950;
4ba5e35d
RK		 879
880 /*
881 * Enable work around for the Oxford Semiconductor 952 rev B
882 * chip which causes it to seriously miscalculate baud rates
883 * when DLL is 0.
884 */
885 if (id3 == 0x52 && rev == 0x01)
886 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 887 return;
888 }
bd71c182 889
1da177e4
LT		 890 /*
891 * We check for a XR16C850 by setting DLL and DLM to 0, and then
892 * reading back DLL and DLM. The chip type depends on the DLM
893 * value read back:
894 * 0x10 - XR16C850 and the DLL contains the chip revision.
895 * 0x12 - XR16C2850.
896 * 0x14 - XR16C854.
897 */
898 id1 = autoconfig_read_divisor_id(up);
899 DEBUG_AUTOCONF("850id=%04x ", id1);
900
901 id2 = id1 >> 8;
902 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 903 up->port.type = PORT_16850;
904 return;
905 }
906
907 /*
908 * It wasn't an XR16C850.
909 *
910 * We distinguish between the '654 and the '650 by counting
911 * how many bytes are in the FIFO. I'm using this for now,
912 * since that's the technique that was sent to me in the
913 * serial driver update, but I'm not convinced this works.
914 * I've had problems doing this in the past. -TYT
915 */
916 if (size_fifo(up) == 64)
917 up->port.type = PORT_16654;
918 else
919 up->port.type = PORT_16650V2;
920}
921
922/*
923 * We detected a chip without a FIFO. Only two fall into
924 * this category - the original 8250 and the 16450. The
925 * 16450 has a scratch register (accessible with LCR=0)
926 */
927static void autoconfig_8250(struct uart_8250_port *up)
928{
929 unsigned char scratch, status1, status2;
930
931 up->port.type = PORT_8250;
932
933 scratch = serial_in(up, UART_SCR);
934 serial_outp(up, UART_SCR, 0xa5);
935 status1 = serial_in(up, UART_SCR);
936 serial_outp(up, UART_SCR, 0x5a);
937 status2 = serial_in(up, UART_SCR);
938 serial_outp(up, UART_SCR, scratch);
939
940 if (status1 == 0xa5 && status2 == 0x5a)
941 up->port.type = PORT_16450;
942}
943
944static int broken_efr(struct uart_8250_port *up)
945{
946 /*
947 * Exar ST16C2550 "A2" devices incorrectly detect as
948 * having an EFR, and report an ID of 0x0201. See
631dd1a8 949 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1da177e4
LT		 950 */
951 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
952 return 1;
953
954 return 0;
955}
956
957/*
958 * We know that the chip has FIFOs. Does it have an EFR? The
959 * EFR is located in the same register position as the IIR and
960 * we know the top two bits of the IIR are currently set. The
961 * EFR should contain zero. Try to read the EFR.
962 */
963static void autoconfig_16550a(struct uart_8250_port *up)
964{
965 unsigned char status1, status2;
966 unsigned int iersave;
967
968 up->port.type = PORT_16550A;
969 up->capabilities |= UART_CAP_FIFO;
970
971 /*
972 * Check for presence of the EFR when DLAB is set.
973 * Only ST16C650V1 UARTs pass this test.
974 */
662b083a 975 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 976 if (serial_in(up, UART_EFR) == 0) {
977 serial_outp(up, UART_EFR, 0xA8);
978 if (serial_in(up, UART_EFR) != 0) {
979 DEBUG_AUTOCONF("EFRv1 ");
980 up->port.type = PORT_16650;
981 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
982 } else {
983 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
984 }
985 serial_outp(up, UART_EFR, 0);
986 return;
987 }
988
989 /*
990 * Maybe it requires 0xbf to be written to the LCR.
991 * (other ST16C650V2 UARTs, TI16C752A, etc)
992 */
662b083a 993 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 994 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
995 DEBUG_AUTOCONF("EFRv2 ");
996 autoconfig_has_efr(up);
997 return;
998 }
999
1000 /*
1001 * Check for a National Semiconductor SuperIO chip.
1002 * Attempt to switch to bank 2, read the value of the LOOP bit
1003 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1004 * switch back to bank 2, read it from EXCR1 again and check
1005 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 1006 */
1007 serial_outp(up, UART_LCR, 0);
1008 status1 = serial_in(up, UART_MCR);
1009 serial_outp(up, UART_LCR, 0xE0);
1010 status2 = serial_in(up, 0x02); /* EXCR1 */
1011
1012 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1013 serial_outp(up, UART_LCR, 0);
1014 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
1015 serial_outp(up, UART_LCR, 0xE0);
1016 status2 = serial_in(up, 0x02); /* EXCR1 */
1017 serial_outp(up, UART_LCR, 0);
1018 serial_outp(up, UART_MCR, status1);
1019
1020 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 1021 unsigned short quot;
1022
1da177e4 1023 serial_outp(up, UART_LCR, 0xE0);
857dde2e 1024
b32b19b8 1025 quot = serial_dl_read(up);
857dde2e
DW		 1026 quot <<= 3;
1027
b5b82df6 1028 status1 = serial_in(up, 0x04); /* EXCR2 */
1da177e4
LT		 1029 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
1030 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
1031 serial_outp(up, 0x04, status1);
bd71c182 1032
b32b19b8 1033 serial_dl_write(up, quot);
857dde2e 1034
1da177e4 1035 serial_outp(up, UART_LCR, 0);
1da177e4 1036
857dde2e 1037 up->port.uartclk = 921600*16;
1da177e4
LT		 1038 up->port.type = PORT_NS16550A;
1039 up->capabilities |= UART_NATSEMI;
1040 return;
1041 }
1042 }
1043
1044 /*
1045 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1046 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1047 * Try setting it with and without DLAB set. Cheap clones
1048 * set bit 5 without DLAB set.
1049 */
1050 serial_outp(up, UART_LCR, 0);
1051 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1052 status1 = serial_in(up, UART_IIR) >> 5;
1053 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
662b083a 1054 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 1055 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1056 status2 = serial_in(up, UART_IIR) >> 5;
1057 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1058 serial_outp(up, UART_LCR, 0);
1059
1060 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1061
1062 if (status1 == 6 && status2 == 7) {
1063 up->port.type = PORT_16750;
1064 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1065 return;
1066 }
1067
1068 /*
1069 * Try writing and reading the UART_IER_UUE bit (b6).
1070 * If it works, this is probably one of the Xscale platform's
1071 * internal UARTs.
1072 * We're going to explicitly set the UUE bit to 0 before
1073 * trying to write and read a 1 just to make sure it's not
1074 * already a 1 and maybe locked there before we even start start.
1075 */
1076 iersave = serial_in(up, UART_IER);
1077 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1078 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1079 /*
1080 * OK it's in a known zero state, try writing and reading
1081 * without disturbing the current state of the other bits.
1082 */
1083 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1084 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1085 /*
1086 * It's an Xscale.
1087 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1088 */
1089 DEBUG_AUTOCONF("Xscale ");
1090 up->port.type = PORT_XSCALE;
1091 up->capabilities |= UART_CAP_UUE;
1092 return;
1093 }
1094 } else {
1095 /*
1096 * If we got here we couldn't force the IER_UUE bit to 0.
1097 * Log it and continue.
1098 */
1099 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1100 }
1101 serial_outp(up, UART_IER, iersave);
235dae5d
PL		 1102
1103 /*
1104 * We distinguish between 16550A and U6 16550A by counting
1105 * how many bytes are in the FIFO.
1106 */
1107 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1108 up->port.type = PORT_U6_16550A;
1109 up->capabilities |= UART_CAP_AFE;
1110 }
1da177e4
LT		 1111}
1112
1113/*
1114 * This routine is called by rs_init() to initialize a specific serial
1115 * port. It determines what type of UART chip this serial port is
1116 * using: 8250, 16450, 16550, 16550A. The important question is
1117 * whether or not this UART is a 16550A or not, since this will
1118 * determine whether or not we can use its FIFO features or not.
1119 */
1120static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1121{
1122 unsigned char status1, scratch, scratch2, scratch3;
1123 unsigned char save_lcr, save_mcr;
1124 unsigned long flags;
1125
1126 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1127 return;
1128
80647b95 1129 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
8440838b 1130 serial_index(&up->port), up->port.iobase, up->port.membase);
1da177e4
LT		 1131
1132 /*
1133 * We really do need global IRQs disabled here - we're going to
1134 * be frobbing the chips IRQ enable register to see if it exists.
1135 */
1136 spin_lock_irqsave(&up->port.lock, flags);
1da177e4
LT		 1137
1138 up->capabilities = 0;
4ba5e35d 1139 up->bugs = 0;
1da177e4
LT		 1140
1141 if (!(up->port.flags & UPF_BUGGY_UART)) {
1142 /*
1143 * Do a simple existence test first; if we fail this,
1144 * there's no point trying anything else.
bd71c182 1145 *
1da177e4
LT		 1146 * 0x80 is used as a nonsense port to prevent against
1147 * false positives due to ISA bus float. The
1148 * assumption is that 0x80 is a non-existent port;
1149 * which should be safe since include/asm/io.h also
1150 * makes this assumption.
1151 *
1152 * Note: this is safe as long as MCR bit 4 is clear
1153 * and the device is in "PC" mode.
1154 */
1155 scratch = serial_inp(up, UART_IER);
1156 serial_outp(up, UART_IER, 0);
1157#ifdef __i386__
1158 outb(0xff, 0x080);
1159#endif
48212008
TH		 1160 /*
1161 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1162 * 16C754B) allow only to modify them if an EFR bit is set.
1163 */
1164 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1165 serial_outp(up, UART_IER, 0x0F);
1166#ifdef __i386__
1167 outb(0, 0x080);
1168#endif
48212008 1169 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1170 serial_outp(up, UART_IER, scratch);
1171 if (scratch2 != 0 || scratch3 != 0x0F) {
1172 /*
1173 * We failed; there's nothing here
1174 */
1175 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1176 scratch2, scratch3);
1177 goto out;
1178 }
1179 }
1180
1181 save_mcr = serial_in(up, UART_MCR);
1182 save_lcr = serial_in(up, UART_LCR);
1183
bd71c182 1184 /*
1da177e4
LT		 1185 * Check to see if a UART is really there. Certain broken
1186 * internal modems based on the Rockwell chipset fail this
1187 * test, because they apparently don't implement the loopback
1188 * test mode. So this test is skipped on the COM 1 through
1189 * COM 4 ports. This *should* be safe, since no board
1190 * manufacturer would be stupid enough to design a board
1191 * that conflicts with COM 1-4 --- we hope!
1192 */
1193 if (!(up->port.flags & UPF_SKIP_TEST)) {
1194 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1195 status1 = serial_inp(up, UART_MSR) & 0xF0;
1196 serial_outp(up, UART_MCR, save_mcr);
1197 if (status1 != 0x90) {
1198 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1199 status1);
1200 goto out;
1201 }
1202 }
1203
1204 /*
1205 * We're pretty sure there's a port here. Lets find out what
1206 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1207 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1208 * determines what we test for next.
1209 *
1210 * We also initialise the EFR (if any) to zero for later. The
1211 * EFR occupies the same register location as the FCR and IIR.
1212 */
662b083a 1213 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 1214 serial_outp(up, UART_EFR, 0);
1215 serial_outp(up, UART_LCR, 0);
1216
1217 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1218 scratch = serial_in(up, UART_IIR) >> 6;
1219
1220 DEBUG_AUTOCONF("iir=%d ", scratch);
1221
1222 switch (scratch) {
1223 case 0:
1224 autoconfig_8250(up);
1225 break;
1226 case 1:
1227 up->port.type = PORT_UNKNOWN;
1228 break;
1229 case 2:
1230 up->port.type = PORT_16550;
1231 break;
1232 case 3:
1233 autoconfig_16550a(up);
1234 break;
1235 }
1236
1237#ifdef CONFIG_SERIAL_8250_RSA
1238 /*
1239 * Only probe for RSA ports if we got the region.
1240 */
1241 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1242 int i;
1243
1244 for (i = 0 ; i < probe_rsa_count; ++i) {
1245 if (probe_rsa[i] == up->port.iobase &&
1246 __enable_rsa(up)) {
1247 up->port.type = PORT_RSA;
1248 break;
1249 }
1250 }
1251 }
1252#endif
21c614a7 1253
1da177e4
LT		 1254 serial_outp(up, UART_LCR, save_lcr);
1255
1256 if (up->capabilities != uart_config[up->port.type].flags) {
1257 printk(KERN_WARNING
1258 "ttyS%d: detected caps %08x should be %08x\n",
8440838b
DM		 1259 serial_index(&up->port), up->capabilities,
1260 uart_config[up->port.type].flags);
1da177e4
LT		 1261 }
1262
1263 up->port.fifosize = uart_config[up->port.type].fifo_size;
1264 up->capabilities = uart_config[up->port.type].flags;
1265 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1266
1267 if (up->port.type == PORT_UNKNOWN)
1268 goto out;
1269
1270 /*
1271 * Reset the UART.
1272 */
1273#ifdef CONFIG_SERIAL_8250_RSA
1274 if (up->port.type == PORT_RSA)
1275 serial_outp(up, UART_RSA_FRR, 0);
1276#endif
1277 serial_outp(up, UART_MCR, save_mcr);
1278 serial8250_clear_fifos(up);
40b36daa 1279 serial_in(up, UART_RX);
5c8c755c
LB		 1280 if (up->capabilities & UART_CAP_UUE)
1281 serial_outp(up, UART_IER, UART_IER_UUE);
1282 else
1283 serial_outp(up, UART_IER, 0);
1da177e4 1284
bd71c182 1285 out:
1da177e4 1286 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1287 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1288}
1289
1290static void autoconfig_irq(struct uart_8250_port *up)
1291{
1292 unsigned char save_mcr, save_ier;
1293 unsigned char save_ICP = 0;
1294 unsigned int ICP = 0;
1295 unsigned long irqs;
1296 int irq;
1297
1298 if (up->port.flags & UPF_FOURPORT) {
1299 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1300 save_ICP = inb_p(ICP);
1301 outb_p(0x80, ICP);
1302 (void) inb_p(ICP);
1303 }
1304
1305 /* forget possible initially masked and pending IRQ */
1306 probe_irq_off(probe_irq_on());
1307 save_mcr = serial_inp(up, UART_MCR);
1308 save_ier = serial_inp(up, UART_IER);
1309 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1310
1da177e4
LT		 1311 irqs = probe_irq_on();
1312 serial_outp(up, UART_MCR, 0);
6f803cd0
AC		 1313 udelay(10);
1314 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 1315 serial_outp(up, UART_MCR,
1316 UART_MCR_DTR | UART_MCR_RTS);
1317 } else {
1318 serial_outp(up, UART_MCR,
1319 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1320 }
1321 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1322 (void)serial_inp(up, UART_LSR);
1323 (void)serial_inp(up, UART_RX);
1324 (void)serial_inp(up, UART_IIR);
1325 (void)serial_inp(up, UART_MSR);
1326 serial_outp(up, UART_TX, 0xFF);
6f803cd0 1327 udelay(20);
1da177e4
LT		 1328 irq = probe_irq_off(irqs);
1329
1330 serial_outp(up, UART_MCR, save_mcr);
1331 serial_outp(up, UART_IER, save_ier);
1332
1333 if (up->port.flags & UPF_FOURPORT)
1334 outb_p(save_ICP, ICP);
1335
1336 up->port.irq = (irq > 0) ? irq : 0;
1337}
1338
e763b90c
RK		 1339static inline void __stop_tx(struct uart_8250_port *p)
1340{
1341 if (p->ier & UART_IER_THRI) {
1342 p->ier &= ~UART_IER_THRI;
1343 serial_out(p, UART_IER, p->ier);
1344 }
1345}
1346
b129a8cc 1347static void serial8250_stop_tx(struct uart_port *port)
1da177e4 1348{
49d5741b
JI		 1349 struct uart_8250_port *up =
1350 container_of(port, struct uart_8250_port, port);
1da177e4 1351
e763b90c 1352 __stop_tx(up);
1da177e4
LT		 1353
1354 /*
e763b90c 1355 * We really want to stop the transmitter from sending.
1da177e4 1356 */
e763b90c 1357 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1358 up->acr |= UART_ACR_TXDIS;
1359 serial_icr_write(up, UART_ACR, up->acr);
1360 }
1361}
1362
55d3b282
RK		 1363static void transmit_chars(struct uart_8250_port *up);
1364
b129a8cc 1365static void serial8250_start_tx(struct uart_port *port)
1da177e4 1366{
49d5741b
JI		 1367 struct uart_8250_port *up =
1368 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1369
1370 if (!(up->ier & UART_IER_THRI)) {
1371 up->ier |= UART_IER_THRI;
1372 serial_out(up, UART_IER, up->ier);
55d3b282 1373
67f7654e 1374 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1375 unsigned char lsr;
55d3b282 1376 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1377 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
bd71c182 1378 if ((up->port.type == PORT_RM9000) ?
68cb4f8e
IJ		 1379 (lsr & UART_LSR_THRE) :
1380 (lsr & UART_LSR_TEMT))
55d3b282
RK		 1381 transmit_chars(up);
1382 }
1da177e4 1383 }
e763b90c 1384
1da177e4 1385 /*
e763b90c 1386 * Re-enable the transmitter if we disabled it.
1da177e4 1387 */
e763b90c 1388 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1389 up->acr &= ~UART_ACR_TXDIS;
1390 serial_icr_write(up, UART_ACR, up->acr);
1391 }
1392}
1393
1394static void serial8250_stop_rx(struct uart_port *port)
1395{
49d5741b
JI		 1396 struct uart_8250_port *up =
1397 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1398
1399 up->ier &= ~UART_IER_RLSI;
1400 up->port.read_status_mask &= ~UART_LSR_DR;
1401 serial_out(up, UART_IER, up->ier);
1402}
1403
1404static void serial8250_enable_ms(struct uart_port *port)
1405{
49d5741b
JI		 1406 struct uart_8250_port *up =
1407 container_of(port, struct uart_8250_port, port);
1da177e4 1408
21c614a7
PA		 1409 /* no MSR capabilities */
1410 if (up->bugs & UART_BUG_NOMSR)
1411 return;
1412
1da177e4
LT		 1413 up->ier |= UART_IER_MSI;
1414 serial_out(up, UART_IER, up->ier);
1415}
1416
ea8874dc 1417static void
cc79aa9d 1418receive_chars(struct uart_8250_port *up, unsigned int *status)
1da177e4 1419{
ebd2c8f6 1420 struct tty_struct *tty = up->port.state->port.tty;
1da177e4
LT		 1421 unsigned char ch, lsr = *status;
1422 int max_count = 256;
1423 char flag;
1424
1425 do {
7500b1f6
AR		 1426 if (likely(lsr & UART_LSR_DR))
1427 ch = serial_inp(up, UART_RX);
1428 else
1429 /*
1430 * Intel 82571 has a Serial Over Lan device that will
1431 * set UART_LSR_BI without setting UART_LSR_DR when
1432 * it receives a break. To avoid reading from the
1433 * receive buffer without UART_LSR_DR bit set, we
1434 * just force the read character to be 0
1435 */
1436 ch = 0;
1437
1da177e4
LT		 1438 flag = TTY_NORMAL;
1439 up->port.icount.rx++;
1440
ad4c2aa6
CM		 1441 lsr |= up->lsr_saved_flags;
1442 up->lsr_saved_flags = 0;
1da177e4 1443
ad4c2aa6 1444 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1445 /*
1446 * For statistics only
1447 */
1448 if (lsr & UART_LSR_BI) {
1449 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1450 up->port.icount.brk++;
1451 /*
1452 * We do the SysRQ and SAK checking
1453 * here because otherwise the break
1454 * may get masked by ignore_status_mask
1455 * or read_status_mask.
1456 */
1457 if (uart_handle_break(&up->port))
1458 goto ignore_char;
1459 } else if (lsr & UART_LSR_PE)
1460 up->port.icount.parity++;
1461 else if (lsr & UART_LSR_FE)
1462 up->port.icount.frame++;
1463 if (lsr & UART_LSR_OE)
1464 up->port.icount.overrun++;
1465
1466 /*
23907eb8 1467 * Mask off conditions which should be ignored.
1da177e4
LT		 1468 */
1469 lsr &= up->port.read_status_mask;
1470
1471 if (lsr & UART_LSR_BI) {
1472 DEBUG_INTR("handling break....");
1473 flag = TTY_BREAK;
1474 } else if (lsr & UART_LSR_PE)
1475 flag = TTY_PARITY;
1476 else if (lsr & UART_LSR_FE)
1477 flag = TTY_FRAME;
1478 }
7d12e780 1479 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1480 goto ignore_char;
05ab3014
RK		 1481
1482 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1483
6f803cd0 1484ignore_char:
1da177e4 1485 lsr = serial_inp(up, UART_LSR);
7500b1f6 1486 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1da177e4
LT		 1487 spin_unlock(&up->port.lock);
1488 tty_flip_buffer_push(tty);
1489 spin_lock(&up->port.lock);
1490 *status = lsr;
1491}
1492
ea8874dc 1493static void transmit_chars(struct uart_8250_port *up)
1da177e4 1494{
ebd2c8f6 1495 struct circ_buf *xmit = &up->port.state->xmit;
1da177e4
LT		 1496 int count;
1497
1498 if (up->port.x_char) {
1499 serial_outp(up, UART_TX, up->port.x_char);
1500 up->port.icount.tx++;
1501 up->port.x_char = 0;
1502 return;
1503 }
b129a8cc
RK		 1504 if (uart_tx_stopped(&up->port)) {
1505 serial8250_stop_tx(&up->port);
1506 return;
1507 }
1508 if (uart_circ_empty(xmit)) {
e763b90c 1509 __stop_tx(up);
1da177e4
LT		 1510 return;
1511 }
1512
1513 count = up->tx_loadsz;
1514 do {
1515 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1516 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1517 up->port.icount.tx++;
1518 if (uart_circ_empty(xmit))
1519 break;
1520 } while (--count > 0);
1521
1522 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1523 uart_write_wakeup(&up->port);
1524
1525 DEBUG_INTR("THRE...");
1526
1527 if (uart_circ_empty(xmit))
e763b90c 1528 __stop_tx(up);
1da177e4
LT		 1529}
1530
2af7cd68 1531static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1532{
2af7cd68
RK		 1533 unsigned int status = serial_in(up, UART_MSR);
1534
ad4c2aa6
CM		 1535 status |= up->msr_saved_flags;
1536 up->msr_saved_flags = 0;
fdc30b3d 1537 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
ebd2c8f6 1538 up->port.state != NULL) {
2af7cd68
RK		 1539 if (status & UART_MSR_TERI)
1540 up->port.icount.rng++;
1541 if (status & UART_MSR_DDSR)
1542 up->port.icount.dsr++;
1543 if (status & UART_MSR_DDCD)
1544 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1545 if (status & UART_MSR_DCTS)
1546 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1547
bdc04e31 1548 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
2af7cd68 1549 }
1da177e4 1550
2af7cd68 1551 return status;
1da177e4
LT		 1552}
1553
1554/*
1555 * This handles the interrupt from one port.
1556 */
b5d674ab 1557static void serial8250_handle_port(struct uart_8250_port *up)
1da177e4 1558{
45e24601 1559 unsigned int status;
4bf3631c 1560 unsigned long flags;
45e24601 1561
4bf3631c 1562 spin_lock_irqsave(&up->port.lock, flags);
45e24601
RK		 1563
1564 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1565
1566 DEBUG_INTR("status = %x...", status);
1567
7500b1f6 1568 if (status & (UART_LSR_DR | UART_LSR_BI))
7d12e780 1569 receive_chars(up, &status);
1da177e4
LT		 1570 check_modem_status(up);
1571 if (status & UART_LSR_THRE)
1572 transmit_chars(up);
45e24601 1573
4bf3631c 1574 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1575}
1576
1577/*
1578 * This is the serial driver's interrupt routine.
1579 *
1580 * Arjan thinks the old way was overly complex, so it got simplified.
1581 * Alan disagrees, saying that need the complexity to handle the weird
1582 * nature of ISA shared interrupts. (This is a special exception.)
1583 *
1584 * In order to handle ISA shared interrupts properly, we need to check
1585 * that all ports have been serviced, and therefore the ISA interrupt
1586 * line has been de-asserted.
1587 *
1588 * This means we need to loop through all ports. checking that they
1589 * don't have an interrupt pending.
1590 */
7d12e780 1591static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1592{
1593 struct irq_info *i = dev_id;
1594 struct list_head *l, *end = NULL;
1595 int pass_counter = 0, handled = 0;
1596
1597 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1598
1599 spin_lock(&i->lock);
1600
1601 l = i->head;
1602 do {
1603 struct uart_8250_port *up;
1604 unsigned int iir;
1605
1606 up = list_entry(l, struct uart_8250_port, list);
1607
1608 iir = serial_in(up, UART_IIR);
1609 if (!(iir & UART_IIR_NO_INT)) {
7d12e780 1610 serial8250_handle_port(up);
1da177e4
LT		 1611
1612 handled = 1;
1613
beab697a 1614 end = NULL;
a3ae0fc3
JI		 1615 } else if ((up->port.iotype == UPIO_DWAPB ||
1616 up->port.iotype == UPIO_DWAPB32) &&
beab697a
MSJ		 1617 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1618 /* The DesignWare APB UART has an Busy Detect (0x07)
1619 * interrupt meaning an LCR write attempt occured while the
1620 * UART was busy. The interrupt must be cleared by reading
1621 * the UART status register (USR) and the LCR re-written. */
1622 unsigned int status;
1623 status = *(volatile u32 *)up->port.private_data;
1624 serial_out(up, UART_LCR, up->lcr);
1625
1626 handled = 1;
1627
1da177e4
LT		 1628 end = NULL;
1629 } else if (end == NULL)
1630 end = l;
1631
1632 l = l->next;
1633
1634 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1635 /* If we hit this, we're dead. */
cd3ecad1
DD		 1636 printk_ratelimited(KERN_ERR
1637 "serial8250: too much work for irq%d\n", irq);
1da177e4
LT		 1638 break;
1639 }
1640 } while (l != end);
1641
1642 spin_unlock(&i->lock);
1643
1644 DEBUG_INTR("end.\n");
1645
1646 return IRQ_RETVAL(handled);
1647}
1648
1649/*
1650 * To support ISA shared interrupts, we need to have one interrupt
1651 * handler that ensures that the IRQ line has been deasserted
1652 * before returning. Failing to do this will result in the IRQ
1653 * line being stuck active, and, since ISA irqs are edge triggered,
1654 * no more IRQs will be seen.
1655 */
1656static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1657{
1658 spin_lock_irq(&i->lock);
1659
1660 if (!list_empty(i->head)) {
1661 if (i->head == &up->list)
1662 i->head = i->head->next;
1663 list_del(&up->list);
1664 } else {
1665 BUG_ON(i->head != &up->list);
1666 i->head = NULL;
1667 }
1da177e4 1668 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1669 /* List empty so throw away the hash node */
1670 if (i->head == NULL) {
1671 hlist_del(&i->node);
1672 kfree(i);
1673 }
1da177e4
LT		 1674}
1675
1676static int serial_link_irq_chain(struct uart_8250_port *up)
1677{
25db8ad5
AC		 1678 struct hlist_head *h;
1679 struct hlist_node *n;
1680 struct irq_info *i;
40663cc7 1681 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1682
25db8ad5
AC		 1683 mutex_lock(&hash_mutex);
1684
1685 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1686
1687 hlist_for_each(n, h) {
1688 i = hlist_entry(n, struct irq_info, node);
1689 if (i->irq == up->port.irq)
1690 break;
1691 }
1692
1693 if (n == NULL) {
1694 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1695 if (i == NULL) {
1696 mutex_unlock(&hash_mutex);
1697 return -ENOMEM;
1698 }
1699 spin_lock_init(&i->lock);
1700 i->irq = up->port.irq;
1701 hlist_add_head(&i->node, h);
1702 }
1703 mutex_unlock(&hash_mutex);
1704
1da177e4
LT		 1705 spin_lock_irq(&i->lock);
1706
1707 if (i->head) {
1708 list_add(&up->list, i->head);
1709 spin_unlock_irq(&i->lock);
1710
1711 ret = 0;
1712 } else {
1713 INIT_LIST_HEAD(&up->list);
1714 i->head = &up->list;
1715 spin_unlock_irq(&i->lock);
1c2f0493 1716 irq_flags |= up->port.irqflags;
1da177e4
LT		 1717 ret = request_irq(up->port.irq, serial8250_interrupt,
1718 irq_flags, "serial", i);
1719 if (ret < 0)
1720 serial_do_unlink(i, up);
1721 }
1722
1723 return ret;
1724}
1725
1726static void serial_unlink_irq_chain(struct uart_8250_port *up)
1727{
25db8ad5
AC		 1728 struct irq_info *i;
1729 struct hlist_node *n;
1730 struct hlist_head *h;
1da177e4 1731
25db8ad5
AC		 1732 mutex_lock(&hash_mutex);
1733
1734 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1735
1736 hlist_for_each(n, h) {
1737 i = hlist_entry(n, struct irq_info, node);
1738 if (i->irq == up->port.irq)
1739 break;
1740 }
1741
1742 BUG_ON(n == NULL);
1da177e4
LT		 1743 BUG_ON(i->head == NULL);
1744
1745 if (list_empty(i->head))
1746 free_irq(up->port.irq, i);
1747
1748 serial_do_unlink(i, up);
25db8ad5 1749 mutex_unlock(&hash_mutex);
1da177e4
LT		 1750}
1751
1752/*
1753 * This function is used to handle ports that do not have an
1754 * interrupt. This doesn't work very well for 16450's, but gives
1755 * barely passable results for a 16550A. (Although at the expense
1756 * of much CPU overhead).
1757 */
1758static void serial8250_timeout(unsigned long data)
1759{
1760 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4
LT		 1761 unsigned int iir;
1762
1763 iir = serial_in(up, UART_IIR);
45e24601 1764 if (!(iir & UART_IIR_NO_INT))
7d12e780 1765 serial8250_handle_port(up);
54381067 1766 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
40b36daa
AW		 1767}
1768
1769static void serial8250_backup_timeout(unsigned long data)
1770{
1771 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1772 unsigned int iir, ier = 0, lsr;
1773 unsigned long flags;
40b36daa
AW		 1774
1775 /*
1776 * Must disable interrupts or else we risk racing with the interrupt
1777 * based handler.
1778 */
1779 if (is_real_interrupt(up->port.irq)) {
1780 ier = serial_in(up, UART_IER);
1781 serial_out(up, UART_IER, 0);
1782 }
1da177e4 1783
40b36daa
AW		 1784 iir = serial_in(up, UART_IIR);
1785
1786 /*
1787 * This should be a safe test for anyone who doesn't trust the
1788 * IIR bits on their UART, but it's specifically designed for
1789 * the "Diva" UART used on the management processor on many HP
1790 * ia64 and parisc boxes.
1791 */
ad4c2aa6
CM		 1792 spin_lock_irqsave(&up->port.lock, flags);
1793 lsr = serial_in(up, UART_LSR);
1794 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1795 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa 1796 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1797 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1798 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1799 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1800 iir |= UART_IIR_THRI;
1801 }
1802
1803 if (!(iir & UART_IIR_NO_INT))
1804 serial8250_handle_port(up);
1805
1806 if (is_real_interrupt(up->port.irq))
1807 serial_out(up, UART_IER, ier);
1808
1809 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0 1810 mod_timer(&up->timer,
54381067 1811 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1da177e4
LT		 1812}
1813
1814static unsigned int serial8250_tx_empty(struct uart_port *port)
1815{
49d5741b
JI		 1816 struct uart_8250_port *up =
1817 container_of(port, struct uart_8250_port, port);
1da177e4 1818 unsigned long flags;
ad4c2aa6 1819 unsigned int lsr;
1da177e4
LT		 1820
1821 spin_lock_irqsave(&up->port.lock, flags);
ad4c2aa6
CM		 1822 lsr = serial_in(up, UART_LSR);
1823 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1da177e4
LT		 1824 spin_unlock_irqrestore(&up->port.lock, flags);
1825
bca47613 1826 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1827}
1828
1829static unsigned int serial8250_get_mctrl(struct uart_port *port)
1830{
49d5741b
JI		 1831 struct uart_8250_port *up =
1832 container_of(port, struct uart_8250_port, port);
2af7cd68 1833 unsigned int status;
1da177e4
LT		 1834 unsigned int ret;
1835
2af7cd68 1836 status = check_modem_status(up);
1da177e4
LT		 1837
1838 ret = 0;
1839 if (status & UART_MSR_DCD)
1840 ret |= TIOCM_CAR;
1841 if (status & UART_MSR_RI)
1842 ret |= TIOCM_RNG;
1843 if (status & UART_MSR_DSR)
1844 ret |= TIOCM_DSR;
1845 if (status & UART_MSR_CTS)
1846 ret |= TIOCM_CTS;
1847 return ret;
1848}
1849
1850static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1851{
49d5741b
JI		 1852 struct uart_8250_port *up =
1853 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1854 unsigned char mcr = 0;
1855
1856 if (mctrl & TIOCM_RTS)
1857 mcr |= UART_MCR_RTS;
1858 if (mctrl & TIOCM_DTR)
1859 mcr |= UART_MCR_DTR;
1860 if (mctrl & TIOCM_OUT1)
1861 mcr |= UART_MCR_OUT1;
1862 if (mctrl & TIOCM_OUT2)
1863 mcr |= UART_MCR_OUT2;
1864 if (mctrl & TIOCM_LOOP)
1865 mcr |= UART_MCR_LOOP;
1866
1867 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1868
1869 serial_out(up, UART_MCR, mcr);
1870}
1871
1872static void serial8250_break_ctl(struct uart_port *port, int break_state)
1873{
49d5741b
JI		 1874 struct uart_8250_port *up =
1875 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1876 unsigned long flags;
1877
1878 spin_lock_irqsave(&up->port.lock, flags);
1879 if (break_state == -1)
1880 up->lcr |= UART_LCR_SBC;
1881 else
1882 up->lcr &= ~UART_LCR_SBC;
1883 serial_out(up, UART_LCR, up->lcr);
1884 spin_unlock_irqrestore(&up->port.lock, flags);
1885}
1886
40b36daa
AW		 1887/*
1888 * Wait for transmitter & holding register to empty
1889 */
b5d674ab 1890static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1891{
1892 unsigned int status, tmout = 10000;
1893
1894 /* Wait up to 10ms for the character(s) to be sent. */
97d303b7 1895 for (;;) {
40b36daa
AW		 1896 status = serial_in(up, UART_LSR);
1897
ad4c2aa6 1898 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa 1899
97d303b7
DD		 1900 if ((status & bits) == bits)
1901 break;
40b36daa
AW		 1902 if (--tmout == 0)
1903 break;
1904 udelay(1);
97d303b7 1905 }
40b36daa
AW		 1906
1907 /* Wait up to 1s for flow control if necessary */
1908 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1909 unsigned int tmout;
1910 for (tmout = 1000000; tmout; tmout--) {
1911 unsigned int msr = serial_in(up, UART_MSR);
1912 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1913 if (msr & UART_MSR_CTS)
1914 break;
40b36daa
AW		 1915 udelay(1);
1916 touch_nmi_watchdog();
1917 }
1918 }
1919}
1920
f2d937f3
JW		 1921#ifdef CONFIG_CONSOLE_POLL
1922/*
1923 * Console polling routines for writing and reading from the uart while
1924 * in an interrupt or debug context.
1925 */
1926
1927static int serial8250_get_poll_char(struct uart_port *port)
1928{
49d5741b
JI		 1929 struct uart_8250_port *up =
1930 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1931 unsigned char lsr = serial_inp(up, UART_LSR);
1932
f5316b4a
JW		 1933 if (!(lsr & UART_LSR_DR))
1934 return NO_POLL_CHAR;
f2d937f3
JW		 1935
1936 return serial_inp(up, UART_RX);
1937}
1938
1939
1940static void serial8250_put_poll_char(struct uart_port *port,
1941 unsigned char c)
1942{
1943 unsigned int ier;
49d5741b
JI		 1944 struct uart_8250_port *up =
1945 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1946
1947 /*
1948 * First save the IER then disable the interrupts
1949 */
1950 ier = serial_in(up, UART_IER);
1951 if (up->capabilities & UART_CAP_UUE)
1952 serial_out(up, UART_IER, UART_IER_UUE);
1953 else
1954 serial_out(up, UART_IER, 0);
1955
1956 wait_for_xmitr(up, BOTH_EMPTY);
1957 /*
1958 * Send the character out.
1959 * If a LF, also do CR...
1960 */
1961 serial_out(up, UART_TX, c);
1962 if (c == 10) {
1963 wait_for_xmitr(up, BOTH_EMPTY);
1964 serial_out(up, UART_TX, 13);
1965 }
1966
1967 /*
1968 * Finally, wait for transmitter to become empty
1969 * and restore the IER
1970 */
1971 wait_for_xmitr(up, BOTH_EMPTY);
1972 serial_out(up, UART_IER, ier);
1973}
1974
1975#endif /* CONFIG_CONSOLE_POLL */
1976
1da177e4
LT		 1977static int serial8250_startup(struct uart_port *port)
1978{
49d5741b
JI		 1979 struct uart_8250_port *up =
1980 container_of(port, struct uart_8250_port, port);
1da177e4 1981 unsigned long flags;
55d3b282 1982 unsigned char lsr, iir;
1da177e4
LT		 1983 int retval;
1984
e4f05af1
OP		 1985 up->port.fifosize = uart_config[up->port.type].fifo_size;
1986 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1da177e4
LT		 1987 up->capabilities = uart_config[up->port.type].flags;
1988 up->mcr = 0;
1989
b8e7e40a
AC		 1990 if (up->port.iotype != up->cur_iotype)
1991 set_io_from_upio(port);
1992
1da177e4
LT		 1993 if (up->port.type == PORT_16C950) {
1994 /* Wake up and initialize UART */
1995 up->acr = 0;
662b083a 1996 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 1997 serial_outp(up, UART_EFR, UART_EFR_ECB);
1998 serial_outp(up, UART_IER, 0);
1999 serial_outp(up, UART_LCR, 0);
2000 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2001 serial_outp(up, UART_LCR, 0xBF);
2002 serial_outp(up, UART_EFR, UART_EFR_ECB);
2003 serial_outp(up, UART_LCR, 0);
2004 }
2005
2006#ifdef CONFIG_SERIAL_8250_RSA
2007 /*
2008 * If this is an RSA port, see if we can kick it up to the
2009 * higher speed clock.
2010 */
2011 enable_rsa(up);
2012#endif
2013
2014 /*
2015 * Clear the FIFO buffers and disable them.
7f927fcc 2016 * (they will be reenabled in set_termios())
1da177e4
LT		 2017 */
2018 serial8250_clear_fifos(up);
2019
2020 /*
2021 * Clear the interrupt registers.
2022 */
2023 (void) serial_inp(up, UART_LSR);
2024 (void) serial_inp(up, UART_RX);
2025 (void) serial_inp(up, UART_IIR);
2026 (void) serial_inp(up, UART_MSR);
2027
2028 /*
2029 * At this point, there's no way the LSR could still be 0xff;
2030 * if it is, then bail out, because there's likely no UART
2031 * here.
2032 */
2033 if (!(up->port.flags & UPF_BUGGY_UART) &&
2034 (serial_inp(up, UART_LSR) == 0xff)) {
8440838b
DM		 2035 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2036 serial_index(&up->port));
1da177e4
LT		 2037 return -ENODEV;
2038 }
2039
2040 /*
2041 * For a XR16C850, we need to set the trigger levels
2042 */
2043 if (up->port.type == PORT_16850) {
2044 unsigned char fctr;
2045
662b083a 2046 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 2047
2048 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2049 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2050 serial_outp(up, UART_TRG, UART_TRG_96);
2051 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2052 serial_outp(up, UART_TRG, UART_TRG_96);
2053
2054 serial_outp(up, UART_LCR, 0);
2055 }
2056
40b36daa 2057 if (is_real_interrupt(up->port.irq)) {
01c194d9 2058 unsigned char iir1;
40b36daa
AW		 2059 /*
2060 * Test for UARTs that do not reassert THRE when the
2061 * transmitter is idle and the interrupt has already
2062 * been cleared. Real 16550s should always reassert
2063 * this interrupt whenever the transmitter is idle and
2064 * the interrupt is enabled. Delays are necessary to
2065 * allow register changes to become visible.
2066 */
c389d27b 2067 spin_lock_irqsave(&up->port.lock, flags);
1c2f0493 2068 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2069 disable_irq_nosync(up->port.irq);
40b36daa
AW		 2070
2071 wait_for_xmitr(up, UART_LSR_THRE);
2072 serial_out_sync(up, UART_IER, UART_IER_THRI);
2073 udelay(1); /* allow THRE to set */
01c194d9 2074 iir1 = serial_in(up, UART_IIR);
40b36daa
AW		 2075 serial_out(up, UART_IER, 0);
2076 serial_out_sync(up, UART_IER, UART_IER_THRI);
2077 udelay(1); /* allow a working UART time to re-assert THRE */
2078 iir = serial_in(up, UART_IIR);
2079 serial_out(up, UART_IER, 0);
2080
1c2f0493 2081 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2082 enable_irq(up->port.irq);
c389d27b 2083 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa
AW		 2084
2085 /*
2086 * If the interrupt is not reasserted, setup a timer to
2087 * kick the UART on a regular basis.
2088 */
01c194d9 2089 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
363f66fe 2090 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2091 pr_debug("ttyS%d - using backup timer\n",
2092 serial_index(port));
40b36daa
AW		 2093 }
2094 }
2095
363f66fe
WN		 2096 /*
2097 * The above check will only give an accurate result the first time
2098 * the port is opened so this value needs to be preserved.
2099 */
2100 if (up->bugs & UART_BUG_THRE) {
2101 up->timer.function = serial8250_backup_timeout;
2102 up->timer.data = (unsigned long)up;
2103 mod_timer(&up->timer, jiffies +
54381067 2104 uart_poll_timeout(port) + HZ / 5);
363f66fe
WN		 2105 }
2106
1da177e4
LT		 2107 /*
2108 * If the "interrupt" for this port doesn't correspond with any
2109 * hardware interrupt, we use a timer-based system. The original
2110 * driver used to do this with IRQ0.
2111 */
2112 if (!is_real_interrupt(up->port.irq)) {
1da177e4 2113 up->timer.data = (unsigned long)up;
54381067 2114 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
1da177e4
LT		 2115 } else {
2116 retval = serial_link_irq_chain(up);
2117 if (retval)
2118 return retval;
2119 }
2120
2121 /*
2122 * Now, initialize the UART
2123 */
2124 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2125
2126 spin_lock_irqsave(&up->port.lock, flags);
2127 if (up->port.flags & UPF_FOURPORT) {
2128 if (!is_real_interrupt(up->port.irq))
2129 up->port.mctrl |= TIOCM_OUT1;
2130 } else
2131 /*
2132 * Most PC uarts need OUT2 raised to enable interrupts.
2133 */
2134 if (is_real_interrupt(up->port.irq))
2135 up->port.mctrl |= TIOCM_OUT2;
2136
2137 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282 2138
b6adea33
MCC		 2139 /* Serial over Lan (SoL) hack:
2140 Intel 8257x Gigabit ethernet chips have a
2141 16550 emulation, to be used for Serial Over Lan.
2142 Those chips take a longer time than a normal
2143 serial device to signalize that a transmission
2144 data was queued. Due to that, the above test generally
2145 fails. One solution would be to delay the reading of
2146 iir. However, this is not reliable, since the timeout
2147 is variable. So, let's just don't test if we receive
2148 TX irq. This way, we'll never enable UART_BUG_TXEN.
2149 */
d41a4b51 2150 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2151 goto dont_test_tx_en;
2152
55d3b282
RK		 2153 /*
2154 * Do a quick test to see if we receive an
2155 * interrupt when we enable the TX irq.
2156 */
2157 serial_outp(up, UART_IER, UART_IER_THRI);
2158 lsr = serial_in(up, UART_LSR);
2159 iir = serial_in(up, UART_IIR);
2160 serial_outp(up, UART_IER, 0);
2161
2162 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2163 if (!(up->bugs & UART_BUG_TXEN)) {
2164 up->bugs |= UART_BUG_TXEN;
55d3b282 2165 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2166 serial_index(port));
55d3b282
RK		 2167 }
2168 } else {
67f7654e 2169 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2170 }
2171
b6adea33 2172dont_test_tx_en:
1da177e4
LT		 2173 spin_unlock_irqrestore(&up->port.lock, flags);
2174
ad4c2aa6
CM		 2175 /*
2176 * Clear the interrupt registers again for luck, and clear the
2177 * saved flags to avoid getting false values from polling
2178 * routines or the previous session.
2179 */
2180 serial_inp(up, UART_LSR);
2181 serial_inp(up, UART_RX);
2182 serial_inp(up, UART_IIR);
2183 serial_inp(up, UART_MSR);
2184 up->lsr_saved_flags = 0;
2185 up->msr_saved_flags = 0;
2186
1da177e4
LT		 2187 /*
2188 * Finally, enable interrupts. Note: Modem status interrupts
2189 * are set via set_termios(), which will be occurring imminently
2190 * anyway, so we don't enable them here.
2191 */
2192 up->ier = UART_IER_RLSI | UART_IER_RDI;
2193 serial_outp(up, UART_IER, up->ier);
2194
2195 if (up->port.flags & UPF_FOURPORT) {
2196 unsigned int icp;
2197 /*
2198 * Enable interrupts on the AST Fourport board
2199 */
2200 icp = (up->port.iobase & 0xfe0) | 0x01f;
2201 outb_p(0x80, icp);
2202 (void) inb_p(icp);
2203 }
2204
1da177e4
LT		 2205 return 0;
2206}
2207
2208static void serial8250_shutdown(struct uart_port *port)
2209{
49d5741b
JI		 2210 struct uart_8250_port *up =
2211 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2212 unsigned long flags;
2213
2214 /*
2215 * Disable interrupts from this port
2216 */
2217 up->ier = 0;
2218 serial_outp(up, UART_IER, 0);
2219
2220 spin_lock_irqsave(&up->port.lock, flags);
2221 if (up->port.flags & UPF_FOURPORT) {
2222 /* reset interrupts on the AST Fourport board */
2223 inb((up->port.iobase & 0xfe0) | 0x1f);
2224 up->port.mctrl |= TIOCM_OUT1;
2225 } else
2226 up->port.mctrl &= ~TIOCM_OUT2;
2227
2228 serial8250_set_mctrl(&up->port, up->port.mctrl);
2229 spin_unlock_irqrestore(&up->port.lock, flags);
2230
2231 /*
2232 * Disable break condition and FIFOs
2233 */
2234 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2235 serial8250_clear_fifos(up);
2236
2237#ifdef CONFIG_SERIAL_8250_RSA
2238 /*
2239 * Reset the RSA board back to 115kbps compat mode.
2240 */
2241 disable_rsa(up);
2242#endif
2243
2244 /*
2245 * Read data port to reset things, and then unlink from
2246 * the IRQ chain.
2247 */
2248 (void) serial_in(up, UART_RX);
2249
40b36daa
AW		 2250 del_timer_sync(&up->timer);
2251 up->timer.function = serial8250_timeout;
2252 if (is_real_interrupt(up->port.irq))
1da177e4
LT		 2253 serial_unlink_irq_chain(up);
2254}
2255
2256static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2257{
2258 unsigned int quot;
2259
2260 /*
2261 * Handle magic divisors for baud rates above baud_base on
2262 * SMSC SuperIO chips.
2263 */
2264 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2265 baud == (port->uartclk/4))
2266 quot = 0x8001;
2267 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2268 baud == (port->uartclk/8))
2269 quot = 0x8002;
2270 else
2271 quot = uart_get_divisor(port, baud);
2272
2273 return quot;
2274}
2275
235dae5d
PL		 2276void
2277serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2278 struct ktermios *old)
1da177e4 2279{
49d5741b
JI		 2280 struct uart_8250_port *up =
2281 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2282 unsigned char cval, fcr = 0;
2283 unsigned long flags;
2284 unsigned int baud, quot;
2285
2286 switch (termios->c_cflag & CSIZE) {
2287 case CS5:
0a8b80c5 2288 cval = UART_LCR_WLEN5;
1da177e4
LT		 2289 break;
2290 case CS6:
0a8b80c5 2291 cval = UART_LCR_WLEN6;
1da177e4
LT		 2292 break;
2293 case CS7:
0a8b80c5 2294 cval = UART_LCR_WLEN7;
1da177e4
LT		 2295 break;
2296 default:
2297 case CS8:
0a8b80c5 2298 cval = UART_LCR_WLEN8;
1da177e4
LT		 2299 break;
2300 }
2301
2302 if (termios->c_cflag & CSTOPB)
0a8b80c5 2303 cval |= UART_LCR_STOP;
1da177e4
LT		 2304 if (termios->c_cflag & PARENB)
2305 cval |= UART_LCR_PARITY;
2306 if (!(termios->c_cflag & PARODD))
2307 cval |= UART_LCR_EPAR;
2308#ifdef CMSPAR
2309 if (termios->c_cflag & CMSPAR)
2310 cval |= UART_LCR_SPAR;
2311#endif
2312
2313 /*
2314 * Ask the core to calculate the divisor for us.
2315 */
24d481ec
AV		 2316 baud = uart_get_baud_rate(port, termios, old,
2317 port->uartclk / 16 / 0xffff,
2318 port->uartclk / 16);
1da177e4
LT		 2319 quot = serial8250_get_divisor(port, baud);
2320
2321 /*
4ba5e35d 2322 * Oxford Semi 952 rev B workaround
1da177e4 2323 */
4ba5e35d 2324 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2325 quot++;
1da177e4
LT		 2326
2327 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2328 if (baud < 2400)
2329 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2330 else
2331 fcr = uart_config[up->port.type].fcr;
2332 }
2333
2334 /*
2335 * MCR-based auto flow control. When AFE is enabled, RTS will be
2336 * deasserted when the receive FIFO contains more characters than
2337 * the trigger, or the MCR RTS bit is cleared. In the case where
2338 * the remote UART is not using CTS auto flow control, we must
2339 * have sufficient FIFO entries for the latency of the remote
2340 * UART to respond. IOW, at least 32 bytes of FIFO.
2341 */
2342 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2343 up->mcr &= ~UART_MCR_AFE;
2344 if (termios->c_cflag & CRTSCTS)
2345 up->mcr |= UART_MCR_AFE;
2346 }
2347
2348 /*
2349 * Ok, we're now changing the port state. Do it with
2350 * interrupts disabled.
2351 */
2352 spin_lock_irqsave(&up->port.lock, flags);
2353
2354 /*
2355 * Update the per-port timeout.
2356 */
2357 uart_update_timeout(port, termios->c_cflag, baud);
2358
2359 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2360 if (termios->c_iflag & INPCK)
2361 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2362 if (termios->c_iflag & (BRKINT | PARMRK))
2363 up->port.read_status_mask |= UART_LSR_BI;
2364
2365 /*
2366 * Characteres to ignore
2367 */
2368 up->port.ignore_status_mask = 0;
2369 if (termios->c_iflag & IGNPAR)
2370 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2371 if (termios->c_iflag & IGNBRK) {
2372 up->port.ignore_status_mask |= UART_LSR_BI;
2373 /*
2374 * If we're ignoring parity and break indicators,
2375 * ignore overruns too (for real raw support).
2376 */
2377 if (termios->c_iflag & IGNPAR)
2378 up->port.ignore_status_mask |= UART_LSR_OE;
2379 }
2380
2381 /*
2382 * ignore all characters if CREAD is not set
2383 */
2384 if ((termios->c_cflag & CREAD) == 0)
2385 up->port.ignore_status_mask |= UART_LSR_DR;
2386
2387 /*
2388 * CTS flow control flag and modem status interrupts
2389 */
f8b372a1 2390 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2391 if (!(up->bugs & UART_BUG_NOMSR) &&
2392 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2393 up->ier |= UART_IER_MSI;
2394 if (up->capabilities & UART_CAP_UUE)
2395 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2396
2397 serial_out(up, UART_IER, up->ier);
2398
2399 if (up->capabilities & UART_CAP_EFR) {
2400 unsigned char efr = 0;
2401 /*
2402 * TI16C752/Startech hardware flow control. FIXME:
2403 * - TI16C752 requires control thresholds to be set.
2404 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2405 */
2406 if (termios->c_cflag & CRTSCTS)
2407 efr |= UART_EFR_CTS;
2408
662b083a 2409 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 2410 serial_outp(up, UART_EFR, efr);
2411 }
2412
f2eda27d 2413#ifdef CONFIG_ARCH_OMAP
255341c6 2414 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
5668545a 2415 if (cpu_is_omap1510() && is_omap_port(up)) {
255341c6
JM		 2416 if (baud == 115200) {
2417 quot = 1;
2418 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2419 } else
2420 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2421 }
2422#endif
2423
1da177e4
LT		 2424 if (up->capabilities & UART_NATSEMI) {
2425 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2426 serial_outp(up, UART_LCR, 0xe0);
2427 } else {
2428 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2429 }
2430
b32b19b8 2431 serial_dl_write(up, quot);
1da177e4
LT		 2432
2433 /*
2434 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2435 * is written without DLAB set, this mode will be disabled.
2436 */
2437 if (up->port.type == PORT_16750)
2438 serial_outp(up, UART_FCR, fcr);
2439
2440 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2441 up->lcr = cval; /* Save LCR */
2442 if (up->port.type != PORT_16750) {
2443 if (fcr & UART_FCR_ENABLE_FIFO) {
2444 /* emulated UARTs (Lucent Venus 167x) need two steps */
2445 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2446 }
2447 serial_outp(up, UART_FCR, fcr); /* set fcr */
2448 }
2449 serial8250_set_mctrl(&up->port, up->port.mctrl);
2450 spin_unlock_irqrestore(&up->port.lock, flags);
e991a2bd
AC		 2451 /* Don't rewrite B0 */
2452 if (tty_termios_baud_rate(termios))
2453 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4 2454}
235dae5d
PL		 2455EXPORT_SYMBOL(serial8250_do_set_termios);
2456
2457static void
2458serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2459 struct ktermios *old)
2460{
2461 if (port->set_termios)
2462 port->set_termios(port, termios, old);
2463 else
2464 serial8250_do_set_termios(port, termios, old);
2465}
1da177e4 2466
dc77f161 2467static void
a0821df6 2468serial8250_set_ldisc(struct uart_port *port, int new)
dc77f161 2469{
a0821df6 2470 if (new == N_PPS) {
dc77f161
RG		 2471 port->flags |= UPF_HARDPPS_CD;
2472 serial8250_enable_ms(port);
2473 } else
2474 port->flags &= ~UPF_HARDPPS_CD;
2475}
2476
c161afe9
ML		 2477
2478void serial8250_do_pm(struct uart_port *port, unsigned int state,
2479 unsigned int oldstate)
1da177e4 2480{
49d5741b
JI		 2481 struct uart_8250_port *p =
2482 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2483
2484 serial8250_set_sleep(p, state != 0);
c161afe9
ML		 2485}
2486EXPORT_SYMBOL(serial8250_do_pm);
1da177e4 2487
c161afe9
ML		 2488static void
2489serial8250_pm(struct uart_port *port, unsigned int state,
2490 unsigned int oldstate)
2491{
2492 if (port->pm)
2493 port->pm(port, state, oldstate);
2494 else
2495 serial8250_do_pm(port, state, oldstate);
1da177e4
LT		 2496}
2497
f2eda27d
RK		 2498static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2499{
2500 if (pt->port.iotype == UPIO_AU)
b2b13cdf 2501 return 0x1000;
f2eda27d
RK		 2502#ifdef CONFIG_ARCH_OMAP
2503 if (is_omap_port(pt))
2504 return 0x16 << pt->port.regshift;
2505#endif
2506 return 8 << pt->port.regshift;
2507}
2508
1da177e4
LT		 2509/*
2510 * Resource handling.
2511 */
2512static int serial8250_request_std_resource(struct uart_8250_port *up)
2513{
f2eda27d 2514 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2515 int ret = 0;
2516
2517 switch (up->port.iotype) {
85835f44 2518 case UPIO_AU:
0b30d668
SS		 2519 case UPIO_TSI:
2520 case UPIO_MEM32:
1da177e4 2521 case UPIO_MEM:
beab697a 2522 case UPIO_DWAPB:
a3ae0fc3 2523 case UPIO_DWAPB32:
1da177e4
LT		 2524 if (!up->port.mapbase)
2525 break;
2526
2527 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2528 ret = -EBUSY;
2529 break;
2530 }
2531
2532 if (up->port.flags & UPF_IOREMAP) {
6f441fe9
AC		 2533 up->port.membase = ioremap_nocache(up->port.mapbase,
2534 size);
1da177e4
LT		 2535 if (!up->port.membase) {
2536 release_mem_region(up->port.mapbase, size);
2537 ret = -ENOMEM;
2538 }
2539 }
2540 break;
2541
2542 case UPIO_HUB6:
2543 case UPIO_PORT:
2544 if (!request_region(up->port.iobase, size, "serial"))
2545 ret = -EBUSY;
2546 break;
2547 }
2548 return ret;
2549}
2550
2551static void serial8250_release_std_resource(struct uart_8250_port *up)
2552{
f2eda27d 2553 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2554
2555 switch (up->port.iotype) {
85835f44 2556 case UPIO_AU:
0b30d668
SS		 2557 case UPIO_TSI:
2558 case UPIO_MEM32:
1da177e4 2559 case UPIO_MEM:
beab697a 2560 case UPIO_DWAPB:
a3ae0fc3 2561 case UPIO_DWAPB32:
1da177e4
LT		 2562 if (!up->port.mapbase)
2563 break;
2564
2565 if (up->port.flags & UPF_IOREMAP) {
2566 iounmap(up->port.membase);
2567 up->port.membase = NULL;
2568 }
2569
2570 release_mem_region(up->port.mapbase, size);
2571 break;
2572
2573 case UPIO_HUB6:
2574 case UPIO_PORT:
2575 release_region(up->port.iobase, size);
2576 break;
2577 }
2578}
2579
2580static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2581{
2582 unsigned long start = UART_RSA_BASE << up->port.regshift;
2583 unsigned int size = 8 << up->port.regshift;
0b30d668 2584 int ret = -EINVAL;
1da177e4
LT		 2585
2586 switch (up->port.iotype) {
1da177e4
LT		 2587 case UPIO_HUB6:
2588 case UPIO_PORT:
2589 start += up->port.iobase;
0b30d668
SS		 2590 if (request_region(start, size, "serial-rsa"))
2591 ret = 0;
2592 else
1da177e4
LT		 2593 ret = -EBUSY;
2594 break;
2595 }
2596
2597 return ret;
2598}
2599
2600static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2601{
2602 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2603 unsigned int size = 8 << up->port.regshift;
2604
2605 switch (up->port.iotype) {
1da177e4
LT		 2606 case UPIO_HUB6:
2607 case UPIO_PORT:
2608 release_region(up->port.iobase + offset, size);
2609 break;
2610 }
2611}
2612
2613static void serial8250_release_port(struct uart_port *port)
2614{
49d5741b
JI		 2615 struct uart_8250_port *up =
2616 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2617
2618 serial8250_release_std_resource(up);
2619 if (up->port.type == PORT_RSA)
2620 serial8250_release_rsa_resource(up);
2621}
2622
2623static int serial8250_request_port(struct uart_port *port)
2624{
49d5741b
JI		 2625 struct uart_8250_port *up =
2626 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2627 int ret = 0;
2628
2629 ret = serial8250_request_std_resource(up);
2630 if (ret == 0 && up->port.type == PORT_RSA) {
2631 ret = serial8250_request_rsa_resource(up);
2632 if (ret < 0)
2633 serial8250_release_std_resource(up);
2634 }
2635
2636 return ret;
2637}
2638
2639static void serial8250_config_port(struct uart_port *port, int flags)
2640{
49d5741b
JI		 2641 struct uart_8250_port *up =
2642 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2643 int probeflags = PROBE_ANY;
2644 int ret;
2645
1da177e4
LT		 2646 /*
2647 * Find the region that we can probe for. This in turn
2648 * tells us whether we can probe for the type of port.
2649 */
2650 ret = serial8250_request_std_resource(up);
2651 if (ret < 0)
2652 return;
2653
2654 ret = serial8250_request_rsa_resource(up);
2655 if (ret < 0)
2656 probeflags &= ~PROBE_RSA;
2657
b8e7e40a
AC		 2658 if (up->port.iotype != up->cur_iotype)
2659 set_io_from_upio(port);
2660
1da177e4
LT		 2661 if (flags & UART_CONFIG_TYPE)
2662 autoconfig(up, probeflags);
b2b13cdf 2663
b2b13cdf
ML		 2664 /* if access method is AU, it is a 16550 with a quirk */
2665 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2666 up->bugs |= UART_BUG_NOMSR;
b2b13cdf 2667
1da177e4
LT		 2668 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2669 autoconfig_irq(up);
2670
2671 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2672 serial8250_release_rsa_resource(up);
2673 if (up->port.type == PORT_UNKNOWN)
2674 serial8250_release_std_resource(up);
2675}
2676
2677static int
2678serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2679{
a62c4133 2680 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2681 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2682 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2683 ser->type == PORT_STARTECH)
2684 return -EINVAL;
2685 return 0;
2686}
2687
2688static const char *
2689serial8250_type(struct uart_port *port)
2690{
2691 int type = port->type;
2692
2693 if (type >= ARRAY_SIZE(uart_config))
2694 type = 0;
2695 return uart_config[type].name;
2696}
2697
2698static struct uart_ops serial8250_pops = {
2699 .tx_empty = serial8250_tx_empty,
2700 .set_mctrl = serial8250_set_mctrl,
2701 .get_mctrl = serial8250_get_mctrl,
2702 .stop_tx = serial8250_stop_tx,
2703 .start_tx = serial8250_start_tx,
2704 .stop_rx = serial8250_stop_rx,
2705 .enable_ms = serial8250_enable_ms,
2706 .break_ctl = serial8250_break_ctl,
2707 .startup = serial8250_startup,
2708 .shutdown = serial8250_shutdown,
2709 .set_termios = serial8250_set_termios,
dc77f161 2710 .set_ldisc = serial8250_set_ldisc,
1da177e4
LT		 2711 .pm = serial8250_pm,
2712 .type = serial8250_type,
2713 .release_port = serial8250_release_port,
2714 .request_port = serial8250_request_port,
2715 .config_port = serial8250_config_port,
2716 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2717#ifdef CONFIG_CONSOLE_POLL
2718 .poll_get_char = serial8250_get_poll_char,
2719 .poll_put_char = serial8250_put_poll_char,
2720#endif
1da177e4
LT		 2721};
2722
2723static struct uart_8250_port serial8250_ports[UART_NR];
2724
af7f3743
AC		 2725static void (*serial8250_isa_config)(int port, struct uart_port *up,
2726 unsigned short *capabilities);
2727
2728void serial8250_set_isa_configurator(
2729 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2730{
2731 serial8250_isa_config = v;
2732}
2733EXPORT_SYMBOL(serial8250_set_isa_configurator);
2734
1da177e4
LT		 2735static void __init serial8250_isa_init_ports(void)
2736{
2737 struct uart_8250_port *up;
2738 static int first = 1;
4c0ebb80 2739 int i, irqflag = 0;
1da177e4
LT		 2740
2741 if (!first)
2742 return;
2743 first = 0;
2744
a61c2d78 2745 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2746 struct uart_8250_port *up = &serial8250_ports[i];
2747
2748 up->port.line = i;
2749 spin_lock_init(&up->port.lock);
2750
2751 init_timer(&up->timer);
2752 up->timer.function = serial8250_timeout;
2753
2754 /*
2755 * ALPHA_KLUDGE_MCR needs to be killed.
2756 */
2757 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2758 up->mcr_force = ALPHA_KLUDGE_MCR;
2759
2760 up->port.ops = &serial8250_pops;
2761 }
2762
4c0ebb80
AGR		 2763 if (share_irqs)
2764 irqflag = IRQF_SHARED;
2765
44454bcd 2766 for (i = 0, up = serial8250_ports;
a61c2d78 2767 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2768 i++, up++) {
2769 up->port.iobase = old_serial_port[i].port;
2770 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
1c2f0493 2771 up->port.irqflags = old_serial_port[i].irqflags;
1da177e4
LT		 2772 up->port.uartclk = old_serial_port[i].baud_base * 16;
2773 up->port.flags = old_serial_port[i].flags;
2774 up->port.hub6 = old_serial_port[i].hub6;
2775 up->port.membase = old_serial_port[i].iomem_base;
2776 up->port.iotype = old_serial_port[i].io_type;
2777 up->port.regshift = old_serial_port[i].iomem_reg_shift;
7d6a07d1 2778 set_io_from_upio(&up->port);
4c0ebb80 2779 up->port.irqflags |= irqflag;
af7f3743
AC		 2780 if (serial8250_isa_config != NULL)
2781 serial8250_isa_config(i, &up->port, &up->capabilities);
2782
1da177e4
LT		 2783 }
2784}
2785
b5d228cc
SL		 2786static void
2787serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2788{
2789 up->port.type = type;
2790 up->port.fifosize = uart_config[type].fifo_size;
2791 up->capabilities = uart_config[type].flags;
2792 up->tx_loadsz = uart_config[type].tx_loadsz;
2793}
2794
1da177e4
LT		 2795static void __init
2796serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2797{
2798 int i;
2799
b8e7e40a
AC		 2800 for (i = 0; i < nr_uarts; i++) {
2801 struct uart_8250_port *up = &serial8250_ports[i];
2802 up->cur_iotype = 0xFF;
2803 }
2804
1da177e4
LT		 2805 serial8250_isa_init_ports();
2806
a61c2d78 2807 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2808 struct uart_8250_port *up = &serial8250_ports[i];
2809
2810 up->port.dev = dev;
b5d228cc
SL		 2811
2812 if (up->port.flags & UPF_FIXED_TYPE)
2813 serial8250_init_fixed_type_port(up, up->port.type);
2814
1da177e4
LT		 2815 uart_add_one_port(drv, &up->port);
2816 }
2817}
2818
2819#ifdef CONFIG_SERIAL_8250_CONSOLE
2820
d358788f
RK		 2821static void serial8250_console_putchar(struct uart_port *port, int ch)
2822{
49d5741b
JI		 2823 struct uart_8250_port *up =
2824 container_of(port, struct uart_8250_port, port);
d358788f
RK		 2825
2826 wait_for_xmitr(up, UART_LSR_THRE);
2827 serial_out(up, UART_TX, ch);
2828}
2829
1da177e4
LT		 2830/*
2831 * Print a string to the serial port trying not to disturb
2832 * any possible real use of the port...
2833 *
2834 * The console_lock must be held when we get here.
2835 */
2836static void
2837serial8250_console_write(struct console *co, const char *s, unsigned int count)
2838{
2839 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2840 unsigned long flags;
1da177e4 2841 unsigned int ier;
d8a5a8d7 2842 int locked = 1;
1da177e4 2843
78512ece
AM		 2844 touch_nmi_watchdog();
2845
68aa2c0d
AM		 2846 local_irq_save(flags);
2847 if (up->port.sysrq) {
2848 /* serial8250_handle_port() already took the lock */
2849 locked = 0;
2850 } else if (oops_in_progress) {
2851 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2852 } else
68aa2c0d 2853 spin_lock(&up->port.lock);
d8a5a8d7 2854
1da177e4 2855 /*
dc7bf130 2856 * First save the IER then disable the interrupts
1da177e4
LT		 2857 */
2858 ier = serial_in(up, UART_IER);
2859
2860 if (up->capabilities & UART_CAP_UUE)
2861 serial_out(up, UART_IER, UART_IER_UUE);
2862 else
2863 serial_out(up, UART_IER, 0);
2864
d358788f 2865 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2866
2867 /*
2868 * Finally, wait for transmitter to become empty
2869 * and restore the IER
2870 */
f91a3715 2871 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2872 serial_out(up, UART_IER, ier);
d8a5a8d7 2873
ad4c2aa6
CM		 2874 /*
2875 * The receive handling will happen properly because the
2876 * receive ready bit will still be set; it is not cleared
2877 * on read. However, modem control will not, we must
2878 * call it if we have saved something in the saved flags
2879 * while processing with interrupts off.
2880 */
2881 if (up->msr_saved_flags)
2882 check_modem_status(up);
2883
d8a5a8d7 2884 if (locked)
68aa2c0d
AM		 2885 spin_unlock(&up->port.lock);
2886 local_irq_restore(flags);
1da177e4
LT		 2887}
2888
118c0ace 2889static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2890{
2891 struct uart_port *port;
2892 int baud = 9600;
2893 int bits = 8;
2894 int parity = 'n';
2895 int flow = 'n';
2896
2897 /*
2898 * Check whether an invalid uart number has been specified, and
2899 * if so, search for the first available port that does have
2900 * console support.
2901 */
a61c2d78 2902 if (co->index >= nr_uarts)
1da177e4
LT		 2903 co->index = 0;
2904 port = &serial8250_ports[co->index].port;
2905 if (!port->iobase && !port->membase)
2906 return -ENODEV;
2907
2908 if (options)
2909 uart_parse_options(options, &baud, &parity, &bits, &flow);
2910
2911 return uart_set_options(port, co, baud, parity, bits, flow);
2912}
2913
b6b1d877 2914static int serial8250_console_early_setup(void)
18a8bd94
YL		 2915{
2916 return serial8250_find_port_for_earlycon();
2917}
2918
1da177e4
LT		 2919static struct console serial8250_console = {
2920 .name = "ttyS",
2921 .write = serial8250_console_write,
2922 .device = uart_console_device,
2923 .setup = serial8250_console_setup,
18a8bd94 2924 .early_setup = serial8250_console_early_setup,
a80c49db 2925 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2926 .index = -1,
2927 .data = &serial8250_reg,
2928};
2929
2930static int __init serial8250_console_init(void)
2931{
05d81d22
EB		 2932 if (nr_uarts > UART_NR)
2933 nr_uarts = UART_NR;
2934
1da177e4
LT		 2935 serial8250_isa_init_ports();
2936 register_console(&serial8250_console);
2937 return 0;
2938}
2939console_initcall(serial8250_console_init);
2940
18a8bd94 2941int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2942{
2943 int line;
2944 struct uart_port *port;
2945
a61c2d78 2946 for (line = 0; line < nr_uarts; line++) {
1da177e4 2947 port = &serial8250_ports[line].port;
50aec3b5 2948 if (uart_match_port(p, port))
1da177e4
LT		 2949 return line;
2950 }
2951 return -ENODEV;
2952}
2953
1da177e4
LT		 2954#define SERIAL8250_CONSOLE &serial8250_console
2955#else
2956#define SERIAL8250_CONSOLE NULL
2957#endif
2958
2959static struct uart_driver serial8250_reg = {
2960 .owner = THIS_MODULE,
2961 .driver_name = "serial",
1da177e4
LT		 2962 .dev_name = "ttyS",
2963 .major = TTY_MAJOR,
2964 .minor = 64,
1da177e4
LT		 2965 .cons = SERIAL8250_CONSOLE,
2966};
2967
d856c666
RK		 2968/*
2969 * early_serial_setup - early registration for 8250 ports
2970 *
2971 * Setup an 8250 port structure prior to console initialisation. Use
2972 * after console initialisation will cause undefined behaviour.
2973 */
1da177e4
LT		 2974int __init early_serial_setup(struct uart_port *port)
2975{
b430428a
DD		 2976 struct uart_port *p;
2977
1da177e4
LT		 2978 if (port->line >= ARRAY_SIZE(serial8250_ports))
2979 return -ENODEV;
2980
2981 serial8250_isa_init_ports();
b430428a
DD		 2982 p = &serial8250_ports[port->line].port;
2983 p->iobase = port->iobase;
2984 p->membase = port->membase;
2985 p->irq = port->irq;
1c2f0493 2986 p->irqflags = port->irqflags;
b430428a
DD		 2987 p->uartclk = port->uartclk;
2988 p->fifosize = port->fifosize;
2989 p->regshift = port->regshift;
2990 p->iotype = port->iotype;
2991 p->flags = port->flags;
2992 p->mapbase = port->mapbase;
2993 p->private_data = port->private_data;
125c97d8
HD		 2994 p->type = port->type;
2995 p->line = port->line;
7d6a07d1
DD		 2996
2997 set_io_from_upio(p);
2998 if (port->serial_in)
2999 p->serial_in = port->serial_in;
3000 if (port->serial_out)
3001 p->serial_out = port->serial_out;
3002
1da177e4
LT		 3003 return 0;
3004}
3005
3006/**
3007 * serial8250_suspend_port - suspend one serial port
3008 * @line: serial line number
1da177e4
LT		 3009 *
3010 * Suspend one serial port.
3011 */
3012void serial8250_suspend_port(int line)
3013{
3014 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3015}
3016
3017/**
3018 * serial8250_resume_port - resume one serial port
3019 * @line: serial line number
1da177e4
LT		 3020 *
3021 * Resume one serial port.
3022 */
3023void serial8250_resume_port(int line)
3024{
b5b82df6
DW		 3025 struct uart_8250_port *up = &serial8250_ports[line];
3026
3027 if (up->capabilities & UART_NATSEMI) {
3028 unsigned char tmp;
3029
3030 /* Ensure it's still in high speed mode */
3031 serial_outp(up, UART_LCR, 0xE0);
3032
3033 tmp = serial_in(up, 0x04); /* EXCR2 */
3034 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
3035 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
3036 serial_outp(up, 0x04, tmp);
3037
3038 serial_outp(up, UART_LCR, 0);
3039 }
3040 uart_resume_port(&serial8250_reg, &up->port);
1da177e4
LT		 3041}
3042
3043/*
3044 * Register a set of serial devices attached to a platform device. The
3045 * list is terminated with a zero flags entry, which means we expect
3046 * all entries to have at least UPF_BOOT_AUTOCONF set.
3047 */
3ae5eaec 3048static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 3049{
3ae5eaec 3050 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 3051 struct uart_port port;
4c0ebb80 3052 int ret, i, irqflag = 0;
1da177e4
LT		 3053
3054 memset(&port, 0, sizeof(struct uart_port));
3055
4c0ebb80
AGR		 3056 if (share_irqs)
3057 irqflag = IRQF_SHARED;
3058
ec9f47cd 3059 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 3060 port.iobase = p->iobase;
3061 port.membase = p->membase;
3062 port.irq = p->irq;
1c2f0493 3063 port.irqflags = p->irqflags;
74a19741
WN		 3064 port.uartclk = p->uartclk;
3065 port.regshift = p->regshift;
3066 port.iotype = p->iotype;
3067 port.flags = p->flags;
3068 port.mapbase = p->mapbase;
3069 port.hub6 = p->hub6;
3070 port.private_data = p->private_data;
8e23fcc8 3071 port.type = p->type;
7d6a07d1
DD		 3072 port.serial_in = p->serial_in;
3073 port.serial_out = p->serial_out;
235dae5d 3074 port.set_termios = p->set_termios;
c161afe9 3075 port.pm = p->pm;
74a19741 3076 port.dev = &dev->dev;
4c0ebb80 3077 port.irqflags |= irqflag;
ec9f47cd
RK		 3078 ret = serial8250_register_port(&port);
3079 if (ret < 0) {
3ae5eaec 3080 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 3081 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3082 p->iobase, (unsigned long long)p->mapbase,
3083 p->irq, ret);
ec9f47cd 3084 }
1da177e4
LT		 3085 }
3086 return 0;
3087}
3088
3089/*
3090 * Remove serial ports registered against a platform device.
3091 */
3ae5eaec 3092static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 3093{
3094 int i;
3095
a61c2d78 3096 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 3097 struct uart_8250_port *up = &serial8250_ports[i];
3098
3ae5eaec 3099 if (up->port.dev == &dev->dev)
1da177e4
LT		 3100 serial8250_unregister_port(i);
3101 }
3102 return 0;
3103}
3104
3ae5eaec 3105static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 3106{
3107 int i;
3108
1da177e4
LT		 3109 for (i = 0; i < UART_NR; i++) {
3110 struct uart_8250_port *up = &serial8250_ports[i];
3111
3ae5eaec 3112 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3113 uart_suspend_port(&serial8250_reg, &up->port);
3114 }
3115
3116 return 0;
3117}
3118
3ae5eaec 3119static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3120{
3121 int i;
3122
1da177e4
LT		 3123 for (i = 0; i < UART_NR; i++) {
3124 struct uart_8250_port *up = &serial8250_ports[i];
3125
3ae5eaec 3126 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3127 serial8250_resume_port(i);
1da177e4
LT		 3128 }
3129
3130 return 0;
3131}
3132
3ae5eaec 3133static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 3134 .probe = serial8250_probe,
3135 .remove = __devexit_p(serial8250_remove),
3136 .suspend = serial8250_suspend,
3137 .resume = serial8250_resume,
3ae5eaec
RK		 3138 .driver = {
3139 .name = "serial8250",
7493a314 3140 .owner = THIS_MODULE,
3ae5eaec 3141 },
1da177e4
LT		 3142};
3143
3144/*
3145 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3146 * in the table in include/asm/serial.h
3147 */
3148static struct platform_device *serial8250_isa_devs;
3149
3150/*
3151 * serial8250_register_port and serial8250_unregister_port allows for
3152 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3153 * modems and PCI multiport cards.
3154 */
f392ecfa 3155static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3156
3157static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3158{
3159 int i;
3160
3161 /*
3162 * First, find a port entry which matches.
3163 */
a61c2d78 3164 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3165 if (uart_match_port(&serial8250_ports[i].port, port))
3166 return &serial8250_ports[i];
3167
3168 /*
3169 * We didn't find a matching entry, so look for the first
3170 * free entry. We look for one which hasn't been previously
3171 * used (indicated by zero iobase).
3172 */
a61c2d78 3173 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3174 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3175 serial8250_ports[i].port.iobase == 0)
3176 return &serial8250_ports[i];
3177
3178 /*
3179 * That also failed. Last resort is to find any entry which
3180 * doesn't have a real port associated with it.
3181 */
a61c2d78 3182 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3183 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3184 return &serial8250_ports[i];
3185
3186 return NULL;
3187}
3188
3189/**
3190 * serial8250_register_port - register a serial port
3191 * @port: serial port template
3192 *
3193 * Configure the serial port specified by the request. If the
3194 * port exists and is in use, it is hung up and unregistered
3195 * first.
3196 *
3197 * The port is then probed and if necessary the IRQ is autodetected
3198 * If this fails an error is returned.
3199 *
3200 * On success the port is ready to use and the line number is returned.
3201 */
3202int serial8250_register_port(struct uart_port *port)
3203{
3204 struct uart_8250_port *uart;
3205 int ret = -ENOSPC;
3206
3207 if (port->uartclk == 0)
3208 return -EINVAL;
3209
f392ecfa 3210 mutex_lock(&serial_mutex);
1da177e4
LT		 3211
3212 uart = serial8250_find_match_or_unused(port);
3213 if (uart) {
3214 uart_remove_one_port(&serial8250_reg, &uart->port);
3215
74a19741
WN		 3216 uart->port.iobase = port->iobase;
3217 uart->port.membase = port->membase;
3218 uart->port.irq = port->irq;
1c2f0493 3219 uart->port.irqflags = port->irqflags;
74a19741
WN		 3220 uart->port.uartclk = port->uartclk;
3221 uart->port.fifosize = port->fifosize;
3222 uart->port.regshift = port->regshift;
3223 uart->port.iotype = port->iotype;
3224 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3225 uart->port.mapbase = port->mapbase;
3226 uart->port.private_data = port->private_data;
1da177e4
LT		 3227 if (port->dev)
3228 uart->port.dev = port->dev;
8e23fcc8 3229
b5d228cc
SL		 3230 if (port->flags & UPF_FIXED_TYPE)
3231 serial8250_init_fixed_type_port(uart, port->type);
8e23fcc8 3232
7d6a07d1
DD		 3233 set_io_from_upio(&uart->port);
3234 /* Possibly override default I/O functions. */
3235 if (port->serial_in)
3236 uart->port.serial_in = port->serial_in;
3237 if (port->serial_out)
3238 uart->port.serial_out = port->serial_out;
235dae5d
PL		 3239 /* Possibly override set_termios call */
3240 if (port->set_termios)
3241 uart->port.set_termios = port->set_termios;
c161afe9
ML		 3242 if (port->pm)
3243 uart->port.pm = port->pm;
1da177e4 3244
af7f3743
AC		 3245 if (serial8250_isa_config != NULL)
3246 serial8250_isa_config(0, &uart->port,
3247 &uart->capabilities);
3248
1da177e4
LT		 3249 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3250 if (ret == 0)
3251 ret = uart->port.line;
3252 }
f392ecfa 3253 mutex_unlock(&serial_mutex);
1da177e4
LT		 3254
3255 return ret;
3256}
3257EXPORT_SYMBOL(serial8250_register_port);
3258
3259/**
3260 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3261 * @line: serial line number
3262 *
3263 * Remove one serial port. This may not be called from interrupt
3264 * context. We hand the port back to the our control.
3265 */
3266void serial8250_unregister_port(int line)
3267{
3268 struct uart_8250_port *uart = &serial8250_ports[line];
3269
f392ecfa 3270 mutex_lock(&serial_mutex);
1da177e4
LT		 3271 uart_remove_one_port(&serial8250_reg, &uart->port);
3272 if (serial8250_isa_devs) {
3273 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3274 uart->port.type = PORT_UNKNOWN;
3275 uart->port.dev = &serial8250_isa_devs->dev;
3276 uart_add_one_port(&serial8250_reg, &uart->port);
3277 } else {
3278 uart->port.dev = NULL;
3279 }
f392ecfa 3280 mutex_unlock(&serial_mutex);
1da177e4
LT		 3281}
3282EXPORT_SYMBOL(serial8250_unregister_port);
3283
3284static int __init serial8250_init(void)
3285{
25db8ad5 3286 int ret;
1da177e4 3287
a61c2d78
DJ		 3288 if (nr_uarts > UART_NR)
3289 nr_uarts = UART_NR;
3290
f1fb9bb8 3291 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3292 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3293 share_irqs ? "en" : "dis");
3294
b70ac771
DM		 3295#ifdef CONFIG_SPARC
3296 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3297#else
3298 serial8250_reg.nr = UART_NR;
1da177e4 3299 ret = uart_register_driver(&serial8250_reg);
b70ac771 3300#endif
1da177e4
LT		 3301 if (ret)
3302 goto out;
3303
7493a314
DT		 3304 serial8250_isa_devs = platform_device_alloc("serial8250",
3305 PLAT8250_DEV_LEGACY);
3306 if (!serial8250_isa_devs) {
3307 ret = -ENOMEM;
bc965a7f 3308 goto unreg_uart_drv;
1da177e4
LT		 3309 }
3310
7493a314
DT		 3311 ret = platform_device_add(serial8250_isa_devs);
3312 if (ret)
3313 goto put_dev;
3314
1da177e4
LT		 3315 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3316
bc965a7f
RK		 3317 ret = platform_driver_register(&serial8250_isa_driver);
3318 if (ret == 0)
3319 goto out;
1da177e4 3320
bc965a7f 3321 platform_device_del(serial8250_isa_devs);
25db8ad5 3322put_dev:
7493a314 3323 platform_device_put(serial8250_isa_devs);
25db8ad5 3324unreg_uart_drv:
b70ac771
DM		 3325#ifdef CONFIG_SPARC
3326 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3327#else
1da177e4 3328 uart_unregister_driver(&serial8250_reg);
b70ac771 3329#endif
25db8ad5 3330out:
1da177e4
LT		 3331 return ret;
3332}
3333
3334static void __exit serial8250_exit(void)
3335{
3336 struct platform_device *isa_dev = serial8250_isa_devs;
3337
3338 /*
3339 * This tells serial8250_unregister_port() not to re-register
3340 * the ports (thereby making serial8250_isa_driver permanently
3341 * in use.)
3342 */
3343 serial8250_isa_devs = NULL;
3344
3ae5eaec 3345 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3346 platform_device_unregister(isa_dev);
3347
b70ac771
DM		 3348#ifdef CONFIG_SPARC
3349 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3350#else
1da177e4 3351 uart_unregister_driver(&serial8250_reg);
b70ac771 3352#endif
1da177e4
LT		 3353}
3354
3355module_init(serial8250_init);
3356module_exit(serial8250_exit);
3357
3358EXPORT_SYMBOL(serial8250_suspend_port);
3359EXPORT_SYMBOL(serial8250_resume_port);
3360
3361MODULE_LICENSE("GPL");
d87a6d95 3362MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3363
3364module_param(share_irqs, uint, 0644);
3365MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3366 " (unsafe)");
3367
a61c2d78
DJ		 3368module_param(nr_uarts, uint, 0644);
3369MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3370
d41a4b51
CE		 3371module_param(skip_txen_test, uint, 0644);
3372MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3373
1da177e4
LT		 3374#ifdef CONFIG_SERIAL_8250_RSA
3375module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3376MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3377#endif
3378MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux kernel - Deliverables
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