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serial: export the key functions for an 8250 IRQ handler
[deliverable/linux.git] / drivers / tty / serial / 8250.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
1da177e4
LT		 13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
1da177e4
LT		 18
19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
1da177e4 29#include <linux/delay.h>
d052d1be 30#include <linux/platform_device.h>
1da177e4 31#include <linux/tty.h>
cd3ecad1 32#include <linux/ratelimit.h>
1da177e4
LT		 33#include <linux/tty_flip.h>
34#include <linux/serial_reg.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
78512ece 38#include <linux/nmi.h>
f392ecfa 39#include <linux/mutex.h>
5a0e3ad6 40#include <linux/slab.h>
1da177e4
LT		 41
42#include <asm/io.h>
43#include <asm/irq.h>
44
45#include "8250.h"
46
b70ac771
DM		 47#ifdef CONFIG_SPARC
48#include "suncore.h"
49#endif
50
1da177e4
LT		 51/*
52 * Configuration:
40663cc7 53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 54 * is unsafe when used on edge-triggered interrupts.
55 */
408b664a 56static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 57
a61c2d78
DJ		 58static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
8440838b
DM		 60static struct uart_driver serial8250_reg;
61
62static int serial_index(struct uart_port *port)
63{
64 return (serial8250_reg.minor - 64) + port->line;
65}
66
d41a4b51
CE		 67static unsigned int skip_txen_test; /* force skip of txen test at init time */
68
1da177e4
LT		 69/*
70 * Debugging.
71 */
72#if 0
73#define DEBUG_AUTOCONF(fmt...) printk(fmt)
74#else
75#define DEBUG_AUTOCONF(fmt...) do { } while (0)
76#endif
77
78#if 0
79#define DEBUG_INTR(fmt...) printk(fmt)
80#else
81#define DEBUG_INTR(fmt...) do { } while (0)
82#endif
83
e7328ae1 84#define PASS_LIMIT 512
1da177e4 85
bca47613
DH		 86#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
87
88
1da177e4
LT		 89/*
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
93 */
94#define is_real_interrupt(irq) ((irq) != 0)
95
1da177e4
LT		 96#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97#define CONFIG_SERIAL_DETECT_IRQ 1
98#endif
1da177e4
LT		 99#ifdef CONFIG_SERIAL_8250_MANY_PORTS
100#define CONFIG_SERIAL_MANY_PORTS 1
101#endif
102
103/*
104 * HUB6 is always on. This will be removed once the header
105 * files have been cleaned.
106 */
107#define CONFIG_HUB6 1
108
a4ed1e41 109#include <asm/serial.h>
1da177e4
LT		 110/*
111 * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 * standard enumeration mechanism. Platforms that can find all
113 * serial ports via mechanisms like ACPI or PCI need not supply it.
114 */
115#ifndef SERIAL_PORT_DFNS
116#define SERIAL_PORT_DFNS
117#endif
118
cb3592be 119static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 120 SERIAL_PORT_DFNS /* defined in asm/serial.h */
121};
122
026d02a2 123#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 124
125#ifdef CONFIG_SERIAL_8250_RSA
126
127#define PORT_RSA_MAX 4
128static unsigned long probe_rsa[PORT_RSA_MAX];
129static unsigned int probe_rsa_count;
130#endif /* CONFIG_SERIAL_8250_RSA */
131
1da177e4 132struct irq_info {
25db8ad5
AC		 133 struct hlist_node node;
134 int irq;
135 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 136 struct list_head *head;
137};
138
25db8ad5
AC		 139#define NR_IRQ_HASH 32 /* Can be adjusted later */
140static struct hlist_head irq_lists[NR_IRQ_HASH];
141static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 142
143/*
144 * Here we define the default xmit fifo size used for each type of UART.
145 */
146static const struct serial8250_config uart_config[] = {
147 [PORT_UNKNOWN] = {
148 .name = "unknown",
149 .fifo_size = 1,
150 .tx_loadsz = 1,
151 },
152 [PORT_8250] = {
153 .name = "8250",
154 .fifo_size = 1,
155 .tx_loadsz = 1,
156 },
157 [PORT_16450] = {
158 .name = "16450",
159 .fifo_size = 1,
160 .tx_loadsz = 1,
161 },
162 [PORT_16550] = {
163 .name = "16550",
164 .fifo_size = 1,
165 .tx_loadsz = 1,
166 },
167 [PORT_16550A] = {
168 .name = "16550A",
169 .fifo_size = 16,
170 .tx_loadsz = 16,
171 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
172 .flags = UART_CAP_FIFO,
173 },
174 [PORT_CIRRUS] = {
175 .name = "Cirrus",
176 .fifo_size = 1,
177 .tx_loadsz = 1,
178 },
179 [PORT_16650] = {
180 .name = "ST16650",
181 .fifo_size = 1,
182 .tx_loadsz = 1,
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184 },
185 [PORT_16650V2] = {
186 .name = "ST16650V2",
187 .fifo_size = 32,
188 .tx_loadsz = 16,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
190 UART_FCR_T_TRIG_00,
191 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
192 },
193 [PORT_16750] = {
194 .name = "TI16750",
195 .fifo_size = 64,
196 .tx_loadsz = 64,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
198 UART_FCR7_64BYTE,
199 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
200 },
201 [PORT_STARTECH] = {
202 .name = "Startech",
203 .fifo_size = 1,
204 .tx_loadsz = 1,
205 },
206 [PORT_16C950] = {
207 .name = "16C950/954",
208 .fifo_size = 128,
209 .tx_loadsz = 128,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
d0694e2a
PM		 211 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
212 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
1da177e4
LT		 213 },
214 [PORT_16654] = {
215 .name = "ST16654",
216 .fifo_size = 64,
217 .tx_loadsz = 32,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
219 UART_FCR_T_TRIG_10,
220 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
221 },
222 [PORT_16850] = {
223 .name = "XR16850",
224 .fifo_size = 128,
225 .tx_loadsz = 128,
226 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
227 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
228 },
229 [PORT_RSA] = {
230 .name = "RSA",
231 .fifo_size = 2048,
232 .tx_loadsz = 2048,
233 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
234 .flags = UART_CAP_FIFO,
235 },
236 [PORT_NS16550A] = {
237 .name = "NS16550A",
238 .fifo_size = 16,
239 .tx_loadsz = 16,
240 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
241 .flags = UART_CAP_FIFO | UART_NATSEMI,
242 },
243 [PORT_XSCALE] = {
244 .name = "XScale",
245 .fifo_size = 32,
246 .tx_loadsz = 32,
247 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
4539c24f 248 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
1da177e4 249 },
bd71c182
TK		 250 [PORT_RM9000] = {
251 .name = "RM9000",
252 .fifo_size = 16,
253 .tx_loadsz = 16,
254 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 255 .flags = UART_CAP_FIFO,
256 },
257 [PORT_OCTEON] = {
258 .name = "OCTEON",
259 .fifo_size = 64,
260 .tx_loadsz = 64,
261 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 262 .flags = UART_CAP_FIFO,
263 },
08e0992f
FF		 264 [PORT_AR7] = {
265 .name = "AR7",
266 .fifo_size = 16,
267 .tx_loadsz = 16,
268 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
269 .flags = UART_CAP_FIFO | UART_CAP_AFE,
270 },
235dae5d
PL		 271 [PORT_U6_16550A] = {
272 .name = "U6_16550A",
273 .fifo_size = 64,
274 .tx_loadsz = 64,
275 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
276 .flags = UART_CAP_FIFO | UART_CAP_AFE,
277 },
4539c24f
SW		 278 [PORT_TEGRA] = {
279 .name = "Tegra",
280 .fifo_size = 32,
281 .tx_loadsz = 8,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
283 UART_FCR_T_TRIG_01,
284 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
285 },
06315348
SH		 286 [PORT_XR17D15X] = {
287 .name = "XR17D15X",
288 .fifo_size = 64,
289 .tx_loadsz = 64,
290 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
291 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
292 },
1da177e4
LT		 293};
294
12bf3f24 295#if defined(CONFIG_MIPS_ALCHEMY)
21c614a7
PA		 296
297/* Au1x00 UART hardware has a weird register layout */
298static const u8 au_io_in_map[] = {
299 [UART_RX] = 0,
300 [UART_IER] = 2,
301 [UART_IIR] = 3,
302 [UART_LCR] = 5,
303 [UART_MCR] = 6,
304 [UART_LSR] = 7,
305 [UART_MSR] = 8,
306};
307
308static const u8 au_io_out_map[] = {
309 [UART_TX] = 1,
310 [UART_IER] = 2,
311 [UART_FCR] = 4,
312 [UART_LCR] = 5,
313 [UART_MCR] = 6,
314};
315
316/* sane hardware needs no mapping */
7d6a07d1 317static inline int map_8250_in_reg(struct uart_port *p, int offset)
21c614a7 318{
7d6a07d1 319 if (p->iotype != UPIO_AU)
21c614a7
PA		 320 return offset;
321 return au_io_in_map[offset];
322}
323
7d6a07d1 324static inline int map_8250_out_reg(struct uart_port *p, int offset)
21c614a7 325{
7d6a07d1 326 if (p->iotype != UPIO_AU)
21c614a7
PA		 327 return offset;
328 return au_io_out_map[offset];
329}
330
6f803cd0 331#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 332
333static const u8
334 regmap_in[8] = {
335 [UART_RX] = 0x00,
336 [UART_IER] = 0x0c,
337 [UART_IIR] = 0x14,
338 [UART_LCR] = 0x1c,
339 [UART_MCR] = 0x20,
340 [UART_LSR] = 0x24,
341 [UART_MSR] = 0x28,
342 [UART_SCR] = 0x2c
343 },
344 regmap_out[8] = {
345 [UART_TX] = 0x04,
346 [UART_IER] = 0x0c,
347 [UART_FCR] = 0x18,
348 [UART_LCR] = 0x1c,
349 [UART_MCR] = 0x20,
350 [UART_LSR] = 0x24,
351 [UART_MSR] = 0x28,
352 [UART_SCR] = 0x2c
353 };
354
7d6a07d1 355static inline int map_8250_in_reg(struct uart_port *p, int offset)
bd71c182 356{
7d6a07d1 357 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 358 return offset;
359 return regmap_in[offset];
360}
361
7d6a07d1 362static inline int map_8250_out_reg(struct uart_port *p, int offset)
bd71c182 363{
7d6a07d1 364 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 365 return offset;
366 return regmap_out[offset];
367}
368
21c614a7
PA		 369#else
370
371/* sane hardware needs no mapping */
372#define map_8250_in_reg(up, offset) (offset)
373#define map_8250_out_reg(up, offset) (offset)
374
375#endif
376
7d6a07d1 377static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 378{
7d6a07d1
DD		 379 offset = map_8250_in_reg(p, offset) << p->regshift;
380 outb(p->hub6 - 1 + offset, p->iobase);
381 return inb(p->iobase + 1);
382}
1da177e4 383
7d6a07d1
DD		 384static void hub6_serial_out(struct uart_port *p, int offset, int value)
385{
386 offset = map_8250_out_reg(p, offset) << p->regshift;
387 outb(p->hub6 - 1 + offset, p->iobase);
388 outb(value, p->iobase + 1);
389}
1da177e4 390
7d6a07d1
DD		 391static unsigned int mem_serial_in(struct uart_port *p, int offset)
392{
393 offset = map_8250_in_reg(p, offset) << p->regshift;
394 return readb(p->membase + offset);
395}
1da177e4 396
7d6a07d1
DD		 397static void mem_serial_out(struct uart_port *p, int offset, int value)
398{
399 offset = map_8250_out_reg(p, offset) << p->regshift;
400 writeb(value, p->membase + offset);
401}
402
403static void mem32_serial_out(struct uart_port *p, int offset, int value)
404{
405 offset = map_8250_out_reg(p, offset) << p->regshift;
406 writel(value, p->membase + offset);
407}
408
409static unsigned int mem32_serial_in(struct uart_port *p, int offset)
410{
411 offset = map_8250_in_reg(p, offset) << p->regshift;
412 return readl(p->membase + offset);
413}
1da177e4 414
7d6a07d1
DD		 415static unsigned int au_serial_in(struct uart_port *p, int offset)
416{
417 offset = map_8250_in_reg(p, offset) << p->regshift;
418 return __raw_readl(p->membase + offset);
419}
420
421static void au_serial_out(struct uart_port *p, int offset, int value)
422{
423 offset = map_8250_out_reg(p, offset) << p->regshift;
424 __raw_writel(value, p->membase + offset);
425}
21c614a7 426
7d6a07d1
DD		 427static unsigned int io_serial_in(struct uart_port *p, int offset)
428{
429 offset = map_8250_in_reg(p, offset) << p->regshift;
430 return inb(p->iobase + offset);
431}
432
433static void io_serial_out(struct uart_port *p, int offset, int value)
434{
435 offset = map_8250_out_reg(p, offset) << p->regshift;
436 outb(value, p->iobase + offset);
437}
438
583d28e9
JI		 439static int serial8250_default_handle_irq(struct uart_port *port);
440
7d6a07d1
DD		 441static void set_io_from_upio(struct uart_port *p)
442{
49d5741b
JI		 443 struct uart_8250_port *up =
444 container_of(p, struct uart_8250_port, port);
7d6a07d1 445 switch (p->iotype) {
1da177e4 446 case UPIO_HUB6:
7d6a07d1
DD		 447 p->serial_in = hub6_serial_in;
448 p->serial_out = hub6_serial_out;
1da177e4
LT		 449 break;
450
451 case UPIO_MEM:
7d6a07d1
DD		 452 p->serial_in = mem_serial_in;
453 p->serial_out = mem_serial_out;
1da177e4
LT		 454 break;
455
bd71c182 456 case UPIO_RM9000:
1da177e4 457 case UPIO_MEM32:
7d6a07d1
DD		 458 p->serial_in = mem32_serial_in;
459 p->serial_out = mem32_serial_out;
1da177e4
LT		 460 break;
461
21c614a7 462 case UPIO_AU:
7d6a07d1
DD		 463 p->serial_in = au_serial_in;
464 p->serial_out = au_serial_out;
21c614a7 465 break;
12bf3f24 466
1da177e4 467 default:
7d6a07d1
DD		 468 p->serial_in = io_serial_in;
469 p->serial_out = io_serial_out;
470 break;
1da177e4 471 }
b8e7e40a
AC		 472 /* Remember loaded iotype */
473 up->cur_iotype = p->iotype;
583d28e9 474 p->handle_irq = serial8250_default_handle_irq;
1da177e4
LT		 475}
476
40b36daa
AW		 477static void
478serial_out_sync(struct uart_8250_port *up, int offset, int value)
479{
7d6a07d1
DD		 480 struct uart_port *p = &up->port;
481 switch (p->iotype) {
40b36daa
AW		 482 case UPIO_MEM:
483 case UPIO_MEM32:
40b36daa 484 case UPIO_AU:
7d6a07d1
DD		 485 p->serial_out(p, offset, value);
486 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 487 break;
488 default:
7d6a07d1 489 p->serial_out(p, offset, value);
40b36daa
AW		 490 }
491}
492
7d6a07d1
DD		 493#define serial_in(up, offset) \
494 (up->port.serial_in(&(up)->port, (offset)))
495#define serial_out(up, offset, value) \
496 (up->port.serial_out(&(up)->port, (offset), (value)))
1da177e4
LT		 497/*
498 * We used to support using pause I/O for certain machines. We
499 * haven't supported this for a while, but just in case it's badly
500 * needed for certain old 386 machines, I've left these #define's
501 * in....
502 */
503#define serial_inp(up, offset) serial_in(up, offset)
504#define serial_outp(up, offset, value) serial_out(up, offset, value)
505
b32b19b8
JAH		 506/* Uart divisor latch read */
507static inline int _serial_dl_read(struct uart_8250_port *up)
508{
509 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
510}
511
512/* Uart divisor latch write */
513static inline void _serial_dl_write(struct uart_8250_port *up, int value)
514{
515 serial_outp(up, UART_DLL, value & 0xff);
516 serial_outp(up, UART_DLM, value >> 8 & 0xff);
517}
518
12bf3f24 519#if defined(CONFIG_MIPS_ALCHEMY)
b32b19b8
JAH		 520/* Au1x00 haven't got a standard divisor latch */
521static int serial_dl_read(struct uart_8250_port *up)
522{
523 if (up->port.iotype == UPIO_AU)
524 return __raw_readl(up->port.membase + 0x28);
525 else
526 return _serial_dl_read(up);
527}
528
529static void serial_dl_write(struct uart_8250_port *up, int value)
530{
531 if (up->port.iotype == UPIO_AU)
532 __raw_writel(value, up->port.membase + 0x28);
533 else
534 _serial_dl_write(up, value);
535}
6f803cd0 536#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 537static int serial_dl_read(struct uart_8250_port *up)
538{
539 return (up->port.iotype == UPIO_RM9000) ?
540 (((__raw_readl(up->port.membase + 0x10) << 8) |
541 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
542 _serial_dl_read(up);
543}
544
545static void serial_dl_write(struct uart_8250_port *up, int value)
546{
547 if (up->port.iotype == UPIO_RM9000) {
548 __raw_writel(value, up->port.membase + 0x08);
549 __raw_writel(value >> 8, up->port.membase + 0x10);
550 } else {
551 _serial_dl_write(up, value);
552 }
553}
b32b19b8
JAH		 554#else
555#define serial_dl_read(up) _serial_dl_read(up)
556#define serial_dl_write(up, value) _serial_dl_write(up, value)
557#endif
1da177e4
LT		 558
559/*
560 * For the 16C950
561 */
562static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
563{
564 serial_out(up, UART_SCR, offset);
565 serial_out(up, UART_ICR, value);
566}
567
568static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
569{
570 unsigned int value;
571
572 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
573 serial_out(up, UART_SCR, offset);
574 value = serial_in(up, UART_ICR);
575 serial_icr_write(up, UART_ACR, up->acr);
576
577 return value;
578}
579
580/*
581 * FIFO support.
582 */
b5d674ab 583static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 584{
585 if (p->capabilities & UART_CAP_FIFO) {
586 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
587 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
588 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
589 serial_outp(p, UART_FCR, 0);
590 }
591}
592
593/*
594 * IER sleep support. UARTs which have EFRs need the "extended
595 * capability" bit enabled. Note that on XR16C850s, we need to
596 * reset LCR to write to IER.
597 */
b5d674ab 598static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4
LT		 599{
600 if (p->capabilities & UART_CAP_SLEEP) {
601 if (p->capabilities & UART_CAP_EFR) {
662b083a 602 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 603 serial_outp(p, UART_EFR, UART_EFR_ECB);
604 serial_outp(p, UART_LCR, 0);
605 }
606 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
607 if (p->capabilities & UART_CAP_EFR) {
662b083a 608 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 609 serial_outp(p, UART_EFR, 0);
610 serial_outp(p, UART_LCR, 0);
611 }
612 }
613}
614
615#ifdef CONFIG_SERIAL_8250_RSA
616/*
617 * Attempts to turn on the RSA FIFO. Returns zero on failure.
618 * We set the port uart clock rate if we succeed.
619 */
620static int __enable_rsa(struct uart_8250_port *up)
621{
622 unsigned char mode;
623 int result;
624
625 mode = serial_inp(up, UART_RSA_MSR);
626 result = mode & UART_RSA_MSR_FIFO;
627
628 if (!result) {
629 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
630 mode = serial_inp(up, UART_RSA_MSR);
631 result = mode & UART_RSA_MSR_FIFO;
632 }
633
634 if (result)
635 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
636
637 return result;
638}
639
640static void enable_rsa(struct uart_8250_port *up)
641{
642 if (up->port.type == PORT_RSA) {
643 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
644 spin_lock_irq(&up->port.lock);
645 __enable_rsa(up);
646 spin_unlock_irq(&up->port.lock);
647 }
648 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
649 serial_outp(up, UART_RSA_FRR, 0);
650 }
651}
652
653/*
654 * Attempts to turn off the RSA FIFO. Returns zero on failure.
655 * It is unknown why interrupts were disabled in here. However,
656 * the caller is expected to preserve this behaviour by grabbing
657 * the spinlock before calling this function.
658 */
659static void disable_rsa(struct uart_8250_port *up)
660{
661 unsigned char mode;
662 int result;
663
664 if (up->port.type == PORT_RSA &&
665 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
666 spin_lock_irq(&up->port.lock);
667
668 mode = serial_inp(up, UART_RSA_MSR);
669 result = !(mode & UART_RSA_MSR_FIFO);
670
671 if (!result) {
672 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
673 mode = serial_inp(up, UART_RSA_MSR);
674 result = !(mode & UART_RSA_MSR_FIFO);
675 }
676
677 if (result)
678 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
679 spin_unlock_irq(&up->port.lock);
680 }
681}
682#endif /* CONFIG_SERIAL_8250_RSA */
683
684/*
685 * This is a quickie test to see how big the FIFO is.
686 * It doesn't work at all the time, more's the pity.
687 */
688static int size_fifo(struct uart_8250_port *up)
689{
b32b19b8
JAH		 690 unsigned char old_fcr, old_mcr, old_lcr;
691 unsigned short old_dl;
1da177e4
LT		 692 int count;
693
694 old_lcr = serial_inp(up, UART_LCR);
695 serial_outp(up, UART_LCR, 0);
696 old_fcr = serial_inp(up, UART_FCR);
697 old_mcr = serial_inp(up, UART_MCR);
698 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
699 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
700 serial_outp(up, UART_MCR, UART_MCR_LOOP);
662b083a 701 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8
JAH		 702 old_dl = serial_dl_read(up);
703 serial_dl_write(up, 0x0001);
1da177e4
LT		 704 serial_outp(up, UART_LCR, 0x03);
705 for (count = 0; count < 256; count++)
706 serial_outp(up, UART_TX, count);
707 mdelay(20);/* FIXME - schedule_timeout */
708 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
709 (count < 256); count++)
710 serial_inp(up, UART_RX);
711 serial_outp(up, UART_FCR, old_fcr);
712 serial_outp(up, UART_MCR, old_mcr);
662b083a 713 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8 714 serial_dl_write(up, old_dl);
1da177e4
LT		 715 serial_outp(up, UART_LCR, old_lcr);
716
717 return count;
718}
719
720/*
721 * Read UART ID using the divisor method - set DLL and DLM to zero
722 * and the revision will be in DLL and device type in DLM. We
723 * preserve the device state across this.
724 */
725static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
726{
727 unsigned char old_dll, old_dlm, old_lcr;
728 unsigned int id;
729
730 old_lcr = serial_inp(p, UART_LCR);
662b083a 731 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 732
733 old_dll = serial_inp(p, UART_DLL);
734 old_dlm = serial_inp(p, UART_DLM);
735
736 serial_outp(p, UART_DLL, 0);
737 serial_outp(p, UART_DLM, 0);
738
739 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
740
741 serial_outp(p, UART_DLL, old_dll);
742 serial_outp(p, UART_DLM, old_dlm);
743 serial_outp(p, UART_LCR, old_lcr);
744
745 return id;
746}
747
748/*
749 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
750 * When this function is called we know it is at least a StarTech
751 * 16650 V2, but it might be one of several StarTech UARTs, or one of
752 * its clones. (We treat the broken original StarTech 16650 V1 as a
753 * 16550, and why not? Startech doesn't seem to even acknowledge its
754 * existence.)
bd71c182 755 *
1da177e4
LT		 756 * What evil have men's minds wrought...
757 */
758static void autoconfig_has_efr(struct uart_8250_port *up)
759{
760 unsigned int id1, id2, id3, rev;
761
762 /*
763 * Everything with an EFR has SLEEP
764 */
765 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
766
767 /*
768 * First we check to see if it's an Oxford Semiconductor UART.
769 *
770 * If we have to do this here because some non-National
771 * Semiconductor clone chips lock up if you try writing to the
772 * LSR register (which serial_icr_read does)
773 */
774
775 /*
776 * Check for Oxford Semiconductor 16C950.
777 *
778 * EFR [4] must be set else this test fails.
779 *
780 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
781 * claims that it's needed for 952 dual UART's (which are not
782 * recommended for new designs).
783 */
784 up->acr = 0;
662b083a 785 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 786 serial_out(up, UART_EFR, UART_EFR_ECB);
787 serial_out(up, UART_LCR, 0x00);
788 id1 = serial_icr_read(up, UART_ID1);
789 id2 = serial_icr_read(up, UART_ID2);
790 id3 = serial_icr_read(up, UART_ID3);
791 rev = serial_icr_read(up, UART_REV);
792
793 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
794
795 if (id1 == 0x16 && id2 == 0xC9 &&
796 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
797 up->port.type = PORT_16C950;
4ba5e35d
RK		 798
799 /*
800 * Enable work around for the Oxford Semiconductor 952 rev B
801 * chip which causes it to seriously miscalculate baud rates
802 * when DLL is 0.
803 */
804 if (id3 == 0x52 && rev == 0x01)
805 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 806 return;
807 }
bd71c182 808
1da177e4
LT		 809 /*
810 * We check for a XR16C850 by setting DLL and DLM to 0, and then
811 * reading back DLL and DLM. The chip type depends on the DLM
812 * value read back:
813 * 0x10 - XR16C850 and the DLL contains the chip revision.
814 * 0x12 - XR16C2850.
815 * 0x14 - XR16C854.
816 */
817 id1 = autoconfig_read_divisor_id(up);
818 DEBUG_AUTOCONF("850id=%04x ", id1);
819
820 id2 = id1 >> 8;
821 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 822 up->port.type = PORT_16850;
823 return;
824 }
825
826 /*
827 * It wasn't an XR16C850.
828 *
829 * We distinguish between the '654 and the '650 by counting
830 * how many bytes are in the FIFO. I'm using this for now,
831 * since that's the technique that was sent to me in the
832 * serial driver update, but I'm not convinced this works.
833 * I've had problems doing this in the past. -TYT
834 */
835 if (size_fifo(up) == 64)
836 up->port.type = PORT_16654;
837 else
838 up->port.type = PORT_16650V2;
839}
840
841/*
842 * We detected a chip without a FIFO. Only two fall into
843 * this category - the original 8250 and the 16450. The
844 * 16450 has a scratch register (accessible with LCR=0)
845 */
846static void autoconfig_8250(struct uart_8250_port *up)
847{
848 unsigned char scratch, status1, status2;
849
850 up->port.type = PORT_8250;
851
852 scratch = serial_in(up, UART_SCR);
853 serial_outp(up, UART_SCR, 0xa5);
854 status1 = serial_in(up, UART_SCR);
855 serial_outp(up, UART_SCR, 0x5a);
856 status2 = serial_in(up, UART_SCR);
857 serial_outp(up, UART_SCR, scratch);
858
859 if (status1 == 0xa5 && status2 == 0x5a)
860 up->port.type = PORT_16450;
861}
862
863static int broken_efr(struct uart_8250_port *up)
864{
865 /*
866 * Exar ST16C2550 "A2" devices incorrectly detect as
867 * having an EFR, and report an ID of 0x0201. See
631dd1a8 868 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1da177e4
LT		 869 */
870 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
871 return 1;
872
873 return 0;
874}
875
0d0389e5
YK		 876static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
877{
878 unsigned char status;
879
880 status = serial_in(up, 0x04); /* EXCR2 */
881#define PRESL(x) ((x) & 0x30)
882 if (PRESL(status) == 0x10) {
883 /* already in high speed mode */
884 return 0;
885 } else {
886 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
887 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
888 serial_outp(up, 0x04, status);
889 }
890 return 1;
891}
892
1da177e4
LT		 893/*
894 * We know that the chip has FIFOs. Does it have an EFR? The
895 * EFR is located in the same register position as the IIR and
896 * we know the top two bits of the IIR are currently set. The
897 * EFR should contain zero. Try to read the EFR.
898 */
899static void autoconfig_16550a(struct uart_8250_port *up)
900{
901 unsigned char status1, status2;
902 unsigned int iersave;
903
904 up->port.type = PORT_16550A;
905 up->capabilities |= UART_CAP_FIFO;
906
907 /*
908 * Check for presence of the EFR when DLAB is set.
909 * Only ST16C650V1 UARTs pass this test.
910 */
662b083a 911 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 912 if (serial_in(up, UART_EFR) == 0) {
913 serial_outp(up, UART_EFR, 0xA8);
914 if (serial_in(up, UART_EFR) != 0) {
915 DEBUG_AUTOCONF("EFRv1 ");
916 up->port.type = PORT_16650;
917 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
918 } else {
919 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
920 }
921 serial_outp(up, UART_EFR, 0);
922 return;
923 }
924
925 /*
926 * Maybe it requires 0xbf to be written to the LCR.
927 * (other ST16C650V2 UARTs, TI16C752A, etc)
928 */
662b083a 929 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 930 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
931 DEBUG_AUTOCONF("EFRv2 ");
932 autoconfig_has_efr(up);
933 return;
934 }
935
936 /*
937 * Check for a National Semiconductor SuperIO chip.
938 * Attempt to switch to bank 2, read the value of the LOOP bit
939 * from EXCR1. Switch back to bank 0, change it in MCR. Then
940 * switch back to bank 2, read it from EXCR1 again and check
941 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 942 */
943 serial_outp(up, UART_LCR, 0);
944 status1 = serial_in(up, UART_MCR);
945 serial_outp(up, UART_LCR, 0xE0);
946 status2 = serial_in(up, 0x02); /* EXCR1 */
947
948 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
949 serial_outp(up, UART_LCR, 0);
950 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
951 serial_outp(up, UART_LCR, 0xE0);
952 status2 = serial_in(up, 0x02); /* EXCR1 */
953 serial_outp(up, UART_LCR, 0);
954 serial_outp(up, UART_MCR, status1);
955
956 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 957 unsigned short quot;
958
1da177e4 959 serial_outp(up, UART_LCR, 0xE0);
857dde2e 960
b32b19b8 961 quot = serial_dl_read(up);
857dde2e
DW		 962 quot <<= 3;
963
0d0389e5
YK		 964 if (ns16550a_goto_highspeed(up))
965 serial_dl_write(up, quot);
857dde2e 966
1da177e4 967 serial_outp(up, UART_LCR, 0);
1da177e4 968
857dde2e 969 up->port.uartclk = 921600*16;
1da177e4
LT		 970 up->port.type = PORT_NS16550A;
971 up->capabilities |= UART_NATSEMI;
972 return;
973 }
974 }
975
976 /*
977 * No EFR. Try to detect a TI16750, which only sets bit 5 of
978 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
979 * Try setting it with and without DLAB set. Cheap clones
980 * set bit 5 without DLAB set.
981 */
982 serial_outp(up, UART_LCR, 0);
983 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
984 status1 = serial_in(up, UART_IIR) >> 5;
985 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
662b083a 986 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 987 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
988 status2 = serial_in(up, UART_IIR) >> 5;
989 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
990 serial_outp(up, UART_LCR, 0);
991
992 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
993
994 if (status1 == 6 && status2 == 7) {
995 up->port.type = PORT_16750;
996 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
997 return;
998 }
999
1000 /*
1001 * Try writing and reading the UART_IER_UUE bit (b6).
1002 * If it works, this is probably one of the Xscale platform's
1003 * internal UARTs.
1004 * We're going to explicitly set the UUE bit to 0 before
1005 * trying to write and read a 1 just to make sure it's not
1006 * already a 1 and maybe locked there before we even start start.
1007 */
1008 iersave = serial_in(up, UART_IER);
1009 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1010 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1011 /*
1012 * OK it's in a known zero state, try writing and reading
1013 * without disturbing the current state of the other bits.
1014 */
1015 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1016 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1017 /*
1018 * It's an Xscale.
1019 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1020 */
1021 DEBUG_AUTOCONF("Xscale ");
1022 up->port.type = PORT_XSCALE;
5568181f 1023 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1da177e4
LT		 1024 return;
1025 }
1026 } else {
1027 /*
1028 * If we got here we couldn't force the IER_UUE bit to 0.
1029 * Log it and continue.
1030 */
1031 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1032 }
1033 serial_outp(up, UART_IER, iersave);
235dae5d 1034
06315348
SH		 1035 /*
1036 * Exar uarts have EFR in a weird location
1037 */
1038 if (up->port.flags & UPF_EXAR_EFR) {
1039 up->port.type = PORT_XR17D15X;
1040 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1041 }
1042
235dae5d
PL		 1043 /*
1044 * We distinguish between 16550A and U6 16550A by counting
1045 * how many bytes are in the FIFO.
1046 */
1047 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1048 up->port.type = PORT_U6_16550A;
1049 up->capabilities |= UART_CAP_AFE;
1050 }
1da177e4
LT		 1051}
1052
1053/*
1054 * This routine is called by rs_init() to initialize a specific serial
1055 * port. It determines what type of UART chip this serial port is
1056 * using: 8250, 16450, 16550, 16550A. The important question is
1057 * whether or not this UART is a 16550A or not, since this will
1058 * determine whether or not we can use its FIFO features or not.
1059 */
1060static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1061{
1062 unsigned char status1, scratch, scratch2, scratch3;
1063 unsigned char save_lcr, save_mcr;
1064 unsigned long flags;
1065
1066 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1067 return;
1068
80647b95 1069 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
8440838b 1070 serial_index(&up->port), up->port.iobase, up->port.membase);
1da177e4
LT		 1071
1072 /*
1073 * We really do need global IRQs disabled here - we're going to
1074 * be frobbing the chips IRQ enable register to see if it exists.
1075 */
1076 spin_lock_irqsave(&up->port.lock, flags);
1da177e4
LT		 1077
1078 up->capabilities = 0;
4ba5e35d 1079 up->bugs = 0;
1da177e4
LT		 1080
1081 if (!(up->port.flags & UPF_BUGGY_UART)) {
1082 /*
1083 * Do a simple existence test first; if we fail this,
1084 * there's no point trying anything else.
bd71c182 1085 *
1da177e4
LT		 1086 * 0x80 is used as a nonsense port to prevent against
1087 * false positives due to ISA bus float. The
1088 * assumption is that 0x80 is a non-existent port;
1089 * which should be safe since include/asm/io.h also
1090 * makes this assumption.
1091 *
1092 * Note: this is safe as long as MCR bit 4 is clear
1093 * and the device is in "PC" mode.
1094 */
1095 scratch = serial_inp(up, UART_IER);
1096 serial_outp(up, UART_IER, 0);
1097#ifdef __i386__
1098 outb(0xff, 0x080);
1099#endif
48212008
TH		 1100 /*
1101 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1102 * 16C754B) allow only to modify them if an EFR bit is set.
1103 */
1104 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1105 serial_outp(up, UART_IER, 0x0F);
1106#ifdef __i386__
1107 outb(0, 0x080);
1108#endif
48212008 1109 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1110 serial_outp(up, UART_IER, scratch);
1111 if (scratch2 != 0 || scratch3 != 0x0F) {
1112 /*
1113 * We failed; there's nothing here
1114 */
1115 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1116 scratch2, scratch3);
1117 goto out;
1118 }
1119 }
1120
1121 save_mcr = serial_in(up, UART_MCR);
1122 save_lcr = serial_in(up, UART_LCR);
1123
bd71c182 1124 /*
1da177e4
LT		 1125 * Check to see if a UART is really there. Certain broken
1126 * internal modems based on the Rockwell chipset fail this
1127 * test, because they apparently don't implement the loopback
1128 * test mode. So this test is skipped on the COM 1 through
1129 * COM 4 ports. This *should* be safe, since no board
1130 * manufacturer would be stupid enough to design a board
1131 * that conflicts with COM 1-4 --- we hope!
1132 */
1133 if (!(up->port.flags & UPF_SKIP_TEST)) {
1134 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1135 status1 = serial_inp(up, UART_MSR) & 0xF0;
1136 serial_outp(up, UART_MCR, save_mcr);
1137 if (status1 != 0x90) {
1138 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1139 status1);
1140 goto out;
1141 }
1142 }
1143
1144 /*
1145 * We're pretty sure there's a port here. Lets find out what
1146 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1147 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1148 * determines what we test for next.
1149 *
1150 * We also initialise the EFR (if any) to zero for later. The
1151 * EFR occupies the same register location as the FCR and IIR.
1152 */
662b083a 1153 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 1154 serial_outp(up, UART_EFR, 0);
1155 serial_outp(up, UART_LCR, 0);
1156
1157 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1158 scratch = serial_in(up, UART_IIR) >> 6;
1159
1160 DEBUG_AUTOCONF("iir=%d ", scratch);
1161
1162 switch (scratch) {
1163 case 0:
1164 autoconfig_8250(up);
1165 break;
1166 case 1:
1167 up->port.type = PORT_UNKNOWN;
1168 break;
1169 case 2:
1170 up->port.type = PORT_16550;
1171 break;
1172 case 3:
1173 autoconfig_16550a(up);
1174 break;
1175 }
1176
1177#ifdef CONFIG_SERIAL_8250_RSA
1178 /*
1179 * Only probe for RSA ports if we got the region.
1180 */
1181 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1182 int i;
1183
1184 for (i = 0 ; i < probe_rsa_count; ++i) {
1185 if (probe_rsa[i] == up->port.iobase &&
1186 __enable_rsa(up)) {
1187 up->port.type = PORT_RSA;
1188 break;
1189 }
1190 }
1191 }
1192#endif
21c614a7 1193
1da177e4
LT		 1194 serial_outp(up, UART_LCR, save_lcr);
1195
1196 if (up->capabilities != uart_config[up->port.type].flags) {
1197 printk(KERN_WARNING
1198 "ttyS%d: detected caps %08x should be %08x\n",
8440838b
DM		 1199 serial_index(&up->port), up->capabilities,
1200 uart_config[up->port.type].flags);
1da177e4
LT		 1201 }
1202
1203 up->port.fifosize = uart_config[up->port.type].fifo_size;
1204 up->capabilities = uart_config[up->port.type].flags;
1205 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1206
1207 if (up->port.type == PORT_UNKNOWN)
1208 goto out;
1209
1210 /*
1211 * Reset the UART.
1212 */
1213#ifdef CONFIG_SERIAL_8250_RSA
1214 if (up->port.type == PORT_RSA)
1215 serial_outp(up, UART_RSA_FRR, 0);
1216#endif
1217 serial_outp(up, UART_MCR, save_mcr);
1218 serial8250_clear_fifos(up);
40b36daa 1219 serial_in(up, UART_RX);
5c8c755c
LB		 1220 if (up->capabilities & UART_CAP_UUE)
1221 serial_outp(up, UART_IER, UART_IER_UUE);
1222 else
1223 serial_outp(up, UART_IER, 0);
1da177e4 1224
bd71c182 1225 out:
1da177e4 1226 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1227 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1228}
1229
1230static void autoconfig_irq(struct uart_8250_port *up)
1231{
1232 unsigned char save_mcr, save_ier;
1233 unsigned char save_ICP = 0;
1234 unsigned int ICP = 0;
1235 unsigned long irqs;
1236 int irq;
1237
1238 if (up->port.flags & UPF_FOURPORT) {
1239 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1240 save_ICP = inb_p(ICP);
1241 outb_p(0x80, ICP);
1242 (void) inb_p(ICP);
1243 }
1244
1245 /* forget possible initially masked and pending IRQ */
1246 probe_irq_off(probe_irq_on());
1247 save_mcr = serial_inp(up, UART_MCR);
1248 save_ier = serial_inp(up, UART_IER);
1249 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1250
1da177e4
LT		 1251 irqs = probe_irq_on();
1252 serial_outp(up, UART_MCR, 0);
6f803cd0
AC		 1253 udelay(10);
1254 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 1255 serial_outp(up, UART_MCR,
1256 UART_MCR_DTR | UART_MCR_RTS);
1257 } else {
1258 serial_outp(up, UART_MCR,
1259 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1260 }
1261 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1262 (void)serial_inp(up, UART_LSR);
1263 (void)serial_inp(up, UART_RX);
1264 (void)serial_inp(up, UART_IIR);
1265 (void)serial_inp(up, UART_MSR);
1266 serial_outp(up, UART_TX, 0xFF);
6f803cd0 1267 udelay(20);
1da177e4
LT		 1268 irq = probe_irq_off(irqs);
1269
1270 serial_outp(up, UART_MCR, save_mcr);
1271 serial_outp(up, UART_IER, save_ier);
1272
1273 if (up->port.flags & UPF_FOURPORT)
1274 outb_p(save_ICP, ICP);
1275
1276 up->port.irq = (irq > 0) ? irq : 0;
1277}
1278
e763b90c
RK		 1279static inline void __stop_tx(struct uart_8250_port *p)
1280{
1281 if (p->ier & UART_IER_THRI) {
1282 p->ier &= ~UART_IER_THRI;
1283 serial_out(p, UART_IER, p->ier);
1284 }
1285}
1286
b129a8cc 1287static void serial8250_stop_tx(struct uart_port *port)
1da177e4 1288{
49d5741b
JI		 1289 struct uart_8250_port *up =
1290 container_of(port, struct uart_8250_port, port);
1da177e4 1291
e763b90c 1292 __stop_tx(up);
1da177e4
LT		 1293
1294 /*
e763b90c 1295 * We really want to stop the transmitter from sending.
1da177e4 1296 */
e763b90c 1297 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1298 up->acr |= UART_ACR_TXDIS;
1299 serial_icr_write(up, UART_ACR, up->acr);
1300 }
1301}
1302
b129a8cc 1303static void serial8250_start_tx(struct uart_port *port)
1da177e4 1304{
49d5741b
JI		 1305 struct uart_8250_port *up =
1306 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1307
1308 if (!(up->ier & UART_IER_THRI)) {
1309 up->ier |= UART_IER_THRI;
1310 serial_out(up, UART_IER, up->ier);
55d3b282 1311
67f7654e 1312 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1313 unsigned char lsr;
55d3b282 1314 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1315 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
bd71c182 1316 if ((up->port.type == PORT_RM9000) ?
68cb4f8e
IJ		 1317 (lsr & UART_LSR_THRE) :
1318 (lsr & UART_LSR_TEMT))
3986fb2b 1319 serial8250_tx_chars(up);
55d3b282 1320 }
1da177e4 1321 }
e763b90c 1322
1da177e4 1323 /*
e763b90c 1324 * Re-enable the transmitter if we disabled it.
1da177e4 1325 */
e763b90c 1326 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1327 up->acr &= ~UART_ACR_TXDIS;
1328 serial_icr_write(up, UART_ACR, up->acr);
1329 }
1330}
1331
1332static void serial8250_stop_rx(struct uart_port *port)
1333{
49d5741b
JI		 1334 struct uart_8250_port *up =
1335 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1336
1337 up->ier &= ~UART_IER_RLSI;
1338 up->port.read_status_mask &= ~UART_LSR_DR;
1339 serial_out(up, UART_IER, up->ier);
1340}
1341
1342static void serial8250_enable_ms(struct uart_port *port)
1343{
49d5741b
JI		 1344 struct uart_8250_port *up =
1345 container_of(port, struct uart_8250_port, port);
1da177e4 1346
21c614a7
PA		 1347 /* no MSR capabilities */
1348 if (up->bugs & UART_BUG_NOMSR)
1349 return;
1350
1da177e4
LT		 1351 up->ier |= UART_IER_MSI;
1352 serial_out(up, UART_IER, up->ier);
1353}
1354
5f873bae
SW		 1355/*
1356 * Clear the Tegra rx fifo after a break
1357 *
1358 * FIXME: This needs to become a port specific callback once we have a
1359 * framework for this
1360 */
1361static void clear_rx_fifo(struct uart_8250_port *up)
1362{
1363 unsigned int status, tmout = 10000;
1364 do {
1365 status = serial_in(up, UART_LSR);
1366 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1367 status = serial_in(up, UART_RX);
1368 else
1369 break;
1370 if (--tmout == 0)
1371 break;
1372 udelay(1);
1373 } while (1);
1374}
1375
0690f41f 1376/*
3986fb2b 1377 * serial8250_rx_chars: processes according to the passed in LSR
0690f41f
PG		 1378 * value, and returns the remaining LSR bits not handled
1379 * by this Rx routine.
1380 */
3986fb2b
PG		 1381unsigned char
1382serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1da177e4 1383{
ebd2c8f6 1384 struct tty_struct *tty = up->port.state->port.tty;
0690f41f 1385 unsigned char ch;
1da177e4
LT		 1386 int max_count = 256;
1387 char flag;
1388
1389 do {
7500b1f6
AR		 1390 if (likely(lsr & UART_LSR_DR))
1391 ch = serial_inp(up, UART_RX);
1392 else
1393 /*
1394 * Intel 82571 has a Serial Over Lan device that will
1395 * set UART_LSR_BI without setting UART_LSR_DR when
1396 * it receives a break. To avoid reading from the
1397 * receive buffer without UART_LSR_DR bit set, we
1398 * just force the read character to be 0
1399 */
1400 ch = 0;
1401
1da177e4
LT		 1402 flag = TTY_NORMAL;
1403 up->port.icount.rx++;
1404
ad4c2aa6
CM		 1405 lsr |= up->lsr_saved_flags;
1406 up->lsr_saved_flags = 0;
1da177e4 1407
ad4c2aa6 1408 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1409 /*
1410 * For statistics only
1411 */
1412 if (lsr & UART_LSR_BI) {
1413 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1414 up->port.icount.brk++;
5f873bae
SW		 1415 /*
1416 * If tegra port then clear the rx fifo to
1417 * accept another break/character.
1418 */
1419 if (up->port.type == PORT_TEGRA)
1420 clear_rx_fifo(up);
1421
1da177e4
LT		 1422 /*
1423 * We do the SysRQ and SAK checking
1424 * here because otherwise the break
1425 * may get masked by ignore_status_mask
1426 * or read_status_mask.
1427 */
1428 if (uart_handle_break(&up->port))
1429 goto ignore_char;
1430 } else if (lsr & UART_LSR_PE)
1431 up->port.icount.parity++;
1432 else if (lsr & UART_LSR_FE)
1433 up->port.icount.frame++;
1434 if (lsr & UART_LSR_OE)
1435 up->port.icount.overrun++;
1436
1437 /*
23907eb8 1438 * Mask off conditions which should be ignored.
1da177e4
LT		 1439 */
1440 lsr &= up->port.read_status_mask;
1441
1442 if (lsr & UART_LSR_BI) {
1443 DEBUG_INTR("handling break....");
1444 flag = TTY_BREAK;
1445 } else if (lsr & UART_LSR_PE)
1446 flag = TTY_PARITY;
1447 else if (lsr & UART_LSR_FE)
1448 flag = TTY_FRAME;
1449 }
7d12e780 1450 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1451 goto ignore_char;
05ab3014
RK		 1452
1453 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1454
6f803cd0 1455ignore_char:
1da177e4 1456 lsr = serial_inp(up, UART_LSR);
7500b1f6 1457 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1da177e4
LT		 1458 spin_unlock(&up->port.lock);
1459 tty_flip_buffer_push(tty);
1460 spin_lock(&up->port.lock);
0690f41f 1461 return lsr;
1da177e4 1462}
3986fb2b 1463EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1da177e4 1464
3986fb2b 1465void serial8250_tx_chars(struct uart_8250_port *up)
1da177e4 1466{
ebd2c8f6 1467 struct circ_buf *xmit = &up->port.state->xmit;
1da177e4
LT		 1468 int count;
1469
1470 if (up->port.x_char) {
1471 serial_outp(up, UART_TX, up->port.x_char);
1472 up->port.icount.tx++;
1473 up->port.x_char = 0;
1474 return;
1475 }
b129a8cc
RK		 1476 if (uart_tx_stopped(&up->port)) {
1477 serial8250_stop_tx(&up->port);
1478 return;
1479 }
1480 if (uart_circ_empty(xmit)) {
e763b90c 1481 __stop_tx(up);
1da177e4
LT		 1482 return;
1483 }
1484
1485 count = up->tx_loadsz;
1486 do {
1487 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1488 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1489 up->port.icount.tx++;
1490 if (uart_circ_empty(xmit))
1491 break;
1492 } while (--count > 0);
1493
1494 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1495 uart_write_wakeup(&up->port);
1496
1497 DEBUG_INTR("THRE...");
1498
1499 if (uart_circ_empty(xmit))
e763b90c 1500 __stop_tx(up);
1da177e4 1501}
3986fb2b 1502EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1da177e4 1503
3986fb2b 1504unsigned int serial8250_modem_status(struct uart_8250_port *up)
1da177e4 1505{
2af7cd68
RK		 1506 unsigned int status = serial_in(up, UART_MSR);
1507
ad4c2aa6
CM		 1508 status |= up->msr_saved_flags;
1509 up->msr_saved_flags = 0;
fdc30b3d 1510 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
ebd2c8f6 1511 up->port.state != NULL) {
2af7cd68
RK		 1512 if (status & UART_MSR_TERI)
1513 up->port.icount.rng++;
1514 if (status & UART_MSR_DDSR)
1515 up->port.icount.dsr++;
1516 if (status & UART_MSR_DDCD)
1517 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1518 if (status & UART_MSR_DCTS)
1519 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1520
bdc04e31 1521 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
2af7cd68 1522 }
1da177e4 1523
2af7cd68 1524 return status;
1da177e4 1525}
3986fb2b 1526EXPORT_SYMBOL_GPL(serial8250_modem_status);
1da177e4
LT		 1527
1528/*
1529 * This handles the interrupt from one port.
1530 */
b5d674ab 1531static void serial8250_handle_port(struct uart_8250_port *up)
1da177e4 1532{
0690f41f 1533 unsigned char status;
4bf3631c 1534 unsigned long flags;
45e24601 1535
4bf3631c 1536 spin_lock_irqsave(&up->port.lock, flags);
45e24601
RK		 1537
1538 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1539
1540 DEBUG_INTR("status = %x...", status);
1541
7500b1f6 1542 if (status & (UART_LSR_DR | UART_LSR_BI))
3986fb2b
PG		 1543 status = serial8250_rx_chars(up, status);
1544 serial8250_modem_status(up);
1da177e4 1545 if (status & UART_LSR_THRE)
3986fb2b 1546 serial8250_tx_chars(up);
45e24601 1547
4bf3631c 1548 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1549}
1550
583d28e9
JI		 1551int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1552{
1553 struct uart_8250_port *up =
1554 container_of(port, struct uart_8250_port, port);
1555
1556 if (!(iir & UART_IIR_NO_INT)) {
1557 serial8250_handle_port(up);
1558 return 1;
1559 }
1560
1561 return 0;
1562}
c7a1bdc5 1563EXPORT_SYMBOL_GPL(serial8250_handle_irq);
583d28e9
JI		 1564
1565static int serial8250_default_handle_irq(struct uart_port *port)
1566{
1567 struct uart_8250_port *up =
1568 container_of(port, struct uart_8250_port, port);
1569 unsigned int iir = serial_in(up, UART_IIR);
1570
1571 return serial8250_handle_irq(port, iir);
1572}
1573
1da177e4
LT		 1574/*
1575 * This is the serial driver's interrupt routine.
1576 *
1577 * Arjan thinks the old way was overly complex, so it got simplified.
1578 * Alan disagrees, saying that need the complexity to handle the weird
1579 * nature of ISA shared interrupts. (This is a special exception.)
1580 *
1581 * In order to handle ISA shared interrupts properly, we need to check
1582 * that all ports have been serviced, and therefore the ISA interrupt
1583 * line has been de-asserted.
1584 *
1585 * This means we need to loop through all ports. checking that they
1586 * don't have an interrupt pending.
1587 */
7d12e780 1588static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1589{
1590 struct irq_info *i = dev_id;
1591 struct list_head *l, *end = NULL;
1592 int pass_counter = 0, handled = 0;
1593
1594 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1595
1596 spin_lock(&i->lock);
1597
1598 l = i->head;
1599 do {
1600 struct uart_8250_port *up;
583d28e9 1601 struct uart_port *port;
448ac154 1602 bool skip;
1da177e4
LT		 1603
1604 up = list_entry(l, struct uart_8250_port, list);
583d28e9 1605 port = &up->port;
448ac154 1606 skip = pass_counter && up->port.flags & UPF_IIR_ONCE;
1da177e4 1607
448ac154 1608 if (!skip && port->handle_irq(port)) {
1da177e4 1609 handled = 1;
1da177e4
LT		 1610 end = NULL;
1611 } else if (end == NULL)
1612 end = l;
1613
1614 l = l->next;
1615
1616 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1617 /* If we hit this, we're dead. */
cd3ecad1
DD		 1618 printk_ratelimited(KERN_ERR
1619 "serial8250: too much work for irq%d\n", irq);
1da177e4
LT		 1620 break;
1621 }
1622 } while (l != end);
1623
1624 spin_unlock(&i->lock);
1625
1626 DEBUG_INTR("end.\n");
1627
1628 return IRQ_RETVAL(handled);
1629}
1630
1631/*
1632 * To support ISA shared interrupts, we need to have one interrupt
1633 * handler that ensures that the IRQ line has been deasserted
1634 * before returning. Failing to do this will result in the IRQ
1635 * line being stuck active, and, since ISA irqs are edge triggered,
1636 * no more IRQs will be seen.
1637 */
1638static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1639{
1640 spin_lock_irq(&i->lock);
1641
1642 if (!list_empty(i->head)) {
1643 if (i->head == &up->list)
1644 i->head = i->head->next;
1645 list_del(&up->list);
1646 } else {
1647 BUG_ON(i->head != &up->list);
1648 i->head = NULL;
1649 }
1da177e4 1650 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1651 /* List empty so throw away the hash node */
1652 if (i->head == NULL) {
1653 hlist_del(&i->node);
1654 kfree(i);
1655 }
1da177e4
LT		 1656}
1657
1658static int serial_link_irq_chain(struct uart_8250_port *up)
1659{
25db8ad5
AC		 1660 struct hlist_head *h;
1661 struct hlist_node *n;
1662 struct irq_info *i;
40663cc7 1663 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1664
25db8ad5
AC		 1665 mutex_lock(&hash_mutex);
1666
1667 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1668
1669 hlist_for_each(n, h) {
1670 i = hlist_entry(n, struct irq_info, node);
1671 if (i->irq == up->port.irq)
1672 break;
1673 }
1674
1675 if (n == NULL) {
1676 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1677 if (i == NULL) {
1678 mutex_unlock(&hash_mutex);
1679 return -ENOMEM;
1680 }
1681 spin_lock_init(&i->lock);
1682 i->irq = up->port.irq;
1683 hlist_add_head(&i->node, h);
1684 }
1685 mutex_unlock(&hash_mutex);
1686
1da177e4
LT		 1687 spin_lock_irq(&i->lock);
1688
1689 if (i->head) {
1690 list_add(&up->list, i->head);
1691 spin_unlock_irq(&i->lock);
1692
1693 ret = 0;
1694 } else {
1695 INIT_LIST_HEAD(&up->list);
1696 i->head = &up->list;
1697 spin_unlock_irq(&i->lock);
1c2f0493 1698 irq_flags |= up->port.irqflags;
1da177e4
LT		 1699 ret = request_irq(up->port.irq, serial8250_interrupt,
1700 irq_flags, "serial", i);
1701 if (ret < 0)
1702 serial_do_unlink(i, up);
1703 }
1704
1705 return ret;
1706}
1707
1708static void serial_unlink_irq_chain(struct uart_8250_port *up)
1709{
25db8ad5
AC		 1710 struct irq_info *i;
1711 struct hlist_node *n;
1712 struct hlist_head *h;
1da177e4 1713
25db8ad5
AC		 1714 mutex_lock(&hash_mutex);
1715
1716 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1717
1718 hlist_for_each(n, h) {
1719 i = hlist_entry(n, struct irq_info, node);
1720 if (i->irq == up->port.irq)
1721 break;
1722 }
1723
1724 BUG_ON(n == NULL);
1da177e4
LT		 1725 BUG_ON(i->head == NULL);
1726
1727 if (list_empty(i->head))
1728 free_irq(up->port.irq, i);
1729
1730 serial_do_unlink(i, up);
25db8ad5 1731 mutex_unlock(&hash_mutex);
1da177e4
LT		 1732}
1733
1734/*
1735 * This function is used to handle ports that do not have an
1736 * interrupt. This doesn't work very well for 16450's, but gives
1737 * barely passable results for a 16550A. (Although at the expense
1738 * of much CPU overhead).
1739 */
1740static void serial8250_timeout(unsigned long data)
1741{
1742 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4
LT		 1743 unsigned int iir;
1744
1745 iir = serial_in(up, UART_IIR);
45e24601 1746 if (!(iir & UART_IIR_NO_INT))
7d12e780 1747 serial8250_handle_port(up);
54381067 1748 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
40b36daa
AW		 1749}
1750
1751static void serial8250_backup_timeout(unsigned long data)
1752{
1753 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1754 unsigned int iir, ier = 0, lsr;
1755 unsigned long flags;
40b36daa 1756
dbb3b1ca
AC		 1757 spin_lock_irqsave(&up->port.lock, flags);
1758
40b36daa
AW		 1759 /*
1760 * Must disable interrupts or else we risk racing with the interrupt
1761 * based handler.
1762 */
1763 if (is_real_interrupt(up->port.irq)) {
1764 ier = serial_in(up, UART_IER);
1765 serial_out(up, UART_IER, 0);
1766 }
1da177e4 1767
40b36daa
AW		 1768 iir = serial_in(up, UART_IIR);
1769
1770 /*
1771 * This should be a safe test for anyone who doesn't trust the
1772 * IIR bits on their UART, but it's specifically designed for
1773 * the "Diva" UART used on the management processor on many HP
1774 * ia64 and parisc boxes.
1775 */
ad4c2aa6
CM		 1776 lsr = serial_in(up, UART_LSR);
1777 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
40b36daa 1778 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1779 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1780 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1781 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1782 iir |= UART_IIR_THRI;
1783 }
1784
1785 if (!(iir & UART_IIR_NO_INT))
3986fb2b 1786 serial8250_tx_chars(up);
40b36daa
AW		 1787
1788 if (is_real_interrupt(up->port.irq))
1789 serial_out(up, UART_IER, ier);
1790
dbb3b1ca
AC		 1791 spin_unlock_irqrestore(&up->port.lock, flags);
1792
40b36daa 1793 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0 1794 mod_timer(&up->timer,
54381067 1795 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1da177e4
LT		 1796}
1797
1798static unsigned int serial8250_tx_empty(struct uart_port *port)
1799{
49d5741b
JI		 1800 struct uart_8250_port *up =
1801 container_of(port, struct uart_8250_port, port);
1da177e4 1802 unsigned long flags;
ad4c2aa6 1803 unsigned int lsr;
1da177e4
LT		 1804
1805 spin_lock_irqsave(&up->port.lock, flags);
ad4c2aa6
CM		 1806 lsr = serial_in(up, UART_LSR);
1807 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1da177e4
LT		 1808 spin_unlock_irqrestore(&up->port.lock, flags);
1809
bca47613 1810 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1811}
1812
1813static unsigned int serial8250_get_mctrl(struct uart_port *port)
1814{
49d5741b
JI		 1815 struct uart_8250_port *up =
1816 container_of(port, struct uart_8250_port, port);
2af7cd68 1817 unsigned int status;
1da177e4
LT		 1818 unsigned int ret;
1819
3986fb2b 1820 status = serial8250_modem_status(up);
1da177e4
LT		 1821
1822 ret = 0;
1823 if (status & UART_MSR_DCD)
1824 ret |= TIOCM_CAR;
1825 if (status & UART_MSR_RI)
1826 ret |= TIOCM_RNG;
1827 if (status & UART_MSR_DSR)
1828 ret |= TIOCM_DSR;
1829 if (status & UART_MSR_CTS)
1830 ret |= TIOCM_CTS;
1831 return ret;
1832}
1833
1834static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1835{
49d5741b
JI		 1836 struct uart_8250_port *up =
1837 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1838 unsigned char mcr = 0;
1839
1840 if (mctrl & TIOCM_RTS)
1841 mcr |= UART_MCR_RTS;
1842 if (mctrl & TIOCM_DTR)
1843 mcr |= UART_MCR_DTR;
1844 if (mctrl & TIOCM_OUT1)
1845 mcr |= UART_MCR_OUT1;
1846 if (mctrl & TIOCM_OUT2)
1847 mcr |= UART_MCR_OUT2;
1848 if (mctrl & TIOCM_LOOP)
1849 mcr |= UART_MCR_LOOP;
1850
1851 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1852
1853 serial_out(up, UART_MCR, mcr);
1854}
1855
1856static void serial8250_break_ctl(struct uart_port *port, int break_state)
1857{
49d5741b
JI		 1858 struct uart_8250_port *up =
1859 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1860 unsigned long flags;
1861
1862 spin_lock_irqsave(&up->port.lock, flags);
1863 if (break_state == -1)
1864 up->lcr |= UART_LCR_SBC;
1865 else
1866 up->lcr &= ~UART_LCR_SBC;
1867 serial_out(up, UART_LCR, up->lcr);
1868 spin_unlock_irqrestore(&up->port.lock, flags);
1869}
1870
40b36daa
AW		 1871/*
1872 * Wait for transmitter & holding register to empty
1873 */
b5d674ab 1874static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1875{
1876 unsigned int status, tmout = 10000;
1877
1878 /* Wait up to 10ms for the character(s) to be sent. */
97d303b7 1879 for (;;) {
40b36daa
AW		 1880 status = serial_in(up, UART_LSR);
1881
ad4c2aa6 1882 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa 1883
97d303b7
DD		 1884 if ((status & bits) == bits)
1885 break;
40b36daa
AW		 1886 if (--tmout == 0)
1887 break;
1888 udelay(1);
97d303b7 1889 }
40b36daa
AW		 1890
1891 /* Wait up to 1s for flow control if necessary */
1892 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1893 unsigned int tmout;
1894 for (tmout = 1000000; tmout; tmout--) {
1895 unsigned int msr = serial_in(up, UART_MSR);
1896 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1897 if (msr & UART_MSR_CTS)
1898 break;
40b36daa
AW		 1899 udelay(1);
1900 touch_nmi_watchdog();
1901 }
1902 }
1903}
1904
f2d937f3
JW		 1905#ifdef CONFIG_CONSOLE_POLL
1906/*
1907 * Console polling routines for writing and reading from the uart while
1908 * in an interrupt or debug context.
1909 */
1910
1911static int serial8250_get_poll_char(struct uart_port *port)
1912{
49d5741b
JI		 1913 struct uart_8250_port *up =
1914 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1915 unsigned char lsr = serial_inp(up, UART_LSR);
1916
f5316b4a
JW		 1917 if (!(lsr & UART_LSR_DR))
1918 return NO_POLL_CHAR;
f2d937f3
JW		 1919
1920 return serial_inp(up, UART_RX);
1921}
1922
1923
1924static void serial8250_put_poll_char(struct uart_port *port,
1925 unsigned char c)
1926{
1927 unsigned int ier;
49d5741b
JI		 1928 struct uart_8250_port *up =
1929 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1930
1931 /*
1932 * First save the IER then disable the interrupts
1933 */
1934 ier = serial_in(up, UART_IER);
1935 if (up->capabilities & UART_CAP_UUE)
1936 serial_out(up, UART_IER, UART_IER_UUE);
1937 else
1938 serial_out(up, UART_IER, 0);
1939
1940 wait_for_xmitr(up, BOTH_EMPTY);
1941 /*
1942 * Send the character out.
1943 * If a LF, also do CR...
1944 */
1945 serial_out(up, UART_TX, c);
1946 if (c == 10) {
1947 wait_for_xmitr(up, BOTH_EMPTY);
1948 serial_out(up, UART_TX, 13);
1949 }
1950
1951 /*
1952 * Finally, wait for transmitter to become empty
1953 * and restore the IER
1954 */
1955 wait_for_xmitr(up, BOTH_EMPTY);
1956 serial_out(up, UART_IER, ier);
1957}
1958
1959#endif /* CONFIG_CONSOLE_POLL */
1960
1da177e4
LT		 1961static int serial8250_startup(struct uart_port *port)
1962{
49d5741b
JI		 1963 struct uart_8250_port *up =
1964 container_of(port, struct uart_8250_port, port);
1da177e4 1965 unsigned long flags;
55d3b282 1966 unsigned char lsr, iir;
1da177e4
LT		 1967 int retval;
1968
e4f05af1
OP		 1969 up->port.fifosize = uart_config[up->port.type].fifo_size;
1970 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1da177e4
LT		 1971 up->capabilities = uart_config[up->port.type].flags;
1972 up->mcr = 0;
1973
b8e7e40a
AC		 1974 if (up->port.iotype != up->cur_iotype)
1975 set_io_from_upio(port);
1976
1da177e4
LT		 1977 if (up->port.type == PORT_16C950) {
1978 /* Wake up and initialize UART */
1979 up->acr = 0;
662b083a 1980 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 1981 serial_outp(up, UART_EFR, UART_EFR_ECB);
1982 serial_outp(up, UART_IER, 0);
1983 serial_outp(up, UART_LCR, 0);
1984 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
7d73aaf1 1985 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 1986 serial_outp(up, UART_EFR, UART_EFR_ECB);
1987 serial_outp(up, UART_LCR, 0);
1988 }
1989
1990#ifdef CONFIG_SERIAL_8250_RSA
1991 /*
1992 * If this is an RSA port, see if we can kick it up to the
1993 * higher speed clock.
1994 */
1995 enable_rsa(up);
1996#endif
1997
1998 /*
1999 * Clear the FIFO buffers and disable them.
7f927fcc 2000 * (they will be reenabled in set_termios())
1da177e4
LT		 2001 */
2002 serial8250_clear_fifos(up);
2003
2004 /*
2005 * Clear the interrupt registers.
2006 */
2007 (void) serial_inp(up, UART_LSR);
2008 (void) serial_inp(up, UART_RX);
2009 (void) serial_inp(up, UART_IIR);
2010 (void) serial_inp(up, UART_MSR);
2011
2012 /*
2013 * At this point, there's no way the LSR could still be 0xff;
2014 * if it is, then bail out, because there's likely no UART
2015 * here.
2016 */
2017 if (!(up->port.flags & UPF_BUGGY_UART) &&
2018 (serial_inp(up, UART_LSR) == 0xff)) {
7808a4c4
KRW		 2019 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2020 serial_index(&up->port));
1da177e4
LT		 2021 return -ENODEV;
2022 }
2023
2024 /*
2025 * For a XR16C850, we need to set the trigger levels
2026 */
2027 if (up->port.type == PORT_16850) {
2028 unsigned char fctr;
2029
662b083a 2030 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 2031
2032 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2033 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2034 serial_outp(up, UART_TRG, UART_TRG_96);
2035 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2036 serial_outp(up, UART_TRG, UART_TRG_96);
2037
2038 serial_outp(up, UART_LCR, 0);
2039 }
2040
40b36daa 2041 if (is_real_interrupt(up->port.irq)) {
01c194d9 2042 unsigned char iir1;
40b36daa
AW		 2043 /*
2044 * Test for UARTs that do not reassert THRE when the
2045 * transmitter is idle and the interrupt has already
2046 * been cleared. Real 16550s should always reassert
2047 * this interrupt whenever the transmitter is idle and
2048 * the interrupt is enabled. Delays are necessary to
2049 * allow register changes to become visible.
2050 */
c389d27b 2051 spin_lock_irqsave(&up->port.lock, flags);
1c2f0493 2052 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2053 disable_irq_nosync(up->port.irq);
40b36daa
AW		 2054
2055 wait_for_xmitr(up, UART_LSR_THRE);
2056 serial_out_sync(up, UART_IER, UART_IER_THRI);
2057 udelay(1); /* allow THRE to set */
01c194d9 2058 iir1 = serial_in(up, UART_IIR);
40b36daa
AW		 2059 serial_out(up, UART_IER, 0);
2060 serial_out_sync(up, UART_IER, UART_IER_THRI);
2061 udelay(1); /* allow a working UART time to re-assert THRE */
2062 iir = serial_in(up, UART_IIR);
2063 serial_out(up, UART_IER, 0);
2064
1c2f0493 2065 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2066 enable_irq(up->port.irq);
c389d27b 2067 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa
AW		 2068
2069 /*
2070 * If the interrupt is not reasserted, setup a timer to
2071 * kick the UART on a regular basis.
2072 */
01c194d9 2073 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
363f66fe 2074 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2075 pr_debug("ttyS%d - using backup timer\n",
2076 serial_index(port));
40b36daa
AW		 2077 }
2078 }
2079
363f66fe
WN		 2080 /*
2081 * The above check will only give an accurate result the first time
2082 * the port is opened so this value needs to be preserved.
2083 */
2084 if (up->bugs & UART_BUG_THRE) {
2085 up->timer.function = serial8250_backup_timeout;
2086 up->timer.data = (unsigned long)up;
2087 mod_timer(&up->timer, jiffies +
54381067 2088 uart_poll_timeout(port) + HZ / 5);
363f66fe
WN		 2089 }
2090
1da177e4
LT		 2091 /*
2092 * If the "interrupt" for this port doesn't correspond with any
2093 * hardware interrupt, we use a timer-based system. The original
2094 * driver used to do this with IRQ0.
2095 */
2096 if (!is_real_interrupt(up->port.irq)) {
1da177e4 2097 up->timer.data = (unsigned long)up;
54381067 2098 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
1da177e4
LT		 2099 } else {
2100 retval = serial_link_irq_chain(up);
2101 if (retval)
2102 return retval;
2103 }
2104
2105 /*
2106 * Now, initialize the UART
2107 */
2108 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2109
2110 spin_lock_irqsave(&up->port.lock, flags);
2111 if (up->port.flags & UPF_FOURPORT) {
2112 if (!is_real_interrupt(up->port.irq))
2113 up->port.mctrl |= TIOCM_OUT1;
2114 } else
2115 /*
2116 * Most PC uarts need OUT2 raised to enable interrupts.
2117 */
2118 if (is_real_interrupt(up->port.irq))
2119 up->port.mctrl |= TIOCM_OUT2;
2120
2121 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282 2122
b6adea33
MCC		 2123 /* Serial over Lan (SoL) hack:
2124 Intel 8257x Gigabit ethernet chips have a
2125 16550 emulation, to be used for Serial Over Lan.
2126 Those chips take a longer time than a normal
2127 serial device to signalize that a transmission
2128 data was queued. Due to that, the above test generally
2129 fails. One solution would be to delay the reading of
2130 iir. However, this is not reliable, since the timeout
2131 is variable. So, let's just don't test if we receive
2132 TX irq. This way, we'll never enable UART_BUG_TXEN.
2133 */
d41a4b51 2134 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2135 goto dont_test_tx_en;
2136
55d3b282
RK		 2137 /*
2138 * Do a quick test to see if we receive an
2139 * interrupt when we enable the TX irq.
2140 */
2141 serial_outp(up, UART_IER, UART_IER_THRI);
2142 lsr = serial_in(up, UART_LSR);
2143 iir = serial_in(up, UART_IIR);
2144 serial_outp(up, UART_IER, 0);
2145
2146 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2147 if (!(up->bugs & UART_BUG_TXEN)) {
2148 up->bugs |= UART_BUG_TXEN;
55d3b282 2149 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2150 serial_index(port));
55d3b282
RK		 2151 }
2152 } else {
67f7654e 2153 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2154 }
2155
b6adea33 2156dont_test_tx_en:
1da177e4
LT		 2157 spin_unlock_irqrestore(&up->port.lock, flags);
2158
ad4c2aa6
CM		 2159 /*
2160 * Clear the interrupt registers again for luck, and clear the
2161 * saved flags to avoid getting false values from polling
2162 * routines or the previous session.
2163 */
2164 serial_inp(up, UART_LSR);
2165 serial_inp(up, UART_RX);
2166 serial_inp(up, UART_IIR);
2167 serial_inp(up, UART_MSR);
2168 up->lsr_saved_flags = 0;
2169 up->msr_saved_flags = 0;
2170
1da177e4
LT		 2171 /*
2172 * Finally, enable interrupts. Note: Modem status interrupts
2173 * are set via set_termios(), which will be occurring imminently
2174 * anyway, so we don't enable them here.
2175 */
2176 up->ier = UART_IER_RLSI | UART_IER_RDI;
2177 serial_outp(up, UART_IER, up->ier);
2178
2179 if (up->port.flags & UPF_FOURPORT) {
2180 unsigned int icp;
2181 /*
2182 * Enable interrupts on the AST Fourport board
2183 */
2184 icp = (up->port.iobase & 0xfe0) | 0x01f;
2185 outb_p(0x80, icp);
2186 (void) inb_p(icp);
2187 }
2188
1da177e4
LT		 2189 return 0;
2190}
2191
2192static void serial8250_shutdown(struct uart_port *port)
2193{
49d5741b
JI		 2194 struct uart_8250_port *up =
2195 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2196 unsigned long flags;
2197
2198 /*
2199 * Disable interrupts from this port
2200 */
2201 up->ier = 0;
2202 serial_outp(up, UART_IER, 0);
2203
2204 spin_lock_irqsave(&up->port.lock, flags);
2205 if (up->port.flags & UPF_FOURPORT) {
2206 /* reset interrupts on the AST Fourport board */
2207 inb((up->port.iobase & 0xfe0) | 0x1f);
2208 up->port.mctrl |= TIOCM_OUT1;
2209 } else
2210 up->port.mctrl &= ~TIOCM_OUT2;
2211
2212 serial8250_set_mctrl(&up->port, up->port.mctrl);
2213 spin_unlock_irqrestore(&up->port.lock, flags);
2214
2215 /*
2216 * Disable break condition and FIFOs
2217 */
2218 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2219 serial8250_clear_fifos(up);
2220
2221#ifdef CONFIG_SERIAL_8250_RSA
2222 /*
2223 * Reset the RSA board back to 115kbps compat mode.
2224 */
2225 disable_rsa(up);
2226#endif
2227
2228 /*
2229 * Read data port to reset things, and then unlink from
2230 * the IRQ chain.
2231 */
2232 (void) serial_in(up, UART_RX);
2233
40b36daa
AW		 2234 del_timer_sync(&up->timer);
2235 up->timer.function = serial8250_timeout;
2236 if (is_real_interrupt(up->port.irq))
1da177e4
LT		 2237 serial_unlink_irq_chain(up);
2238}
2239
2240static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2241{
2242 unsigned int quot;
2243
2244 /*
2245 * Handle magic divisors for baud rates above baud_base on
2246 * SMSC SuperIO chips.
2247 */
2248 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2249 baud == (port->uartclk/4))
2250 quot = 0x8001;
2251 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2252 baud == (port->uartclk/8))
2253 quot = 0x8002;
2254 else
2255 quot = uart_get_divisor(port, baud);
2256
2257 return quot;
2258}
2259
235dae5d
PL		 2260void
2261serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2262 struct ktermios *old)
1da177e4 2263{
49d5741b
JI		 2264 struct uart_8250_port *up =
2265 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2266 unsigned char cval, fcr = 0;
2267 unsigned long flags;
2268 unsigned int baud, quot;
2269
2270 switch (termios->c_cflag & CSIZE) {
2271 case CS5:
0a8b80c5 2272 cval = UART_LCR_WLEN5;
1da177e4
LT		 2273 break;
2274 case CS6:
0a8b80c5 2275 cval = UART_LCR_WLEN6;
1da177e4
LT		 2276 break;
2277 case CS7:
0a8b80c5 2278 cval = UART_LCR_WLEN7;
1da177e4
LT		 2279 break;
2280 default:
2281 case CS8:
0a8b80c5 2282 cval = UART_LCR_WLEN8;
1da177e4
LT		 2283 break;
2284 }
2285
2286 if (termios->c_cflag & CSTOPB)
0a8b80c5 2287 cval |= UART_LCR_STOP;
1da177e4
LT		 2288 if (termios->c_cflag & PARENB)
2289 cval |= UART_LCR_PARITY;
2290 if (!(termios->c_cflag & PARODD))
2291 cval |= UART_LCR_EPAR;
2292#ifdef CMSPAR
2293 if (termios->c_cflag & CMSPAR)
2294 cval |= UART_LCR_SPAR;
2295#endif
2296
2297 /*
2298 * Ask the core to calculate the divisor for us.
2299 */
24d481ec
AV		 2300 baud = uart_get_baud_rate(port, termios, old,
2301 port->uartclk / 16 / 0xffff,
2302 port->uartclk / 16);
1da177e4
LT		 2303 quot = serial8250_get_divisor(port, baud);
2304
2305 /*
4ba5e35d 2306 * Oxford Semi 952 rev B workaround
1da177e4 2307 */
4ba5e35d 2308 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2309 quot++;
1da177e4
LT		 2310
2311 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2312 if (baud < 2400)
2313 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2314 else
2315 fcr = uart_config[up->port.type].fcr;
2316 }
2317
2318 /*
2319 * MCR-based auto flow control. When AFE is enabled, RTS will be
2320 * deasserted when the receive FIFO contains more characters than
2321 * the trigger, or the MCR RTS bit is cleared. In the case where
2322 * the remote UART is not using CTS auto flow control, we must
2323 * have sufficient FIFO entries for the latency of the remote
2324 * UART to respond. IOW, at least 32 bytes of FIFO.
2325 */
2326 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2327 up->mcr &= ~UART_MCR_AFE;
2328 if (termios->c_cflag & CRTSCTS)
2329 up->mcr |= UART_MCR_AFE;
2330 }
2331
2332 /*
2333 * Ok, we're now changing the port state. Do it with
2334 * interrupts disabled.
2335 */
2336 spin_lock_irqsave(&up->port.lock, flags);
2337
2338 /*
2339 * Update the per-port timeout.
2340 */
2341 uart_update_timeout(port, termios->c_cflag, baud);
2342
2343 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2344 if (termios->c_iflag & INPCK)
2345 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2346 if (termios->c_iflag & (BRKINT | PARMRK))
2347 up->port.read_status_mask |= UART_LSR_BI;
2348
2349 /*
2350 * Characteres to ignore
2351 */
2352 up->port.ignore_status_mask = 0;
2353 if (termios->c_iflag & IGNPAR)
2354 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2355 if (termios->c_iflag & IGNBRK) {
2356 up->port.ignore_status_mask |= UART_LSR_BI;
2357 /*
2358 * If we're ignoring parity and break indicators,
2359 * ignore overruns too (for real raw support).
2360 */
2361 if (termios->c_iflag & IGNPAR)
2362 up->port.ignore_status_mask |= UART_LSR_OE;
2363 }
2364
2365 /*
2366 * ignore all characters if CREAD is not set
2367 */
2368 if ((termios->c_cflag & CREAD) == 0)
2369 up->port.ignore_status_mask |= UART_LSR_DR;
2370
2371 /*
2372 * CTS flow control flag and modem status interrupts
2373 */
f8b372a1 2374 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2375 if (!(up->bugs & UART_BUG_NOMSR) &&
2376 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2377 up->ier |= UART_IER_MSI;
2378 if (up->capabilities & UART_CAP_UUE)
4539c24f
SW		 2379 up->ier |= UART_IER_UUE;
2380 if (up->capabilities & UART_CAP_RTOIE)
2381 up->ier |= UART_IER_RTOIE;
1da177e4
LT		 2382
2383 serial_out(up, UART_IER, up->ier);
2384
2385 if (up->capabilities & UART_CAP_EFR) {
2386 unsigned char efr = 0;
2387 /*
2388 * TI16C752/Startech hardware flow control. FIXME:
2389 * - TI16C752 requires control thresholds to be set.
2390 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2391 */
2392 if (termios->c_cflag & CRTSCTS)
2393 efr |= UART_EFR_CTS;
2394
662b083a 2395 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
06315348
SH		 2396 if (up->port.flags & UPF_EXAR_EFR)
2397 serial_outp(up, UART_XR_EFR, efr);
2398 else
2399 serial_outp(up, UART_EFR, efr);
1da177e4
LT		 2400 }
2401
f2eda27d 2402#ifdef CONFIG_ARCH_OMAP
255341c6 2403 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
5668545a 2404 if (cpu_is_omap1510() && is_omap_port(up)) {
255341c6
JM		 2405 if (baud == 115200) {
2406 quot = 1;
2407 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2408 } else
2409 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2410 }
2411#endif
2412
1da177e4
LT		 2413 if (up->capabilities & UART_NATSEMI) {
2414 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2415 serial_outp(up, UART_LCR, 0xe0);
2416 } else {
2417 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2418 }
2419
b32b19b8 2420 serial_dl_write(up, quot);
1da177e4
LT		 2421
2422 /*
2423 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2424 * is written without DLAB set, this mode will be disabled.
2425 */
2426 if (up->port.type == PORT_16750)
2427 serial_outp(up, UART_FCR, fcr);
2428
2429 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2430 up->lcr = cval; /* Save LCR */
2431 if (up->port.type != PORT_16750) {
2432 if (fcr & UART_FCR_ENABLE_FIFO) {
2433 /* emulated UARTs (Lucent Venus 167x) need two steps */
2434 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2435 }
2436 serial_outp(up, UART_FCR, fcr); /* set fcr */
2437 }
2438 serial8250_set_mctrl(&up->port, up->port.mctrl);
2439 spin_unlock_irqrestore(&up->port.lock, flags);
e991a2bd
AC		 2440 /* Don't rewrite B0 */
2441 if (tty_termios_baud_rate(termios))
2442 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4 2443}
235dae5d
PL		 2444EXPORT_SYMBOL(serial8250_do_set_termios);
2445
2446static void
2447serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2448 struct ktermios *old)
2449{
2450 if (port->set_termios)
2451 port->set_termios(port, termios, old);
2452 else
2453 serial8250_do_set_termios(port, termios, old);
2454}
1da177e4 2455
dc77f161 2456static void
a0821df6 2457serial8250_set_ldisc(struct uart_port *port, int new)
dc77f161 2458{
a0821df6 2459 if (new == N_PPS) {
dc77f161
RG		 2460 port->flags |= UPF_HARDPPS_CD;
2461 serial8250_enable_ms(port);
2462 } else
2463 port->flags &= ~UPF_HARDPPS_CD;
2464}
2465
c161afe9
ML		 2466
2467void serial8250_do_pm(struct uart_port *port, unsigned int state,
2468 unsigned int oldstate)
1da177e4 2469{
49d5741b
JI		 2470 struct uart_8250_port *p =
2471 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2472
2473 serial8250_set_sleep(p, state != 0);
c161afe9
ML		 2474}
2475EXPORT_SYMBOL(serial8250_do_pm);
1da177e4 2476
c161afe9
ML		 2477static void
2478serial8250_pm(struct uart_port *port, unsigned int state,
2479 unsigned int oldstate)
2480{
2481 if (port->pm)
2482 port->pm(port, state, oldstate);
2483 else
2484 serial8250_do_pm(port, state, oldstate);
1da177e4
LT		 2485}
2486
f2eda27d
RK		 2487static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2488{
2489 if (pt->port.iotype == UPIO_AU)
b2b13cdf 2490 return 0x1000;
f2eda27d
RK		 2491#ifdef CONFIG_ARCH_OMAP
2492 if (is_omap_port(pt))
2493 return 0x16 << pt->port.regshift;
2494#endif
2495 return 8 << pt->port.regshift;
2496}
2497
1da177e4
LT		 2498/*
2499 * Resource handling.
2500 */
2501static int serial8250_request_std_resource(struct uart_8250_port *up)
2502{
f2eda27d 2503 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2504 int ret = 0;
2505
2506 switch (up->port.iotype) {
85835f44 2507 case UPIO_AU:
0b30d668
SS		 2508 case UPIO_TSI:
2509 case UPIO_MEM32:
1da177e4
LT		 2510 case UPIO_MEM:
2511 if (!up->port.mapbase)
2512 break;
2513
2514 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2515 ret = -EBUSY;
2516 break;
2517 }
2518
2519 if (up->port.flags & UPF_IOREMAP) {
6f441fe9
AC		 2520 up->port.membase = ioremap_nocache(up->port.mapbase,
2521 size);
1da177e4
LT		 2522 if (!up->port.membase) {
2523 release_mem_region(up->port.mapbase, size);
2524 ret = -ENOMEM;
2525 }
2526 }
2527 break;
2528
2529 case UPIO_HUB6:
2530 case UPIO_PORT:
2531 if (!request_region(up->port.iobase, size, "serial"))
2532 ret = -EBUSY;
2533 break;
2534 }
2535 return ret;
2536}
2537
2538static void serial8250_release_std_resource(struct uart_8250_port *up)
2539{
f2eda27d 2540 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2541
2542 switch (up->port.iotype) {
85835f44 2543 case UPIO_AU:
0b30d668
SS		 2544 case UPIO_TSI:
2545 case UPIO_MEM32:
1da177e4
LT		 2546 case UPIO_MEM:
2547 if (!up->port.mapbase)
2548 break;
2549
2550 if (up->port.flags & UPF_IOREMAP) {
2551 iounmap(up->port.membase);
2552 up->port.membase = NULL;
2553 }
2554
2555 release_mem_region(up->port.mapbase, size);
2556 break;
2557
2558 case UPIO_HUB6:
2559 case UPIO_PORT:
2560 release_region(up->port.iobase, size);
2561 break;
2562 }
2563}
2564
2565static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2566{
2567 unsigned long start = UART_RSA_BASE << up->port.regshift;
2568 unsigned int size = 8 << up->port.regshift;
0b30d668 2569 int ret = -EINVAL;
1da177e4
LT		 2570
2571 switch (up->port.iotype) {
1da177e4
LT		 2572 case UPIO_HUB6:
2573 case UPIO_PORT:
2574 start += up->port.iobase;
0b30d668
SS		 2575 if (request_region(start, size, "serial-rsa"))
2576 ret = 0;
2577 else
1da177e4
LT		 2578 ret = -EBUSY;
2579 break;
2580 }
2581
2582 return ret;
2583}
2584
2585static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2586{
2587 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2588 unsigned int size = 8 << up->port.regshift;
2589
2590 switch (up->port.iotype) {
1da177e4
LT		 2591 case UPIO_HUB6:
2592 case UPIO_PORT:
2593 release_region(up->port.iobase + offset, size);
2594 break;
2595 }
2596}
2597
2598static void serial8250_release_port(struct uart_port *port)
2599{
49d5741b
JI		 2600 struct uart_8250_port *up =
2601 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2602
2603 serial8250_release_std_resource(up);
2604 if (up->port.type == PORT_RSA)
2605 serial8250_release_rsa_resource(up);
2606}
2607
2608static int serial8250_request_port(struct uart_port *port)
2609{
49d5741b
JI		 2610 struct uart_8250_port *up =
2611 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2612 int ret = 0;
2613
2614 ret = serial8250_request_std_resource(up);
2615 if (ret == 0 && up->port.type == PORT_RSA) {
2616 ret = serial8250_request_rsa_resource(up);
2617 if (ret < 0)
2618 serial8250_release_std_resource(up);
2619 }
2620
2621 return ret;
2622}
2623
2624static void serial8250_config_port(struct uart_port *port, int flags)
2625{
49d5741b
JI		 2626 struct uart_8250_port *up =
2627 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2628 int probeflags = PROBE_ANY;
2629 int ret;
2630
1da177e4
LT		 2631 /*
2632 * Find the region that we can probe for. This in turn
2633 * tells us whether we can probe for the type of port.
2634 */
2635 ret = serial8250_request_std_resource(up);
2636 if (ret < 0)
2637 return;
2638
2639 ret = serial8250_request_rsa_resource(up);
2640 if (ret < 0)
2641 probeflags &= ~PROBE_RSA;
2642
b8e7e40a
AC		 2643 if (up->port.iotype != up->cur_iotype)
2644 set_io_from_upio(port);
2645
1da177e4
LT		 2646 if (flags & UART_CONFIG_TYPE)
2647 autoconfig(up, probeflags);
b2b13cdf 2648
b2b13cdf
ML		 2649 /* if access method is AU, it is a 16550 with a quirk */
2650 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2651 up->bugs |= UART_BUG_NOMSR;
b2b13cdf 2652
1da177e4
LT		 2653 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2654 autoconfig_irq(up);
2655
2656 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2657 serial8250_release_rsa_resource(up);
2658 if (up->port.type == PORT_UNKNOWN)
2659 serial8250_release_std_resource(up);
2660}
2661
2662static int
2663serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2664{
a62c4133 2665 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2666 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2667 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2668 ser->type == PORT_STARTECH)
2669 return -EINVAL;
2670 return 0;
2671}
2672
2673static const char *
2674serial8250_type(struct uart_port *port)
2675{
2676 int type = port->type;
2677
2678 if (type >= ARRAY_SIZE(uart_config))
2679 type = 0;
2680 return uart_config[type].name;
2681}
2682
2683static struct uart_ops serial8250_pops = {
2684 .tx_empty = serial8250_tx_empty,
2685 .set_mctrl = serial8250_set_mctrl,
2686 .get_mctrl = serial8250_get_mctrl,
2687 .stop_tx = serial8250_stop_tx,
2688 .start_tx = serial8250_start_tx,
2689 .stop_rx = serial8250_stop_rx,
2690 .enable_ms = serial8250_enable_ms,
2691 .break_ctl = serial8250_break_ctl,
2692 .startup = serial8250_startup,
2693 .shutdown = serial8250_shutdown,
2694 .set_termios = serial8250_set_termios,
dc77f161 2695 .set_ldisc = serial8250_set_ldisc,
1da177e4
LT		 2696 .pm = serial8250_pm,
2697 .type = serial8250_type,
2698 .release_port = serial8250_release_port,
2699 .request_port = serial8250_request_port,
2700 .config_port = serial8250_config_port,
2701 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2702#ifdef CONFIG_CONSOLE_POLL
2703 .poll_get_char = serial8250_get_poll_char,
2704 .poll_put_char = serial8250_put_poll_char,
2705#endif
1da177e4
LT		 2706};
2707
2708static struct uart_8250_port serial8250_ports[UART_NR];
2709
af7f3743
AC		 2710static void (*serial8250_isa_config)(int port, struct uart_port *up,
2711 unsigned short *capabilities);
2712
2713void serial8250_set_isa_configurator(
2714 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2715{
2716 serial8250_isa_config = v;
2717}
2718EXPORT_SYMBOL(serial8250_set_isa_configurator);
2719
1da177e4
LT		 2720static void __init serial8250_isa_init_ports(void)
2721{
2722 struct uart_8250_port *up;
2723 static int first = 1;
4c0ebb80 2724 int i, irqflag = 0;
1da177e4
LT		 2725
2726 if (!first)
2727 return;
2728 first = 0;
2729
a61c2d78 2730 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2731 struct uart_8250_port *up = &serial8250_ports[i];
2732
2733 up->port.line = i;
2734 spin_lock_init(&up->port.lock);
2735
2736 init_timer(&up->timer);
2737 up->timer.function = serial8250_timeout;
2738
2739 /*
2740 * ALPHA_KLUDGE_MCR needs to be killed.
2741 */
2742 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2743 up->mcr_force = ALPHA_KLUDGE_MCR;
2744
2745 up->port.ops = &serial8250_pops;
2746 }
2747
4c0ebb80
AGR		 2748 if (share_irqs)
2749 irqflag = IRQF_SHARED;
2750
44454bcd 2751 for (i = 0, up = serial8250_ports;
a61c2d78 2752 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2753 i++, up++) {
2754 up->port.iobase = old_serial_port[i].port;
2755 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
1c2f0493 2756 up->port.irqflags = old_serial_port[i].irqflags;
1da177e4
LT		 2757 up->port.uartclk = old_serial_port[i].baud_base * 16;
2758 up->port.flags = old_serial_port[i].flags;
2759 up->port.hub6 = old_serial_port[i].hub6;
2760 up->port.membase = old_serial_port[i].iomem_base;
2761 up->port.iotype = old_serial_port[i].io_type;
2762 up->port.regshift = old_serial_port[i].iomem_reg_shift;
7d6a07d1 2763 set_io_from_upio(&up->port);
4c0ebb80 2764 up->port.irqflags |= irqflag;
af7f3743
AC		 2765 if (serial8250_isa_config != NULL)
2766 serial8250_isa_config(i, &up->port, &up->capabilities);
2767
1da177e4
LT		 2768 }
2769}
2770
b5d228cc
SL		 2771static void
2772serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2773{
2774 up->port.type = type;
2775 up->port.fifosize = uart_config[type].fifo_size;
2776 up->capabilities = uart_config[type].flags;
2777 up->tx_loadsz = uart_config[type].tx_loadsz;
2778}
2779
1da177e4
LT		 2780static void __init
2781serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2782{
2783 int i;
2784
b8e7e40a
AC		 2785 for (i = 0; i < nr_uarts; i++) {
2786 struct uart_8250_port *up = &serial8250_ports[i];
2787 up->cur_iotype = 0xFF;
2788 }
2789
1da177e4
LT		 2790 serial8250_isa_init_ports();
2791
a61c2d78 2792 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2793 struct uart_8250_port *up = &serial8250_ports[i];
2794
2795 up->port.dev = dev;
b5d228cc
SL		 2796
2797 if (up->port.flags & UPF_FIXED_TYPE)
2798 serial8250_init_fixed_type_port(up, up->port.type);
2799
1da177e4
LT		 2800 uart_add_one_port(drv, &up->port);
2801 }
2802}
2803
2804#ifdef CONFIG_SERIAL_8250_CONSOLE
2805
d358788f
RK		 2806static void serial8250_console_putchar(struct uart_port *port, int ch)
2807{
49d5741b
JI		 2808 struct uart_8250_port *up =
2809 container_of(port, struct uart_8250_port, port);
d358788f
RK		 2810
2811 wait_for_xmitr(up, UART_LSR_THRE);
2812 serial_out(up, UART_TX, ch);
2813}
2814
1da177e4
LT		 2815/*
2816 * Print a string to the serial port trying not to disturb
2817 * any possible real use of the port...
2818 *
2819 * The console_lock must be held when we get here.
2820 */
2821static void
2822serial8250_console_write(struct console *co, const char *s, unsigned int count)
2823{
2824 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2825 unsigned long flags;
1da177e4 2826 unsigned int ier;
d8a5a8d7 2827 int locked = 1;
1da177e4 2828
78512ece
AM		 2829 touch_nmi_watchdog();
2830
68aa2c0d
AM		 2831 local_irq_save(flags);
2832 if (up->port.sysrq) {
2833 /* serial8250_handle_port() already took the lock */
2834 locked = 0;
2835 } else if (oops_in_progress) {
2836 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2837 } else
68aa2c0d 2838 spin_lock(&up->port.lock);
d8a5a8d7 2839
1da177e4 2840 /*
dc7bf130 2841 * First save the IER then disable the interrupts
1da177e4
LT		 2842 */
2843 ier = serial_in(up, UART_IER);
2844
2845 if (up->capabilities & UART_CAP_UUE)
2846 serial_out(up, UART_IER, UART_IER_UUE);
2847 else
2848 serial_out(up, UART_IER, 0);
2849
d358788f 2850 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2851
2852 /*
2853 * Finally, wait for transmitter to become empty
2854 * and restore the IER
2855 */
f91a3715 2856 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2857 serial_out(up, UART_IER, ier);
d8a5a8d7 2858
ad4c2aa6
CM		 2859 /*
2860 * The receive handling will happen properly because the
2861 * receive ready bit will still be set; it is not cleared
2862 * on read. However, modem control will not, we must
2863 * call it if we have saved something in the saved flags
2864 * while processing with interrupts off.
2865 */
2866 if (up->msr_saved_flags)
3986fb2b 2867 serial8250_modem_status(up);
ad4c2aa6 2868
d8a5a8d7 2869 if (locked)
68aa2c0d
AM		 2870 spin_unlock(&up->port.lock);
2871 local_irq_restore(flags);
1da177e4
LT		 2872}
2873
118c0ace 2874static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2875{
2876 struct uart_port *port;
2877 int baud = 9600;
2878 int bits = 8;
2879 int parity = 'n';
2880 int flow = 'n';
2881
2882 /*
2883 * Check whether an invalid uart number has been specified, and
2884 * if so, search for the first available port that does have
2885 * console support.
2886 */
a61c2d78 2887 if (co->index >= nr_uarts)
1da177e4
LT		 2888 co->index = 0;
2889 port = &serial8250_ports[co->index].port;
2890 if (!port->iobase && !port->membase)
2891 return -ENODEV;
2892
2893 if (options)
2894 uart_parse_options(options, &baud, &parity, &bits, &flow);
2895
2896 return uart_set_options(port, co, baud, parity, bits, flow);
2897}
2898
b6b1d877 2899static int serial8250_console_early_setup(void)
18a8bd94
YL		 2900{
2901 return serial8250_find_port_for_earlycon();
2902}
2903
1da177e4
LT		 2904static struct console serial8250_console = {
2905 .name = "ttyS",
2906 .write = serial8250_console_write,
2907 .device = uart_console_device,
2908 .setup = serial8250_console_setup,
18a8bd94 2909 .early_setup = serial8250_console_early_setup,
a80c49db 2910 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2911 .index = -1,
2912 .data = &serial8250_reg,
2913};
2914
2915static int __init serial8250_console_init(void)
2916{
05d81d22
EB		 2917 if (nr_uarts > UART_NR)
2918 nr_uarts = UART_NR;
2919
1da177e4
LT		 2920 serial8250_isa_init_ports();
2921 register_console(&serial8250_console);
2922 return 0;
2923}
2924console_initcall(serial8250_console_init);
2925
18a8bd94 2926int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2927{
2928 int line;
2929 struct uart_port *port;
2930
a61c2d78 2931 for (line = 0; line < nr_uarts; line++) {
1da177e4 2932 port = &serial8250_ports[line].port;
50aec3b5 2933 if (uart_match_port(p, port))
1da177e4
LT		 2934 return line;
2935 }
2936 return -ENODEV;
2937}
2938
1da177e4
LT		 2939#define SERIAL8250_CONSOLE &serial8250_console
2940#else
2941#define SERIAL8250_CONSOLE NULL
2942#endif
2943
2944static struct uart_driver serial8250_reg = {
2945 .owner = THIS_MODULE,
2946 .driver_name = "serial",
1da177e4
LT		 2947 .dev_name = "ttyS",
2948 .major = TTY_MAJOR,
2949 .minor = 64,
1da177e4
LT		 2950 .cons = SERIAL8250_CONSOLE,
2951};
2952
d856c666
RK		 2953/*
2954 * early_serial_setup - early registration for 8250 ports
2955 *
2956 * Setup an 8250 port structure prior to console initialisation. Use
2957 * after console initialisation will cause undefined behaviour.
2958 */
1da177e4
LT		 2959int __init early_serial_setup(struct uart_port *port)
2960{
b430428a
DD		 2961 struct uart_port *p;
2962
1da177e4
LT		 2963 if (port->line >= ARRAY_SIZE(serial8250_ports))
2964 return -ENODEV;
2965
2966 serial8250_isa_init_ports();
b430428a
DD		 2967 p = &serial8250_ports[port->line].port;
2968 p->iobase = port->iobase;
2969 p->membase = port->membase;
2970 p->irq = port->irq;
1c2f0493 2971 p->irqflags = port->irqflags;
b430428a
DD		 2972 p->uartclk = port->uartclk;
2973 p->fifosize = port->fifosize;
2974 p->regshift = port->regshift;
2975 p->iotype = port->iotype;
2976 p->flags = port->flags;
2977 p->mapbase = port->mapbase;
2978 p->private_data = port->private_data;
125c97d8
HD		 2979 p->type = port->type;
2980 p->line = port->line;
7d6a07d1
DD		 2981
2982 set_io_from_upio(p);
2983 if (port->serial_in)
2984 p->serial_in = port->serial_in;
2985 if (port->serial_out)
2986 p->serial_out = port->serial_out;
583d28e9
JI		 2987 if (port->handle_irq)
2988 p->handle_irq = port->handle_irq;
2989 else
2990 p->handle_irq = serial8250_default_handle_irq;
7d6a07d1 2991
1da177e4
LT		 2992 return 0;
2993}
2994
2995/**
2996 * serial8250_suspend_port - suspend one serial port
2997 * @line: serial line number
1da177e4
LT		 2998 *
2999 * Suspend one serial port.
3000 */
3001void serial8250_suspend_port(int line)
3002{
3003 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3004}
3005
3006/**
3007 * serial8250_resume_port - resume one serial port
3008 * @line: serial line number
1da177e4
LT		 3009 *
3010 * Resume one serial port.
3011 */
3012void serial8250_resume_port(int line)
3013{
b5b82df6
DW		 3014 struct uart_8250_port *up = &serial8250_ports[line];
3015
3016 if (up->capabilities & UART_NATSEMI) {
b5b82df6
DW		 3017 /* Ensure it's still in high speed mode */
3018 serial_outp(up, UART_LCR, 0xE0);
3019
0d0389e5 3020 ns16550a_goto_highspeed(up);
b5b82df6
DW		 3021
3022 serial_outp(up, UART_LCR, 0);
95926d2d 3023 up->port.uartclk = 921600*16;
b5b82df6
DW		 3024 }
3025 uart_resume_port(&serial8250_reg, &up->port);
1da177e4
LT		 3026}
3027
3028/*
3029 * Register a set of serial devices attached to a platform device. The
3030 * list is terminated with a zero flags entry, which means we expect
3031 * all entries to have at least UPF_BOOT_AUTOCONF set.
3032 */
3ae5eaec 3033static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 3034{
3ae5eaec 3035 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 3036 struct uart_port port;
4c0ebb80 3037 int ret, i, irqflag = 0;
1da177e4
LT		 3038
3039 memset(&port, 0, sizeof(struct uart_port));
3040
4c0ebb80
AGR		 3041 if (share_irqs)
3042 irqflag = IRQF_SHARED;
3043
ec9f47cd 3044 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 3045 port.iobase = p->iobase;
3046 port.membase = p->membase;
3047 port.irq = p->irq;
1c2f0493 3048 port.irqflags = p->irqflags;
74a19741
WN		 3049 port.uartclk = p->uartclk;
3050 port.regshift = p->regshift;
3051 port.iotype = p->iotype;
3052 port.flags = p->flags;
3053 port.mapbase = p->mapbase;
3054 port.hub6 = p->hub6;
3055 port.private_data = p->private_data;
8e23fcc8 3056 port.type = p->type;
7d6a07d1
DD		 3057 port.serial_in = p->serial_in;
3058 port.serial_out = p->serial_out;
583d28e9 3059 port.handle_irq = p->handle_irq;
235dae5d 3060 port.set_termios = p->set_termios;
c161afe9 3061 port.pm = p->pm;
74a19741 3062 port.dev = &dev->dev;
4c0ebb80 3063 port.irqflags |= irqflag;
ec9f47cd
RK		 3064 ret = serial8250_register_port(&port);
3065 if (ret < 0) {
3ae5eaec 3066 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 3067 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3068 p->iobase, (unsigned long long)p->mapbase,
3069 p->irq, ret);
ec9f47cd 3070 }
1da177e4
LT		 3071 }
3072 return 0;
3073}
3074
3075/*
3076 * Remove serial ports registered against a platform device.
3077 */
3ae5eaec 3078static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 3079{
3080 int i;
3081
a61c2d78 3082 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 3083 struct uart_8250_port *up = &serial8250_ports[i];
3084
3ae5eaec 3085 if (up->port.dev == &dev->dev)
1da177e4
LT		 3086 serial8250_unregister_port(i);
3087 }
3088 return 0;
3089}
3090
3ae5eaec 3091static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 3092{
3093 int i;
3094
1da177e4
LT		 3095 for (i = 0; i < UART_NR; i++) {
3096 struct uart_8250_port *up = &serial8250_ports[i];
3097
3ae5eaec 3098 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3099 uart_suspend_port(&serial8250_reg, &up->port);
3100 }
3101
3102 return 0;
3103}
3104
3ae5eaec 3105static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3106{
3107 int i;
3108
1da177e4
LT		 3109 for (i = 0; i < UART_NR; i++) {
3110 struct uart_8250_port *up = &serial8250_ports[i];
3111
3ae5eaec 3112 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3113 serial8250_resume_port(i);
1da177e4
LT		 3114 }
3115
3116 return 0;
3117}
3118
3ae5eaec 3119static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 3120 .probe = serial8250_probe,
3121 .remove = __devexit_p(serial8250_remove),
3122 .suspend = serial8250_suspend,
3123 .resume = serial8250_resume,
3ae5eaec
RK		 3124 .driver = {
3125 .name = "serial8250",
7493a314 3126 .owner = THIS_MODULE,
3ae5eaec 3127 },
1da177e4
LT		 3128};
3129
3130/*
3131 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3132 * in the table in include/asm/serial.h
3133 */
3134static struct platform_device *serial8250_isa_devs;
3135
3136/*
3137 * serial8250_register_port and serial8250_unregister_port allows for
3138 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3139 * modems and PCI multiport cards.
3140 */
f392ecfa 3141static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3142
3143static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3144{
3145 int i;
3146
3147 /*
3148 * First, find a port entry which matches.
3149 */
a61c2d78 3150 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3151 if (uart_match_port(&serial8250_ports[i].port, port))
3152 return &serial8250_ports[i];
3153
3154 /*
3155 * We didn't find a matching entry, so look for the first
3156 * free entry. We look for one which hasn't been previously
3157 * used (indicated by zero iobase).
3158 */
a61c2d78 3159 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3160 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3161 serial8250_ports[i].port.iobase == 0)
3162 return &serial8250_ports[i];
3163
3164 /*
3165 * That also failed. Last resort is to find any entry which
3166 * doesn't have a real port associated with it.
3167 */
a61c2d78 3168 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3169 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3170 return &serial8250_ports[i];
3171
3172 return NULL;
3173}
3174
3175/**
3176 * serial8250_register_port - register a serial port
3177 * @port: serial port template
3178 *
3179 * Configure the serial port specified by the request. If the
3180 * port exists and is in use, it is hung up and unregistered
3181 * first.
3182 *
3183 * The port is then probed and if necessary the IRQ is autodetected
3184 * If this fails an error is returned.
3185 *
3186 * On success the port is ready to use and the line number is returned.
3187 */
3188int serial8250_register_port(struct uart_port *port)
3189{
3190 struct uart_8250_port *uart;
3191 int ret = -ENOSPC;
3192
3193 if (port->uartclk == 0)
3194 return -EINVAL;
3195
f392ecfa 3196 mutex_lock(&serial_mutex);
1da177e4
LT		 3197
3198 uart = serial8250_find_match_or_unused(port);
3199 if (uart) {
3200 uart_remove_one_port(&serial8250_reg, &uart->port);
3201
74a19741
WN		 3202 uart->port.iobase = port->iobase;
3203 uart->port.membase = port->membase;
3204 uart->port.irq = port->irq;
1c2f0493 3205 uart->port.irqflags = port->irqflags;
74a19741
WN		 3206 uart->port.uartclk = port->uartclk;
3207 uart->port.fifosize = port->fifosize;
3208 uart->port.regshift = port->regshift;
3209 uart->port.iotype = port->iotype;
3210 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3211 uart->port.mapbase = port->mapbase;
3212 uart->port.private_data = port->private_data;
1da177e4
LT		 3213 if (port->dev)
3214 uart->port.dev = port->dev;
8e23fcc8 3215
b5d228cc
SL		 3216 if (port->flags & UPF_FIXED_TYPE)
3217 serial8250_init_fixed_type_port(uart, port->type);
8e23fcc8 3218
7d6a07d1
DD		 3219 set_io_from_upio(&uart->port);
3220 /* Possibly override default I/O functions. */
3221 if (port->serial_in)
3222 uart->port.serial_in = port->serial_in;
3223 if (port->serial_out)
3224 uart->port.serial_out = port->serial_out;
583d28e9
JI		 3225 if (port->handle_irq)
3226 uart->port.handle_irq = port->handle_irq;
235dae5d
PL		 3227 /* Possibly override set_termios call */
3228 if (port->set_termios)
3229 uart->port.set_termios = port->set_termios;
c161afe9
ML		 3230 if (port->pm)
3231 uart->port.pm = port->pm;
1da177e4 3232
af7f3743
AC		 3233 if (serial8250_isa_config != NULL)
3234 serial8250_isa_config(0, &uart->port,
3235 &uart->capabilities);
3236
1da177e4
LT		 3237 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3238 if (ret == 0)
3239 ret = uart->port.line;
3240 }
f392ecfa 3241 mutex_unlock(&serial_mutex);
1da177e4
LT		 3242
3243 return ret;
3244}
3245EXPORT_SYMBOL(serial8250_register_port);
3246
3247/**
3248 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3249 * @line: serial line number
3250 *
3251 * Remove one serial port. This may not be called from interrupt
3252 * context. We hand the port back to the our control.
3253 */
3254void serial8250_unregister_port(int line)
3255{
3256 struct uart_8250_port *uart = &serial8250_ports[line];
3257
f392ecfa 3258 mutex_lock(&serial_mutex);
1da177e4
LT		 3259 uart_remove_one_port(&serial8250_reg, &uart->port);
3260 if (serial8250_isa_devs) {
3261 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3262 uart->port.type = PORT_UNKNOWN;
3263 uart->port.dev = &serial8250_isa_devs->dev;
cb01ece3 3264 uart->capabilities = uart_config[uart->port.type].flags;
1da177e4
LT		 3265 uart_add_one_port(&serial8250_reg, &uart->port);
3266 } else {
3267 uart->port.dev = NULL;
3268 }
f392ecfa 3269 mutex_unlock(&serial_mutex);
1da177e4
LT		 3270}
3271EXPORT_SYMBOL(serial8250_unregister_port);
3272
3273static int __init serial8250_init(void)
3274{
25db8ad5 3275 int ret;
1da177e4 3276
a61c2d78
DJ		 3277 if (nr_uarts > UART_NR)
3278 nr_uarts = UART_NR;
3279
f1fb9bb8 3280 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3281 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3282 share_irqs ? "en" : "dis");
3283
b70ac771
DM		 3284#ifdef CONFIG_SPARC
3285 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3286#else
3287 serial8250_reg.nr = UART_NR;
1da177e4 3288 ret = uart_register_driver(&serial8250_reg);
b70ac771 3289#endif
1da177e4
LT		 3290 if (ret)
3291 goto out;
3292
7493a314
DT		 3293 serial8250_isa_devs = platform_device_alloc("serial8250",
3294 PLAT8250_DEV_LEGACY);
3295 if (!serial8250_isa_devs) {
3296 ret = -ENOMEM;
bc965a7f 3297 goto unreg_uart_drv;
1da177e4
LT		 3298 }
3299
7493a314
DT		 3300 ret = platform_device_add(serial8250_isa_devs);
3301 if (ret)
3302 goto put_dev;
3303
1da177e4
LT		 3304 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3305
bc965a7f
RK		 3306 ret = platform_driver_register(&serial8250_isa_driver);
3307 if (ret == 0)
3308 goto out;
1da177e4 3309
bc965a7f 3310 platform_device_del(serial8250_isa_devs);
25db8ad5 3311put_dev:
7493a314 3312 platform_device_put(serial8250_isa_devs);
25db8ad5 3313unreg_uart_drv:
b70ac771
DM		 3314#ifdef CONFIG_SPARC
3315 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3316#else
1da177e4 3317 uart_unregister_driver(&serial8250_reg);
b70ac771 3318#endif
25db8ad5 3319out:
1da177e4
LT		 3320 return ret;
3321}
3322
3323static void __exit serial8250_exit(void)
3324{
3325 struct platform_device *isa_dev = serial8250_isa_devs;
3326
3327 /*
3328 * This tells serial8250_unregister_port() not to re-register
3329 * the ports (thereby making serial8250_isa_driver permanently
3330 * in use.)
3331 */
3332 serial8250_isa_devs = NULL;
3333
3ae5eaec 3334 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3335 platform_device_unregister(isa_dev);
3336
b70ac771
DM		 3337#ifdef CONFIG_SPARC
3338 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3339#else
1da177e4 3340 uart_unregister_driver(&serial8250_reg);
b70ac771 3341#endif
1da177e4
LT		 3342}
3343
3344module_init(serial8250_init);
3345module_exit(serial8250_exit);
3346
3347EXPORT_SYMBOL(serial8250_suspend_port);
3348EXPORT_SYMBOL(serial8250_resume_port);
3349
3350MODULE_LICENSE("GPL");
d87a6d95 3351MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3352
3353module_param(share_irqs, uint, 0644);
3354MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3355 " (unsafe)");
3356
a61c2d78
DJ		 3357module_param(nr_uarts, uint, 0644);
3358MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3359
d41a4b51
CE		 3360module_param(skip_txen_test, uint, 0644);
3361MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3362
1da177e4
LT		 3363#ifdef CONFIG_SERIAL_8250_RSA
3364module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3365MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3366#endif
3367MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux kernel - Deliverables
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