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serial: move struct uart_8250_port from 8250.c to 8250.h
[deliverable/linux.git] / drivers / tty / serial / 8250.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
1da177e4
LT		 13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
1da177e4
LT		 18
19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
1da177e4 29#include <linux/delay.h>
d052d1be 30#include <linux/platform_device.h>
1da177e4 31#include <linux/tty.h>
cd3ecad1 32#include <linux/ratelimit.h>
1da177e4
LT		 33#include <linux/tty_flip.h>
34#include <linux/serial_reg.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
78512ece 38#include <linux/nmi.h>
f392ecfa 39#include <linux/mutex.h>
5a0e3ad6 40#include <linux/slab.h>
1da177e4
LT		 41
42#include <asm/io.h>
43#include <asm/irq.h>
44
45#include "8250.h"
46
b70ac771
DM		 47#ifdef CONFIG_SPARC
48#include "suncore.h"
49#endif
50
1da177e4
LT		 51/*
52 * Configuration:
40663cc7 53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 54 * is unsafe when used on edge-triggered interrupts.
55 */
408b664a 56static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 57
a61c2d78
DJ		 58static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
8440838b
DM		 60static struct uart_driver serial8250_reg;
61
62static int serial_index(struct uart_port *port)
63{
64 return (serial8250_reg.minor - 64) + port->line;
65}
66
d41a4b51
CE		 67static unsigned int skip_txen_test; /* force skip of txen test at init time */
68
1da177e4
LT		 69/*
70 * Debugging.
71 */
72#if 0
73#define DEBUG_AUTOCONF(fmt...) printk(fmt)
74#else
75#define DEBUG_AUTOCONF(fmt...) do { } while (0)
76#endif
77
78#if 0
79#define DEBUG_INTR(fmt...) printk(fmt)
80#else
81#define DEBUG_INTR(fmt...) do { } while (0)
82#endif
83
e7328ae1 84#define PASS_LIMIT 512
1da177e4 85
bca47613
DH		 86#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
87
88
1da177e4
LT		 89/*
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
93 */
94#define is_real_interrupt(irq) ((irq) != 0)
95
1da177e4
LT		 96#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97#define CONFIG_SERIAL_DETECT_IRQ 1
98#endif
1da177e4
LT		 99#ifdef CONFIG_SERIAL_8250_MANY_PORTS
100#define CONFIG_SERIAL_MANY_PORTS 1
101#endif
102
103/*
104 * HUB6 is always on. This will be removed once the header
105 * files have been cleaned.
106 */
107#define CONFIG_HUB6 1
108
a4ed1e41 109#include <asm/serial.h>
1da177e4
LT		 110/*
111 * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 * standard enumeration mechanism. Platforms that can find all
113 * serial ports via mechanisms like ACPI or PCI need not supply it.
114 */
115#ifndef SERIAL_PORT_DFNS
116#define SERIAL_PORT_DFNS
117#endif
118
cb3592be 119static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 120 SERIAL_PORT_DFNS /* defined in asm/serial.h */
121};
122
026d02a2 123#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 124
125#ifdef CONFIG_SERIAL_8250_RSA
126
127#define PORT_RSA_MAX 4
128static unsigned long probe_rsa[PORT_RSA_MAX];
129static unsigned int probe_rsa_count;
130#endif /* CONFIG_SERIAL_8250_RSA */
131
1da177e4 132struct irq_info {
25db8ad5
AC		 133 struct hlist_node node;
134 int irq;
135 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 136 struct list_head *head;
137};
138
25db8ad5
AC		 139#define NR_IRQ_HASH 32 /* Can be adjusted later */
140static struct hlist_head irq_lists[NR_IRQ_HASH];
141static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 142
143/*
144 * Here we define the default xmit fifo size used for each type of UART.
145 */
146static const struct serial8250_config uart_config[] = {
147 [PORT_UNKNOWN] = {
148 .name = "unknown",
149 .fifo_size = 1,
150 .tx_loadsz = 1,
151 },
152 [PORT_8250] = {
153 .name = "8250",
154 .fifo_size = 1,
155 .tx_loadsz = 1,
156 },
157 [PORT_16450] = {
158 .name = "16450",
159 .fifo_size = 1,
160 .tx_loadsz = 1,
161 },
162 [PORT_16550] = {
163 .name = "16550",
164 .fifo_size = 1,
165 .tx_loadsz = 1,
166 },
167 [PORT_16550A] = {
168 .name = "16550A",
169 .fifo_size = 16,
170 .tx_loadsz = 16,
171 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
172 .flags = UART_CAP_FIFO,
173 },
174 [PORT_CIRRUS] = {
175 .name = "Cirrus",
176 .fifo_size = 1,
177 .tx_loadsz = 1,
178 },
179 [PORT_16650] = {
180 .name = "ST16650",
181 .fifo_size = 1,
182 .tx_loadsz = 1,
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184 },
185 [PORT_16650V2] = {
186 .name = "ST16650V2",
187 .fifo_size = 32,
188 .tx_loadsz = 16,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
190 UART_FCR_T_TRIG_00,
191 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
192 },
193 [PORT_16750] = {
194 .name = "TI16750",
195 .fifo_size = 64,
196 .tx_loadsz = 64,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
198 UART_FCR7_64BYTE,
199 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
200 },
201 [PORT_STARTECH] = {
202 .name = "Startech",
203 .fifo_size = 1,
204 .tx_loadsz = 1,
205 },
206 [PORT_16C950] = {
207 .name = "16C950/954",
208 .fifo_size = 128,
209 .tx_loadsz = 128,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
d0694e2a
PM		 211 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
212 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
1da177e4
LT		 213 },
214 [PORT_16654] = {
215 .name = "ST16654",
216 .fifo_size = 64,
217 .tx_loadsz = 32,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
219 UART_FCR_T_TRIG_10,
220 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
221 },
222 [PORT_16850] = {
223 .name = "XR16850",
224 .fifo_size = 128,
225 .tx_loadsz = 128,
226 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
227 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
228 },
229 [PORT_RSA] = {
230 .name = "RSA",
231 .fifo_size = 2048,
232 .tx_loadsz = 2048,
233 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
234 .flags = UART_CAP_FIFO,
235 },
236 [PORT_NS16550A] = {
237 .name = "NS16550A",
238 .fifo_size = 16,
239 .tx_loadsz = 16,
240 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
241 .flags = UART_CAP_FIFO | UART_NATSEMI,
242 },
243 [PORT_XSCALE] = {
244 .name = "XScale",
245 .fifo_size = 32,
246 .tx_loadsz = 32,
247 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
4539c24f 248 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
1da177e4 249 },
bd71c182
TK		 250 [PORT_RM9000] = {
251 .name = "RM9000",
252 .fifo_size = 16,
253 .tx_loadsz = 16,
254 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 255 .flags = UART_CAP_FIFO,
256 },
257 [PORT_OCTEON] = {
258 .name = "OCTEON",
259 .fifo_size = 64,
260 .tx_loadsz = 64,
261 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 262 .flags = UART_CAP_FIFO,
263 },
08e0992f
FF		 264 [PORT_AR7] = {
265 .name = "AR7",
266 .fifo_size = 16,
267 .tx_loadsz = 16,
268 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
269 .flags = UART_CAP_FIFO | UART_CAP_AFE,
270 },
235dae5d
PL		 271 [PORT_U6_16550A] = {
272 .name = "U6_16550A",
273 .fifo_size = 64,
274 .tx_loadsz = 64,
275 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
276 .flags = UART_CAP_FIFO | UART_CAP_AFE,
277 },
4539c24f
SW		 278 [PORT_TEGRA] = {
279 .name = "Tegra",
280 .fifo_size = 32,
281 .tx_loadsz = 8,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
283 UART_FCR_T_TRIG_01,
284 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
285 },
06315348
SH		 286 [PORT_XR17D15X] = {
287 .name = "XR17D15X",
288 .fifo_size = 64,
289 .tx_loadsz = 64,
290 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
291 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
292 },
1da177e4
LT		 293};
294
12bf3f24 295#if defined(CONFIG_MIPS_ALCHEMY)
21c614a7
PA		 296
297/* Au1x00 UART hardware has a weird register layout */
298static const u8 au_io_in_map[] = {
299 [UART_RX] = 0,
300 [UART_IER] = 2,
301 [UART_IIR] = 3,
302 [UART_LCR] = 5,
303 [UART_MCR] = 6,
304 [UART_LSR] = 7,
305 [UART_MSR] = 8,
306};
307
308static const u8 au_io_out_map[] = {
309 [UART_TX] = 1,
310 [UART_IER] = 2,
311 [UART_FCR] = 4,
312 [UART_LCR] = 5,
313 [UART_MCR] = 6,
314};
315
316/* sane hardware needs no mapping */
7d6a07d1 317static inline int map_8250_in_reg(struct uart_port *p, int offset)
21c614a7 318{
7d6a07d1 319 if (p->iotype != UPIO_AU)
21c614a7
PA		 320 return offset;
321 return au_io_in_map[offset];
322}
323
7d6a07d1 324static inline int map_8250_out_reg(struct uart_port *p, int offset)
21c614a7 325{
7d6a07d1 326 if (p->iotype != UPIO_AU)
21c614a7
PA		 327 return offset;
328 return au_io_out_map[offset];
329}
330
6f803cd0 331#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 332
333static const u8
334 regmap_in[8] = {
335 [UART_RX] = 0x00,
336 [UART_IER] = 0x0c,
337 [UART_IIR] = 0x14,
338 [UART_LCR] = 0x1c,
339 [UART_MCR] = 0x20,
340 [UART_LSR] = 0x24,
341 [UART_MSR] = 0x28,
342 [UART_SCR] = 0x2c
343 },
344 regmap_out[8] = {
345 [UART_TX] = 0x04,
346 [UART_IER] = 0x0c,
347 [UART_FCR] = 0x18,
348 [UART_LCR] = 0x1c,
349 [UART_MCR] = 0x20,
350 [UART_LSR] = 0x24,
351 [UART_MSR] = 0x28,
352 [UART_SCR] = 0x2c
353 };
354
7d6a07d1 355static inline int map_8250_in_reg(struct uart_port *p, int offset)
bd71c182 356{
7d6a07d1 357 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 358 return offset;
359 return regmap_in[offset];
360}
361
7d6a07d1 362static inline int map_8250_out_reg(struct uart_port *p, int offset)
bd71c182 363{
7d6a07d1 364 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 365 return offset;
366 return regmap_out[offset];
367}
368
21c614a7
PA		 369#else
370
371/* sane hardware needs no mapping */
372#define map_8250_in_reg(up, offset) (offset)
373#define map_8250_out_reg(up, offset) (offset)
374
375#endif
376
7d6a07d1 377static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 378{
7d6a07d1
DD		 379 offset = map_8250_in_reg(p, offset) << p->regshift;
380 outb(p->hub6 - 1 + offset, p->iobase);
381 return inb(p->iobase + 1);
382}
1da177e4 383
7d6a07d1
DD		 384static void hub6_serial_out(struct uart_port *p, int offset, int value)
385{
386 offset = map_8250_out_reg(p, offset) << p->regshift;
387 outb(p->hub6 - 1 + offset, p->iobase);
388 outb(value, p->iobase + 1);
389}
1da177e4 390
7d6a07d1
DD		 391static unsigned int mem_serial_in(struct uart_port *p, int offset)
392{
393 offset = map_8250_in_reg(p, offset) << p->regshift;
394 return readb(p->membase + offset);
395}
1da177e4 396
7d6a07d1
DD		 397static void mem_serial_out(struct uart_port *p, int offset, int value)
398{
399 offset = map_8250_out_reg(p, offset) << p->regshift;
400 writeb(value, p->membase + offset);
401}
402
403static void mem32_serial_out(struct uart_port *p, int offset, int value)
404{
405 offset = map_8250_out_reg(p, offset) << p->regshift;
406 writel(value, p->membase + offset);
407}
408
409static unsigned int mem32_serial_in(struct uart_port *p, int offset)
410{
411 offset = map_8250_in_reg(p, offset) << p->regshift;
412 return readl(p->membase + offset);
413}
1da177e4 414
7d6a07d1
DD		 415static unsigned int au_serial_in(struct uart_port *p, int offset)
416{
417 offset = map_8250_in_reg(p, offset) << p->regshift;
418 return __raw_readl(p->membase + offset);
419}
420
421static void au_serial_out(struct uart_port *p, int offset, int value)
422{
423 offset = map_8250_out_reg(p, offset) << p->regshift;
424 __raw_writel(value, p->membase + offset);
425}
21c614a7 426
7d6a07d1
DD		 427static unsigned int io_serial_in(struct uart_port *p, int offset)
428{
429 offset = map_8250_in_reg(p, offset) << p->regshift;
430 return inb(p->iobase + offset);
431}
432
433static void io_serial_out(struct uart_port *p, int offset, int value)
434{
435 offset = map_8250_out_reg(p, offset) << p->regshift;
436 outb(value, p->iobase + offset);
437}
438
583d28e9
JI		 439static int serial8250_default_handle_irq(struct uart_port *port);
440
7d6a07d1
DD		 441static void set_io_from_upio(struct uart_port *p)
442{
49d5741b
JI		 443 struct uart_8250_port *up =
444 container_of(p, struct uart_8250_port, port);
7d6a07d1 445 switch (p->iotype) {
1da177e4 446 case UPIO_HUB6:
7d6a07d1
DD		 447 p->serial_in = hub6_serial_in;
448 p->serial_out = hub6_serial_out;
1da177e4
LT		 449 break;
450
451 case UPIO_MEM:
7d6a07d1
DD		 452 p->serial_in = mem_serial_in;
453 p->serial_out = mem_serial_out;
1da177e4
LT		 454 break;
455
bd71c182 456 case UPIO_RM9000:
1da177e4 457 case UPIO_MEM32:
7d6a07d1
DD		 458 p->serial_in = mem32_serial_in;
459 p->serial_out = mem32_serial_out;
1da177e4
LT		 460 break;
461
21c614a7 462 case UPIO_AU:
7d6a07d1
DD		 463 p->serial_in = au_serial_in;
464 p->serial_out = au_serial_out;
21c614a7 465 break;
12bf3f24 466
1da177e4 467 default:
7d6a07d1
DD		 468 p->serial_in = io_serial_in;
469 p->serial_out = io_serial_out;
470 break;
1da177e4 471 }
b8e7e40a
AC		 472 /* Remember loaded iotype */
473 up->cur_iotype = p->iotype;
583d28e9 474 p->handle_irq = serial8250_default_handle_irq;
1da177e4
LT		 475}
476
40b36daa
AW		 477static void
478serial_out_sync(struct uart_8250_port *up, int offset, int value)
479{
7d6a07d1
DD		 480 struct uart_port *p = &up->port;
481 switch (p->iotype) {
40b36daa
AW		 482 case UPIO_MEM:
483 case UPIO_MEM32:
40b36daa 484 case UPIO_AU:
7d6a07d1
DD		 485 p->serial_out(p, offset, value);
486 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 487 break;
488 default:
7d6a07d1 489 p->serial_out(p, offset, value);
40b36daa
AW		 490 }
491}
492
7d6a07d1
DD		 493#define serial_in(up, offset) \
494 (up->port.serial_in(&(up)->port, (offset)))
495#define serial_out(up, offset, value) \
496 (up->port.serial_out(&(up)->port, (offset), (value)))
1da177e4
LT		 497/*
498 * We used to support using pause I/O for certain machines. We
499 * haven't supported this for a while, but just in case it's badly
500 * needed for certain old 386 machines, I've left these #define's
501 * in....
502 */
503#define serial_inp(up, offset) serial_in(up, offset)
504#define serial_outp(up, offset, value) serial_out(up, offset, value)
505
b32b19b8
JAH		 506/* Uart divisor latch read */
507static inline int _serial_dl_read(struct uart_8250_port *up)
508{
509 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
510}
511
512/* Uart divisor latch write */
513static inline void _serial_dl_write(struct uart_8250_port *up, int value)
514{
515 serial_outp(up, UART_DLL, value & 0xff);
516 serial_outp(up, UART_DLM, value >> 8 & 0xff);
517}
518
12bf3f24 519#if defined(CONFIG_MIPS_ALCHEMY)
b32b19b8
JAH		 520/* Au1x00 haven't got a standard divisor latch */
521static int serial_dl_read(struct uart_8250_port *up)
522{
523 if (up->port.iotype == UPIO_AU)
524 return __raw_readl(up->port.membase + 0x28);
525 else
526 return _serial_dl_read(up);
527}
528
529static void serial_dl_write(struct uart_8250_port *up, int value)
530{
531 if (up->port.iotype == UPIO_AU)
532 __raw_writel(value, up->port.membase + 0x28);
533 else
534 _serial_dl_write(up, value);
535}
6f803cd0 536#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 537static int serial_dl_read(struct uart_8250_port *up)
538{
539 return (up->port.iotype == UPIO_RM9000) ?
540 (((__raw_readl(up->port.membase + 0x10) << 8) |
541 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
542 _serial_dl_read(up);
543}
544
545static void serial_dl_write(struct uart_8250_port *up, int value)
546{
547 if (up->port.iotype == UPIO_RM9000) {
548 __raw_writel(value, up->port.membase + 0x08);
549 __raw_writel(value >> 8, up->port.membase + 0x10);
550 } else {
551 _serial_dl_write(up, value);
552 }
553}
b32b19b8
JAH		 554#else
555#define serial_dl_read(up) _serial_dl_read(up)
556#define serial_dl_write(up, value) _serial_dl_write(up, value)
557#endif
1da177e4
LT		 558
559/*
560 * For the 16C950
561 */
562static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
563{
564 serial_out(up, UART_SCR, offset);
565 serial_out(up, UART_ICR, value);
566}
567
568static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
569{
570 unsigned int value;
571
572 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
573 serial_out(up, UART_SCR, offset);
574 value = serial_in(up, UART_ICR);
575 serial_icr_write(up, UART_ACR, up->acr);
576
577 return value;
578}
579
580/*
581 * FIFO support.
582 */
b5d674ab 583static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 584{
585 if (p->capabilities & UART_CAP_FIFO) {
586 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
587 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
588 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
589 serial_outp(p, UART_FCR, 0);
590 }
591}
592
593/*
594 * IER sleep support. UARTs which have EFRs need the "extended
595 * capability" bit enabled. Note that on XR16C850s, we need to
596 * reset LCR to write to IER.
597 */
b5d674ab 598static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4
LT		 599{
600 if (p->capabilities & UART_CAP_SLEEP) {
601 if (p->capabilities & UART_CAP_EFR) {
662b083a 602 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 603 serial_outp(p, UART_EFR, UART_EFR_ECB);
604 serial_outp(p, UART_LCR, 0);
605 }
606 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
607 if (p->capabilities & UART_CAP_EFR) {
662b083a 608 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 609 serial_outp(p, UART_EFR, 0);
610 serial_outp(p, UART_LCR, 0);
611 }
612 }
613}
614
615#ifdef CONFIG_SERIAL_8250_RSA
616/*
617 * Attempts to turn on the RSA FIFO. Returns zero on failure.
618 * We set the port uart clock rate if we succeed.
619 */
620static int __enable_rsa(struct uart_8250_port *up)
621{
622 unsigned char mode;
623 int result;
624
625 mode = serial_inp(up, UART_RSA_MSR);
626 result = mode & UART_RSA_MSR_FIFO;
627
628 if (!result) {
629 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
630 mode = serial_inp(up, UART_RSA_MSR);
631 result = mode & UART_RSA_MSR_FIFO;
632 }
633
634 if (result)
635 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
636
637 return result;
638}
639
640static void enable_rsa(struct uart_8250_port *up)
641{
642 if (up->port.type == PORT_RSA) {
643 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
644 spin_lock_irq(&up->port.lock);
645 __enable_rsa(up);
646 spin_unlock_irq(&up->port.lock);
647 }
648 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
649 serial_outp(up, UART_RSA_FRR, 0);
650 }
651}
652
653/*
654 * Attempts to turn off the RSA FIFO. Returns zero on failure.
655 * It is unknown why interrupts were disabled in here. However,
656 * the caller is expected to preserve this behaviour by grabbing
657 * the spinlock before calling this function.
658 */
659static void disable_rsa(struct uart_8250_port *up)
660{
661 unsigned char mode;
662 int result;
663
664 if (up->port.type == PORT_RSA &&
665 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
666 spin_lock_irq(&up->port.lock);
667
668 mode = serial_inp(up, UART_RSA_MSR);
669 result = !(mode & UART_RSA_MSR_FIFO);
670
671 if (!result) {
672 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
673 mode = serial_inp(up, UART_RSA_MSR);
674 result = !(mode & UART_RSA_MSR_FIFO);
675 }
676
677 if (result)
678 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
679 spin_unlock_irq(&up->port.lock);
680 }
681}
682#endif /* CONFIG_SERIAL_8250_RSA */
683
684/*
685 * This is a quickie test to see how big the FIFO is.
686 * It doesn't work at all the time, more's the pity.
687 */
688static int size_fifo(struct uart_8250_port *up)
689{
b32b19b8
JAH		 690 unsigned char old_fcr, old_mcr, old_lcr;
691 unsigned short old_dl;
1da177e4
LT		 692 int count;
693
694 old_lcr = serial_inp(up, UART_LCR);
695 serial_outp(up, UART_LCR, 0);
696 old_fcr = serial_inp(up, UART_FCR);
697 old_mcr = serial_inp(up, UART_MCR);
698 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
699 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
700 serial_outp(up, UART_MCR, UART_MCR_LOOP);
662b083a 701 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8
JAH		 702 old_dl = serial_dl_read(up);
703 serial_dl_write(up, 0x0001);
1da177e4
LT		 704 serial_outp(up, UART_LCR, 0x03);
705 for (count = 0; count < 256; count++)
706 serial_outp(up, UART_TX, count);
707 mdelay(20);/* FIXME - schedule_timeout */
708 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
709 (count < 256); count++)
710 serial_inp(up, UART_RX);
711 serial_outp(up, UART_FCR, old_fcr);
712 serial_outp(up, UART_MCR, old_mcr);
662b083a 713 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
b32b19b8 714 serial_dl_write(up, old_dl);
1da177e4
LT		 715 serial_outp(up, UART_LCR, old_lcr);
716
717 return count;
718}
719
720/*
721 * Read UART ID using the divisor method - set DLL and DLM to zero
722 * and the revision will be in DLL and device type in DLM. We
723 * preserve the device state across this.
724 */
725static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
726{
727 unsigned char old_dll, old_dlm, old_lcr;
728 unsigned int id;
729
730 old_lcr = serial_inp(p, UART_LCR);
662b083a 731 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 732
733 old_dll = serial_inp(p, UART_DLL);
734 old_dlm = serial_inp(p, UART_DLM);
735
736 serial_outp(p, UART_DLL, 0);
737 serial_outp(p, UART_DLM, 0);
738
739 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
740
741 serial_outp(p, UART_DLL, old_dll);
742 serial_outp(p, UART_DLM, old_dlm);
743 serial_outp(p, UART_LCR, old_lcr);
744
745 return id;
746}
747
748/*
749 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
750 * When this function is called we know it is at least a StarTech
751 * 16650 V2, but it might be one of several StarTech UARTs, or one of
752 * its clones. (We treat the broken original StarTech 16650 V1 as a
753 * 16550, and why not? Startech doesn't seem to even acknowledge its
754 * existence.)
bd71c182 755 *
1da177e4
LT		 756 * What evil have men's minds wrought...
757 */
758static void autoconfig_has_efr(struct uart_8250_port *up)
759{
760 unsigned int id1, id2, id3, rev;
761
762 /*
763 * Everything with an EFR has SLEEP
764 */
765 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
766
767 /*
768 * First we check to see if it's an Oxford Semiconductor UART.
769 *
770 * If we have to do this here because some non-National
771 * Semiconductor clone chips lock up if you try writing to the
772 * LSR register (which serial_icr_read does)
773 */
774
775 /*
776 * Check for Oxford Semiconductor 16C950.
777 *
778 * EFR [4] must be set else this test fails.
779 *
780 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
781 * claims that it's needed for 952 dual UART's (which are not
782 * recommended for new designs).
783 */
784 up->acr = 0;
662b083a 785 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 786 serial_out(up, UART_EFR, UART_EFR_ECB);
787 serial_out(up, UART_LCR, 0x00);
788 id1 = serial_icr_read(up, UART_ID1);
789 id2 = serial_icr_read(up, UART_ID2);
790 id3 = serial_icr_read(up, UART_ID3);
791 rev = serial_icr_read(up, UART_REV);
792
793 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
794
795 if (id1 == 0x16 && id2 == 0xC9 &&
796 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
797 up->port.type = PORT_16C950;
4ba5e35d
RK		 798
799 /*
800 * Enable work around for the Oxford Semiconductor 952 rev B
801 * chip which causes it to seriously miscalculate baud rates
802 * when DLL is 0.
803 */
804 if (id3 == 0x52 && rev == 0x01)
805 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 806 return;
807 }
bd71c182 808
1da177e4
LT		 809 /*
810 * We check for a XR16C850 by setting DLL and DLM to 0, and then
811 * reading back DLL and DLM. The chip type depends on the DLM
812 * value read back:
813 * 0x10 - XR16C850 and the DLL contains the chip revision.
814 * 0x12 - XR16C2850.
815 * 0x14 - XR16C854.
816 */
817 id1 = autoconfig_read_divisor_id(up);
818 DEBUG_AUTOCONF("850id=%04x ", id1);
819
820 id2 = id1 >> 8;
821 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 822 up->port.type = PORT_16850;
823 return;
824 }
825
826 /*
827 * It wasn't an XR16C850.
828 *
829 * We distinguish between the '654 and the '650 by counting
830 * how many bytes are in the FIFO. I'm using this for now,
831 * since that's the technique that was sent to me in the
832 * serial driver update, but I'm not convinced this works.
833 * I've had problems doing this in the past. -TYT
834 */
835 if (size_fifo(up) == 64)
836 up->port.type = PORT_16654;
837 else
838 up->port.type = PORT_16650V2;
839}
840
841/*
842 * We detected a chip without a FIFO. Only two fall into
843 * this category - the original 8250 and the 16450. The
844 * 16450 has a scratch register (accessible with LCR=0)
845 */
846static void autoconfig_8250(struct uart_8250_port *up)
847{
848 unsigned char scratch, status1, status2;
849
850 up->port.type = PORT_8250;
851
852 scratch = serial_in(up, UART_SCR);
853 serial_outp(up, UART_SCR, 0xa5);
854 status1 = serial_in(up, UART_SCR);
855 serial_outp(up, UART_SCR, 0x5a);
856 status2 = serial_in(up, UART_SCR);
857 serial_outp(up, UART_SCR, scratch);
858
859 if (status1 == 0xa5 && status2 == 0x5a)
860 up->port.type = PORT_16450;
861}
862
863static int broken_efr(struct uart_8250_port *up)
864{
865 /*
866 * Exar ST16C2550 "A2" devices incorrectly detect as
867 * having an EFR, and report an ID of 0x0201. See
631dd1a8 868 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1da177e4
LT		 869 */
870 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
871 return 1;
872
873 return 0;
874}
875
0d0389e5
YK		 876static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
877{
878 unsigned char status;
879
880 status = serial_in(up, 0x04); /* EXCR2 */
881#define PRESL(x) ((x) & 0x30)
882 if (PRESL(status) == 0x10) {
883 /* already in high speed mode */
884 return 0;
885 } else {
886 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
887 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
888 serial_outp(up, 0x04, status);
889 }
890 return 1;
891}
892
1da177e4
LT		 893/*
894 * We know that the chip has FIFOs. Does it have an EFR? The
895 * EFR is located in the same register position as the IIR and
896 * we know the top two bits of the IIR are currently set. The
897 * EFR should contain zero. Try to read the EFR.
898 */
899static void autoconfig_16550a(struct uart_8250_port *up)
900{
901 unsigned char status1, status2;
902 unsigned int iersave;
903
904 up->port.type = PORT_16550A;
905 up->capabilities |= UART_CAP_FIFO;
906
907 /*
908 * Check for presence of the EFR when DLAB is set.
909 * Only ST16C650V1 UARTs pass this test.
910 */
662b083a 911 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 912 if (serial_in(up, UART_EFR) == 0) {
913 serial_outp(up, UART_EFR, 0xA8);
914 if (serial_in(up, UART_EFR) != 0) {
915 DEBUG_AUTOCONF("EFRv1 ");
916 up->port.type = PORT_16650;
917 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
918 } else {
919 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
920 }
921 serial_outp(up, UART_EFR, 0);
922 return;
923 }
924
925 /*
926 * Maybe it requires 0xbf to be written to the LCR.
927 * (other ST16C650V2 UARTs, TI16C752A, etc)
928 */
662b083a 929 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 930 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
931 DEBUG_AUTOCONF("EFRv2 ");
932 autoconfig_has_efr(up);
933 return;
934 }
935
936 /*
937 * Check for a National Semiconductor SuperIO chip.
938 * Attempt to switch to bank 2, read the value of the LOOP bit
939 * from EXCR1. Switch back to bank 0, change it in MCR. Then
940 * switch back to bank 2, read it from EXCR1 again and check
941 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 942 */
943 serial_outp(up, UART_LCR, 0);
944 status1 = serial_in(up, UART_MCR);
945 serial_outp(up, UART_LCR, 0xE0);
946 status2 = serial_in(up, 0x02); /* EXCR1 */
947
948 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
949 serial_outp(up, UART_LCR, 0);
950 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
951 serial_outp(up, UART_LCR, 0xE0);
952 status2 = serial_in(up, 0x02); /* EXCR1 */
953 serial_outp(up, UART_LCR, 0);
954 serial_outp(up, UART_MCR, status1);
955
956 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 957 unsigned short quot;
958
1da177e4 959 serial_outp(up, UART_LCR, 0xE0);
857dde2e 960
b32b19b8 961 quot = serial_dl_read(up);
857dde2e
DW		 962 quot <<= 3;
963
0d0389e5
YK		 964 if (ns16550a_goto_highspeed(up))
965 serial_dl_write(up, quot);
857dde2e 966
1da177e4 967 serial_outp(up, UART_LCR, 0);
1da177e4 968
857dde2e 969 up->port.uartclk = 921600*16;
1da177e4
LT		 970 up->port.type = PORT_NS16550A;
971 up->capabilities |= UART_NATSEMI;
972 return;
973 }
974 }
975
976 /*
977 * No EFR. Try to detect a TI16750, which only sets bit 5 of
978 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
979 * Try setting it with and without DLAB set. Cheap clones
980 * set bit 5 without DLAB set.
981 */
982 serial_outp(up, UART_LCR, 0);
983 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
984 status1 = serial_in(up, UART_IIR) >> 5;
985 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
662b083a 986 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1da177e4
LT		 987 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
988 status2 = serial_in(up, UART_IIR) >> 5;
989 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
990 serial_outp(up, UART_LCR, 0);
991
992 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
993
994 if (status1 == 6 && status2 == 7) {
995 up->port.type = PORT_16750;
996 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
997 return;
998 }
999
1000 /*
1001 * Try writing and reading the UART_IER_UUE bit (b6).
1002 * If it works, this is probably one of the Xscale platform's
1003 * internal UARTs.
1004 * We're going to explicitly set the UUE bit to 0 before
1005 * trying to write and read a 1 just to make sure it's not
1006 * already a 1 and maybe locked there before we even start start.
1007 */
1008 iersave = serial_in(up, UART_IER);
1009 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1010 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1011 /*
1012 * OK it's in a known zero state, try writing and reading
1013 * without disturbing the current state of the other bits.
1014 */
1015 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1016 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1017 /*
1018 * It's an Xscale.
1019 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1020 */
1021 DEBUG_AUTOCONF("Xscale ");
1022 up->port.type = PORT_XSCALE;
5568181f 1023 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1da177e4
LT		 1024 return;
1025 }
1026 } else {
1027 /*
1028 * If we got here we couldn't force the IER_UUE bit to 0.
1029 * Log it and continue.
1030 */
1031 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1032 }
1033 serial_outp(up, UART_IER, iersave);
235dae5d 1034
06315348
SH		 1035 /*
1036 * Exar uarts have EFR in a weird location
1037 */
1038 if (up->port.flags & UPF_EXAR_EFR) {
1039 up->port.type = PORT_XR17D15X;
1040 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1041 }
1042
235dae5d
PL		 1043 /*
1044 * We distinguish between 16550A and U6 16550A by counting
1045 * how many bytes are in the FIFO.
1046 */
1047 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1048 up->port.type = PORT_U6_16550A;
1049 up->capabilities |= UART_CAP_AFE;
1050 }
1da177e4
LT		 1051}
1052
1053/*
1054 * This routine is called by rs_init() to initialize a specific serial
1055 * port. It determines what type of UART chip this serial port is
1056 * using: 8250, 16450, 16550, 16550A. The important question is
1057 * whether or not this UART is a 16550A or not, since this will
1058 * determine whether or not we can use its FIFO features or not.
1059 */
1060static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1061{
1062 unsigned char status1, scratch, scratch2, scratch3;
1063 unsigned char save_lcr, save_mcr;
1064 unsigned long flags;
1065
1066 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1067 return;
1068
80647b95 1069 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
8440838b 1070 serial_index(&up->port), up->port.iobase, up->port.membase);
1da177e4
LT		 1071
1072 /*
1073 * We really do need global IRQs disabled here - we're going to
1074 * be frobbing the chips IRQ enable register to see if it exists.
1075 */
1076 spin_lock_irqsave(&up->port.lock, flags);
1da177e4
LT		 1077
1078 up->capabilities = 0;
4ba5e35d 1079 up->bugs = 0;
1da177e4
LT		 1080
1081 if (!(up->port.flags & UPF_BUGGY_UART)) {
1082 /*
1083 * Do a simple existence test first; if we fail this,
1084 * there's no point trying anything else.
bd71c182 1085 *
1da177e4
LT		 1086 * 0x80 is used as a nonsense port to prevent against
1087 * false positives due to ISA bus float. The
1088 * assumption is that 0x80 is a non-existent port;
1089 * which should be safe since include/asm/io.h also
1090 * makes this assumption.
1091 *
1092 * Note: this is safe as long as MCR bit 4 is clear
1093 * and the device is in "PC" mode.
1094 */
1095 scratch = serial_inp(up, UART_IER);
1096 serial_outp(up, UART_IER, 0);
1097#ifdef __i386__
1098 outb(0xff, 0x080);
1099#endif
48212008
TH		 1100 /*
1101 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1102 * 16C754B) allow only to modify them if an EFR bit is set.
1103 */
1104 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1105 serial_outp(up, UART_IER, 0x0F);
1106#ifdef __i386__
1107 outb(0, 0x080);
1108#endif
48212008 1109 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1110 serial_outp(up, UART_IER, scratch);
1111 if (scratch2 != 0 || scratch3 != 0x0F) {
1112 /*
1113 * We failed; there's nothing here
1114 */
1115 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1116 scratch2, scratch3);
1117 goto out;
1118 }
1119 }
1120
1121 save_mcr = serial_in(up, UART_MCR);
1122 save_lcr = serial_in(up, UART_LCR);
1123
bd71c182 1124 /*
1da177e4
LT		 1125 * Check to see if a UART is really there. Certain broken
1126 * internal modems based on the Rockwell chipset fail this
1127 * test, because they apparently don't implement the loopback
1128 * test mode. So this test is skipped on the COM 1 through
1129 * COM 4 ports. This *should* be safe, since no board
1130 * manufacturer would be stupid enough to design a board
1131 * that conflicts with COM 1-4 --- we hope!
1132 */
1133 if (!(up->port.flags & UPF_SKIP_TEST)) {
1134 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1135 status1 = serial_inp(up, UART_MSR) & 0xF0;
1136 serial_outp(up, UART_MCR, save_mcr);
1137 if (status1 != 0x90) {
1138 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1139 status1);
1140 goto out;
1141 }
1142 }
1143
1144 /*
1145 * We're pretty sure there's a port here. Lets find out what
1146 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1147 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1148 * determines what we test for next.
1149 *
1150 * We also initialise the EFR (if any) to zero for later. The
1151 * EFR occupies the same register location as the FCR and IIR.
1152 */
662b083a 1153 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 1154 serial_outp(up, UART_EFR, 0);
1155 serial_outp(up, UART_LCR, 0);
1156
1157 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1158 scratch = serial_in(up, UART_IIR) >> 6;
1159
1160 DEBUG_AUTOCONF("iir=%d ", scratch);
1161
1162 switch (scratch) {
1163 case 0:
1164 autoconfig_8250(up);
1165 break;
1166 case 1:
1167 up->port.type = PORT_UNKNOWN;
1168 break;
1169 case 2:
1170 up->port.type = PORT_16550;
1171 break;
1172 case 3:
1173 autoconfig_16550a(up);
1174 break;
1175 }
1176
1177#ifdef CONFIG_SERIAL_8250_RSA
1178 /*
1179 * Only probe for RSA ports if we got the region.
1180 */
1181 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1182 int i;
1183
1184 for (i = 0 ; i < probe_rsa_count; ++i) {
1185 if (probe_rsa[i] == up->port.iobase &&
1186 __enable_rsa(up)) {
1187 up->port.type = PORT_RSA;
1188 break;
1189 }
1190 }
1191 }
1192#endif
21c614a7 1193
1da177e4
LT		 1194 serial_outp(up, UART_LCR, save_lcr);
1195
1196 if (up->capabilities != uart_config[up->port.type].flags) {
1197 printk(KERN_WARNING
1198 "ttyS%d: detected caps %08x should be %08x\n",
8440838b
DM		 1199 serial_index(&up->port), up->capabilities,
1200 uart_config[up->port.type].flags);
1da177e4
LT		 1201 }
1202
1203 up->port.fifosize = uart_config[up->port.type].fifo_size;
1204 up->capabilities = uart_config[up->port.type].flags;
1205 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1206
1207 if (up->port.type == PORT_UNKNOWN)
1208 goto out;
1209
1210 /*
1211 * Reset the UART.
1212 */
1213#ifdef CONFIG_SERIAL_8250_RSA
1214 if (up->port.type == PORT_RSA)
1215 serial_outp(up, UART_RSA_FRR, 0);
1216#endif
1217 serial_outp(up, UART_MCR, save_mcr);
1218 serial8250_clear_fifos(up);
40b36daa 1219 serial_in(up, UART_RX);
5c8c755c
LB		 1220 if (up->capabilities & UART_CAP_UUE)
1221 serial_outp(up, UART_IER, UART_IER_UUE);
1222 else
1223 serial_outp(up, UART_IER, 0);
1da177e4 1224
bd71c182 1225 out:
1da177e4 1226 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1227 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1228}
1229
1230static void autoconfig_irq(struct uart_8250_port *up)
1231{
1232 unsigned char save_mcr, save_ier;
1233 unsigned char save_ICP = 0;
1234 unsigned int ICP = 0;
1235 unsigned long irqs;
1236 int irq;
1237
1238 if (up->port.flags & UPF_FOURPORT) {
1239 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1240 save_ICP = inb_p(ICP);
1241 outb_p(0x80, ICP);
1242 (void) inb_p(ICP);
1243 }
1244
1245 /* forget possible initially masked and pending IRQ */
1246 probe_irq_off(probe_irq_on());
1247 save_mcr = serial_inp(up, UART_MCR);
1248 save_ier = serial_inp(up, UART_IER);
1249 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1250
1da177e4
LT		 1251 irqs = probe_irq_on();
1252 serial_outp(up, UART_MCR, 0);
6f803cd0
AC		 1253 udelay(10);
1254 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 1255 serial_outp(up, UART_MCR,
1256 UART_MCR_DTR | UART_MCR_RTS);
1257 } else {
1258 serial_outp(up, UART_MCR,
1259 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1260 }
1261 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1262 (void)serial_inp(up, UART_LSR);
1263 (void)serial_inp(up, UART_RX);
1264 (void)serial_inp(up, UART_IIR);
1265 (void)serial_inp(up, UART_MSR);
1266 serial_outp(up, UART_TX, 0xFF);
6f803cd0 1267 udelay(20);
1da177e4
LT		 1268 irq = probe_irq_off(irqs);
1269
1270 serial_outp(up, UART_MCR, save_mcr);
1271 serial_outp(up, UART_IER, save_ier);
1272
1273 if (up->port.flags & UPF_FOURPORT)
1274 outb_p(save_ICP, ICP);
1275
1276 up->port.irq = (irq > 0) ? irq : 0;
1277}
1278
e763b90c
RK		 1279static inline void __stop_tx(struct uart_8250_port *p)
1280{
1281 if (p->ier & UART_IER_THRI) {
1282 p->ier &= ~UART_IER_THRI;
1283 serial_out(p, UART_IER, p->ier);
1284 }
1285}
1286
b129a8cc 1287static void serial8250_stop_tx(struct uart_port *port)
1da177e4 1288{
49d5741b
JI		 1289 struct uart_8250_port *up =
1290 container_of(port, struct uart_8250_port, port);
1da177e4 1291
e763b90c 1292 __stop_tx(up);
1da177e4
LT		 1293
1294 /*
e763b90c 1295 * We really want to stop the transmitter from sending.
1da177e4 1296 */
e763b90c 1297 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1298 up->acr |= UART_ACR_TXDIS;
1299 serial_icr_write(up, UART_ACR, up->acr);
1300 }
1301}
1302
55d3b282
RK		 1303static void transmit_chars(struct uart_8250_port *up);
1304
b129a8cc 1305static void serial8250_start_tx(struct uart_port *port)
1da177e4 1306{
49d5741b
JI		 1307 struct uart_8250_port *up =
1308 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1309
1310 if (!(up->ier & UART_IER_THRI)) {
1311 up->ier |= UART_IER_THRI;
1312 serial_out(up, UART_IER, up->ier);
55d3b282 1313
67f7654e 1314 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1315 unsigned char lsr;
55d3b282 1316 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1317 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
bd71c182 1318 if ((up->port.type == PORT_RM9000) ?
68cb4f8e
IJ		 1319 (lsr & UART_LSR_THRE) :
1320 (lsr & UART_LSR_TEMT))
55d3b282
RK		 1321 transmit_chars(up);
1322 }
1da177e4 1323 }
e763b90c 1324
1da177e4 1325 /*
e763b90c 1326 * Re-enable the transmitter if we disabled it.
1da177e4 1327 */
e763b90c 1328 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1329 up->acr &= ~UART_ACR_TXDIS;
1330 serial_icr_write(up, UART_ACR, up->acr);
1331 }
1332}
1333
1334static void serial8250_stop_rx(struct uart_port *port)
1335{
49d5741b
JI		 1336 struct uart_8250_port *up =
1337 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1338
1339 up->ier &= ~UART_IER_RLSI;
1340 up->port.read_status_mask &= ~UART_LSR_DR;
1341 serial_out(up, UART_IER, up->ier);
1342}
1343
1344static void serial8250_enable_ms(struct uart_port *port)
1345{
49d5741b
JI		 1346 struct uart_8250_port *up =
1347 container_of(port, struct uart_8250_port, port);
1da177e4 1348
21c614a7
PA		 1349 /* no MSR capabilities */
1350 if (up->bugs & UART_BUG_NOMSR)
1351 return;
1352
1da177e4
LT		 1353 up->ier |= UART_IER_MSI;
1354 serial_out(up, UART_IER, up->ier);
1355}
1356
5f873bae
SW		 1357/*
1358 * Clear the Tegra rx fifo after a break
1359 *
1360 * FIXME: This needs to become a port specific callback once we have a
1361 * framework for this
1362 */
1363static void clear_rx_fifo(struct uart_8250_port *up)
1364{
1365 unsigned int status, tmout = 10000;
1366 do {
1367 status = serial_in(up, UART_LSR);
1368 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1369 status = serial_in(up, UART_RX);
1370 else
1371 break;
1372 if (--tmout == 0)
1373 break;
1374 udelay(1);
1375 } while (1);
1376}
1377
ea8874dc 1378static void
cc79aa9d 1379receive_chars(struct uart_8250_port *up, unsigned int *status)
1da177e4 1380{
ebd2c8f6 1381 struct tty_struct *tty = up->port.state->port.tty;
1da177e4
LT		 1382 unsigned char ch, lsr = *status;
1383 int max_count = 256;
1384 char flag;
1385
1386 do {
7500b1f6
AR		 1387 if (likely(lsr & UART_LSR_DR))
1388 ch = serial_inp(up, UART_RX);
1389 else
1390 /*
1391 * Intel 82571 has a Serial Over Lan device that will
1392 * set UART_LSR_BI without setting UART_LSR_DR when
1393 * it receives a break. To avoid reading from the
1394 * receive buffer without UART_LSR_DR bit set, we
1395 * just force the read character to be 0
1396 */
1397 ch = 0;
1398
1da177e4
LT		 1399 flag = TTY_NORMAL;
1400 up->port.icount.rx++;
1401
ad4c2aa6
CM		 1402 lsr |= up->lsr_saved_flags;
1403 up->lsr_saved_flags = 0;
1da177e4 1404
ad4c2aa6 1405 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1406 /*
1407 * For statistics only
1408 */
1409 if (lsr & UART_LSR_BI) {
1410 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1411 up->port.icount.brk++;
5f873bae
SW		 1412 /*
1413 * If tegra port then clear the rx fifo to
1414 * accept another break/character.
1415 */
1416 if (up->port.type == PORT_TEGRA)
1417 clear_rx_fifo(up);
1418
1da177e4
LT		 1419 /*
1420 * We do the SysRQ and SAK checking
1421 * here because otherwise the break
1422 * may get masked by ignore_status_mask
1423 * or read_status_mask.
1424 */
1425 if (uart_handle_break(&up->port))
1426 goto ignore_char;
1427 } else if (lsr & UART_LSR_PE)
1428 up->port.icount.parity++;
1429 else if (lsr & UART_LSR_FE)
1430 up->port.icount.frame++;
1431 if (lsr & UART_LSR_OE)
1432 up->port.icount.overrun++;
1433
1434 /*
23907eb8 1435 * Mask off conditions which should be ignored.
1da177e4
LT		 1436 */
1437 lsr &= up->port.read_status_mask;
1438
1439 if (lsr & UART_LSR_BI) {
1440 DEBUG_INTR("handling break....");
1441 flag = TTY_BREAK;
1442 } else if (lsr & UART_LSR_PE)
1443 flag = TTY_PARITY;
1444 else if (lsr & UART_LSR_FE)
1445 flag = TTY_FRAME;
1446 }
7d12e780 1447 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1448 goto ignore_char;
05ab3014
RK		 1449
1450 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1451
6f803cd0 1452ignore_char:
1da177e4 1453 lsr = serial_inp(up, UART_LSR);
7500b1f6 1454 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1da177e4
LT		 1455 spin_unlock(&up->port.lock);
1456 tty_flip_buffer_push(tty);
1457 spin_lock(&up->port.lock);
1458 *status = lsr;
1459}
1460
ea8874dc 1461static void transmit_chars(struct uart_8250_port *up)
1da177e4 1462{
ebd2c8f6 1463 struct circ_buf *xmit = &up->port.state->xmit;
1da177e4
LT		 1464 int count;
1465
1466 if (up->port.x_char) {
1467 serial_outp(up, UART_TX, up->port.x_char);
1468 up->port.icount.tx++;
1469 up->port.x_char = 0;
1470 return;
1471 }
b129a8cc
RK		 1472 if (uart_tx_stopped(&up->port)) {
1473 serial8250_stop_tx(&up->port);
1474 return;
1475 }
1476 if (uart_circ_empty(xmit)) {
e763b90c 1477 __stop_tx(up);
1da177e4
LT		 1478 return;
1479 }
1480
1481 count = up->tx_loadsz;
1482 do {
1483 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1484 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1485 up->port.icount.tx++;
1486 if (uart_circ_empty(xmit))
1487 break;
1488 } while (--count > 0);
1489
1490 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1491 uart_write_wakeup(&up->port);
1492
1493 DEBUG_INTR("THRE...");
1494
1495 if (uart_circ_empty(xmit))
e763b90c 1496 __stop_tx(up);
1da177e4
LT		 1497}
1498
2af7cd68 1499static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1500{
2af7cd68
RK		 1501 unsigned int status = serial_in(up, UART_MSR);
1502
ad4c2aa6
CM		 1503 status |= up->msr_saved_flags;
1504 up->msr_saved_flags = 0;
fdc30b3d 1505 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
ebd2c8f6 1506 up->port.state != NULL) {
2af7cd68
RK		 1507 if (status & UART_MSR_TERI)
1508 up->port.icount.rng++;
1509 if (status & UART_MSR_DDSR)
1510 up->port.icount.dsr++;
1511 if (status & UART_MSR_DDCD)
1512 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1513 if (status & UART_MSR_DCTS)
1514 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1515
bdc04e31 1516 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
2af7cd68 1517 }
1da177e4 1518
2af7cd68 1519 return status;
1da177e4
LT		 1520}
1521
1522/*
1523 * This handles the interrupt from one port.
1524 */
b5d674ab 1525static void serial8250_handle_port(struct uart_8250_port *up)
1da177e4 1526{
45e24601 1527 unsigned int status;
4bf3631c 1528 unsigned long flags;
45e24601 1529
4bf3631c 1530 spin_lock_irqsave(&up->port.lock, flags);
45e24601
RK		 1531
1532 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1533
1534 DEBUG_INTR("status = %x...", status);
1535
7500b1f6 1536 if (status & (UART_LSR_DR | UART_LSR_BI))
7d12e780 1537 receive_chars(up, &status);
1da177e4
LT		 1538 check_modem_status(up);
1539 if (status & UART_LSR_THRE)
1540 transmit_chars(up);
45e24601 1541
4bf3631c 1542 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1543}
1544
583d28e9
JI		 1545int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1546{
1547 struct uart_8250_port *up =
1548 container_of(port, struct uart_8250_port, port);
1549
1550 if (!(iir & UART_IIR_NO_INT)) {
1551 serial8250_handle_port(up);
1552 return 1;
1553 }
1554
1555 return 0;
1556}
c7a1bdc5 1557EXPORT_SYMBOL_GPL(serial8250_handle_irq);
583d28e9
JI		 1558
1559static int serial8250_default_handle_irq(struct uart_port *port)
1560{
1561 struct uart_8250_port *up =
1562 container_of(port, struct uart_8250_port, port);
1563 unsigned int iir = serial_in(up, UART_IIR);
1564
1565 return serial8250_handle_irq(port, iir);
1566}
1567
1da177e4
LT		 1568/*
1569 * This is the serial driver's interrupt routine.
1570 *
1571 * Arjan thinks the old way was overly complex, so it got simplified.
1572 * Alan disagrees, saying that need the complexity to handle the weird
1573 * nature of ISA shared interrupts. (This is a special exception.)
1574 *
1575 * In order to handle ISA shared interrupts properly, we need to check
1576 * that all ports have been serviced, and therefore the ISA interrupt
1577 * line has been de-asserted.
1578 *
1579 * This means we need to loop through all ports. checking that they
1580 * don't have an interrupt pending.
1581 */
7d12e780 1582static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1583{
1584 struct irq_info *i = dev_id;
1585 struct list_head *l, *end = NULL;
1586 int pass_counter = 0, handled = 0;
1587
1588 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1589
1590 spin_lock(&i->lock);
1591
1592 l = i->head;
1593 do {
1594 struct uart_8250_port *up;
583d28e9 1595 struct uart_port *port;
448ac154 1596 bool skip;
1da177e4
LT		 1597
1598 up = list_entry(l, struct uart_8250_port, list);
583d28e9 1599 port = &up->port;
448ac154 1600 skip = pass_counter && up->port.flags & UPF_IIR_ONCE;
1da177e4 1601
448ac154 1602 if (!skip && port->handle_irq(port)) {
1da177e4 1603 handled = 1;
1da177e4
LT		 1604 end = NULL;
1605 } else if (end == NULL)
1606 end = l;
1607
1608 l = l->next;
1609
1610 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1611 /* If we hit this, we're dead. */
cd3ecad1
DD		 1612 printk_ratelimited(KERN_ERR
1613 "serial8250: too much work for irq%d\n", irq);
1da177e4
LT		 1614 break;
1615 }
1616 } while (l != end);
1617
1618 spin_unlock(&i->lock);
1619
1620 DEBUG_INTR("end.\n");
1621
1622 return IRQ_RETVAL(handled);
1623}
1624
1625/*
1626 * To support ISA shared interrupts, we need to have one interrupt
1627 * handler that ensures that the IRQ line has been deasserted
1628 * before returning. Failing to do this will result in the IRQ
1629 * line being stuck active, and, since ISA irqs are edge triggered,
1630 * no more IRQs will be seen.
1631 */
1632static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1633{
1634 spin_lock_irq(&i->lock);
1635
1636 if (!list_empty(i->head)) {
1637 if (i->head == &up->list)
1638 i->head = i->head->next;
1639 list_del(&up->list);
1640 } else {
1641 BUG_ON(i->head != &up->list);
1642 i->head = NULL;
1643 }
1da177e4 1644 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1645 /* List empty so throw away the hash node */
1646 if (i->head == NULL) {
1647 hlist_del(&i->node);
1648 kfree(i);
1649 }
1da177e4
LT		 1650}
1651
1652static int serial_link_irq_chain(struct uart_8250_port *up)
1653{
25db8ad5
AC		 1654 struct hlist_head *h;
1655 struct hlist_node *n;
1656 struct irq_info *i;
40663cc7 1657 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1658
25db8ad5
AC		 1659 mutex_lock(&hash_mutex);
1660
1661 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1662
1663 hlist_for_each(n, h) {
1664 i = hlist_entry(n, struct irq_info, node);
1665 if (i->irq == up->port.irq)
1666 break;
1667 }
1668
1669 if (n == NULL) {
1670 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1671 if (i == NULL) {
1672 mutex_unlock(&hash_mutex);
1673 return -ENOMEM;
1674 }
1675 spin_lock_init(&i->lock);
1676 i->irq = up->port.irq;
1677 hlist_add_head(&i->node, h);
1678 }
1679 mutex_unlock(&hash_mutex);
1680
1da177e4
LT		 1681 spin_lock_irq(&i->lock);
1682
1683 if (i->head) {
1684 list_add(&up->list, i->head);
1685 spin_unlock_irq(&i->lock);
1686
1687 ret = 0;
1688 } else {
1689 INIT_LIST_HEAD(&up->list);
1690 i->head = &up->list;
1691 spin_unlock_irq(&i->lock);
1c2f0493 1692 irq_flags |= up->port.irqflags;
1da177e4
LT		 1693 ret = request_irq(up->port.irq, serial8250_interrupt,
1694 irq_flags, "serial", i);
1695 if (ret < 0)
1696 serial_do_unlink(i, up);
1697 }
1698
1699 return ret;
1700}
1701
1702static void serial_unlink_irq_chain(struct uart_8250_port *up)
1703{
25db8ad5
AC		 1704 struct irq_info *i;
1705 struct hlist_node *n;
1706 struct hlist_head *h;
1da177e4 1707
25db8ad5
AC		 1708 mutex_lock(&hash_mutex);
1709
1710 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1711
1712 hlist_for_each(n, h) {
1713 i = hlist_entry(n, struct irq_info, node);
1714 if (i->irq == up->port.irq)
1715 break;
1716 }
1717
1718 BUG_ON(n == NULL);
1da177e4
LT		 1719 BUG_ON(i->head == NULL);
1720
1721 if (list_empty(i->head))
1722 free_irq(up->port.irq, i);
1723
1724 serial_do_unlink(i, up);
25db8ad5 1725 mutex_unlock(&hash_mutex);
1da177e4
LT		 1726}
1727
1728/*
1729 * This function is used to handle ports that do not have an
1730 * interrupt. This doesn't work very well for 16450's, but gives
1731 * barely passable results for a 16550A. (Although at the expense
1732 * of much CPU overhead).
1733 */
1734static void serial8250_timeout(unsigned long data)
1735{
1736 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4
LT		 1737 unsigned int iir;
1738
1739 iir = serial_in(up, UART_IIR);
45e24601 1740 if (!(iir & UART_IIR_NO_INT))
7d12e780 1741 serial8250_handle_port(up);
54381067 1742 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
40b36daa
AW		 1743}
1744
1745static void serial8250_backup_timeout(unsigned long data)
1746{
1747 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1748 unsigned int iir, ier = 0, lsr;
1749 unsigned long flags;
40b36daa 1750
dbb3b1ca
AC		 1751 spin_lock_irqsave(&up->port.lock, flags);
1752
40b36daa
AW		 1753 /*
1754 * Must disable interrupts or else we risk racing with the interrupt
1755 * based handler.
1756 */
1757 if (is_real_interrupt(up->port.irq)) {
1758 ier = serial_in(up, UART_IER);
1759 serial_out(up, UART_IER, 0);
1760 }
1da177e4 1761
40b36daa
AW		 1762 iir = serial_in(up, UART_IIR);
1763
1764 /*
1765 * This should be a safe test for anyone who doesn't trust the
1766 * IIR bits on their UART, but it's specifically designed for
1767 * the "Diva" UART used on the management processor on many HP
1768 * ia64 and parisc boxes.
1769 */
ad4c2aa6
CM		 1770 lsr = serial_in(up, UART_LSR);
1771 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
40b36daa 1772 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1773 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1774 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1775 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1776 iir |= UART_IIR_THRI;
1777 }
1778
1779 if (!(iir & UART_IIR_NO_INT))
dbb3b1ca 1780 transmit_chars(up);
40b36daa
AW		 1781
1782 if (is_real_interrupt(up->port.irq))
1783 serial_out(up, UART_IER, ier);
1784
dbb3b1ca
AC		 1785 spin_unlock_irqrestore(&up->port.lock, flags);
1786
40b36daa 1787 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0 1788 mod_timer(&up->timer,
54381067 1789 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1da177e4
LT		 1790}
1791
1792static unsigned int serial8250_tx_empty(struct uart_port *port)
1793{
49d5741b
JI		 1794 struct uart_8250_port *up =
1795 container_of(port, struct uart_8250_port, port);
1da177e4 1796 unsigned long flags;
ad4c2aa6 1797 unsigned int lsr;
1da177e4
LT		 1798
1799 spin_lock_irqsave(&up->port.lock, flags);
ad4c2aa6
CM		 1800 lsr = serial_in(up, UART_LSR);
1801 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1da177e4
LT		 1802 spin_unlock_irqrestore(&up->port.lock, flags);
1803
bca47613 1804 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1805}
1806
1807static unsigned int serial8250_get_mctrl(struct uart_port *port)
1808{
49d5741b
JI		 1809 struct uart_8250_port *up =
1810 container_of(port, struct uart_8250_port, port);
2af7cd68 1811 unsigned int status;
1da177e4
LT		 1812 unsigned int ret;
1813
2af7cd68 1814 status = check_modem_status(up);
1da177e4
LT		 1815
1816 ret = 0;
1817 if (status & UART_MSR_DCD)
1818 ret |= TIOCM_CAR;
1819 if (status & UART_MSR_RI)
1820 ret |= TIOCM_RNG;
1821 if (status & UART_MSR_DSR)
1822 ret |= TIOCM_DSR;
1823 if (status & UART_MSR_CTS)
1824 ret |= TIOCM_CTS;
1825 return ret;
1826}
1827
1828static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1829{
49d5741b
JI		 1830 struct uart_8250_port *up =
1831 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1832 unsigned char mcr = 0;
1833
1834 if (mctrl & TIOCM_RTS)
1835 mcr |= UART_MCR_RTS;
1836 if (mctrl & TIOCM_DTR)
1837 mcr |= UART_MCR_DTR;
1838 if (mctrl & TIOCM_OUT1)
1839 mcr |= UART_MCR_OUT1;
1840 if (mctrl & TIOCM_OUT2)
1841 mcr |= UART_MCR_OUT2;
1842 if (mctrl & TIOCM_LOOP)
1843 mcr |= UART_MCR_LOOP;
1844
1845 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1846
1847 serial_out(up, UART_MCR, mcr);
1848}
1849
1850static void serial8250_break_ctl(struct uart_port *port, int break_state)
1851{
49d5741b
JI		 1852 struct uart_8250_port *up =
1853 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 1854 unsigned long flags;
1855
1856 spin_lock_irqsave(&up->port.lock, flags);
1857 if (break_state == -1)
1858 up->lcr |= UART_LCR_SBC;
1859 else
1860 up->lcr &= ~UART_LCR_SBC;
1861 serial_out(up, UART_LCR, up->lcr);
1862 spin_unlock_irqrestore(&up->port.lock, flags);
1863}
1864
40b36daa
AW		 1865/*
1866 * Wait for transmitter & holding register to empty
1867 */
b5d674ab 1868static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1869{
1870 unsigned int status, tmout = 10000;
1871
1872 /* Wait up to 10ms for the character(s) to be sent. */
97d303b7 1873 for (;;) {
40b36daa
AW		 1874 status = serial_in(up, UART_LSR);
1875
ad4c2aa6 1876 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa 1877
97d303b7
DD		 1878 if ((status & bits) == bits)
1879 break;
40b36daa
AW		 1880 if (--tmout == 0)
1881 break;
1882 udelay(1);
97d303b7 1883 }
40b36daa
AW		 1884
1885 /* Wait up to 1s for flow control if necessary */
1886 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1887 unsigned int tmout;
1888 for (tmout = 1000000; tmout; tmout--) {
1889 unsigned int msr = serial_in(up, UART_MSR);
1890 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1891 if (msr & UART_MSR_CTS)
1892 break;
40b36daa
AW		 1893 udelay(1);
1894 touch_nmi_watchdog();
1895 }
1896 }
1897}
1898
f2d937f3
JW		 1899#ifdef CONFIG_CONSOLE_POLL
1900/*
1901 * Console polling routines for writing and reading from the uart while
1902 * in an interrupt or debug context.
1903 */
1904
1905static int serial8250_get_poll_char(struct uart_port *port)
1906{
49d5741b
JI		 1907 struct uart_8250_port *up =
1908 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1909 unsigned char lsr = serial_inp(up, UART_LSR);
1910
f5316b4a
JW		 1911 if (!(lsr & UART_LSR_DR))
1912 return NO_POLL_CHAR;
f2d937f3
JW		 1913
1914 return serial_inp(up, UART_RX);
1915}
1916
1917
1918static void serial8250_put_poll_char(struct uart_port *port,
1919 unsigned char c)
1920{
1921 unsigned int ier;
49d5741b
JI		 1922 struct uart_8250_port *up =
1923 container_of(port, struct uart_8250_port, port);
f2d937f3
JW		 1924
1925 /*
1926 * First save the IER then disable the interrupts
1927 */
1928 ier = serial_in(up, UART_IER);
1929 if (up->capabilities & UART_CAP_UUE)
1930 serial_out(up, UART_IER, UART_IER_UUE);
1931 else
1932 serial_out(up, UART_IER, 0);
1933
1934 wait_for_xmitr(up, BOTH_EMPTY);
1935 /*
1936 * Send the character out.
1937 * If a LF, also do CR...
1938 */
1939 serial_out(up, UART_TX, c);
1940 if (c == 10) {
1941 wait_for_xmitr(up, BOTH_EMPTY);
1942 serial_out(up, UART_TX, 13);
1943 }
1944
1945 /*
1946 * Finally, wait for transmitter to become empty
1947 * and restore the IER
1948 */
1949 wait_for_xmitr(up, BOTH_EMPTY);
1950 serial_out(up, UART_IER, ier);
1951}
1952
1953#endif /* CONFIG_CONSOLE_POLL */
1954
1da177e4
LT		 1955static int serial8250_startup(struct uart_port *port)
1956{
49d5741b
JI		 1957 struct uart_8250_port *up =
1958 container_of(port, struct uart_8250_port, port);
1da177e4 1959 unsigned long flags;
55d3b282 1960 unsigned char lsr, iir;
1da177e4
LT		 1961 int retval;
1962
e4f05af1
OP		 1963 up->port.fifosize = uart_config[up->port.type].fifo_size;
1964 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1da177e4
LT		 1965 up->capabilities = uart_config[up->port.type].flags;
1966 up->mcr = 0;
1967
b8e7e40a
AC		 1968 if (up->port.iotype != up->cur_iotype)
1969 set_io_from_upio(port);
1970
1da177e4
LT		 1971 if (up->port.type == PORT_16C950) {
1972 /* Wake up and initialize UART */
1973 up->acr = 0;
662b083a 1974 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 1975 serial_outp(up, UART_EFR, UART_EFR_ECB);
1976 serial_outp(up, UART_IER, 0);
1977 serial_outp(up, UART_LCR, 0);
1978 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
7d73aaf1 1979 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 1980 serial_outp(up, UART_EFR, UART_EFR_ECB);
1981 serial_outp(up, UART_LCR, 0);
1982 }
1983
1984#ifdef CONFIG_SERIAL_8250_RSA
1985 /*
1986 * If this is an RSA port, see if we can kick it up to the
1987 * higher speed clock.
1988 */
1989 enable_rsa(up);
1990#endif
1991
1992 /*
1993 * Clear the FIFO buffers and disable them.
7f927fcc 1994 * (they will be reenabled in set_termios())
1da177e4
LT		 1995 */
1996 serial8250_clear_fifos(up);
1997
1998 /*
1999 * Clear the interrupt registers.
2000 */
2001 (void) serial_inp(up, UART_LSR);
2002 (void) serial_inp(up, UART_RX);
2003 (void) serial_inp(up, UART_IIR);
2004 (void) serial_inp(up, UART_MSR);
2005
2006 /*
2007 * At this point, there's no way the LSR could still be 0xff;
2008 * if it is, then bail out, because there's likely no UART
2009 * here.
2010 */
2011 if (!(up->port.flags & UPF_BUGGY_UART) &&
2012 (serial_inp(up, UART_LSR) == 0xff)) {
7808a4c4
KRW		 2013 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2014 serial_index(&up->port));
1da177e4
LT		 2015 return -ENODEV;
2016 }
2017
2018 /*
2019 * For a XR16C850, we need to set the trigger levels
2020 */
2021 if (up->port.type == PORT_16850) {
2022 unsigned char fctr;
2023
662b083a 2024 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1da177e4
LT		 2025
2026 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2027 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2028 serial_outp(up, UART_TRG, UART_TRG_96);
2029 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2030 serial_outp(up, UART_TRG, UART_TRG_96);
2031
2032 serial_outp(up, UART_LCR, 0);
2033 }
2034
40b36daa 2035 if (is_real_interrupt(up->port.irq)) {
01c194d9 2036 unsigned char iir1;
40b36daa
AW		 2037 /*
2038 * Test for UARTs that do not reassert THRE when the
2039 * transmitter is idle and the interrupt has already
2040 * been cleared. Real 16550s should always reassert
2041 * this interrupt whenever the transmitter is idle and
2042 * the interrupt is enabled. Delays are necessary to
2043 * allow register changes to become visible.
2044 */
c389d27b 2045 spin_lock_irqsave(&up->port.lock, flags);
1c2f0493 2046 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2047 disable_irq_nosync(up->port.irq);
40b36daa
AW		 2048
2049 wait_for_xmitr(up, UART_LSR_THRE);
2050 serial_out_sync(up, UART_IER, UART_IER_THRI);
2051 udelay(1); /* allow THRE to set */
01c194d9 2052 iir1 = serial_in(up, UART_IIR);
40b36daa
AW		 2053 serial_out(up, UART_IER, 0);
2054 serial_out_sync(up, UART_IER, UART_IER_THRI);
2055 udelay(1); /* allow a working UART time to re-assert THRE */
2056 iir = serial_in(up, UART_IIR);
2057 serial_out(up, UART_IER, 0);
2058
1c2f0493 2059 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2060 enable_irq(up->port.irq);
c389d27b 2061 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa
AW		 2062
2063 /*
2064 * If the interrupt is not reasserted, setup a timer to
2065 * kick the UART on a regular basis.
2066 */
01c194d9 2067 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
363f66fe 2068 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2069 pr_debug("ttyS%d - using backup timer\n",
2070 serial_index(port));
40b36daa
AW		 2071 }
2072 }
2073
363f66fe
WN		 2074 /*
2075 * The above check will only give an accurate result the first time
2076 * the port is opened so this value needs to be preserved.
2077 */
2078 if (up->bugs & UART_BUG_THRE) {
2079 up->timer.function = serial8250_backup_timeout;
2080 up->timer.data = (unsigned long)up;
2081 mod_timer(&up->timer, jiffies +
54381067 2082 uart_poll_timeout(port) + HZ / 5);
363f66fe
WN		 2083 }
2084
1da177e4
LT		 2085 /*
2086 * If the "interrupt" for this port doesn't correspond with any
2087 * hardware interrupt, we use a timer-based system. The original
2088 * driver used to do this with IRQ0.
2089 */
2090 if (!is_real_interrupt(up->port.irq)) {
1da177e4 2091 up->timer.data = (unsigned long)up;
54381067 2092 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
1da177e4
LT		 2093 } else {
2094 retval = serial_link_irq_chain(up);
2095 if (retval)
2096 return retval;
2097 }
2098
2099 /*
2100 * Now, initialize the UART
2101 */
2102 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2103
2104 spin_lock_irqsave(&up->port.lock, flags);
2105 if (up->port.flags & UPF_FOURPORT) {
2106 if (!is_real_interrupt(up->port.irq))
2107 up->port.mctrl |= TIOCM_OUT1;
2108 } else
2109 /*
2110 * Most PC uarts need OUT2 raised to enable interrupts.
2111 */
2112 if (is_real_interrupt(up->port.irq))
2113 up->port.mctrl |= TIOCM_OUT2;
2114
2115 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282 2116
b6adea33
MCC		 2117 /* Serial over Lan (SoL) hack:
2118 Intel 8257x Gigabit ethernet chips have a
2119 16550 emulation, to be used for Serial Over Lan.
2120 Those chips take a longer time than a normal
2121 serial device to signalize that a transmission
2122 data was queued. Due to that, the above test generally
2123 fails. One solution would be to delay the reading of
2124 iir. However, this is not reliable, since the timeout
2125 is variable. So, let's just don't test if we receive
2126 TX irq. This way, we'll never enable UART_BUG_TXEN.
2127 */
d41a4b51 2128 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2129 goto dont_test_tx_en;
2130
55d3b282
RK		 2131 /*
2132 * Do a quick test to see if we receive an
2133 * interrupt when we enable the TX irq.
2134 */
2135 serial_outp(up, UART_IER, UART_IER_THRI);
2136 lsr = serial_in(up, UART_LSR);
2137 iir = serial_in(up, UART_IIR);
2138 serial_outp(up, UART_IER, 0);
2139
2140 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2141 if (!(up->bugs & UART_BUG_TXEN)) {
2142 up->bugs |= UART_BUG_TXEN;
55d3b282 2143 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2144 serial_index(port));
55d3b282
RK		 2145 }
2146 } else {
67f7654e 2147 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2148 }
2149
b6adea33 2150dont_test_tx_en:
1da177e4
LT		 2151 spin_unlock_irqrestore(&up->port.lock, flags);
2152
ad4c2aa6
CM		 2153 /*
2154 * Clear the interrupt registers again for luck, and clear the
2155 * saved flags to avoid getting false values from polling
2156 * routines or the previous session.
2157 */
2158 serial_inp(up, UART_LSR);
2159 serial_inp(up, UART_RX);
2160 serial_inp(up, UART_IIR);
2161 serial_inp(up, UART_MSR);
2162 up->lsr_saved_flags = 0;
2163 up->msr_saved_flags = 0;
2164
1da177e4
LT		 2165 /*
2166 * Finally, enable interrupts. Note: Modem status interrupts
2167 * are set via set_termios(), which will be occurring imminently
2168 * anyway, so we don't enable them here.
2169 */
2170 up->ier = UART_IER_RLSI | UART_IER_RDI;
2171 serial_outp(up, UART_IER, up->ier);
2172
2173 if (up->port.flags & UPF_FOURPORT) {
2174 unsigned int icp;
2175 /*
2176 * Enable interrupts on the AST Fourport board
2177 */
2178 icp = (up->port.iobase & 0xfe0) | 0x01f;
2179 outb_p(0x80, icp);
2180 (void) inb_p(icp);
2181 }
2182
1da177e4
LT		 2183 return 0;
2184}
2185
2186static void serial8250_shutdown(struct uart_port *port)
2187{
49d5741b
JI		 2188 struct uart_8250_port *up =
2189 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2190 unsigned long flags;
2191
2192 /*
2193 * Disable interrupts from this port
2194 */
2195 up->ier = 0;
2196 serial_outp(up, UART_IER, 0);
2197
2198 spin_lock_irqsave(&up->port.lock, flags);
2199 if (up->port.flags & UPF_FOURPORT) {
2200 /* reset interrupts on the AST Fourport board */
2201 inb((up->port.iobase & 0xfe0) | 0x1f);
2202 up->port.mctrl |= TIOCM_OUT1;
2203 } else
2204 up->port.mctrl &= ~TIOCM_OUT2;
2205
2206 serial8250_set_mctrl(&up->port, up->port.mctrl);
2207 spin_unlock_irqrestore(&up->port.lock, flags);
2208
2209 /*
2210 * Disable break condition and FIFOs
2211 */
2212 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2213 serial8250_clear_fifos(up);
2214
2215#ifdef CONFIG_SERIAL_8250_RSA
2216 /*
2217 * Reset the RSA board back to 115kbps compat mode.
2218 */
2219 disable_rsa(up);
2220#endif
2221
2222 /*
2223 * Read data port to reset things, and then unlink from
2224 * the IRQ chain.
2225 */
2226 (void) serial_in(up, UART_RX);
2227
40b36daa
AW		 2228 del_timer_sync(&up->timer);
2229 up->timer.function = serial8250_timeout;
2230 if (is_real_interrupt(up->port.irq))
1da177e4
LT		 2231 serial_unlink_irq_chain(up);
2232}
2233
2234static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2235{
2236 unsigned int quot;
2237
2238 /*
2239 * Handle magic divisors for baud rates above baud_base on
2240 * SMSC SuperIO chips.
2241 */
2242 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2243 baud == (port->uartclk/4))
2244 quot = 0x8001;
2245 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2246 baud == (port->uartclk/8))
2247 quot = 0x8002;
2248 else
2249 quot = uart_get_divisor(port, baud);
2250
2251 return quot;
2252}
2253
235dae5d
PL		 2254void
2255serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2256 struct ktermios *old)
1da177e4 2257{
49d5741b
JI		 2258 struct uart_8250_port *up =
2259 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2260 unsigned char cval, fcr = 0;
2261 unsigned long flags;
2262 unsigned int baud, quot;
2263
2264 switch (termios->c_cflag & CSIZE) {
2265 case CS5:
0a8b80c5 2266 cval = UART_LCR_WLEN5;
1da177e4
LT		 2267 break;
2268 case CS6:
0a8b80c5 2269 cval = UART_LCR_WLEN6;
1da177e4
LT		 2270 break;
2271 case CS7:
0a8b80c5 2272 cval = UART_LCR_WLEN7;
1da177e4
LT		 2273 break;
2274 default:
2275 case CS8:
0a8b80c5 2276 cval = UART_LCR_WLEN8;
1da177e4
LT		 2277 break;
2278 }
2279
2280 if (termios->c_cflag & CSTOPB)
0a8b80c5 2281 cval |= UART_LCR_STOP;
1da177e4
LT		 2282 if (termios->c_cflag & PARENB)
2283 cval |= UART_LCR_PARITY;
2284 if (!(termios->c_cflag & PARODD))
2285 cval |= UART_LCR_EPAR;
2286#ifdef CMSPAR
2287 if (termios->c_cflag & CMSPAR)
2288 cval |= UART_LCR_SPAR;
2289#endif
2290
2291 /*
2292 * Ask the core to calculate the divisor for us.
2293 */
24d481ec
AV		 2294 baud = uart_get_baud_rate(port, termios, old,
2295 port->uartclk / 16 / 0xffff,
2296 port->uartclk / 16);
1da177e4
LT		 2297 quot = serial8250_get_divisor(port, baud);
2298
2299 /*
4ba5e35d 2300 * Oxford Semi 952 rev B workaround
1da177e4 2301 */
4ba5e35d 2302 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2303 quot++;
1da177e4
LT		 2304
2305 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2306 if (baud < 2400)
2307 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2308 else
2309 fcr = uart_config[up->port.type].fcr;
2310 }
2311
2312 /*
2313 * MCR-based auto flow control. When AFE is enabled, RTS will be
2314 * deasserted when the receive FIFO contains more characters than
2315 * the trigger, or the MCR RTS bit is cleared. In the case where
2316 * the remote UART is not using CTS auto flow control, we must
2317 * have sufficient FIFO entries for the latency of the remote
2318 * UART to respond. IOW, at least 32 bytes of FIFO.
2319 */
2320 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2321 up->mcr &= ~UART_MCR_AFE;
2322 if (termios->c_cflag & CRTSCTS)
2323 up->mcr |= UART_MCR_AFE;
2324 }
2325
2326 /*
2327 * Ok, we're now changing the port state. Do it with
2328 * interrupts disabled.
2329 */
2330 spin_lock_irqsave(&up->port.lock, flags);
2331
2332 /*
2333 * Update the per-port timeout.
2334 */
2335 uart_update_timeout(port, termios->c_cflag, baud);
2336
2337 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2338 if (termios->c_iflag & INPCK)
2339 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2340 if (termios->c_iflag & (BRKINT | PARMRK))
2341 up->port.read_status_mask |= UART_LSR_BI;
2342
2343 /*
2344 * Characteres to ignore
2345 */
2346 up->port.ignore_status_mask = 0;
2347 if (termios->c_iflag & IGNPAR)
2348 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2349 if (termios->c_iflag & IGNBRK) {
2350 up->port.ignore_status_mask |= UART_LSR_BI;
2351 /*
2352 * If we're ignoring parity and break indicators,
2353 * ignore overruns too (for real raw support).
2354 */
2355 if (termios->c_iflag & IGNPAR)
2356 up->port.ignore_status_mask |= UART_LSR_OE;
2357 }
2358
2359 /*
2360 * ignore all characters if CREAD is not set
2361 */
2362 if ((termios->c_cflag & CREAD) == 0)
2363 up->port.ignore_status_mask |= UART_LSR_DR;
2364
2365 /*
2366 * CTS flow control flag and modem status interrupts
2367 */
f8b372a1 2368 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2369 if (!(up->bugs & UART_BUG_NOMSR) &&
2370 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2371 up->ier |= UART_IER_MSI;
2372 if (up->capabilities & UART_CAP_UUE)
4539c24f
SW		 2373 up->ier |= UART_IER_UUE;
2374 if (up->capabilities & UART_CAP_RTOIE)
2375 up->ier |= UART_IER_RTOIE;
1da177e4
LT		 2376
2377 serial_out(up, UART_IER, up->ier);
2378
2379 if (up->capabilities & UART_CAP_EFR) {
2380 unsigned char efr = 0;
2381 /*
2382 * TI16C752/Startech hardware flow control. FIXME:
2383 * - TI16C752 requires control thresholds to be set.
2384 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2385 */
2386 if (termios->c_cflag & CRTSCTS)
2387 efr |= UART_EFR_CTS;
2388
662b083a 2389 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
06315348
SH		 2390 if (up->port.flags & UPF_EXAR_EFR)
2391 serial_outp(up, UART_XR_EFR, efr);
2392 else
2393 serial_outp(up, UART_EFR, efr);
1da177e4
LT		 2394 }
2395
f2eda27d 2396#ifdef CONFIG_ARCH_OMAP
255341c6 2397 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
5668545a 2398 if (cpu_is_omap1510() && is_omap_port(up)) {
255341c6
JM		 2399 if (baud == 115200) {
2400 quot = 1;
2401 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2402 } else
2403 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2404 }
2405#endif
2406
1da177e4
LT		 2407 if (up->capabilities & UART_NATSEMI) {
2408 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2409 serial_outp(up, UART_LCR, 0xe0);
2410 } else {
2411 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2412 }
2413
b32b19b8 2414 serial_dl_write(up, quot);
1da177e4
LT		 2415
2416 /*
2417 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2418 * is written without DLAB set, this mode will be disabled.
2419 */
2420 if (up->port.type == PORT_16750)
2421 serial_outp(up, UART_FCR, fcr);
2422
2423 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2424 up->lcr = cval; /* Save LCR */
2425 if (up->port.type != PORT_16750) {
2426 if (fcr & UART_FCR_ENABLE_FIFO) {
2427 /* emulated UARTs (Lucent Venus 167x) need two steps */
2428 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2429 }
2430 serial_outp(up, UART_FCR, fcr); /* set fcr */
2431 }
2432 serial8250_set_mctrl(&up->port, up->port.mctrl);
2433 spin_unlock_irqrestore(&up->port.lock, flags);
e991a2bd
AC		 2434 /* Don't rewrite B0 */
2435 if (tty_termios_baud_rate(termios))
2436 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4 2437}
235dae5d
PL		 2438EXPORT_SYMBOL(serial8250_do_set_termios);
2439
2440static void
2441serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2442 struct ktermios *old)
2443{
2444 if (port->set_termios)
2445 port->set_termios(port, termios, old);
2446 else
2447 serial8250_do_set_termios(port, termios, old);
2448}
1da177e4 2449
dc77f161 2450static void
a0821df6 2451serial8250_set_ldisc(struct uart_port *port, int new)
dc77f161 2452{
a0821df6 2453 if (new == N_PPS) {
dc77f161
RG		 2454 port->flags |= UPF_HARDPPS_CD;
2455 serial8250_enable_ms(port);
2456 } else
2457 port->flags &= ~UPF_HARDPPS_CD;
2458}
2459
c161afe9
ML		 2460
2461void serial8250_do_pm(struct uart_port *port, unsigned int state,
2462 unsigned int oldstate)
1da177e4 2463{
49d5741b
JI		 2464 struct uart_8250_port *p =
2465 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2466
2467 serial8250_set_sleep(p, state != 0);
c161afe9
ML		 2468}
2469EXPORT_SYMBOL(serial8250_do_pm);
1da177e4 2470
c161afe9
ML		 2471static void
2472serial8250_pm(struct uart_port *port, unsigned int state,
2473 unsigned int oldstate)
2474{
2475 if (port->pm)
2476 port->pm(port, state, oldstate);
2477 else
2478 serial8250_do_pm(port, state, oldstate);
1da177e4
LT		 2479}
2480
f2eda27d
RK		 2481static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2482{
2483 if (pt->port.iotype == UPIO_AU)
b2b13cdf 2484 return 0x1000;
f2eda27d
RK		 2485#ifdef CONFIG_ARCH_OMAP
2486 if (is_omap_port(pt))
2487 return 0x16 << pt->port.regshift;
2488#endif
2489 return 8 << pt->port.regshift;
2490}
2491
1da177e4
LT		 2492/*
2493 * Resource handling.
2494 */
2495static int serial8250_request_std_resource(struct uart_8250_port *up)
2496{
f2eda27d 2497 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2498 int ret = 0;
2499
2500 switch (up->port.iotype) {
85835f44 2501 case UPIO_AU:
0b30d668
SS		 2502 case UPIO_TSI:
2503 case UPIO_MEM32:
1da177e4
LT		 2504 case UPIO_MEM:
2505 if (!up->port.mapbase)
2506 break;
2507
2508 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2509 ret = -EBUSY;
2510 break;
2511 }
2512
2513 if (up->port.flags & UPF_IOREMAP) {
6f441fe9
AC		 2514 up->port.membase = ioremap_nocache(up->port.mapbase,
2515 size);
1da177e4
LT		 2516 if (!up->port.membase) {
2517 release_mem_region(up->port.mapbase, size);
2518 ret = -ENOMEM;
2519 }
2520 }
2521 break;
2522
2523 case UPIO_HUB6:
2524 case UPIO_PORT:
2525 if (!request_region(up->port.iobase, size, "serial"))
2526 ret = -EBUSY;
2527 break;
2528 }
2529 return ret;
2530}
2531
2532static void serial8250_release_std_resource(struct uart_8250_port *up)
2533{
f2eda27d 2534 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2535
2536 switch (up->port.iotype) {
85835f44 2537 case UPIO_AU:
0b30d668
SS		 2538 case UPIO_TSI:
2539 case UPIO_MEM32:
1da177e4
LT		 2540 case UPIO_MEM:
2541 if (!up->port.mapbase)
2542 break;
2543
2544 if (up->port.flags & UPF_IOREMAP) {
2545 iounmap(up->port.membase);
2546 up->port.membase = NULL;
2547 }
2548
2549 release_mem_region(up->port.mapbase, size);
2550 break;
2551
2552 case UPIO_HUB6:
2553 case UPIO_PORT:
2554 release_region(up->port.iobase, size);
2555 break;
2556 }
2557}
2558
2559static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2560{
2561 unsigned long start = UART_RSA_BASE << up->port.regshift;
2562 unsigned int size = 8 << up->port.regshift;
0b30d668 2563 int ret = -EINVAL;
1da177e4
LT		 2564
2565 switch (up->port.iotype) {
1da177e4
LT		 2566 case UPIO_HUB6:
2567 case UPIO_PORT:
2568 start += up->port.iobase;
0b30d668
SS		 2569 if (request_region(start, size, "serial-rsa"))
2570 ret = 0;
2571 else
1da177e4
LT		 2572 ret = -EBUSY;
2573 break;
2574 }
2575
2576 return ret;
2577}
2578
2579static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2580{
2581 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2582 unsigned int size = 8 << up->port.regshift;
2583
2584 switch (up->port.iotype) {
1da177e4
LT		 2585 case UPIO_HUB6:
2586 case UPIO_PORT:
2587 release_region(up->port.iobase + offset, size);
2588 break;
2589 }
2590}
2591
2592static void serial8250_release_port(struct uart_port *port)
2593{
49d5741b
JI		 2594 struct uart_8250_port *up =
2595 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2596
2597 serial8250_release_std_resource(up);
2598 if (up->port.type == PORT_RSA)
2599 serial8250_release_rsa_resource(up);
2600}
2601
2602static int serial8250_request_port(struct uart_port *port)
2603{
49d5741b
JI		 2604 struct uart_8250_port *up =
2605 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2606 int ret = 0;
2607
2608 ret = serial8250_request_std_resource(up);
2609 if (ret == 0 && up->port.type == PORT_RSA) {
2610 ret = serial8250_request_rsa_resource(up);
2611 if (ret < 0)
2612 serial8250_release_std_resource(up);
2613 }
2614
2615 return ret;
2616}
2617
2618static void serial8250_config_port(struct uart_port *port, int flags)
2619{
49d5741b
JI		 2620 struct uart_8250_port *up =
2621 container_of(port, struct uart_8250_port, port);
1da177e4
LT		 2622 int probeflags = PROBE_ANY;
2623 int ret;
2624
1da177e4
LT		 2625 /*
2626 * Find the region that we can probe for. This in turn
2627 * tells us whether we can probe for the type of port.
2628 */
2629 ret = serial8250_request_std_resource(up);
2630 if (ret < 0)
2631 return;
2632
2633 ret = serial8250_request_rsa_resource(up);
2634 if (ret < 0)
2635 probeflags &= ~PROBE_RSA;
2636
b8e7e40a
AC		 2637 if (up->port.iotype != up->cur_iotype)
2638 set_io_from_upio(port);
2639
1da177e4
LT		 2640 if (flags & UART_CONFIG_TYPE)
2641 autoconfig(up, probeflags);
b2b13cdf 2642
b2b13cdf
ML		 2643 /* if access method is AU, it is a 16550 with a quirk */
2644 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2645 up->bugs |= UART_BUG_NOMSR;
b2b13cdf 2646
1da177e4
LT		 2647 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2648 autoconfig_irq(up);
2649
2650 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2651 serial8250_release_rsa_resource(up);
2652 if (up->port.type == PORT_UNKNOWN)
2653 serial8250_release_std_resource(up);
2654}
2655
2656static int
2657serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2658{
a62c4133 2659 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2660 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2661 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2662 ser->type == PORT_STARTECH)
2663 return -EINVAL;
2664 return 0;
2665}
2666
2667static const char *
2668serial8250_type(struct uart_port *port)
2669{
2670 int type = port->type;
2671
2672 if (type >= ARRAY_SIZE(uart_config))
2673 type = 0;
2674 return uart_config[type].name;
2675}
2676
2677static struct uart_ops serial8250_pops = {
2678 .tx_empty = serial8250_tx_empty,
2679 .set_mctrl = serial8250_set_mctrl,
2680 .get_mctrl = serial8250_get_mctrl,
2681 .stop_tx = serial8250_stop_tx,
2682 .start_tx = serial8250_start_tx,
2683 .stop_rx = serial8250_stop_rx,
2684 .enable_ms = serial8250_enable_ms,
2685 .break_ctl = serial8250_break_ctl,
2686 .startup = serial8250_startup,
2687 .shutdown = serial8250_shutdown,
2688 .set_termios = serial8250_set_termios,
dc77f161 2689 .set_ldisc = serial8250_set_ldisc,
1da177e4
LT		 2690 .pm = serial8250_pm,
2691 .type = serial8250_type,
2692 .release_port = serial8250_release_port,
2693 .request_port = serial8250_request_port,
2694 .config_port = serial8250_config_port,
2695 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2696#ifdef CONFIG_CONSOLE_POLL
2697 .poll_get_char = serial8250_get_poll_char,
2698 .poll_put_char = serial8250_put_poll_char,
2699#endif
1da177e4
LT		 2700};
2701
2702static struct uart_8250_port serial8250_ports[UART_NR];
2703
af7f3743
AC		 2704static void (*serial8250_isa_config)(int port, struct uart_port *up,
2705 unsigned short *capabilities);
2706
2707void serial8250_set_isa_configurator(
2708 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2709{
2710 serial8250_isa_config = v;
2711}
2712EXPORT_SYMBOL(serial8250_set_isa_configurator);
2713
1da177e4
LT		 2714static void __init serial8250_isa_init_ports(void)
2715{
2716 struct uart_8250_port *up;
2717 static int first = 1;
4c0ebb80 2718 int i, irqflag = 0;
1da177e4
LT		 2719
2720 if (!first)
2721 return;
2722 first = 0;
2723
a61c2d78 2724 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2725 struct uart_8250_port *up = &serial8250_ports[i];
2726
2727 up->port.line = i;
2728 spin_lock_init(&up->port.lock);
2729
2730 init_timer(&up->timer);
2731 up->timer.function = serial8250_timeout;
2732
2733 /*
2734 * ALPHA_KLUDGE_MCR needs to be killed.
2735 */
2736 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2737 up->mcr_force = ALPHA_KLUDGE_MCR;
2738
2739 up->port.ops = &serial8250_pops;
2740 }
2741
4c0ebb80
AGR		 2742 if (share_irqs)
2743 irqflag = IRQF_SHARED;
2744
44454bcd 2745 for (i = 0, up = serial8250_ports;
a61c2d78 2746 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2747 i++, up++) {
2748 up->port.iobase = old_serial_port[i].port;
2749 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
1c2f0493 2750 up->port.irqflags = old_serial_port[i].irqflags;
1da177e4
LT		 2751 up->port.uartclk = old_serial_port[i].baud_base * 16;
2752 up->port.flags = old_serial_port[i].flags;
2753 up->port.hub6 = old_serial_port[i].hub6;
2754 up->port.membase = old_serial_port[i].iomem_base;
2755 up->port.iotype = old_serial_port[i].io_type;
2756 up->port.regshift = old_serial_port[i].iomem_reg_shift;
7d6a07d1 2757 set_io_from_upio(&up->port);
4c0ebb80 2758 up->port.irqflags |= irqflag;
af7f3743
AC		 2759 if (serial8250_isa_config != NULL)
2760 serial8250_isa_config(i, &up->port, &up->capabilities);
2761
1da177e4
LT		 2762 }
2763}
2764
b5d228cc
SL		 2765static void
2766serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2767{
2768 up->port.type = type;
2769 up->port.fifosize = uart_config[type].fifo_size;
2770 up->capabilities = uart_config[type].flags;
2771 up->tx_loadsz = uart_config[type].tx_loadsz;
2772}
2773
1da177e4
LT		 2774static void __init
2775serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2776{
2777 int i;
2778
b8e7e40a
AC		 2779 for (i = 0; i < nr_uarts; i++) {
2780 struct uart_8250_port *up = &serial8250_ports[i];
2781 up->cur_iotype = 0xFF;
2782 }
2783
1da177e4
LT		 2784 serial8250_isa_init_ports();
2785
a61c2d78 2786 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2787 struct uart_8250_port *up = &serial8250_ports[i];
2788
2789 up->port.dev = dev;
b5d228cc
SL		 2790
2791 if (up->port.flags & UPF_FIXED_TYPE)
2792 serial8250_init_fixed_type_port(up, up->port.type);
2793
1da177e4
LT		 2794 uart_add_one_port(drv, &up->port);
2795 }
2796}
2797
2798#ifdef CONFIG_SERIAL_8250_CONSOLE
2799
d358788f
RK		 2800static void serial8250_console_putchar(struct uart_port *port, int ch)
2801{
49d5741b
JI		 2802 struct uart_8250_port *up =
2803 container_of(port, struct uart_8250_port, port);
d358788f
RK		 2804
2805 wait_for_xmitr(up, UART_LSR_THRE);
2806 serial_out(up, UART_TX, ch);
2807}
2808
1da177e4
LT		 2809/*
2810 * Print a string to the serial port trying not to disturb
2811 * any possible real use of the port...
2812 *
2813 * The console_lock must be held when we get here.
2814 */
2815static void
2816serial8250_console_write(struct console *co, const char *s, unsigned int count)
2817{
2818 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2819 unsigned long flags;
1da177e4 2820 unsigned int ier;
d8a5a8d7 2821 int locked = 1;
1da177e4 2822
78512ece
AM		 2823 touch_nmi_watchdog();
2824
68aa2c0d
AM		 2825 local_irq_save(flags);
2826 if (up->port.sysrq) {
2827 /* serial8250_handle_port() already took the lock */
2828 locked = 0;
2829 } else if (oops_in_progress) {
2830 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2831 } else
68aa2c0d 2832 spin_lock(&up->port.lock);
d8a5a8d7 2833
1da177e4 2834 /*
dc7bf130 2835 * First save the IER then disable the interrupts
1da177e4
LT		 2836 */
2837 ier = serial_in(up, UART_IER);
2838
2839 if (up->capabilities & UART_CAP_UUE)
2840 serial_out(up, UART_IER, UART_IER_UUE);
2841 else
2842 serial_out(up, UART_IER, 0);
2843
d358788f 2844 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2845
2846 /*
2847 * Finally, wait for transmitter to become empty
2848 * and restore the IER
2849 */
f91a3715 2850 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2851 serial_out(up, UART_IER, ier);
d8a5a8d7 2852
ad4c2aa6
CM		 2853 /*
2854 * The receive handling will happen properly because the
2855 * receive ready bit will still be set; it is not cleared
2856 * on read. However, modem control will not, we must
2857 * call it if we have saved something in the saved flags
2858 * while processing with interrupts off.
2859 */
2860 if (up->msr_saved_flags)
2861 check_modem_status(up);
2862
d8a5a8d7 2863 if (locked)
68aa2c0d
AM		 2864 spin_unlock(&up->port.lock);
2865 local_irq_restore(flags);
1da177e4
LT		 2866}
2867
118c0ace 2868static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2869{
2870 struct uart_port *port;
2871 int baud = 9600;
2872 int bits = 8;
2873 int parity = 'n';
2874 int flow = 'n';
2875
2876 /*
2877 * Check whether an invalid uart number has been specified, and
2878 * if so, search for the first available port that does have
2879 * console support.
2880 */
a61c2d78 2881 if (co->index >= nr_uarts)
1da177e4
LT		 2882 co->index = 0;
2883 port = &serial8250_ports[co->index].port;
2884 if (!port->iobase && !port->membase)
2885 return -ENODEV;
2886
2887 if (options)
2888 uart_parse_options(options, &baud, &parity, &bits, &flow);
2889
2890 return uart_set_options(port, co, baud, parity, bits, flow);
2891}
2892
b6b1d877 2893static int serial8250_console_early_setup(void)
18a8bd94
YL		 2894{
2895 return serial8250_find_port_for_earlycon();
2896}
2897
1da177e4
LT		 2898static struct console serial8250_console = {
2899 .name = "ttyS",
2900 .write = serial8250_console_write,
2901 .device = uart_console_device,
2902 .setup = serial8250_console_setup,
18a8bd94 2903 .early_setup = serial8250_console_early_setup,
a80c49db 2904 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1da177e4
LT		 2905 .index = -1,
2906 .data = &serial8250_reg,
2907};
2908
2909static int __init serial8250_console_init(void)
2910{
05d81d22
EB		 2911 if (nr_uarts > UART_NR)
2912 nr_uarts = UART_NR;
2913
1da177e4
LT		 2914 serial8250_isa_init_ports();
2915 register_console(&serial8250_console);
2916 return 0;
2917}
2918console_initcall(serial8250_console_init);
2919
18a8bd94 2920int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2921{
2922 int line;
2923 struct uart_port *port;
2924
a61c2d78 2925 for (line = 0; line < nr_uarts; line++) {
1da177e4 2926 port = &serial8250_ports[line].port;
50aec3b5 2927 if (uart_match_port(p, port))
1da177e4
LT		 2928 return line;
2929 }
2930 return -ENODEV;
2931}
2932
1da177e4
LT		 2933#define SERIAL8250_CONSOLE &serial8250_console
2934#else
2935#define SERIAL8250_CONSOLE NULL
2936#endif
2937
2938static struct uart_driver serial8250_reg = {
2939 .owner = THIS_MODULE,
2940 .driver_name = "serial",
1da177e4
LT		 2941 .dev_name = "ttyS",
2942 .major = TTY_MAJOR,
2943 .minor = 64,
1da177e4
LT		 2944 .cons = SERIAL8250_CONSOLE,
2945};
2946
d856c666
RK		 2947/*
2948 * early_serial_setup - early registration for 8250 ports
2949 *
2950 * Setup an 8250 port structure prior to console initialisation. Use
2951 * after console initialisation will cause undefined behaviour.
2952 */
1da177e4
LT		 2953int __init early_serial_setup(struct uart_port *port)
2954{
b430428a
DD		 2955 struct uart_port *p;
2956
1da177e4
LT		 2957 if (port->line >= ARRAY_SIZE(serial8250_ports))
2958 return -ENODEV;
2959
2960 serial8250_isa_init_ports();
b430428a
DD		 2961 p = &serial8250_ports[port->line].port;
2962 p->iobase = port->iobase;
2963 p->membase = port->membase;
2964 p->irq = port->irq;
1c2f0493 2965 p->irqflags = port->irqflags;
b430428a
DD		 2966 p->uartclk = port->uartclk;
2967 p->fifosize = port->fifosize;
2968 p->regshift = port->regshift;
2969 p->iotype = port->iotype;
2970 p->flags = port->flags;
2971 p->mapbase = port->mapbase;
2972 p->private_data = port->private_data;
125c97d8
HD		 2973 p->type = port->type;
2974 p->line = port->line;
7d6a07d1
DD		 2975
2976 set_io_from_upio(p);
2977 if (port->serial_in)
2978 p->serial_in = port->serial_in;
2979 if (port->serial_out)
2980 p->serial_out = port->serial_out;
583d28e9
JI		 2981 if (port->handle_irq)
2982 p->handle_irq = port->handle_irq;
2983 else
2984 p->handle_irq = serial8250_default_handle_irq;
7d6a07d1 2985
1da177e4
LT		 2986 return 0;
2987}
2988
2989/**
2990 * serial8250_suspend_port - suspend one serial port
2991 * @line: serial line number
1da177e4
LT		 2992 *
2993 * Suspend one serial port.
2994 */
2995void serial8250_suspend_port(int line)
2996{
2997 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2998}
2999
3000/**
3001 * serial8250_resume_port - resume one serial port
3002 * @line: serial line number
1da177e4
LT		 3003 *
3004 * Resume one serial port.
3005 */
3006void serial8250_resume_port(int line)
3007{
b5b82df6
DW		 3008 struct uart_8250_port *up = &serial8250_ports[line];
3009
3010 if (up->capabilities & UART_NATSEMI) {
b5b82df6
DW		 3011 /* Ensure it's still in high speed mode */
3012 serial_outp(up, UART_LCR, 0xE0);
3013
0d0389e5 3014 ns16550a_goto_highspeed(up);
b5b82df6
DW		 3015
3016 serial_outp(up, UART_LCR, 0);
95926d2d 3017 up->port.uartclk = 921600*16;
b5b82df6
DW		 3018 }
3019 uart_resume_port(&serial8250_reg, &up->port);
1da177e4
LT		 3020}
3021
3022/*
3023 * Register a set of serial devices attached to a platform device. The
3024 * list is terminated with a zero flags entry, which means we expect
3025 * all entries to have at least UPF_BOOT_AUTOCONF set.
3026 */
3ae5eaec 3027static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 3028{
3ae5eaec 3029 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 3030 struct uart_port port;
4c0ebb80 3031 int ret, i, irqflag = 0;
1da177e4
LT		 3032
3033 memset(&port, 0, sizeof(struct uart_port));
3034
4c0ebb80
AGR		 3035 if (share_irqs)
3036 irqflag = IRQF_SHARED;
3037
ec9f47cd 3038 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 3039 port.iobase = p->iobase;
3040 port.membase = p->membase;
3041 port.irq = p->irq;
1c2f0493 3042 port.irqflags = p->irqflags;
74a19741
WN		 3043 port.uartclk = p->uartclk;
3044 port.regshift = p->regshift;
3045 port.iotype = p->iotype;
3046 port.flags = p->flags;
3047 port.mapbase = p->mapbase;
3048 port.hub6 = p->hub6;
3049 port.private_data = p->private_data;
8e23fcc8 3050 port.type = p->type;
7d6a07d1
DD		 3051 port.serial_in = p->serial_in;
3052 port.serial_out = p->serial_out;
583d28e9 3053 port.handle_irq = p->handle_irq;
235dae5d 3054 port.set_termios = p->set_termios;
c161afe9 3055 port.pm = p->pm;
74a19741 3056 port.dev = &dev->dev;
4c0ebb80 3057 port.irqflags |= irqflag;
ec9f47cd
RK		 3058 ret = serial8250_register_port(&port);
3059 if (ret < 0) {
3ae5eaec 3060 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 3061 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3062 p->iobase, (unsigned long long)p->mapbase,
3063 p->irq, ret);
ec9f47cd 3064 }
1da177e4
LT		 3065 }
3066 return 0;
3067}
3068
3069/*
3070 * Remove serial ports registered against a platform device.
3071 */
3ae5eaec 3072static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 3073{
3074 int i;
3075
a61c2d78 3076 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 3077 struct uart_8250_port *up = &serial8250_ports[i];
3078
3ae5eaec 3079 if (up->port.dev == &dev->dev)
1da177e4
LT		 3080 serial8250_unregister_port(i);
3081 }
3082 return 0;
3083}
3084
3ae5eaec 3085static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 3086{
3087 int i;
3088
1da177e4
LT		 3089 for (i = 0; i < UART_NR; i++) {
3090 struct uart_8250_port *up = &serial8250_ports[i];
3091
3ae5eaec 3092 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3093 uart_suspend_port(&serial8250_reg, &up->port);
3094 }
3095
3096 return 0;
3097}
3098
3ae5eaec 3099static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3100{
3101 int i;
3102
1da177e4
LT		 3103 for (i = 0; i < UART_NR; i++) {
3104 struct uart_8250_port *up = &serial8250_ports[i];
3105
3ae5eaec 3106 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3107 serial8250_resume_port(i);
1da177e4
LT		 3108 }
3109
3110 return 0;
3111}
3112
3ae5eaec 3113static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 3114 .probe = serial8250_probe,
3115 .remove = __devexit_p(serial8250_remove),
3116 .suspend = serial8250_suspend,
3117 .resume = serial8250_resume,
3ae5eaec
RK		 3118 .driver = {
3119 .name = "serial8250",
7493a314 3120 .owner = THIS_MODULE,
3ae5eaec 3121 },
1da177e4
LT		 3122};
3123
3124/*
3125 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3126 * in the table in include/asm/serial.h
3127 */
3128static struct platform_device *serial8250_isa_devs;
3129
3130/*
3131 * serial8250_register_port and serial8250_unregister_port allows for
3132 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3133 * modems and PCI multiport cards.
3134 */
f392ecfa 3135static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3136
3137static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3138{
3139 int i;
3140
3141 /*
3142 * First, find a port entry which matches.
3143 */
a61c2d78 3144 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3145 if (uart_match_port(&serial8250_ports[i].port, port))
3146 return &serial8250_ports[i];
3147
3148 /*
3149 * We didn't find a matching entry, so look for the first
3150 * free entry. We look for one which hasn't been previously
3151 * used (indicated by zero iobase).
3152 */
a61c2d78 3153 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3154 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3155 serial8250_ports[i].port.iobase == 0)
3156 return &serial8250_ports[i];
3157
3158 /*
3159 * That also failed. Last resort is to find any entry which
3160 * doesn't have a real port associated with it.
3161 */
a61c2d78 3162 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3163 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3164 return &serial8250_ports[i];
3165
3166 return NULL;
3167}
3168
3169/**
3170 * serial8250_register_port - register a serial port
3171 * @port: serial port template
3172 *
3173 * Configure the serial port specified by the request. If the
3174 * port exists and is in use, it is hung up and unregistered
3175 * first.
3176 *
3177 * The port is then probed and if necessary the IRQ is autodetected
3178 * If this fails an error is returned.
3179 *
3180 * On success the port is ready to use and the line number is returned.
3181 */
3182int serial8250_register_port(struct uart_port *port)
3183{
3184 struct uart_8250_port *uart;
3185 int ret = -ENOSPC;
3186
3187 if (port->uartclk == 0)
3188 return -EINVAL;
3189
f392ecfa 3190 mutex_lock(&serial_mutex);
1da177e4
LT		 3191
3192 uart = serial8250_find_match_or_unused(port);
3193 if (uart) {
3194 uart_remove_one_port(&serial8250_reg, &uart->port);
3195
74a19741
WN		 3196 uart->port.iobase = port->iobase;
3197 uart->port.membase = port->membase;
3198 uart->port.irq = port->irq;
1c2f0493 3199 uart->port.irqflags = port->irqflags;
74a19741
WN		 3200 uart->port.uartclk = port->uartclk;
3201 uart->port.fifosize = port->fifosize;
3202 uart->port.regshift = port->regshift;
3203 uart->port.iotype = port->iotype;
3204 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3205 uart->port.mapbase = port->mapbase;
3206 uart->port.private_data = port->private_data;
1da177e4
LT		 3207 if (port->dev)
3208 uart->port.dev = port->dev;
8e23fcc8 3209
b5d228cc
SL		 3210 if (port->flags & UPF_FIXED_TYPE)
3211 serial8250_init_fixed_type_port(uart, port->type);
8e23fcc8 3212
7d6a07d1
DD		 3213 set_io_from_upio(&uart->port);
3214 /* Possibly override default I/O functions. */
3215 if (port->serial_in)
3216 uart->port.serial_in = port->serial_in;
3217 if (port->serial_out)
3218 uart->port.serial_out = port->serial_out;
583d28e9
JI		 3219 if (port->handle_irq)
3220 uart->port.handle_irq = port->handle_irq;
235dae5d
PL		 3221 /* Possibly override set_termios call */
3222 if (port->set_termios)
3223 uart->port.set_termios = port->set_termios;
c161afe9
ML		 3224 if (port->pm)
3225 uart->port.pm = port->pm;
1da177e4 3226
af7f3743
AC		 3227 if (serial8250_isa_config != NULL)
3228 serial8250_isa_config(0, &uart->port,
3229 &uart->capabilities);
3230
1da177e4
LT		 3231 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3232 if (ret == 0)
3233 ret = uart->port.line;
3234 }
f392ecfa 3235 mutex_unlock(&serial_mutex);
1da177e4
LT		 3236
3237 return ret;
3238}
3239EXPORT_SYMBOL(serial8250_register_port);
3240
3241/**
3242 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3243 * @line: serial line number
3244 *
3245 * Remove one serial port. This may not be called from interrupt
3246 * context. We hand the port back to the our control.
3247 */
3248void serial8250_unregister_port(int line)
3249{
3250 struct uart_8250_port *uart = &serial8250_ports[line];
3251
f392ecfa 3252 mutex_lock(&serial_mutex);
1da177e4
LT		 3253 uart_remove_one_port(&serial8250_reg, &uart->port);
3254 if (serial8250_isa_devs) {
3255 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3256 uart->port.type = PORT_UNKNOWN;
3257 uart->port.dev = &serial8250_isa_devs->dev;
cb01ece3 3258 uart->capabilities = uart_config[uart->port.type].flags;
1da177e4
LT		 3259 uart_add_one_port(&serial8250_reg, &uart->port);
3260 } else {
3261 uart->port.dev = NULL;
3262 }
f392ecfa 3263 mutex_unlock(&serial_mutex);
1da177e4
LT		 3264}
3265EXPORT_SYMBOL(serial8250_unregister_port);
3266
3267static int __init serial8250_init(void)
3268{
25db8ad5 3269 int ret;
1da177e4 3270
a61c2d78
DJ		 3271 if (nr_uarts > UART_NR)
3272 nr_uarts = UART_NR;
3273
f1fb9bb8 3274 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3275 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3276 share_irqs ? "en" : "dis");
3277
b70ac771
DM		 3278#ifdef CONFIG_SPARC
3279 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3280#else
3281 serial8250_reg.nr = UART_NR;
1da177e4 3282 ret = uart_register_driver(&serial8250_reg);
b70ac771 3283#endif
1da177e4
LT		 3284 if (ret)
3285 goto out;
3286
7493a314
DT		 3287 serial8250_isa_devs = platform_device_alloc("serial8250",
3288 PLAT8250_DEV_LEGACY);
3289 if (!serial8250_isa_devs) {
3290 ret = -ENOMEM;
bc965a7f 3291 goto unreg_uart_drv;
1da177e4
LT		 3292 }
3293
7493a314
DT		 3294 ret = platform_device_add(serial8250_isa_devs);
3295 if (ret)
3296 goto put_dev;
3297
1da177e4
LT		 3298 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3299
bc965a7f
RK		 3300 ret = platform_driver_register(&serial8250_isa_driver);
3301 if (ret == 0)
3302 goto out;
1da177e4 3303
bc965a7f 3304 platform_device_del(serial8250_isa_devs);
25db8ad5 3305put_dev:
7493a314 3306 platform_device_put(serial8250_isa_devs);
25db8ad5 3307unreg_uart_drv:
b70ac771
DM		 3308#ifdef CONFIG_SPARC
3309 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3310#else
1da177e4 3311 uart_unregister_driver(&serial8250_reg);
b70ac771 3312#endif
25db8ad5 3313out:
1da177e4
LT		 3314 return ret;
3315}
3316
3317static void __exit serial8250_exit(void)
3318{
3319 struct platform_device *isa_dev = serial8250_isa_devs;
3320
3321 /*
3322 * This tells serial8250_unregister_port() not to re-register
3323 * the ports (thereby making serial8250_isa_driver permanently
3324 * in use.)
3325 */
3326 serial8250_isa_devs = NULL;
3327
3ae5eaec 3328 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3329 platform_device_unregister(isa_dev);
3330
b70ac771
DM		 3331#ifdef CONFIG_SPARC
3332 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3333#else
1da177e4 3334 uart_unregister_driver(&serial8250_reg);
b70ac771 3335#endif
1da177e4
LT		 3336}
3337
3338module_init(serial8250_init);
3339module_exit(serial8250_exit);
3340
3341EXPORT_SYMBOL(serial8250_suspend_port);
3342EXPORT_SYMBOL(serial8250_resume_port);
3343
3344MODULE_LICENSE("GPL");
d87a6d95 3345MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3346
3347module_param(share_irqs, uint, 0644);
3348MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3349 " (unsafe)");
3350
a61c2d78
DJ		 3351module_param(nr_uarts, uint, 0644);
3352MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3353
d41a4b51
CE		 3354module_param(skip_txen_test, uint, 0644);
3355MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3356
1da177e4
LT		 3357#ifdef CONFIG_SERIAL_8250_RSA
3358module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3359MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3360#endif
3361MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux kernel - Deliverables
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