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h8300: drivers/serial/Kconfig was moved
[deliverable/linux.git] / drivers / tty / serial / 8250_pci.c
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1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4
LT		 11 */
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
20#include <linux/serial_core.h>
21#include <linux/8250_pci.h>
22#include <linux/bitops.h>
23
24#include <asm/byteorder.h>
25#include <asm/io.h>
26
27#include "8250.h"
28
29#undef SERIAL_DEBUG_PCI
30
1da177e4
LT		 31/*
32 * init function returns:
33 * > 0 - number of ports
34 * = 0 - use board->num_ports
35 * < 0 - error
36 */
37struct pci_serial_quirk {
38 u32 vendor;
39 u32 device;
40 u32 subvendor;
41 u32 subdevice;
5bf8f501 42 int (*probe)(struct pci_dev *dev);
1da177e4 43 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 44 int (*setup)(struct serial_private *,
45 const struct pciserial_board *,
05caac58 46 struct uart_port *, int);
1da177e4
LT		 47 void (*exit)(struct pci_dev *dev);
48};
49
50#define PCI_NUM_BAR_RESOURCES 6
51
52struct serial_private {
70db3d91 53 struct pci_dev *dev;
1da177e4
LT		 54 unsigned int nr;
55 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
56 struct pci_serial_quirk *quirk;
57 int line[0];
58};
59
7808edcd
NG		 60static int pci_default_setup(struct serial_private*,
61 const struct pciserial_board*, struct uart_port*, int);
62
1da177e4
LT		 63static void moan_device(const char *str, struct pci_dev *dev)
64{
ad361c98
JP		 65 printk(KERN_WARNING
66 "%s: %s\n"
67 "Please send the output of lspci -vv, this\n"
68 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
69 "manufacturer and name of serial board or\n"
70 "modem board to rmk+serial@arm.linux.org.uk.\n",
1da177e4
LT		 71 pci_name(dev), str, dev->vendor, dev->device,
72 dev->subsystem_vendor, dev->subsystem_device);
73}
74
75static int
70db3d91 76setup_port(struct serial_private *priv, struct uart_port *port,
1da177e4
LT		 77 int bar, int offset, int regshift)
78{
70db3d91 79 struct pci_dev *dev = priv->dev;
1da177e4
LT		 80 unsigned long base, len;
81
82 if (bar >= PCI_NUM_BAR_RESOURCES)
83 return -EINVAL;
84
72ce9a83
RK		 85 base = pci_resource_start(dev, bar);
86
1da177e4 87 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 88 len = pci_resource_len(dev, bar);
89
90 if (!priv->remapped_bar[bar])
6f441fe9 91 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 92 if (!priv->remapped_bar[bar])
93 return -ENOMEM;
94
95 port->iotype = UPIO_MEM;
72ce9a83 96 port->iobase = 0;
1da177e4
LT		 97 port->mapbase = base + offset;
98 port->membase = priv->remapped_bar[bar] + offset;
99 port->regshift = regshift;
100 } else {
1da177e4 101 port->iotype = UPIO_PORT;
72ce9a83
RK		 102 port->iobase = base + offset;
103 port->mapbase = 0;
104 port->membase = NULL;
105 port->regshift = 0;
1da177e4
LT		 106 }
107 return 0;
108}
109
02c9b5cf
KJ		 110/*
111 * ADDI-DATA GmbH communication cards <info@addi-data.com>
112 */
113static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 114 const struct pciserial_board *board,
02c9b5cf
KJ		 115 struct uart_port *port, int idx)
116{
117 unsigned int bar = 0, offset = board->first_offset;
118 bar = FL_GET_BASE(board->flags);
119
120 if (idx < 2) {
121 offset += idx * board->uart_offset;
122 } else if ((idx >= 2) && (idx < 4)) {
123 bar += 1;
124 offset += ((idx - 2) * board->uart_offset);
125 } else if ((idx >= 4) && (idx < 6)) {
126 bar += 2;
127 offset += ((idx - 4) * board->uart_offset);
128 } else if (idx >= 6) {
129 bar += 3;
130 offset += ((idx - 6) * board->uart_offset);
131 }
132
133 return setup_port(priv, port, bar, offset, board->reg_shift);
134}
135
1da177e4
LT		 136/*
137 * AFAVLAB uses a different mixture of BARs and offsets
138 * Not that ugly ;) -- HW
139 */
140static int
975a1a7d 141afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 142 struct uart_port *port, int idx)
143{
144 unsigned int bar, offset = board->first_offset;
5756ee99 145
1da177e4
LT		 146 bar = FL_GET_BASE(board->flags);
147 if (idx < 4)
148 bar += idx;
149 else {
150 bar = 4;
151 offset += (idx - 4) * board->uart_offset;
152 }
153
70db3d91 154 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 155}
156
157/*
158 * HP's Remote Management Console. The Diva chip came in several
159 * different versions. N-class, L2000 and A500 have two Diva chips, each
160 * with 3 UARTs (the third UART on the second chip is unused). Superdome
161 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
162 * one Diva chip, but it has been expanded to 5 UARTs.
163 */
61a116ef 164static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 165{
166 int rc = 0;
167
168 switch (dev->subsystem_device) {
169 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
170 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
171 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
172 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
173 rc = 3;
174 break;
175 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
176 rc = 2;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
179 rc = 4;
180 break;
181 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 182 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 183 rc = 1;
184 break;
185 }
186
187 return rc;
188}
189
190/*
191 * HP's Diva chip puts the 4th/5th serial port further out, and
192 * some serial ports are supposed to be hidden on certain models.
193 */
194static int
975a1a7d
RK		 195pci_hp_diva_setup(struct serial_private *priv,
196 const struct pciserial_board *board,
197 struct uart_port *port, int idx)
1da177e4
LT		 198{
199 unsigned int offset = board->first_offset;
200 unsigned int bar = FL_GET_BASE(board->flags);
201
70db3d91 202 switch (priv->dev->subsystem_device) {
1da177e4
LT		 203 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
204 if (idx == 3)
205 idx++;
206 break;
207 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
208 if (idx > 0)
209 idx++;
210 if (idx > 2)
211 idx++;
212 break;
213 }
214 if (idx > 2)
215 offset = 0x18;
216
217 offset += idx * board->uart_offset;
218
70db3d91 219 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 220}
221
222/*
223 * Added for EKF Intel i960 serial boards
224 */
61a116ef 225static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 226{
227 unsigned long oldval;
228
229 if (!(dev->subsystem_device & 0x1000))
230 return -ENODEV;
231
232 /* is firmware started? */
5756ee99
AC		 233 pci_read_config_dword(dev, 0x44, (void *)&oldval);
234 if (oldval == 0x00001000L) { /* RESET value */
1da177e4
LT		 235 printk(KERN_DEBUG "Local i960 firmware missing");
236 return -ENODEV;
237 }
238 return 0;
239}
240
241/*
242 * Some PCI serial cards using the PLX 9050 PCI interface chip require
243 * that the card interrupt be explicitly enabled or disabled. This
244 * seems to be mainly needed on card using the PLX which also use I/O
245 * mapped memory.
246 */
61a116ef 247static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 248{
249 u8 irq_config;
250 void __iomem *p;
251
252 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
253 moan_device("no memory in bar 0", dev);
254 return 0;
255 }
256
257 irq_config = 0x41;
add7b58e 258 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 259 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 260 irq_config = 0x43;
5756ee99 261
1da177e4 262 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 263 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 264 /*
265 * As the megawolf cards have the int pins active
266 * high, and have 2 UART chips, both ints must be
267 * enabled on the 9050. Also, the UARTS are set in
268 * 16450 mode by default, so we have to enable the
269 * 16C950 'enhanced' mode so that we can use the
270 * deep FIFOs
271 */
272 irq_config = 0x5b;
1da177e4
LT		 273 /*
274 * enable/disable interrupts
275 */
6f441fe9 276 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 277 if (p == NULL)
278 return -ENOMEM;
279 writel(irq_config, p + 0x4c);
280
281 /*
282 * Read the register back to ensure that it took effect.
283 */
284 readl(p + 0x4c);
285 iounmap(p);
286
287 return 0;
288}
289
290static void __devexit pci_plx9050_exit(struct pci_dev *dev)
291{
292 u8 __iomem *p;
293
294 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
295 return;
296
297 /*
298 * disable interrupts
299 */
6f441fe9 300 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 301 if (p != NULL) {
302 writel(0, p + 0x4c);
303
304 /*
305 * Read the register back to ensure that it took effect.
306 */
307 readl(p + 0x4c);
308 iounmap(p);
309 }
310}
311
04bf7e74
WP		 312#define NI8420_INT_ENABLE_REG 0x38
313#define NI8420_INT_ENABLE_BIT 0x2000
314
315static void __devexit pci_ni8420_exit(struct pci_dev *dev)
316{
317 void __iomem *p;
318 unsigned long base, len;
319 unsigned int bar = 0;
320
321 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
322 moan_device("no memory in bar", dev);
323 return;
324 }
325
326 base = pci_resource_start(dev, bar);
327 len = pci_resource_len(dev, bar);
328 p = ioremap_nocache(base, len);
329 if (p == NULL)
330 return;
331
332 /* Disable the CPU Interrupt */
333 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
334 p + NI8420_INT_ENABLE_REG);
335 iounmap(p);
336}
337
338
46a0fac9
SB		 339/* MITE registers */
340#define MITE_IOWBSR1 0xc4
341#define MITE_IOWCR1 0xf4
342#define MITE_LCIMR1 0x08
343#define MITE_LCIMR2 0x10
344
345#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
346
347static void __devexit pci_ni8430_exit(struct pci_dev *dev)
348{
349 void __iomem *p;
350 unsigned long base, len;
351 unsigned int bar = 0;
352
353 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
354 moan_device("no memory in bar", dev);
355 return;
356 }
357
358 base = pci_resource_start(dev, bar);
359 len = pci_resource_len(dev, bar);
360 p = ioremap_nocache(base, len);
361 if (p == NULL)
362 return;
363
364 /* Disable the CPU Interrupt */
365 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
366 iounmap(p);
367}
368
1da177e4
LT		 369/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
370static int
975a1a7d 371sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 372 struct uart_port *port, int idx)
373{
374 unsigned int bar, offset = board->first_offset;
375
376 bar = 0;
377
378 if (idx < 4) {
379 /* first four channels map to 0, 0x100, 0x200, 0x300 */
380 offset += idx * board->uart_offset;
381 } else if (idx < 8) {
382 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
383 offset += idx * board->uart_offset + 0xC00;
384 } else /* we have only 8 ports on PMC-OCTALPRO */
385 return 1;
386
70db3d91 387 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 388}
389
390/*
391* This does initialization for PMC OCTALPRO cards:
392* maps the device memory, resets the UARTs (needed, bc
393* if the module is removed and inserted again, the card
394* is in the sleep mode) and enables global interrupt.
395*/
396
397/* global control register offset for SBS PMC-OctalPro */
398#define OCT_REG_CR_OFF 0x500
399
61a116ef 400static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 401{
402 u8 __iomem *p;
403
24ed3aba 404 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 405
406 if (p == NULL)
407 return -ENOMEM;
408 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 409 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 410 udelay(50);
5756ee99 411 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 412
413 /* Set bit-2 (INTENABLE) of Control Register */
414 writeb(0x4, p + OCT_REG_CR_OFF);
415 iounmap(p);
416
417 return 0;
418}
419
420/*
421 * Disables the global interrupt of PMC-OctalPro
422 */
423
424static void __devexit sbs_exit(struct pci_dev *dev)
425{
426 u8 __iomem *p;
427
24ed3aba 428 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 429 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
430 if (p != NULL)
1da177e4 431 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 432 iounmap(p);
433}
434
435/*
436 * SIIG serial cards have an PCI interface chip which also controls
437 * the UART clocking frequency. Each UART can be clocked independently
25985edc 438 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 439 * are stored in the EEPROM chip. It can cause problems because this
440 * version of serial driver doesn't support differently clocked UART's
441 * on single PCI card. To prevent this, initialization functions set
442 * high frequency clocking for all UART's on given card. It is safe (I
443 * hope) because it doesn't touch EEPROM settings to prevent conflicts
444 * with other OSes (like M$ DOS).
445 *
446 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 447 *
1da177e4
LT		 448 * There is two family of SIIG serial cards with different PCI
449 * interface chip and different configuration methods:
450 * - 10x cards have control registers in IO and/or memory space;
451 * - 20x cards have control registers in standard PCI configuration space.
452 *
67d74b87
RK		 453 * Note: all 10x cards have PCI device ids 0x10..
454 * all 20x cards have PCI device ids 0x20..
455 *
fbc0dc0d
AP		 456 * There are also Quartet Serial cards which use Oxford Semiconductor
457 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
458 *
1da177e4
LT		 459 * Note: some SIIG cards are probed by the parport_serial object.
460 */
461
462#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
463#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
464
465static int pci_siig10x_init(struct pci_dev *dev)
466{
467 u16 data;
468 void __iomem *p;
469
470 switch (dev->device & 0xfff8) {
471 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
472 data = 0xffdf;
473 break;
474 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
475 data = 0xf7ff;
476 break;
477 default: /* 1S1P, 4S */
478 data = 0xfffb;
479 break;
480 }
481
6f441fe9 482 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 483 if (p == NULL)
484 return -ENOMEM;
485
486 writew(readw(p + 0x28) & data, p + 0x28);
487 readw(p + 0x28);
488 iounmap(p);
489 return 0;
490}
491
492#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
493#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
494
495static int pci_siig20x_init(struct pci_dev *dev)
496{
497 u8 data;
498
499 /* Change clock frequency for the first UART. */
500 pci_read_config_byte(dev, 0x6f, &data);
501 pci_write_config_byte(dev, 0x6f, data & 0xef);
502
503 /* If this card has 2 UART, we have to do the same with second UART. */
504 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
505 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
506 pci_read_config_byte(dev, 0x73, &data);
507 pci_write_config_byte(dev, 0x73, data & 0xef);
508 }
509 return 0;
510}
511
67d74b87
RK		 512static int pci_siig_init(struct pci_dev *dev)
513{
514 unsigned int type = dev->device & 0xff00;
515
516 if (type == 0x1000)
517 return pci_siig10x_init(dev);
518 else if (type == 0x2000)
519 return pci_siig20x_init(dev);
520
521 moan_device("Unknown SIIG card", dev);
522 return -ENODEV;
523}
524
3ec9c594 525static int pci_siig_setup(struct serial_private *priv,
975a1a7d 526 const struct pciserial_board *board,
3ec9c594
AP		 527 struct uart_port *port, int idx)
528{
529 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
530
531 if (idx > 3) {
532 bar = 4;
533 offset = (idx - 4) * 8;
534 }
535
536 return setup_port(priv, port, bar, offset, 0);
537}
538
1da177e4
LT		 539/*
540 * Timedia has an explosion of boards, and to avoid the PCI table from
541 * growing *huge*, we use this function to collapse some 70 entries
542 * in the PCI table into one, for sanity's and compactness's sake.
543 */
e9422e09 544static const unsigned short timedia_single_port[] = {
1da177e4
LT		 545 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
546};
547
e9422e09 548static const unsigned short timedia_dual_port[] = {
1da177e4 549 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 550 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
551 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 552 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
553 0xD079, 0
554};
555
e9422e09 556static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 557 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
558 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 559 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
560 0xB157, 0
561};
562
e9422e09 563static const unsigned short timedia_eight_port[] = {
5756ee99 564 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 565 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
566};
567
cb3592be 568static const struct timedia_struct {
1da177e4 569 int num;
e9422e09 570 const unsigned short *ids;
1da177e4
LT		 571} timedia_data[] = {
572 { 1, timedia_single_port },
573 { 2, timedia_dual_port },
574 { 4, timedia_quad_port },
e9422e09 575 { 8, timedia_eight_port }
1da177e4
LT		 576};
577
b9b24558
FB		 578/*
579 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
580 * listing them individually, this driver merely grabs them all with
581 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
582 * and should be left free to be claimed by parport_serial instead.
583 */
584static int pci_timedia_probe(struct pci_dev *dev)
585{
586 /*
587 * Check the third digit of the subdevice ID
588 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
589 */
590 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
591 dev_info(&dev->dev,
592 "ignoring Timedia subdevice %04x for parport_serial\n",
593 dev->subsystem_device);
594 return -ENODEV;
595 }
596
597 return 0;
598}
599
61a116ef 600static int pci_timedia_init(struct pci_dev *dev)
1da177e4 601{
e9422e09 602 const unsigned short *ids;
1da177e4
LT		 603 int i, j;
604
e9422e09 605 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 606 ids = timedia_data[i].ids;
607 for (j = 0; ids[j]; j++)
608 if (dev->subsystem_device == ids[j])
609 return timedia_data[i].num;
610 }
611 return 0;
612}
613
614/*
615 * Timedia/SUNIX uses a mixture of BARs and offsets
616 * Ugh, this is ugly as all hell --- TYT
617 */
618static int
975a1a7d
RK		 619pci_timedia_setup(struct serial_private *priv,
620 const struct pciserial_board *board,
1da177e4
LT		 621 struct uart_port *port, int idx)
622{
623 unsigned int bar = 0, offset = board->first_offset;
624
625 switch (idx) {
626 case 0:
627 bar = 0;
628 break;
629 case 1:
630 offset = board->uart_offset;
631 bar = 0;
632 break;
633 case 2:
634 bar = 1;
635 break;
636 case 3:
637 offset = board->uart_offset;
c2cd6d3c 638 /* FALLTHROUGH */
1da177e4
LT		 639 case 4: /* BAR 2 */
640 case 5: /* BAR 3 */
641 case 6: /* BAR 4 */
642 case 7: /* BAR 5 */
643 bar = idx - 2;
644 }
645
70db3d91 646 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 647}
648
649/*
650 * Some Titan cards are also a little weird
651 */
652static int
70db3d91 653titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 654 const struct pciserial_board *board,
1da177e4
LT		 655 struct uart_port *port, int idx)
656{
657 unsigned int bar, offset = board->first_offset;
658
659 switch (idx) {
660 case 0:
661 bar = 1;
662 break;
663 case 1:
664 bar = 2;
665 break;
666 default:
667 bar = 4;
668 offset = (idx - 2) * board->uart_offset;
669 }
670
70db3d91 671 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 672}
673
61a116ef 674static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 675{
676 msleep(100);
677 return 0;
678}
679
04bf7e74
WP		 680static int pci_ni8420_init(struct pci_dev *dev)
681{
682 void __iomem *p;
683 unsigned long base, len;
684 unsigned int bar = 0;
685
686 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
687 moan_device("no memory in bar", dev);
688 return 0;
689 }
690
691 base = pci_resource_start(dev, bar);
692 len = pci_resource_len(dev, bar);
693 p = ioremap_nocache(base, len);
694 if (p == NULL)
695 return -ENOMEM;
696
697 /* Enable CPU Interrupt */
698 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
699 p + NI8420_INT_ENABLE_REG);
700
701 iounmap(p);
702 return 0;
703}
704
46a0fac9
SB		 705#define MITE_IOWBSR1_WSIZE 0xa
706#define MITE_IOWBSR1_WIN_OFFSET 0x800
707#define MITE_IOWBSR1_WENAB (1 << 7)
708#define MITE_LCIMR1_IO_IE_0 (1 << 24)
709#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
710#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
711
712static int pci_ni8430_init(struct pci_dev *dev)
713{
714 void __iomem *p;
715 unsigned long base, len;
716 u32 device_window;
717 unsigned int bar = 0;
718
719 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
720 moan_device("no memory in bar", dev);
721 return 0;
722 }
723
724 base = pci_resource_start(dev, bar);
725 len = pci_resource_len(dev, bar);
726 p = ioremap_nocache(base, len);
727 if (p == NULL)
728 return -ENOMEM;
729
730 /* Set device window address and size in BAR0 */
731 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
732 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
733 writel(device_window, p + MITE_IOWBSR1);
734
735 /* Set window access to go to RAMSEL IO address space */
736 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
737 p + MITE_IOWCR1);
738
739 /* Enable IO Bus Interrupt 0 */
740 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
741
742 /* Enable CPU Interrupt */
743 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
744
745 iounmap(p);
746 return 0;
747}
748
749/* UART Port Control Register */
750#define NI8430_PORTCON 0x0f
751#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
752
753static int
bf538fe4
AC		 754pci_ni8430_setup(struct serial_private *priv,
755 const struct pciserial_board *board,
46a0fac9
SB		 756 struct uart_port *port, int idx)
757{
758 void __iomem *p;
759 unsigned long base, len;
760 unsigned int bar, offset = board->first_offset;
761
762 if (idx >= board->num_ports)
763 return 1;
764
765 bar = FL_GET_BASE(board->flags);
766 offset += idx * board->uart_offset;
767
768 base = pci_resource_start(priv->dev, bar);
769 len = pci_resource_len(priv->dev, bar);
770 p = ioremap_nocache(base, len);
771
7c9d440e 772 /* enable the transceiver */
46a0fac9
SB		 773 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
774 p + offset + NI8430_PORTCON);
775
776 iounmap(p);
777
778 return setup_port(priv, port, bar, offset, board->reg_shift);
779}
780
7808edcd
NG		 781static int pci_netmos_9900_setup(struct serial_private *priv,
782 const struct pciserial_board *board,
783 struct uart_port *port, int idx)
784{
785 unsigned int bar;
786
787 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
788 /* netmos apparently orders BARs by datasheet layout, so serial
789 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
790 */
791 bar = 3 * idx;
792
793 return setup_port(priv, port, bar, 0, board->reg_shift);
794 } else {
795 return pci_default_setup(priv, board, port, idx);
796 }
797}
798
799/* the 99xx series comes with a range of device IDs and a variety
800 * of capabilities:
801 *
802 * 9900 has varying capabilities and can cascade to sub-controllers
803 * (cascading should be purely internal)
804 * 9904 is hardwired with 4 serial ports
805 * 9912 and 9922 are hardwired with 2 serial ports
806 */
807static int pci_netmos_9900_numports(struct pci_dev *dev)
808{
809 unsigned int c = dev->class;
810 unsigned int pi;
811 unsigned short sub_serports;
812
813 pi = (c & 0xff);
814
815 if (pi == 2) {
816 return 1;
817 } else if ((pi == 0) &&
818 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
819 /* two possibilities: 0x30ps encodes number of parallel and
820 * serial ports, or 0x1000 indicates *something*. This is not
821 * immediately obvious, since the 2s1p+4s configuration seems
822 * to offer all functionality on functions 0..2, while still
823 * advertising the same function 3 as the 4s+2s1p config.
824 */
825 sub_serports = dev->subsystem_device & 0xf;
826 if (sub_serports > 0) {
827 return sub_serports;
828 } else {
829 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
830 return 0;
831 }
832 }
833
834 moan_device("unknown NetMos/Mostech program interface", dev);
835 return 0;
836}
46a0fac9 837
61a116ef 838static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 839{
840 /* subdevice 0x00PS means <P> parallel, <S> serial */
841 unsigned int num_serial = dev->subsystem_device & 0xf;
842
ac6ec5b1
IS		 843 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
844 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 845 return 0;
7808edcd 846
25cf9bc1
JS		 847 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
848 dev->subsystem_device == 0x0299)
849 return 0;
850
7808edcd
NG		 851 switch (dev->device) { /* FALLTHROUGH on all */
852 case PCI_DEVICE_ID_NETMOS_9904:
853 case PCI_DEVICE_ID_NETMOS_9912:
854 case PCI_DEVICE_ID_NETMOS_9922:
855 case PCI_DEVICE_ID_NETMOS_9900:
856 num_serial = pci_netmos_9900_numports(dev);
857 break;
858
859 default:
860 if (num_serial == 0 ) {
861 moan_device("unknown NetMos/Mostech device", dev);
862 }
863 }
864
1da177e4
LT		 865 if (num_serial == 0)
866 return -ENODEV;
7808edcd 867
1da177e4
LT		 868 return num_serial;
869}
870
84f8c6fc 871/*
84f8c6fc
NV		 872 * These chips are available with optionally one parallel port and up to
873 * two serial ports. Unfortunately they all have the same product id.
874 *
875 * Basic configuration is done over a region of 32 I/O ports. The base
876 * ioport is called INTA or INTC, depending on docs/other drivers.
877 *
878 * The region of the 32 I/O ports is configured in POSIO0R...
879 */
880
881/* registers */
882#define ITE_887x_MISCR 0x9c
883#define ITE_887x_INTCBAR 0x78
884#define ITE_887x_UARTBAR 0x7c
885#define ITE_887x_PS0BAR 0x10
886#define ITE_887x_POSIO0 0x60
887
888/* I/O space size */
889#define ITE_887x_IOSIZE 32
890/* I/O space size (bits 26-24; 8 bytes = 011b) */
891#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
892/* I/O space size (bits 26-24; 32 bytes = 101b) */
893#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
894/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
895#define ITE_887x_POSIO_SPEED (3 << 29)
896/* enable IO_Space bit */
897#define ITE_887x_POSIO_ENABLE (1 << 31)
898
f79abb82 899static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 900{
901 /* inta_addr are the configuration addresses of the ITE */
902 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
903 0x200, 0x280, 0 };
904 int ret, i, type;
905 struct resource *iobase = NULL;
906 u32 miscr, uartbar, ioport;
907
908 /* search for the base-ioport */
909 i = 0;
910 while (inta_addr[i] && iobase == NULL) {
911 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
912 "ite887x");
913 if (iobase != NULL) {
914 /* write POSIO0R - speed | size | ioport */
915 pci_write_config_dword(dev, ITE_887x_POSIO0,
916 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
917 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
918 /* write INTCBAR - ioport */
5756ee99
AC		 919 pci_write_config_dword(dev, ITE_887x_INTCBAR,
920 inta_addr[i]);
84f8c6fc
NV		 921 ret = inb(inta_addr[i]);
922 if (ret != 0xff) {
923 /* ioport connected */
924 break;
925 }
926 release_region(iobase->start, ITE_887x_IOSIZE);
927 iobase = NULL;
928 }
929 i++;
930 }
931
932 if (!inta_addr[i]) {
933 printk(KERN_ERR "ite887x: could not find iobase\n");
934 return -ENODEV;
935 }
936
937 /* start of undocumented type checking (see parport_pc.c) */
938 type = inb(iobase->start + 0x18) & 0x0f;
939
940 switch (type) {
941 case 0x2: /* ITE8871 (1P) */
942 case 0xa: /* ITE8875 (1P) */
943 ret = 0;
944 break;
945 case 0xe: /* ITE8872 (2S1P) */
946 ret = 2;
947 break;
948 case 0x6: /* ITE8873 (1S) */
949 ret = 1;
950 break;
951 case 0x8: /* ITE8874 (2S) */
952 ret = 2;
953 break;
954 default:
955 moan_device("Unknown ITE887x", dev);
956 ret = -ENODEV;
957 }
958
959 /* configure all serial ports */
960 for (i = 0; i < ret; i++) {
961 /* read the I/O port from the device */
962 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
963 &ioport);
964 ioport &= 0x0000FF00; /* the actual base address */
965 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
966 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
967 ITE_887x_POSIO_IOSIZE_8 | ioport);
968
969 /* write the ioport to the UARTBAR */
970 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
971 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
972 uartbar |= (ioport << (16 * i)); /* set the ioport */
973 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
974
975 /* get current config */
976 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
977 /* disable interrupts (UARTx_Routing[3:0]) */
978 miscr &= ~(0xf << (12 - 4 * i));
979 /* activate the UART (UARTx_En) */
980 miscr |= 1 << (23 - i);
981 /* write new config with activated UART */
982 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
983 }
984
985 if (ret <= 0) {
986 /* the device has no UARTs if we get here */
987 release_region(iobase->start, ITE_887x_IOSIZE);
988 }
989
990 return ret;
991}
992
993static void __devexit pci_ite887x_exit(struct pci_dev *dev)
994{
995 u32 ioport;
996 /* the ioport is bit 0-15 in POSIO0R */
997 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
998 ioport &= 0xffff;
999 release_region(ioport, ITE_887x_IOSIZE);
1000}
1001
9f2a036a
RK		 1002/*
1003 * Oxford Semiconductor Inc.
1004 * Check that device is part of the Tornado range of devices, then determine
1005 * the number of ports available on the device.
1006 */
1007static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008{
1009 u8 __iomem *p;
1010 unsigned long deviceID;
1011 unsigned int number_uarts = 0;
1012
1013 /* OxSemi Tornado devices are all 0xCxxx */
1014 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015 (dev->device & 0xF000) != 0xC000)
1016 return 0;
1017
1018 p = pci_iomap(dev, 0, 5);
1019 if (p == NULL)
1020 return -ENOMEM;
1021
1022 deviceID = ioread32(p);
1023 /* Tornado device */
1024 if (deviceID == 0x07000200) {
1025 number_uarts = ioread8(p + 4);
1026 printk(KERN_DEBUG
1027 "%d ports detected on Oxford PCI Express device\n",
1028 number_uarts);
1029 }
1030 pci_iounmap(dev, p);
1031 return number_uarts;
1032}
1033
1da177e4 1034static int
975a1a7d
RK		 1035pci_default_setup(struct serial_private *priv,
1036 const struct pciserial_board *board,
1da177e4
LT		 1037 struct uart_port *port, int idx)
1038{
1039 unsigned int bar, offset = board->first_offset, maxnr;
1040
1041 bar = FL_GET_BASE(board->flags);
1042 if (board->flags & FL_BASE_BARS)
1043 bar += idx;
1044 else
1045 offset += idx * board->uart_offset;
1046
2427ddd8
GKH		 1047 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1048 (board->reg_shift + 3);
1da177e4
LT		 1049
1050 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1051 return 1;
5756ee99 1052
70db3d91 1053 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 1054}
1055
095e24b0
DB		 1056static int
1057ce4100_serial_setup(struct serial_private *priv,
1058 const struct pciserial_board *board,
1059 struct uart_port *port, int idx)
1060{
1061 int ret;
1062
1063 ret = setup_port(priv, port, 0, 0, board->reg_shift);
1064 port->iotype = UPIO_MEM32;
1065 port->type = PORT_XSCALE;
1066 port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1067 port->regshift = 2;
1068
1069 return ret;
1070}
1071
d9a0fbfd
AP		 1072static int
1073pci_omegapci_setup(struct serial_private *priv,
1798ca13 1074 const struct pciserial_board *board,
d9a0fbfd
AP		 1075 struct uart_port *port, int idx)
1076{
1077 return setup_port(priv, port, 2, idx * 8, 0);
1078}
1079
b6adea33
MCC		 1080static int skip_tx_en_setup(struct serial_private *priv,
1081 const struct pciserial_board *board,
1082 struct uart_port *port, int idx)
1083{
1084 port->flags |= UPF_NO_TXEN_TEST;
1085 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1086 "[%04x:%04x] subsystem [%04x:%04x]\n",
1087 priv->dev->vendor,
1088 priv->dev->device,
1089 priv->dev->subsystem_vendor,
1090 priv->dev->subsystem_device);
1091
1092 return pci_default_setup(priv, board, port, idx);
1093}
1094
eb7073db
TM		 1095static int pci_eg20t_init(struct pci_dev *dev)
1096{
1097#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1098 return -ENODEV;
1099#else
1100 return 0;
1101#endif
1102}
1103
06315348
SH		 1104static int
1105pci_xr17c154_setup(struct serial_private *priv,
1106 const struct pciserial_board *board,
1107 struct uart_port *port, int idx)
1108{
1109 port->flags |= UPF_EXAR_EFR;
1110 return pci_default_setup(priv, board, port, idx);
1111}
1112
1da177e4
LT		 1113/* This should be in linux/pci_ids.h */
1114#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1115#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1116#define PCI_DEVICE_ID_OCTPRO 0x0001
1117#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1118#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1119#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1120#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
78d70d48 1121#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 1122#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 1123#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
66169ad1
YY		 1124#define PCI_DEVICE_ID_TITAN_200I 0x8028
1125#define PCI_DEVICE_ID_TITAN_400I 0x8048
1126#define PCI_DEVICE_ID_TITAN_800I 0x8088
1127#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1128#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1129#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1130#define PCI_DEVICE_ID_TITAN_100E 0xA010
1131#define PCI_DEVICE_ID_TITAN_200E 0xA012
1132#define PCI_DEVICE_ID_TITAN_400E 0xA013
1133#define PCI_DEVICE_ID_TITAN_800E 0xA014
1134#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1135#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
e847003f 1136#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
aa273ae5 1137#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
d9a0fbfd 1138#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1da177e4 1139
b76c5a07
CB		 1140/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1141#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1142
1da177e4
LT		 1143/*
1144 * Master list of serial port init/setup/exit quirks.
1145 * This does not describe the general nature of the port.
1146 * (ie, baud base, number and location of ports, etc)
1147 *
1148 * This list is ordered alphabetically by vendor then device.
1149 * Specific entries must come before more generic entries.
1150 */
7a63ce5a 1151static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 1152 /*
1153 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1154 */
1155 {
1156 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1157 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1158 .subvendor = PCI_ANY_ID,
1159 .subdevice = PCI_ANY_ID,
1160 .setup = addidata_apci7800_setup,
1161 },
1da177e4 1162 /*
61a116ef 1163 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 1164 * It is not clear whether this applies to all products.
1165 */
1166 {
1167 .vendor = PCI_VENDOR_ID_AFAVLAB,
1168 .device = PCI_ANY_ID,
1169 .subvendor = PCI_ANY_ID,
1170 .subdevice = PCI_ANY_ID,
1171 .setup = afavlab_setup,
1172 },
1173 /*
1174 * HP Diva
1175 */
1176 {
1177 .vendor = PCI_VENDOR_ID_HP,
1178 .device = PCI_DEVICE_ID_HP_DIVA,
1179 .subvendor = PCI_ANY_ID,
1180 .subdevice = PCI_ANY_ID,
1181 .init = pci_hp_diva_init,
1182 .setup = pci_hp_diva_setup,
1183 },
1184 /*
1185 * Intel
1186 */
1187 {
1188 .vendor = PCI_VENDOR_ID_INTEL,
1189 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1190 .subvendor = 0xe4bf,
1191 .subdevice = PCI_ANY_ID,
1192 .init = pci_inteli960ni_init,
1193 .setup = pci_default_setup,
1194 },
b6adea33
MCC		 1195 {
1196 .vendor = PCI_VENDOR_ID_INTEL,
1197 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1198 .subvendor = PCI_ANY_ID,
1199 .subdevice = PCI_ANY_ID,
1200 .setup = skip_tx_en_setup,
1201 },
1202 {
1203 .vendor = PCI_VENDOR_ID_INTEL,
1204 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1205 .subvendor = PCI_ANY_ID,
1206 .subdevice = PCI_ANY_ID,
1207 .setup = skip_tx_en_setup,
1208 },
1209 {
1210 .vendor = PCI_VENDOR_ID_INTEL,
1211 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1212 .subvendor = PCI_ANY_ID,
1213 .subdevice = PCI_ANY_ID,
1214 .setup = skip_tx_en_setup,
1215 },
095e24b0
DB		 1216 {
1217 .vendor = PCI_VENDOR_ID_INTEL,
1218 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1219 .subvendor = PCI_ANY_ID,
1220 .subdevice = PCI_ANY_ID,
1221 .setup = ce4100_serial_setup,
1222 },
84f8c6fc
NV		 1223 /*
1224 * ITE
1225 */
1226 {
1227 .vendor = PCI_VENDOR_ID_ITE,
1228 .device = PCI_DEVICE_ID_ITE_8872,
1229 .subvendor = PCI_ANY_ID,
1230 .subdevice = PCI_ANY_ID,
1231 .init = pci_ite887x_init,
1232 .setup = pci_default_setup,
1233 .exit = __devexit_p(pci_ite887x_exit),
1234 },
46a0fac9
SB		 1235 /*
1236 * National Instruments
1237 */
04bf7e74
WP		 1238 {
1239 .vendor = PCI_VENDOR_ID_NI,
1240 .device = PCI_DEVICE_ID_NI_PCI23216,
1241 .subvendor = PCI_ANY_ID,
1242 .subdevice = PCI_ANY_ID,
1243 .init = pci_ni8420_init,
1244 .setup = pci_default_setup,
1245 .exit = __devexit_p(pci_ni8420_exit),
1246 },
1247 {
1248 .vendor = PCI_VENDOR_ID_NI,
1249 .device = PCI_DEVICE_ID_NI_PCI2328,
1250 .subvendor = PCI_ANY_ID,
1251 .subdevice = PCI_ANY_ID,
1252 .init = pci_ni8420_init,
1253 .setup = pci_default_setup,
1254 .exit = __devexit_p(pci_ni8420_exit),
1255 },
1256 {
1257 .vendor = PCI_VENDOR_ID_NI,
1258 .device = PCI_DEVICE_ID_NI_PCI2324,
1259 .subvendor = PCI_ANY_ID,
1260 .subdevice = PCI_ANY_ID,
1261 .init = pci_ni8420_init,
1262 .setup = pci_default_setup,
1263 .exit = __devexit_p(pci_ni8420_exit),
1264 },
1265 {
1266 .vendor = PCI_VENDOR_ID_NI,
1267 .device = PCI_DEVICE_ID_NI_PCI2322,
1268 .subvendor = PCI_ANY_ID,
1269 .subdevice = PCI_ANY_ID,
1270 .init = pci_ni8420_init,
1271 .setup = pci_default_setup,
1272 .exit = __devexit_p(pci_ni8420_exit),
1273 },
1274 {
1275 .vendor = PCI_VENDOR_ID_NI,
1276 .device = PCI_DEVICE_ID_NI_PCI2324I,
1277 .subvendor = PCI_ANY_ID,
1278 .subdevice = PCI_ANY_ID,
1279 .init = pci_ni8420_init,
1280 .setup = pci_default_setup,
1281 .exit = __devexit_p(pci_ni8420_exit),
1282 },
1283 {
1284 .vendor = PCI_VENDOR_ID_NI,
1285 .device = PCI_DEVICE_ID_NI_PCI2322I,
1286 .subvendor = PCI_ANY_ID,
1287 .subdevice = PCI_ANY_ID,
1288 .init = pci_ni8420_init,
1289 .setup = pci_default_setup,
1290 .exit = __devexit_p(pci_ni8420_exit),
1291 },
1292 {
1293 .vendor = PCI_VENDOR_ID_NI,
1294 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1295 .subvendor = PCI_ANY_ID,
1296 .subdevice = PCI_ANY_ID,
1297 .init = pci_ni8420_init,
1298 .setup = pci_default_setup,
1299 .exit = __devexit_p(pci_ni8420_exit),
1300 },
1301 {
1302 .vendor = PCI_VENDOR_ID_NI,
1303 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1304 .subvendor = PCI_ANY_ID,
1305 .subdevice = PCI_ANY_ID,
1306 .init = pci_ni8420_init,
1307 .setup = pci_default_setup,
1308 .exit = __devexit_p(pci_ni8420_exit),
1309 },
1310 {
1311 .vendor = PCI_VENDOR_ID_NI,
1312 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1313 .subvendor = PCI_ANY_ID,
1314 .subdevice = PCI_ANY_ID,
1315 .init = pci_ni8420_init,
1316 .setup = pci_default_setup,
1317 .exit = __devexit_p(pci_ni8420_exit),
1318 },
1319 {
1320 .vendor = PCI_VENDOR_ID_NI,
1321 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1322 .subvendor = PCI_ANY_ID,
1323 .subdevice = PCI_ANY_ID,
1324 .init = pci_ni8420_init,
1325 .setup = pci_default_setup,
1326 .exit = __devexit_p(pci_ni8420_exit),
1327 },
1328 {
1329 .vendor = PCI_VENDOR_ID_NI,
1330 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1331 .subvendor = PCI_ANY_ID,
1332 .subdevice = PCI_ANY_ID,
1333 .init = pci_ni8420_init,
1334 .setup = pci_default_setup,
1335 .exit = __devexit_p(pci_ni8420_exit),
1336 },
1337 {
1338 .vendor = PCI_VENDOR_ID_NI,
1339 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1340 .subvendor = PCI_ANY_ID,
1341 .subdevice = PCI_ANY_ID,
1342 .init = pci_ni8420_init,
1343 .setup = pci_default_setup,
1344 .exit = __devexit_p(pci_ni8420_exit),
1345 },
46a0fac9
SB		 1346 {
1347 .vendor = PCI_VENDOR_ID_NI,
1348 .device = PCI_ANY_ID,
1349 .subvendor = PCI_ANY_ID,
1350 .subdevice = PCI_ANY_ID,
1351 .init = pci_ni8430_init,
1352 .setup = pci_ni8430_setup,
1353 .exit = __devexit_p(pci_ni8430_exit),
1354 },
1da177e4
LT		 1355 /*
1356 * Panacom
1357 */
1358 {
1359 .vendor = PCI_VENDOR_ID_PANACOM,
1360 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1361 .subvendor = PCI_ANY_ID,
1362 .subdevice = PCI_ANY_ID,
1363 .init = pci_plx9050_init,
1364 .setup = pci_default_setup,
1365 .exit = __devexit_p(pci_plx9050_exit),
5756ee99 1366 },
1da177e4
LT		 1367 {
1368 .vendor = PCI_VENDOR_ID_PANACOM,
1369 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1370 .subvendor = PCI_ANY_ID,
1371 .subdevice = PCI_ANY_ID,
1372 .init = pci_plx9050_init,
1373 .setup = pci_default_setup,
1374 .exit = __devexit_p(pci_plx9050_exit),
1375 },
1376 /*
1377 * PLX
1378 */
48212008
TH		 1379 {
1380 .vendor = PCI_VENDOR_ID_PLX,
1381 .device = PCI_DEVICE_ID_PLX_9030,
1382 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1383 .subdevice = PCI_ANY_ID,
1384 .setup = pci_default_setup,
1385 },
add7b58e
BH		 1386 {
1387 .vendor = PCI_VENDOR_ID_PLX,
1388 .device = PCI_DEVICE_ID_PLX_9050,
1389 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1390 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1391 .init = pci_plx9050_init,
1392 .setup = pci_default_setup,
1393 .exit = __devexit_p(pci_plx9050_exit),
1394 },
1da177e4
LT		 1395 {
1396 .vendor = PCI_VENDOR_ID_PLX,
1397 .device = PCI_DEVICE_ID_PLX_9050,
1398 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1399 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1400 .init = pci_plx9050_init,
1401 .setup = pci_default_setup,
1402 .exit = __devexit_p(pci_plx9050_exit),
1403 },
b76c5a07
CB		 1404 {
1405 .vendor = PCI_VENDOR_ID_PLX,
1406 .device = PCI_DEVICE_ID_PLX_9050,
1407 .subvendor = PCI_VENDOR_ID_PLX,
1408 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1409 .init = pci_plx9050_init,
1410 .setup = pci_default_setup,
1411 .exit = __devexit_p(pci_plx9050_exit),
1412 },
1da177e4
LT		 1413 {
1414 .vendor = PCI_VENDOR_ID_PLX,
1415 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1416 .subvendor = PCI_VENDOR_ID_PLX,
1417 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1418 .init = pci_plx9050_init,
1419 .setup = pci_default_setup,
1420 .exit = __devexit_p(pci_plx9050_exit),
1421 },
1422 /*
1423 * SBS Technologies, Inc., PMC-OCTALPRO 232
1424 */
1425 {
1426 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1427 .device = PCI_DEVICE_ID_OCTPRO,
1428 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1429 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1430 .init = sbs_init,
1431 .setup = sbs_setup,
1432 .exit = __devexit_p(sbs_exit),
1433 },
1434 /*
1435 * SBS Technologies, Inc., PMC-OCTALPRO 422
1436 */
1437 {
1438 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1439 .device = PCI_DEVICE_ID_OCTPRO,
1440 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1441 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1442 .init = sbs_init,
1443 .setup = sbs_setup,
1444 .exit = __devexit_p(sbs_exit),
1445 },
1446 /*
1447 * SBS Technologies, Inc., P-Octal 232
1448 */
1449 {
1450 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1451 .device = PCI_DEVICE_ID_OCTPRO,
1452 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1453 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1454 .init = sbs_init,
1455 .setup = sbs_setup,
1456 .exit = __devexit_p(sbs_exit),
1457 },
1458 /*
1459 * SBS Technologies, Inc., P-Octal 422
1460 */
1461 {
1462 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1463 .device = PCI_DEVICE_ID_OCTPRO,
1464 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1465 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1466 .init = sbs_init,
1467 .setup = sbs_setup,
1468 .exit = __devexit_p(sbs_exit),
1469 },
1da177e4 1470 /*
61a116ef 1471 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 1472 */
1473 {
1474 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 1475 .device = PCI_ANY_ID,
1da177e4
LT		 1476 .subvendor = PCI_ANY_ID,
1477 .subdevice = PCI_ANY_ID,
67d74b87 1478 .init = pci_siig_init,
3ec9c594 1479 .setup = pci_siig_setup,
1da177e4
LT		 1480 },
1481 /*
1482 * Titan cards
1483 */
1484 {
1485 .vendor = PCI_VENDOR_ID_TITAN,
1486 .device = PCI_DEVICE_ID_TITAN_400L,
1487 .subvendor = PCI_ANY_ID,
1488 .subdevice = PCI_ANY_ID,
1489 .setup = titan_400l_800l_setup,
1490 },
1491 {
1492 .vendor = PCI_VENDOR_ID_TITAN,
1493 .device = PCI_DEVICE_ID_TITAN_800L,
1494 .subvendor = PCI_ANY_ID,
1495 .subdevice = PCI_ANY_ID,
1496 .setup = titan_400l_800l_setup,
1497 },
1498 /*
1499 * Timedia cards
1500 */
1501 {
1502 .vendor = PCI_VENDOR_ID_TIMEDIA,
1503 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1504 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1505 .subdevice = PCI_ANY_ID,
b9b24558 1506 .probe = pci_timedia_probe,
1da177e4
LT		 1507 .init = pci_timedia_init,
1508 .setup = pci_timedia_setup,
1509 },
1510 {
1511 .vendor = PCI_VENDOR_ID_TIMEDIA,
1512 .device = PCI_ANY_ID,
1513 .subvendor = PCI_ANY_ID,
1514 .subdevice = PCI_ANY_ID,
1515 .setup = pci_timedia_setup,
1516 },
06315348
SH		 1517 /*
1518 * Exar cards
1519 */
1520 {
1521 .vendor = PCI_VENDOR_ID_EXAR,
1522 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1523 .subvendor = PCI_ANY_ID,
1524 .subdevice = PCI_ANY_ID,
1525 .setup = pci_xr17c154_setup,
1526 },
1527 {
1528 .vendor = PCI_VENDOR_ID_EXAR,
1529 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1530 .subvendor = PCI_ANY_ID,
1531 .subdevice = PCI_ANY_ID,
1532 .setup = pci_xr17c154_setup,
1533 },
1534 {
1535 .vendor = PCI_VENDOR_ID_EXAR,
1536 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1537 .subvendor = PCI_ANY_ID,
1538 .subdevice = PCI_ANY_ID,
1539 .setup = pci_xr17c154_setup,
1540 },
1da177e4
LT		 1541 /*
1542 * Xircom cards
1543 */
1544 {
1545 .vendor = PCI_VENDOR_ID_XIRCOM,
1546 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1547 .subvendor = PCI_ANY_ID,
1548 .subdevice = PCI_ANY_ID,
1549 .init = pci_xircom_init,
1550 .setup = pci_default_setup,
1551 },
1552 /*
61a116ef 1553 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 1554 */
1555 {
1556 .vendor = PCI_VENDOR_ID_NETMOS,
1557 .device = PCI_ANY_ID,
1558 .subvendor = PCI_ANY_ID,
1559 .subdevice = PCI_ANY_ID,
1560 .init = pci_netmos_init,
7808edcd 1561 .setup = pci_netmos_9900_setup,
1da177e4 1562 },
9f2a036a 1563 /*
aa273ae5 1564 * For Oxford Semiconductor Tornado based devices
9f2a036a
RK		 1565 */
1566 {
1567 .vendor = PCI_VENDOR_ID_OXSEMI,
1568 .device = PCI_ANY_ID,
1569 .subvendor = PCI_ANY_ID,
1570 .subdevice = PCI_ANY_ID,
1571 .init = pci_oxsemi_tornado_init,
1572 .setup = pci_default_setup,
1573 },
1574 {
1575 .vendor = PCI_VENDOR_ID_MAINPINE,
1576 .device = PCI_ANY_ID,
1577 .subvendor = PCI_ANY_ID,
1578 .subdevice = PCI_ANY_ID,
1579 .init = pci_oxsemi_tornado_init,
1580 .setup = pci_default_setup,
1581 },
aa273ae5
SK		 1582 {
1583 .vendor = PCI_VENDOR_ID_DIGI,
1584 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1585 .subvendor = PCI_SUBVENDOR_ID_IBM,
1586 .subdevice = PCI_ANY_ID,
1587 .init = pci_oxsemi_tornado_init,
1588 .setup = pci_default_setup,
1589 },
eb7073db
TM		 1590 {
1591 .vendor = PCI_VENDOR_ID_INTEL,
1592 .device = 0x8811,
1593 .init = pci_eg20t_init,
1594 },
1595 {
1596 .vendor = PCI_VENDOR_ID_INTEL,
1597 .device = 0x8812,
1598 .init = pci_eg20t_init,
1599 },
1600 {
1601 .vendor = PCI_VENDOR_ID_INTEL,
1602 .device = 0x8813,
1603 .init = pci_eg20t_init,
1604 },
1605 {
1606 .vendor = PCI_VENDOR_ID_INTEL,
1607 .device = 0x8814,
1608 .init = pci_eg20t_init,
1609 },
1610 {
1611 .vendor = 0x10DB,
1612 .device = 0x8027,
1613 .init = pci_eg20t_init,
1614 },
1615 {
1616 .vendor = 0x10DB,
1617 .device = 0x8028,
1618 .init = pci_eg20t_init,
1619 },
1620 {
1621 .vendor = 0x10DB,
1622 .device = 0x8029,
1623 .init = pci_eg20t_init,
1624 },
1625 {
1626 .vendor = 0x10DB,
1627 .device = 0x800C,
1628 .init = pci_eg20t_init,
1629 },
1630 {
1631 .vendor = 0x10DB,
1632 .device = 0x800D,
1633 .init = pci_eg20t_init,
1634 },
1635 {
1636 .vendor = 0x10DB,
1637 .device = 0x800D,
1638 .init = pci_eg20t_init,
1639 },
d9a0fbfd
AP		 1640 /*
1641 * Cronyx Omega PCI (PLX-chip based)
1642 */
1643 {
1644 .vendor = PCI_VENDOR_ID_PLX,
1645 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1646 .subvendor = PCI_ANY_ID,
1647 .subdevice = PCI_ANY_ID,
1648 .setup = pci_omegapci_setup,
1649 },
1da177e4
LT		 1650 /*
1651 * Default "match everything" terminator entry
1652 */
1653 {
1654 .vendor = PCI_ANY_ID,
1655 .device = PCI_ANY_ID,
1656 .subvendor = PCI_ANY_ID,
1657 .subdevice = PCI_ANY_ID,
1658 .setup = pci_default_setup,
1659 }
1660};
1661
1662static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1663{
1664 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1665}
1666
1667static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1668{
1669 struct pci_serial_quirk *quirk;
1670
1671 for (quirk = pci_serial_quirks; ; quirk++)
1672 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1673 quirk_id_matches(quirk->device, dev->device) &&
1674 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1675 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 1676 break;
1da177e4
LT		 1677 return quirk;
1678}
1679
dd68e88c 1680static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 1681 const struct pciserial_board *board)
1da177e4
LT		 1682{
1683 if (board->flags & FL_NOIRQ)
1684 return 0;
1685 else
1686 return dev->irq;
1687}
1688
1689/*
1690 * This is the configuration table for all of the PCI serial boards
1691 * which we support. It is directly indexed by the pci_board_num_t enum
1692 * value, which is encoded in the pci_device_id PCI probe table's
1693 * driver_data member.
1694 *
1695 * The makeup of these names are:
26e92861 1696 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 1697 *
26e92861
GH		 1698 * bn = PCI BAR number
1699 * bt = Index using PCI BARs
1700 * n = number of serial ports
1701 * baud = baud rate
1702 * offsetinhex = offset for each sequential port (in hex)
1da177e4 1703 *
26e92861 1704 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 1705 *
1da177e4
LT		 1706 * Please note: in theory if n = 1, _bt infix should make no difference.
1707 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1708 */
1709enum pci_board_num_t {
1710 pbn_default = 0,
1711
1712 pbn_b0_1_115200,
1713 pbn_b0_2_115200,
1714 pbn_b0_4_115200,
1715 pbn_b0_5_115200,
bf0df636 1716 pbn_b0_8_115200,
1da177e4
LT		 1717
1718 pbn_b0_1_921600,
1719 pbn_b0_2_921600,
1720 pbn_b0_4_921600,
1721
db1de159
DR		 1722 pbn_b0_2_1130000,
1723
fbc0dc0d
AP		 1724 pbn_b0_4_1152000,
1725
26e92861
GH		 1726 pbn_b0_2_1843200,
1727 pbn_b0_4_1843200,
1728
1729 pbn_b0_2_1843200_200,
1730 pbn_b0_4_1843200_200,
1731 pbn_b0_8_1843200_200,
1732
7106b4e3
LH		 1733 pbn_b0_1_4000000,
1734
1da177e4
LT		 1735 pbn_b0_bt_1_115200,
1736 pbn_b0_bt_2_115200,
ac6ec5b1 1737 pbn_b0_bt_4_115200,
1da177e4
LT		 1738 pbn_b0_bt_8_115200,
1739
1740 pbn_b0_bt_1_460800,
1741 pbn_b0_bt_2_460800,
1742 pbn_b0_bt_4_460800,
1743
1744 pbn_b0_bt_1_921600,
1745 pbn_b0_bt_2_921600,
1746 pbn_b0_bt_4_921600,
1747 pbn_b0_bt_8_921600,
1748
1749 pbn_b1_1_115200,
1750 pbn_b1_2_115200,
1751 pbn_b1_4_115200,
1752 pbn_b1_8_115200,
04bf7e74 1753 pbn_b1_16_115200,
1da177e4
LT		 1754
1755 pbn_b1_1_921600,
1756 pbn_b1_2_921600,
1757 pbn_b1_4_921600,
1758 pbn_b1_8_921600,
1759
26e92861
GH		 1760 pbn_b1_2_1250000,
1761
84f8c6fc 1762 pbn_b1_bt_1_115200,
04bf7e74
WP		 1763 pbn_b1_bt_2_115200,
1764 pbn_b1_bt_4_115200,
1765
1da177e4
LT		 1766 pbn_b1_bt_2_921600,
1767
1768 pbn_b1_1_1382400,
1769 pbn_b1_2_1382400,
1770 pbn_b1_4_1382400,
1771 pbn_b1_8_1382400,
1772
1773 pbn_b2_1_115200,
737c1756 1774 pbn_b2_2_115200,
a9cccd34 1775 pbn_b2_4_115200,
1da177e4
LT		 1776 pbn_b2_8_115200,
1777
1778 pbn_b2_1_460800,
1779 pbn_b2_4_460800,
1780 pbn_b2_8_460800,
1781 pbn_b2_16_460800,
1782
1783 pbn_b2_1_921600,
1784 pbn_b2_4_921600,
1785 pbn_b2_8_921600,
1786
e847003f
LB		 1787 pbn_b2_8_1152000,
1788
1da177e4
LT		 1789 pbn_b2_bt_1_115200,
1790 pbn_b2_bt_2_115200,
1791 pbn_b2_bt_4_115200,
1792
1793 pbn_b2_bt_2_921600,
1794 pbn_b2_bt_4_921600,
1795
d9004eb4 1796 pbn_b3_2_115200,
1da177e4
LT		 1797 pbn_b3_4_115200,
1798 pbn_b3_8_115200,
1799
66169ad1
YY		 1800 pbn_b4_bt_2_921600,
1801 pbn_b4_bt_4_921600,
1802 pbn_b4_bt_8_921600,
1803
1da177e4
LT		 1804 /*
1805 * Board-specific versions.
1806 */
1807 pbn_panacom,
1808 pbn_panacom2,
1809 pbn_panacom4,
add7b58e 1810 pbn_exsys_4055,
1da177e4
LT		 1811 pbn_plx_romulus,
1812 pbn_oxsemi,
7106b4e3
LH		 1813 pbn_oxsemi_1_4000000,
1814 pbn_oxsemi_2_4000000,
1815 pbn_oxsemi_4_4000000,
1816 pbn_oxsemi_8_4000000,
1da177e4
LT		 1817 pbn_intel_i960,
1818 pbn_sgi_ioc3,
1da177e4
LT		 1819 pbn_computone_4,
1820 pbn_computone_6,
1821 pbn_computone_8,
1822 pbn_sbsxrsio,
1823 pbn_exar_XR17C152,
1824 pbn_exar_XR17C154,
1825 pbn_exar_XR17C158,
c68d2b15 1826 pbn_exar_ibm_saturn,
aa798505 1827 pbn_pasemi_1682M,
46a0fac9
SB		 1828 pbn_ni8430_2,
1829 pbn_ni8430_4,
1830 pbn_ni8430_8,
1831 pbn_ni8430_16,
1b62cbf2
KJ		 1832 pbn_ADDIDATA_PCIe_1_3906250,
1833 pbn_ADDIDATA_PCIe_2_3906250,
1834 pbn_ADDIDATA_PCIe_4_3906250,
1835 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 1836 pbn_ce4100_1_115200,
d9a0fbfd 1837 pbn_omegapci,
7808edcd 1838 pbn_NETMOS9900_2s_115200,
1da177e4
LT		 1839};
1840
1841/*
1842 * uart_offset - the space between channels
1843 * reg_shift - describes how the UART registers are mapped
1844 * to PCI memory by the card.
1845 * For example IER register on SBS, Inc. PMC-OctPro is located at
1846 * offset 0x10 from the UART base, while UART_IER is defined as 1
1847 * in include/linux/serial_reg.h,
1848 * see first lines of serial_in() and serial_out() in 8250.c
1849*/
1850
1c7c1fe5 1851static struct pciserial_board pci_boards[] __devinitdata = {
1da177e4
LT		 1852 [pbn_default] = {
1853 .flags = FL_BASE0,
1854 .num_ports = 1,
1855 .base_baud = 115200,
1856 .uart_offset = 8,
1857 },
1858 [pbn_b0_1_115200] = {
1859 .flags = FL_BASE0,
1860 .num_ports = 1,
1861 .base_baud = 115200,
1862 .uart_offset = 8,
1863 },
1864 [pbn_b0_2_115200] = {
1865 .flags = FL_BASE0,
1866 .num_ports = 2,
1867 .base_baud = 115200,
1868 .uart_offset = 8,
1869 },
1870 [pbn_b0_4_115200] = {
1871 .flags = FL_BASE0,
1872 .num_ports = 4,
1873 .base_baud = 115200,
1874 .uart_offset = 8,
1875 },
1876 [pbn_b0_5_115200] = {
1877 .flags = FL_BASE0,
1878 .num_ports = 5,
1879 .base_baud = 115200,
1880 .uart_offset = 8,
1881 },
bf0df636
AC		 1882 [pbn_b0_8_115200] = {
1883 .flags = FL_BASE0,
1884 .num_ports = 8,
1885 .base_baud = 115200,
1886 .uart_offset = 8,
1887 },
1da177e4
LT		 1888 [pbn_b0_1_921600] = {
1889 .flags = FL_BASE0,
1890 .num_ports = 1,
1891 .base_baud = 921600,
1892 .uart_offset = 8,
1893 },
1894 [pbn_b0_2_921600] = {
1895 .flags = FL_BASE0,
1896 .num_ports = 2,
1897 .base_baud = 921600,
1898 .uart_offset = 8,
1899 },
1900 [pbn_b0_4_921600] = {
1901 .flags = FL_BASE0,
1902 .num_ports = 4,
1903 .base_baud = 921600,
1904 .uart_offset = 8,
1905 },
db1de159
DR		 1906
1907 [pbn_b0_2_1130000] = {
1908 .flags = FL_BASE0,
1909 .num_ports = 2,
1910 .base_baud = 1130000,
1911 .uart_offset = 8,
1912 },
1913
fbc0dc0d
AP		 1914 [pbn_b0_4_1152000] = {
1915 .flags = FL_BASE0,
1916 .num_ports = 4,
1917 .base_baud = 1152000,
1918 .uart_offset = 8,
1919 },
1da177e4 1920
26e92861
GH		 1921 [pbn_b0_2_1843200] = {
1922 .flags = FL_BASE0,
1923 .num_ports = 2,
1924 .base_baud = 1843200,
1925 .uart_offset = 8,
1926 },
1927 [pbn_b0_4_1843200] = {
1928 .flags = FL_BASE0,
1929 .num_ports = 4,
1930 .base_baud = 1843200,
1931 .uart_offset = 8,
1932 },
1933
1934 [pbn_b0_2_1843200_200] = {
1935 .flags = FL_BASE0,
1936 .num_ports = 2,
1937 .base_baud = 1843200,
1938 .uart_offset = 0x200,
1939 },
1940 [pbn_b0_4_1843200_200] = {
1941 .flags = FL_BASE0,
1942 .num_ports = 4,
1943 .base_baud = 1843200,
1944 .uart_offset = 0x200,
1945 },
1946 [pbn_b0_8_1843200_200] = {
1947 .flags = FL_BASE0,
1948 .num_ports = 8,
1949 .base_baud = 1843200,
1950 .uart_offset = 0x200,
1951 },
7106b4e3
LH		 1952 [pbn_b0_1_4000000] = {
1953 .flags = FL_BASE0,
1954 .num_ports = 1,
1955 .base_baud = 4000000,
1956 .uart_offset = 8,
1957 },
26e92861 1958
1da177e4
LT		 1959 [pbn_b0_bt_1_115200] = {
1960 .flags = FL_BASE0|FL_BASE_BARS,
1961 .num_ports = 1,
1962 .base_baud = 115200,
1963 .uart_offset = 8,
1964 },
1965 [pbn_b0_bt_2_115200] = {
1966 .flags = FL_BASE0|FL_BASE_BARS,
1967 .num_ports = 2,
1968 .base_baud = 115200,
1969 .uart_offset = 8,
1970 },
ac6ec5b1
IS		 1971 [pbn_b0_bt_4_115200] = {
1972 .flags = FL_BASE0|FL_BASE_BARS,
1973 .num_ports = 4,
1974 .base_baud = 115200,
1975 .uart_offset = 8,
1976 },
1da177e4
LT		 1977 [pbn_b0_bt_8_115200] = {
1978 .flags = FL_BASE0|FL_BASE_BARS,
1979 .num_ports = 8,
1980 .base_baud = 115200,
1981 .uart_offset = 8,
1982 },
1983
1984 [pbn_b0_bt_1_460800] = {
1985 .flags = FL_BASE0|FL_BASE_BARS,
1986 .num_ports = 1,
1987 .base_baud = 460800,
1988 .uart_offset = 8,
1989 },
1990 [pbn_b0_bt_2_460800] = {
1991 .flags = FL_BASE0|FL_BASE_BARS,
1992 .num_ports = 2,
1993 .base_baud = 460800,
1994 .uart_offset = 8,
1995 },
1996 [pbn_b0_bt_4_460800] = {
1997 .flags = FL_BASE0|FL_BASE_BARS,
1998 .num_ports = 4,
1999 .base_baud = 460800,
2000 .uart_offset = 8,
2001 },
2002
2003 [pbn_b0_bt_1_921600] = {
2004 .flags = FL_BASE0|FL_BASE_BARS,
2005 .num_ports = 1,
2006 .base_baud = 921600,
2007 .uart_offset = 8,
2008 },
2009 [pbn_b0_bt_2_921600] = {
2010 .flags = FL_BASE0|FL_BASE_BARS,
2011 .num_ports = 2,
2012 .base_baud = 921600,
2013 .uart_offset = 8,
2014 },
2015 [pbn_b0_bt_4_921600] = {
2016 .flags = FL_BASE0|FL_BASE_BARS,
2017 .num_ports = 4,
2018 .base_baud = 921600,
2019 .uart_offset = 8,
2020 },
2021 [pbn_b0_bt_8_921600] = {
2022 .flags = FL_BASE0|FL_BASE_BARS,
2023 .num_ports = 8,
2024 .base_baud = 921600,
2025 .uart_offset = 8,
2026 },
2027
2028 [pbn_b1_1_115200] = {
2029 .flags = FL_BASE1,
2030 .num_ports = 1,
2031 .base_baud = 115200,
2032 .uart_offset = 8,
2033 },
2034 [pbn_b1_2_115200] = {
2035 .flags = FL_BASE1,
2036 .num_ports = 2,
2037 .base_baud = 115200,
2038 .uart_offset = 8,
2039 },
2040 [pbn_b1_4_115200] = {
2041 .flags = FL_BASE1,
2042 .num_ports = 4,
2043 .base_baud = 115200,
2044 .uart_offset = 8,
2045 },
2046 [pbn_b1_8_115200] = {
2047 .flags = FL_BASE1,
2048 .num_ports = 8,
2049 .base_baud = 115200,
2050 .uart_offset = 8,
2051 },
04bf7e74
WP		 2052 [pbn_b1_16_115200] = {
2053 .flags = FL_BASE1,
2054 .num_ports = 16,
2055 .base_baud = 115200,
2056 .uart_offset = 8,
2057 },
1da177e4
LT		 2058
2059 [pbn_b1_1_921600] = {
2060 .flags = FL_BASE1,
2061 .num_ports = 1,
2062 .base_baud = 921600,
2063 .uart_offset = 8,
2064 },
2065 [pbn_b1_2_921600] = {
2066 .flags = FL_BASE1,
2067 .num_ports = 2,
2068 .base_baud = 921600,
2069 .uart_offset = 8,
2070 },
2071 [pbn_b1_4_921600] = {
2072 .flags = FL_BASE1,
2073 .num_ports = 4,
2074 .base_baud = 921600,
2075 .uart_offset = 8,
2076 },
2077 [pbn_b1_8_921600] = {
2078 .flags = FL_BASE1,
2079 .num_ports = 8,
2080 .base_baud = 921600,
2081 .uart_offset = 8,
2082 },
26e92861
GH		 2083 [pbn_b1_2_1250000] = {
2084 .flags = FL_BASE1,
2085 .num_ports = 2,
2086 .base_baud = 1250000,
2087 .uart_offset = 8,
2088 },
1da177e4 2089
84f8c6fc
NV		 2090 [pbn_b1_bt_1_115200] = {
2091 .flags = FL_BASE1|FL_BASE_BARS,
2092 .num_ports = 1,
2093 .base_baud = 115200,
2094 .uart_offset = 8,
2095 },
04bf7e74
WP		 2096 [pbn_b1_bt_2_115200] = {
2097 .flags = FL_BASE1|FL_BASE_BARS,
2098 .num_ports = 2,
2099 .base_baud = 115200,
2100 .uart_offset = 8,
2101 },
2102 [pbn_b1_bt_4_115200] = {
2103 .flags = FL_BASE1|FL_BASE_BARS,
2104 .num_ports = 4,
2105 .base_baud = 115200,
2106 .uart_offset = 8,
2107 },
84f8c6fc 2108
1da177e4
LT		 2109 [pbn_b1_bt_2_921600] = {
2110 .flags = FL_BASE1|FL_BASE_BARS,
2111 .num_ports = 2,
2112 .base_baud = 921600,
2113 .uart_offset = 8,
2114 },
2115
2116 [pbn_b1_1_1382400] = {
2117 .flags = FL_BASE1,
2118 .num_ports = 1,
2119 .base_baud = 1382400,
2120 .uart_offset = 8,
2121 },
2122 [pbn_b1_2_1382400] = {
2123 .flags = FL_BASE1,
2124 .num_ports = 2,
2125 .base_baud = 1382400,
2126 .uart_offset = 8,
2127 },
2128 [pbn_b1_4_1382400] = {
2129 .flags = FL_BASE1,
2130 .num_ports = 4,
2131 .base_baud = 1382400,
2132 .uart_offset = 8,
2133 },
2134 [pbn_b1_8_1382400] = {
2135 .flags = FL_BASE1,
2136 .num_ports = 8,
2137 .base_baud = 1382400,
2138 .uart_offset = 8,
2139 },
2140
2141 [pbn_b2_1_115200] = {
2142 .flags = FL_BASE2,
2143 .num_ports = 1,
2144 .base_baud = 115200,
2145 .uart_offset = 8,
2146 },
737c1756
PH		 2147 [pbn_b2_2_115200] = {
2148 .flags = FL_BASE2,
2149 .num_ports = 2,
2150 .base_baud = 115200,
2151 .uart_offset = 8,
2152 },
a9cccd34
MF		 2153 [pbn_b2_4_115200] = {
2154 .flags = FL_BASE2,
2155 .num_ports = 4,
2156 .base_baud = 115200,
2157 .uart_offset = 8,
2158 },
1da177e4
LT		 2159 [pbn_b2_8_115200] = {
2160 .flags = FL_BASE2,
2161 .num_ports = 8,
2162 .base_baud = 115200,
2163 .uart_offset = 8,
2164 },
2165
2166 [pbn_b2_1_460800] = {
2167 .flags = FL_BASE2,
2168 .num_ports = 1,
2169 .base_baud = 460800,
2170 .uart_offset = 8,
2171 },
2172 [pbn_b2_4_460800] = {
2173 .flags = FL_BASE2,
2174 .num_ports = 4,
2175 .base_baud = 460800,
2176 .uart_offset = 8,
2177 },
2178 [pbn_b2_8_460800] = {
2179 .flags = FL_BASE2,
2180 .num_ports = 8,
2181 .base_baud = 460800,
2182 .uart_offset = 8,
2183 },
2184 [pbn_b2_16_460800] = {
2185 .flags = FL_BASE2,
2186 .num_ports = 16,
2187 .base_baud = 460800,
2188 .uart_offset = 8,
2189 },
2190
2191 [pbn_b2_1_921600] = {
2192 .flags = FL_BASE2,
2193 .num_ports = 1,
2194 .base_baud = 921600,
2195 .uart_offset = 8,
2196 },
2197 [pbn_b2_4_921600] = {
2198 .flags = FL_BASE2,
2199 .num_ports = 4,
2200 .base_baud = 921600,
2201 .uart_offset = 8,
2202 },
2203 [pbn_b2_8_921600] = {
2204 .flags = FL_BASE2,
2205 .num_ports = 8,
2206 .base_baud = 921600,
2207 .uart_offset = 8,
2208 },
2209
e847003f
LB		 2210 [pbn_b2_8_1152000] = {
2211 .flags = FL_BASE2,
2212 .num_ports = 8,
2213 .base_baud = 1152000,
2214 .uart_offset = 8,
2215 },
2216
1da177e4
LT		 2217 [pbn_b2_bt_1_115200] = {
2218 .flags = FL_BASE2|FL_BASE_BARS,
2219 .num_ports = 1,
2220 .base_baud = 115200,
2221 .uart_offset = 8,
2222 },
2223 [pbn_b2_bt_2_115200] = {
2224 .flags = FL_BASE2|FL_BASE_BARS,
2225 .num_ports = 2,
2226 .base_baud = 115200,
2227 .uart_offset = 8,
2228 },
2229 [pbn_b2_bt_4_115200] = {
2230 .flags = FL_BASE2|FL_BASE_BARS,
2231 .num_ports = 4,
2232 .base_baud = 115200,
2233 .uart_offset = 8,
2234 },
2235
2236 [pbn_b2_bt_2_921600] = {
2237 .flags = FL_BASE2|FL_BASE_BARS,
2238 .num_ports = 2,
2239 .base_baud = 921600,
2240 .uart_offset = 8,
2241 },
2242 [pbn_b2_bt_4_921600] = {
2243 .flags = FL_BASE2|FL_BASE_BARS,
2244 .num_ports = 4,
2245 .base_baud = 921600,
2246 .uart_offset = 8,
2247 },
2248
d9004eb4
ABL		 2249 [pbn_b3_2_115200] = {
2250 .flags = FL_BASE3,
2251 .num_ports = 2,
2252 .base_baud = 115200,
2253 .uart_offset = 8,
2254 },
1da177e4
LT		 2255 [pbn_b3_4_115200] = {
2256 .flags = FL_BASE3,
2257 .num_ports = 4,
2258 .base_baud = 115200,
2259 .uart_offset = 8,
2260 },
2261 [pbn_b3_8_115200] = {
2262 .flags = FL_BASE3,
2263 .num_ports = 8,
2264 .base_baud = 115200,
2265 .uart_offset = 8,
2266 },
2267
66169ad1
YY		 2268 [pbn_b4_bt_2_921600] = {
2269 .flags = FL_BASE4,
2270 .num_ports = 2,
2271 .base_baud = 921600,
2272 .uart_offset = 8,
2273 },
2274 [pbn_b4_bt_4_921600] = {
2275 .flags = FL_BASE4,
2276 .num_ports = 4,
2277 .base_baud = 921600,
2278 .uart_offset = 8,
2279 },
2280 [pbn_b4_bt_8_921600] = {
2281 .flags = FL_BASE4,
2282 .num_ports = 8,
2283 .base_baud = 921600,
2284 .uart_offset = 8,
2285 },
2286
1da177e4
LT		 2287 /*
2288 * Entries following this are board-specific.
2289 */
2290
2291 /*
2292 * Panacom - IOMEM
2293 */
2294 [pbn_panacom] = {
2295 .flags = FL_BASE2,
2296 .num_ports = 2,
2297 .base_baud = 921600,
2298 .uart_offset = 0x400,
2299 .reg_shift = 7,
2300 },
2301 [pbn_panacom2] = {
2302 .flags = FL_BASE2|FL_BASE_BARS,
2303 .num_ports = 2,
2304 .base_baud = 921600,
2305 .uart_offset = 0x400,
2306 .reg_shift = 7,
2307 },
2308 [pbn_panacom4] = {
2309 .flags = FL_BASE2|FL_BASE_BARS,
2310 .num_ports = 4,
2311 .base_baud = 921600,
2312 .uart_offset = 0x400,
2313 .reg_shift = 7,
2314 },
2315
add7b58e
BH		 2316 [pbn_exsys_4055] = {
2317 .flags = FL_BASE2,
2318 .num_ports = 4,
2319 .base_baud = 115200,
2320 .uart_offset = 8,
2321 },
2322
1da177e4
LT		 2323 /* I think this entry is broken - the first_offset looks wrong --rmk */
2324 [pbn_plx_romulus] = {
2325 .flags = FL_BASE2,
2326 .num_ports = 4,
2327 .base_baud = 921600,
2328 .uart_offset = 8 << 2,
2329 .reg_shift = 2,
2330 .first_offset = 0x03,
2331 },
2332
2333 /*
2334 * This board uses the size of PCI Base region 0 to
2335 * signal now many ports are available
2336 */
2337 [pbn_oxsemi] = {
2338 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2339 .num_ports = 32,
2340 .base_baud = 115200,
2341 .uart_offset = 8,
2342 },
7106b4e3
LH		 2343 [pbn_oxsemi_1_4000000] = {
2344 .flags = FL_BASE0,
2345 .num_ports = 1,
2346 .base_baud = 4000000,
2347 .uart_offset = 0x200,
2348 .first_offset = 0x1000,
2349 },
2350 [pbn_oxsemi_2_4000000] = {
2351 .flags = FL_BASE0,
2352 .num_ports = 2,
2353 .base_baud = 4000000,
2354 .uart_offset = 0x200,
2355 .first_offset = 0x1000,
2356 },
2357 [pbn_oxsemi_4_4000000] = {
2358 .flags = FL_BASE0,
2359 .num_ports = 4,
2360 .base_baud = 4000000,
2361 .uart_offset = 0x200,
2362 .first_offset = 0x1000,
2363 },
2364 [pbn_oxsemi_8_4000000] = {
2365 .flags = FL_BASE0,
2366 .num_ports = 8,
2367 .base_baud = 4000000,
2368 .uart_offset = 0x200,
2369 .first_offset = 0x1000,
2370 },
2371
1da177e4
LT		 2372
2373 /*
2374 * EKF addition for i960 Boards form EKF with serial port.
2375 * Max 256 ports.
2376 */
2377 [pbn_intel_i960] = {
2378 .flags = FL_BASE0,
2379 .num_ports = 32,
2380 .base_baud = 921600,
2381 .uart_offset = 8 << 2,
2382 .reg_shift = 2,
2383 .first_offset = 0x10000,
2384 },
2385 [pbn_sgi_ioc3] = {
2386 .flags = FL_BASE0|FL_NOIRQ,
2387 .num_ports = 1,
2388 .base_baud = 458333,
2389 .uart_offset = 8,
2390 .reg_shift = 0,
2391 .first_offset = 0x20178,
2392 },
2393
1da177e4
LT		 2394 /*
2395 * Computone - uses IOMEM.
2396 */
2397 [pbn_computone_4] = {
2398 .flags = FL_BASE0,
2399 .num_ports = 4,
2400 .base_baud = 921600,
2401 .uart_offset = 0x40,
2402 .reg_shift = 2,
2403 .first_offset = 0x200,
2404 },
2405 [pbn_computone_6] = {
2406 .flags = FL_BASE0,
2407 .num_ports = 6,
2408 .base_baud = 921600,
2409 .uart_offset = 0x40,
2410 .reg_shift = 2,
2411 .first_offset = 0x200,
2412 },
2413 [pbn_computone_8] = {
2414 .flags = FL_BASE0,
2415 .num_ports = 8,
2416 .base_baud = 921600,
2417 .uart_offset = 0x40,
2418 .reg_shift = 2,
2419 .first_offset = 0x200,
2420 },
2421 [pbn_sbsxrsio] = {
2422 .flags = FL_BASE0,
2423 .num_ports = 8,
2424 .base_baud = 460800,
2425 .uart_offset = 256,
2426 .reg_shift = 4,
2427 },
2428 /*
2429 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2430 * Only basic 16550A support.
2431 * XR17C15[24] are not tested, but they should work.
2432 */
2433 [pbn_exar_XR17C152] = {
2434 .flags = FL_BASE0,
2435 .num_ports = 2,
2436 .base_baud = 921600,
2437 .uart_offset = 0x200,
2438 },
2439 [pbn_exar_XR17C154] = {
2440 .flags = FL_BASE0,
2441 .num_ports = 4,
2442 .base_baud = 921600,
2443 .uart_offset = 0x200,
2444 },
2445 [pbn_exar_XR17C158] = {
2446 .flags = FL_BASE0,
2447 .num_ports = 8,
2448 .base_baud = 921600,
2449 .uart_offset = 0x200,
2450 },
c68d2b15
BH		 2451 [pbn_exar_ibm_saturn] = {
2452 .flags = FL_BASE0,
2453 .num_ports = 1,
2454 .base_baud = 921600,
2455 .uart_offset = 0x200,
2456 },
2457
aa798505
OJ		 2458 /*
2459 * PA Semi PWRficient PA6T-1682M on-chip UART
2460 */
2461 [pbn_pasemi_1682M] = {
2462 .flags = FL_BASE0,
2463 .num_ports = 1,
2464 .base_baud = 8333333,
2465 },
46a0fac9
SB		 2466 /*
2467 * National Instruments 843x
2468 */
2469 [pbn_ni8430_16] = {
2470 .flags = FL_BASE0,
2471 .num_ports = 16,
2472 .base_baud = 3686400,
2473 .uart_offset = 0x10,
2474 .first_offset = 0x800,
2475 },
2476 [pbn_ni8430_8] = {
2477 .flags = FL_BASE0,
2478 .num_ports = 8,
2479 .base_baud = 3686400,
2480 .uart_offset = 0x10,
2481 .first_offset = 0x800,
2482 },
2483 [pbn_ni8430_4] = {
2484 .flags = FL_BASE0,
2485 .num_ports = 4,
2486 .base_baud = 3686400,
2487 .uart_offset = 0x10,
2488 .first_offset = 0x800,
2489 },
2490 [pbn_ni8430_2] = {
2491 .flags = FL_BASE0,
2492 .num_ports = 2,
2493 .base_baud = 3686400,
2494 .uart_offset = 0x10,
2495 .first_offset = 0x800,
2496 },
1b62cbf2
KJ		 2497 /*
2498 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2499 */
2500 [pbn_ADDIDATA_PCIe_1_3906250] = {
2501 .flags = FL_BASE0,
2502 .num_ports = 1,
2503 .base_baud = 3906250,
2504 .uart_offset = 0x200,
2505 .first_offset = 0x1000,
2506 },
2507 [pbn_ADDIDATA_PCIe_2_3906250] = {
2508 .flags = FL_BASE0,
2509 .num_ports = 2,
2510 .base_baud = 3906250,
2511 .uart_offset = 0x200,
2512 .first_offset = 0x1000,
2513 },
2514 [pbn_ADDIDATA_PCIe_4_3906250] = {
2515 .flags = FL_BASE0,
2516 .num_ports = 4,
2517 .base_baud = 3906250,
2518 .uart_offset = 0x200,
2519 .first_offset = 0x1000,
2520 },
2521 [pbn_ADDIDATA_PCIe_8_3906250] = {
2522 .flags = FL_BASE0,
2523 .num_ports = 8,
2524 .base_baud = 3906250,
2525 .uart_offset = 0x200,
2526 .first_offset = 0x1000,
2527 },
095e24b0
DB		 2528 [pbn_ce4100_1_115200] = {
2529 .flags = FL_BASE0,
2530 .num_ports = 1,
2531 .base_baud = 921600,
2532 .reg_shift = 2,
2533 },
d9a0fbfd
AP		 2534 [pbn_omegapci] = {
2535 .flags = FL_BASE0,
2536 .num_ports = 8,
2537 .base_baud = 115200,
2538 .uart_offset = 0x200,
2539 },
7808edcd
NG		 2540 [pbn_NETMOS9900_2s_115200] = {
2541 .flags = FL_BASE0,
2542 .num_ports = 2,
2543 .base_baud = 115200,
2544 },
1da177e4
LT		 2545};
2546
436bbd43 2547static const struct pci_device_id softmodem_blacklist[] = {
5756ee99 2548 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 2549 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2550 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
436bbd43
CS		 2551};
2552
1da177e4
LT		 2553/*
2554 * Given a complete unknown PCI device, try to use some heuristics to
2555 * guess what the configuration might be, based on the pitiful PCI
2556 * serial specs. Returns 0 on success, 1 on failure.
2557 */
2558static int __devinit
1c7c1fe5 2559serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 2560{
436bbd43 2561 const struct pci_device_id *blacklist;
1da177e4 2562 int num_iomem, num_port, first_port = -1, i;
5756ee99 2563
1da177e4
LT		 2564 /*
2565 * If it is not a communications device or the programming
2566 * interface is greater than 6, give up.
2567 *
2568 * (Should we try to make guesses for multiport serial devices
5756ee99 2569 * later?)
1da177e4
LT		 2570 */
2571 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2572 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2573 (dev->class & 0xff) > 6)
2574 return -ENODEV;
2575
436bbd43
CS		 2576 /*
2577 * Do not access blacklisted devices that are known not to
2578 * feature serial ports.
2579 */
2580 for (blacklist = softmodem_blacklist;
2581 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2582 blacklist++) {
2583 if (dev->vendor == blacklist->vendor &&
2584 dev->device == blacklist->device)
2585 return -ENODEV;
2586 }
2587
1da177e4
LT		 2588 num_iomem = num_port = 0;
2589 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2590 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2591 num_port++;
2592 if (first_port == -1)
2593 first_port = i;
2594 }
2595 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2596 num_iomem++;
2597 }
2598
2599 /*
2600 * If there is 1 or 0 iomem regions, and exactly one port,
2601 * use it. We guess the number of ports based on the IO
2602 * region size.
2603 */
2604 if (num_iomem <= 1 && num_port == 1) {
2605 board->flags = first_port;
2606 board->num_ports = pci_resource_len(dev, first_port) / 8;
2607 return 0;
2608 }
2609
2610 /*
2611 * Now guess if we've got a board which indexes by BARs.
2612 * Each IO BAR should be 8 bytes, and they should follow
2613 * consecutively.
2614 */
2615 first_port = -1;
2616 num_port = 0;
2617 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2618 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2619 pci_resource_len(dev, i) == 8 &&
2620 (first_port == -1 || (first_port + num_port) == i)) {
2621 num_port++;
2622 if (first_port == -1)
2623 first_port = i;
2624 }
2625 }
2626
2627 if (num_port > 1) {
2628 board->flags = first_port | FL_BASE_BARS;
2629 board->num_ports = num_port;
2630 return 0;
2631 }
2632
2633 return -ENODEV;
2634}
2635
2636static inline int
975a1a7d
RK		 2637serial_pci_matches(const struct pciserial_board *board,
2638 const struct pciserial_board *guessed)
1da177e4
LT		 2639{
2640 return
2641 board->num_ports == guessed->num_ports &&
2642 board->base_baud == guessed->base_baud &&
2643 board->uart_offset == guessed->uart_offset &&
2644 board->reg_shift == guessed->reg_shift &&
2645 board->first_offset == guessed->first_offset;
2646}
2647
241fc436 2648struct serial_private *
975a1a7d 2649pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 2650{
72ce9a83 2651 struct uart_port serial_port;
1da177e4 2652 struct serial_private *priv;
1da177e4
LT		 2653 struct pci_serial_quirk *quirk;
2654 int rc, nr_ports, i;
2655
1da177e4
LT		 2656 nr_ports = board->num_ports;
2657
2658 /*
2659 * Find an init and setup quirks.
2660 */
2661 quirk = find_quirk(dev);
2662
2663 /*
2664 * Run the new-style initialization function.
2665 * The initialization function returns:
2666 * <0 - error
2667 * 0 - use board->num_ports
2668 * >0 - number of ports
2669 */
2670 if (quirk->init) {
2671 rc = quirk->init(dev);
241fc436
RK		 2672 if (rc < 0) {
2673 priv = ERR_PTR(rc);
2674 goto err_out;
2675 }
1da177e4
LT		 2676 if (rc)
2677 nr_ports = rc;
2678 }
2679
8f31bb39 2680 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 2681 sizeof(unsigned int) * nr_ports,
2682 GFP_KERNEL);
2683 if (!priv) {
241fc436
RK		 2684 priv = ERR_PTR(-ENOMEM);
2685 goto err_deinit;
1da177e4
LT		 2686 }
2687
70db3d91 2688 priv->dev = dev;
1da177e4 2689 priv->quirk = quirk;
1da177e4 2690
72ce9a83
RK		 2691 memset(&serial_port, 0, sizeof(struct uart_port));
2692 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2693 serial_port.uartclk = board->base_baud * 16;
2694 serial_port.irq = get_pci_irq(dev, board);
2695 serial_port.dev = &dev->dev;
2696
1da177e4 2697 for (i = 0; i < nr_ports; i++) {
70db3d91 2698 if (quirk->setup(priv, board, &serial_port, i))
1da177e4 2699 break;
72ce9a83 2700
1da177e4 2701#ifdef SERIAL_DEBUG_PCI
80647b95 2702 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
1da177e4
LT		 2703 serial_port.iobase, serial_port.irq, serial_port.iotype);
2704#endif
5756ee99 2705
1da177e4
LT		 2706 priv->line[i] = serial8250_register_port(&serial_port);
2707 if (priv->line[i] < 0) {
2708 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2709 break;
2710 }
2711 }
1da177e4 2712 priv->nr = i;
241fc436 2713 return priv;
1da177e4 2714
5756ee99 2715err_deinit:
1da177e4
LT		 2716 if (quirk->exit)
2717 quirk->exit(dev);
5756ee99 2718err_out:
241fc436 2719 return priv;
1da177e4 2720}
241fc436 2721EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 2722
241fc436 2723void pciserial_remove_ports(struct serial_private *priv)
1da177e4 2724{
056a8763
RK		 2725 struct pci_serial_quirk *quirk;
2726 int i;
1da177e4 2727
056a8763
RK		 2728 for (i = 0; i < priv->nr; i++)
2729 serial8250_unregister_port(priv->line[i]);
1da177e4 2730
056a8763
RK		 2731 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2732 if (priv->remapped_bar[i])
2733 iounmap(priv->remapped_bar[i]);
2734 priv->remapped_bar[i] = NULL;
2735 }
1da177e4 2736
056a8763
RK		 2737 /*
2738 * Find the exit quirks.
2739 */
241fc436 2740 quirk = find_quirk(priv->dev);
056a8763 2741 if (quirk->exit)
241fc436
RK		 2742 quirk->exit(priv->dev);
2743
2744 kfree(priv);
2745}
2746EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2747
2748void pciserial_suspend_ports(struct serial_private *priv)
2749{
2750 int i;
2751
2752 for (i = 0; i < priv->nr; i++)
2753 if (priv->line[i] >= 0)
2754 serial8250_suspend_port(priv->line[i]);
2755}
2756EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2757
2758void pciserial_resume_ports(struct serial_private *priv)
2759{
2760 int i;
2761
2762 /*
2763 * Ensure that the board is correctly configured.
2764 */
2765 if (priv->quirk->init)
2766 priv->quirk->init(priv->dev);
2767
2768 for (i = 0; i < priv->nr; i++)
2769 if (priv->line[i] >= 0)
2770 serial8250_resume_port(priv->line[i]);
2771}
2772EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2773
2774/*
2775 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2776 * to the arrangement of serial ports on a PCI card.
2777 */
2778static int __devinit
2779pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2780{
5bf8f501 2781 struct pci_serial_quirk *quirk;
241fc436 2782 struct serial_private *priv;
975a1a7d
RK		 2783 const struct pciserial_board *board;
2784 struct pciserial_board tmp;
241fc436
RK		 2785 int rc;
2786
5bf8f501
FB		 2787 quirk = find_quirk(dev);
2788 if (quirk->probe) {
2789 rc = quirk->probe(dev);
2790 if (rc)
2791 return rc;
2792 }
2793
241fc436
RK		 2794 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2795 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2796 ent->driver_data);
2797 return -EINVAL;
2798 }
2799
2800 board = &pci_boards[ent->driver_data];
2801
2802 rc = pci_enable_device(dev);
2807190b 2803 pci_save_state(dev);
241fc436
RK		 2804 if (rc)
2805 return rc;
2806
2807 if (ent->driver_data == pbn_default) {
2808 /*
2809 * Use a copy of the pci_board entry for this;
2810 * avoid changing entries in the table.
2811 */
2812 memcpy(&tmp, board, sizeof(struct pciserial_board));
2813 board = &tmp;
2814
2815 /*
2816 * We matched one of our class entries. Try to
2817 * determine the parameters of this board.
2818 */
975a1a7d 2819 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 2820 if (rc)
2821 goto disable;
2822 } else {
2823 /*
2824 * We matched an explicit entry. If we are able to
2825 * detect this boards settings with our heuristic,
2826 * then we no longer need this entry.
2827 */
2828 memcpy(&tmp, &pci_boards[pbn_default],
2829 sizeof(struct pciserial_board));
2830 rc = serial_pci_guess_board(dev, &tmp);
2831 if (rc == 0 && serial_pci_matches(board, &tmp))
2832 moan_device("Redundant entry in serial pci_table.",
2833 dev);
2834 }
2835
2836 priv = pciserial_init_ports(dev, board);
2837 if (!IS_ERR(priv)) {
2838 pci_set_drvdata(dev, priv);
2839 return 0;
2840 }
2841
2842 rc = PTR_ERR(priv);
1da177e4 2843
241fc436 2844 disable:
056a8763 2845 pci_disable_device(dev);
241fc436
RK		 2846 return rc;
2847}
1da177e4 2848
241fc436
RK		 2849static void __devexit pciserial_remove_one(struct pci_dev *dev)
2850{
2851 struct serial_private *priv = pci_get_drvdata(dev);
2852
2853 pci_set_drvdata(dev, NULL);
2854
2855 pciserial_remove_ports(priv);
2856
2857 pci_disable_device(dev);
1da177e4
LT		 2858}
2859
1d5e7996 2860#ifdef CONFIG_PM
1da177e4
LT		 2861static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2862{
2863 struct serial_private *priv = pci_get_drvdata(dev);
2864
241fc436
RK		 2865 if (priv)
2866 pciserial_suspend_ports(priv);
1da177e4 2867
1da177e4
LT		 2868 pci_save_state(dev);
2869 pci_set_power_state(dev, pci_choose_state(dev, state));
2870 return 0;
2871}
2872
2873static int pciserial_resume_one(struct pci_dev *dev)
2874{
ccb9d59e 2875 int err;
1da177e4
LT		 2876 struct serial_private *priv = pci_get_drvdata(dev);
2877
2878 pci_set_power_state(dev, PCI_D0);
2879 pci_restore_state(dev);
2880
2881 if (priv) {
1da177e4
LT		 2882 /*
2883 * The device may have been disabled. Re-enable it.
2884 */
ccb9d59e 2885 err = pci_enable_device(dev);
40836c48 2886 /* FIXME: We cannot simply error out here */
ccb9d59e 2887 if (err)
40836c48 2888 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
241fc436 2889 pciserial_resume_ports(priv);
1da177e4
LT		 2890 }
2891 return 0;
2892}
1d5e7996 2893#endif
1da177e4
LT		 2894
2895static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 2896 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2897 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2898 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2899 pbn_b2_8_921600 },
1da177e4
LT		 2900 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2901 PCI_SUBVENDOR_ID_CONNECT_TECH,
2902 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2903 pbn_b1_8_1382400 },
2904 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2905 PCI_SUBVENDOR_ID_CONNECT_TECH,
2906 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2907 pbn_b1_4_1382400 },
2908 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2909 PCI_SUBVENDOR_ID_CONNECT_TECH,
2910 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2911 pbn_b1_2_1382400 },
2912 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2913 PCI_SUBVENDOR_ID_CONNECT_TECH,
2914 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2915 pbn_b1_8_1382400 },
2916 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2917 PCI_SUBVENDOR_ID_CONNECT_TECH,
2918 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2919 pbn_b1_4_1382400 },
2920 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2921 PCI_SUBVENDOR_ID_CONNECT_TECH,
2922 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2923 pbn_b1_2_1382400 },
2924 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2925 PCI_SUBVENDOR_ID_CONNECT_TECH,
2926 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2927 pbn_b1_8_921600 },
2928 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2929 PCI_SUBVENDOR_ID_CONNECT_TECH,
2930 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2931 pbn_b1_8_921600 },
2932 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2933 PCI_SUBVENDOR_ID_CONNECT_TECH,
2934 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2935 pbn_b1_4_921600 },
2936 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2937 PCI_SUBVENDOR_ID_CONNECT_TECH,
2938 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2939 pbn_b1_4_921600 },
2940 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2941 PCI_SUBVENDOR_ID_CONNECT_TECH,
2942 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2943 pbn_b1_2_921600 },
2944 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2945 PCI_SUBVENDOR_ID_CONNECT_TECH,
2946 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2947 pbn_b1_8_921600 },
2948 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2949 PCI_SUBVENDOR_ID_CONNECT_TECH,
2950 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2951 pbn_b1_8_921600 },
2952 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2953 PCI_SUBVENDOR_ID_CONNECT_TECH,
2954 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2955 pbn_b1_4_921600 },
26e92861
GH		 2956 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2957 PCI_SUBVENDOR_ID_CONNECT_TECH,
2958 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2959 pbn_b1_2_1250000 },
2960 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2961 PCI_SUBVENDOR_ID_CONNECT_TECH,
2962 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2963 pbn_b0_2_1843200 },
2964 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2965 PCI_SUBVENDOR_ID_CONNECT_TECH,
2966 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2967 pbn_b0_4_1843200 },
85d1494e
YY		 2968 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2969 PCI_VENDOR_ID_AFAVLAB,
2970 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2971 pbn_b0_4_1152000 },
26e92861
GH		 2972 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2973 PCI_SUBVENDOR_ID_CONNECT_TECH,
2974 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2975 pbn_b0_2_1843200_200 },
2976 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2977 PCI_SUBVENDOR_ID_CONNECT_TECH,
2978 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2979 pbn_b0_4_1843200_200 },
2980 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2981 PCI_SUBVENDOR_ID_CONNECT_TECH,
2982 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2983 pbn_b0_8_1843200_200 },
2984 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2985 PCI_SUBVENDOR_ID_CONNECT_TECH,
2986 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2987 pbn_b0_2_1843200_200 },
2988 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2989 PCI_SUBVENDOR_ID_CONNECT_TECH,
2990 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2991 pbn_b0_4_1843200_200 },
2992 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2993 PCI_SUBVENDOR_ID_CONNECT_TECH,
2994 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2995 pbn_b0_8_1843200_200 },
2996 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2997 PCI_SUBVENDOR_ID_CONNECT_TECH,
2998 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2999 pbn_b0_2_1843200_200 },
3000 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3001 PCI_SUBVENDOR_ID_CONNECT_TECH,
3002 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3003 pbn_b0_4_1843200_200 },
3004 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3005 PCI_SUBVENDOR_ID_CONNECT_TECH,
3006 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3007 pbn_b0_8_1843200_200 },
3008 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3009 PCI_SUBVENDOR_ID_CONNECT_TECH,
3010 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3011 pbn_b0_2_1843200_200 },
3012 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3013 PCI_SUBVENDOR_ID_CONNECT_TECH,
3014 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3015 pbn_b0_4_1843200_200 },
3016 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3017 PCI_SUBVENDOR_ID_CONNECT_TECH,
3018 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3019 pbn_b0_8_1843200_200 },
c68d2b15
BH		 3020 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3021 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3022 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 3023
3024 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 3025 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3026 pbn_b2_bt_1_115200 },
3027 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 3028 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3029 pbn_b2_bt_2_115200 },
3030 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 3031 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3032 pbn_b2_bt_4_115200 },
3033 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 3034 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3035 pbn_b2_bt_2_115200 },
3036 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 3037 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3038 pbn_b2_bt_4_115200 },
3039 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 3040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3041 pbn_b2_8_115200 },
e65f0f82
FL		 3042 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3044 pbn_b2_8_460800 },
1da177e4
LT		 3045 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3046 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3047 pbn_b2_8_115200 },
3048
3049 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3050 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3051 pbn_b2_bt_2_115200 },
3052 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3053 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3054 pbn_b2_bt_2_921600 },
3055 /*
3056 * VScom SPCOM800, from sl@s.pl
3057 */
5756ee99
AC		 3058 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3059 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3060 pbn_b2_8_921600 },
3061 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 3062 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 3063 pbn_b2_4_921600 },
b76c5a07
CB		 3064 /* Unknown card - subdevice 0x1584 */
3065 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3066 PCI_VENDOR_ID_PLX,
3067 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3068 pbn_b0_4_115200 },
1da177e4
LT		 3069 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3070 PCI_SUBVENDOR_ID_KEYSPAN,
3071 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3072 pbn_panacom },
3073 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3074 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3075 pbn_panacom4 },
3076 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3077 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3078 pbn_panacom2 },
a9cccd34
MF		 3079 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3080 PCI_VENDOR_ID_ESDGMBH,
3081 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3082 pbn_b2_4_115200 },
1da177e4
LT		 3083 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3084 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3085 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 3086 pbn_b2_4_460800 },
3087 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3088 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3089 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 3090 pbn_b2_8_460800 },
3091 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3092 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3093 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 3094 pbn_b2_16_460800 },
3095 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3096 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 3097 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 3098 pbn_b2_16_460800 },
3099 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3100 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 3101 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 3102 pbn_b2_4_460800 },
3103 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3104 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 3105 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 3106 pbn_b2_8_460800 },
add7b58e
BH		 3107 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3108 PCI_SUBVENDOR_ID_EXSYS,
3109 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3110 pbn_exsys_4055 },
1da177e4
LT		 3111 /*
3112 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3113 * (Exoray@isys.ca)
3114 */
3115 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3116 0x10b5, 0x106a, 0, 0,
3117 pbn_plx_romulus },
3118 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3119 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3120 pbn_b1_4_115200 },
3121 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3123 pbn_b1_2_115200 },
3124 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3125 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3126 pbn_b1_8_115200 },
3127 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3129 pbn_b1_8_115200 },
3130 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 3131 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3132 0, 0,
1da177e4 3133 pbn_b0_4_921600 },
fbc0dc0d 3134 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 3135 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3136 0, 0,
fbc0dc0d 3137 pbn_b0_4_1152000 },
c9bd9d01
MP		 3138 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3140 pbn_b0_bt_2_921600 },
db1de159
DR		 3141
3142 /*
3143 * The below card is a little controversial since it is the
3144 * subject of a PCI vendor/device ID clash. (See
3145 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3146 * For now just used the hex ID 0x950a.
3147 */
39aced68
NV		 3148 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3149 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
3150 pbn_b0_2_115200 },
db1de159
DR		 3151 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3153 pbn_b0_2_1130000 },
70fd8fde
AP		 3154 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3155 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3156 pbn_b0_1_921600 },
1da177e4
LT		 3157 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3159 pbn_b0_4_115200 },
3160 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3162 pbn_b0_bt_2_921600 },
e847003f
LB		 3163 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3164 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3165 pbn_b2_8_1152000 },
1da177e4 3166
7106b4e3
LH		 3167 /*
3168 * Oxford Semiconductor Inc. Tornado PCI express device range.
3169 */
3170 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3171 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3172 pbn_b0_1_4000000 },
3173 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3174 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3175 pbn_b0_1_4000000 },
3176 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3177 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3178 pbn_oxsemi_1_4000000 },
3179 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3180 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3181 pbn_oxsemi_1_4000000 },
3182 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3183 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3184 pbn_b0_1_4000000 },
3185 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3186 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3187 pbn_b0_1_4000000 },
3188 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3189 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3190 pbn_oxsemi_1_4000000 },
3191 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3192 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3193 pbn_oxsemi_1_4000000 },
3194 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3195 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3196 pbn_b0_1_4000000 },
3197 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3198 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3199 pbn_b0_1_4000000 },
3200 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3201 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3202 pbn_b0_1_4000000 },
3203 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3204 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3205 pbn_b0_1_4000000 },
3206 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3208 pbn_oxsemi_2_4000000 },
3209 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3210 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3211 pbn_oxsemi_2_4000000 },
3212 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3213 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3214 pbn_oxsemi_4_4000000 },
3215 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3216 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3217 pbn_oxsemi_4_4000000 },
3218 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3219 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3220 pbn_oxsemi_8_4000000 },
3221 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3222 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3223 pbn_oxsemi_8_4000000 },
3224 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3225 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3226 pbn_oxsemi_1_4000000 },
3227 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3228 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3229 pbn_oxsemi_1_4000000 },
3230 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3231 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3232 pbn_oxsemi_1_4000000 },
3233 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3234 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3235 pbn_oxsemi_1_4000000 },
3236 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3237 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3238 pbn_oxsemi_1_4000000 },
3239 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3240 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3241 pbn_oxsemi_1_4000000 },
3242 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3243 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3244 pbn_oxsemi_1_4000000 },
3245 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3246 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3247 pbn_oxsemi_1_4000000 },
3248 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3249 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3250 pbn_oxsemi_1_4000000 },
3251 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3252 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3253 pbn_oxsemi_1_4000000 },
3254 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3255 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3256 pbn_oxsemi_1_4000000 },
3257 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3258 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3259 pbn_oxsemi_1_4000000 },
3260 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3261 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3262 pbn_oxsemi_1_4000000 },
3263 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3264 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3265 pbn_oxsemi_1_4000000 },
3266 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3267 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3268 pbn_oxsemi_1_4000000 },
3269 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3270 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3271 pbn_oxsemi_1_4000000 },
3272 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3274 pbn_oxsemi_1_4000000 },
3275 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3276 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3277 pbn_oxsemi_1_4000000 },
3278 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3280 pbn_oxsemi_1_4000000 },
3281 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3282 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3283 pbn_oxsemi_1_4000000 },
3284 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3285 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3286 pbn_oxsemi_1_4000000 },
3287 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3288 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3289 pbn_oxsemi_1_4000000 },
3290 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3291 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3292 pbn_oxsemi_1_4000000 },
3293 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3294 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3295 pbn_oxsemi_1_4000000 },
3296 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3298 pbn_oxsemi_1_4000000 },
3299 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3300 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3301 pbn_oxsemi_1_4000000 },
b80de369
LH		 3302 /*
3303 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3304 */
3305 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3306 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3307 pbn_oxsemi_1_4000000 },
3308 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3309 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3310 pbn_oxsemi_2_4000000 },
3311 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3312 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3313 pbn_oxsemi_4_4000000 },
3314 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3315 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3316 pbn_oxsemi_8_4000000 },
aa273ae5
SK		 3317
3318 /*
3319 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3320 */
3321 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3322 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3323 pbn_oxsemi_2_4000000 },
3324
1da177e4
LT		 3325 /*
3326 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3327 * from skokodyn@yahoo.com
3328 */
3329 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3330 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3331 pbn_sbsxrsio },
3332 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3333 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3334 pbn_sbsxrsio },
3335 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3336 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3337 pbn_sbsxrsio },
3338 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3339 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3340 pbn_sbsxrsio },
3341
3342 /*
3343 * Digitan DS560-558, from jimd@esoft.com
3344 */
3345 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 3346 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3347 pbn_b1_1_115200 },
3348
3349 /*
3350 * Titan Electronic cards
3351 * The 400L and 800L have a custom setup quirk.
3352 */
3353 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 3354 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3355 pbn_b0_1_921600 },
3356 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 3357 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3358 pbn_b0_2_921600 },
3359 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 3360 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3361 pbn_b0_4_921600 },
3362 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 3363 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3364 pbn_b0_4_921600 },
3365 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3366 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3367 pbn_b1_1_921600 },
3368 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3369 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3370 pbn_b1_bt_2_921600 },
3371 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3372 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3373 pbn_b0_bt_4_921600 },
3374 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3375 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3376 pbn_b0_bt_8_921600 },
66169ad1
YY		 3377 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3378 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3379 pbn_b4_bt_2_921600 },
3380 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3381 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3382 pbn_b4_bt_4_921600 },
3383 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3384 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3385 pbn_b4_bt_8_921600 },
3386 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3387 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3388 pbn_b0_4_921600 },
3389 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3390 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3391 pbn_b0_4_921600 },
3392 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3393 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3394 pbn_b0_4_921600 },
3395 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3396 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3397 pbn_oxsemi_1_4000000 },
3398 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3400 pbn_oxsemi_2_4000000 },
3401 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3403 pbn_oxsemi_4_4000000 },
3404 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3405 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3406 pbn_oxsemi_8_4000000 },
3407 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3409 pbn_oxsemi_2_4000000 },
3410 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3411 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3412 pbn_oxsemi_2_4000000 },
1da177e4
LT		 3413
3414 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3416 pbn_b2_1_460800 },
3417 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3419 pbn_b2_1_460800 },
3420 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3422 pbn_b2_1_460800 },
3423 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3425 pbn_b2_bt_2_921600 },
3426 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3428 pbn_b2_bt_2_921600 },
3429 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3431 pbn_b2_bt_2_921600 },
3432 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3434 pbn_b2_bt_4_921600 },
3435 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3437 pbn_b2_bt_4_921600 },
3438 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3440 pbn_b2_bt_4_921600 },
3441 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3443 pbn_b0_1_921600 },
3444 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3446 pbn_b0_1_921600 },
3447 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3449 pbn_b0_1_921600 },
3450 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3452 pbn_b0_bt_2_921600 },
3453 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3455 pbn_b0_bt_2_921600 },
3456 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3457 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3458 pbn_b0_bt_2_921600 },
3459 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3460 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3461 pbn_b0_bt_4_921600 },
3462 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3464 pbn_b0_bt_4_921600 },
3465 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3466 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3467 pbn_b0_bt_4_921600 },
3ec9c594
AP		 3468 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3469 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3470 pbn_b0_bt_8_921600 },
3471 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3472 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3473 pbn_b0_bt_8_921600 },
3474 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3475 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3476 pbn_b0_bt_8_921600 },
1da177e4
LT		 3477
3478 /*
3479 * Computone devices submitted by Doug McNash dmcnash@computone.com
3480 */
3481 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3482 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3483 0, 0, pbn_computone_4 },
3484 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3485 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3486 0, 0, pbn_computone_8 },
3487 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3488 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3489 0, 0, pbn_computone_6 },
3490
3491 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3493 pbn_oxsemi },
3494 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3495 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3496 pbn_b0_bt_1_921600 },
3497
3498 /*
3499 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3500 */
3501 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3503 pbn_b0_bt_8_115200 },
3504 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3506 pbn_b0_bt_8_115200 },
3507
3508 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3510 pbn_b0_bt_2_115200 },
3511 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3513 pbn_b0_bt_2_115200 },
3514 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3515 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3516 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 3517 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3518 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3519 pbn_b0_bt_2_115200 },
3520 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3521 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3522 pbn_b0_bt_2_115200 },
1da177e4
LT		 3523 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3525 pbn_b0_bt_4_460800 },
3526 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3527 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3528 pbn_b0_bt_4_460800 },
3529 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3530 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3531 pbn_b0_bt_2_460800 },
3532 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3533 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3534 pbn_b0_bt_2_460800 },
3535 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3536 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3537 pbn_b0_bt_2_460800 },
3538 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3539 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3540 pbn_b0_bt_1_115200 },
3541 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3542 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3543 pbn_b0_bt_1_460800 },
3544
1fb8cacc
RK		 3545 /*
3546 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3547 * Cards are identified by their subsystem vendor IDs, which
3548 * (in hex) match the model number.
3549 *
3550 * Note that JC140x are RS422/485 cards which require ox950
3551 * ACR = 0x10, and as such are not currently fully supported.
3552 */
3553 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3554 0x1204, 0x0004, 0, 0,
3555 pbn_b0_4_921600 },
3556 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3557 0x1208, 0x0004, 0, 0,
3558 pbn_b0_4_921600 },
3559/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3560 0x1402, 0x0002, 0, 0,
3561 pbn_b0_2_921600 }, */
3562/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3563 0x1404, 0x0004, 0, 0,
3564 pbn_b0_4_921600 }, */
3565 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3566 0x1208, 0x0004, 0, 0,
3567 pbn_b0_4_921600 },
3568
2a52fcb5
KY		 3569 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3570 0x1204, 0x0004, 0, 0,
3571 pbn_b0_4_921600 },
3572 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3573 0x1208, 0x0004, 0, 0,
3574 pbn_b0_4_921600 },
3575 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3576 0x1208, 0x0004, 0, 0,
3577 pbn_b0_4_921600 },
1da177e4
LT		 3578 /*
3579 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3580 */
3581 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3583 pbn_b1_1_1382400 },
3584
3585 /*
3586 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3587 */
3588 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3590 pbn_b1_1_1382400 },
3591
3592 /*
3593 * RAStel 2 port modem, gerg@moreton.com.au
3594 */
3595 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3596 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3597 pbn_b2_bt_2_115200 },
3598
3599 /*
3600 * EKF addition for i960 Boards form EKF with serial port
3601 */
3602 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3603 0xE4BF, PCI_ANY_ID, 0, 0,
3604 pbn_intel_i960 },
3605
3606 /*
3607 * Xircom Cardbus/Ethernet combos
3608 */
3609 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3611 pbn_b0_1_115200 },
3612 /*
3613 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3614 */
3615 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3617 pbn_b0_1_115200 },
3618
3619 /*
3620 * Untested PCI modems, sent in from various folks...
3621 */
3622
3623 /*
3624 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3625 */
3626 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3627 0x1048, 0x1500, 0, 0,
3628 pbn_b1_1_115200 },
3629
3630 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3631 0xFF00, 0, 0, 0,
3632 pbn_sgi_ioc3 },
3633
3634 /*
3635 * HP Diva card
3636 */
3637 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3638 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3639 pbn_b1_1_115200 },
3640 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3642 pbn_b0_5_115200 },
3643 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3644 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3645 pbn_b2_1_115200 },
3646
d9004eb4
ABL		 3647 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3649 pbn_b3_2_115200 },
1da177e4
LT		 3650 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3651 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3652 pbn_b3_4_115200 },
3653 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3654 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3655 pbn_b3_8_115200 },
3656
3657 /*
3658 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3659 */
3660 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3661 PCI_ANY_ID, PCI_ANY_ID,
3662 0,
3663 0, pbn_exar_XR17C152 },
3664 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3665 PCI_ANY_ID, PCI_ANY_ID,
3666 0,
3667 0, pbn_exar_XR17C154 },
3668 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3669 PCI_ANY_ID, PCI_ANY_ID,
3670 0,
3671 0, pbn_exar_XR17C158 },
3672
3673 /*
3674 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3675 */
3676 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3677 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3678 pbn_b0_1_115200 },
84f8c6fc
NV		 3679 /*
3680 * ITE
3681 */
3682 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3683 PCI_ANY_ID, PCI_ANY_ID,
3684 0, 0,
3685 pbn_b1_bt_1_115200 },
1da177e4 3686
737c1756
PH		 3687 /*
3688 * IntaShield IS-200
3689 */
3690 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3691 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3692 pbn_b2_2_115200 },
4b6f6ce9
IGP		 3693 /*
3694 * IntaShield IS-400
3695 */
3696 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3697 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3698 pbn_b2_4_115200 },
48212008
TH		 3699 /*
3700 * Perle PCI-RAS cards
3701 */
3702 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3703 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3704 0, 0, pbn_b2_4_921600 },
3705 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3706 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3707 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 3708
3709 /*
3710 * Mainpine series cards: Fairly standard layout but fools
3711 * parts of the autodetect in some cases and uses otherwise
3712 * unmatched communications subclasses in the PCI Express case
3713 */
3714
3715 { /* RockForceDUO */
3716 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3717 PCI_VENDOR_ID_MAINPINE, 0x0200,
3718 0, 0, pbn_b0_2_115200 },
3719 { /* RockForceQUATRO */
3720 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3721 PCI_VENDOR_ID_MAINPINE, 0x0300,
3722 0, 0, pbn_b0_4_115200 },
3723 { /* RockForceDUO+ */
3724 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3725 PCI_VENDOR_ID_MAINPINE, 0x0400,
3726 0, 0, pbn_b0_2_115200 },
3727 { /* RockForceQUATRO+ */
3728 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3729 PCI_VENDOR_ID_MAINPINE, 0x0500,
3730 0, 0, pbn_b0_4_115200 },
3731 { /* RockForce+ */
3732 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3733 PCI_VENDOR_ID_MAINPINE, 0x0600,
3734 0, 0, pbn_b0_2_115200 },
3735 { /* RockForce+ */
3736 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3737 PCI_VENDOR_ID_MAINPINE, 0x0700,
3738 0, 0, pbn_b0_4_115200 },
3739 { /* RockForceOCTO+ */
3740 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3741 PCI_VENDOR_ID_MAINPINE, 0x0800,
3742 0, 0, pbn_b0_8_115200 },
3743 { /* RockForceDUO+ */
3744 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3745 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3746 0, 0, pbn_b0_2_115200 },
3747 { /* RockForceQUARTRO+ */
3748 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3749 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3750 0, 0, pbn_b0_4_115200 },
3751 { /* RockForceOCTO+ */
3752 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3753 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3754 0, 0, pbn_b0_8_115200 },
3755 { /* RockForceD1 */
3756 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3757 PCI_VENDOR_ID_MAINPINE, 0x2000,
3758 0, 0, pbn_b0_1_115200 },
3759 { /* RockForceF1 */
3760 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3761 PCI_VENDOR_ID_MAINPINE, 0x2100,
3762 0, 0, pbn_b0_1_115200 },
3763 { /* RockForceD2 */
3764 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3765 PCI_VENDOR_ID_MAINPINE, 0x2200,
3766 0, 0, pbn_b0_2_115200 },
3767 { /* RockForceF2 */
3768 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3769 PCI_VENDOR_ID_MAINPINE, 0x2300,
3770 0, 0, pbn_b0_2_115200 },
3771 { /* RockForceD4 */
3772 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3773 PCI_VENDOR_ID_MAINPINE, 0x2400,
3774 0, 0, pbn_b0_4_115200 },
3775 { /* RockForceF4 */
3776 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3777 PCI_VENDOR_ID_MAINPINE, 0x2500,
3778 0, 0, pbn_b0_4_115200 },
3779 { /* RockForceD8 */
3780 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3781 PCI_VENDOR_ID_MAINPINE, 0x2600,
3782 0, 0, pbn_b0_8_115200 },
3783 { /* RockForceF8 */
3784 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3785 PCI_VENDOR_ID_MAINPINE, 0x2700,
3786 0, 0, pbn_b0_8_115200 },
3787 { /* IQ Express D1 */
3788 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3789 PCI_VENDOR_ID_MAINPINE, 0x3000,
3790 0, 0, pbn_b0_1_115200 },
3791 { /* IQ Express F1 */
3792 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3793 PCI_VENDOR_ID_MAINPINE, 0x3100,
3794 0, 0, pbn_b0_1_115200 },
3795 { /* IQ Express D2 */
3796 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3797 PCI_VENDOR_ID_MAINPINE, 0x3200,
3798 0, 0, pbn_b0_2_115200 },
3799 { /* IQ Express F2 */
3800 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3801 PCI_VENDOR_ID_MAINPINE, 0x3300,
3802 0, 0, pbn_b0_2_115200 },
3803 { /* IQ Express D4 */
3804 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3805 PCI_VENDOR_ID_MAINPINE, 0x3400,
3806 0, 0, pbn_b0_4_115200 },
3807 { /* IQ Express F4 */
3808 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3809 PCI_VENDOR_ID_MAINPINE, 0x3500,
3810 0, 0, pbn_b0_4_115200 },
3811 { /* IQ Express D8 */
3812 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3813 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3814 0, 0, pbn_b0_8_115200 },
3815 { /* IQ Express F8 */
3816 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3817 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3818 0, 0, pbn_b0_8_115200 },
3819
3820
aa798505
OJ		 3821 /*
3822 * PA Semi PA6T-1682M on-chip UART
3823 */
3824 { PCI_VENDOR_ID_PASEMI, 0xa004,
3825 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3826 pbn_pasemi_1682M },
3827
46a0fac9
SB		 3828 /*
3829 * National Instruments
3830 */
04bf7e74
WP		 3831 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3832 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3833 pbn_b1_16_115200 },
3834 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3835 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3836 pbn_b1_8_115200 },
3837 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3838 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3839 pbn_b1_bt_4_115200 },
3840 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3841 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3842 pbn_b1_bt_2_115200 },
3843 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3844 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3845 pbn_b1_bt_4_115200 },
3846 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3847 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3848 pbn_b1_bt_2_115200 },
3849 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3850 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3851 pbn_b1_16_115200 },
3852 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3853 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3854 pbn_b1_8_115200 },
3855 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3856 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3857 pbn_b1_bt_4_115200 },
3858 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3859 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3860 pbn_b1_bt_2_115200 },
3861 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3862 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3863 pbn_b1_bt_4_115200 },
3864 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3865 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3866 pbn_b1_bt_2_115200 },
46a0fac9
SB		 3867 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3868 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3869 pbn_ni8430_2 },
3870 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3871 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3872 pbn_ni8430_2 },
3873 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3874 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3875 pbn_ni8430_4 },
3876 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3877 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3878 pbn_ni8430_4 },
3879 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3880 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3881 pbn_ni8430_8 },
3882 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3884 pbn_ni8430_8 },
3885 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3887 pbn_ni8430_16 },
3888 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3889 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3890 pbn_ni8430_16 },
3891 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3892 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3893 pbn_ni8430_2 },
3894 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3895 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3896 pbn_ni8430_2 },
3897 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3898 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3899 pbn_ni8430_4 },
3900 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3902 pbn_ni8430_4 },
3903
02c9b5cf
KJ		 3904 /*
3905 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3906 */
3907 { PCI_VENDOR_ID_ADDIDATA,
3908 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3909 PCI_ANY_ID,
3910 PCI_ANY_ID,
3911 0,
3912 0,
3913 pbn_b0_4_115200 },
3914
3915 { PCI_VENDOR_ID_ADDIDATA,
3916 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3917 PCI_ANY_ID,
3918 PCI_ANY_ID,
3919 0,
3920 0,
3921 pbn_b0_2_115200 },
3922
3923 { PCI_VENDOR_ID_ADDIDATA,
3924 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3925 PCI_ANY_ID,
3926 PCI_ANY_ID,
3927 0,
3928 0,
3929 pbn_b0_1_115200 },
3930
3931 { PCI_VENDOR_ID_ADDIDATA_OLD,
3932 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3933 PCI_ANY_ID,
3934 PCI_ANY_ID,
3935 0,
3936 0,
3937 pbn_b1_8_115200 },
3938
3939 { PCI_VENDOR_ID_ADDIDATA,
3940 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3941 PCI_ANY_ID,
3942 PCI_ANY_ID,
3943 0,
3944 0,
3945 pbn_b0_4_115200 },
3946
3947 { PCI_VENDOR_ID_ADDIDATA,
3948 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3949 PCI_ANY_ID,
3950 PCI_ANY_ID,
3951 0,
3952 0,
3953 pbn_b0_2_115200 },
3954
3955 { PCI_VENDOR_ID_ADDIDATA,
3956 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3957 PCI_ANY_ID,
3958 PCI_ANY_ID,
3959 0,
3960 0,
3961 pbn_b0_1_115200 },
3962
3963 { PCI_VENDOR_ID_ADDIDATA,
3964 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3965 PCI_ANY_ID,
3966 PCI_ANY_ID,
3967 0,
3968 0,
3969 pbn_b0_4_115200 },
3970
3971 { PCI_VENDOR_ID_ADDIDATA,
3972 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3973 PCI_ANY_ID,
3974 PCI_ANY_ID,
3975 0,
3976 0,
3977 pbn_b0_2_115200 },
3978
3979 { PCI_VENDOR_ID_ADDIDATA,
3980 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3981 PCI_ANY_ID,
3982 PCI_ANY_ID,
3983 0,
3984 0,
3985 pbn_b0_1_115200 },
3986
3987 { PCI_VENDOR_ID_ADDIDATA,
3988 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3989 PCI_ANY_ID,
3990 PCI_ANY_ID,
3991 0,
3992 0,
3993 pbn_b0_8_115200 },
3994
1b62cbf2
KJ		 3995 { PCI_VENDOR_ID_ADDIDATA,
3996 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
3997 PCI_ANY_ID,
3998 PCI_ANY_ID,
3999 0,
4000 0,
4001 pbn_ADDIDATA_PCIe_4_3906250 },
4002
4003 { PCI_VENDOR_ID_ADDIDATA,
4004 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4005 PCI_ANY_ID,
4006 PCI_ANY_ID,
4007 0,
4008 0,
4009 pbn_ADDIDATA_PCIe_2_3906250 },
4010
4011 { PCI_VENDOR_ID_ADDIDATA,
4012 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4013 PCI_ANY_ID,
4014 PCI_ANY_ID,
4015 0,
4016 0,
4017 pbn_ADDIDATA_PCIe_1_3906250 },
4018
4019 { PCI_VENDOR_ID_ADDIDATA,
4020 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4021 PCI_ANY_ID,
4022 PCI_ANY_ID,
4023 0,
4024 0,
4025 pbn_ADDIDATA_PCIe_8_3906250 },
4026
25cf9bc1
JS		 4027 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4028 PCI_VENDOR_ID_IBM, 0x0299,
4029 0, 0, pbn_b0_bt_2_115200 },
4030
c4285b47
MB		 4031 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4032 0xA000, 0x1000,
4033 0, 0, pbn_b0_1_115200 },
4034
7808edcd
NG		 4035 /* the 9901 is a rebranded 9912 */
4036 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4037 0xA000, 0x1000,
4038 0, 0, pbn_b0_1_115200 },
4039
4040 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4041 0xA000, 0x1000,
4042 0, 0, pbn_b0_1_115200 },
4043
4044 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4045 0xA000, 0x1000,
4046 0, 0, pbn_b0_1_115200 },
4047
4048 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4049 0xA000, 0x1000,
4050 0, 0, pbn_b0_1_115200 },
4051
4052 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4053 0xA000, 0x3002,
4054 0, 0, pbn_NETMOS9900_2s_115200 },
4055
ac6ec5b1
IS		 4056 /*
4057 * Best Connectivity PCI Multi I/O cards
4058 */
4059
4060 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4061 0xA000, 0x1000,
4062 0, 0, pbn_b0_1_115200 },
4063
4064 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4065 0xA000, 0x3004,
4066 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 4067 /* Intel CE4100 */
4068 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4070 pbn_ce4100_1_115200 },
4071
d9a0fbfd
AP		 4072 /*
4073 * Cronyx Omega PCI
4074 */
4075 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4076 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4077 pbn_omegapci },
ac6ec5b1 4078
1da177e4
LT		 4079 /*
4080 * These entries match devices with class COMMUNICATION_SERIAL,
4081 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4082 */
4083 { PCI_ANY_ID, PCI_ANY_ID,
4084 PCI_ANY_ID, PCI_ANY_ID,
4085 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4086 0xffff00, pbn_default },
4087 { PCI_ANY_ID, PCI_ANY_ID,
4088 PCI_ANY_ID, PCI_ANY_ID,
4089 PCI_CLASS_COMMUNICATION_MODEM << 8,
4090 0xffff00, pbn_default },
4091 { PCI_ANY_ID, PCI_ANY_ID,
4092 PCI_ANY_ID, PCI_ANY_ID,
4093 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4094 0xffff00, pbn_default },
4095 { 0, }
4096};
4097
2807190b
MR		 4098static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4099 pci_channel_state_t state)
4100{
4101 struct serial_private *priv = pci_get_drvdata(dev);
4102
4103 if (state == pci_channel_io_perm_failure)
4104 return PCI_ERS_RESULT_DISCONNECT;
4105
4106 if (priv)
4107 pciserial_suspend_ports(priv);
4108
4109 pci_disable_device(dev);
4110
4111 return PCI_ERS_RESULT_NEED_RESET;
4112}
4113
4114static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4115{
4116 int rc;
4117
4118 rc = pci_enable_device(dev);
4119
4120 if (rc)
4121 return PCI_ERS_RESULT_DISCONNECT;
4122
4123 pci_restore_state(dev);
4124 pci_save_state(dev);
4125
4126 return PCI_ERS_RESULT_RECOVERED;
4127}
4128
4129static void serial8250_io_resume(struct pci_dev *dev)
4130{
4131 struct serial_private *priv = pci_get_drvdata(dev);
4132
4133 if (priv)
4134 pciserial_resume_ports(priv);
4135}
4136
4137static struct pci_error_handlers serial8250_err_handler = {
4138 .error_detected = serial8250_io_error_detected,
4139 .slot_reset = serial8250_io_slot_reset,
4140 .resume = serial8250_io_resume,
4141};
4142
1da177e4
LT		 4143static struct pci_driver serial_pci_driver = {
4144 .name = "serial",
4145 .probe = pciserial_init_one,
4146 .remove = __devexit_p(pciserial_remove_one),
1d5e7996 4147#ifdef CONFIG_PM
1da177e4
LT		 4148 .suspend = pciserial_suspend_one,
4149 .resume = pciserial_resume_one,
1d5e7996 4150#endif
1da177e4 4151 .id_table = serial_pci_tbl,
2807190b 4152 .err_handler = &serial8250_err_handler,
1da177e4
LT		 4153};
4154
4155static int __init serial8250_pci_init(void)
4156{
4157 return pci_register_driver(&serial_pci_driver);
4158}
4159
4160static void __exit serial8250_pci_exit(void)
4161{
4162 pci_unregister_driver(&serial_pci_driver);
4163}
4164
4165module_init(serial8250_pci_init);
4166module_exit(serial8250_pci_exit);
4167
4168MODULE_LICENSE("GPL");
4169MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4170MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux kernel - Deliverables
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