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ASoC: Update cx20442 for TTY API change
[deliverable/linux.git] / drivers / tty / serial / 8250_pci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
1da177e4
LT		 11 */
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
1da177e4
LT		 15#include <linux/string.h>
16#include <linux/kernel.h>
17#include <linux/slab.h>
18#include <linux/delay.h>
19#include <linux/tty.h>
20#include <linux/serial_core.h>
21#include <linux/8250_pci.h>
22#include <linux/bitops.h>
23
24#include <asm/byteorder.h>
25#include <asm/io.h>
26
27#include "8250.h"
28
29#undef SERIAL_DEBUG_PCI
30
1da177e4
LT		 31/*
32 * init function returns:
33 * > 0 - number of ports
34 * = 0 - use board->num_ports
35 * < 0 - error
36 */
37struct pci_serial_quirk {
38 u32 vendor;
39 u32 device;
40 u32 subvendor;
41 u32 subdevice;
42 int (*init)(struct pci_dev *dev);
975a1a7d
RK		 43 int (*setup)(struct serial_private *,
44 const struct pciserial_board *,
05caac58 45 struct uart_port *, int);
1da177e4
LT		 46 void (*exit)(struct pci_dev *dev);
47};
48
49#define PCI_NUM_BAR_RESOURCES 6
50
51struct serial_private {
70db3d91 52 struct pci_dev *dev;
1da177e4
LT		 53 unsigned int nr;
54 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
55 struct pci_serial_quirk *quirk;
56 int line[0];
57};
58
59static void moan_device(const char *str, struct pci_dev *dev)
60{
ad361c98
JP		 61 printk(KERN_WARNING
62 "%s: %s\n"
63 "Please send the output of lspci -vv, this\n"
64 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
65 "manufacturer and name of serial board or\n"
66 "modem board to rmk+serial@arm.linux.org.uk.\n",
1da177e4
LT		 67 pci_name(dev), str, dev->vendor, dev->device,
68 dev->subsystem_vendor, dev->subsystem_device);
69}
70
71static int
70db3d91 72setup_port(struct serial_private *priv, struct uart_port *port,
1da177e4
LT		 73 int bar, int offset, int regshift)
74{
70db3d91 75 struct pci_dev *dev = priv->dev;
1da177e4
LT		 76 unsigned long base, len;
77
78 if (bar >= PCI_NUM_BAR_RESOURCES)
79 return -EINVAL;
80
72ce9a83
RK		 81 base = pci_resource_start(dev, bar);
82
1da177e4 83 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
1da177e4
LT		 84 len = pci_resource_len(dev, bar);
85
86 if (!priv->remapped_bar[bar])
6f441fe9 87 priv->remapped_bar[bar] = ioremap_nocache(base, len);
1da177e4
LT		 88 if (!priv->remapped_bar[bar])
89 return -ENOMEM;
90
91 port->iotype = UPIO_MEM;
72ce9a83 92 port->iobase = 0;
1da177e4
LT		 93 port->mapbase = base + offset;
94 port->membase = priv->remapped_bar[bar] + offset;
95 port->regshift = regshift;
96 } else {
1da177e4 97 port->iotype = UPIO_PORT;
72ce9a83
RK		 98 port->iobase = base + offset;
99 port->mapbase = 0;
100 port->membase = NULL;
101 port->regshift = 0;
1da177e4
LT		 102 }
103 return 0;
104}
105
02c9b5cf
KJ		 106/*
107 * ADDI-DATA GmbH communication cards <info@addi-data.com>
108 */
109static int addidata_apci7800_setup(struct serial_private *priv,
975a1a7d 110 const struct pciserial_board *board,
02c9b5cf
KJ		 111 struct uart_port *port, int idx)
112{
113 unsigned int bar = 0, offset = board->first_offset;
114 bar = FL_GET_BASE(board->flags);
115
116 if (idx < 2) {
117 offset += idx * board->uart_offset;
118 } else if ((idx >= 2) && (idx < 4)) {
119 bar += 1;
120 offset += ((idx - 2) * board->uart_offset);
121 } else if ((idx >= 4) && (idx < 6)) {
122 bar += 2;
123 offset += ((idx - 4) * board->uart_offset);
124 } else if (idx >= 6) {
125 bar += 3;
126 offset += ((idx - 6) * board->uart_offset);
127 }
128
129 return setup_port(priv, port, bar, offset, board->reg_shift);
130}
131
1da177e4
LT		 132/*
133 * AFAVLAB uses a different mixture of BARs and offsets
134 * Not that ugly ;) -- HW
135 */
136static int
975a1a7d 137afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 138 struct uart_port *port, int idx)
139{
140 unsigned int bar, offset = board->first_offset;
5756ee99 141
1da177e4
LT		 142 bar = FL_GET_BASE(board->flags);
143 if (idx < 4)
144 bar += idx;
145 else {
146 bar = 4;
147 offset += (idx - 4) * board->uart_offset;
148 }
149
70db3d91 150 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 151}
152
153/*
154 * HP's Remote Management Console. The Diva chip came in several
155 * different versions. N-class, L2000 and A500 have two Diva chips, each
156 * with 3 UARTs (the third UART on the second chip is unused). Superdome
157 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
158 * one Diva chip, but it has been expanded to 5 UARTs.
159 */
61a116ef 160static int pci_hp_diva_init(struct pci_dev *dev)
1da177e4
LT		 161{
162 int rc = 0;
163
164 switch (dev->subsystem_device) {
165 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
166 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
167 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
168 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
169 rc = 3;
170 break;
171 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
172 rc = 2;
173 break;
174 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
175 rc = 4;
176 break;
177 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
551f8f0e 178 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
1da177e4
LT		 179 rc = 1;
180 break;
181 }
182
183 return rc;
184}
185
186/*
187 * HP's Diva chip puts the 4th/5th serial port further out, and
188 * some serial ports are supposed to be hidden on certain models.
189 */
190static int
975a1a7d
RK		 191pci_hp_diva_setup(struct serial_private *priv,
192 const struct pciserial_board *board,
193 struct uart_port *port, int idx)
1da177e4
LT		 194{
195 unsigned int offset = board->first_offset;
196 unsigned int bar = FL_GET_BASE(board->flags);
197
70db3d91 198 switch (priv->dev->subsystem_device) {
1da177e4
LT		 199 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
200 if (idx == 3)
201 idx++;
202 break;
203 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
204 if (idx > 0)
205 idx++;
206 if (idx > 2)
207 idx++;
208 break;
209 }
210 if (idx > 2)
211 offset = 0x18;
212
213 offset += idx * board->uart_offset;
214
70db3d91 215 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 216}
217
218/*
219 * Added for EKF Intel i960 serial boards
220 */
61a116ef 221static int pci_inteli960ni_init(struct pci_dev *dev)
1da177e4
LT		 222{
223 unsigned long oldval;
224
225 if (!(dev->subsystem_device & 0x1000))
226 return -ENODEV;
227
228 /* is firmware started? */
5756ee99
AC		 229 pci_read_config_dword(dev, 0x44, (void *)&oldval);
230 if (oldval == 0x00001000L) { /* RESET value */
1da177e4
LT		 231 printk(KERN_DEBUG "Local i960 firmware missing");
232 return -ENODEV;
233 }
234 return 0;
235}
236
237/*
238 * Some PCI serial cards using the PLX 9050 PCI interface chip require
239 * that the card interrupt be explicitly enabled or disabled. This
240 * seems to be mainly needed on card using the PLX which also use I/O
241 * mapped memory.
242 */
61a116ef 243static int pci_plx9050_init(struct pci_dev *dev)
1da177e4
LT		 244{
245 u8 irq_config;
246 void __iomem *p;
247
248 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
249 moan_device("no memory in bar 0", dev);
250 return 0;
251 }
252
253 irq_config = 0x41;
add7b58e 254 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
5756ee99 255 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
1da177e4 256 irq_config = 0x43;
5756ee99 257
1da177e4 258 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
5756ee99 259 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
1da177e4
LT		 260 /*
261 * As the megawolf cards have the int pins active
262 * high, and have 2 UART chips, both ints must be
263 * enabled on the 9050. Also, the UARTS are set in
264 * 16450 mode by default, so we have to enable the
265 * 16C950 'enhanced' mode so that we can use the
266 * deep FIFOs
267 */
268 irq_config = 0x5b;
1da177e4
LT		 269 /*
270 * enable/disable interrupts
271 */
6f441fe9 272 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 273 if (p == NULL)
274 return -ENOMEM;
275 writel(irq_config, p + 0x4c);
276
277 /*
278 * Read the register back to ensure that it took effect.
279 */
280 readl(p + 0x4c);
281 iounmap(p);
282
283 return 0;
284}
285
286static void __devexit pci_plx9050_exit(struct pci_dev *dev)
287{
288 u8 __iomem *p;
289
290 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
291 return;
292
293 /*
294 * disable interrupts
295 */
6f441fe9 296 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 297 if (p != NULL) {
298 writel(0, p + 0x4c);
299
300 /*
301 * Read the register back to ensure that it took effect.
302 */
303 readl(p + 0x4c);
304 iounmap(p);
305 }
306}
307
04bf7e74
WP		 308#define NI8420_INT_ENABLE_REG 0x38
309#define NI8420_INT_ENABLE_BIT 0x2000
310
311static void __devexit pci_ni8420_exit(struct pci_dev *dev)
312{
313 void __iomem *p;
314 unsigned long base, len;
315 unsigned int bar = 0;
316
317 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
318 moan_device("no memory in bar", dev);
319 return;
320 }
321
322 base = pci_resource_start(dev, bar);
323 len = pci_resource_len(dev, bar);
324 p = ioremap_nocache(base, len);
325 if (p == NULL)
326 return;
327
328 /* Disable the CPU Interrupt */
329 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
330 p + NI8420_INT_ENABLE_REG);
331 iounmap(p);
332}
333
334
46a0fac9
SB		 335/* MITE registers */
336#define MITE_IOWBSR1 0xc4
337#define MITE_IOWCR1 0xf4
338#define MITE_LCIMR1 0x08
339#define MITE_LCIMR2 0x10
340
341#define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
342
343static void __devexit pci_ni8430_exit(struct pci_dev *dev)
344{
345 void __iomem *p;
346 unsigned long base, len;
347 unsigned int bar = 0;
348
349 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
350 moan_device("no memory in bar", dev);
351 return;
352 }
353
354 base = pci_resource_start(dev, bar);
355 len = pci_resource_len(dev, bar);
356 p = ioremap_nocache(base, len);
357 if (p == NULL)
358 return;
359
360 /* Disable the CPU Interrupt */
361 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
362 iounmap(p);
363}
364
1da177e4
LT		 365/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
366static int
975a1a7d 367sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
1da177e4
LT		 368 struct uart_port *port, int idx)
369{
370 unsigned int bar, offset = board->first_offset;
371
372 bar = 0;
373
374 if (idx < 4) {
375 /* first four channels map to 0, 0x100, 0x200, 0x300 */
376 offset += idx * board->uart_offset;
377 } else if (idx < 8) {
378 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
379 offset += idx * board->uart_offset + 0xC00;
380 } else /* we have only 8 ports on PMC-OCTALPRO */
381 return 1;
382
70db3d91 383 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 384}
385
386/*
387* This does initialization for PMC OCTALPRO cards:
388* maps the device memory, resets the UARTs (needed, bc
389* if the module is removed and inserted again, the card
390* is in the sleep mode) and enables global interrupt.
391*/
392
393/* global control register offset for SBS PMC-OctalPro */
394#define OCT_REG_CR_OFF 0x500
395
61a116ef 396static int sbs_init(struct pci_dev *dev)
1da177e4
LT		 397{
398 u8 __iomem *p;
399
24ed3aba 400 p = pci_ioremap_bar(dev, 0);
1da177e4
LT		 401
402 if (p == NULL)
403 return -ENOMEM;
404 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
5756ee99 405 writeb(0x10, p + OCT_REG_CR_OFF);
1da177e4 406 udelay(50);
5756ee99 407 writeb(0x0, p + OCT_REG_CR_OFF);
1da177e4
LT		 408
409 /* Set bit-2 (INTENABLE) of Control Register */
410 writeb(0x4, p + OCT_REG_CR_OFF);
411 iounmap(p);
412
413 return 0;
414}
415
416/*
417 * Disables the global interrupt of PMC-OctalPro
418 */
419
420static void __devexit sbs_exit(struct pci_dev *dev)
421{
422 u8 __iomem *p;
423
24ed3aba 424 p = pci_ioremap_bar(dev, 0);
5756ee99
AC		 425 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
426 if (p != NULL)
1da177e4 427 writeb(0, p + OCT_REG_CR_OFF);
1da177e4
LT		 428 iounmap(p);
429}
430
431/*
432 * SIIG serial cards have an PCI interface chip which also controls
433 * the UART clocking frequency. Each UART can be clocked independently
25985edc 434 * (except cards equipped with 4 UARTs) and initial clocking settings
1da177e4
LT		 435 * are stored in the EEPROM chip. It can cause problems because this
436 * version of serial driver doesn't support differently clocked UART's
437 * on single PCI card. To prevent this, initialization functions set
438 * high frequency clocking for all UART's on given card. It is safe (I
439 * hope) because it doesn't touch EEPROM settings to prevent conflicts
440 * with other OSes (like M$ DOS).
441 *
442 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
5756ee99 443 *
1da177e4
LT		 444 * There is two family of SIIG serial cards with different PCI
445 * interface chip and different configuration methods:
446 * - 10x cards have control registers in IO and/or memory space;
447 * - 20x cards have control registers in standard PCI configuration space.
448 *
67d74b87
RK		 449 * Note: all 10x cards have PCI device ids 0x10..
450 * all 20x cards have PCI device ids 0x20..
451 *
fbc0dc0d
AP		 452 * There are also Quartet Serial cards which use Oxford Semiconductor
453 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
454 *
1da177e4
LT		 455 * Note: some SIIG cards are probed by the parport_serial object.
456 */
457
458#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
459#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
460
461static int pci_siig10x_init(struct pci_dev *dev)
462{
463 u16 data;
464 void __iomem *p;
465
466 switch (dev->device & 0xfff8) {
467 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
468 data = 0xffdf;
469 break;
470 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
471 data = 0xf7ff;
472 break;
473 default: /* 1S1P, 4S */
474 data = 0xfffb;
475 break;
476 }
477
6f441fe9 478 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
1da177e4
LT		 479 if (p == NULL)
480 return -ENOMEM;
481
482 writew(readw(p + 0x28) & data, p + 0x28);
483 readw(p + 0x28);
484 iounmap(p);
485 return 0;
486}
487
488#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
489#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
490
491static int pci_siig20x_init(struct pci_dev *dev)
492{
493 u8 data;
494
495 /* Change clock frequency for the first UART. */
496 pci_read_config_byte(dev, 0x6f, &data);
497 pci_write_config_byte(dev, 0x6f, data & 0xef);
498
499 /* If this card has 2 UART, we have to do the same with second UART. */
500 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
501 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
502 pci_read_config_byte(dev, 0x73, &data);
503 pci_write_config_byte(dev, 0x73, data & 0xef);
504 }
505 return 0;
506}
507
67d74b87
RK		 508static int pci_siig_init(struct pci_dev *dev)
509{
510 unsigned int type = dev->device & 0xff00;
511
512 if (type == 0x1000)
513 return pci_siig10x_init(dev);
514 else if (type == 0x2000)
515 return pci_siig20x_init(dev);
516
517 moan_device("Unknown SIIG card", dev);
518 return -ENODEV;
519}
520
3ec9c594 521static int pci_siig_setup(struct serial_private *priv,
975a1a7d 522 const struct pciserial_board *board,
3ec9c594
AP		 523 struct uart_port *port, int idx)
524{
525 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
526
527 if (idx > 3) {
528 bar = 4;
529 offset = (idx - 4) * 8;
530 }
531
532 return setup_port(priv, port, bar, offset, 0);
533}
534
1da177e4
LT		 535/*
536 * Timedia has an explosion of boards, and to avoid the PCI table from
537 * growing *huge*, we use this function to collapse some 70 entries
538 * in the PCI table into one, for sanity's and compactness's sake.
539 */
e9422e09 540static const unsigned short timedia_single_port[] = {
1da177e4
LT		 541 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
542};
543
e9422e09 544static const unsigned short timedia_dual_port[] = {
1da177e4 545 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
5756ee99
AC		 546 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
547 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
1da177e4
LT		 548 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
549 0xD079, 0
550};
551
e9422e09 552static const unsigned short timedia_quad_port[] = {
5756ee99
AC		 553 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
554 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
1da177e4
LT		 555 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
556 0xB157, 0
557};
558
e9422e09 559static const unsigned short timedia_eight_port[] = {
5756ee99 560 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
1da177e4
LT		 561 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
562};
563
cb3592be 564static const struct timedia_struct {
1da177e4 565 int num;
e9422e09 566 const unsigned short *ids;
1da177e4
LT		 567} timedia_data[] = {
568 { 1, timedia_single_port },
569 { 2, timedia_dual_port },
570 { 4, timedia_quad_port },
e9422e09 571 { 8, timedia_eight_port }
1da177e4
LT		 572};
573
61a116ef 574static int pci_timedia_init(struct pci_dev *dev)
1da177e4 575{
e9422e09 576 const unsigned short *ids;
1da177e4
LT		 577 int i, j;
578
e9422e09 579 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
1da177e4
LT		 580 ids = timedia_data[i].ids;
581 for (j = 0; ids[j]; j++)
582 if (dev->subsystem_device == ids[j])
583 return timedia_data[i].num;
584 }
585 return 0;
586}
587
588/*
589 * Timedia/SUNIX uses a mixture of BARs and offsets
590 * Ugh, this is ugly as all hell --- TYT
591 */
592static int
975a1a7d
RK		 593pci_timedia_setup(struct serial_private *priv,
594 const struct pciserial_board *board,
1da177e4
LT		 595 struct uart_port *port, int idx)
596{
597 unsigned int bar = 0, offset = board->first_offset;
598
599 switch (idx) {
600 case 0:
601 bar = 0;
602 break;
603 case 1:
604 offset = board->uart_offset;
605 bar = 0;
606 break;
607 case 2:
608 bar = 1;
609 break;
610 case 3:
611 offset = board->uart_offset;
c2cd6d3c 612 /* FALLTHROUGH */
1da177e4
LT		 613 case 4: /* BAR 2 */
614 case 5: /* BAR 3 */
615 case 6: /* BAR 4 */
616 case 7: /* BAR 5 */
617 bar = idx - 2;
618 }
619
70db3d91 620 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 621}
622
623/*
624 * Some Titan cards are also a little weird
625 */
626static int
70db3d91 627titan_400l_800l_setup(struct serial_private *priv,
975a1a7d 628 const struct pciserial_board *board,
1da177e4
LT		 629 struct uart_port *port, int idx)
630{
631 unsigned int bar, offset = board->first_offset;
632
633 switch (idx) {
634 case 0:
635 bar = 1;
636 break;
637 case 1:
638 bar = 2;
639 break;
640 default:
641 bar = 4;
642 offset = (idx - 2) * board->uart_offset;
643 }
644
70db3d91 645 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 646}
647
61a116ef 648static int pci_xircom_init(struct pci_dev *dev)
1da177e4
LT		 649{
650 msleep(100);
651 return 0;
652}
653
04bf7e74
WP		 654static int pci_ni8420_init(struct pci_dev *dev)
655{
656 void __iomem *p;
657 unsigned long base, len;
658 unsigned int bar = 0;
659
660 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
661 moan_device("no memory in bar", dev);
662 return 0;
663 }
664
665 base = pci_resource_start(dev, bar);
666 len = pci_resource_len(dev, bar);
667 p = ioremap_nocache(base, len);
668 if (p == NULL)
669 return -ENOMEM;
670
671 /* Enable CPU Interrupt */
672 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
673 p + NI8420_INT_ENABLE_REG);
674
675 iounmap(p);
676 return 0;
677}
678
46a0fac9
SB		 679#define MITE_IOWBSR1_WSIZE 0xa
680#define MITE_IOWBSR1_WIN_OFFSET 0x800
681#define MITE_IOWBSR1_WENAB (1 << 7)
682#define MITE_LCIMR1_IO_IE_0 (1 << 24)
683#define MITE_LCIMR2_SET_CPU_IE (1 << 31)
684#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
685
686static int pci_ni8430_init(struct pci_dev *dev)
687{
688 void __iomem *p;
689 unsigned long base, len;
690 u32 device_window;
691 unsigned int bar = 0;
692
693 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
694 moan_device("no memory in bar", dev);
695 return 0;
696 }
697
698 base = pci_resource_start(dev, bar);
699 len = pci_resource_len(dev, bar);
700 p = ioremap_nocache(base, len);
701 if (p == NULL)
702 return -ENOMEM;
703
704 /* Set device window address and size in BAR0 */
705 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
706 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
707 writel(device_window, p + MITE_IOWBSR1);
708
709 /* Set window access to go to RAMSEL IO address space */
710 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
711 p + MITE_IOWCR1);
712
713 /* Enable IO Bus Interrupt 0 */
714 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
715
716 /* Enable CPU Interrupt */
717 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
718
719 iounmap(p);
720 return 0;
721}
722
723/* UART Port Control Register */
724#define NI8430_PORTCON 0x0f
725#define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
726
727static int
bf538fe4
AC		 728pci_ni8430_setup(struct serial_private *priv,
729 const struct pciserial_board *board,
46a0fac9
SB		 730 struct uart_port *port, int idx)
731{
732 void __iomem *p;
733 unsigned long base, len;
734 unsigned int bar, offset = board->first_offset;
735
736 if (idx >= board->num_ports)
737 return 1;
738
739 bar = FL_GET_BASE(board->flags);
740 offset += idx * board->uart_offset;
741
742 base = pci_resource_start(priv->dev, bar);
743 len = pci_resource_len(priv->dev, bar);
744 p = ioremap_nocache(base, len);
745
746 /* enable the transciever */
747 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
748 p + offset + NI8430_PORTCON);
749
750 iounmap(p);
751
752 return setup_port(priv, port, bar, offset, board->reg_shift);
753}
754
755
61a116ef 756static int pci_netmos_init(struct pci_dev *dev)
1da177e4
LT		 757{
758 /* subdevice 0x00PS means <P> parallel, <S> serial */
759 unsigned int num_serial = dev->subsystem_device & 0xf;
760
ac6ec5b1
IS		 761 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
762 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
c4285b47 763 return 0;
25cf9bc1
JS		 764 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
765 dev->subsystem_device == 0x0299)
766 return 0;
767
1da177e4
LT		 768 if (num_serial == 0)
769 return -ENODEV;
770 return num_serial;
771}
772
84f8c6fc 773/*
84f8c6fc
NV		 774 * These chips are available with optionally one parallel port and up to
775 * two serial ports. Unfortunately they all have the same product id.
776 *
777 * Basic configuration is done over a region of 32 I/O ports. The base
778 * ioport is called INTA or INTC, depending on docs/other drivers.
779 *
780 * The region of the 32 I/O ports is configured in POSIO0R...
781 */
782
783/* registers */
784#define ITE_887x_MISCR 0x9c
785#define ITE_887x_INTCBAR 0x78
786#define ITE_887x_UARTBAR 0x7c
787#define ITE_887x_PS0BAR 0x10
788#define ITE_887x_POSIO0 0x60
789
790/* I/O space size */
791#define ITE_887x_IOSIZE 32
792/* I/O space size (bits 26-24; 8 bytes = 011b) */
793#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
794/* I/O space size (bits 26-24; 32 bytes = 101b) */
795#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
796/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
797#define ITE_887x_POSIO_SPEED (3 << 29)
798/* enable IO_Space bit */
799#define ITE_887x_POSIO_ENABLE (1 << 31)
800
f79abb82 801static int pci_ite887x_init(struct pci_dev *dev)
84f8c6fc
NV		 802{
803 /* inta_addr are the configuration addresses of the ITE */
804 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
805 0x200, 0x280, 0 };
806 int ret, i, type;
807 struct resource *iobase = NULL;
808 u32 miscr, uartbar, ioport;
809
810 /* search for the base-ioport */
811 i = 0;
812 while (inta_addr[i] && iobase == NULL) {
813 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
814 "ite887x");
815 if (iobase != NULL) {
816 /* write POSIO0R - speed | size | ioport */
817 pci_write_config_dword(dev, ITE_887x_POSIO0,
818 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
819 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
820 /* write INTCBAR - ioport */
5756ee99
AC		 821 pci_write_config_dword(dev, ITE_887x_INTCBAR,
822 inta_addr[i]);
84f8c6fc
NV		 823 ret = inb(inta_addr[i]);
824 if (ret != 0xff) {
825 /* ioport connected */
826 break;
827 }
828 release_region(iobase->start, ITE_887x_IOSIZE);
829 iobase = NULL;
830 }
831 i++;
832 }
833
834 if (!inta_addr[i]) {
835 printk(KERN_ERR "ite887x: could not find iobase\n");
836 return -ENODEV;
837 }
838
839 /* start of undocumented type checking (see parport_pc.c) */
840 type = inb(iobase->start + 0x18) & 0x0f;
841
842 switch (type) {
843 case 0x2: /* ITE8871 (1P) */
844 case 0xa: /* ITE8875 (1P) */
845 ret = 0;
846 break;
847 case 0xe: /* ITE8872 (2S1P) */
848 ret = 2;
849 break;
850 case 0x6: /* ITE8873 (1S) */
851 ret = 1;
852 break;
853 case 0x8: /* ITE8874 (2S) */
854 ret = 2;
855 break;
856 default:
857 moan_device("Unknown ITE887x", dev);
858 ret = -ENODEV;
859 }
860
861 /* configure all serial ports */
862 for (i = 0; i < ret; i++) {
863 /* read the I/O port from the device */
864 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
865 &ioport);
866 ioport &= 0x0000FF00; /* the actual base address */
867 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
868 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
869 ITE_887x_POSIO_IOSIZE_8 | ioport);
870
871 /* write the ioport to the UARTBAR */
872 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
873 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
874 uartbar |= (ioport << (16 * i)); /* set the ioport */
875 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
876
877 /* get current config */
878 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
879 /* disable interrupts (UARTx_Routing[3:0]) */
880 miscr &= ~(0xf << (12 - 4 * i));
881 /* activate the UART (UARTx_En) */
882 miscr |= 1 << (23 - i);
883 /* write new config with activated UART */
884 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
885 }
886
887 if (ret <= 0) {
888 /* the device has no UARTs if we get here */
889 release_region(iobase->start, ITE_887x_IOSIZE);
890 }
891
892 return ret;
893}
894
895static void __devexit pci_ite887x_exit(struct pci_dev *dev)
896{
897 u32 ioport;
898 /* the ioport is bit 0-15 in POSIO0R */
899 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
900 ioport &= 0xffff;
901 release_region(ioport, ITE_887x_IOSIZE);
902}
903
9f2a036a
RK		 904/*
905 * Oxford Semiconductor Inc.
906 * Check that device is part of the Tornado range of devices, then determine
907 * the number of ports available on the device.
908 */
909static int pci_oxsemi_tornado_init(struct pci_dev *dev)
910{
911 u8 __iomem *p;
912 unsigned long deviceID;
913 unsigned int number_uarts = 0;
914
915 /* OxSemi Tornado devices are all 0xCxxx */
916 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
917 (dev->device & 0xF000) != 0xC000)
918 return 0;
919
920 p = pci_iomap(dev, 0, 5);
921 if (p == NULL)
922 return -ENOMEM;
923
924 deviceID = ioread32(p);
925 /* Tornado device */
926 if (deviceID == 0x07000200) {
927 number_uarts = ioread8(p + 4);
928 printk(KERN_DEBUG
929 "%d ports detected on Oxford PCI Express device\n",
930 number_uarts);
931 }
932 pci_iounmap(dev, p);
933 return number_uarts;
934}
935
1da177e4 936static int
975a1a7d
RK		 937pci_default_setup(struct serial_private *priv,
938 const struct pciserial_board *board,
1da177e4
LT		 939 struct uart_port *port, int idx)
940{
941 unsigned int bar, offset = board->first_offset, maxnr;
942
943 bar = FL_GET_BASE(board->flags);
944 if (board->flags & FL_BASE_BARS)
945 bar += idx;
946 else
947 offset += idx * board->uart_offset;
948
2427ddd8
GKH		 949 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
950 (board->reg_shift + 3);
1da177e4
LT		 951
952 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
953 return 1;
5756ee99 954
70db3d91 955 return setup_port(priv, port, bar, offset, board->reg_shift);
1da177e4
LT		 956}
957
095e24b0
DB		 958static int
959ce4100_serial_setup(struct serial_private *priv,
960 const struct pciserial_board *board,
961 struct uart_port *port, int idx)
962{
963 int ret;
964
965 ret = setup_port(priv, port, 0, 0, board->reg_shift);
966 port->iotype = UPIO_MEM32;
967 port->type = PORT_XSCALE;
968 port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
969 port->regshift = 2;
970
971 return ret;
972}
973
b6adea33
MCC		 974static int skip_tx_en_setup(struct serial_private *priv,
975 const struct pciserial_board *board,
976 struct uart_port *port, int idx)
977{
978 port->flags |= UPF_NO_TXEN_TEST;
979 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
980 "[%04x:%04x] subsystem [%04x:%04x]\n",
981 priv->dev->vendor,
982 priv->dev->device,
983 priv->dev->subsystem_vendor,
984 priv->dev->subsystem_device);
985
986 return pci_default_setup(priv, board, port, idx);
987}
988
1da177e4
LT		 989/* This should be in linux/pci_ids.h */
990#define PCI_VENDOR_ID_SBSMODULARIO 0x124B
991#define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
992#define PCI_DEVICE_ID_OCTPRO 0x0001
993#define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
994#define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
995#define PCI_SUBDEVICE_ID_POCTAL232 0x0308
996#define PCI_SUBDEVICE_ID_POCTAL422 0x0408
78d70d48 997#define PCI_VENDOR_ID_ADVANTECH 0x13fe
095e24b0 998#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
78d70d48 999#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
66169ad1
YY		 1000#define PCI_DEVICE_ID_TITAN_200I 0x8028
1001#define PCI_DEVICE_ID_TITAN_400I 0x8048
1002#define PCI_DEVICE_ID_TITAN_800I 0x8088
1003#define PCI_DEVICE_ID_TITAN_800EH 0xA007
1004#define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1005#define PCI_DEVICE_ID_TITAN_400EH 0xA009
1006#define PCI_DEVICE_ID_TITAN_100E 0xA010
1007#define PCI_DEVICE_ID_TITAN_200E 0xA012
1008#define PCI_DEVICE_ID_TITAN_400E 0xA013
1009#define PCI_DEVICE_ID_TITAN_800E 0xA014
1010#define PCI_DEVICE_ID_TITAN_200EI 0xA016
1011#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
e847003f 1012#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1da177e4 1013
b76c5a07
CB		 1014/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1015#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1016
1da177e4
LT		 1017/*
1018 * Master list of serial port init/setup/exit quirks.
1019 * This does not describe the general nature of the port.
1020 * (ie, baud base, number and location of ports, etc)
1021 *
1022 * This list is ordered alphabetically by vendor then device.
1023 * Specific entries must come before more generic entries.
1024 */
7a63ce5a 1025static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
02c9b5cf
KJ		 1026 /*
1027 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1028 */
1029 {
1030 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1031 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1032 .subvendor = PCI_ANY_ID,
1033 .subdevice = PCI_ANY_ID,
1034 .setup = addidata_apci7800_setup,
1035 },
1da177e4 1036 /*
61a116ef 1037 * AFAVLAB cards - these may be called via parport_serial
1da177e4
LT		 1038 * It is not clear whether this applies to all products.
1039 */
1040 {
1041 .vendor = PCI_VENDOR_ID_AFAVLAB,
1042 .device = PCI_ANY_ID,
1043 .subvendor = PCI_ANY_ID,
1044 .subdevice = PCI_ANY_ID,
1045 .setup = afavlab_setup,
1046 },
1047 /*
1048 * HP Diva
1049 */
1050 {
1051 .vendor = PCI_VENDOR_ID_HP,
1052 .device = PCI_DEVICE_ID_HP_DIVA,
1053 .subvendor = PCI_ANY_ID,
1054 .subdevice = PCI_ANY_ID,
1055 .init = pci_hp_diva_init,
1056 .setup = pci_hp_diva_setup,
1057 },
1058 /*
1059 * Intel
1060 */
1061 {
1062 .vendor = PCI_VENDOR_ID_INTEL,
1063 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1064 .subvendor = 0xe4bf,
1065 .subdevice = PCI_ANY_ID,
1066 .init = pci_inteli960ni_init,
1067 .setup = pci_default_setup,
1068 },
b6adea33
MCC		 1069 {
1070 .vendor = PCI_VENDOR_ID_INTEL,
1071 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1072 .subvendor = PCI_ANY_ID,
1073 .subdevice = PCI_ANY_ID,
1074 .setup = skip_tx_en_setup,
1075 },
1076 {
1077 .vendor = PCI_VENDOR_ID_INTEL,
1078 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1079 .subvendor = PCI_ANY_ID,
1080 .subdevice = PCI_ANY_ID,
1081 .setup = skip_tx_en_setup,
1082 },
1083 {
1084 .vendor = PCI_VENDOR_ID_INTEL,
1085 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1086 .subvendor = PCI_ANY_ID,
1087 .subdevice = PCI_ANY_ID,
1088 .setup = skip_tx_en_setup,
1089 },
095e24b0
DB		 1090 {
1091 .vendor = PCI_VENDOR_ID_INTEL,
1092 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1093 .subvendor = PCI_ANY_ID,
1094 .subdevice = PCI_ANY_ID,
1095 .setup = ce4100_serial_setup,
1096 },
84f8c6fc
NV		 1097 /*
1098 * ITE
1099 */
1100 {
1101 .vendor = PCI_VENDOR_ID_ITE,
1102 .device = PCI_DEVICE_ID_ITE_8872,
1103 .subvendor = PCI_ANY_ID,
1104 .subdevice = PCI_ANY_ID,
1105 .init = pci_ite887x_init,
1106 .setup = pci_default_setup,
1107 .exit = __devexit_p(pci_ite887x_exit),
1108 },
46a0fac9
SB		 1109 /*
1110 * National Instruments
1111 */
04bf7e74
WP		 1112 {
1113 .vendor = PCI_VENDOR_ID_NI,
1114 .device = PCI_DEVICE_ID_NI_PCI23216,
1115 .subvendor = PCI_ANY_ID,
1116 .subdevice = PCI_ANY_ID,
1117 .init = pci_ni8420_init,
1118 .setup = pci_default_setup,
1119 .exit = __devexit_p(pci_ni8420_exit),
1120 },
1121 {
1122 .vendor = PCI_VENDOR_ID_NI,
1123 .device = PCI_DEVICE_ID_NI_PCI2328,
1124 .subvendor = PCI_ANY_ID,
1125 .subdevice = PCI_ANY_ID,
1126 .init = pci_ni8420_init,
1127 .setup = pci_default_setup,
1128 .exit = __devexit_p(pci_ni8420_exit),
1129 },
1130 {
1131 .vendor = PCI_VENDOR_ID_NI,
1132 .device = PCI_DEVICE_ID_NI_PCI2324,
1133 .subvendor = PCI_ANY_ID,
1134 .subdevice = PCI_ANY_ID,
1135 .init = pci_ni8420_init,
1136 .setup = pci_default_setup,
1137 .exit = __devexit_p(pci_ni8420_exit),
1138 },
1139 {
1140 .vendor = PCI_VENDOR_ID_NI,
1141 .device = PCI_DEVICE_ID_NI_PCI2322,
1142 .subvendor = PCI_ANY_ID,
1143 .subdevice = PCI_ANY_ID,
1144 .init = pci_ni8420_init,
1145 .setup = pci_default_setup,
1146 .exit = __devexit_p(pci_ni8420_exit),
1147 },
1148 {
1149 .vendor = PCI_VENDOR_ID_NI,
1150 .device = PCI_DEVICE_ID_NI_PCI2324I,
1151 .subvendor = PCI_ANY_ID,
1152 .subdevice = PCI_ANY_ID,
1153 .init = pci_ni8420_init,
1154 .setup = pci_default_setup,
1155 .exit = __devexit_p(pci_ni8420_exit),
1156 },
1157 {
1158 .vendor = PCI_VENDOR_ID_NI,
1159 .device = PCI_DEVICE_ID_NI_PCI2322I,
1160 .subvendor = PCI_ANY_ID,
1161 .subdevice = PCI_ANY_ID,
1162 .init = pci_ni8420_init,
1163 .setup = pci_default_setup,
1164 .exit = __devexit_p(pci_ni8420_exit),
1165 },
1166 {
1167 .vendor = PCI_VENDOR_ID_NI,
1168 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1169 .subvendor = PCI_ANY_ID,
1170 .subdevice = PCI_ANY_ID,
1171 .init = pci_ni8420_init,
1172 .setup = pci_default_setup,
1173 .exit = __devexit_p(pci_ni8420_exit),
1174 },
1175 {
1176 .vendor = PCI_VENDOR_ID_NI,
1177 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1178 .subvendor = PCI_ANY_ID,
1179 .subdevice = PCI_ANY_ID,
1180 .init = pci_ni8420_init,
1181 .setup = pci_default_setup,
1182 .exit = __devexit_p(pci_ni8420_exit),
1183 },
1184 {
1185 .vendor = PCI_VENDOR_ID_NI,
1186 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1187 .subvendor = PCI_ANY_ID,
1188 .subdevice = PCI_ANY_ID,
1189 .init = pci_ni8420_init,
1190 .setup = pci_default_setup,
1191 .exit = __devexit_p(pci_ni8420_exit),
1192 },
1193 {
1194 .vendor = PCI_VENDOR_ID_NI,
1195 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1196 .subvendor = PCI_ANY_ID,
1197 .subdevice = PCI_ANY_ID,
1198 .init = pci_ni8420_init,
1199 .setup = pci_default_setup,
1200 .exit = __devexit_p(pci_ni8420_exit),
1201 },
1202 {
1203 .vendor = PCI_VENDOR_ID_NI,
1204 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1205 .subvendor = PCI_ANY_ID,
1206 .subdevice = PCI_ANY_ID,
1207 .init = pci_ni8420_init,
1208 .setup = pci_default_setup,
1209 .exit = __devexit_p(pci_ni8420_exit),
1210 },
1211 {
1212 .vendor = PCI_VENDOR_ID_NI,
1213 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1214 .subvendor = PCI_ANY_ID,
1215 .subdevice = PCI_ANY_ID,
1216 .init = pci_ni8420_init,
1217 .setup = pci_default_setup,
1218 .exit = __devexit_p(pci_ni8420_exit),
1219 },
46a0fac9
SB		 1220 {
1221 .vendor = PCI_VENDOR_ID_NI,
1222 .device = PCI_ANY_ID,
1223 .subvendor = PCI_ANY_ID,
1224 .subdevice = PCI_ANY_ID,
1225 .init = pci_ni8430_init,
1226 .setup = pci_ni8430_setup,
1227 .exit = __devexit_p(pci_ni8430_exit),
1228 },
1da177e4
LT		 1229 /*
1230 * Panacom
1231 */
1232 {
1233 .vendor = PCI_VENDOR_ID_PANACOM,
1234 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1235 .subvendor = PCI_ANY_ID,
1236 .subdevice = PCI_ANY_ID,
1237 .init = pci_plx9050_init,
1238 .setup = pci_default_setup,
1239 .exit = __devexit_p(pci_plx9050_exit),
5756ee99 1240 },
1da177e4
LT		 1241 {
1242 .vendor = PCI_VENDOR_ID_PANACOM,
1243 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1244 .subvendor = PCI_ANY_ID,
1245 .subdevice = PCI_ANY_ID,
1246 .init = pci_plx9050_init,
1247 .setup = pci_default_setup,
1248 .exit = __devexit_p(pci_plx9050_exit),
1249 },
1250 /*
1251 * PLX
1252 */
48212008
TH		 1253 {
1254 .vendor = PCI_VENDOR_ID_PLX,
1255 .device = PCI_DEVICE_ID_PLX_9030,
1256 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1257 .subdevice = PCI_ANY_ID,
1258 .setup = pci_default_setup,
1259 },
add7b58e
BH		 1260 {
1261 .vendor = PCI_VENDOR_ID_PLX,
1262 .device = PCI_DEVICE_ID_PLX_9050,
1263 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1264 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1265 .init = pci_plx9050_init,
1266 .setup = pci_default_setup,
1267 .exit = __devexit_p(pci_plx9050_exit),
1268 },
1da177e4
LT		 1269 {
1270 .vendor = PCI_VENDOR_ID_PLX,
1271 .device = PCI_DEVICE_ID_PLX_9050,
1272 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1273 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1274 .init = pci_plx9050_init,
1275 .setup = pci_default_setup,
1276 .exit = __devexit_p(pci_plx9050_exit),
1277 },
b76c5a07
CB		 1278 {
1279 .vendor = PCI_VENDOR_ID_PLX,
1280 .device = PCI_DEVICE_ID_PLX_9050,
1281 .subvendor = PCI_VENDOR_ID_PLX,
1282 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1283 .init = pci_plx9050_init,
1284 .setup = pci_default_setup,
1285 .exit = __devexit_p(pci_plx9050_exit),
1286 },
1da177e4
LT		 1287 {
1288 .vendor = PCI_VENDOR_ID_PLX,
1289 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1290 .subvendor = PCI_VENDOR_ID_PLX,
1291 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1292 .init = pci_plx9050_init,
1293 .setup = pci_default_setup,
1294 .exit = __devexit_p(pci_plx9050_exit),
1295 },
1296 /*
1297 * SBS Technologies, Inc., PMC-OCTALPRO 232
1298 */
1299 {
1300 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1301 .device = PCI_DEVICE_ID_OCTPRO,
1302 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1303 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1304 .init = sbs_init,
1305 .setup = sbs_setup,
1306 .exit = __devexit_p(sbs_exit),
1307 },
1308 /*
1309 * SBS Technologies, Inc., PMC-OCTALPRO 422
1310 */
1311 {
1312 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1313 .device = PCI_DEVICE_ID_OCTPRO,
1314 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1315 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1316 .init = sbs_init,
1317 .setup = sbs_setup,
1318 .exit = __devexit_p(sbs_exit),
1319 },
1320 /*
1321 * SBS Technologies, Inc., P-Octal 232
1322 */
1323 {
1324 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1325 .device = PCI_DEVICE_ID_OCTPRO,
1326 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1327 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1328 .init = sbs_init,
1329 .setup = sbs_setup,
1330 .exit = __devexit_p(sbs_exit),
1331 },
1332 /*
1333 * SBS Technologies, Inc., P-Octal 422
1334 */
1335 {
1336 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1337 .device = PCI_DEVICE_ID_OCTPRO,
1338 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1339 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1340 .init = sbs_init,
1341 .setup = sbs_setup,
1342 .exit = __devexit_p(sbs_exit),
1343 },
1da177e4 1344 /*
61a116ef 1345 * SIIG cards - these may be called via parport_serial
1da177e4
LT		 1346 */
1347 {
1348 .vendor = PCI_VENDOR_ID_SIIG,
67d74b87 1349 .device = PCI_ANY_ID,
1da177e4
LT		 1350 .subvendor = PCI_ANY_ID,
1351 .subdevice = PCI_ANY_ID,
67d74b87 1352 .init = pci_siig_init,
3ec9c594 1353 .setup = pci_siig_setup,
1da177e4
LT		 1354 },
1355 /*
1356 * Titan cards
1357 */
1358 {
1359 .vendor = PCI_VENDOR_ID_TITAN,
1360 .device = PCI_DEVICE_ID_TITAN_400L,
1361 .subvendor = PCI_ANY_ID,
1362 .subdevice = PCI_ANY_ID,
1363 .setup = titan_400l_800l_setup,
1364 },
1365 {
1366 .vendor = PCI_VENDOR_ID_TITAN,
1367 .device = PCI_DEVICE_ID_TITAN_800L,
1368 .subvendor = PCI_ANY_ID,
1369 .subdevice = PCI_ANY_ID,
1370 .setup = titan_400l_800l_setup,
1371 },
1372 /*
1373 * Timedia cards
1374 */
1375 {
1376 .vendor = PCI_VENDOR_ID_TIMEDIA,
1377 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1378 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1379 .subdevice = PCI_ANY_ID,
1380 .init = pci_timedia_init,
1381 .setup = pci_timedia_setup,
1382 },
1383 {
1384 .vendor = PCI_VENDOR_ID_TIMEDIA,
1385 .device = PCI_ANY_ID,
1386 .subvendor = PCI_ANY_ID,
1387 .subdevice = PCI_ANY_ID,
1388 .setup = pci_timedia_setup,
1389 },
1390 /*
1391 * Xircom cards
1392 */
1393 {
1394 .vendor = PCI_VENDOR_ID_XIRCOM,
1395 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1396 .subvendor = PCI_ANY_ID,
1397 .subdevice = PCI_ANY_ID,
1398 .init = pci_xircom_init,
1399 .setup = pci_default_setup,
1400 },
1401 /*
61a116ef 1402 * Netmos cards - these may be called via parport_serial
1da177e4
LT		 1403 */
1404 {
1405 .vendor = PCI_VENDOR_ID_NETMOS,
1406 .device = PCI_ANY_ID,
1407 .subvendor = PCI_ANY_ID,
1408 .subdevice = PCI_ANY_ID,
1409 .init = pci_netmos_init,
1410 .setup = pci_default_setup,
1411 },
9f2a036a
RK		 1412 /*
1413 * For Oxford Semiconductor and Mainpine
1414 */
1415 {
1416 .vendor = PCI_VENDOR_ID_OXSEMI,
1417 .device = PCI_ANY_ID,
1418 .subvendor = PCI_ANY_ID,
1419 .subdevice = PCI_ANY_ID,
1420 .init = pci_oxsemi_tornado_init,
1421 .setup = pci_default_setup,
1422 },
1423 {
1424 .vendor = PCI_VENDOR_ID_MAINPINE,
1425 .device = PCI_ANY_ID,
1426 .subvendor = PCI_ANY_ID,
1427 .subdevice = PCI_ANY_ID,
1428 .init = pci_oxsemi_tornado_init,
1429 .setup = pci_default_setup,
1430 },
1da177e4
LT		 1431 /*
1432 * Default "match everything" terminator entry
1433 */
1434 {
1435 .vendor = PCI_ANY_ID,
1436 .device = PCI_ANY_ID,
1437 .subvendor = PCI_ANY_ID,
1438 .subdevice = PCI_ANY_ID,
1439 .setup = pci_default_setup,
1440 }
1441};
1442
1443static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1444{
1445 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1446}
1447
1448static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1449{
1450 struct pci_serial_quirk *quirk;
1451
1452 for (quirk = pci_serial_quirks; ; quirk++)
1453 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1454 quirk_id_matches(quirk->device, dev->device) &&
1455 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1456 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
5756ee99 1457 break;
1da177e4
LT		 1458 return quirk;
1459}
1460
dd68e88c 1461static inline int get_pci_irq(struct pci_dev *dev,
975a1a7d 1462 const struct pciserial_board *board)
1da177e4
LT		 1463{
1464 if (board->flags & FL_NOIRQ)
1465 return 0;
1466 else
1467 return dev->irq;
1468}
1469
1470/*
1471 * This is the configuration table for all of the PCI serial boards
1472 * which we support. It is directly indexed by the pci_board_num_t enum
1473 * value, which is encoded in the pci_device_id PCI probe table's
1474 * driver_data member.
1475 *
1476 * The makeup of these names are:
26e92861 1477 * pbn_bn{_bt}_n_baud{_offsetinhex}
1da177e4 1478 *
26e92861
GH		 1479 * bn = PCI BAR number
1480 * bt = Index using PCI BARs
1481 * n = number of serial ports
1482 * baud = baud rate
1483 * offsetinhex = offset for each sequential port (in hex)
1da177e4 1484 *
26e92861 1485 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
f1690f37 1486 *
1da177e4
LT		 1487 * Please note: in theory if n = 1, _bt infix should make no difference.
1488 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1489 */
1490enum pci_board_num_t {
1491 pbn_default = 0,
1492
1493 pbn_b0_1_115200,
1494 pbn_b0_2_115200,
1495 pbn_b0_4_115200,
1496 pbn_b0_5_115200,
bf0df636 1497 pbn_b0_8_115200,
1da177e4
LT		 1498
1499 pbn_b0_1_921600,
1500 pbn_b0_2_921600,
1501 pbn_b0_4_921600,
1502
db1de159
DR		 1503 pbn_b0_2_1130000,
1504
fbc0dc0d
AP		 1505 pbn_b0_4_1152000,
1506
26e92861
GH		 1507 pbn_b0_2_1843200,
1508 pbn_b0_4_1843200,
1509
1510 pbn_b0_2_1843200_200,
1511 pbn_b0_4_1843200_200,
1512 pbn_b0_8_1843200_200,
1513
7106b4e3
LH		 1514 pbn_b0_1_4000000,
1515
1da177e4
LT		 1516 pbn_b0_bt_1_115200,
1517 pbn_b0_bt_2_115200,
ac6ec5b1 1518 pbn_b0_bt_4_115200,
1da177e4
LT		 1519 pbn_b0_bt_8_115200,
1520
1521 pbn_b0_bt_1_460800,
1522 pbn_b0_bt_2_460800,
1523 pbn_b0_bt_4_460800,
1524
1525 pbn_b0_bt_1_921600,
1526 pbn_b0_bt_2_921600,
1527 pbn_b0_bt_4_921600,
1528 pbn_b0_bt_8_921600,
1529
1530 pbn_b1_1_115200,
1531 pbn_b1_2_115200,
1532 pbn_b1_4_115200,
1533 pbn_b1_8_115200,
04bf7e74 1534 pbn_b1_16_115200,
1da177e4
LT		 1535
1536 pbn_b1_1_921600,
1537 pbn_b1_2_921600,
1538 pbn_b1_4_921600,
1539 pbn_b1_8_921600,
1540
26e92861
GH		 1541 pbn_b1_2_1250000,
1542
84f8c6fc 1543 pbn_b1_bt_1_115200,
04bf7e74
WP		 1544 pbn_b1_bt_2_115200,
1545 pbn_b1_bt_4_115200,
1546
1da177e4
LT		 1547 pbn_b1_bt_2_921600,
1548
1549 pbn_b1_1_1382400,
1550 pbn_b1_2_1382400,
1551 pbn_b1_4_1382400,
1552 pbn_b1_8_1382400,
1553
1554 pbn_b2_1_115200,
737c1756 1555 pbn_b2_2_115200,
a9cccd34 1556 pbn_b2_4_115200,
1da177e4
LT		 1557 pbn_b2_8_115200,
1558
1559 pbn_b2_1_460800,
1560 pbn_b2_4_460800,
1561 pbn_b2_8_460800,
1562 pbn_b2_16_460800,
1563
1564 pbn_b2_1_921600,
1565 pbn_b2_4_921600,
1566 pbn_b2_8_921600,
1567
e847003f
LB		 1568 pbn_b2_8_1152000,
1569
1da177e4
LT		 1570 pbn_b2_bt_1_115200,
1571 pbn_b2_bt_2_115200,
1572 pbn_b2_bt_4_115200,
1573
1574 pbn_b2_bt_2_921600,
1575 pbn_b2_bt_4_921600,
1576
d9004eb4 1577 pbn_b3_2_115200,
1da177e4
LT		 1578 pbn_b3_4_115200,
1579 pbn_b3_8_115200,
1580
66169ad1
YY		 1581 pbn_b4_bt_2_921600,
1582 pbn_b4_bt_4_921600,
1583 pbn_b4_bt_8_921600,
1584
1da177e4
LT		 1585 /*
1586 * Board-specific versions.
1587 */
1588 pbn_panacom,
1589 pbn_panacom2,
1590 pbn_panacom4,
add7b58e 1591 pbn_exsys_4055,
1da177e4
LT		 1592 pbn_plx_romulus,
1593 pbn_oxsemi,
7106b4e3
LH		 1594 pbn_oxsemi_1_4000000,
1595 pbn_oxsemi_2_4000000,
1596 pbn_oxsemi_4_4000000,
1597 pbn_oxsemi_8_4000000,
1da177e4
LT		 1598 pbn_intel_i960,
1599 pbn_sgi_ioc3,
1da177e4
LT		 1600 pbn_computone_4,
1601 pbn_computone_6,
1602 pbn_computone_8,
1603 pbn_sbsxrsio,
1604 pbn_exar_XR17C152,
1605 pbn_exar_XR17C154,
1606 pbn_exar_XR17C158,
c68d2b15 1607 pbn_exar_ibm_saturn,
aa798505 1608 pbn_pasemi_1682M,
46a0fac9
SB		 1609 pbn_ni8430_2,
1610 pbn_ni8430_4,
1611 pbn_ni8430_8,
1612 pbn_ni8430_16,
1b62cbf2
KJ		 1613 pbn_ADDIDATA_PCIe_1_3906250,
1614 pbn_ADDIDATA_PCIe_2_3906250,
1615 pbn_ADDIDATA_PCIe_4_3906250,
1616 pbn_ADDIDATA_PCIe_8_3906250,
095e24b0 1617 pbn_ce4100_1_115200,
1da177e4
LT		 1618};
1619
1620/*
1621 * uart_offset - the space between channels
1622 * reg_shift - describes how the UART registers are mapped
1623 * to PCI memory by the card.
1624 * For example IER register on SBS, Inc. PMC-OctPro is located at
1625 * offset 0x10 from the UART base, while UART_IER is defined as 1
1626 * in include/linux/serial_reg.h,
1627 * see first lines of serial_in() and serial_out() in 8250.c
1628*/
1629
1c7c1fe5 1630static struct pciserial_board pci_boards[] __devinitdata = {
1da177e4
LT		 1631 [pbn_default] = {
1632 .flags = FL_BASE0,
1633 .num_ports = 1,
1634 .base_baud = 115200,
1635 .uart_offset = 8,
1636 },
1637 [pbn_b0_1_115200] = {
1638 .flags = FL_BASE0,
1639 .num_ports = 1,
1640 .base_baud = 115200,
1641 .uart_offset = 8,
1642 },
1643 [pbn_b0_2_115200] = {
1644 .flags = FL_BASE0,
1645 .num_ports = 2,
1646 .base_baud = 115200,
1647 .uart_offset = 8,
1648 },
1649 [pbn_b0_4_115200] = {
1650 .flags = FL_BASE0,
1651 .num_ports = 4,
1652 .base_baud = 115200,
1653 .uart_offset = 8,
1654 },
1655 [pbn_b0_5_115200] = {
1656 .flags = FL_BASE0,
1657 .num_ports = 5,
1658 .base_baud = 115200,
1659 .uart_offset = 8,
1660 },
bf0df636
AC		 1661 [pbn_b0_8_115200] = {
1662 .flags = FL_BASE0,
1663 .num_ports = 8,
1664 .base_baud = 115200,
1665 .uart_offset = 8,
1666 },
1da177e4
LT		 1667 [pbn_b0_1_921600] = {
1668 .flags = FL_BASE0,
1669 .num_ports = 1,
1670 .base_baud = 921600,
1671 .uart_offset = 8,
1672 },
1673 [pbn_b0_2_921600] = {
1674 .flags = FL_BASE0,
1675 .num_ports = 2,
1676 .base_baud = 921600,
1677 .uart_offset = 8,
1678 },
1679 [pbn_b0_4_921600] = {
1680 .flags = FL_BASE0,
1681 .num_ports = 4,
1682 .base_baud = 921600,
1683 .uart_offset = 8,
1684 },
db1de159
DR		 1685
1686 [pbn_b0_2_1130000] = {
1687 .flags = FL_BASE0,
1688 .num_ports = 2,
1689 .base_baud = 1130000,
1690 .uart_offset = 8,
1691 },
1692
fbc0dc0d
AP		 1693 [pbn_b0_4_1152000] = {
1694 .flags = FL_BASE0,
1695 .num_ports = 4,
1696 .base_baud = 1152000,
1697 .uart_offset = 8,
1698 },
1da177e4 1699
26e92861
GH		 1700 [pbn_b0_2_1843200] = {
1701 .flags = FL_BASE0,
1702 .num_ports = 2,
1703 .base_baud = 1843200,
1704 .uart_offset = 8,
1705 },
1706 [pbn_b0_4_1843200] = {
1707 .flags = FL_BASE0,
1708 .num_ports = 4,
1709 .base_baud = 1843200,
1710 .uart_offset = 8,
1711 },
1712
1713 [pbn_b0_2_1843200_200] = {
1714 .flags = FL_BASE0,
1715 .num_ports = 2,
1716 .base_baud = 1843200,
1717 .uart_offset = 0x200,
1718 },
1719 [pbn_b0_4_1843200_200] = {
1720 .flags = FL_BASE0,
1721 .num_ports = 4,
1722 .base_baud = 1843200,
1723 .uart_offset = 0x200,
1724 },
1725 [pbn_b0_8_1843200_200] = {
1726 .flags = FL_BASE0,
1727 .num_ports = 8,
1728 .base_baud = 1843200,
1729 .uart_offset = 0x200,
1730 },
7106b4e3
LH		 1731 [pbn_b0_1_4000000] = {
1732 .flags = FL_BASE0,
1733 .num_ports = 1,
1734 .base_baud = 4000000,
1735 .uart_offset = 8,
1736 },
26e92861 1737
1da177e4
LT		 1738 [pbn_b0_bt_1_115200] = {
1739 .flags = FL_BASE0|FL_BASE_BARS,
1740 .num_ports = 1,
1741 .base_baud = 115200,
1742 .uart_offset = 8,
1743 },
1744 [pbn_b0_bt_2_115200] = {
1745 .flags = FL_BASE0|FL_BASE_BARS,
1746 .num_ports = 2,
1747 .base_baud = 115200,
1748 .uart_offset = 8,
1749 },
ac6ec5b1
IS		 1750 [pbn_b0_bt_4_115200] = {
1751 .flags = FL_BASE0|FL_BASE_BARS,
1752 .num_ports = 4,
1753 .base_baud = 115200,
1754 .uart_offset = 8,
1755 },
1da177e4
LT		 1756 [pbn_b0_bt_8_115200] = {
1757 .flags = FL_BASE0|FL_BASE_BARS,
1758 .num_ports = 8,
1759 .base_baud = 115200,
1760 .uart_offset = 8,
1761 },
1762
1763 [pbn_b0_bt_1_460800] = {
1764 .flags = FL_BASE0|FL_BASE_BARS,
1765 .num_ports = 1,
1766 .base_baud = 460800,
1767 .uart_offset = 8,
1768 },
1769 [pbn_b0_bt_2_460800] = {
1770 .flags = FL_BASE0|FL_BASE_BARS,
1771 .num_ports = 2,
1772 .base_baud = 460800,
1773 .uart_offset = 8,
1774 },
1775 [pbn_b0_bt_4_460800] = {
1776 .flags = FL_BASE0|FL_BASE_BARS,
1777 .num_ports = 4,
1778 .base_baud = 460800,
1779 .uart_offset = 8,
1780 },
1781
1782 [pbn_b0_bt_1_921600] = {
1783 .flags = FL_BASE0|FL_BASE_BARS,
1784 .num_ports = 1,
1785 .base_baud = 921600,
1786 .uart_offset = 8,
1787 },
1788 [pbn_b0_bt_2_921600] = {
1789 .flags = FL_BASE0|FL_BASE_BARS,
1790 .num_ports = 2,
1791 .base_baud = 921600,
1792 .uart_offset = 8,
1793 },
1794 [pbn_b0_bt_4_921600] = {
1795 .flags = FL_BASE0|FL_BASE_BARS,
1796 .num_ports = 4,
1797 .base_baud = 921600,
1798 .uart_offset = 8,
1799 },
1800 [pbn_b0_bt_8_921600] = {
1801 .flags = FL_BASE0|FL_BASE_BARS,
1802 .num_ports = 8,
1803 .base_baud = 921600,
1804 .uart_offset = 8,
1805 },
1806
1807 [pbn_b1_1_115200] = {
1808 .flags = FL_BASE1,
1809 .num_ports = 1,
1810 .base_baud = 115200,
1811 .uart_offset = 8,
1812 },
1813 [pbn_b1_2_115200] = {
1814 .flags = FL_BASE1,
1815 .num_ports = 2,
1816 .base_baud = 115200,
1817 .uart_offset = 8,
1818 },
1819 [pbn_b1_4_115200] = {
1820 .flags = FL_BASE1,
1821 .num_ports = 4,
1822 .base_baud = 115200,
1823 .uart_offset = 8,
1824 },
1825 [pbn_b1_8_115200] = {
1826 .flags = FL_BASE1,
1827 .num_ports = 8,
1828 .base_baud = 115200,
1829 .uart_offset = 8,
1830 },
04bf7e74
WP		 1831 [pbn_b1_16_115200] = {
1832 .flags = FL_BASE1,
1833 .num_ports = 16,
1834 .base_baud = 115200,
1835 .uart_offset = 8,
1836 },
1da177e4
LT		 1837
1838 [pbn_b1_1_921600] = {
1839 .flags = FL_BASE1,
1840 .num_ports = 1,
1841 .base_baud = 921600,
1842 .uart_offset = 8,
1843 },
1844 [pbn_b1_2_921600] = {
1845 .flags = FL_BASE1,
1846 .num_ports = 2,
1847 .base_baud = 921600,
1848 .uart_offset = 8,
1849 },
1850 [pbn_b1_4_921600] = {
1851 .flags = FL_BASE1,
1852 .num_ports = 4,
1853 .base_baud = 921600,
1854 .uart_offset = 8,
1855 },
1856 [pbn_b1_8_921600] = {
1857 .flags = FL_BASE1,
1858 .num_ports = 8,
1859 .base_baud = 921600,
1860 .uart_offset = 8,
1861 },
26e92861
GH		 1862 [pbn_b1_2_1250000] = {
1863 .flags = FL_BASE1,
1864 .num_ports = 2,
1865 .base_baud = 1250000,
1866 .uart_offset = 8,
1867 },
1da177e4 1868
84f8c6fc
NV		 1869 [pbn_b1_bt_1_115200] = {
1870 .flags = FL_BASE1|FL_BASE_BARS,
1871 .num_ports = 1,
1872 .base_baud = 115200,
1873 .uart_offset = 8,
1874 },
04bf7e74
WP		 1875 [pbn_b1_bt_2_115200] = {
1876 .flags = FL_BASE1|FL_BASE_BARS,
1877 .num_ports = 2,
1878 .base_baud = 115200,
1879 .uart_offset = 8,
1880 },
1881 [pbn_b1_bt_4_115200] = {
1882 .flags = FL_BASE1|FL_BASE_BARS,
1883 .num_ports = 4,
1884 .base_baud = 115200,
1885 .uart_offset = 8,
1886 },
84f8c6fc 1887
1da177e4
LT		 1888 [pbn_b1_bt_2_921600] = {
1889 .flags = FL_BASE1|FL_BASE_BARS,
1890 .num_ports = 2,
1891 .base_baud = 921600,
1892 .uart_offset = 8,
1893 },
1894
1895 [pbn_b1_1_1382400] = {
1896 .flags = FL_BASE1,
1897 .num_ports = 1,
1898 .base_baud = 1382400,
1899 .uart_offset = 8,
1900 },
1901 [pbn_b1_2_1382400] = {
1902 .flags = FL_BASE1,
1903 .num_ports = 2,
1904 .base_baud = 1382400,
1905 .uart_offset = 8,
1906 },
1907 [pbn_b1_4_1382400] = {
1908 .flags = FL_BASE1,
1909 .num_ports = 4,
1910 .base_baud = 1382400,
1911 .uart_offset = 8,
1912 },
1913 [pbn_b1_8_1382400] = {
1914 .flags = FL_BASE1,
1915 .num_ports = 8,
1916 .base_baud = 1382400,
1917 .uart_offset = 8,
1918 },
1919
1920 [pbn_b2_1_115200] = {
1921 .flags = FL_BASE2,
1922 .num_ports = 1,
1923 .base_baud = 115200,
1924 .uart_offset = 8,
1925 },
737c1756
PH		 1926 [pbn_b2_2_115200] = {
1927 .flags = FL_BASE2,
1928 .num_ports = 2,
1929 .base_baud = 115200,
1930 .uart_offset = 8,
1931 },
a9cccd34
MF		 1932 [pbn_b2_4_115200] = {
1933 .flags = FL_BASE2,
1934 .num_ports = 4,
1935 .base_baud = 115200,
1936 .uart_offset = 8,
1937 },
1da177e4
LT		 1938 [pbn_b2_8_115200] = {
1939 .flags = FL_BASE2,
1940 .num_ports = 8,
1941 .base_baud = 115200,
1942 .uart_offset = 8,
1943 },
1944
1945 [pbn_b2_1_460800] = {
1946 .flags = FL_BASE2,
1947 .num_ports = 1,
1948 .base_baud = 460800,
1949 .uart_offset = 8,
1950 },
1951 [pbn_b2_4_460800] = {
1952 .flags = FL_BASE2,
1953 .num_ports = 4,
1954 .base_baud = 460800,
1955 .uart_offset = 8,
1956 },
1957 [pbn_b2_8_460800] = {
1958 .flags = FL_BASE2,
1959 .num_ports = 8,
1960 .base_baud = 460800,
1961 .uart_offset = 8,
1962 },
1963 [pbn_b2_16_460800] = {
1964 .flags = FL_BASE2,
1965 .num_ports = 16,
1966 .base_baud = 460800,
1967 .uart_offset = 8,
1968 },
1969
1970 [pbn_b2_1_921600] = {
1971 .flags = FL_BASE2,
1972 .num_ports = 1,
1973 .base_baud = 921600,
1974 .uart_offset = 8,
1975 },
1976 [pbn_b2_4_921600] = {
1977 .flags = FL_BASE2,
1978 .num_ports = 4,
1979 .base_baud = 921600,
1980 .uart_offset = 8,
1981 },
1982 [pbn_b2_8_921600] = {
1983 .flags = FL_BASE2,
1984 .num_ports = 8,
1985 .base_baud = 921600,
1986 .uart_offset = 8,
1987 },
1988
e847003f
LB		 1989 [pbn_b2_8_1152000] = {
1990 .flags = FL_BASE2,
1991 .num_ports = 8,
1992 .base_baud = 1152000,
1993 .uart_offset = 8,
1994 },
1995
1da177e4
LT		 1996 [pbn_b2_bt_1_115200] = {
1997 .flags = FL_BASE2|FL_BASE_BARS,
1998 .num_ports = 1,
1999 .base_baud = 115200,
2000 .uart_offset = 8,
2001 },
2002 [pbn_b2_bt_2_115200] = {
2003 .flags = FL_BASE2|FL_BASE_BARS,
2004 .num_ports = 2,
2005 .base_baud = 115200,
2006 .uart_offset = 8,
2007 },
2008 [pbn_b2_bt_4_115200] = {
2009 .flags = FL_BASE2|FL_BASE_BARS,
2010 .num_ports = 4,
2011 .base_baud = 115200,
2012 .uart_offset = 8,
2013 },
2014
2015 [pbn_b2_bt_2_921600] = {
2016 .flags = FL_BASE2|FL_BASE_BARS,
2017 .num_ports = 2,
2018 .base_baud = 921600,
2019 .uart_offset = 8,
2020 },
2021 [pbn_b2_bt_4_921600] = {
2022 .flags = FL_BASE2|FL_BASE_BARS,
2023 .num_ports = 4,
2024 .base_baud = 921600,
2025 .uart_offset = 8,
2026 },
2027
d9004eb4
ABL		 2028 [pbn_b3_2_115200] = {
2029 .flags = FL_BASE3,
2030 .num_ports = 2,
2031 .base_baud = 115200,
2032 .uart_offset = 8,
2033 },
1da177e4
LT		 2034 [pbn_b3_4_115200] = {
2035 .flags = FL_BASE3,
2036 .num_ports = 4,
2037 .base_baud = 115200,
2038 .uart_offset = 8,
2039 },
2040 [pbn_b3_8_115200] = {
2041 .flags = FL_BASE3,
2042 .num_ports = 8,
2043 .base_baud = 115200,
2044 .uart_offset = 8,
2045 },
2046
66169ad1
YY		 2047 [pbn_b4_bt_2_921600] = {
2048 .flags = FL_BASE4,
2049 .num_ports = 2,
2050 .base_baud = 921600,
2051 .uart_offset = 8,
2052 },
2053 [pbn_b4_bt_4_921600] = {
2054 .flags = FL_BASE4,
2055 .num_ports = 4,
2056 .base_baud = 921600,
2057 .uart_offset = 8,
2058 },
2059 [pbn_b4_bt_8_921600] = {
2060 .flags = FL_BASE4,
2061 .num_ports = 8,
2062 .base_baud = 921600,
2063 .uart_offset = 8,
2064 },
2065
1da177e4
LT		 2066 /*
2067 * Entries following this are board-specific.
2068 */
2069
2070 /*
2071 * Panacom - IOMEM
2072 */
2073 [pbn_panacom] = {
2074 .flags = FL_BASE2,
2075 .num_ports = 2,
2076 .base_baud = 921600,
2077 .uart_offset = 0x400,
2078 .reg_shift = 7,
2079 },
2080 [pbn_panacom2] = {
2081 .flags = FL_BASE2|FL_BASE_BARS,
2082 .num_ports = 2,
2083 .base_baud = 921600,
2084 .uart_offset = 0x400,
2085 .reg_shift = 7,
2086 },
2087 [pbn_panacom4] = {
2088 .flags = FL_BASE2|FL_BASE_BARS,
2089 .num_ports = 4,
2090 .base_baud = 921600,
2091 .uart_offset = 0x400,
2092 .reg_shift = 7,
2093 },
2094
add7b58e
BH		 2095 [pbn_exsys_4055] = {
2096 .flags = FL_BASE2,
2097 .num_ports = 4,
2098 .base_baud = 115200,
2099 .uart_offset = 8,
2100 },
2101
1da177e4
LT		 2102 /* I think this entry is broken - the first_offset looks wrong --rmk */
2103 [pbn_plx_romulus] = {
2104 .flags = FL_BASE2,
2105 .num_ports = 4,
2106 .base_baud = 921600,
2107 .uart_offset = 8 << 2,
2108 .reg_shift = 2,
2109 .first_offset = 0x03,
2110 },
2111
2112 /*
2113 * This board uses the size of PCI Base region 0 to
2114 * signal now many ports are available
2115 */
2116 [pbn_oxsemi] = {
2117 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2118 .num_ports = 32,
2119 .base_baud = 115200,
2120 .uart_offset = 8,
2121 },
7106b4e3
LH		 2122 [pbn_oxsemi_1_4000000] = {
2123 .flags = FL_BASE0,
2124 .num_ports = 1,
2125 .base_baud = 4000000,
2126 .uart_offset = 0x200,
2127 .first_offset = 0x1000,
2128 },
2129 [pbn_oxsemi_2_4000000] = {
2130 .flags = FL_BASE0,
2131 .num_ports = 2,
2132 .base_baud = 4000000,
2133 .uart_offset = 0x200,
2134 .first_offset = 0x1000,
2135 },
2136 [pbn_oxsemi_4_4000000] = {
2137 .flags = FL_BASE0,
2138 .num_ports = 4,
2139 .base_baud = 4000000,
2140 .uart_offset = 0x200,
2141 .first_offset = 0x1000,
2142 },
2143 [pbn_oxsemi_8_4000000] = {
2144 .flags = FL_BASE0,
2145 .num_ports = 8,
2146 .base_baud = 4000000,
2147 .uart_offset = 0x200,
2148 .first_offset = 0x1000,
2149 },
2150
1da177e4
LT		 2151
2152 /*
2153 * EKF addition for i960 Boards form EKF with serial port.
2154 * Max 256 ports.
2155 */
2156 [pbn_intel_i960] = {
2157 .flags = FL_BASE0,
2158 .num_ports = 32,
2159 .base_baud = 921600,
2160 .uart_offset = 8 << 2,
2161 .reg_shift = 2,
2162 .first_offset = 0x10000,
2163 },
2164 [pbn_sgi_ioc3] = {
2165 .flags = FL_BASE0|FL_NOIRQ,
2166 .num_ports = 1,
2167 .base_baud = 458333,
2168 .uart_offset = 8,
2169 .reg_shift = 0,
2170 .first_offset = 0x20178,
2171 },
2172
1da177e4
LT		 2173 /*
2174 * Computone - uses IOMEM.
2175 */
2176 [pbn_computone_4] = {
2177 .flags = FL_BASE0,
2178 .num_ports = 4,
2179 .base_baud = 921600,
2180 .uart_offset = 0x40,
2181 .reg_shift = 2,
2182 .first_offset = 0x200,
2183 },
2184 [pbn_computone_6] = {
2185 .flags = FL_BASE0,
2186 .num_ports = 6,
2187 .base_baud = 921600,
2188 .uart_offset = 0x40,
2189 .reg_shift = 2,
2190 .first_offset = 0x200,
2191 },
2192 [pbn_computone_8] = {
2193 .flags = FL_BASE0,
2194 .num_ports = 8,
2195 .base_baud = 921600,
2196 .uart_offset = 0x40,
2197 .reg_shift = 2,
2198 .first_offset = 0x200,
2199 },
2200 [pbn_sbsxrsio] = {
2201 .flags = FL_BASE0,
2202 .num_ports = 8,
2203 .base_baud = 460800,
2204 .uart_offset = 256,
2205 .reg_shift = 4,
2206 },
2207 /*
2208 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2209 * Only basic 16550A support.
2210 * XR17C15[24] are not tested, but they should work.
2211 */
2212 [pbn_exar_XR17C152] = {
2213 .flags = FL_BASE0,
2214 .num_ports = 2,
2215 .base_baud = 921600,
2216 .uart_offset = 0x200,
2217 },
2218 [pbn_exar_XR17C154] = {
2219 .flags = FL_BASE0,
2220 .num_ports = 4,
2221 .base_baud = 921600,
2222 .uart_offset = 0x200,
2223 },
2224 [pbn_exar_XR17C158] = {
2225 .flags = FL_BASE0,
2226 .num_ports = 8,
2227 .base_baud = 921600,
2228 .uart_offset = 0x200,
2229 },
c68d2b15
BH		 2230 [pbn_exar_ibm_saturn] = {
2231 .flags = FL_BASE0,
2232 .num_ports = 1,
2233 .base_baud = 921600,
2234 .uart_offset = 0x200,
2235 },
2236
aa798505
OJ		 2237 /*
2238 * PA Semi PWRficient PA6T-1682M on-chip UART
2239 */
2240 [pbn_pasemi_1682M] = {
2241 .flags = FL_BASE0,
2242 .num_ports = 1,
2243 .base_baud = 8333333,
2244 },
46a0fac9
SB		 2245 /*
2246 * National Instruments 843x
2247 */
2248 [pbn_ni8430_16] = {
2249 .flags = FL_BASE0,
2250 .num_ports = 16,
2251 .base_baud = 3686400,
2252 .uart_offset = 0x10,
2253 .first_offset = 0x800,
2254 },
2255 [pbn_ni8430_8] = {
2256 .flags = FL_BASE0,
2257 .num_ports = 8,
2258 .base_baud = 3686400,
2259 .uart_offset = 0x10,
2260 .first_offset = 0x800,
2261 },
2262 [pbn_ni8430_4] = {
2263 .flags = FL_BASE0,
2264 .num_ports = 4,
2265 .base_baud = 3686400,
2266 .uart_offset = 0x10,
2267 .first_offset = 0x800,
2268 },
2269 [pbn_ni8430_2] = {
2270 .flags = FL_BASE0,
2271 .num_ports = 2,
2272 .base_baud = 3686400,
2273 .uart_offset = 0x10,
2274 .first_offset = 0x800,
2275 },
1b62cbf2
KJ		 2276 /*
2277 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2278 */
2279 [pbn_ADDIDATA_PCIe_1_3906250] = {
2280 .flags = FL_BASE0,
2281 .num_ports = 1,
2282 .base_baud = 3906250,
2283 .uart_offset = 0x200,
2284 .first_offset = 0x1000,
2285 },
2286 [pbn_ADDIDATA_PCIe_2_3906250] = {
2287 .flags = FL_BASE0,
2288 .num_ports = 2,
2289 .base_baud = 3906250,
2290 .uart_offset = 0x200,
2291 .first_offset = 0x1000,
2292 },
2293 [pbn_ADDIDATA_PCIe_4_3906250] = {
2294 .flags = FL_BASE0,
2295 .num_ports = 4,
2296 .base_baud = 3906250,
2297 .uart_offset = 0x200,
2298 .first_offset = 0x1000,
2299 },
2300 [pbn_ADDIDATA_PCIe_8_3906250] = {
2301 .flags = FL_BASE0,
2302 .num_ports = 8,
2303 .base_baud = 3906250,
2304 .uart_offset = 0x200,
2305 .first_offset = 0x1000,
2306 },
095e24b0
DB		 2307 [pbn_ce4100_1_115200] = {
2308 .flags = FL_BASE0,
2309 .num_ports = 1,
2310 .base_baud = 921600,
2311 .reg_shift = 2,
2312 },
1da177e4
LT		 2313};
2314
436bbd43 2315static const struct pci_device_id softmodem_blacklist[] = {
5756ee99 2316 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
ebf7c066
MS		 2317 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2318 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
436bbd43
CS		 2319};
2320
1da177e4
LT		 2321/*
2322 * Given a complete unknown PCI device, try to use some heuristics to
2323 * guess what the configuration might be, based on the pitiful PCI
2324 * serial specs. Returns 0 on success, 1 on failure.
2325 */
2326static int __devinit
1c7c1fe5 2327serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1da177e4 2328{
436bbd43 2329 const struct pci_device_id *blacklist;
1da177e4 2330 int num_iomem, num_port, first_port = -1, i;
5756ee99 2331
1da177e4
LT		 2332 /*
2333 * If it is not a communications device or the programming
2334 * interface is greater than 6, give up.
2335 *
2336 * (Should we try to make guesses for multiport serial devices
5756ee99 2337 * later?)
1da177e4
LT		 2338 */
2339 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2340 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2341 (dev->class & 0xff) > 6)
2342 return -ENODEV;
2343
436bbd43
CS		 2344 /*
2345 * Do not access blacklisted devices that are known not to
2346 * feature serial ports.
2347 */
2348 for (blacklist = softmodem_blacklist;
2349 blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2350 blacklist++) {
2351 if (dev->vendor == blacklist->vendor &&
2352 dev->device == blacklist->device)
2353 return -ENODEV;
2354 }
2355
1da177e4
LT		 2356 num_iomem = num_port = 0;
2357 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2358 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2359 num_port++;
2360 if (first_port == -1)
2361 first_port = i;
2362 }
2363 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2364 num_iomem++;
2365 }
2366
2367 /*
2368 * If there is 1 or 0 iomem regions, and exactly one port,
2369 * use it. We guess the number of ports based on the IO
2370 * region size.
2371 */
2372 if (num_iomem <= 1 && num_port == 1) {
2373 board->flags = first_port;
2374 board->num_ports = pci_resource_len(dev, first_port) / 8;
2375 return 0;
2376 }
2377
2378 /*
2379 * Now guess if we've got a board which indexes by BARs.
2380 * Each IO BAR should be 8 bytes, and they should follow
2381 * consecutively.
2382 */
2383 first_port = -1;
2384 num_port = 0;
2385 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2386 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2387 pci_resource_len(dev, i) == 8 &&
2388 (first_port == -1 || (first_port + num_port) == i)) {
2389 num_port++;
2390 if (first_port == -1)
2391 first_port = i;
2392 }
2393 }
2394
2395 if (num_port > 1) {
2396 board->flags = first_port | FL_BASE_BARS;
2397 board->num_ports = num_port;
2398 return 0;
2399 }
2400
2401 return -ENODEV;
2402}
2403
2404static inline int
975a1a7d
RK		 2405serial_pci_matches(const struct pciserial_board *board,
2406 const struct pciserial_board *guessed)
1da177e4
LT		 2407{
2408 return
2409 board->num_ports == guessed->num_ports &&
2410 board->base_baud == guessed->base_baud &&
2411 board->uart_offset == guessed->uart_offset &&
2412 board->reg_shift == guessed->reg_shift &&
2413 board->first_offset == guessed->first_offset;
2414}
2415
241fc436 2416struct serial_private *
975a1a7d 2417pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
1da177e4 2418{
72ce9a83 2419 struct uart_port serial_port;
1da177e4 2420 struct serial_private *priv;
1da177e4
LT		 2421 struct pci_serial_quirk *quirk;
2422 int rc, nr_ports, i;
2423
1da177e4
LT		 2424 nr_ports = board->num_ports;
2425
2426 /*
2427 * Find an init and setup quirks.
2428 */
2429 quirk = find_quirk(dev);
2430
2431 /*
2432 * Run the new-style initialization function.
2433 * The initialization function returns:
2434 * <0 - error
2435 * 0 - use board->num_ports
2436 * >0 - number of ports
2437 */
2438 if (quirk->init) {
2439 rc = quirk->init(dev);
241fc436
RK		 2440 if (rc < 0) {
2441 priv = ERR_PTR(rc);
2442 goto err_out;
2443 }
1da177e4
LT		 2444 if (rc)
2445 nr_ports = rc;
2446 }
2447
8f31bb39 2448 priv = kzalloc(sizeof(struct serial_private) +
1da177e4
LT		 2449 sizeof(unsigned int) * nr_ports,
2450 GFP_KERNEL);
2451 if (!priv) {
241fc436
RK		 2452 priv = ERR_PTR(-ENOMEM);
2453 goto err_deinit;
1da177e4
LT		 2454 }
2455
70db3d91 2456 priv->dev = dev;
1da177e4 2457 priv->quirk = quirk;
1da177e4 2458
72ce9a83
RK		 2459 memset(&serial_port, 0, sizeof(struct uart_port));
2460 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2461 serial_port.uartclk = board->base_baud * 16;
2462 serial_port.irq = get_pci_irq(dev, board);
2463 serial_port.dev = &dev->dev;
2464
1da177e4 2465 for (i = 0; i < nr_ports; i++) {
70db3d91 2466 if (quirk->setup(priv, board, &serial_port, i))
1da177e4 2467 break;
72ce9a83 2468
1da177e4 2469#ifdef SERIAL_DEBUG_PCI
80647b95 2470 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
1da177e4
LT		 2471 serial_port.iobase, serial_port.irq, serial_port.iotype);
2472#endif
5756ee99 2473
1da177e4
LT		 2474 priv->line[i] = serial8250_register_port(&serial_port);
2475 if (priv->line[i] < 0) {
2476 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2477 break;
2478 }
2479 }
1da177e4 2480 priv->nr = i;
241fc436 2481 return priv;
1da177e4 2482
5756ee99 2483err_deinit:
1da177e4
LT		 2484 if (quirk->exit)
2485 quirk->exit(dev);
5756ee99 2486err_out:
241fc436 2487 return priv;
1da177e4 2488}
241fc436 2489EXPORT_SYMBOL_GPL(pciserial_init_ports);
1da177e4 2490
241fc436 2491void pciserial_remove_ports(struct serial_private *priv)
1da177e4 2492{
056a8763
RK		 2493 struct pci_serial_quirk *quirk;
2494 int i;
1da177e4 2495
056a8763
RK		 2496 for (i = 0; i < priv->nr; i++)
2497 serial8250_unregister_port(priv->line[i]);
1da177e4 2498
056a8763
RK		 2499 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2500 if (priv->remapped_bar[i])
2501 iounmap(priv->remapped_bar[i]);
2502 priv->remapped_bar[i] = NULL;
2503 }
1da177e4 2504
056a8763
RK		 2505 /*
2506 * Find the exit quirks.
2507 */
241fc436 2508 quirk = find_quirk(priv->dev);
056a8763 2509 if (quirk->exit)
241fc436
RK		 2510 quirk->exit(priv->dev);
2511
2512 kfree(priv);
2513}
2514EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2515
2516void pciserial_suspend_ports(struct serial_private *priv)
2517{
2518 int i;
2519
2520 for (i = 0; i < priv->nr; i++)
2521 if (priv->line[i] >= 0)
2522 serial8250_suspend_port(priv->line[i]);
2523}
2524EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2525
2526void pciserial_resume_ports(struct serial_private *priv)
2527{
2528 int i;
2529
2530 /*
2531 * Ensure that the board is correctly configured.
2532 */
2533 if (priv->quirk->init)
2534 priv->quirk->init(priv->dev);
2535
2536 for (i = 0; i < priv->nr; i++)
2537 if (priv->line[i] >= 0)
2538 serial8250_resume_port(priv->line[i]);
2539}
2540EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2541
2542/*
2543 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2544 * to the arrangement of serial ports on a PCI card.
2545 */
2546static int __devinit
2547pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2548{
2549 struct serial_private *priv;
975a1a7d
RK		 2550 const struct pciserial_board *board;
2551 struct pciserial_board tmp;
241fc436
RK		 2552 int rc;
2553
2554 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2555 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2556 ent->driver_data);
2557 return -EINVAL;
2558 }
2559
2560 board = &pci_boards[ent->driver_data];
2561
2562 rc = pci_enable_device(dev);
2563 if (rc)
2564 return rc;
2565
2566 if (ent->driver_data == pbn_default) {
2567 /*
2568 * Use a copy of the pci_board entry for this;
2569 * avoid changing entries in the table.
2570 */
2571 memcpy(&tmp, board, sizeof(struct pciserial_board));
2572 board = &tmp;
2573
2574 /*
2575 * We matched one of our class entries. Try to
2576 * determine the parameters of this board.
2577 */
975a1a7d 2578 rc = serial_pci_guess_board(dev, &tmp);
241fc436
RK		 2579 if (rc)
2580 goto disable;
2581 } else {
2582 /*
2583 * We matched an explicit entry. If we are able to
2584 * detect this boards settings with our heuristic,
2585 * then we no longer need this entry.
2586 */
2587 memcpy(&tmp, &pci_boards[pbn_default],
2588 sizeof(struct pciserial_board));
2589 rc = serial_pci_guess_board(dev, &tmp);
2590 if (rc == 0 && serial_pci_matches(board, &tmp))
2591 moan_device("Redundant entry in serial pci_table.",
2592 dev);
2593 }
2594
2595 priv = pciserial_init_ports(dev, board);
2596 if (!IS_ERR(priv)) {
2597 pci_set_drvdata(dev, priv);
2598 return 0;
2599 }
2600
2601 rc = PTR_ERR(priv);
1da177e4 2602
241fc436 2603 disable:
056a8763 2604 pci_disable_device(dev);
241fc436
RK		 2605 return rc;
2606}
1da177e4 2607
241fc436
RK		 2608static void __devexit pciserial_remove_one(struct pci_dev *dev)
2609{
2610 struct serial_private *priv = pci_get_drvdata(dev);
2611
2612 pci_set_drvdata(dev, NULL);
2613
2614 pciserial_remove_ports(priv);
2615
2616 pci_disable_device(dev);
1da177e4
LT		 2617}
2618
1d5e7996 2619#ifdef CONFIG_PM
1da177e4
LT		 2620static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2621{
2622 struct serial_private *priv = pci_get_drvdata(dev);
2623
241fc436
RK		 2624 if (priv)
2625 pciserial_suspend_ports(priv);
1da177e4 2626
1da177e4
LT		 2627 pci_save_state(dev);
2628 pci_set_power_state(dev, pci_choose_state(dev, state));
2629 return 0;
2630}
2631
2632static int pciserial_resume_one(struct pci_dev *dev)
2633{
ccb9d59e 2634 int err;
1da177e4
LT		 2635 struct serial_private *priv = pci_get_drvdata(dev);
2636
2637 pci_set_power_state(dev, PCI_D0);
2638 pci_restore_state(dev);
2639
2640 if (priv) {
1da177e4
LT		 2641 /*
2642 * The device may have been disabled. Re-enable it.
2643 */
ccb9d59e 2644 err = pci_enable_device(dev);
40836c48 2645 /* FIXME: We cannot simply error out here */
ccb9d59e 2646 if (err)
40836c48 2647 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
241fc436 2648 pciserial_resume_ports(priv);
1da177e4
LT		 2649 }
2650 return 0;
2651}
1d5e7996 2652#endif
1da177e4
LT		 2653
2654static struct pci_device_id serial_pci_tbl[] = {
78d70d48
MB		 2655 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2656 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2657 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2658 pbn_b2_8_921600 },
1da177e4
LT		 2659 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2660 PCI_SUBVENDOR_ID_CONNECT_TECH,
2661 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2662 pbn_b1_8_1382400 },
2663 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2664 PCI_SUBVENDOR_ID_CONNECT_TECH,
2665 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2666 pbn_b1_4_1382400 },
2667 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2668 PCI_SUBVENDOR_ID_CONNECT_TECH,
2669 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2670 pbn_b1_2_1382400 },
2671 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2672 PCI_SUBVENDOR_ID_CONNECT_TECH,
2673 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2674 pbn_b1_8_1382400 },
2675 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2676 PCI_SUBVENDOR_ID_CONNECT_TECH,
2677 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2678 pbn_b1_4_1382400 },
2679 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2680 PCI_SUBVENDOR_ID_CONNECT_TECH,
2681 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2682 pbn_b1_2_1382400 },
2683 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2684 PCI_SUBVENDOR_ID_CONNECT_TECH,
2685 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2686 pbn_b1_8_921600 },
2687 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2688 PCI_SUBVENDOR_ID_CONNECT_TECH,
2689 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2690 pbn_b1_8_921600 },
2691 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2692 PCI_SUBVENDOR_ID_CONNECT_TECH,
2693 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2694 pbn_b1_4_921600 },
2695 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2696 PCI_SUBVENDOR_ID_CONNECT_TECH,
2697 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2698 pbn_b1_4_921600 },
2699 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2700 PCI_SUBVENDOR_ID_CONNECT_TECH,
2701 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2702 pbn_b1_2_921600 },
2703 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2704 PCI_SUBVENDOR_ID_CONNECT_TECH,
2705 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2706 pbn_b1_8_921600 },
2707 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2708 PCI_SUBVENDOR_ID_CONNECT_TECH,
2709 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
2710 pbn_b1_8_921600 },
2711 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2712 PCI_SUBVENDOR_ID_CONNECT_TECH,
2713 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
2714 pbn_b1_4_921600 },
26e92861
GH		 2715 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2716 PCI_SUBVENDOR_ID_CONNECT_TECH,
2717 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
2718 pbn_b1_2_1250000 },
2719 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2720 PCI_SUBVENDOR_ID_CONNECT_TECH,
2721 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
2722 pbn_b0_2_1843200 },
2723 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2724 PCI_SUBVENDOR_ID_CONNECT_TECH,
2725 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
2726 pbn_b0_4_1843200 },
85d1494e
YY		 2727 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2728 PCI_VENDOR_ID_AFAVLAB,
2729 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
2730 pbn_b0_4_1152000 },
26e92861
GH		 2731 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2732 PCI_SUBVENDOR_ID_CONNECT_TECH,
2733 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
2734 pbn_b0_2_1843200_200 },
2735 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2736 PCI_SUBVENDOR_ID_CONNECT_TECH,
2737 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
2738 pbn_b0_4_1843200_200 },
2739 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2740 PCI_SUBVENDOR_ID_CONNECT_TECH,
2741 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
2742 pbn_b0_8_1843200_200 },
2743 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2744 PCI_SUBVENDOR_ID_CONNECT_TECH,
2745 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
2746 pbn_b0_2_1843200_200 },
2747 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2748 PCI_SUBVENDOR_ID_CONNECT_TECH,
2749 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
2750 pbn_b0_4_1843200_200 },
2751 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2752 PCI_SUBVENDOR_ID_CONNECT_TECH,
2753 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
2754 pbn_b0_8_1843200_200 },
2755 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2756 PCI_SUBVENDOR_ID_CONNECT_TECH,
2757 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
2758 pbn_b0_2_1843200_200 },
2759 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2760 PCI_SUBVENDOR_ID_CONNECT_TECH,
2761 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
2762 pbn_b0_4_1843200_200 },
2763 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2764 PCI_SUBVENDOR_ID_CONNECT_TECH,
2765 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
2766 pbn_b0_8_1843200_200 },
2767 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2768 PCI_SUBVENDOR_ID_CONNECT_TECH,
2769 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
2770 pbn_b0_2_1843200_200 },
2771 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2772 PCI_SUBVENDOR_ID_CONNECT_TECH,
2773 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
2774 pbn_b0_4_1843200_200 },
2775 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2776 PCI_SUBVENDOR_ID_CONNECT_TECH,
2777 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
2778 pbn_b0_8_1843200_200 },
c68d2b15
BH		 2779 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2780 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
2781 0, 0, pbn_exar_ibm_saturn },
1da177e4
LT		 2782
2783 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
5756ee99 2784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2785 pbn_b2_bt_1_115200 },
2786 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
5756ee99 2787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2788 pbn_b2_bt_2_115200 },
2789 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
5756ee99 2790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2791 pbn_b2_bt_4_115200 },
2792 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
5756ee99 2793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2794 pbn_b2_bt_2_115200 },
2795 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
5756ee99 2796 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2797 pbn_b2_bt_4_115200 },
2798 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
5756ee99 2799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 2800 pbn_b2_8_115200 },
e65f0f82
FL		 2801 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
2802 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2803 pbn_b2_8_460800 },
1da177e4
LT		 2804 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
2805 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2806 pbn_b2_8_115200 },
2807
2808 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
2809 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2810 pbn_b2_bt_2_115200 },
2811 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
2812 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2813 pbn_b2_bt_2_921600 },
2814 /*
2815 * VScom SPCOM800, from sl@s.pl
2816 */
5756ee99
AC		 2817 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
2818 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 2819 pbn_b2_8_921600 },
2820 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
5756ee99 2821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4 2822 pbn_b2_4_921600 },
b76c5a07
CB		 2823 /* Unknown card - subdevice 0x1584 */
2824 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2825 PCI_VENDOR_ID_PLX,
2826 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
2827 pbn_b0_4_115200 },
1da177e4
LT		 2828 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2829 PCI_SUBVENDOR_ID_KEYSPAN,
2830 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
2831 pbn_panacom },
2832 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
2833 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2834 pbn_panacom4 },
2835 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
2836 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2837 pbn_panacom2 },
a9cccd34
MF		 2838 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
2839 PCI_VENDOR_ID_ESDGMBH,
2840 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
2841 pbn_b2_4_115200 },
1da177e4
LT		 2842 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2843 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2844 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1da177e4
LT		 2845 pbn_b2_4_460800 },
2846 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2847 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2848 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1da177e4
LT		 2849 pbn_b2_8_460800 },
2850 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2851 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2852 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1da177e4
LT		 2853 pbn_b2_16_460800 },
2854 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2855 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
5756ee99 2856 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1da177e4
LT		 2857 pbn_b2_16_460800 },
2858 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2859 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 2860 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1da177e4
LT		 2861 pbn_b2_4_460800 },
2862 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2863 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
5756ee99 2864 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1da177e4 2865 pbn_b2_8_460800 },
add7b58e
BH		 2866 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
2867 PCI_SUBVENDOR_ID_EXSYS,
2868 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
2869 pbn_exsys_4055 },
1da177e4
LT		 2870 /*
2871 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2872 * (Exoray@isys.ca)
2873 */
2874 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
2875 0x10b5, 0x106a, 0, 0,
2876 pbn_plx_romulus },
2877 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
2878 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2879 pbn_b1_4_115200 },
2880 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
2881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2882 pbn_b1_2_115200 },
2883 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
2884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2885 pbn_b1_8_115200 },
2886 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
2887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2888 pbn_b1_8_115200 },
2889 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 2890 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
2891 0, 0,
1da177e4 2892 pbn_b0_4_921600 },
fbc0dc0d 2893 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
5756ee99
AC		 2894 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
2895 0, 0,
fbc0dc0d 2896 pbn_b0_4_1152000 },
c9bd9d01
MP		 2897 { PCI_VENDOR_ID_OXSEMI, 0x9505,
2898 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2899 pbn_b0_bt_2_921600 },
db1de159
DR		 2900
2901 /*
2902 * The below card is a little controversial since it is the
2903 * subject of a PCI vendor/device ID clash. (See
2904 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2905 * For now just used the hex ID 0x950a.
2906 */
39aced68
NV		 2907 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2908 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
2909 pbn_b0_2_115200 },
db1de159
DR		 2910 { PCI_VENDOR_ID_OXSEMI, 0x950a,
2911 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2912 pbn_b0_2_1130000 },
70fd8fde
AP		 2913 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
2914 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
2915 pbn_b0_1_921600 },
1da177e4
LT		 2916 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
2917 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2918 pbn_b0_4_115200 },
2919 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
2920 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2921 pbn_b0_bt_2_921600 },
e847003f
LB		 2922 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
2923 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
2924 pbn_b2_8_1152000 },
1da177e4 2925
7106b4e3
LH		 2926 /*
2927 * Oxford Semiconductor Inc. Tornado PCI express device range.
2928 */
2929 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
2930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2931 pbn_b0_1_4000000 },
2932 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
2933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2934 pbn_b0_1_4000000 },
2935 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
2936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2937 pbn_oxsemi_1_4000000 },
2938 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
2939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2940 pbn_oxsemi_1_4000000 },
2941 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
2942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2943 pbn_b0_1_4000000 },
2944 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
2945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2946 pbn_b0_1_4000000 },
2947 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
2948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2949 pbn_oxsemi_1_4000000 },
2950 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
2951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2952 pbn_oxsemi_1_4000000 },
2953 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
2954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2955 pbn_b0_1_4000000 },
2956 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
2957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2958 pbn_b0_1_4000000 },
2959 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
2960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2961 pbn_b0_1_4000000 },
2962 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
2963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2964 pbn_b0_1_4000000 },
2965 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
2966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2967 pbn_oxsemi_2_4000000 },
2968 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
2969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2970 pbn_oxsemi_2_4000000 },
2971 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
2972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2973 pbn_oxsemi_4_4000000 },
2974 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
2975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2976 pbn_oxsemi_4_4000000 },
2977 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
2978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2979 pbn_oxsemi_8_4000000 },
2980 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
2981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2982 pbn_oxsemi_8_4000000 },
2983 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
2984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2985 pbn_oxsemi_1_4000000 },
2986 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
2987 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2988 pbn_oxsemi_1_4000000 },
2989 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
2990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2991 pbn_oxsemi_1_4000000 },
2992 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
2993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2994 pbn_oxsemi_1_4000000 },
2995 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
2996 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2997 pbn_oxsemi_1_4000000 },
2998 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
2999 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3000 pbn_oxsemi_1_4000000 },
3001 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3002 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3003 pbn_oxsemi_1_4000000 },
3004 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3005 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3006 pbn_oxsemi_1_4000000 },
3007 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3008 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3009 pbn_oxsemi_1_4000000 },
3010 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3011 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3012 pbn_oxsemi_1_4000000 },
3013 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3014 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3015 pbn_oxsemi_1_4000000 },
3016 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3017 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3018 pbn_oxsemi_1_4000000 },
3019 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3020 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3021 pbn_oxsemi_1_4000000 },
3022 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3023 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3024 pbn_oxsemi_1_4000000 },
3025 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3026 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3027 pbn_oxsemi_1_4000000 },
3028 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3029 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3030 pbn_oxsemi_1_4000000 },
3031 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3032 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3033 pbn_oxsemi_1_4000000 },
3034 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3035 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3036 pbn_oxsemi_1_4000000 },
3037 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3038 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3039 pbn_oxsemi_1_4000000 },
3040 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3041 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3042 pbn_oxsemi_1_4000000 },
3043 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3044 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3045 pbn_oxsemi_1_4000000 },
3046 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3047 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3048 pbn_oxsemi_1_4000000 },
3049 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3050 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3051 pbn_oxsemi_1_4000000 },
3052 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3053 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3054 pbn_oxsemi_1_4000000 },
3055 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
3056 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3057 pbn_oxsemi_1_4000000 },
3058 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
3059 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3060 pbn_oxsemi_1_4000000 },
b80de369
LH		 3061 /*
3062 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3063 */
3064 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3065 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3066 pbn_oxsemi_1_4000000 },
3067 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3068 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3069 pbn_oxsemi_2_4000000 },
3070 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3071 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3072 pbn_oxsemi_4_4000000 },
3073 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3074 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3075 pbn_oxsemi_8_4000000 },
1da177e4
LT		 3076 /*
3077 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3078 * from skokodyn@yahoo.com
3079 */
3080 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3081 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3082 pbn_sbsxrsio },
3083 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3084 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3085 pbn_sbsxrsio },
3086 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3087 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3088 pbn_sbsxrsio },
3089 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3090 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3091 pbn_sbsxrsio },
3092
3093 /*
3094 * Digitan DS560-558, from jimd@esoft.com
3095 */
3096 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
5756ee99 3097 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3098 pbn_b1_1_115200 },
3099
3100 /*
3101 * Titan Electronic cards
3102 * The 400L and 800L have a custom setup quirk.
3103 */
3104 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
5756ee99 3105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3106 pbn_b0_1_921600 },
3107 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
5756ee99 3108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3109 pbn_b0_2_921600 },
3110 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
5756ee99 3111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3112 pbn_b0_4_921600 },
3113 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
5756ee99 3114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1da177e4
LT		 3115 pbn_b0_4_921600 },
3116 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3118 pbn_b1_1_921600 },
3119 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3121 pbn_b1_bt_2_921600 },
3122 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3124 pbn_b0_bt_4_921600 },
3125 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3127 pbn_b0_bt_8_921600 },
66169ad1
YY		 3128 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3129 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3130 pbn_b4_bt_2_921600 },
3131 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3132 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3133 pbn_b4_bt_4_921600 },
3134 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3135 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3136 pbn_b4_bt_8_921600 },
3137 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3138 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3139 pbn_b0_4_921600 },
3140 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3142 pbn_b0_4_921600 },
3143 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3145 pbn_b0_4_921600 },
3146 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3148 pbn_oxsemi_1_4000000 },
3149 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3150 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3151 pbn_oxsemi_2_4000000 },
3152 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3153 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3154 pbn_oxsemi_4_4000000 },
3155 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3156 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3157 pbn_oxsemi_8_4000000 },
3158 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3159 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3160 pbn_oxsemi_2_4000000 },
3161 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3163 pbn_oxsemi_2_4000000 },
1da177e4
LT		 3164
3165 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3167 pbn_b2_1_460800 },
3168 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3170 pbn_b2_1_460800 },
3171 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3173 pbn_b2_1_460800 },
3174 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3176 pbn_b2_bt_2_921600 },
3177 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3178 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3179 pbn_b2_bt_2_921600 },
3180 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3181 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3182 pbn_b2_bt_2_921600 },
3183 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3184 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3185 pbn_b2_bt_4_921600 },
3186 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3187 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3188 pbn_b2_bt_4_921600 },
3189 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3190 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3191 pbn_b2_bt_4_921600 },
3192 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3193 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3194 pbn_b0_1_921600 },
3195 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3196 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3197 pbn_b0_1_921600 },
3198 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3199 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3200 pbn_b0_1_921600 },
3201 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3202 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3203 pbn_b0_bt_2_921600 },
3204 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3206 pbn_b0_bt_2_921600 },
3207 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3208 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3209 pbn_b0_bt_2_921600 },
3210 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3211 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3212 pbn_b0_bt_4_921600 },
3213 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3214 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3215 pbn_b0_bt_4_921600 },
3216 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3218 pbn_b0_bt_4_921600 },
3ec9c594
AP		 3219 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3221 pbn_b0_bt_8_921600 },
3222 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3223 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3224 pbn_b0_bt_8_921600 },
3225 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3226 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3227 pbn_b0_bt_8_921600 },
1da177e4
LT		 3228
3229 /*
3230 * Computone devices submitted by Doug McNash dmcnash@computone.com
3231 */
3232 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3233 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3234 0, 0, pbn_computone_4 },
3235 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3236 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3237 0, 0, pbn_computone_8 },
3238 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3239 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3240 0, 0, pbn_computone_6 },
3241
3242 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3243 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3244 pbn_oxsemi },
3245 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3246 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3247 pbn_b0_bt_1_921600 },
3248
3249 /*
3250 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3251 */
3252 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3253 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3254 pbn_b0_bt_8_115200 },
3255 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3256 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3257 pbn_b0_bt_8_115200 },
3258
3259 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3261 pbn_b0_bt_2_115200 },
3262 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3264 pbn_b0_bt_2_115200 },
3265 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3267 pbn_b0_bt_2_115200 },
b87e5e2b
LB		 3268 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3270 pbn_b0_bt_2_115200 },
3271 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3272 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3273 pbn_b0_bt_2_115200 },
1da177e4
LT		 3274 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3275 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3276 pbn_b0_bt_4_460800 },
3277 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3278 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3279 pbn_b0_bt_4_460800 },
3280 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3281 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3282 pbn_b0_bt_2_460800 },
3283 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3285 pbn_b0_bt_2_460800 },
3286 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3287 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3288 pbn_b0_bt_2_460800 },
3289 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3290 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3291 pbn_b0_bt_1_115200 },
3292 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3294 pbn_b0_bt_1_460800 },
3295
1fb8cacc
RK		 3296 /*
3297 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3298 * Cards are identified by their subsystem vendor IDs, which
3299 * (in hex) match the model number.
3300 *
3301 * Note that JC140x are RS422/485 cards which require ox950
3302 * ACR = 0x10, and as such are not currently fully supported.
3303 */
3304 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3305 0x1204, 0x0004, 0, 0,
3306 pbn_b0_4_921600 },
3307 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3308 0x1208, 0x0004, 0, 0,
3309 pbn_b0_4_921600 },
3310/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3311 0x1402, 0x0002, 0, 0,
3312 pbn_b0_2_921600 }, */
3313/* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3314 0x1404, 0x0004, 0, 0,
3315 pbn_b0_4_921600 }, */
3316 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3317 0x1208, 0x0004, 0, 0,
3318 pbn_b0_4_921600 },
3319
2a52fcb5
KY		 3320 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3321 0x1204, 0x0004, 0, 0,
3322 pbn_b0_4_921600 },
3323 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3324 0x1208, 0x0004, 0, 0,
3325 pbn_b0_4_921600 },
3326 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3327 0x1208, 0x0004, 0, 0,
3328 pbn_b0_4_921600 },
1da177e4
LT		 3329 /*
3330 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3331 */
3332 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3333 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3334 pbn_b1_1_1382400 },
3335
3336 /*
3337 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3338 */
3339 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3340 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3341 pbn_b1_1_1382400 },
3342
3343 /*
3344 * RAStel 2 port modem, gerg@moreton.com.au
3345 */
3346 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3348 pbn_b2_bt_2_115200 },
3349
3350 /*
3351 * EKF addition for i960 Boards form EKF with serial port
3352 */
3353 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3354 0xE4BF, PCI_ANY_ID, 0, 0,
3355 pbn_intel_i960 },
3356
3357 /*
3358 * Xircom Cardbus/Ethernet combos
3359 */
3360 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3361 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3362 pbn_b0_1_115200 },
3363 /*
3364 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3365 */
3366 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3367 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3368 pbn_b0_1_115200 },
3369
3370 /*
3371 * Untested PCI modems, sent in from various folks...
3372 */
3373
3374 /*
3375 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3376 */
3377 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
3378 0x1048, 0x1500, 0, 0,
3379 pbn_b1_1_115200 },
3380
3381 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3382 0xFF00, 0, 0, 0,
3383 pbn_sgi_ioc3 },
3384
3385 /*
3386 * HP Diva card
3387 */
3388 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3389 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3390 pbn_b1_1_115200 },
3391 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3392 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3393 pbn_b0_5_115200 },
3394 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3395 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3396 pbn_b2_1_115200 },
3397
d9004eb4
ABL		 3398 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3400 pbn_b3_2_115200 },
1da177e4
LT		 3401 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3403 pbn_b3_4_115200 },
3404 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3405 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3406 pbn_b3_8_115200 },
3407
3408 /*
3409 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3410 */
3411 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3412 PCI_ANY_ID, PCI_ANY_ID,
3413 0,
3414 0, pbn_exar_XR17C152 },
3415 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3416 PCI_ANY_ID, PCI_ANY_ID,
3417 0,
3418 0, pbn_exar_XR17C154 },
3419 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3420 PCI_ANY_ID, PCI_ANY_ID,
3421 0,
3422 0, pbn_exar_XR17C158 },
3423
3424 /*
3425 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3426 */
3427 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3428 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3429 pbn_b0_1_115200 },
84f8c6fc
NV		 3430 /*
3431 * ITE
3432 */
3433 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3434 PCI_ANY_ID, PCI_ANY_ID,
3435 0, 0,
3436 pbn_b1_bt_1_115200 },
1da177e4 3437
737c1756
PH		 3438 /*
3439 * IntaShield IS-200
3440 */
3441 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3442 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
3443 pbn_b2_2_115200 },
4b6f6ce9
IGP		 3444 /*
3445 * IntaShield IS-400
3446 */
3447 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3448 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
3449 pbn_b2_4_115200 },
48212008
TH		 3450 /*
3451 * Perle PCI-RAS cards
3452 */
3453 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3454 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3455 0, 0, pbn_b2_4_921600 },
3456 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3457 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3458 0, 0, pbn_b2_8_921600 },
bf0df636
AC		 3459
3460 /*
3461 * Mainpine series cards: Fairly standard layout but fools
3462 * parts of the autodetect in some cases and uses otherwise
3463 * unmatched communications subclasses in the PCI Express case
3464 */
3465
3466 { /* RockForceDUO */
3467 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3468 PCI_VENDOR_ID_MAINPINE, 0x0200,
3469 0, 0, pbn_b0_2_115200 },
3470 { /* RockForceQUATRO */
3471 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3472 PCI_VENDOR_ID_MAINPINE, 0x0300,
3473 0, 0, pbn_b0_4_115200 },
3474 { /* RockForceDUO+ */
3475 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3476 PCI_VENDOR_ID_MAINPINE, 0x0400,
3477 0, 0, pbn_b0_2_115200 },
3478 { /* RockForceQUATRO+ */
3479 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3480 PCI_VENDOR_ID_MAINPINE, 0x0500,
3481 0, 0, pbn_b0_4_115200 },
3482 { /* RockForce+ */
3483 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3484 PCI_VENDOR_ID_MAINPINE, 0x0600,
3485 0, 0, pbn_b0_2_115200 },
3486 { /* RockForce+ */
3487 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3488 PCI_VENDOR_ID_MAINPINE, 0x0700,
3489 0, 0, pbn_b0_4_115200 },
3490 { /* RockForceOCTO+ */
3491 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3492 PCI_VENDOR_ID_MAINPINE, 0x0800,
3493 0, 0, pbn_b0_8_115200 },
3494 { /* RockForceDUO+ */
3495 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3496 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3497 0, 0, pbn_b0_2_115200 },
3498 { /* RockForceQUARTRO+ */
3499 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3500 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3501 0, 0, pbn_b0_4_115200 },
3502 { /* RockForceOCTO+ */
3503 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3504 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3505 0, 0, pbn_b0_8_115200 },
3506 { /* RockForceD1 */
3507 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3508 PCI_VENDOR_ID_MAINPINE, 0x2000,
3509 0, 0, pbn_b0_1_115200 },
3510 { /* RockForceF1 */
3511 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3512 PCI_VENDOR_ID_MAINPINE, 0x2100,
3513 0, 0, pbn_b0_1_115200 },
3514 { /* RockForceD2 */
3515 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3516 PCI_VENDOR_ID_MAINPINE, 0x2200,
3517 0, 0, pbn_b0_2_115200 },
3518 { /* RockForceF2 */
3519 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3520 PCI_VENDOR_ID_MAINPINE, 0x2300,
3521 0, 0, pbn_b0_2_115200 },
3522 { /* RockForceD4 */
3523 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3524 PCI_VENDOR_ID_MAINPINE, 0x2400,
3525 0, 0, pbn_b0_4_115200 },
3526 { /* RockForceF4 */
3527 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3528 PCI_VENDOR_ID_MAINPINE, 0x2500,
3529 0, 0, pbn_b0_4_115200 },
3530 { /* RockForceD8 */
3531 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3532 PCI_VENDOR_ID_MAINPINE, 0x2600,
3533 0, 0, pbn_b0_8_115200 },
3534 { /* RockForceF8 */
3535 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3536 PCI_VENDOR_ID_MAINPINE, 0x2700,
3537 0, 0, pbn_b0_8_115200 },
3538 { /* IQ Express D1 */
3539 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3540 PCI_VENDOR_ID_MAINPINE, 0x3000,
3541 0, 0, pbn_b0_1_115200 },
3542 { /* IQ Express F1 */
3543 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3544 PCI_VENDOR_ID_MAINPINE, 0x3100,
3545 0, 0, pbn_b0_1_115200 },
3546 { /* IQ Express D2 */
3547 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3548 PCI_VENDOR_ID_MAINPINE, 0x3200,
3549 0, 0, pbn_b0_2_115200 },
3550 { /* IQ Express F2 */
3551 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3552 PCI_VENDOR_ID_MAINPINE, 0x3300,
3553 0, 0, pbn_b0_2_115200 },
3554 { /* IQ Express D4 */
3555 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3556 PCI_VENDOR_ID_MAINPINE, 0x3400,
3557 0, 0, pbn_b0_4_115200 },
3558 { /* IQ Express F4 */
3559 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3560 PCI_VENDOR_ID_MAINPINE, 0x3500,
3561 0, 0, pbn_b0_4_115200 },
3562 { /* IQ Express D8 */
3563 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3564 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3565 0, 0, pbn_b0_8_115200 },
3566 { /* IQ Express F8 */
3567 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3568 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3569 0, 0, pbn_b0_8_115200 },
3570
3571
aa798505
OJ		 3572 /*
3573 * PA Semi PA6T-1682M on-chip UART
3574 */
3575 { PCI_VENDOR_ID_PASEMI, 0xa004,
3576 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3577 pbn_pasemi_1682M },
3578
46a0fac9
SB		 3579 /*
3580 * National Instruments
3581 */
04bf7e74
WP		 3582 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3584 pbn_b1_16_115200 },
3585 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3587 pbn_b1_8_115200 },
3588 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3590 pbn_b1_bt_4_115200 },
3591 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3593 pbn_b1_bt_2_115200 },
3594 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3596 pbn_b1_bt_4_115200 },
3597 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3599 pbn_b1_bt_2_115200 },
3600 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
3601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3602 pbn_b1_16_115200 },
3603 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
3604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3605 pbn_b1_8_115200 },
3606 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
3607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3608 pbn_b1_bt_4_115200 },
3609 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
3610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3611 pbn_b1_bt_2_115200 },
3612 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
3613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3614 pbn_b1_bt_4_115200 },
3615 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
3616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3617 pbn_b1_bt_2_115200 },
46a0fac9
SB		 3618 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
3619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3620 pbn_ni8430_2 },
3621 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
3622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3623 pbn_ni8430_2 },
3624 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
3625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3626 pbn_ni8430_4 },
3627 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
3628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3629 pbn_ni8430_4 },
3630 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
3631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3632 pbn_ni8430_8 },
3633 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
3634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3635 pbn_ni8430_8 },
3636 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
3637 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3638 pbn_ni8430_16 },
3639 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
3640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3641 pbn_ni8430_16 },
3642 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
3643 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3644 pbn_ni8430_2 },
3645 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
3646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3647 pbn_ni8430_2 },
3648 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
3649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3650 pbn_ni8430_4 },
3651 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
3652 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3653 pbn_ni8430_4 },
3654
02c9b5cf
KJ		 3655 /*
3656 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3657 */
3658 { PCI_VENDOR_ID_ADDIDATA,
3659 PCI_DEVICE_ID_ADDIDATA_APCI7500,
3660 PCI_ANY_ID,
3661 PCI_ANY_ID,
3662 0,
3663 0,
3664 pbn_b0_4_115200 },
3665
3666 { PCI_VENDOR_ID_ADDIDATA,
3667 PCI_DEVICE_ID_ADDIDATA_APCI7420,
3668 PCI_ANY_ID,
3669 PCI_ANY_ID,
3670 0,
3671 0,
3672 pbn_b0_2_115200 },
3673
3674 { PCI_VENDOR_ID_ADDIDATA,
3675 PCI_DEVICE_ID_ADDIDATA_APCI7300,
3676 PCI_ANY_ID,
3677 PCI_ANY_ID,
3678 0,
3679 0,
3680 pbn_b0_1_115200 },
3681
3682 { PCI_VENDOR_ID_ADDIDATA_OLD,
3683 PCI_DEVICE_ID_ADDIDATA_APCI7800,
3684 PCI_ANY_ID,
3685 PCI_ANY_ID,
3686 0,
3687 0,
3688 pbn_b1_8_115200 },
3689
3690 { PCI_VENDOR_ID_ADDIDATA,
3691 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
3692 PCI_ANY_ID,
3693 PCI_ANY_ID,
3694 0,
3695 0,
3696 pbn_b0_4_115200 },
3697
3698 { PCI_VENDOR_ID_ADDIDATA,
3699 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
3700 PCI_ANY_ID,
3701 PCI_ANY_ID,
3702 0,
3703 0,
3704 pbn_b0_2_115200 },
3705
3706 { PCI_VENDOR_ID_ADDIDATA,
3707 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
3708 PCI_ANY_ID,
3709 PCI_ANY_ID,
3710 0,
3711 0,
3712 pbn_b0_1_115200 },
3713
3714 { PCI_VENDOR_ID_ADDIDATA,
3715 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
3716 PCI_ANY_ID,
3717 PCI_ANY_ID,
3718 0,
3719 0,
3720 pbn_b0_4_115200 },
3721
3722 { PCI_VENDOR_ID_ADDIDATA,
3723 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
3724 PCI_ANY_ID,
3725 PCI_ANY_ID,
3726 0,
3727 0,
3728 pbn_b0_2_115200 },
3729
3730 { PCI_VENDOR_ID_ADDIDATA,
3731 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
3732 PCI_ANY_ID,
3733 PCI_ANY_ID,
3734 0,
3735 0,
3736 pbn_b0_1_115200 },
3737
3738 { PCI_VENDOR_ID_ADDIDATA,
3739 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
3740 PCI_ANY_ID,
3741 PCI_ANY_ID,
3742 0,
3743 0,
3744 pbn_b0_8_115200 },
3745
1b62cbf2
KJ		 3746 { PCI_VENDOR_ID_ADDIDATA,
3747 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
3748 PCI_ANY_ID,
3749 PCI_ANY_ID,
3750 0,
3751 0,
3752 pbn_ADDIDATA_PCIe_4_3906250 },
3753
3754 { PCI_VENDOR_ID_ADDIDATA,
3755 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
3756 PCI_ANY_ID,
3757 PCI_ANY_ID,
3758 0,
3759 0,
3760 pbn_ADDIDATA_PCIe_2_3906250 },
3761
3762 { PCI_VENDOR_ID_ADDIDATA,
3763 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
3764 PCI_ANY_ID,
3765 PCI_ANY_ID,
3766 0,
3767 0,
3768 pbn_ADDIDATA_PCIe_1_3906250 },
3769
3770 { PCI_VENDOR_ID_ADDIDATA,
3771 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
3772 PCI_ANY_ID,
3773 PCI_ANY_ID,
3774 0,
3775 0,
3776 pbn_ADDIDATA_PCIe_8_3906250 },
3777
25cf9bc1
JS		 3778 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
3779 PCI_VENDOR_ID_IBM, 0x0299,
3780 0, 0, pbn_b0_bt_2_115200 },
3781
c4285b47
MB		 3782 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
3783 0xA000, 0x1000,
3784 0, 0, pbn_b0_1_115200 },
3785
ac6ec5b1
IS		 3786 /*
3787 * Best Connectivity PCI Multi I/O cards
3788 */
3789
3790 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3791 0xA000, 0x1000,
3792 0, 0, pbn_b0_1_115200 },
3793
3794 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
3795 0xA000, 0x3004,
3796 0, 0, pbn_b0_bt_4_115200 },
095e24b0
DB		 3797 /* Intel CE4100 */
3798 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
3799 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3800 pbn_ce4100_1_115200 },
3801
ac6ec5b1 3802
1da177e4
LT		 3803 /*
3804 * These entries match devices with class COMMUNICATION_SERIAL,
3805 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3806 */
3807 { PCI_ANY_ID, PCI_ANY_ID,
3808 PCI_ANY_ID, PCI_ANY_ID,
3809 PCI_CLASS_COMMUNICATION_SERIAL << 8,
3810 0xffff00, pbn_default },
3811 { PCI_ANY_ID, PCI_ANY_ID,
3812 PCI_ANY_ID, PCI_ANY_ID,
3813 PCI_CLASS_COMMUNICATION_MODEM << 8,
3814 0xffff00, pbn_default },
3815 { PCI_ANY_ID, PCI_ANY_ID,
3816 PCI_ANY_ID, PCI_ANY_ID,
3817 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
3818 0xffff00, pbn_default },
3819 { 0, }
3820};
3821
3822static struct pci_driver serial_pci_driver = {
3823 .name = "serial",
3824 .probe = pciserial_init_one,
3825 .remove = __devexit_p(pciserial_remove_one),
1d5e7996 3826#ifdef CONFIG_PM
1da177e4
LT		 3827 .suspend = pciserial_suspend_one,
3828 .resume = pciserial_resume_one,
1d5e7996 3829#endif
1da177e4
LT		 3830 .id_table = serial_pci_tbl,
3831};
3832
3833static int __init serial8250_pci_init(void)
3834{
3835 return pci_register_driver(&serial_pci_driver);
3836}
3837
3838static void __exit serial8250_pci_exit(void)
3839{
3840 pci_unregister_driver(&serial_pci_driver);
3841}
3842
3843module_init(serial8250_pci_init);
3844module_exit(serial8250_pci_exit);
3845
3846MODULE_LICENSE("GPL");
3847MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3848MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux kernel - Deliverables
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