Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for AMBA serial ports |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * | |
6 | * Copyright 1999 ARM Limited | |
7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
1da177e4 LT |
23 | * This is a generic driver for ARM AMBA-type serial ports. They |
24 | * have a lot of 16550-like features, but are not register compatible. | |
25 | * Note that although they do have CTS, DCD and DSR inputs, they do | |
26 | * not have an RI input, nor do they have DTR or RTS outputs. If | |
27 | * required, these have to be supplied via some other means (eg, GPIO) | |
28 | * and hooked into this driver. | |
29 | */ | |
1da177e4 LT |
30 | |
31 | #if defined(CONFIG_SERIAL_AMBA_PL010_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
32 | #define SUPPORT_SYSRQ | |
33 | #endif | |
34 | ||
35 | #include <linux/module.h> | |
36 | #include <linux/ioport.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/console.h> | |
39 | #include <linux/sysrq.h> | |
40 | #include <linux/device.h> | |
41 | #include <linux/tty.h> | |
42 | #include <linux/tty_flip.h> | |
43 | #include <linux/serial_core.h> | |
44 | #include <linux/serial.h> | |
a62c80e5 RK |
45 | #include <linux/amba/bus.h> |
46 | #include <linux/amba/serial.h> | |
ed519ded | 47 | #include <linux/clk.h> |
5a0e3ad6 | 48 | #include <linux/slab.h> |
44acd260 | 49 | #include <linux/io.h> |
1da177e4 | 50 | |
4faf4e0e | 51 | #define UART_NR 8 |
1da177e4 LT |
52 | |
53 | #define SERIAL_AMBA_MAJOR 204 | |
54 | #define SERIAL_AMBA_MINOR 16 | |
55 | #define SERIAL_AMBA_NR UART_NR | |
56 | ||
57 | #define AMBA_ISR_PASS_LIMIT 256 | |
58 | ||
1da177e4 LT |
59 | #define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0) |
60 | #define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0) | |
1da177e4 | 61 | |
fbb18a27 | 62 | #define UART_DUMMY_RSR_RX 256 |
1da177e4 LT |
63 | #define UART_PORT_SIZE 64 |
64 | ||
1da177e4 LT |
65 | /* |
66 | * We wrap our port structure around the generic uart_port. | |
67 | */ | |
68 | struct uart_amba_port { | |
69 | struct uart_port port; | |
ed519ded | 70 | struct clk *clk; |
fbb18a27 RK |
71 | struct amba_device *dev; |
72 | struct amba_pl010_data *data; | |
1da177e4 LT |
73 | unsigned int old_status; |
74 | }; | |
75 | ||
b129a8cc | 76 | static void pl010_stop_tx(struct uart_port *port) |
1da177e4 | 77 | { |
b70e5e9d FF |
78 | struct uart_amba_port *uap = |
79 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
80 | unsigned int cr; |
81 | ||
1b0646a0 | 82 | cr = readb(uap->port.membase + UART010_CR); |
1da177e4 | 83 | cr &= ~UART010_CR_TIE; |
1b0646a0 | 84 | writel(cr, uap->port.membase + UART010_CR); |
1da177e4 LT |
85 | } |
86 | ||
b129a8cc | 87 | static void pl010_start_tx(struct uart_port *port) |
1da177e4 | 88 | { |
b70e5e9d FF |
89 | struct uart_amba_port *uap = |
90 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
91 | unsigned int cr; |
92 | ||
1b0646a0 | 93 | cr = readb(uap->port.membase + UART010_CR); |
1da177e4 | 94 | cr |= UART010_CR_TIE; |
1b0646a0 | 95 | writel(cr, uap->port.membase + UART010_CR); |
1da177e4 LT |
96 | } |
97 | ||
98 | static void pl010_stop_rx(struct uart_port *port) | |
99 | { | |
b70e5e9d FF |
100 | struct uart_amba_port *uap = |
101 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
102 | unsigned int cr; |
103 | ||
1b0646a0 | 104 | cr = readb(uap->port.membase + UART010_CR); |
1da177e4 | 105 | cr &= ~(UART010_CR_RIE | UART010_CR_RTIE); |
1b0646a0 | 106 | writel(cr, uap->port.membase + UART010_CR); |
1da177e4 LT |
107 | } |
108 | ||
cab68f89 PH |
109 | static void pl010_disable_ms(struct uart_port *port) |
110 | { | |
111 | struct uart_amba_port *uap = (struct uart_amba_port *)port; | |
112 | unsigned int cr; | |
113 | ||
114 | cr = readb(uap->port.membase + UART010_CR); | |
115 | cr &= ~UART010_CR_MSIE; | |
116 | writel(cr, uap->port.membase + UART010_CR); | |
117 | } | |
118 | ||
1da177e4 LT |
119 | static void pl010_enable_ms(struct uart_port *port) |
120 | { | |
b70e5e9d FF |
121 | struct uart_amba_port *uap = |
122 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
123 | unsigned int cr; |
124 | ||
1b0646a0 | 125 | cr = readb(uap->port.membase + UART010_CR); |
1da177e4 | 126 | cr |= UART010_CR_MSIE; |
1b0646a0 | 127 | writel(cr, uap->port.membase + UART010_CR); |
1da177e4 LT |
128 | } |
129 | ||
1b0646a0 | 130 | static void pl010_rx_chars(struct uart_amba_port *uap) |
1da177e4 | 131 | { |
1da177e4 LT |
132 | unsigned int status, ch, flag, rsr, max_count = 256; |
133 | ||
1b0646a0 | 134 | status = readb(uap->port.membase + UART01x_FR); |
1da177e4 | 135 | while (UART_RX_DATA(status) && max_count--) { |
1b0646a0 | 136 | ch = readb(uap->port.membase + UART01x_DR); |
1da177e4 LT |
137 | flag = TTY_NORMAL; |
138 | ||
1b0646a0 | 139 | uap->port.icount.rx++; |
1da177e4 LT |
140 | |
141 | /* | |
142 | * Note that the error handling code is | |
143 | * out of the main execution path | |
144 | */ | |
1b0646a0 | 145 | rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX; |
45849282 | 146 | if (unlikely(rsr & UART01x_RSR_ANY)) { |
1b0646a0 | 147 | writel(0, uap->port.membase + UART01x_ECR); |
a4ed06ad | 148 | |
1da177e4 LT |
149 | if (rsr & UART01x_RSR_BE) { |
150 | rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE); | |
1b0646a0 RK |
151 | uap->port.icount.brk++; |
152 | if (uart_handle_break(&uap->port)) | |
1da177e4 LT |
153 | goto ignore_char; |
154 | } else if (rsr & UART01x_RSR_PE) | |
1b0646a0 | 155 | uap->port.icount.parity++; |
1da177e4 | 156 | else if (rsr & UART01x_RSR_FE) |
1b0646a0 | 157 | uap->port.icount.frame++; |
1da177e4 | 158 | if (rsr & UART01x_RSR_OE) |
1b0646a0 | 159 | uap->port.icount.overrun++; |
1da177e4 | 160 | |
1b0646a0 | 161 | rsr &= uap->port.read_status_mask; |
1da177e4 LT |
162 | |
163 | if (rsr & UART01x_RSR_BE) | |
164 | flag = TTY_BREAK; | |
165 | else if (rsr & UART01x_RSR_PE) | |
166 | flag = TTY_PARITY; | |
167 | else if (rsr & UART01x_RSR_FE) | |
168 | flag = TTY_FRAME; | |
169 | } | |
170 | ||
1b0646a0 | 171 | if (uart_handle_sysrq_char(&uap->port, ch)) |
1da177e4 LT |
172 | goto ignore_char; |
173 | ||
1b0646a0 | 174 | uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag); |
05ab3014 | 175 | |
1da177e4 | 176 | ignore_char: |
1b0646a0 | 177 | status = readb(uap->port.membase + UART01x_FR); |
1da177e4 | 178 | } |
db002b85 | 179 | spin_unlock(&uap->port.lock); |
2e124b4a | 180 | tty_flip_buffer_push(&uap->port.state->port); |
db002b85 | 181 | spin_lock(&uap->port.lock); |
1da177e4 LT |
182 | } |
183 | ||
1b0646a0 | 184 | static void pl010_tx_chars(struct uart_amba_port *uap) |
1da177e4 | 185 | { |
ebd2c8f6 | 186 | struct circ_buf *xmit = &uap->port.state->xmit; |
1da177e4 LT |
187 | int count; |
188 | ||
1b0646a0 RK |
189 | if (uap->port.x_char) { |
190 | writel(uap->port.x_char, uap->port.membase + UART01x_DR); | |
191 | uap->port.icount.tx++; | |
192 | uap->port.x_char = 0; | |
1da177e4 LT |
193 | return; |
194 | } | |
1b0646a0 RK |
195 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { |
196 | pl010_stop_tx(&uap->port); | |
1da177e4 LT |
197 | return; |
198 | } | |
199 | ||
1b0646a0 | 200 | count = uap->port.fifosize >> 1; |
1da177e4 | 201 | do { |
1b0646a0 | 202 | writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); |
1da177e4 | 203 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
1b0646a0 | 204 | uap->port.icount.tx++; |
1da177e4 LT |
205 | if (uart_circ_empty(xmit)) |
206 | break; | |
207 | } while (--count > 0); | |
208 | ||
209 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1b0646a0 | 210 | uart_write_wakeup(&uap->port); |
1da177e4 LT |
211 | |
212 | if (uart_circ_empty(xmit)) | |
1b0646a0 | 213 | pl010_stop_tx(&uap->port); |
1da177e4 LT |
214 | } |
215 | ||
1b0646a0 | 216 | static void pl010_modem_status(struct uart_amba_port *uap) |
1da177e4 | 217 | { |
1da177e4 LT |
218 | unsigned int status, delta; |
219 | ||
98639a67 | 220 | writel(0, uap->port.membase + UART010_ICR); |
1da177e4 | 221 | |
98639a67 | 222 | status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; |
1da177e4 LT |
223 | |
224 | delta = status ^ uap->old_status; | |
225 | uap->old_status = status; | |
226 | ||
227 | if (!delta) | |
228 | return; | |
229 | ||
230 | if (delta & UART01x_FR_DCD) | |
231 | uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); | |
232 | ||
233 | if (delta & UART01x_FR_DSR) | |
234 | uap->port.icount.dsr++; | |
235 | ||
236 | if (delta & UART01x_FR_CTS) | |
237 | uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); | |
238 | ||
bdc04e31 | 239 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
240 | } |
241 | ||
7d12e780 | 242 | static irqreturn_t pl010_int(int irq, void *dev_id) |
1da177e4 | 243 | { |
1b0646a0 | 244 | struct uart_amba_port *uap = dev_id; |
1da177e4 LT |
245 | unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; |
246 | int handled = 0; | |
247 | ||
1b0646a0 | 248 | spin_lock(&uap->port.lock); |
1da177e4 | 249 | |
1b0646a0 | 250 | status = readb(uap->port.membase + UART010_IIR); |
1da177e4 LT |
251 | if (status) { |
252 | do { | |
253 | if (status & (UART010_IIR_RTIS | UART010_IIR_RIS)) | |
1b0646a0 | 254 | pl010_rx_chars(uap); |
1da177e4 | 255 | if (status & UART010_IIR_MIS) |
1b0646a0 | 256 | pl010_modem_status(uap); |
1da177e4 | 257 | if (status & UART010_IIR_TIS) |
1b0646a0 | 258 | pl010_tx_chars(uap); |
1da177e4 LT |
259 | |
260 | if (pass_counter-- == 0) | |
261 | break; | |
262 | ||
1b0646a0 | 263 | status = readb(uap->port.membase + UART010_IIR); |
1da177e4 LT |
264 | } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS | |
265 | UART010_IIR_TIS)); | |
266 | handled = 1; | |
267 | } | |
268 | ||
1b0646a0 | 269 | spin_unlock(&uap->port.lock); |
1da177e4 LT |
270 | |
271 | return IRQ_RETVAL(handled); | |
272 | } | |
273 | ||
274 | static unsigned int pl010_tx_empty(struct uart_port *port) | |
275 | { | |
b70e5e9d FF |
276 | struct uart_amba_port *uap = |
277 | container_of(port, struct uart_amba_port, port); | |
1b0646a0 RK |
278 | unsigned int status = readb(uap->port.membase + UART01x_FR); |
279 | return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT; | |
1da177e4 LT |
280 | } |
281 | ||
282 | static unsigned int pl010_get_mctrl(struct uart_port *port) | |
283 | { | |
b70e5e9d FF |
284 | struct uart_amba_port *uap = |
285 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
286 | unsigned int result = 0; |
287 | unsigned int status; | |
288 | ||
1b0646a0 | 289 | status = readb(uap->port.membase + UART01x_FR); |
1da177e4 LT |
290 | if (status & UART01x_FR_DCD) |
291 | result |= TIOCM_CAR; | |
292 | if (status & UART01x_FR_DSR) | |
293 | result |= TIOCM_DSR; | |
294 | if (status & UART01x_FR_CTS) | |
295 | result |= TIOCM_CTS; | |
296 | ||
297 | return result; | |
298 | } | |
299 | ||
300 | static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
301 | { | |
b70e5e9d FF |
302 | struct uart_amba_port *uap = |
303 | container_of(port, struct uart_amba_port, port); | |
1da177e4 | 304 | |
fbb18a27 RK |
305 | if (uap->data) |
306 | uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl); | |
1da177e4 LT |
307 | } |
308 | ||
309 | static void pl010_break_ctl(struct uart_port *port, int break_state) | |
310 | { | |
b70e5e9d FF |
311 | struct uart_amba_port *uap = |
312 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
313 | unsigned long flags; |
314 | unsigned int lcr_h; | |
315 | ||
1b0646a0 RK |
316 | spin_lock_irqsave(&uap->port.lock, flags); |
317 | lcr_h = readb(uap->port.membase + UART010_LCRH); | |
1da177e4 LT |
318 | if (break_state == -1) |
319 | lcr_h |= UART01x_LCRH_BRK; | |
320 | else | |
321 | lcr_h &= ~UART01x_LCRH_BRK; | |
1b0646a0 RK |
322 | writel(lcr_h, uap->port.membase + UART010_LCRH); |
323 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
1da177e4 LT |
324 | } |
325 | ||
326 | static int pl010_startup(struct uart_port *port) | |
327 | { | |
b70e5e9d FF |
328 | struct uart_amba_port *uap = |
329 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
330 | int retval; |
331 | ||
ed519ded RK |
332 | /* |
333 | * Try to enable the clock producer. | |
334 | */ | |
1c4c4394 | 335 | retval = clk_prepare_enable(uap->clk); |
ed519ded | 336 | if (retval) |
1c4c4394 | 337 | goto out; |
ed519ded RK |
338 | |
339 | uap->port.uartclk = clk_get_rate(uap->clk); | |
340 | ||
1da177e4 LT |
341 | /* |
342 | * Allocate the IRQ | |
343 | */ | |
1b0646a0 | 344 | retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap); |
1da177e4 | 345 | if (retval) |
ed519ded | 346 | goto clk_dis; |
1da177e4 LT |
347 | |
348 | /* | |
349 | * initialise the old status of the modem signals | |
350 | */ | |
1b0646a0 | 351 | uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; |
1da177e4 LT |
352 | |
353 | /* | |
354 | * Finally, enable interrupts | |
355 | */ | |
98639a67 | 356 | writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE, |
1b0646a0 | 357 | uap->port.membase + UART010_CR); |
1da177e4 LT |
358 | |
359 | return 0; | |
ed519ded RK |
360 | |
361 | clk_dis: | |
1c4c4394 | 362 | clk_disable_unprepare(uap->clk); |
ed519ded RK |
363 | out: |
364 | return retval; | |
1da177e4 LT |
365 | } |
366 | ||
367 | static void pl010_shutdown(struct uart_port *port) | |
368 | { | |
b70e5e9d FF |
369 | struct uart_amba_port *uap = |
370 | container_of(port, struct uart_amba_port, port); | |
1b0646a0 | 371 | |
1da177e4 LT |
372 | /* |
373 | * Free the interrupt | |
374 | */ | |
1b0646a0 | 375 | free_irq(uap->port.irq, uap); |
1da177e4 LT |
376 | |
377 | /* | |
378 | * disable all interrupts, disable the port | |
379 | */ | |
1b0646a0 | 380 | writel(0, uap->port.membase + UART010_CR); |
1da177e4 LT |
381 | |
382 | /* disable break condition and fifos */ | |
1b0646a0 | 383 | writel(readb(uap->port.membase + UART010_LCRH) & |
98639a67 | 384 | ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN), |
1b0646a0 | 385 | uap->port.membase + UART010_LCRH); |
ed519ded RK |
386 | |
387 | /* | |
388 | * Shut down the clock producer | |
389 | */ | |
1c4c4394 | 390 | clk_disable_unprepare(uap->clk); |
1da177e4 LT |
391 | } |
392 | ||
393 | static void | |
606d099c AC |
394 | pl010_set_termios(struct uart_port *port, struct ktermios *termios, |
395 | struct ktermios *old) | |
1da177e4 | 396 | { |
b70e5e9d FF |
397 | struct uart_amba_port *uap = |
398 | container_of(port, struct uart_amba_port, port); | |
1da177e4 LT |
399 | unsigned int lcr_h, old_cr; |
400 | unsigned long flags; | |
401 | unsigned int baud, quot; | |
402 | ||
403 | /* | |
404 | * Ask the core to calculate the divisor for us. | |
405 | */ | |
1b0646a0 | 406 | baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16); |
1da177e4 LT |
407 | quot = uart_get_divisor(port, baud); |
408 | ||
409 | switch (termios->c_cflag & CSIZE) { | |
410 | case CS5: | |
411 | lcr_h = UART01x_LCRH_WLEN_5; | |
412 | break; | |
413 | case CS6: | |
414 | lcr_h = UART01x_LCRH_WLEN_6; | |
415 | break; | |
416 | case CS7: | |
417 | lcr_h = UART01x_LCRH_WLEN_7; | |
418 | break; | |
419 | default: // CS8 | |
420 | lcr_h = UART01x_LCRH_WLEN_8; | |
421 | break; | |
422 | } | |
423 | if (termios->c_cflag & CSTOPB) | |
424 | lcr_h |= UART01x_LCRH_STP2; | |
425 | if (termios->c_cflag & PARENB) { | |
426 | lcr_h |= UART01x_LCRH_PEN; | |
427 | if (!(termios->c_cflag & PARODD)) | |
428 | lcr_h |= UART01x_LCRH_EPS; | |
429 | } | |
1b0646a0 | 430 | if (uap->port.fifosize > 1) |
1da177e4 LT |
431 | lcr_h |= UART01x_LCRH_FEN; |
432 | ||
1b0646a0 | 433 | spin_lock_irqsave(&uap->port.lock, flags); |
1da177e4 LT |
434 | |
435 | /* | |
436 | * Update the per-port timeout. | |
437 | */ | |
438 | uart_update_timeout(port, termios->c_cflag, baud); | |
439 | ||
1b0646a0 | 440 | uap->port.read_status_mask = UART01x_RSR_OE; |
1da177e4 | 441 | if (termios->c_iflag & INPCK) |
1b0646a0 | 442 | uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; |
ef8b9ddc | 443 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
1b0646a0 | 444 | uap->port.read_status_mask |= UART01x_RSR_BE; |
1da177e4 LT |
445 | |
446 | /* | |
447 | * Characters to ignore | |
448 | */ | |
1b0646a0 | 449 | uap->port.ignore_status_mask = 0; |
1da177e4 | 450 | if (termios->c_iflag & IGNPAR) |
1b0646a0 | 451 | uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; |
1da177e4 | 452 | if (termios->c_iflag & IGNBRK) { |
1b0646a0 | 453 | uap->port.ignore_status_mask |= UART01x_RSR_BE; |
1da177e4 LT |
454 | /* |
455 | * If we're ignoring parity and break indicators, | |
456 | * ignore overruns too (for real raw support). | |
457 | */ | |
458 | if (termios->c_iflag & IGNPAR) | |
1b0646a0 | 459 | uap->port.ignore_status_mask |= UART01x_RSR_OE; |
1da177e4 LT |
460 | } |
461 | ||
462 | /* | |
463 | * Ignore all characters if CREAD is not set. | |
464 | */ | |
465 | if ((termios->c_cflag & CREAD) == 0) | |
1b0646a0 | 466 | uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX; |
1da177e4 LT |
467 | |
468 | /* first, disable everything */ | |
1b0646a0 | 469 | old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE; |
1da177e4 LT |
470 | |
471 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
472 | old_cr |= UART010_CR_MSIE; | |
473 | ||
1b0646a0 | 474 | writel(0, uap->port.membase + UART010_CR); |
1da177e4 LT |
475 | |
476 | /* Set baud rate */ | |
477 | quot -= 1; | |
1b0646a0 RK |
478 | writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM); |
479 | writel(quot & 0xff, uap->port.membase + UART010_LCRL); | |
1da177e4 LT |
480 | |
481 | /* | |
482 | * ----------v----------v----------v----------v----- | |
483 | * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L | |
484 | * ----------^----------^----------^----------^----- | |
485 | */ | |
1b0646a0 RK |
486 | writel(lcr_h, uap->port.membase + UART010_LCRH); |
487 | writel(old_cr, uap->port.membase + UART010_CR); | |
1da177e4 | 488 | |
1b0646a0 | 489 | spin_unlock_irqrestore(&uap->port.lock, flags); |
1da177e4 LT |
490 | } |
491 | ||
732a84a0 | 492 | static void pl010_set_ldisc(struct uart_port *port, struct ktermios *termios) |
7ed63d5e | 493 | { |
732a84a0 | 494 | if (termios->c_line == N_PPS) { |
7ed63d5e | 495 | port->flags |= UPF_HARDPPS_CD; |
d41510ce | 496 | spin_lock_irq(&port->lock); |
7ed63d5e | 497 | pl010_enable_ms(port); |
d41510ce | 498 | spin_unlock_irq(&port->lock); |
cab68f89 | 499 | } else { |
7ed63d5e | 500 | port->flags &= ~UPF_HARDPPS_CD; |
cab68f89 PH |
501 | if (!UART_ENABLE_MS(port, termios->c_cflag)) { |
502 | spin_lock_irq(&port->lock); | |
503 | pl010_disable_ms(port); | |
504 | spin_unlock_irq(&port->lock); | |
505 | } | |
506 | } | |
7ed63d5e RG |
507 | } |
508 | ||
1da177e4 LT |
509 | static const char *pl010_type(struct uart_port *port) |
510 | { | |
511 | return port->type == PORT_AMBA ? "AMBA" : NULL; | |
512 | } | |
513 | ||
514 | /* | |
515 | * Release the memory region(s) being used by 'port' | |
516 | */ | |
517 | static void pl010_release_port(struct uart_port *port) | |
518 | { | |
519 | release_mem_region(port->mapbase, UART_PORT_SIZE); | |
520 | } | |
521 | ||
522 | /* | |
523 | * Request the memory region(s) being used by 'port' | |
524 | */ | |
525 | static int pl010_request_port(struct uart_port *port) | |
526 | { | |
527 | return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010") | |
528 | != NULL ? 0 : -EBUSY; | |
529 | } | |
530 | ||
531 | /* | |
532 | * Configure/autoconfigure the port. | |
533 | */ | |
534 | static void pl010_config_port(struct uart_port *port, int flags) | |
535 | { | |
536 | if (flags & UART_CONFIG_TYPE) { | |
537 | port->type = PORT_AMBA; | |
538 | pl010_request_port(port); | |
539 | } | |
540 | } | |
541 | ||
542 | /* | |
543 | * verify the new serial_struct (for TIOCSSERIAL). | |
544 | */ | |
545 | static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) | |
546 | { | |
547 | int ret = 0; | |
548 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) | |
549 | ret = -EINVAL; | |
a62c4133 | 550 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
551 | ret = -EINVAL; |
552 | if (ser->baud_base < 9600) | |
553 | ret = -EINVAL; | |
554 | return ret; | |
555 | } | |
556 | ||
557 | static struct uart_ops amba_pl010_pops = { | |
558 | .tx_empty = pl010_tx_empty, | |
559 | .set_mctrl = pl010_set_mctrl, | |
560 | .get_mctrl = pl010_get_mctrl, | |
561 | .stop_tx = pl010_stop_tx, | |
562 | .start_tx = pl010_start_tx, | |
563 | .stop_rx = pl010_stop_rx, | |
564 | .enable_ms = pl010_enable_ms, | |
565 | .break_ctl = pl010_break_ctl, | |
566 | .startup = pl010_startup, | |
567 | .shutdown = pl010_shutdown, | |
568 | .set_termios = pl010_set_termios, | |
7ed63d5e | 569 | .set_ldisc = pl010_set_ldisc, |
1da177e4 LT |
570 | .type = pl010_type, |
571 | .release_port = pl010_release_port, | |
572 | .request_port = pl010_request_port, | |
573 | .config_port = pl010_config_port, | |
574 | .verify_port = pl010_verify_port, | |
575 | }; | |
576 | ||
fbb18a27 | 577 | static struct uart_amba_port *amba_ports[UART_NR]; |
1da177e4 LT |
578 | |
579 | #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE | |
580 | ||
d358788f RK |
581 | static void pl010_console_putchar(struct uart_port *port, int ch) |
582 | { | |
b70e5e9d FF |
583 | struct uart_amba_port *uap = |
584 | container_of(port, struct uart_amba_port, port); | |
98639a67 RK |
585 | unsigned int status; |
586 | ||
587 | do { | |
1b0646a0 | 588 | status = readb(uap->port.membase + UART01x_FR); |
d358788f | 589 | barrier(); |
98639a67 | 590 | } while (!UART_TX_READY(status)); |
1b0646a0 | 591 | writel(ch, uap->port.membase + UART01x_DR); |
d358788f RK |
592 | } |
593 | ||
1da177e4 LT |
594 | static void |
595 | pl010_console_write(struct console *co, const char *s, unsigned int count) | |
596 | { | |
1b0646a0 | 597 | struct uart_amba_port *uap = amba_ports[co->index]; |
1da177e4 | 598 | unsigned int status, old_cr; |
1da177e4 | 599 | |
ed519ded RK |
600 | clk_enable(uap->clk); |
601 | ||
1da177e4 LT |
602 | /* |
603 | * First save the CR then disable the interrupts | |
604 | */ | |
1b0646a0 RK |
605 | old_cr = readb(uap->port.membase + UART010_CR); |
606 | writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR); | |
1da177e4 | 607 | |
1b0646a0 | 608 | uart_console_write(&uap->port, s, count, pl010_console_putchar); |
1da177e4 LT |
609 | |
610 | /* | |
611 | * Finally, wait for transmitter to become empty | |
612 | * and restore the TCR | |
613 | */ | |
614 | do { | |
1b0646a0 | 615 | status = readb(uap->port.membase + UART01x_FR); |
98639a67 | 616 | barrier(); |
1da177e4 | 617 | } while (status & UART01x_FR_BUSY); |
1b0646a0 | 618 | writel(old_cr, uap->port.membase + UART010_CR); |
ed519ded RK |
619 | |
620 | clk_disable(uap->clk); | |
1da177e4 LT |
621 | } |
622 | ||
623 | static void __init | |
1b0646a0 | 624 | pl010_console_get_options(struct uart_amba_port *uap, int *baud, |
1da177e4 LT |
625 | int *parity, int *bits) |
626 | { | |
1b0646a0 | 627 | if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) { |
1da177e4 | 628 | unsigned int lcr_h, quot; |
1b0646a0 | 629 | lcr_h = readb(uap->port.membase + UART010_LCRH); |
1da177e4 LT |
630 | |
631 | *parity = 'n'; | |
632 | if (lcr_h & UART01x_LCRH_PEN) { | |
633 | if (lcr_h & UART01x_LCRH_EPS) | |
634 | *parity = 'e'; | |
635 | else | |
636 | *parity = 'o'; | |
637 | } | |
638 | ||
639 | if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) | |
640 | *bits = 7; | |
641 | else | |
642 | *bits = 8; | |
643 | ||
1b0646a0 RK |
644 | quot = readb(uap->port.membase + UART010_LCRL) | |
645 | readb(uap->port.membase + UART010_LCRM) << 8; | |
646 | *baud = uap->port.uartclk / (16 * (quot + 1)); | |
1da177e4 LT |
647 | } |
648 | } | |
649 | ||
650 | static int __init pl010_console_setup(struct console *co, char *options) | |
651 | { | |
1b0646a0 | 652 | struct uart_amba_port *uap; |
1da177e4 LT |
653 | int baud = 38400; |
654 | int bits = 8; | |
655 | int parity = 'n'; | |
656 | int flow = 'n'; | |
36b8f1e2 | 657 | int ret; |
1da177e4 LT |
658 | |
659 | /* | |
660 | * Check whether an invalid uart number has been specified, and | |
661 | * if so, search for the first available port that does have | |
662 | * console support. | |
663 | */ | |
664 | if (co->index >= UART_NR) | |
665 | co->index = 0; | |
1b0646a0 RK |
666 | uap = amba_ports[co->index]; |
667 | if (!uap) | |
d28122a5 | 668 | return -ENODEV; |
1da177e4 | 669 | |
36b8f1e2 RK |
670 | ret = clk_prepare(uap->clk); |
671 | if (ret) | |
672 | return ret; | |
673 | ||
ed519ded RK |
674 | uap->port.uartclk = clk_get_rate(uap->clk); |
675 | ||
1da177e4 LT |
676 | if (options) |
677 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
678 | else | |
1b0646a0 | 679 | pl010_console_get_options(uap, &baud, &parity, &bits); |
1da177e4 | 680 | |
1b0646a0 | 681 | return uart_set_options(&uap->port, co, baud, parity, bits, flow); |
1da177e4 LT |
682 | } |
683 | ||
2d93486c | 684 | static struct uart_driver amba_reg; |
1da177e4 LT |
685 | static struct console amba_console = { |
686 | .name = "ttyAM", | |
687 | .write = pl010_console_write, | |
688 | .device = uart_console_device, | |
689 | .setup = pl010_console_setup, | |
690 | .flags = CON_PRINTBUFFER, | |
691 | .index = -1, | |
692 | .data = &amba_reg, | |
693 | }; | |
694 | ||
1da177e4 LT |
695 | #define AMBA_CONSOLE &amba_console |
696 | #else | |
697 | #define AMBA_CONSOLE NULL | |
698 | #endif | |
699 | ||
700 | static struct uart_driver amba_reg = { | |
701 | .owner = THIS_MODULE, | |
702 | .driver_name = "ttyAM", | |
703 | .dev_name = "ttyAM", | |
704 | .major = SERIAL_AMBA_MAJOR, | |
705 | .minor = SERIAL_AMBA_MINOR, | |
706 | .nr = UART_NR, | |
707 | .cons = AMBA_CONSOLE, | |
708 | }; | |
709 | ||
aa25afad | 710 | static int pl010_probe(struct amba_device *dev, const struct amba_id *id) |
1da177e4 | 711 | { |
1b0646a0 | 712 | struct uart_amba_port *uap; |
fbb18a27 RK |
713 | void __iomem *base; |
714 | int i, ret; | |
1da177e4 | 715 | |
fbb18a27 RK |
716 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) |
717 | if (amba_ports[i] == NULL) | |
718 | break; | |
1da177e4 | 719 | |
44acd260 TB |
720 | if (i == ARRAY_SIZE(amba_ports)) |
721 | return -EBUSY; | |
1da177e4 | 722 | |
44acd260 TB |
723 | uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port), |
724 | GFP_KERNEL); | |
725 | if (!uap) | |
726 | return -ENOMEM; | |
fbb18a27 | 727 | |
44acd260 TB |
728 | base = devm_ioremap(&dev->dev, dev->res.start, |
729 | resource_size(&dev->res)); | |
730 | if (!base) | |
731 | return -ENOMEM; | |
fbb18a27 | 732 | |
44acd260 TB |
733 | uap->clk = devm_clk_get(&dev->dev, NULL); |
734 | if (IS_ERR(uap->clk)) | |
735 | return PTR_ERR(uap->clk); | |
ed519ded | 736 | |
1b0646a0 RK |
737 | uap->port.dev = &dev->dev; |
738 | uap->port.mapbase = dev->res.start; | |
739 | uap->port.membase = base; | |
740 | uap->port.iotype = UPIO_MEM; | |
741 | uap->port.irq = dev->irq[0]; | |
1b0646a0 RK |
742 | uap->port.fifosize = 16; |
743 | uap->port.ops = &amba_pl010_pops; | |
744 | uap->port.flags = UPF_BOOT_AUTOCONF; | |
745 | uap->port.line = i; | |
746 | uap->dev = dev; | |
574de559 | 747 | uap->data = dev_get_platdata(&dev->dev); |
1b0646a0 RK |
748 | |
749 | amba_ports[i] = uap; | |
750 | ||
751 | amba_set_drvdata(dev, uap); | |
752 | ret = uart_add_one_port(&amba_reg, &uap->port); | |
44acd260 | 753 | if (ret) |
fbb18a27 | 754 | amba_ports[i] = NULL; |
44acd260 | 755 | |
fbb18a27 | 756 | return ret; |
1da177e4 LT |
757 | } |
758 | ||
759 | static int pl010_remove(struct amba_device *dev) | |
760 | { | |
1b0646a0 | 761 | struct uart_amba_port *uap = amba_get_drvdata(dev); |
fbb18a27 | 762 | int i; |
1da177e4 | 763 | |
1b0646a0 | 764 | uart_remove_one_port(&amba_reg, &uap->port); |
fbb18a27 RK |
765 | |
766 | for (i = 0; i < ARRAY_SIZE(amba_ports); i++) | |
1b0646a0 | 767 | if (amba_ports[i] == uap) |
fbb18a27 RK |
768 | amba_ports[i] = NULL; |
769 | ||
1da177e4 LT |
770 | return 0; |
771 | } | |
772 | ||
95468240 UH |
773 | #ifdef CONFIG_PM_SLEEP |
774 | static int pl010_suspend(struct device *dev) | |
1da177e4 | 775 | { |
95468240 | 776 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
1da177e4 LT |
777 | |
778 | if (uap) | |
779 | uart_suspend_port(&amba_reg, &uap->port); | |
780 | ||
781 | return 0; | |
782 | } | |
783 | ||
95468240 | 784 | static int pl010_resume(struct device *dev) |
1da177e4 | 785 | { |
95468240 | 786 | struct uart_amba_port *uap = dev_get_drvdata(dev); |
1da177e4 LT |
787 | |
788 | if (uap) | |
789 | uart_resume_port(&amba_reg, &uap->port); | |
790 | ||
791 | return 0; | |
792 | } | |
95468240 UH |
793 | #endif |
794 | ||
795 | static SIMPLE_DEV_PM_OPS(pl010_dev_pm_ops, pl010_suspend, pl010_resume); | |
1da177e4 | 796 | |
2c39c9e1 | 797 | static struct amba_id pl010_ids[] = { |
1da177e4 LT |
798 | { |
799 | .id = 0x00041010, | |
800 | .mask = 0x000fffff, | |
801 | }, | |
802 | { 0, 0 }, | |
803 | }; | |
804 | ||
a664a119 DM |
805 | MODULE_DEVICE_TABLE(amba, pl010_ids); |
806 | ||
1da177e4 LT |
807 | static struct amba_driver pl010_driver = { |
808 | .drv = { | |
809 | .name = "uart-pl010", | |
95468240 | 810 | .pm = &pl010_dev_pm_ops, |
1da177e4 LT |
811 | }, |
812 | .id_table = pl010_ids, | |
813 | .probe = pl010_probe, | |
814 | .remove = pl010_remove, | |
1da177e4 LT |
815 | }; |
816 | ||
817 | static int __init pl010_init(void) | |
818 | { | |
819 | int ret; | |
820 | ||
d87a6d95 | 821 | printk(KERN_INFO "Serial: AMBA driver\n"); |
1da177e4 LT |
822 | |
823 | ret = uart_register_driver(&amba_reg); | |
824 | if (ret == 0) { | |
825 | ret = amba_driver_register(&pl010_driver); | |
826 | if (ret) | |
827 | uart_unregister_driver(&amba_reg); | |
828 | } | |
829 | return ret; | |
830 | } | |
831 | ||
832 | static void __exit pl010_exit(void) | |
833 | { | |
834 | amba_driver_unregister(&pl010_driver); | |
835 | uart_unregister_driver(&amba_reg); | |
836 | } | |
837 | ||
838 | module_init(pl010_init); | |
839 | module_exit(pl010_exit); | |
840 | ||
841 | MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); | |
d87a6d95 | 842 | MODULE_DESCRIPTION("ARM AMBA serial port driver"); |
1da177e4 | 843 | MODULE_LICENSE("GPL"); |