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Merge tag 'libnvdimm-for-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm...
[deliverable/linux.git] / drivers / tty / serial / atmel_serial.c
CommitLineData
1e6c9c28 1/*
7192f92c 2 * Driver for Atmel AT91 / AT32 Serial ports
1e6c9c28
AV		 3 * Copyright (C) 2003 Rick Bronson
4 *
5 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
a6670615
CC		 8 * DMA support added by Chip Coldwell.
9 *
1e6c9c28
AV		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
1e6c9c28
AV		 25#include <linux/tty.h>
26#include <linux/ioport.h>
27#include <linux/slab.h>
28#include <linux/init.h>
29#include <linux/serial.h>
afefc415 30#include <linux/clk.h>
1e6c9c28
AV		 31#include <linux/console.h>
32#include <linux/sysrq.h>
33#include <linux/tty_flip.h>
afefc415 34#include <linux/platform_device.h>
5fbe46b6
NF		 35#include <linux/of.h>
36#include <linux/of_device.h>
354e57f3 37#include <linux/of_gpio.h>
a6670615 38#include <linux/dma-mapping.h>
6b997bab 39#include <linux/dmaengine.h>
93a3ddc2 40#include <linux/atmel_pdc.h>
fa3218d8 41#include <linux/atmel_serial.h>
e8faff73 42#include <linux/uaccess.h>
bcd2360c 43#include <linux/platform_data/atmel.h>
2e68c22f 44#include <linux/timer.h>
354e57f3 45#include <linux/gpio.h>
e0b0baad
RG		 46#include <linux/gpio/consumer.h>
47#include <linux/err.h>
ab5e4e41 48#include <linux/irq.h>
2c7af5ba 49#include <linux/suspend.h>
1e6c9c28
AV		 50
51#include <asm/io.h>
f7512e7c 52#include <asm/ioctls.h>
1e6c9c28 53
a6670615
CC		 54#define PDC_BUFFER_SIZE 512
55/* Revisit: We should calculate this based on the actual port settings */
56#define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
57
b5199d46
CP		 58/* The minium number of data FIFOs should be able to contain */
59#define ATMEL_MIN_FIFO_SIZE 8
60/*
61 * These two offsets are substracted from the RX FIFO size to define the RTS
62 * high and low thresholds
63 */
64#define ATMEL_RTS_HIGH_OFFSET 16
65#define ATMEL_RTS_LOW_OFFSET 20
66
749c4e60 67#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
1e6c9c28
AV		 68#define SUPPORT_SYSRQ
69#endif
70
71#include <linux/serial_core.h>
72
e0b0baad
RG		 73#include "serial_mctrl_gpio.h"
74
e8faff73
CS		 75static void atmel_start_rx(struct uart_port *port);
76static void atmel_stop_rx(struct uart_port *port);
77
749c4e60 78#ifdef CONFIG_SERIAL_ATMEL_TTYAT
1e6c9c28
AV		 79
80/* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
81 * should coexist with the 8250 driver, such as if we have an external 16C550
82 * UART. */
7192f92c 83#define SERIAL_ATMEL_MAJOR 204
1e6c9c28 84#define MINOR_START 154
7192f92c 85#define ATMEL_DEVICENAME "ttyAT"
1e6c9c28
AV		 86
87#else
88
89/* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
90 * name, but it is legally reserved for the 8250 driver. */
7192f92c 91#define SERIAL_ATMEL_MAJOR TTY_MAJOR
1e6c9c28 92#define MINOR_START 64
7192f92c 93#define ATMEL_DEVICENAME "ttyS"
1e6c9c28
AV		 94
95#endif
96
7192f92c 97#define ATMEL_ISR_PASS_LIMIT 256
1e6c9c28 98
a6670615
CC		 99struct atmel_dma_buffer {
100 unsigned char *buf;
101 dma_addr_t dma_addr;
102 unsigned int dma_size;
103 unsigned int ofs;
104};
105
1ecc26bd
RB		 106struct atmel_uart_char {
107 u16 status;
108 u16 ch;
109};
110
637ba54f
LD		 111/*
112 * Be careful, the real size of the ring buffer is
113 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
114 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
115 * DMA mode.
116 */
1ecc26bd
RB		 117#define ATMEL_SERIAL_RINGSIZE 1024
118
9af92fbf
AB		 119/*
120 * at91: 6 USARTs and one DBGU port (SAM9260)
121 * avr32: 4
122 */
123#define ATMEL_MAX_UART 7
124
afefc415
AV		 125/*
126 * We wrap our port structure around the generic uart_port.
127 */
7192f92c 128struct atmel_uart_port {
afefc415
AV		 129 struct uart_port uart; /* uart */
130 struct clk *clk; /* uart clock */
f05596db
AS		 131 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
132 u32 backup_imr; /* IMR saved during suspend */
9e6077bd 133 int break_active; /* break being received */
1ecc26bd 134
34df42f5 135 bool use_dma_rx; /* enable DMA receiver */
64e22ebe 136 bool use_pdc_rx; /* enable PDC receiver */
a6670615
CC		 137 short pdc_rx_idx; /* current PDC RX buffer */
138 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
139
08f738be 140 bool use_dma_tx; /* enable DMA transmitter */
64e22ebe 141 bool use_pdc_tx; /* enable PDC transmitter */
a6670615
CC		 142 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
143
08f738be 144 spinlock_t lock_tx; /* port lock */
34df42f5 145 spinlock_t lock_rx; /* port lock */
08f738be 146 struct dma_chan *chan_tx;
34df42f5 147 struct dma_chan *chan_rx;
08f738be 148 struct dma_async_tx_descriptor *desc_tx;
34df42f5 149 struct dma_async_tx_descriptor *desc_rx;
08f738be 150 dma_cookie_t cookie_tx;
34df42f5 151 dma_cookie_t cookie_rx;
08f738be 152 struct scatterlist sg_tx;
34df42f5 153 struct scatterlist sg_rx;
00e8e658
NF		 154 struct tasklet_struct tasklet_rx;
155 struct tasklet_struct tasklet_tx;
98f2082c 156 atomic_t tasklet_shutdown;
1ecc26bd 157 unsigned int irq_status_prev;
5f258b3e 158 unsigned int tx_len;
1ecc26bd
RB		 159
160 struct circ_buf rx_ring;
e8faff73 161
e0b0baad 162 struct mctrl_gpios *gpios;
e8faff73 163 unsigned int tx_done_mask;
b5199d46
CP		 164 u32 fifo_size;
165 u32 rts_high;
166 u32 rts_low;
ab5e4e41 167 bool ms_irq_enabled;
2958ccee 168 u32 rtor; /* address of receiver timeout register if it exists */
4b769371
NF		 169 bool has_hw_timer;
170 struct timer_list uart_timer;
2c7af5ba
BB		 171
172 bool suspended;
173 unsigned int pending;
174 unsigned int pending_status;
175 spinlock_t lock_suspended;
176
a930e528
ES		 177 int (*prepare_rx)(struct uart_port *port);
178 int (*prepare_tx)(struct uart_port *port);
179 void (*schedule_rx)(struct uart_port *port);
180 void (*schedule_tx)(struct uart_port *port);
181 void (*release_rx)(struct uart_port *port);
182 void (*release_tx)(struct uart_port *port);
afefc415
AV		 183};
184
7192f92c 185static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
503bded9 186static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
afefc415 187
1e6c9c28 188#ifdef SUPPORT_SYSRQ
7192f92c 189static struct console atmel_console;
1e6c9c28
AV		 190#endif
191
5fbe46b6
NF		 192#if defined(CONFIG_OF)
193static const struct of_device_id atmel_serial_dt_ids[] = {
194 { .compatible = "atmel,at91rm9200-usart" },
195 { .compatible = "atmel,at91sam9260-usart" },
196 { /* sentinel */ }
197};
5fbe46b6
NF		 198#endif
199
c811ab8c
HS		 200static inline struct atmel_uart_port *
201to_atmel_uart_port(struct uart_port *uart)
202{
203 return container_of(uart, struct atmel_uart_port, uart);
204}
205
4e7decda
CP		 206static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
207{
208 return __raw_readl(port->membase + reg);
209}
210
211static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
212{
213 __raw_writel(value, port->membase + reg);
214}
215
a6499435
CP		 216#ifdef CONFIG_AVR32
217
218/* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */
219static inline u8 atmel_uart_read_char(struct uart_port *port)
220{
221 return __raw_readl(port->membase + ATMEL_US_RHR);
222}
223
224static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
b5199d46 225{
a6499435 226 __raw_writel(value, port->membase + ATMEL_US_THR);
b5199d46
CP		 227}
228
a6499435
CP		 229#else
230
231static inline u8 atmel_uart_read_char(struct uart_port *port)
b5199d46 232{
a6499435 233 return __raw_readb(port->membase + ATMEL_US_RHR);
b5199d46
CP		 234}
235
a6499435
CP		 236static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
237{
238 __raw_writeb(value, port->membase + ATMEL_US_THR);
239}
240
241#endif
242
a6670615 243#ifdef CONFIG_SERIAL_ATMEL_PDC
64e22ebe 244static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615 245{
c811ab8c 246 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 247
64e22ebe 248 return atmel_port->use_pdc_rx;
a6670615
CC		 249}
250
64e22ebe 251static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615 252{
c811ab8c 253 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
a6670615 254
64e22ebe 255 return atmel_port->use_pdc_tx;
a6670615
CC		 256}
257#else
64e22ebe 258static bool atmel_use_pdc_rx(struct uart_port *port)
a6670615
CC		 259{
260 return false;
261}
262
64e22ebe 263static bool atmel_use_pdc_tx(struct uart_port *port)
a6670615
CC		 264{
265 return false;
266}
267#endif
268
08f738be
ES		 269static bool atmel_use_dma_tx(struct uart_port *port)
270{
271 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
272
273 return atmel_port->use_dma_tx;
274}
275
34df42f5
ES		 276static bool atmel_use_dma_rx(struct uart_port *port)
277{
278 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
279
280 return atmel_port->use_dma_rx;
281}
282
5be605ac
AB		 283static bool atmel_use_fifo(struct uart_port *port)
284{
285 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
286
287 return atmel_port->fifo_size;
288}
289
98f2082c
NF		 290static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
291 struct tasklet_struct *t)
292{
293 if (!atomic_read(&atmel_port->tasklet_shutdown))
294 tasklet_schedule(t);
295}
296
e0b0baad
RG		 297static unsigned int atmel_get_lines_status(struct uart_port *port)
298{
299 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
300 unsigned int status, ret = 0;
301
4e7decda 302 status = atmel_uart_readl(port, ATMEL_US_CSR);
e0b0baad
RG		 303
304 mctrl_gpio_get(atmel_port->gpios, &ret);
305
306 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
307 UART_GPIO_CTS))) {
308 if (ret & TIOCM_CTS)
309 status &= ~ATMEL_US_CTS;
310 else
311 status |= ATMEL_US_CTS;
312 }
313
314 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
315 UART_GPIO_DSR))) {
316 if (ret & TIOCM_DSR)
317 status &= ~ATMEL_US_DSR;
318 else
319 status |= ATMEL_US_DSR;
320 }
321
322 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
323 UART_GPIO_RI))) {
324 if (ret & TIOCM_RI)
325 status &= ~ATMEL_US_RI;
326 else
327 status |= ATMEL_US_RI;
328 }
329
330 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
331 UART_GPIO_DCD))) {
332 if (ret & TIOCM_CD)
333 status &= ~ATMEL_US_DCD;
334 else
335 status |= ATMEL_US_DCD;
336 }
337
338 return status;
339}
340
e8faff73 341/* Enable or disable the rs485 support */
13bd3e6f
RRD		 342static int atmel_config_rs485(struct uart_port *port,
343 struct serial_rs485 *rs485conf)
e8faff73
CS		 344{
345 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
346 unsigned int mode;
e8faff73
CS		 347
348 /* Disable interrupts */
4e7decda 349 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
e8faff73 350
4e7decda 351 mode = atmel_uart_readl(port, ATMEL_US_MR);
e8faff73
CS		 352
353 /* Resetting serial mode to RS232 (0x0) */
354 mode &= ~ATMEL_US_USMODE;
355
13bd3e6f 356 port->rs485 = *rs485conf;
e8faff73
CS		 357
358 if (rs485conf->flags & SER_RS485_ENABLED) {
359 dev_dbg(port->dev, "Setting UART to RS485\n");
360 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
4e7decda
CP		 361 atmel_uart_writel(port, ATMEL_US_TTGR,
362 rs485conf->delay_rts_after_send);
e8faff73
CS		 363 mode |= ATMEL_US_USMODE_RS485;
364 } else {
365 dev_dbg(port->dev, "Setting UART to RS232\n");
64e22ebe 366 if (atmel_use_pdc_tx(port))
e8faff73
CS		 367 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
368 ATMEL_US_TXBUFE;
369 else
370 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
371 }
4e7decda 372 atmel_uart_writel(port, ATMEL_US_MR, mode);
e8faff73
CS		 373
374 /* Enable interrupts */
4e7decda 375 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
e8faff73 376
13bd3e6f 377 return 0;
e8faff73
CS		 378}
379
1e6c9c28
AV		 380/*
381 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
382 */
7192f92c 383static u_int atmel_tx_empty(struct uart_port *port)
1e6c9c28 384{
4e7decda
CP		 385 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
386 TIOCSER_TEMT :
387 0;
1e6c9c28
AV		 388}
389
390/*
391 * Set state of the modem control output lines
392 */
7192f92c 393static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
1e6c9c28
AV		 394{
395 unsigned int control = 0;
4e7decda 396 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
1cf6e8fc 397 unsigned int rts_paused, rts_ready;
e8faff73 398 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 399
1cf6e8fc
CP		 400 /* override mode to RS485 if needed, otherwise keep the current mode */
401 if (port->rs485.flags & SER_RS485_ENABLED) {
4e7decda
CP		 402 atmel_uart_writel(port, ATMEL_US_TTGR,
403 port->rs485.delay_rts_after_send);
1cf6e8fc
CP		 404 mode &= ~ATMEL_US_USMODE;
405 mode |= ATMEL_US_USMODE_RS485;
406 }
407
408 /* set the RTS line state according to the mode */
409 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
410 /* force RTS line to high level */
411 rts_paused = ATMEL_US_RTSEN;
412
413 /* give the control of the RTS line back to the hardware */
414 rts_ready = ATMEL_US_RTSDIS;
415 } else {
416 /* force RTS line to high level */
417 rts_paused = ATMEL_US_RTSDIS;
418
419 /* force RTS line to low level */
420 rts_ready = ATMEL_US_RTSEN;
421 }
422
1e6c9c28 423 if (mctrl & TIOCM_RTS)
1cf6e8fc 424 control |= rts_ready;
1e6c9c28 425 else
1cf6e8fc 426 control |= rts_paused;
1e6c9c28
AV		 427
428 if (mctrl & TIOCM_DTR)
7192f92c 429 control |= ATMEL_US_DTREN;
1e6c9c28 430 else
7192f92c 431 control |= ATMEL_US_DTRDIS;
1e6c9c28 432
4e7decda 433 atmel_uart_writel(port, ATMEL_US_CR, control);
afefc415 434
e0b0baad
RG		 435 mctrl_gpio_set(atmel_port->gpios, mctrl);
436
afefc415 437 /* Local loopback mode? */
1cf6e8fc 438 mode &= ~ATMEL_US_CHMODE;
afefc415 439 if (mctrl & TIOCM_LOOP)
7192f92c 440 mode |= ATMEL_US_CHMODE_LOC_LOOP;
afefc415 441 else
7192f92c 442 mode |= ATMEL_US_CHMODE_NORMAL;
e8faff73 443
4e7decda 444 atmel_uart_writel(port, ATMEL_US_MR, mode);
1e6c9c28
AV		 445}
446
447/*
448 * Get state of the modem control input lines
449 */
7192f92c 450static u_int atmel_get_mctrl(struct uart_port *port)
1e6c9c28 451{
e0b0baad
RG		 452 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
453 unsigned int ret = 0, status;
1e6c9c28 454
4e7decda 455 status = atmel_uart_readl(port, ATMEL_US_CSR);
1e6c9c28
AV		 456
457 /*
458 * The control signals are active low.
459 */
7192f92c 460 if (!(status & ATMEL_US_DCD))
1e6c9c28 461 ret |= TIOCM_CD;
7192f92c 462 if (!(status & ATMEL_US_CTS))
1e6c9c28 463 ret |= TIOCM_CTS;
7192f92c 464 if (!(status & ATMEL_US_DSR))
1e6c9c28 465 ret |= TIOCM_DSR;
7192f92c 466 if (!(status & ATMEL_US_RI))
1e6c9c28
AV		 467 ret |= TIOCM_RI;
468
e0b0baad 469 return mctrl_gpio_get(atmel_port->gpios, &ret);
1e6c9c28
AV		 470}
471
472/*
473 * Stop transmitting.
474 */
7192f92c 475static void atmel_stop_tx(struct uart_port *port)
1e6c9c28 476{
e8faff73
CS		 477 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
478
64e22ebe 479 if (atmel_use_pdc_tx(port)) {
a6670615 480 /* disable PDC transmit */
4e7decda 481 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
e8faff73
CS		 482 }
483 /* Disable interrupts */
4e7decda 484 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
e8faff73 485
13bd3e6f
RRD		 486 if ((port->rs485.flags & SER_RS485_ENABLED) &&
487 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
e8faff73 488 atmel_start_rx(port);
1e6c9c28
AV		 489}
490
491/*
492 * Start transmitting.
493 */
7192f92c 494static void atmel_start_tx(struct uart_port *port)
1e6c9c28 495{
e8faff73
CS		 496 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
497
0058f087
AB		 498 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
499 & ATMEL_PDC_TXTEN))
500 /* The transmitter is already running. Yes, we
501 really need this.*/
502 return;
a6670615 503
0058f087 504 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
13bd3e6f
RRD		 505 if ((port->rs485.flags & SER_RS485_ENABLED) &&
506 !(port->rs485.flags & SER_RS485_RX_DURING_TX))
e8faff73
CS		 507 atmel_stop_rx(port);
508
0058f087 509 if (atmel_use_pdc_tx(port))
a6670615 510 /* re-enable PDC transmit */
4e7decda 511 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
0058f087 512
e8faff73 513 /* Enable interrupts */
4e7decda 514 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
e8faff73
CS		 515}
516
517/*
518 * start receiving - port is in process of being opened.
519 */
520static void atmel_start_rx(struct uart_port *port)
521{
4e7decda
CP		 522 /* reset status and receiver */
523 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
e8faff73 524
4e7decda 525 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
57c36868 526
64e22ebe 527 if (atmel_use_pdc_rx(port)) {
e8faff73 528 /* enable PDC controller */
4e7decda
CP		 529 atmel_uart_writel(port, ATMEL_US_IER,
530 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
531 port->read_status_mask);
532 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
e8faff73 533 } else {
4e7decda 534 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
e8faff73 535 }
1e6c9c28
AV		 536}
537
538/*
539 * Stop receiving - port is in process of being closed.
540 */
7192f92c 541static void atmel_stop_rx(struct uart_port *port)
1e6c9c28 542{
4e7decda 543 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
57c36868 544
64e22ebe 545 if (atmel_use_pdc_rx(port)) {
a6670615 546 /* disable PDC receive */
4e7decda
CP		 547 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
548 atmel_uart_writel(port, ATMEL_US_IDR,
549 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
550 port->read_status_mask);
e8faff73 551 } else {
4e7decda 552 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
e8faff73 553 }
1e6c9c28
AV		 554}
555
556/*
557 * Enable modem status interrupts
558 */
7192f92c 559static void atmel_enable_ms(struct uart_port *port)
1e6c9c28 560{
ab5e4e41
RG		 561 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
562 uint32_t ier = 0;
563
564 /*
565 * Interrupt should not be enabled twice
566 */
567 if (atmel_port->ms_irq_enabled)
568 return;
569
570 atmel_port->ms_irq_enabled = true;
571
18dfef9c 572 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
ab5e4e41
RG		 573 ier |= ATMEL_US_CTSIC;
574
18dfef9c 575 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
ab5e4e41
RG		 576 ier |= ATMEL_US_DSRIC;
577
18dfef9c 578 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
ab5e4e41
RG		 579 ier |= ATMEL_US_RIIC;
580
18dfef9c 581 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
ab5e4e41
RG		 582 ier |= ATMEL_US_DCDIC;
583
4e7decda 584 atmel_uart_writel(port, ATMEL_US_IER, ier);
18dfef9c
UKK		 585
586 mctrl_gpio_enable_ms(atmel_port->gpios);
1e6c9c28
AV		 587}
588
35b675b9
RG		 589/*
590 * Disable modem status interrupts
591 */
592static void atmel_disable_ms(struct uart_port *port)
593{
594 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
595 uint32_t idr = 0;
596
597 /*
598 * Interrupt should not be disabled twice
599 */
600 if (!atmel_port->ms_irq_enabled)
601 return;
602
603 atmel_port->ms_irq_enabled = false;
604
18dfef9c
UKK		 605 mctrl_gpio_disable_ms(atmel_port->gpios);
606
607 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
35b675b9
RG		 608 idr |= ATMEL_US_CTSIC;
609
18dfef9c 610 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
35b675b9
RG		 611 idr |= ATMEL_US_DSRIC;
612
18dfef9c 613 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
35b675b9
RG		 614 idr |= ATMEL_US_RIIC;
615
18dfef9c 616 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
35b675b9
RG		 617 idr |= ATMEL_US_DCDIC;
618
4e7decda 619 atmel_uart_writel(port, ATMEL_US_IDR, idr);
35b675b9
RG		 620}
621
1e6c9c28
AV		 622/*
623 * Control the transmission of a break signal
624 */
7192f92c 625static void atmel_break_ctl(struct uart_port *port, int break_state)
1e6c9c28
AV		 626{
627 if (break_state != 0)
4e7decda
CP		 628 /* start break */
629 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
1e6c9c28 630 else
4e7decda
CP		 631 /* stop break */
632 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
1e6c9c28
AV		 633}
634
1ecc26bd
RB		 635/*
636 * Stores the incoming character in the ring buffer
637 */
638static void
639atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
640 unsigned int ch)
641{
c811ab8c 642 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 643 struct circ_buf *ring = &atmel_port->rx_ring;
644 struct atmel_uart_char *c;
645
646 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
647 /* Buffer overflow, ignore char */
648 return;
649
650 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
651 c->status = status;
652 c->ch = ch;
653
654 /* Make sure the character is stored before we update head. */
655 smp_wmb();
656
657 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
658}
659
a6670615
CC		 660/*
661 * Deal with parity, framing and overrun errors.
662 */
663static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
664{
665 /* clear error */
4e7decda 666 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
a6670615
CC		 667
668 if (status & ATMEL_US_RXBRK) {
669 /* ignore side-effect */
670 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
671 port->icount.brk++;
672 }
673 if (status & ATMEL_US_PARE)
674 port->icount.parity++;
675 if (status & ATMEL_US_FRAME)
676 port->icount.frame++;
677 if (status & ATMEL_US_OVRE)
678 port->icount.overrun++;
679}
680
1e6c9c28
AV		 681/*
682 * Characters received (called from interrupt handler)
683 */
7d12e780 684static void atmel_rx_chars(struct uart_port *port)
1e6c9c28 685{
c811ab8c 686 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 687 unsigned int status, ch;
1e6c9c28 688
4e7decda 689 status = atmel_uart_readl(port, ATMEL_US_CSR);
7192f92c 690 while (status & ATMEL_US_RXRDY) {
a6499435 691 ch = atmel_uart_read_char(port);
1e6c9c28 692
1e6c9c28
AV		 693 /*
694 * note that the error handling code is
695 * out of the main execution path
696 */
9e6077bd
HS		 697 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
698 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
699 || atmel_port->break_active)) {
1ecc26bd 700
b843aa21 701 /* clear error */
4e7decda 702 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1ecc26bd 703
9e6077bd
HS		 704 if (status & ATMEL_US_RXBRK
705 && !atmel_port->break_active) {
9e6077bd 706 atmel_port->break_active = 1;
4e7decda
CP		 707 atmel_uart_writel(port, ATMEL_US_IER,
708 ATMEL_US_RXBRK);
9e6077bd
HS		 709 } else {
710 /*
711 * This is either the end-of-break
712 * condition or we've received at
713 * least one character without RXBRK
714 * being set. In both cases, the next
715 * RXBRK will indicate start-of-break.
716 */
4e7decda
CP		 717 atmel_uart_writel(port, ATMEL_US_IDR,
718 ATMEL_US_RXBRK);
9e6077bd
HS		 719 status &= ~ATMEL_US_RXBRK;
720 atmel_port->break_active = 0;
afefc415 721 }
1e6c9c28
AV		 722 }
723
1ecc26bd 724 atmel_buffer_rx_char(port, status, ch);
4e7decda 725 status = atmel_uart_readl(port, ATMEL_US_CSR);
1e6c9c28
AV		 726 }
727
98f2082c 728 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1e6c9c28
AV		 729}
730
731/*
1ecc26bd
RB		 732 * Transmit characters (called from tasklet with TXRDY interrupt
733 * disabled)
1e6c9c28 734 */
7192f92c 735static void atmel_tx_chars(struct uart_port *port)
1e6c9c28 736{
ebd2c8f6 737 struct circ_buf *xmit = &port->state->xmit;
e8faff73 738 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1e6c9c28 739
4e7decda
CP		 740 if (port->x_char &&
741 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
a6499435 742 atmel_uart_write_char(port, port->x_char);
1e6c9c28
AV		 743 port->icount.tx++;
744 port->x_char = 0;
1e6c9c28 745 }
1ecc26bd 746 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
1e6c9c28 747 return;
1e6c9c28 748
4e7decda
CP		 749 while (atmel_uart_readl(port, ATMEL_US_CSR) &
750 atmel_port->tx_done_mask) {
a6499435 751 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
1e6c9c28
AV		 752 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
753 port->icount.tx++;
754 if (uart_circ_empty(xmit))
755 break;
756 }
757
758 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
759 uart_write_wakeup(port);
760
1ecc26bd 761 if (!uart_circ_empty(xmit))
e8faff73 762 /* Enable interrupts */
4e7decda
CP		 763 atmel_uart_writel(port, ATMEL_US_IER,
764 atmel_port->tx_done_mask);
1e6c9c28
AV		 765}
766
08f738be
ES		 767static void atmel_complete_tx_dma(void *arg)
768{
769 struct atmel_uart_port *atmel_port = arg;
770 struct uart_port *port = &atmel_port->uart;
771 struct circ_buf *xmit = &port->state->xmit;
772 struct dma_chan *chan = atmel_port->chan_tx;
773 unsigned long flags;
774
775 spin_lock_irqsave(&port->lock, flags);
776
777 if (chan)
778 dmaengine_terminate_all(chan);
5f258b3e 779 xmit->tail += atmel_port->tx_len;
08f738be
ES		 780 xmit->tail &= UART_XMIT_SIZE - 1;
781
5f258b3e 782 port->icount.tx += atmel_port->tx_len;
08f738be
ES		 783
784 spin_lock_irq(&atmel_port->lock_tx);
785 async_tx_ack(atmel_port->desc_tx);
786 atmel_port->cookie_tx = -EINVAL;
787 atmel_port->desc_tx = NULL;
788 spin_unlock_irq(&atmel_port->lock_tx);
789
790 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
791 uart_write_wakeup(port);
792
1842dc2e
CP		 793 /*
794 * xmit is a circular buffer so, if we have just send data from
795 * xmit->tail to the end of xmit->buf, now we have to transmit the
796 * remaining data from the beginning of xmit->buf to xmit->head.
797 */
08f738be 798 if (!uart_circ_empty(xmit))
98f2082c 799 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
08f738be
ES		 800
801 spin_unlock_irqrestore(&port->lock, flags);
802}
803
804static void atmel_release_tx_dma(struct uart_port *port)
805{
806 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
807 struct dma_chan *chan = atmel_port->chan_tx;
808
809 if (chan) {
810 dmaengine_terminate_all(chan);
811 dma_release_channel(chan);
812 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
48479148 813 DMA_TO_DEVICE);
08f738be
ES		 814 }
815
816 atmel_port->desc_tx = NULL;
817 atmel_port->chan_tx = NULL;
818 atmel_port->cookie_tx = -EINVAL;
819}
820
821/*
822 * Called from tasklet with TXRDY interrupt is disabled.
823 */
824static void atmel_tx_dma(struct uart_port *port)
825{
826 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
827 struct circ_buf *xmit = &port->state->xmit;
828 struct dma_chan *chan = atmel_port->chan_tx;
829 struct dma_async_tx_descriptor *desc;
5f258b3e
CP		 830 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
831 unsigned int tx_len, part1_len, part2_len, sg_len;
832 dma_addr_t phys_addr;
08f738be
ES		 833
834 /* Make sure we have an idle channel */
835 if (atmel_port->desc_tx != NULL)
836 return;
837
838 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
839 /*
840 * DMA is idle now.
841 * Port xmit buffer is already mapped,
842 * and it is one page... Just adjust
843 * offsets and lengths. Since it is a circular buffer,
844 * we have to transmit till the end, and then the rest.
845 * Take the port lock to get a
846 * consistent xmit buffer state.
847 */
5f258b3e
CP		 848 tx_len = CIRC_CNT_TO_END(xmit->head,
849 xmit->tail,
850 UART_XMIT_SIZE);
851
852 if (atmel_port->fifo_size) {
853 /* multi data mode */
854 part1_len = (tx_len & ~0x3); /* DWORD access */
855 part2_len = (tx_len & 0x3); /* BYTE access */
856 } else {
857 /* single data (legacy) mode */
858 part1_len = 0;
859 part2_len = tx_len; /* BYTE access only */
860 }
861
862 sg_init_table(sgl, 2);
863 sg_len = 0;
864 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
865 if (part1_len) {
866 sg = &sgl[sg_len++];
867 sg_dma_address(sg) = phys_addr;
868 sg_dma_len(sg) = part1_len;
869
870 phys_addr += part1_len;
871 }
872
873 if (part2_len) {
874 sg = &sgl[sg_len++];
875 sg_dma_address(sg) = phys_addr;
876 sg_dma_len(sg) = part2_len;
877 }
878
879 /*
880 * save tx_len so atmel_complete_tx_dma() will increase
881 * xmit->tail correctly
882 */
883 atmel_port->tx_len = tx_len;
08f738be
ES		 884
885 desc = dmaengine_prep_slave_sg(chan,
5f258b3e
CP		 886 sgl,
887 sg_len,
1842dc2e
CP		 888 DMA_MEM_TO_DEV,
889 DMA_PREP_INTERRUPT |
890 DMA_CTRL_ACK);
08f738be
ES		 891 if (!desc) {
892 dev_err(port->dev, "Failed to send via dma!\n");
893 return;
894 }
895
5f258b3e 896 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
08f738be
ES		 897
898 atmel_port->desc_tx = desc;
899 desc->callback = atmel_complete_tx_dma;
900 desc->callback_param = atmel_port;
901 atmel_port->cookie_tx = dmaengine_submit(desc);
902
903 } else {
13bd3e6f 904 if (port->rs485.flags & SER_RS485_ENABLED) {
08f738be
ES		 905 /* DMA done, stop TX, start RX for RS485 */
906 atmel_start_rx(port);
907 }
908 }
909
910 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
911 uart_write_wakeup(port);
912}
913
914static int atmel_prepare_tx_dma(struct uart_port *port)
915{
916 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
917 dma_cap_mask_t mask;
918 struct dma_slave_config config;
919 int ret, nent;
920
921 dma_cap_zero(mask);
922 dma_cap_set(DMA_SLAVE, mask);
923
924 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
925 if (atmel_port->chan_tx == NULL)
926 goto chan_err;
927 dev_info(port->dev, "using %s for tx DMA transfers\n",
928 dma_chan_name(atmel_port->chan_tx));
929
930 spin_lock_init(&atmel_port->lock_tx);
931 sg_init_table(&atmel_port->sg_tx, 1);
932 /* UART circular tx buffer is an aligned page. */
2c277054 933 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
08f738be
ES		 934 sg_set_page(&atmel_port->sg_tx,
935 virt_to_page(port->state->xmit.buf),
936 UART_XMIT_SIZE,
c8d1f022 937 (unsigned long)port->state->xmit.buf & ~PAGE_MASK);
08f738be
ES		 938 nent = dma_map_sg(port->dev,
939 &atmel_port->sg_tx,
940 1,
48479148 941 DMA_TO_DEVICE);
08f738be
ES		 942
943 if (!nent) {
944 dev_dbg(port->dev, "need to release resource of dma\n");
945 goto chan_err;
946 } else {
c8d1f022 947 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
08f738be
ES		 948 sg_dma_len(&atmel_port->sg_tx),
949 port->state->xmit.buf,
c8d1f022 950 &sg_dma_address(&atmel_port->sg_tx));
08f738be
ES		 951 }
952
953 /* Configure the slave DMA */
954 memset(&config, 0, sizeof(config));
955 config.direction = DMA_MEM_TO_DEV;
5f258b3e
CP		 956 config.dst_addr_width = (atmel_port->fifo_size) ?
957 DMA_SLAVE_BUSWIDTH_4_BYTES :
958 DMA_SLAVE_BUSWIDTH_1_BYTE;
08f738be 959 config.dst_addr = port->mapbase + ATMEL_US_THR;
a8d4e016 960 config.dst_maxburst = 1;
08f738be 961
5483c10e
MR		 962 ret = dmaengine_slave_config(atmel_port->chan_tx,
963 &config);
08f738be
ES		 964 if (ret) {
965 dev_err(port->dev, "DMA tx slave configuration failed\n");
966 goto chan_err;
967 }
968
969 return 0;
970
971chan_err:
972 dev_err(port->dev, "TX channel not available, switch to pio\n");
973 atmel_port->use_dma_tx = 0;
974 if (atmel_port->chan_tx)
975 atmel_release_tx_dma(port);
976 return -EINVAL;
977}
978
34df42f5
ES		 979static void atmel_complete_rx_dma(void *arg)
980{
981 struct uart_port *port = arg;
982 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
983
98f2082c 984 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
34df42f5
ES		 985}
986
987static void atmel_release_rx_dma(struct uart_port *port)
988{
989 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
990 struct dma_chan *chan = atmel_port->chan_rx;
991
992 if (chan) {
993 dmaengine_terminate_all(chan);
994 dma_release_channel(chan);
995 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
48479148 996 DMA_FROM_DEVICE);
34df42f5
ES		 997 }
998
999 atmel_port->desc_rx = NULL;
1000 atmel_port->chan_rx = NULL;
1001 atmel_port->cookie_rx = -EINVAL;
1002}
1003
1004static void atmel_rx_from_dma(struct uart_port *port)
1005{
1006 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
66f37aaf 1007 struct tty_port *tport = &port->state->port;
34df42f5
ES		 1008 struct circ_buf *ring = &atmel_port->rx_ring;
1009 struct dma_chan *chan = atmel_port->chan_rx;
1010 struct dma_tx_state state;
1011 enum dma_status dmastat;
66f37aaf 1012 size_t count;
34df42f5
ES		 1013
1014
1015 /* Reset the UART timeout early so that we don't miss one */
4e7decda 1016 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
34df42f5
ES		 1017 dmastat = dmaengine_tx_status(chan,
1018 atmel_port->cookie_rx,
1019 &state);
1020 /* Restart a new tasklet if DMA status is error */
1021 if (dmastat == DMA_ERROR) {
1022 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
4e7decda 1023 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
98f2082c 1024 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
34df42f5
ES		 1025 return;
1026 }
34df42f5 1027
66f37aaf
CP		 1028 /* CPU claims ownership of RX DMA buffer */
1029 dma_sync_sg_for_cpu(port->dev,
1030 &atmel_port->sg_rx,
1031 1,
485819b5 1032 DMA_FROM_DEVICE);
66f37aaf
CP		 1033
1034 /*
1035 * ring->head points to the end of data already written by the DMA.
1036 * ring->tail points to the beginning of data to be read by the
1037 * framework.
1038 * The current transfer size should not be larger than the dma buffer
1039 * length.
1040 */
1041 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1042 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
34df42f5 1043 /*
66f37aaf
CP		 1044 * At this point ring->head may point to the first byte right after the
1045 * last byte of the dma buffer:
1046 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1047 *
1048 * However ring->tail must always points inside the dma buffer:
1049 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1050 *
1051 * Since we use a ring buffer, we have to handle the case
1052 * where head is lower than tail. In such a case, we first read from
1053 * tail to the end of the buffer then reset tail.
34df42f5 1054 */
66f37aaf
CP		 1055 if (ring->head < ring->tail) {
1056 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
34df42f5 1057
66f37aaf
CP		 1058 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1059 ring->tail = 0;
1060 port->icount.rx += count;
1061 }
34df42f5 1062
66f37aaf
CP		 1063 /* Finally we read data from tail to head */
1064 if (ring->tail < ring->head) {
1065 count = ring->head - ring->tail;
34df42f5 1066
66f37aaf
CP		 1067 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1068 /* Wrap ring->head if needed */
1069 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1070 ring->head = 0;
1071 ring->tail = ring->head;
34df42f5
ES		 1072 port->icount.rx += count;
1073 }
1074
66f37aaf
CP		 1075 /* USART retreives ownership of RX DMA buffer */
1076 dma_sync_sg_for_device(port->dev,
1077 &atmel_port->sg_rx,
1078 1,
485819b5 1079 DMA_FROM_DEVICE);
66f37aaf
CP		 1080
1081 /*
1082 * Drop the lock here since it might end up calling
1083 * uart_start(), which takes the lock.
1084 */
1085 spin_unlock(&port->lock);
1086 tty_flip_buffer_push(tport);
1087 spin_lock(&port->lock);
1088
4e7decda 1089 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
34df42f5
ES		 1090}
1091
1092static int atmel_prepare_rx_dma(struct uart_port *port)
1093{
1094 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1095 struct dma_async_tx_descriptor *desc;
1096 dma_cap_mask_t mask;
1097 struct dma_slave_config config;
1098 struct circ_buf *ring;
1099 int ret, nent;
1100
1101 ring = &atmel_port->rx_ring;
1102
1103 dma_cap_zero(mask);
1104 dma_cap_set(DMA_CYCLIC, mask);
1105
1106 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1107 if (atmel_port->chan_rx == NULL)
1108 goto chan_err;
1109 dev_info(port->dev, "using %s for rx DMA transfers\n",
1110 dma_chan_name(atmel_port->chan_rx));
1111
1112 spin_lock_init(&atmel_port->lock_rx);
1113 sg_init_table(&atmel_port->sg_rx, 1);
1114 /* UART circular rx buffer is an aligned page. */
2c277054 1115 BUG_ON(!PAGE_ALIGNED(ring->buf));
34df42f5 1116 sg_set_page(&atmel_port->sg_rx,
1842dc2e 1117 virt_to_page(ring->buf),
a510880f 1118 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
c8d1f022 1119 (unsigned long)ring->buf & ~PAGE_MASK);
1842dc2e
CP		 1120 nent = dma_map_sg(port->dev,
1121 &atmel_port->sg_rx,
1122 1,
1123 DMA_FROM_DEVICE);
34df42f5
ES		 1124
1125 if (!nent) {
1126 dev_dbg(port->dev, "need to release resource of dma\n");
1127 goto chan_err;
1128 } else {
c8d1f022 1129 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
34df42f5
ES		 1130 sg_dma_len(&atmel_port->sg_rx),
1131 ring->buf,
c8d1f022 1132 &sg_dma_address(&atmel_port->sg_rx));
34df42f5
ES		 1133 }
1134
1135 /* Configure the slave DMA */
1136 memset(&config, 0, sizeof(config));
1137 config.direction = DMA_DEV_TO_MEM;
1138 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1139 config.src_addr = port->mapbase + ATMEL_US_RHR;
a8d4e016 1140 config.src_maxburst = 1;
34df42f5 1141
5483c10e
MR		 1142 ret = dmaengine_slave_config(atmel_port->chan_rx,
1143 &config);
34df42f5
ES		 1144 if (ret) {
1145 dev_err(port->dev, "DMA rx slave configuration failed\n");
1146 goto chan_err;
1147 }
1148 /*
1149 * Prepare a cyclic dma transfer, assign 2 descriptors,
1150 * each one is half ring buffer size
1151 */
1152 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1842dc2e
CP		 1153 sg_dma_address(&atmel_port->sg_rx),
1154 sg_dma_len(&atmel_port->sg_rx),
1155 sg_dma_len(&atmel_port->sg_rx)/2,
1156 DMA_DEV_TO_MEM,
1157 DMA_PREP_INTERRUPT);
34df42f5
ES		 1158 desc->callback = atmel_complete_rx_dma;
1159 desc->callback_param = port;
1160 atmel_port->desc_rx = desc;
1161 atmel_port->cookie_rx = dmaengine_submit(desc);
1162
1163 return 0;
1164
1165chan_err:
1166 dev_err(port->dev, "RX channel not available, switch to pio\n");
1167 atmel_port->use_dma_rx = 0;
1168 if (atmel_port->chan_rx)
1169 atmel_release_rx_dma(port);
1170 return -EINVAL;
1171}
1172
2e68c22f
ES		 1173static void atmel_uart_timer_callback(unsigned long data)
1174{
1175 struct uart_port *port = (void *)data;
1176 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1177
98f2082c
NF		 1178 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1179 tasklet_schedule(&atmel_port->tasklet_rx);
1180 mod_timer(&atmel_port->uart_timer,
1181 jiffies + uart_poll_timeout(port));
1182 }
2e68c22f
ES		 1183}
1184
b843aa21
RB		 1185/*
1186 * receive interrupt handler.
1187 */
1188static void
1189atmel_handle_receive(struct uart_port *port, unsigned int pending)
1190{
c811ab8c 1191 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
b843aa21 1192
64e22ebe 1193 if (atmel_use_pdc_rx(port)) {
a6670615
CC		 1194 /*
1195 * PDC receive. Just schedule the tasklet and let it
1196 * figure out the details.
1197 *
1198 * TODO: We're not handling error flags correctly at
1199 * the moment.
1200 */
1201 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
4e7decda
CP		 1202 atmel_uart_writel(port, ATMEL_US_IDR,
1203 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
98f2082c
NF		 1204 atmel_tasklet_schedule(atmel_port,
1205 &atmel_port->tasklet_rx);
a6670615
CC		 1206 }
1207
1208 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1209 ATMEL_US_FRAME | ATMEL_US_PARE))
1210 atmel_pdc_rxerr(port, pending);
1211 }
1212
34df42f5
ES		 1213 if (atmel_use_dma_rx(port)) {
1214 if (pending & ATMEL_US_TIMEOUT) {
4e7decda
CP		 1215 atmel_uart_writel(port, ATMEL_US_IDR,
1216 ATMEL_US_TIMEOUT);
98f2082c
NF		 1217 atmel_tasklet_schedule(atmel_port,
1218 &atmel_port->tasklet_rx);
34df42f5
ES		 1219 }
1220 }
1221
b843aa21
RB		 1222 /* Interrupt receive */
1223 if (pending & ATMEL_US_RXRDY)
1224 atmel_rx_chars(port);
1225 else if (pending & ATMEL_US_RXBRK) {
1226 /*
1227 * End of break detected. If it came along with a
1228 * character, atmel_rx_chars will handle it.
1229 */
4e7decda
CP		 1230 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1231 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
b843aa21
RB		 1232 atmel_port->break_active = 0;
1233 }
1234}
1235
1236/*
1ecc26bd 1237 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
b843aa21
RB		 1238 */
1239static void
1240atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1241{
c811ab8c 1242 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd 1243
e8faff73
CS		 1244 if (pending & atmel_port->tx_done_mask) {
1245 /* Either PDC or interrupt transmission */
4e7decda
CP		 1246 atmel_uart_writel(port, ATMEL_US_IDR,
1247 atmel_port->tx_done_mask);
98f2082c 1248 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1ecc26bd 1249 }
b843aa21
RB		 1250}
1251
1252/*
1253 * status flags interrupt handler.
1254 */
1255static void
1256atmel_handle_status(struct uart_port *port, unsigned int pending,
1257 unsigned int status)
1258{
c811ab8c 1259 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
9205218e 1260 unsigned int status_change;
1ecc26bd 1261
b843aa21 1262 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1ecc26bd 1263 | ATMEL_US_CTSIC)) {
9205218e 1264 status_change = status ^ atmel_port->irq_status_prev;
d033e82d 1265 atmel_port->irq_status_prev = status;
9205218e
NF		 1266
1267 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1268 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1269 /* TODO: All reads to CSR will clear these interrupts! */
1270 if (status_change & ATMEL_US_RI)
1271 port->icount.rng++;
1272 if (status_change & ATMEL_US_DSR)
1273 port->icount.dsr++;
1274 if (status_change & ATMEL_US_DCD)
1275 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1276 if (status_change & ATMEL_US_CTS)
1277 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1278
1279 wake_up_interruptible(&port->state->port.delta_msr_wait);
1280 }
1ecc26bd 1281 }
b843aa21
RB		 1282}
1283
1e6c9c28
AV		 1284/*
1285 * Interrupt handler
1286 */
7d12e780 1287static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1e6c9c28
AV		 1288{
1289 struct uart_port *port = dev_id;
ab5e4e41 1290 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba 1291 unsigned int status, pending, mask, pass_counter = 0;
1e6c9c28 1292
2c7af5ba
BB		 1293 spin_lock(&atmel_port->lock_suspended);
1294
a6670615 1295 do {
e0b0baad 1296 status = atmel_get_lines_status(port);
4e7decda 1297 mask = atmel_uart_readl(port, ATMEL_US_IMR);
2c7af5ba 1298 pending = status & mask;
a6670615
CC		 1299 if (!pending)
1300 break;
1301
2c7af5ba
BB		 1302 if (atmel_port->suspended) {
1303 atmel_port->pending |= pending;
1304 atmel_port->pending_status = status;
4e7decda 1305 atmel_uart_writel(port, ATMEL_US_IDR, mask);
2c7af5ba
BB		 1306 pm_system_wakeup();
1307 break;
1308 }
1309
b843aa21
RB		 1310 atmel_handle_receive(port, pending);
1311 atmel_handle_status(port, pending, status);
1312 atmel_handle_transmit(port, pending);
a6670615 1313 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
afefc415 1314
2c7af5ba
BB		 1315 spin_unlock(&atmel_port->lock_suspended);
1316
0400b697 1317 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
a6670615 1318}
1e6c9c28 1319
a930e528
ES		 1320static void atmel_release_tx_pdc(struct uart_port *port)
1321{
1322 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1323 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1324
1325 dma_unmap_single(port->dev,
1326 pdc->dma_addr,
1327 pdc->dma_size,
1328 DMA_TO_DEVICE);
1329}
1330
a6670615
CC		 1331/*
1332 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1333 */
64e22ebe 1334static void atmel_tx_pdc(struct uart_port *port)
a6670615 1335{
c811ab8c 1336 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1337 struct circ_buf *xmit = &port->state->xmit;
a6670615
CC		 1338 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1339 int count;
1340
ba0657ff 1341 /* nothing left to transmit? */
4e7decda 1342 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
ba0657ff
MT		 1343 return;
1344
a6670615
CC		 1345 xmit->tail += pdc->ofs;
1346 xmit->tail &= UART_XMIT_SIZE - 1;
1347
1348 port->icount.tx += pdc->ofs;
1349 pdc->ofs = 0;
1350
ba0657ff 1351 /* more to transmit - setup next transfer */
a6670615 1352
ba0657ff 1353 /* disable PDC transmit */
4e7decda 1354 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
ba0657ff 1355
1f14081d 1356 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
a6670615
CC		 1357 dma_sync_single_for_device(port->dev,
1358 pdc->dma_addr,
1359 pdc->dma_size,
1360 DMA_TO_DEVICE);
1361
1362 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1363 pdc->ofs = count;
1364
4e7decda
CP		 1365 atmel_uart_writel(port, ATMEL_PDC_TPR,
1366 pdc->dma_addr + xmit->tail);
1367 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
e8faff73 1368 /* re-enable PDC transmit */
4e7decda 1369 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
e8faff73 1370 /* Enable interrupts */
4e7decda
CP		 1371 atmel_uart_writel(port, ATMEL_US_IER,
1372 atmel_port->tx_done_mask);
e8faff73 1373 } else {
13bd3e6f
RRD		 1374 if ((port->rs485.flags & SER_RS485_ENABLED) &&
1375 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) {
e8faff73
CS		 1376 /* DMA done, stop TX, start RX for RS485 */
1377 atmel_start_rx(port);
1378 }
1e6c9c28 1379 }
a6670615
CC		 1380
1381 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1382 uart_write_wakeup(port);
1e6c9c28
AV		 1383}
1384
a930e528
ES		 1385static int atmel_prepare_tx_pdc(struct uart_port *port)
1386{
1387 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1388 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1389 struct circ_buf *xmit = &port->state->xmit;
1390
1391 pdc->buf = xmit->buf;
1392 pdc->dma_addr = dma_map_single(port->dev,
1393 pdc->buf,
1394 UART_XMIT_SIZE,
1395 DMA_TO_DEVICE);
1396 pdc->dma_size = UART_XMIT_SIZE;
1397 pdc->ofs = 0;
1398
1399 return 0;
1400}
1401
1ecc26bd
RB		 1402static void atmel_rx_from_ring(struct uart_port *port)
1403{
c811ab8c 1404 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1405 struct circ_buf *ring = &atmel_port->rx_ring;
1406 unsigned int flg;
1407 unsigned int status;
1408
1409 while (ring->head != ring->tail) {
1410 struct atmel_uart_char c;
1411
1412 /* Make sure c is loaded after head. */
1413 smp_rmb();
1414
1415 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1416
1417 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1418
1419 port->icount.rx++;
1420 status = c.status;
1421 flg = TTY_NORMAL;
1422
1423 /*
1424 * note that the error handling code is
1425 * out of the main execution path
1426 */
1427 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1428 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1429 if (status & ATMEL_US_RXBRK) {
1430 /* ignore side-effect */
1431 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1432
1433 port->icount.brk++;
1434 if (uart_handle_break(port))
1435 continue;
1436 }
1437 if (status & ATMEL_US_PARE)
1438 port->icount.parity++;
1439 if (status & ATMEL_US_FRAME)
1440 port->icount.frame++;
1441 if (status & ATMEL_US_OVRE)
1442 port->icount.overrun++;
1443
1444 status &= port->read_status_mask;
1445
1446 if (status & ATMEL_US_RXBRK)
1447 flg = TTY_BREAK;
1448 else if (status & ATMEL_US_PARE)
1449 flg = TTY_PARITY;
1450 else if (status & ATMEL_US_FRAME)
1451 flg = TTY_FRAME;
1452 }
1453
1454
1455 if (uart_handle_sysrq_char(port, c.ch))
1456 continue;
1457
1458 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1459 }
1460
1461 /*
1462 * Drop the lock here since it might end up calling
1463 * uart_start(), which takes the lock.
1464 */
1465 spin_unlock(&port->lock);
2e124b4a 1466 tty_flip_buffer_push(&port->state->port);
1ecc26bd
RB		 1467 spin_lock(&port->lock);
1468}
1469
a930e528
ES		 1470static void atmel_release_rx_pdc(struct uart_port *port)
1471{
1472 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1473 int i;
1474
1475 for (i = 0; i < 2; i++) {
1476 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1477
1478 dma_unmap_single(port->dev,
1479 pdc->dma_addr,
1480 pdc->dma_size,
1481 DMA_FROM_DEVICE);
1482 kfree(pdc->buf);
1483 }
1484}
1485
64e22ebe 1486static void atmel_rx_from_pdc(struct uart_port *port)
a6670615 1487{
c811ab8c 1488 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
05c7cd39 1489 struct tty_port *tport = &port->state->port;
a6670615
CC		 1490 struct atmel_dma_buffer *pdc;
1491 int rx_idx = atmel_port->pdc_rx_idx;
1492 unsigned int head;
1493 unsigned int tail;
1494 unsigned int count;
1495
1496 do {
1497 /* Reset the UART timeout early so that we don't miss one */
4e7decda 1498 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
a6670615
CC		 1499
1500 pdc = &atmel_port->pdc_rx[rx_idx];
4e7decda 1501 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
a6670615
CC		 1502 tail = pdc->ofs;
1503
1504 /* If the PDC has switched buffers, RPR won't contain
1505 * any address within the current buffer. Since head
1506 * is unsigned, we just need a one-way comparison to
1507 * find out.
1508 *
1509 * In this case, we just need to consume the entire
1510 * buffer and resubmit it for DMA. This will clear the
1511 * ENDRX bit as well, so that we can safely re-enable
1512 * all interrupts below.
1513 */
1514 head = min(head, pdc->dma_size);
1515
1516 if (likely(head != tail)) {
1517 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1518 pdc->dma_size, DMA_FROM_DEVICE);
1519
1520 /*
1521 * head will only wrap around when we recycle
1522 * the DMA buffer, and when that happens, we
1523 * explicitly set tail to 0. So head will
1524 * always be greater than tail.
1525 */
1526 count = head - tail;
1527
05c7cd39
JS		 1528 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1529 count);
a6670615
CC		 1530
1531 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1532 pdc->dma_size, DMA_FROM_DEVICE);
1533
1534 port->icount.rx += count;
1535 pdc->ofs = head;
1536 }
1537
1538 /*
1539 * If the current buffer is full, we need to check if
1540 * the next one contains any additional data.
1541 */
1542 if (head >= pdc->dma_size) {
1543 pdc->ofs = 0;
4e7decda
CP		 1544 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1545 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
a6670615
CC		 1546
1547 rx_idx = !rx_idx;
1548 atmel_port->pdc_rx_idx = rx_idx;
1549 }
1550 } while (head >= pdc->dma_size);
1551
1552 /*
1553 * Drop the lock here since it might end up calling
1554 * uart_start(), which takes the lock.
1555 */
1556 spin_unlock(&port->lock);
2e124b4a 1557 tty_flip_buffer_push(tport);
a6670615
CC		 1558 spin_lock(&port->lock);
1559
4e7decda
CP		 1560 atmel_uart_writel(port, ATMEL_US_IER,
1561 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
a6670615
CC		 1562}
1563
a930e528
ES		 1564static int atmel_prepare_rx_pdc(struct uart_port *port)
1565{
1566 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1567 int i;
1568
1569 for (i = 0; i < 2; i++) {
1570 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1571
1572 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1573 if (pdc->buf == NULL) {
1574 if (i != 0) {
1575 dma_unmap_single(port->dev,
1576 atmel_port->pdc_rx[0].dma_addr,
1577 PDC_BUFFER_SIZE,
1578 DMA_FROM_DEVICE);
1579 kfree(atmel_port->pdc_rx[0].buf);
1580 }
1581 atmel_port->use_pdc_rx = 0;
1582 return -ENOMEM;
1583 }
1584 pdc->dma_addr = dma_map_single(port->dev,
1585 pdc->buf,
1586 PDC_BUFFER_SIZE,
1587 DMA_FROM_DEVICE);
1588 pdc->dma_size = PDC_BUFFER_SIZE;
1589 pdc->ofs = 0;
1590 }
1591
1592 atmel_port->pdc_rx_idx = 0;
1593
4e7decda
CP		 1594 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1595 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
a930e528 1596
4e7decda
CP		 1597 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1598 atmel_port->pdc_rx[1].dma_addr);
1599 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
a930e528
ES		 1600
1601 return 0;
1602}
1603
1ecc26bd
RB		 1604/*
1605 * tasklet handling tty stuff outside the interrupt handler.
1606 */
00e8e658 1607static void atmel_tasklet_rx_func(unsigned long data)
1ecc26bd
RB		 1608{
1609 struct uart_port *port = (struct uart_port *)data;
c811ab8c 1610 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1ecc26bd
RB		 1611
1612 /* The interrupt handler does not take the lock */
1613 spin_lock(&port->lock);
a930e528 1614 atmel_port->schedule_rx(port);
00e8e658
NF		 1615 spin_unlock(&port->lock);
1616}
1ecc26bd 1617
00e8e658
NF		 1618static void atmel_tasklet_tx_func(unsigned long data)
1619{
1620 struct uart_port *port = (struct uart_port *)data;
1621 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1622
1623 /* The interrupt handler does not take the lock */
1624 spin_lock(&port->lock);
1625 atmel_port->schedule_tx(port);
1ecc26bd
RB		 1626 spin_unlock(&port->lock);
1627}
1628
4a1e8888 1629static void atmel_init_property(struct atmel_uart_port *atmel_port,
33d64c4f
ES		 1630 struct platform_device *pdev)
1631{
1632 struct device_node *np = pdev->dev.of_node;
574de559 1633 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
33d64c4f
ES		 1634
1635 if (np) {
1636 /* DMA/PDC usage specification */
1637 if (of_get_property(np, "atmel,use-dma-rx", NULL)) {
1638 if (of_get_property(np, "dmas", NULL)) {
1639 atmel_port->use_dma_rx = true;
1640 atmel_port->use_pdc_rx = false;
1641 } else {
1642 atmel_port->use_dma_rx = false;
1643 atmel_port->use_pdc_rx = true;
1644 }
1645 } else {
1646 atmel_port->use_dma_rx = false;
1647 atmel_port->use_pdc_rx = false;
1648 }
1649
1650 if (of_get_property(np, "atmel,use-dma-tx", NULL)) {
1651 if (of_get_property(np, "dmas", NULL)) {
1652 atmel_port->use_dma_tx = true;
1653 atmel_port->use_pdc_tx = false;
1654 } else {
1655 atmel_port->use_dma_tx = false;
1656 atmel_port->use_pdc_tx = true;
1657 }
1658 } else {
1659 atmel_port->use_dma_tx = false;
1660 atmel_port->use_pdc_tx = false;
1661 }
1662
1663 } else {
1664 atmel_port->use_pdc_rx = pdata->use_dma_rx;
1665 atmel_port->use_pdc_tx = pdata->use_dma_tx;
1666 atmel_port->use_dma_rx = false;
1667 atmel_port->use_dma_tx = false;
1668 }
1669
33d64c4f
ES		 1670}
1671
13bd3e6f 1672static void atmel_init_rs485(struct uart_port *port,
33d64c4f
ES		 1673 struct platform_device *pdev)
1674{
1675 struct device_node *np = pdev->dev.of_node;
574de559 1676 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
33d64c4f
ES		 1677
1678 if (np) {
77bdec6f 1679 struct serial_rs485 *rs485conf = &port->rs485;
33d64c4f
ES		 1680 u32 rs485_delay[2];
1681 /* rs485 properties */
1682 if (of_property_read_u32_array(np, "rs485-rts-delay",
1683 rs485_delay, 2) == 0) {
33d64c4f
ES		 1684 rs485conf->delay_rts_before_send = rs485_delay[0];
1685 rs485conf->delay_rts_after_send = rs485_delay[1];
1686 rs485conf->flags = 0;
77bdec6f 1687 }
33d64c4f
ES		 1688
1689 if (of_get_property(np, "rs485-rx-during-tx", NULL))
1690 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1691
1692 if (of_get_property(np, "linux,rs485-enabled-at-boot-time",
1693 NULL))
1694 rs485conf->flags |= SER_RS485_ENABLED;
33d64c4f 1695 } else {
13bd3e6f 1696 port->rs485 = pdata->rs485;
33d64c4f
ES		 1697 }
1698
1699}
1700
a930e528
ES		 1701static void atmel_set_ops(struct uart_port *port)
1702{
1703 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1704
34df42f5
ES		 1705 if (atmel_use_dma_rx(port)) {
1706 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1707 atmel_port->schedule_rx = &atmel_rx_from_dma;
1708 atmel_port->release_rx = &atmel_release_rx_dma;
1709 } else if (atmel_use_pdc_rx(port)) {
a930e528
ES		 1710 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1711 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1712 atmel_port->release_rx = &atmel_release_rx_pdc;
1713 } else {
1714 atmel_port->prepare_rx = NULL;
1715 atmel_port->schedule_rx = &atmel_rx_from_ring;
1716 atmel_port->release_rx = NULL;
1717 }
1718
08f738be
ES		 1719 if (atmel_use_dma_tx(port)) {
1720 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1721 atmel_port->schedule_tx = &atmel_tx_dma;
1722 atmel_port->release_tx = &atmel_release_tx_dma;
1723 } else if (atmel_use_pdc_tx(port)) {
a930e528
ES		 1724 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1725 atmel_port->schedule_tx = &atmel_tx_pdc;
1726 atmel_port->release_tx = &atmel_release_tx_pdc;
1727 } else {
1728 atmel_port->prepare_tx = NULL;
1729 atmel_port->schedule_tx = &atmel_tx_chars;
1730 atmel_port->release_tx = NULL;
1731 }
1732}
1733
055560b0
ES		 1734/*
1735 * Get ip name usart or uart
1736 */
892db58b 1737static void atmel_get_ip_name(struct uart_port *port)
055560b0
ES		 1738{
1739 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
4e7decda 1740 int name = atmel_uart_readl(port, ATMEL_US_NAME);
731d9cae 1741 u32 version;
1d673fb9 1742 u32 usart, dbgu_uart, new_uart;
4b769371
NF		 1743 /* ASCII decoding for IP version */
1744 usart = 0x55534152; /* USAR(T) */
1745 dbgu_uart = 0x44424755; /* DBGU */
1d673fb9 1746 new_uart = 0x55415254; /* UART */
055560b0 1747
4b769371 1748 atmel_port->has_hw_timer = false;
055560b0 1749
2958ccee
LD		 1750 if (name == new_uart) {
1751 dev_dbg(port->dev, "Uart with hw timer");
4b769371 1752 atmel_port->has_hw_timer = true;
2958ccee
LD		 1753 atmel_port->rtor = ATMEL_UA_RTOR;
1754 } else if (name == usart) {
1755 dev_dbg(port->dev, "Usart\n");
1756 atmel_port->has_hw_timer = true;
1757 atmel_port->rtor = ATMEL_US_RTOR;
4b769371
NF		 1758 } else if (name == dbgu_uart) {
1759 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
055560b0 1760 } else {
731d9cae 1761 /* fallback for older SoCs: use version field */
4e7decda 1762 version = atmel_uart_readl(port, ATMEL_US_VERSION);
731d9cae
NF		 1763 switch (version) {
1764 case 0x302:
1765 case 0x10213:
1766 dev_dbg(port->dev, "This version is usart\n");
4b769371 1767 atmel_port->has_hw_timer = true;
2958ccee 1768 atmel_port->rtor = ATMEL_US_RTOR;
731d9cae
NF		 1769 break;
1770 case 0x203:
1771 case 0x10202:
1772 dev_dbg(port->dev, "This version is uart\n");
731d9cae
NF		 1773 break;
1774 default:
1775 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1776 }
055560b0 1777 }
055560b0
ES		 1778}
1779
1e6c9c28
AV		 1780/*
1781 * Perform initialization and enable port for reception
1782 */
7192f92c 1783static int atmel_startup(struct uart_port *port)
1e6c9c28 1784{
33d64c4f 1785 struct platform_device *pdev = to_platform_device(port->dev);
c811ab8c 1786 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
ebd2c8f6 1787 struct tty_struct *tty = port->state->port.tty;
1e6c9c28
AV		 1788 int retval;
1789
1790 /*
1791 * Ensure that no interrupts are enabled otherwise when
1792 * request_irq() is called we could get stuck trying to
1793 * handle an unexpected interrupt
1794 */
4e7decda 1795 atmel_uart_writel(port, ATMEL_US_IDR, -1);
ab5e4e41 1796 atmel_port->ms_irq_enabled = false;
1e6c9c28
AV		 1797
1798 /*
1799 * Allocate the IRQ
1800 */
2c7af5ba
BB		 1801 retval = request_irq(port->irq, atmel_interrupt,
1802 IRQF_SHARED | IRQF_COND_SUSPEND,
ae161068 1803 tty ? tty->name : "atmel_serial", port);
1e6c9c28 1804 if (retval) {
ddaa6037 1805 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1e6c9c28
AV		 1806 return retval;
1807 }
1808
98f2082c
NF		 1809 atomic_set(&atmel_port->tasklet_shutdown, 0);
1810 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1811 (unsigned long)port);
1812 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1813 (unsigned long)port);
1e125786 1814
a6670615
CC		 1815 /*
1816 * Initialize DMA (if necessary)
1817 */
33d64c4f 1818 atmel_init_property(atmel_port, pdev);
4d9628a1 1819 atmel_set_ops(port);
33d64c4f 1820
a930e528
ES		 1821 if (atmel_port->prepare_rx) {
1822 retval = atmel_port->prepare_rx(port);
1823 if (retval < 0)
1824 atmel_set_ops(port);
a6670615 1825 }
a6670615 1826
a930e528
ES		 1827 if (atmel_port->prepare_tx) {
1828 retval = atmel_port->prepare_tx(port);
1829 if (retval < 0)
1830 atmel_set_ops(port);
a6670615 1831 }
1e6c9c28 1832
b5199d46
CP		 1833 /*
1834 * Enable FIFO when available
1835 */
1836 if (atmel_port->fifo_size) {
1837 unsigned int txrdym = ATMEL_US_ONE_DATA;
1838 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1839 unsigned int fmr;
1840
1841 atmel_uart_writel(port, ATMEL_US_CR,
1842 ATMEL_US_FIFOEN |
1843 ATMEL_US_RXFCLR |
1844 ATMEL_US_TXFLCLR);
1845
5f258b3e
CP		 1846 if (atmel_use_dma_tx(port))
1847 txrdym = ATMEL_US_FOUR_DATA;
1848
b5199d46
CP		 1849 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1850 if (atmel_port->rts_high &&
1851 atmel_port->rts_low)
1852 fmr |= ATMEL_US_FRTSC |
1853 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1854 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1855
1856 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1857 }
1858
27c0c8e5 1859 /* Save current CSR for comparison in atmel_tasklet_func() */
e0b0baad 1860 atmel_port->irq_status_prev = atmel_get_lines_status(port);
27c0c8e5 1861
1e6c9c28
AV		 1862 /*
1863 * Finally, enable the serial port
1864 */
4e7decda 1865 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
b843aa21 1866 /* enable xmit & rcvr */
4e7decda 1867 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
afefc415 1868
8bc661bf
MR		 1869 setup_timer(&atmel_port->uart_timer,
1870 atmel_uart_timer_callback,
1871 (unsigned long)port);
1872
64e22ebe 1873 if (atmel_use_pdc_rx(port)) {
a6670615 1874 /* set UART timeout */
4b769371 1875 if (!atmel_port->has_hw_timer) {
2e68c22f
ES		 1876 mod_timer(&atmel_port->uart_timer,
1877 jiffies + uart_poll_timeout(port));
1878 /* set USART timeout */
1879 } else {
2958ccee
LD		 1880 atmel_uart_writel(port, atmel_port->rtor,
1881 PDC_RX_TIMEOUT);
4e7decda 1882 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
a6670615 1883
4e7decda
CP		 1884 atmel_uart_writel(port, ATMEL_US_IER,
1885 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
2e68c22f 1886 }
a6670615 1887 /* enable PDC controller */
4e7decda 1888 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
34df42f5 1889 } else if (atmel_use_dma_rx(port)) {
2e68c22f 1890 /* set UART timeout */
4b769371 1891 if (!atmel_port->has_hw_timer) {
2e68c22f
ES		 1892 mod_timer(&atmel_port->uart_timer,
1893 jiffies + uart_poll_timeout(port));
1894 /* set USART timeout */
1895 } else {
2958ccee
LD		 1896 atmel_uart_writel(port, atmel_port->rtor,
1897 PDC_RX_TIMEOUT);
4e7decda 1898 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
34df42f5 1899
4e7decda
CP		 1900 atmel_uart_writel(port, ATMEL_US_IER,
1901 ATMEL_US_TIMEOUT);
2e68c22f 1902 }
a6670615
CC		 1903 } else {
1904 /* enable receive only */
4e7decda 1905 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
a6670615 1906 }
afefc415 1907
1e6c9c28
AV		 1908 return 0;
1909}
1910
479e9b94
PH		 1911/*
1912 * Flush any TX data submitted for DMA. Called when the TX circular
1913 * buffer is reset.
1914 */
1915static void atmel_flush_buffer(struct uart_port *port)
1916{
1917 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1918
1919 if (atmel_use_pdc_tx(port)) {
4e7decda 1920 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
479e9b94
PH		 1921 atmel_port->pdc_tx.ofs = 0;
1922 }
1923}
1924
1e6c9c28
AV		 1925/*
1926 * Disable the port
1927 */
7192f92c 1928static void atmel_shutdown(struct uart_port *port)
1e6c9c28 1929{
c811ab8c 1930 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
0cc7c6c7 1931
98f2082c
NF		 1932 /* Disable interrupts at device level */
1933 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1934
1935 /* Prevent spurious interrupts from scheduling the tasklet */
1936 atomic_inc(&atmel_port->tasklet_shutdown);
1937
8bc661bf
MR		 1938 /*
1939 * Prevent any tasklets being scheduled during
1940 * cleanup
1941 */
1942 del_timer_sync(&atmel_port->uart_timer);
1943
98f2082c
NF		 1944 /* Make sure that no interrupt is on the fly */
1945 synchronize_irq(port->irq);
1946
0cc7c6c7
MR		 1947 /*
1948 * Clear out any scheduled tasklets before
1949 * we destroy the buffers
1950 */
00e8e658
NF		 1951 tasklet_kill(&atmel_port->tasklet_rx);
1952 tasklet_kill(&atmel_port->tasklet_tx);
0cc7c6c7 1953
a6670615 1954 /*
0cc7c6c7 1955 * Ensure everything is stopped and
98f2082c 1956 * disable port and break condition.
a6670615
CC		 1957 */
1958 atmel_stop_rx(port);
1959 atmel_stop_tx(port);
1960
4e7decda 1961 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
0cc7c6c7 1962
a6670615
CC		 1963 /*
1964 * Shut-down the DMA.
1965 */
a930e528
ES		 1966 if (atmel_port->release_rx)
1967 atmel_port->release_rx(port);
1968 if (atmel_port->release_tx)
1969 atmel_port->release_tx(port);
a6670615 1970
bb7e73c5
MD		 1971 /*
1972 * Reset ring buffer pointers
1973 */
1974 atmel_port->rx_ring.head = 0;
1975 atmel_port->rx_ring.tail = 0;
1976
1e6c9c28 1977 /*
ab5e4e41 1978 * Free the interrupts
1e6c9c28
AV		 1979 */
1980 free_irq(port->irq, port);
ab5e4e41
RG		 1981
1982 atmel_port->ms_irq_enabled = false;
1e6c9c28 1983
479e9b94 1984 atmel_flush_buffer(port);
9afd561a
HS		 1985}
1986
1e6c9c28
AV		 1987/*
1988 * Power / Clock management.
1989 */
b843aa21
RB		 1990static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1991 unsigned int oldstate)
1e6c9c28 1992{
c811ab8c 1993 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 1994
1e6c9c28 1995 switch (state) {
b843aa21
RB		 1996 case 0:
1997 /*
1998 * Enable the peripheral clock for this serial port.
1999 * This is called on uart_open() or a resume event.
2000 */
91f8c2d8 2001 clk_prepare_enable(atmel_port->clk);
f05596db
AS		 2002
2003 /* re-enable interrupts if we disabled some on suspend */
4e7decda 2004 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
b843aa21
RB		 2005 break;
2006 case 3:
f05596db 2007 /* Back up the interrupt mask and disable all interrupts */
4e7decda
CP		 2008 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2009 atmel_uart_writel(port, ATMEL_US_IDR, -1);
f05596db 2010
b843aa21
RB		 2011 /*
2012 * Disable the peripheral clock for this serial port.
2013 * This is called on uart_close() or a suspend event.
2014 */
91f8c2d8 2015 clk_disable_unprepare(atmel_port->clk);
b843aa21
RB		 2016 break;
2017 default:
ddaa6037 2018 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
1e6c9c28
AV		 2019 }
2020}
2021
2022/*
2023 * Change the port parameters
2024 */
b843aa21
RB		 2025static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2026 struct ktermios *old)
1e6c9c28
AV		 2027{
2028 unsigned long flags;
1cf6e8fc
CP		 2029 unsigned int old_mode, mode, imr, quot, baud;
2030
2031 /* save the current mode register */
4e7decda 2032 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
1e6c9c28 2033
1cf6e8fc
CP		 2034 /* reset the mode, clock divisor, parity, stop bits and data size */
2035 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2036 ATMEL_US_PAR | ATMEL_US_USMODE);
03abeac0 2037
b843aa21 2038 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1e6c9c28
AV		 2039 quot = uart_get_divisor(port, baud);
2040
b843aa21 2041 if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */
03abeac0
AV		 2042 quot /= 8;
2043 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2044 }
1e6c9c28
AV		 2045
2046 /* byte size */
2047 switch (termios->c_cflag & CSIZE) {
2048 case CS5:
7192f92c 2049 mode |= ATMEL_US_CHRL_5;
1e6c9c28
AV		 2050 break;
2051 case CS6:
7192f92c 2052 mode |= ATMEL_US_CHRL_6;
1e6c9c28
AV		 2053 break;
2054 case CS7:
7192f92c 2055 mode |= ATMEL_US_CHRL_7;
1e6c9c28
AV		 2056 break;
2057 default:
7192f92c 2058 mode |= ATMEL_US_CHRL_8;
1e6c9c28
AV		 2059 break;
2060 }
2061
2062 /* stop bits */
2063 if (termios->c_cflag & CSTOPB)
7192f92c 2064 mode |= ATMEL_US_NBSTOP_2;
1e6c9c28
AV		 2065
2066 /* parity */
2067 if (termios->c_cflag & PARENB) {
b843aa21
RB		 2068 /* Mark or Space parity */
2069 if (termios->c_cflag & CMSPAR) {
1e6c9c28 2070 if (termios->c_cflag & PARODD)
7192f92c 2071 mode |= ATMEL_US_PAR_MARK;
1e6c9c28 2072 else
7192f92c 2073 mode |= ATMEL_US_PAR_SPACE;
b843aa21 2074 } else if (termios->c_cflag & PARODD)
7192f92c 2075 mode |= ATMEL_US_PAR_ODD;
1e6c9c28 2076 else
7192f92c 2077 mode |= ATMEL_US_PAR_EVEN;
b843aa21 2078 } else
7192f92c 2079 mode |= ATMEL_US_PAR_NONE;
1e6c9c28
AV		 2080
2081 spin_lock_irqsave(&port->lock, flags);
2082
7192f92c 2083 port->read_status_mask = ATMEL_US_OVRE;
1e6c9c28 2084 if (termios->c_iflag & INPCK)
7192f92c 2085 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
ef8b9ddc 2086 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
7192f92c 2087 port->read_status_mask |= ATMEL_US_RXBRK;
1e6c9c28 2088
64e22ebe 2089 if (atmel_use_pdc_rx(port))
a6670615 2090 /* need to enable error interrupts */
4e7decda 2091 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
a6670615 2092
1e6c9c28
AV		 2093 /*
2094 * Characters to ignore
2095 */
2096 port->ignore_status_mask = 0;
2097 if (termios->c_iflag & IGNPAR)
7192f92c 2098 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1e6c9c28 2099 if (termios->c_iflag & IGNBRK) {
7192f92c 2100 port->ignore_status_mask |= ATMEL_US_RXBRK;
1e6c9c28
AV		 2101 /*
2102 * If we're ignoring parity and break indicators,
2103 * ignore overruns too (for real raw support).
2104 */
2105 if (termios->c_iflag & IGNPAR)
7192f92c 2106 port->ignore_status_mask |= ATMEL_US_OVRE;
1e6c9c28 2107 }
b843aa21 2108 /* TODO: Ignore all characters if CREAD is set.*/
1e6c9c28
AV		 2109
2110 /* update the per-port timeout */
2111 uart_update_timeout(port, termios->c_cflag, baud);
2112
0ccad870
HS		 2113 /*
2114 * save/disable interrupts. The tty layer will ensure that the
2115 * transmitter is empty if requested by the caller, so there's
2116 * no need to wait for it here.
2117 */
4e7decda
CP		 2118 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2119 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1e6c9c28
AV		 2120
2121 /* disable receiver and transmitter */
4e7decda 2122 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1e6c9c28 2123
1cf6e8fc 2124 /* mode */
13bd3e6f 2125 if (port->rs485.flags & SER_RS485_ENABLED) {
4e7decda
CP		 2126 atmel_uart_writel(port, ATMEL_US_TTGR,
2127 port->rs485.delay_rts_after_send);
e8faff73 2128 mode |= ATMEL_US_USMODE_RS485;
1cf6e8fc
CP		 2129 } else if (termios->c_cflag & CRTSCTS) {
2130 /* RS232 with hardware handshake (RTS/CTS) */
5be605ac
AB		 2131 if (atmel_use_dma_rx(port) && !atmel_use_fifo(port)) {
2132 dev_info(port->dev, "not enabling hardware flow control because DMA is used");
2133 termios->c_cflag &= ~CRTSCTS;
2134 } else {
2135 mode |= ATMEL_US_USMODE_HWHS;
2136 }
1cf6e8fc
CP		 2137 } else {
2138 /* RS232 without hadware handshake */
2139 mode |= ATMEL_US_USMODE_NORMAL;
e8faff73
CS		 2140 }
2141
1cf6e8fc 2142 /* set the mode, clock divisor, parity, stop bits and data size */
4e7decda 2143 atmel_uart_writel(port, ATMEL_US_MR, mode);
1e6c9c28 2144
1cf6e8fc
CP		 2145 /*
2146 * when switching the mode, set the RTS line state according to the
2147 * new mode, otherwise keep the former state
2148 */
2149 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2150 unsigned int rts_state;
2151
2152 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2153 /* let the hardware control the RTS line */
2154 rts_state = ATMEL_US_RTSDIS;
2155 } else {
2156 /* force RTS line to low level */
2157 rts_state = ATMEL_US_RTSEN;
2158 }
2159
4e7decda 2160 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
1cf6e8fc
CP		 2161 }
2162
1e6c9c28 2163 /* set the baud rate */
4e7decda
CP		 2164 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2165 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2166 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV		 2167
2168 /* restore interrupts */
4e7decda 2169 atmel_uart_writel(port, ATMEL_US_IER, imr);
1e6c9c28
AV		 2170
2171 /* CTS flow-control and modem-status interrupts */
2172 if (UART_ENABLE_MS(port, termios->c_cflag))
35b675b9
RG		 2173 atmel_enable_ms(port);
2174 else
2175 atmel_disable_ms(port);
1e6c9c28
AV		 2176
2177 spin_unlock_irqrestore(&port->lock, flags);
2178}
2179
732a84a0 2180static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
42bd7a4f 2181{
732a84a0 2182 if (termios->c_line == N_PPS) {
42bd7a4f 2183 port->flags |= UPF_HARDPPS_CD;
d41510ce 2184 spin_lock_irq(&port->lock);
42bd7a4f 2185 atmel_enable_ms(port);
d41510ce 2186 spin_unlock_irq(&port->lock);
42bd7a4f
VP		 2187 } else {
2188 port->flags &= ~UPF_HARDPPS_CD;
cab68f89
PH		 2189 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2190 spin_lock_irq(&port->lock);
2191 atmel_disable_ms(port);
2192 spin_unlock_irq(&port->lock);
2193 }
42bd7a4f
VP		 2194 }
2195}
2196
1e6c9c28
AV		 2197/*
2198 * Return string describing the specified port
2199 */
7192f92c 2200static const char *atmel_type(struct uart_port *port)
1e6c9c28 2201{
9ab4f88b 2202 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1e6c9c28
AV		 2203}
2204
2205/*
2206 * Release the memory region(s) being used by 'port'.
2207 */
7192f92c 2208static void atmel_release_port(struct uart_port *port)
1e6c9c28 2209{
afefc415
AV		 2210 struct platform_device *pdev = to_platform_device(port->dev);
2211 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2212
2213 release_mem_region(port->mapbase, size);
2214
2215 if (port->flags & UPF_IOREMAP) {
2216 iounmap(port->membase);
2217 port->membase = NULL;
2218 }
1e6c9c28
AV		 2219}
2220
2221/*
2222 * Request the memory region(s) being used by 'port'.
2223 */
7192f92c 2224static int atmel_request_port(struct uart_port *port)
1e6c9c28 2225{
afefc415
AV		 2226 struct platform_device *pdev = to_platform_device(port->dev);
2227 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2228
7192f92c 2229 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
afefc415
AV		 2230 return -EBUSY;
2231
2232 if (port->flags & UPF_IOREMAP) {
2233 port->membase = ioremap(port->mapbase, size);
2234 if (port->membase == NULL) {
2235 release_mem_region(port->mapbase, size);
2236 return -ENOMEM;
2237 }
2238 }
1e6c9c28 2239
afefc415 2240 return 0;
1e6c9c28
AV		 2241}
2242
2243/*
2244 * Configure/autoconfigure the port.
2245 */
7192f92c 2246static void atmel_config_port(struct uart_port *port, int flags)
1e6c9c28
AV		 2247{
2248 if (flags & UART_CONFIG_TYPE) {
9ab4f88b 2249 port->type = PORT_ATMEL;
7192f92c 2250 atmel_request_port(port);
1e6c9c28
AV		 2251 }
2252}
2253
2254/*
2255 * Verify the new serial_struct (for TIOCSSERIAL).
2256 */
7192f92c 2257static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1e6c9c28
AV		 2258{
2259 int ret = 0;
9ab4f88b 2260 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1e6c9c28
AV		 2261 ret = -EINVAL;
2262 if (port->irq != ser->irq)
2263 ret = -EINVAL;
2264 if (ser->io_type != SERIAL_IO_MEM)
2265 ret = -EINVAL;
2266 if (port->uartclk / 16 != ser->baud_base)
2267 ret = -EINVAL;
270c2ade 2268 if (port->mapbase != (unsigned long)ser->iomem_base)
1e6c9c28
AV		 2269 ret = -EINVAL;
2270 if (port->iobase != ser->port)
2271 ret = -EINVAL;
2272 if (ser->hub6 != 0)
2273 ret = -EINVAL;
2274 return ret;
2275}
2276
8fe2d541
AT		 2277#ifdef CONFIG_CONSOLE_POLL
2278static int atmel_poll_get_char(struct uart_port *port)
2279{
4e7decda 2280 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
8fe2d541
AT		 2281 cpu_relax();
2282
a6499435 2283 return atmel_uart_read_char(port);
8fe2d541
AT		 2284}
2285
2286static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2287{
4e7decda 2288 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
8fe2d541
AT		 2289 cpu_relax();
2290
a6499435 2291 atmel_uart_write_char(port, ch);
8fe2d541
AT		 2292}
2293#endif
2294
7192f92c
HS		 2295static struct uart_ops atmel_pops = {
2296 .tx_empty = atmel_tx_empty,
2297 .set_mctrl = atmel_set_mctrl,
2298 .get_mctrl = atmel_get_mctrl,
2299 .stop_tx = atmel_stop_tx,
2300 .start_tx = atmel_start_tx,
2301 .stop_rx = atmel_stop_rx,
2302 .enable_ms = atmel_enable_ms,
2303 .break_ctl = atmel_break_ctl,
2304 .startup = atmel_startup,
2305 .shutdown = atmel_shutdown,
9afd561a 2306 .flush_buffer = atmel_flush_buffer,
7192f92c 2307 .set_termios = atmel_set_termios,
42bd7a4f 2308 .set_ldisc = atmel_set_ldisc,
7192f92c
HS		 2309 .type = atmel_type,
2310 .release_port = atmel_release_port,
2311 .request_port = atmel_request_port,
2312 .config_port = atmel_config_port,
2313 .verify_port = atmel_verify_port,
2314 .pm = atmel_serial_pm,
8fe2d541
AT		 2315#ifdef CONFIG_CONSOLE_POLL
2316 .poll_get_char = atmel_poll_get_char,
2317 .poll_put_char = atmel_poll_put_char,
2318#endif
1e6c9c28
AV		 2319};
2320
afefc415
AV		 2321/*
2322 * Configure the port from the platform device resource info.
2323 */
91f8c2d8 2324static int atmel_init_port(struct atmel_uart_port *atmel_port,
b843aa21 2325 struct platform_device *pdev)
1e6c9c28 2326{
91f8c2d8 2327 int ret;
7192f92c 2328 struct uart_port *port = &atmel_port->uart;
574de559 2329 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
afefc415 2330
4a1e8888
LZ		 2331 atmel_init_property(atmel_port, pdev);
2332 atmel_set_ops(port);
afefc415 2333
13bd3e6f 2334 atmel_init_rs485(port, pdev);
a930e528 2335
e8faff73
CS		 2336 port->iotype = UPIO_MEM;
2337 port->flags = UPF_BOOT_AUTOCONF;
2338 port->ops = &atmel_pops;
2339 port->fifosize = 1;
e8faff73 2340 port->dev = &pdev->dev;
afefc415
AV		 2341 port->mapbase = pdev->resource[0].start;
2342 port->irq = pdev->resource[1].start;
13bd3e6f 2343 port->rs485_config = atmel_config_rs485;
afefc415 2344
1ecc26bd
RB		 2345 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2346
5fbe46b6 2347 if (pdata && pdata->regs) {
75d35213 2348 /* Already mapped by setup code */
1acfc7ec 2349 port->membase = pdata->regs;
588edbf3 2350 } else {
afefc415
AV		 2351 port->flags |= UPF_IOREMAP;
2352 port->membase = NULL;
2353 }
1e6c9c28 2354
b843aa21
RB		 2355 /* for console, the clock could already be configured */
2356 if (!atmel_port->clk) {
7192f92c 2357 atmel_port->clk = clk_get(&pdev->dev, "usart");
91f8c2d8
BB		 2358 if (IS_ERR(atmel_port->clk)) {
2359 ret = PTR_ERR(atmel_port->clk);
2360 atmel_port->clk = NULL;
2361 return ret;
2362 }
2363 ret = clk_prepare_enable(atmel_port->clk);
2364 if (ret) {
2365 clk_put(atmel_port->clk);
2366 atmel_port->clk = NULL;
2367 return ret;
2368 }
7192f92c 2369 port->uartclk = clk_get_rate(atmel_port->clk);
91f8c2d8 2370 clk_disable_unprepare(atmel_port->clk);
06a7f058 2371 /* only enable clock when USART is in use */
afefc415 2372 }
a6670615 2373
e8faff73 2374 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
13bd3e6f 2375 if (port->rs485.flags & SER_RS485_ENABLED)
e8faff73 2376 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
64e22ebe 2377 else if (atmel_use_pdc_tx(port)) {
a6670615 2378 port->fifosize = PDC_BUFFER_SIZE;
e8faff73
CS		 2379 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2380 } else {
2381 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2382 }
91f8c2d8
BB		 2383
2384 return 0;
1e6c9c28
AV		 2385}
2386
69f6a27b
JCPV		 2387struct platform_device *atmel_default_console_device; /* the serial console device */
2388
749c4e60 2389#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
7192f92c 2390static void atmel_console_putchar(struct uart_port *port, int ch)
d358788f 2391{
4e7decda 2392 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
829dd811 2393 cpu_relax();
a6499435 2394 atmel_uart_write_char(port, ch);
d358788f 2395}
1e6c9c28
AV		 2396
2397/*
2398 * Interrupts are disabled on entering
2399 */
7192f92c 2400static void atmel_console_write(struct console *co, const char *s, u_int count)
1e6c9c28 2401{
7192f92c 2402 struct uart_port *port = &atmel_ports[co->index].uart;
e8faff73 2403 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
d358788f 2404 unsigned int status, imr;
39d4c922 2405 unsigned int pdc_tx;
1e6c9c28
AV		 2406
2407 /*
b843aa21 2408 * First, save IMR and then disable interrupts
1e6c9c28 2409 */
4e7decda
CP		 2410 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2411 atmel_uart_writel(port, ATMEL_US_IDR,
2412 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
1e6c9c28 2413
39d4c922 2414 /* Store PDC transmit status and disable it */
4e7decda
CP		 2415 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2416 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
39d4c922 2417
7192f92c 2418 uart_console_write(port, s, count, atmel_console_putchar);
1e6c9c28
AV		 2419
2420 /*
b843aa21
RB		 2421 * Finally, wait for transmitter to become empty
2422 * and restore IMR
1e6c9c28
AV		 2423 */
2424 do {
4e7decda 2425 status = atmel_uart_readl(port, ATMEL_US_CSR);
7192f92c 2426 } while (!(status & ATMEL_US_TXRDY));
39d4c922
MP		 2427
2428 /* Restore PDC transmit status */
2429 if (pdc_tx)
4e7decda 2430 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
39d4c922 2431
b843aa21 2432 /* set interrupts back the way they were */
4e7decda 2433 atmel_uart_writel(port, ATMEL_US_IER, imr);
1e6c9c28
AV		 2434}
2435
2436/*
b843aa21
RB		 2437 * If the port was already initialised (eg, by a boot loader),
2438 * try to determine the current setup.
1e6c9c28 2439 */
b843aa21
RB		 2440static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2441 int *parity, int *bits)
1e6c9c28
AV		 2442{
2443 unsigned int mr, quot;
2444
1c0fd82f
HS		 2445 /*
2446 * If the baud rate generator isn't running, the port wasn't
2447 * initialized by the boot loader.
2448 */
4e7decda 2449 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
1c0fd82f
HS		 2450 if (!quot)
2451 return;
1e6c9c28 2452
4e7decda 2453 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
7192f92c 2454 if (mr == ATMEL_US_CHRL_8)
1e6c9c28
AV		 2455 *bits = 8;
2456 else
2457 *bits = 7;
2458
4e7decda 2459 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
7192f92c 2460 if (mr == ATMEL_US_PAR_EVEN)
1e6c9c28 2461 *parity = 'e';
7192f92c 2462 else if (mr == ATMEL_US_PAR_ODD)
1e6c9c28
AV		 2463 *parity = 'o';
2464
4d5e392c
HS		 2465 /*
2466 * The serial core only rounds down when matching this to a
2467 * supported baud rate. Make sure we don't end up slightly
2468 * lower than one of those, as it would make us fall through
2469 * to a much lower baud rate than we really want.
2470 */
4d5e392c 2471 *baud = port->uartclk / (16 * (quot - 1));
1e6c9c28
AV		 2472}
2473
7192f92c 2474static int __init atmel_console_setup(struct console *co, char *options)
1e6c9c28 2475{
91f8c2d8 2476 int ret;
7192f92c 2477 struct uart_port *port = &atmel_ports[co->index].uart;
1e6c9c28
AV		 2478 int baud = 115200;
2479 int bits = 8;
2480 int parity = 'n';
2481 int flow = 'n';
2482
b843aa21
RB		 2483 if (port->membase == NULL) {
2484 /* Port not initialized yet - delay setup */
afefc415 2485 return -ENODEV;
b843aa21 2486 }
1e6c9c28 2487
91f8c2d8
BB		 2488 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2489 if (ret)
2490 return ret;
06a7f058 2491
4e7decda
CP		 2492 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2493 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2494 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1e6c9c28
AV		 2495
2496 if (options)
2497 uart_parse_options(options, &baud, &parity, &bits, &flow);
2498 else
7192f92c 2499 atmel_console_get_options(port, &baud, &parity, &bits);
1e6c9c28
AV		 2500
2501 return uart_set_options(port, co, baud, parity, bits, flow);
2502}
2503
7192f92c 2504static struct uart_driver atmel_uart;
1e6c9c28 2505
7192f92c
HS		 2506static struct console atmel_console = {
2507 .name = ATMEL_DEVICENAME,
2508 .write = atmel_console_write,
1e6c9c28 2509 .device = uart_console_device,
7192f92c 2510 .setup = atmel_console_setup,
1e6c9c28
AV		 2511 .flags = CON_PRINTBUFFER,
2512 .index = -1,
7192f92c 2513 .data = &atmel_uart,
1e6c9c28
AV		 2514};
2515
06a7f058 2516#define ATMEL_CONSOLE_DEVICE (&atmel_console)
1e6c9c28 2517
afefc415
AV		 2518/*
2519 * Early console initialization (before VM subsystem initialized).
2520 */
7192f92c 2521static int __init atmel_console_init(void)
1e6c9c28 2522{
91f8c2d8 2523 int ret;
73e2798b 2524 if (atmel_default_console_device) {
0d0a3cc1 2525 struct atmel_uart_data *pdata =
574de559 2526 dev_get_platdata(&atmel_default_console_device->dev);
efb8d21b 2527 int id = pdata->num;
b78cd169 2528 struct atmel_uart_port *atmel_port = &atmel_ports[id];
4cbf9f48 2529
b78cd169
JA		 2530 atmel_port->backup_imr = 0;
2531 atmel_port->uart.line = id;
0d0a3cc1 2532
4cbf9f48 2533 add_preferred_console(ATMEL_DEVICENAME, id, NULL);
b78cd169 2534 ret = atmel_init_port(atmel_port, atmel_default_console_device);
91f8c2d8
BB		 2535 if (ret)
2536 return ret;
7192f92c 2537 register_console(&atmel_console);
afefc415 2538 }
1e6c9c28 2539
1e6c9c28
AV		 2540 return 0;
2541}
b843aa21 2542
7192f92c 2543console_initcall(atmel_console_init);
1e6c9c28 2544
afefc415
AV		 2545/*
2546 * Late console initialization.
2547 */
7192f92c 2548static int __init atmel_late_console_init(void)
afefc415 2549{
b843aa21
RB		 2550 if (atmel_default_console_device
2551 && !(atmel_console.flags & CON_ENABLED))
7192f92c 2552 register_console(&atmel_console);
afefc415
AV		 2553
2554 return 0;
2555}
b843aa21 2556
7192f92c 2557core_initcall(atmel_late_console_init);
afefc415 2558
dfa7f343
HS		 2559static inline bool atmel_is_console_port(struct uart_port *port)
2560{
2561 return port->cons && port->cons->index == port->line;
2562}
2563
1e6c9c28 2564#else
7192f92c 2565#define ATMEL_CONSOLE_DEVICE NULL
dfa7f343
HS		 2566
2567static inline bool atmel_is_console_port(struct uart_port *port)
2568{
2569 return false;
2570}
1e6c9c28
AV		 2571#endif
2572
7192f92c 2573static struct uart_driver atmel_uart = {
b843aa21
RB		 2574 .owner = THIS_MODULE,
2575 .driver_name = "atmel_serial",
2576 .dev_name = ATMEL_DEVICENAME,
2577 .major = SERIAL_ATMEL_MAJOR,
2578 .minor = MINOR_START,
2579 .nr = ATMEL_MAX_UART,
2580 .cons = ATMEL_CONSOLE_DEVICE,
1e6c9c28
AV		 2581};
2582
afefc415 2583#ifdef CONFIG_PM
f826caa4
HS		 2584static bool atmel_serial_clk_will_stop(void)
2585{
2586#ifdef CONFIG_ARCH_AT91
2587 return at91_suspend_entering_slow_clock();
2588#else
2589 return false;
2590#endif
2591}
2592
b843aa21
RB		 2593static int atmel_serial_suspend(struct platform_device *pdev,
2594 pm_message_t state)
1e6c9c28 2595{
afefc415 2596 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2597 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
afefc415 2598
e1c609ef
HS		 2599 if (atmel_is_console_port(port) && console_suspend_enabled) {
2600 /* Drain the TX shifter */
4e7decda
CP		 2601 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2602 ATMEL_US_TXEMPTY))
e1c609ef
HS		 2603 cpu_relax();
2604 }
2605
f05596db
AS		 2606 /* we can not wake up if we're running on slow clock */
2607 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2c7af5ba
BB		 2608 if (atmel_serial_clk_will_stop()) {
2609 unsigned long flags;
2610
2611 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2612 atmel_port->suspended = true;
2613 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
f05596db 2614 device_set_wakeup_enable(&pdev->dev, 0);
2c7af5ba 2615 }
f05596db
AS		 2616
2617 uart_suspend_port(&atmel_uart, port);
1e6c9c28 2618
afefc415
AV		 2619 return 0;
2620}
1e6c9c28 2621
7192f92c 2622static int atmel_serial_resume(struct platform_device *pdev)
afefc415
AV		 2623{
2624 struct uart_port *port = platform_get_drvdata(pdev);
c811ab8c 2625 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2c7af5ba
BB		 2626 unsigned long flags;
2627
2628 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2629 if (atmel_port->pending) {
2630 atmel_handle_receive(port, atmel_port->pending);
2631 atmel_handle_status(port, atmel_port->pending,
2632 atmel_port->pending_status);
2633 atmel_handle_transmit(port, atmel_port->pending);
2634 atmel_port->pending = 0;
2635 }
2636 atmel_port->suspended = false;
2637 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
1e6c9c28 2638
f05596db
AS		 2639 uart_resume_port(&atmel_uart, port);
2640 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
1e6c9c28
AV		 2641
2642 return 0;
2643}
afefc415 2644#else
7192f92c
HS		 2645#define atmel_serial_suspend NULL
2646#define atmel_serial_resume NULL
afefc415 2647#endif
1e6c9c28 2648
b78cd169 2649static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
b5199d46
CP		 2650 struct platform_device *pdev)
2651{
b78cd169
JA		 2652 atmel_port->fifo_size = 0;
2653 atmel_port->rts_low = 0;
2654 atmel_port->rts_high = 0;
b5199d46
CP		 2655
2656 if (of_property_read_u32(pdev->dev.of_node,
2657 "atmel,fifo-size",
b78cd169 2658 &atmel_port->fifo_size))
b5199d46
CP		 2659 return;
2660
b78cd169 2661 if (!atmel_port->fifo_size)
b5199d46
CP		 2662 return;
2663
b78cd169
JA		 2664 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2665 atmel_port->fifo_size = 0;
b5199d46
CP		 2666 dev_err(&pdev->dev, "Invalid FIFO size\n");
2667 return;
2668 }
2669
2670 /*
2671 * 0 <= rts_low <= rts_high <= fifo_size
2672 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2673 * to flush their internal TX FIFO, commonly up to 16 data, before
2674 * actually stopping to send new data. So we try to set the RTS High
2675 * Threshold to a reasonably high value respecting this 16 data
2676 * empirical rule when possible.
2677 */
b78cd169
JA		 2678 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2679 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2680 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2681 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
b5199d46
CP		 2682
2683 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
b78cd169 2684 atmel_port->fifo_size);
b5199d46 2685 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
b78cd169 2686 atmel_port->rts_high);
b5199d46 2687 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
b78cd169 2688 atmel_port->rts_low);
b5199d46
CP		 2689}
2690
9671f099 2691static int atmel_serial_probe(struct platform_device *pdev)
1e6c9c28 2692{
b78cd169 2693 struct atmel_uart_port *atmel_port;
5fbe46b6 2694 struct device_node *np = pdev->dev.of_node;
574de559 2695 struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev);
1ecc26bd 2696 void *data;
4cbf9f48 2697 int ret = -ENODEV;
bd737f87 2698 bool rs485_enabled;
1e6c9c28 2699
9d09daf8 2700 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1ecc26bd 2701
5fbe46b6
NF		 2702 if (np)
2703 ret = of_alias_get_id(np, "serial");
2704 else
2705 if (pdata)
2706 ret = pdata->num;
4cbf9f48
NF		 2707
2708 if (ret < 0)
5fbe46b6 2709 /* port id not found in platform data nor device-tree aliases:
4cbf9f48 2710 * auto-enumerate it */
503bded9 2711 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
4cbf9f48 2712
503bded9 2713 if (ret >= ATMEL_MAX_UART) {
4cbf9f48
NF		 2714 ret = -ENODEV;
2715 goto err;
2716 }
2717
503bded9 2718 if (test_and_set_bit(ret, atmel_ports_in_use)) {
4cbf9f48
NF		 2719 /* port already in use */
2720 ret = -EBUSY;
2721 goto err;
2722 }
2723
b78cd169
JA		 2724 atmel_port = &atmel_ports[ret];
2725 atmel_port->backup_imr = 0;
2726 atmel_port->uart.line = ret;
2727 atmel_serial_probe_fifos(atmel_port, pdev);
e0b0baad 2728
98f2082c 2729 atomic_set(&atmel_port->tasklet_shutdown, 0);
b78cd169 2730 spin_lock_init(&atmel_port->lock_suspended);
2c7af5ba 2731
b78cd169 2732 ret = atmel_init_port(atmel_port, pdev);
91f8c2d8 2733 if (ret)
6fbb9bdf 2734 goto err_clear_bit;
1e6c9c28 2735
b78cd169
JA		 2736 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2737 if (IS_ERR(atmel_port->gpios)) {
2738 ret = PTR_ERR(atmel_port->gpios);
18dfef9c
UKK		 2739 goto err_clear_bit;
2740 }
2741
b78cd169 2742 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
a6670615 2743 ret = -ENOMEM;
6433471d
HS		 2744 data = kmalloc(sizeof(struct atmel_uart_char)
2745 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
a6670615
CC		 2746 if (!data)
2747 goto err_alloc_ring;
b78cd169 2748 atmel_port->rx_ring.buf = data;
a6670615 2749 }
1ecc26bd 2750
b78cd169 2751 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
bd737f87 2752
b78cd169 2753 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
dfa7f343
HS		 2754 if (ret)
2755 goto err_add_port;
2756
8da14b5f 2757#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
b78cd169 2758 if (atmel_is_console_port(&atmel_port->uart)
06a7f058
DB		 2759 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2760 /*
2761 * The serial core enabled the clock for us, so undo
91f8c2d8 2762 * the clk_prepare_enable() in atmel_console_setup()
06a7f058 2763 */
b78cd169 2764 clk_disable_unprepare(atmel_port->clk);
06a7f058 2765 }
8da14b5f 2766#endif
06a7f058 2767
dfa7f343 2768 device_init_wakeup(&pdev->dev, 1);
b78cd169 2769 platform_set_drvdata(pdev, atmel_port);
dfa7f343 2770
d4f64187
CP		 2771 /*
2772 * The peripheral clock has been disabled by atmel_init_port():
2773 * enable it before accessing I/O registers
2774 */
b78cd169 2775 clk_prepare_enable(atmel_port->clk);
d4f64187 2776
bd737f87 2777 if (rs485_enabled) {
b78cd169 2778 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
4e7decda 2779 ATMEL_US_USMODE_NORMAL);
b78cd169
JA		 2780 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2781 ATMEL_US_RTSEN);
5dfbd1d7
CS		 2782 }
2783
055560b0
ES		 2784 /*
2785 * Get port name of usart or uart
2786 */
b78cd169 2787 atmel_get_ip_name(&atmel_port->uart);
055560b0 2788
d4f64187
CP		 2789 /*
2790 * The peripheral clock can now safely be disabled till the port
2791 * is used
2792 */
b78cd169 2793 clk_disable_unprepare(atmel_port->clk);
d4f64187 2794
dfa7f343
HS		 2795 return 0;
2796
2797err_add_port:
b78cd169
JA		 2798 kfree(atmel_port->rx_ring.buf);
2799 atmel_port->rx_ring.buf = NULL;
1ecc26bd 2800err_alloc_ring:
b78cd169
JA		 2801 if (!atmel_is_console_port(&atmel_port->uart)) {
2802 clk_put(atmel_port->clk);
2803 atmel_port->clk = NULL;
afefc415 2804 }
6fbb9bdf 2805err_clear_bit:
b78cd169 2806 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
4cbf9f48 2807err:
afefc415
AV		 2808 return ret;
2809}
2810
f4a8ab04
RI		 2811/*
2812 * Even if the driver is not modular, it makes sense to be able to
2813 * unbind a device: there can be many bound devices, and there are
2814 * situations where dynamic binding and unbinding can be useful.
2815 *
2816 * For example, a connected device can require a specific firmware update
2817 * protocol that needs bitbanging on IO lines, but use the regular serial
2818 * port in the normal case.
2819 */
2820static int atmel_serial_remove(struct platform_device *pdev)
2821{
2822 struct uart_port *port = platform_get_drvdata(pdev);
2823 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2824 int ret = 0;
2825
00e8e658
NF		 2826 tasklet_kill(&atmel_port->tasklet_rx);
2827 tasklet_kill(&atmel_port->tasklet_tx);
f4a8ab04
RI		 2828
2829 device_init_wakeup(&pdev->dev, 0);
2830
2831 ret = uart_remove_one_port(&atmel_uart, port);
2832
2833 kfree(atmel_port->rx_ring.buf);
2834
2835 /* "port" is allocated statically, so we shouldn't free it */
2836
2837 clear_bit(port->line, atmel_ports_in_use);
2838
2839 clk_put(atmel_port->clk);
2840 atmel_port->clk = NULL;
2841
2842 return ret;
2843}
2844
7192f92c
HS		 2845static struct platform_driver atmel_serial_driver = {
2846 .probe = atmel_serial_probe,
f4a8ab04 2847 .remove = atmel_serial_remove,
7192f92c
HS		 2848 .suspend = atmel_serial_suspend,
2849 .resume = atmel_serial_resume,
afefc415 2850 .driver = {
c39dfebc
PG		 2851 .name = "atmel_usart",
2852 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
afefc415
AV		 2853 },
2854};
2855
7192f92c 2856static int __init atmel_serial_init(void)
afefc415
AV		 2857{
2858 int ret;
2859
7192f92c 2860 ret = uart_register_driver(&atmel_uart);
afefc415
AV		 2861 if (ret)
2862 return ret;
2863
7192f92c 2864 ret = platform_driver_register(&atmel_serial_driver);
afefc415 2865 if (ret)
7192f92c 2866 uart_unregister_driver(&atmel_uart);
afefc415
AV		 2867
2868 return ret;
2869}
c39dfebc 2870device_initcall(atmel_serial_init);
Linux kernel - Deliverables
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