Commit | Line | Data |
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1e6c9c28 | 1 | /* |
7192f92c | 2 | * Driver for Atmel AT91 / AT32 Serial ports |
1e6c9c28 AV |
3 | * Copyright (C) 2003 Rick Bronson |
4 | * | |
5 | * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd. | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * | |
a6670615 CC |
8 | * DMA support added by Chip Coldwell. |
9 | * | |
1e6c9c28 AV |
10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
23 | * | |
24 | */ | |
1e6c9c28 AV |
25 | #include <linux/module.h> |
26 | #include <linux/tty.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/slab.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/serial.h> | |
afefc415 | 31 | #include <linux/clk.h> |
1e6c9c28 AV |
32 | #include <linux/console.h> |
33 | #include <linux/sysrq.h> | |
34 | #include <linux/tty_flip.h> | |
afefc415 | 35 | #include <linux/platform_device.h> |
5fbe46b6 NF |
36 | #include <linux/of.h> |
37 | #include <linux/of_device.h> | |
354e57f3 | 38 | #include <linux/of_gpio.h> |
a6670615 | 39 | #include <linux/dma-mapping.h> |
6b997bab | 40 | #include <linux/dmaengine.h> |
93a3ddc2 | 41 | #include <linux/atmel_pdc.h> |
fa3218d8 | 42 | #include <linux/atmel_serial.h> |
e8faff73 | 43 | #include <linux/uaccess.h> |
bcd2360c | 44 | #include <linux/platform_data/atmel.h> |
2e68c22f | 45 | #include <linux/timer.h> |
354e57f3 | 46 | #include <linux/gpio.h> |
e0b0baad RG |
47 | #include <linux/gpio/consumer.h> |
48 | #include <linux/err.h> | |
ab5e4e41 | 49 | #include <linux/irq.h> |
2c7af5ba | 50 | #include <linux/suspend.h> |
1e6c9c28 AV |
51 | |
52 | #include <asm/io.h> | |
f7512e7c | 53 | #include <asm/ioctls.h> |
1e6c9c28 | 54 | |
a6670615 CC |
55 | #define PDC_BUFFER_SIZE 512 |
56 | /* Revisit: We should calculate this based on the actual port settings */ | |
57 | #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */ | |
58 | ||
b5199d46 CP |
59 | /* The minium number of data FIFOs should be able to contain */ |
60 | #define ATMEL_MIN_FIFO_SIZE 8 | |
61 | /* | |
62 | * These two offsets are substracted from the RX FIFO size to define the RTS | |
63 | * high and low thresholds | |
64 | */ | |
65 | #define ATMEL_RTS_HIGH_OFFSET 16 | |
66 | #define ATMEL_RTS_LOW_OFFSET 20 | |
67 | ||
749c4e60 | 68 | #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
1e6c9c28 AV |
69 | #define SUPPORT_SYSRQ |
70 | #endif | |
71 | ||
72 | #include <linux/serial_core.h> | |
73 | ||
e0b0baad RG |
74 | #include "serial_mctrl_gpio.h" |
75 | ||
e8faff73 CS |
76 | static void atmel_start_rx(struct uart_port *port); |
77 | static void atmel_stop_rx(struct uart_port *port); | |
78 | ||
749c4e60 | 79 | #ifdef CONFIG_SERIAL_ATMEL_TTYAT |
1e6c9c28 AV |
80 | |
81 | /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we | |
82 | * should coexist with the 8250 driver, such as if we have an external 16C550 | |
83 | * UART. */ | |
7192f92c | 84 | #define SERIAL_ATMEL_MAJOR 204 |
1e6c9c28 | 85 | #define MINOR_START 154 |
7192f92c | 86 | #define ATMEL_DEVICENAME "ttyAT" |
1e6c9c28 AV |
87 | |
88 | #else | |
89 | ||
90 | /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port | |
91 | * name, but it is legally reserved for the 8250 driver. */ | |
7192f92c | 92 | #define SERIAL_ATMEL_MAJOR TTY_MAJOR |
1e6c9c28 | 93 | #define MINOR_START 64 |
7192f92c | 94 | #define ATMEL_DEVICENAME "ttyS" |
1e6c9c28 AV |
95 | |
96 | #endif | |
97 | ||
7192f92c | 98 | #define ATMEL_ISR_PASS_LIMIT 256 |
1e6c9c28 | 99 | |
a6670615 CC |
100 | struct atmel_dma_buffer { |
101 | unsigned char *buf; | |
102 | dma_addr_t dma_addr; | |
103 | unsigned int dma_size; | |
104 | unsigned int ofs; | |
105 | }; | |
106 | ||
1ecc26bd RB |
107 | struct atmel_uart_char { |
108 | u16 status; | |
109 | u16 ch; | |
110 | }; | |
111 | ||
112 | #define ATMEL_SERIAL_RINGSIZE 1024 | |
113 | ||
9af92fbf AB |
114 | /* |
115 | * at91: 6 USARTs and one DBGU port (SAM9260) | |
116 | * avr32: 4 | |
117 | */ | |
118 | #define ATMEL_MAX_UART 7 | |
119 | ||
afefc415 AV |
120 | /* |
121 | * We wrap our port structure around the generic uart_port. | |
122 | */ | |
7192f92c | 123 | struct atmel_uart_port { |
afefc415 AV |
124 | struct uart_port uart; /* uart */ |
125 | struct clk *clk; /* uart clock */ | |
f05596db AS |
126 | int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ |
127 | u32 backup_imr; /* IMR saved during suspend */ | |
9e6077bd | 128 | int break_active; /* break being received */ |
1ecc26bd | 129 | |
34df42f5 | 130 | bool use_dma_rx; /* enable DMA receiver */ |
64e22ebe | 131 | bool use_pdc_rx; /* enable PDC receiver */ |
a6670615 CC |
132 | short pdc_rx_idx; /* current PDC RX buffer */ |
133 | struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */ | |
134 | ||
08f738be | 135 | bool use_dma_tx; /* enable DMA transmitter */ |
64e22ebe | 136 | bool use_pdc_tx; /* enable PDC transmitter */ |
a6670615 CC |
137 | struct atmel_dma_buffer pdc_tx; /* PDC transmitter */ |
138 | ||
08f738be | 139 | spinlock_t lock_tx; /* port lock */ |
34df42f5 | 140 | spinlock_t lock_rx; /* port lock */ |
08f738be | 141 | struct dma_chan *chan_tx; |
34df42f5 | 142 | struct dma_chan *chan_rx; |
08f738be | 143 | struct dma_async_tx_descriptor *desc_tx; |
34df42f5 | 144 | struct dma_async_tx_descriptor *desc_rx; |
08f738be | 145 | dma_cookie_t cookie_tx; |
34df42f5 | 146 | dma_cookie_t cookie_rx; |
08f738be | 147 | struct scatterlist sg_tx; |
34df42f5 | 148 | struct scatterlist sg_rx; |
1ecc26bd RB |
149 | struct tasklet_struct tasklet; |
150 | unsigned int irq_status; | |
151 | unsigned int irq_status_prev; | |
d033e82d | 152 | unsigned int status_change; |
5f258b3e | 153 | unsigned int tx_len; |
1ecc26bd RB |
154 | |
155 | struct circ_buf rx_ring; | |
e8faff73 | 156 | |
e0b0baad | 157 | struct mctrl_gpios *gpios; |
ab5e4e41 | 158 | int gpio_irq[UART_GPIO_MAX]; |
e8faff73 | 159 | unsigned int tx_done_mask; |
b5199d46 CP |
160 | u32 fifo_size; |
161 | u32 rts_high; | |
162 | u32 rts_low; | |
ab5e4e41 | 163 | bool ms_irq_enabled; |
055560b0 | 164 | bool is_usart; /* usart or uart */ |
2e68c22f | 165 | struct timer_list uart_timer; /* uart timer */ |
2c7af5ba BB |
166 | |
167 | bool suspended; | |
168 | unsigned int pending; | |
169 | unsigned int pending_status; | |
170 | spinlock_t lock_suspended; | |
171 | ||
a930e528 ES |
172 | int (*prepare_rx)(struct uart_port *port); |
173 | int (*prepare_tx)(struct uart_port *port); | |
174 | void (*schedule_rx)(struct uart_port *port); | |
175 | void (*schedule_tx)(struct uart_port *port); | |
176 | void (*release_rx)(struct uart_port *port); | |
177 | void (*release_tx)(struct uart_port *port); | |
afefc415 AV |
178 | }; |
179 | ||
7192f92c | 180 | static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART]; |
503bded9 | 181 | static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART); |
afefc415 | 182 | |
1e6c9c28 | 183 | #ifdef SUPPORT_SYSRQ |
7192f92c | 184 | static struct console atmel_console; |
1e6c9c28 AV |
185 | #endif |
186 | ||
5fbe46b6 NF |
187 | #if defined(CONFIG_OF) |
188 | static const struct of_device_id atmel_serial_dt_ids[] = { | |
189 | { .compatible = "atmel,at91rm9200-usart" }, | |
190 | { .compatible = "atmel,at91sam9260-usart" }, | |
191 | { /* sentinel */ } | |
192 | }; | |
193 | ||
194 | MODULE_DEVICE_TABLE(of, atmel_serial_dt_ids); | |
195 | #endif | |
196 | ||
c811ab8c HS |
197 | static inline struct atmel_uart_port * |
198 | to_atmel_uart_port(struct uart_port *uart) | |
199 | { | |
200 | return container_of(uart, struct atmel_uart_port, uart); | |
201 | } | |
202 | ||
4e7decda CP |
203 | static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg) |
204 | { | |
205 | return __raw_readl(port->membase + reg); | |
206 | } | |
207 | ||
208 | static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value) | |
209 | { | |
210 | __raw_writel(value, port->membase + reg); | |
211 | } | |
212 | ||
a6499435 CP |
213 | #ifdef CONFIG_AVR32 |
214 | ||
215 | /* AVR32 cannot handle 8 or 16bit I/O accesses but only 32bit I/O accesses */ | |
216 | static inline u8 atmel_uart_read_char(struct uart_port *port) | |
217 | { | |
218 | return __raw_readl(port->membase + ATMEL_US_RHR); | |
219 | } | |
220 | ||
221 | static inline void atmel_uart_write_char(struct uart_port *port, u8 value) | |
b5199d46 | 222 | { |
a6499435 | 223 | __raw_writel(value, port->membase + ATMEL_US_THR); |
b5199d46 CP |
224 | } |
225 | ||
a6499435 CP |
226 | #else |
227 | ||
228 | static inline u8 atmel_uart_read_char(struct uart_port *port) | |
b5199d46 | 229 | { |
a6499435 | 230 | return __raw_readb(port->membase + ATMEL_US_RHR); |
b5199d46 CP |
231 | } |
232 | ||
a6499435 CP |
233 | static inline void atmel_uart_write_char(struct uart_port *port, u8 value) |
234 | { | |
235 | __raw_writeb(value, port->membase + ATMEL_US_THR); | |
236 | } | |
237 | ||
238 | #endif | |
239 | ||
a6670615 | 240 | #ifdef CONFIG_SERIAL_ATMEL_PDC |
64e22ebe | 241 | static bool atmel_use_pdc_rx(struct uart_port *port) |
a6670615 | 242 | { |
c811ab8c | 243 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 | 244 | |
64e22ebe | 245 | return atmel_port->use_pdc_rx; |
a6670615 CC |
246 | } |
247 | ||
64e22ebe | 248 | static bool atmel_use_pdc_tx(struct uart_port *port) |
a6670615 | 249 | { |
c811ab8c | 250 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
a6670615 | 251 | |
64e22ebe | 252 | return atmel_port->use_pdc_tx; |
a6670615 CC |
253 | } |
254 | #else | |
64e22ebe | 255 | static bool atmel_use_pdc_rx(struct uart_port *port) |
a6670615 CC |
256 | { |
257 | return false; | |
258 | } | |
259 | ||
64e22ebe | 260 | static bool atmel_use_pdc_tx(struct uart_port *port) |
a6670615 CC |
261 | { |
262 | return false; | |
263 | } | |
264 | #endif | |
265 | ||
08f738be ES |
266 | static bool atmel_use_dma_tx(struct uart_port *port) |
267 | { | |
268 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
269 | ||
270 | return atmel_port->use_dma_tx; | |
271 | } | |
272 | ||
34df42f5 ES |
273 | static bool atmel_use_dma_rx(struct uart_port *port) |
274 | { | |
275 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
276 | ||
277 | return atmel_port->use_dma_rx; | |
278 | } | |
279 | ||
e0b0baad RG |
280 | static unsigned int atmel_get_lines_status(struct uart_port *port) |
281 | { | |
282 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
283 | unsigned int status, ret = 0; | |
284 | ||
4e7decda | 285 | status = atmel_uart_readl(port, ATMEL_US_CSR); |
e0b0baad RG |
286 | |
287 | mctrl_gpio_get(atmel_port->gpios, &ret); | |
288 | ||
289 | if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, | |
290 | UART_GPIO_CTS))) { | |
291 | if (ret & TIOCM_CTS) | |
292 | status &= ~ATMEL_US_CTS; | |
293 | else | |
294 | status |= ATMEL_US_CTS; | |
295 | } | |
296 | ||
297 | if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, | |
298 | UART_GPIO_DSR))) { | |
299 | if (ret & TIOCM_DSR) | |
300 | status &= ~ATMEL_US_DSR; | |
301 | else | |
302 | status |= ATMEL_US_DSR; | |
303 | } | |
304 | ||
305 | if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, | |
306 | UART_GPIO_RI))) { | |
307 | if (ret & TIOCM_RI) | |
308 | status &= ~ATMEL_US_RI; | |
309 | else | |
310 | status |= ATMEL_US_RI; | |
311 | } | |
312 | ||
313 | if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios, | |
314 | UART_GPIO_DCD))) { | |
315 | if (ret & TIOCM_CD) | |
316 | status &= ~ATMEL_US_DCD; | |
317 | else | |
318 | status |= ATMEL_US_DCD; | |
319 | } | |
320 | ||
321 | return status; | |
322 | } | |
323 | ||
e8faff73 | 324 | /* Enable or disable the rs485 support */ |
13bd3e6f RRD |
325 | static int atmel_config_rs485(struct uart_port *port, |
326 | struct serial_rs485 *rs485conf) | |
e8faff73 CS |
327 | { |
328 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
329 | unsigned int mode; | |
e8faff73 CS |
330 | |
331 | /* Disable interrupts */ | |
4e7decda | 332 | atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); |
e8faff73 | 333 | |
4e7decda | 334 | mode = atmel_uart_readl(port, ATMEL_US_MR); |
e8faff73 CS |
335 | |
336 | /* Resetting serial mode to RS232 (0x0) */ | |
337 | mode &= ~ATMEL_US_USMODE; | |
338 | ||
13bd3e6f | 339 | port->rs485 = *rs485conf; |
e8faff73 CS |
340 | |
341 | if (rs485conf->flags & SER_RS485_ENABLED) { | |
342 | dev_dbg(port->dev, "Setting UART to RS485\n"); | |
343 | atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; | |
4e7decda CP |
344 | atmel_uart_writel(port, ATMEL_US_TTGR, |
345 | rs485conf->delay_rts_after_send); | |
e8faff73 CS |
346 | mode |= ATMEL_US_USMODE_RS485; |
347 | } else { | |
348 | dev_dbg(port->dev, "Setting UART to RS232\n"); | |
64e22ebe | 349 | if (atmel_use_pdc_tx(port)) |
e8faff73 CS |
350 | atmel_port->tx_done_mask = ATMEL_US_ENDTX | |
351 | ATMEL_US_TXBUFE; | |
352 | else | |
353 | atmel_port->tx_done_mask = ATMEL_US_TXRDY; | |
354 | } | |
4e7decda | 355 | atmel_uart_writel(port, ATMEL_US_MR, mode); |
e8faff73 CS |
356 | |
357 | /* Enable interrupts */ | |
4e7decda | 358 | atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); |
e8faff73 | 359 | |
13bd3e6f | 360 | return 0; |
e8faff73 CS |
361 | } |
362 | ||
1e6c9c28 AV |
363 | /* |
364 | * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty. | |
365 | */ | |
7192f92c | 366 | static u_int atmel_tx_empty(struct uart_port *port) |
1e6c9c28 | 367 | { |
4e7decda CP |
368 | return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ? |
369 | TIOCSER_TEMT : | |
370 | 0; | |
1e6c9c28 AV |
371 | } |
372 | ||
373 | /* | |
374 | * Set state of the modem control output lines | |
375 | */ | |
7192f92c | 376 | static void atmel_set_mctrl(struct uart_port *port, u_int mctrl) |
1e6c9c28 AV |
377 | { |
378 | unsigned int control = 0; | |
4e7decda | 379 | unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR); |
1cf6e8fc | 380 | unsigned int rts_paused, rts_ready; |
e8faff73 | 381 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 382 | |
1cf6e8fc CP |
383 | /* override mode to RS485 if needed, otherwise keep the current mode */ |
384 | if (port->rs485.flags & SER_RS485_ENABLED) { | |
4e7decda CP |
385 | atmel_uart_writel(port, ATMEL_US_TTGR, |
386 | port->rs485.delay_rts_after_send); | |
1cf6e8fc CP |
387 | mode &= ~ATMEL_US_USMODE; |
388 | mode |= ATMEL_US_USMODE_RS485; | |
389 | } | |
390 | ||
391 | /* set the RTS line state according to the mode */ | |
392 | if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { | |
393 | /* force RTS line to high level */ | |
394 | rts_paused = ATMEL_US_RTSEN; | |
395 | ||
396 | /* give the control of the RTS line back to the hardware */ | |
397 | rts_ready = ATMEL_US_RTSDIS; | |
398 | } else { | |
399 | /* force RTS line to high level */ | |
400 | rts_paused = ATMEL_US_RTSDIS; | |
401 | ||
402 | /* force RTS line to low level */ | |
403 | rts_ready = ATMEL_US_RTSEN; | |
404 | } | |
405 | ||
1e6c9c28 | 406 | if (mctrl & TIOCM_RTS) |
1cf6e8fc | 407 | control |= rts_ready; |
1e6c9c28 | 408 | else |
1cf6e8fc | 409 | control |= rts_paused; |
1e6c9c28 AV |
410 | |
411 | if (mctrl & TIOCM_DTR) | |
7192f92c | 412 | control |= ATMEL_US_DTREN; |
1e6c9c28 | 413 | else |
7192f92c | 414 | control |= ATMEL_US_DTRDIS; |
1e6c9c28 | 415 | |
4e7decda | 416 | atmel_uart_writel(port, ATMEL_US_CR, control); |
afefc415 | 417 | |
e0b0baad RG |
418 | mctrl_gpio_set(atmel_port->gpios, mctrl); |
419 | ||
afefc415 | 420 | /* Local loopback mode? */ |
1cf6e8fc | 421 | mode &= ~ATMEL_US_CHMODE; |
afefc415 | 422 | if (mctrl & TIOCM_LOOP) |
7192f92c | 423 | mode |= ATMEL_US_CHMODE_LOC_LOOP; |
afefc415 | 424 | else |
7192f92c | 425 | mode |= ATMEL_US_CHMODE_NORMAL; |
e8faff73 | 426 | |
4e7decda | 427 | atmel_uart_writel(port, ATMEL_US_MR, mode); |
1e6c9c28 AV |
428 | } |
429 | ||
430 | /* | |
431 | * Get state of the modem control input lines | |
432 | */ | |
7192f92c | 433 | static u_int atmel_get_mctrl(struct uart_port *port) |
1e6c9c28 | 434 | { |
e0b0baad RG |
435 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
436 | unsigned int ret = 0, status; | |
1e6c9c28 | 437 | |
4e7decda | 438 | status = atmel_uart_readl(port, ATMEL_US_CSR); |
1e6c9c28 AV |
439 | |
440 | /* | |
441 | * The control signals are active low. | |
442 | */ | |
7192f92c | 443 | if (!(status & ATMEL_US_DCD)) |
1e6c9c28 | 444 | ret |= TIOCM_CD; |
7192f92c | 445 | if (!(status & ATMEL_US_CTS)) |
1e6c9c28 | 446 | ret |= TIOCM_CTS; |
7192f92c | 447 | if (!(status & ATMEL_US_DSR)) |
1e6c9c28 | 448 | ret |= TIOCM_DSR; |
7192f92c | 449 | if (!(status & ATMEL_US_RI)) |
1e6c9c28 AV |
450 | ret |= TIOCM_RI; |
451 | ||
e0b0baad | 452 | return mctrl_gpio_get(atmel_port->gpios, &ret); |
1e6c9c28 AV |
453 | } |
454 | ||
455 | /* | |
456 | * Stop transmitting. | |
457 | */ | |
7192f92c | 458 | static void atmel_stop_tx(struct uart_port *port) |
1e6c9c28 | 459 | { |
e8faff73 CS |
460 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
461 | ||
64e22ebe | 462 | if (atmel_use_pdc_tx(port)) { |
a6670615 | 463 | /* disable PDC transmit */ |
4e7decda | 464 | atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); |
e8faff73 CS |
465 | } |
466 | /* Disable interrupts */ | |
4e7decda | 467 | atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask); |
e8faff73 | 468 | |
13bd3e6f RRD |
469 | if ((port->rs485.flags & SER_RS485_ENABLED) && |
470 | !(port->rs485.flags & SER_RS485_RX_DURING_TX)) | |
e8faff73 | 471 | atmel_start_rx(port); |
1e6c9c28 AV |
472 | } |
473 | ||
474 | /* | |
475 | * Start transmitting. | |
476 | */ | |
7192f92c | 477 | static void atmel_start_tx(struct uart_port *port) |
1e6c9c28 | 478 | { |
e8faff73 CS |
479 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
480 | ||
64e22ebe | 481 | if (atmel_use_pdc_tx(port)) { |
4e7decda | 482 | if (atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN) |
a6670615 CC |
483 | /* The transmitter is already running. Yes, we |
484 | really need this.*/ | |
485 | return; | |
486 | ||
13bd3e6f RRD |
487 | if ((port->rs485.flags & SER_RS485_ENABLED) && |
488 | !(port->rs485.flags & SER_RS485_RX_DURING_TX)) | |
e8faff73 CS |
489 | atmel_stop_rx(port); |
490 | ||
a6670615 | 491 | /* re-enable PDC transmit */ |
4e7decda | 492 | atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); |
e8faff73 CS |
493 | } |
494 | /* Enable interrupts */ | |
4e7decda | 495 | atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask); |
e8faff73 CS |
496 | } |
497 | ||
498 | /* | |
499 | * start receiving - port is in process of being opened. | |
500 | */ | |
501 | static void atmel_start_rx(struct uart_port *port) | |
502 | { | |
4e7decda CP |
503 | /* reset status and receiver */ |
504 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); | |
e8faff73 | 505 | |
4e7decda | 506 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN); |
57c36868 | 507 | |
64e22ebe | 508 | if (atmel_use_pdc_rx(port)) { |
e8faff73 | 509 | /* enable PDC controller */ |
4e7decda CP |
510 | atmel_uart_writel(port, ATMEL_US_IER, |
511 | ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | | |
512 | port->read_status_mask); | |
513 | atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); | |
e8faff73 | 514 | } else { |
4e7decda | 515 | atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY); |
e8faff73 | 516 | } |
1e6c9c28 AV |
517 | } |
518 | ||
519 | /* | |
520 | * Stop receiving - port is in process of being closed. | |
521 | */ | |
7192f92c | 522 | static void atmel_stop_rx(struct uart_port *port) |
1e6c9c28 | 523 | { |
4e7decda | 524 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS); |
57c36868 | 525 | |
64e22ebe | 526 | if (atmel_use_pdc_rx(port)) { |
a6670615 | 527 | /* disable PDC receive */ |
4e7decda CP |
528 | atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS); |
529 | atmel_uart_writel(port, ATMEL_US_IDR, | |
530 | ATMEL_US_ENDRX | ATMEL_US_TIMEOUT | | |
531 | port->read_status_mask); | |
e8faff73 | 532 | } else { |
4e7decda | 533 | atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY); |
e8faff73 | 534 | } |
1e6c9c28 AV |
535 | } |
536 | ||
537 | /* | |
538 | * Enable modem status interrupts | |
539 | */ | |
7192f92c | 540 | static void atmel_enable_ms(struct uart_port *port) |
1e6c9c28 | 541 | { |
ab5e4e41 RG |
542 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
543 | uint32_t ier = 0; | |
544 | ||
545 | /* | |
546 | * Interrupt should not be enabled twice | |
547 | */ | |
548 | if (atmel_port->ms_irq_enabled) | |
549 | return; | |
550 | ||
551 | atmel_port->ms_irq_enabled = true; | |
552 | ||
553 | if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0) | |
554 | enable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]); | |
555 | else | |
556 | ier |= ATMEL_US_CTSIC; | |
557 | ||
558 | if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0) | |
559 | enable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]); | |
560 | else | |
561 | ier |= ATMEL_US_DSRIC; | |
562 | ||
563 | if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0) | |
564 | enable_irq(atmel_port->gpio_irq[UART_GPIO_RI]); | |
565 | else | |
566 | ier |= ATMEL_US_RIIC; | |
567 | ||
568 | if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0) | |
569 | enable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]); | |
570 | else | |
571 | ier |= ATMEL_US_DCDIC; | |
572 | ||
4e7decda | 573 | atmel_uart_writel(port, ATMEL_US_IER, ier); |
1e6c9c28 AV |
574 | } |
575 | ||
35b675b9 RG |
576 | /* |
577 | * Disable modem status interrupts | |
578 | */ | |
579 | static void atmel_disable_ms(struct uart_port *port) | |
580 | { | |
581 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
582 | uint32_t idr = 0; | |
583 | ||
584 | /* | |
585 | * Interrupt should not be disabled twice | |
586 | */ | |
587 | if (!atmel_port->ms_irq_enabled) | |
588 | return; | |
589 | ||
590 | atmel_port->ms_irq_enabled = false; | |
591 | ||
592 | if (atmel_port->gpio_irq[UART_GPIO_CTS] >= 0) | |
593 | disable_irq(atmel_port->gpio_irq[UART_GPIO_CTS]); | |
594 | else | |
595 | idr |= ATMEL_US_CTSIC; | |
596 | ||
597 | if (atmel_port->gpio_irq[UART_GPIO_DSR] >= 0) | |
598 | disable_irq(atmel_port->gpio_irq[UART_GPIO_DSR]); | |
599 | else | |
600 | idr |= ATMEL_US_DSRIC; | |
601 | ||
602 | if (atmel_port->gpio_irq[UART_GPIO_RI] >= 0) | |
603 | disable_irq(atmel_port->gpio_irq[UART_GPIO_RI]); | |
604 | else | |
605 | idr |= ATMEL_US_RIIC; | |
606 | ||
607 | if (atmel_port->gpio_irq[UART_GPIO_DCD] >= 0) | |
608 | disable_irq(atmel_port->gpio_irq[UART_GPIO_DCD]); | |
609 | else | |
610 | idr |= ATMEL_US_DCDIC; | |
611 | ||
4e7decda | 612 | atmel_uart_writel(port, ATMEL_US_IDR, idr); |
35b675b9 RG |
613 | } |
614 | ||
1e6c9c28 AV |
615 | /* |
616 | * Control the transmission of a break signal | |
617 | */ | |
7192f92c | 618 | static void atmel_break_ctl(struct uart_port *port, int break_state) |
1e6c9c28 AV |
619 | { |
620 | if (break_state != 0) | |
4e7decda CP |
621 | /* start break */ |
622 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK); | |
1e6c9c28 | 623 | else |
4e7decda CP |
624 | /* stop break */ |
625 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK); | |
1e6c9c28 AV |
626 | } |
627 | ||
1ecc26bd RB |
628 | /* |
629 | * Stores the incoming character in the ring buffer | |
630 | */ | |
631 | static void | |
632 | atmel_buffer_rx_char(struct uart_port *port, unsigned int status, | |
633 | unsigned int ch) | |
634 | { | |
c811ab8c | 635 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
636 | struct circ_buf *ring = &atmel_port->rx_ring; |
637 | struct atmel_uart_char *c; | |
638 | ||
639 | if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE)) | |
640 | /* Buffer overflow, ignore char */ | |
641 | return; | |
642 | ||
643 | c = &((struct atmel_uart_char *)ring->buf)[ring->head]; | |
644 | c->status = status; | |
645 | c->ch = ch; | |
646 | ||
647 | /* Make sure the character is stored before we update head. */ | |
648 | smp_wmb(); | |
649 | ||
650 | ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1); | |
651 | } | |
652 | ||
a6670615 CC |
653 | /* |
654 | * Deal with parity, framing and overrun errors. | |
655 | */ | |
656 | static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status) | |
657 | { | |
658 | /* clear error */ | |
4e7decda | 659 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); |
a6670615 CC |
660 | |
661 | if (status & ATMEL_US_RXBRK) { | |
662 | /* ignore side-effect */ | |
663 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
664 | port->icount.brk++; | |
665 | } | |
666 | if (status & ATMEL_US_PARE) | |
667 | port->icount.parity++; | |
668 | if (status & ATMEL_US_FRAME) | |
669 | port->icount.frame++; | |
670 | if (status & ATMEL_US_OVRE) | |
671 | port->icount.overrun++; | |
672 | } | |
673 | ||
1e6c9c28 AV |
674 | /* |
675 | * Characters received (called from interrupt handler) | |
676 | */ | |
7d12e780 | 677 | static void atmel_rx_chars(struct uart_port *port) |
1e6c9c28 | 678 | { |
c811ab8c | 679 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 680 | unsigned int status, ch; |
1e6c9c28 | 681 | |
4e7decda | 682 | status = atmel_uart_readl(port, ATMEL_US_CSR); |
7192f92c | 683 | while (status & ATMEL_US_RXRDY) { |
a6499435 | 684 | ch = atmel_uart_read_char(port); |
1e6c9c28 | 685 | |
1e6c9c28 AV |
686 | /* |
687 | * note that the error handling code is | |
688 | * out of the main execution path | |
689 | */ | |
9e6077bd HS |
690 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME |
691 | | ATMEL_US_OVRE | ATMEL_US_RXBRK) | |
692 | || atmel_port->break_active)) { | |
1ecc26bd | 693 | |
b843aa21 | 694 | /* clear error */ |
4e7decda | 695 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); |
1ecc26bd | 696 | |
9e6077bd HS |
697 | if (status & ATMEL_US_RXBRK |
698 | && !atmel_port->break_active) { | |
9e6077bd | 699 | atmel_port->break_active = 1; |
4e7decda CP |
700 | atmel_uart_writel(port, ATMEL_US_IER, |
701 | ATMEL_US_RXBRK); | |
9e6077bd HS |
702 | } else { |
703 | /* | |
704 | * This is either the end-of-break | |
705 | * condition or we've received at | |
706 | * least one character without RXBRK | |
707 | * being set. In both cases, the next | |
708 | * RXBRK will indicate start-of-break. | |
709 | */ | |
4e7decda CP |
710 | atmel_uart_writel(port, ATMEL_US_IDR, |
711 | ATMEL_US_RXBRK); | |
9e6077bd HS |
712 | status &= ~ATMEL_US_RXBRK; |
713 | atmel_port->break_active = 0; | |
afefc415 | 714 | } |
1e6c9c28 AV |
715 | } |
716 | ||
1ecc26bd | 717 | atmel_buffer_rx_char(port, status, ch); |
4e7decda | 718 | status = atmel_uart_readl(port, ATMEL_US_CSR); |
1e6c9c28 AV |
719 | } |
720 | ||
1ecc26bd | 721 | tasklet_schedule(&atmel_port->tasklet); |
1e6c9c28 AV |
722 | } |
723 | ||
724 | /* | |
1ecc26bd RB |
725 | * Transmit characters (called from tasklet with TXRDY interrupt |
726 | * disabled) | |
1e6c9c28 | 727 | */ |
7192f92c | 728 | static void atmel_tx_chars(struct uart_port *port) |
1e6c9c28 | 729 | { |
ebd2c8f6 | 730 | struct circ_buf *xmit = &port->state->xmit; |
e8faff73 | 731 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1e6c9c28 | 732 | |
4e7decda CP |
733 | if (port->x_char && |
734 | (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) { | |
a6499435 | 735 | atmel_uart_write_char(port, port->x_char); |
1e6c9c28 AV |
736 | port->icount.tx++; |
737 | port->x_char = 0; | |
1e6c9c28 | 738 | } |
1ecc26bd | 739 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) |
1e6c9c28 | 740 | return; |
1e6c9c28 | 741 | |
4e7decda CP |
742 | while (atmel_uart_readl(port, ATMEL_US_CSR) & |
743 | atmel_port->tx_done_mask) { | |
a6499435 | 744 | atmel_uart_write_char(port, xmit->buf[xmit->tail]); |
1e6c9c28 AV |
745 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
746 | port->icount.tx++; | |
747 | if (uart_circ_empty(xmit)) | |
748 | break; | |
749 | } | |
750 | ||
751 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
752 | uart_write_wakeup(port); | |
753 | ||
1ecc26bd | 754 | if (!uart_circ_empty(xmit)) |
e8faff73 | 755 | /* Enable interrupts */ |
4e7decda CP |
756 | atmel_uart_writel(port, ATMEL_US_IER, |
757 | atmel_port->tx_done_mask); | |
1e6c9c28 AV |
758 | } |
759 | ||
08f738be ES |
760 | static void atmel_complete_tx_dma(void *arg) |
761 | { | |
762 | struct atmel_uart_port *atmel_port = arg; | |
763 | struct uart_port *port = &atmel_port->uart; | |
764 | struct circ_buf *xmit = &port->state->xmit; | |
765 | struct dma_chan *chan = atmel_port->chan_tx; | |
766 | unsigned long flags; | |
767 | ||
768 | spin_lock_irqsave(&port->lock, flags); | |
769 | ||
770 | if (chan) | |
771 | dmaengine_terminate_all(chan); | |
5f258b3e | 772 | xmit->tail += atmel_port->tx_len; |
08f738be ES |
773 | xmit->tail &= UART_XMIT_SIZE - 1; |
774 | ||
5f258b3e | 775 | port->icount.tx += atmel_port->tx_len; |
08f738be ES |
776 | |
777 | spin_lock_irq(&atmel_port->lock_tx); | |
778 | async_tx_ack(atmel_port->desc_tx); | |
779 | atmel_port->cookie_tx = -EINVAL; | |
780 | atmel_port->desc_tx = NULL; | |
781 | spin_unlock_irq(&atmel_port->lock_tx); | |
782 | ||
783 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
784 | uart_write_wakeup(port); | |
785 | ||
1842dc2e CP |
786 | /* |
787 | * xmit is a circular buffer so, if we have just send data from | |
788 | * xmit->tail to the end of xmit->buf, now we have to transmit the | |
789 | * remaining data from the beginning of xmit->buf to xmit->head. | |
790 | */ | |
08f738be ES |
791 | if (!uart_circ_empty(xmit)) |
792 | tasklet_schedule(&atmel_port->tasklet); | |
793 | ||
794 | spin_unlock_irqrestore(&port->lock, flags); | |
795 | } | |
796 | ||
797 | static void atmel_release_tx_dma(struct uart_port *port) | |
798 | { | |
799 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
800 | struct dma_chan *chan = atmel_port->chan_tx; | |
801 | ||
802 | if (chan) { | |
803 | dmaengine_terminate_all(chan); | |
804 | dma_release_channel(chan); | |
805 | dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1, | |
48479148 | 806 | DMA_TO_DEVICE); |
08f738be ES |
807 | } |
808 | ||
809 | atmel_port->desc_tx = NULL; | |
810 | atmel_port->chan_tx = NULL; | |
811 | atmel_port->cookie_tx = -EINVAL; | |
812 | } | |
813 | ||
814 | /* | |
815 | * Called from tasklet with TXRDY interrupt is disabled. | |
816 | */ | |
817 | static void atmel_tx_dma(struct uart_port *port) | |
818 | { | |
819 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
820 | struct circ_buf *xmit = &port->state->xmit; | |
821 | struct dma_chan *chan = atmel_port->chan_tx; | |
822 | struct dma_async_tx_descriptor *desc; | |
5f258b3e CP |
823 | struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx; |
824 | unsigned int tx_len, part1_len, part2_len, sg_len; | |
825 | dma_addr_t phys_addr; | |
08f738be ES |
826 | |
827 | /* Make sure we have an idle channel */ | |
828 | if (atmel_port->desc_tx != NULL) | |
829 | return; | |
830 | ||
831 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { | |
832 | /* | |
833 | * DMA is idle now. | |
834 | * Port xmit buffer is already mapped, | |
835 | * and it is one page... Just adjust | |
836 | * offsets and lengths. Since it is a circular buffer, | |
837 | * we have to transmit till the end, and then the rest. | |
838 | * Take the port lock to get a | |
839 | * consistent xmit buffer state. | |
840 | */ | |
5f258b3e CP |
841 | tx_len = CIRC_CNT_TO_END(xmit->head, |
842 | xmit->tail, | |
843 | UART_XMIT_SIZE); | |
844 | ||
845 | if (atmel_port->fifo_size) { | |
846 | /* multi data mode */ | |
847 | part1_len = (tx_len & ~0x3); /* DWORD access */ | |
848 | part2_len = (tx_len & 0x3); /* BYTE access */ | |
849 | } else { | |
850 | /* single data (legacy) mode */ | |
851 | part1_len = 0; | |
852 | part2_len = tx_len; /* BYTE access only */ | |
853 | } | |
854 | ||
855 | sg_init_table(sgl, 2); | |
856 | sg_len = 0; | |
857 | phys_addr = sg_dma_address(sg_tx) + xmit->tail; | |
858 | if (part1_len) { | |
859 | sg = &sgl[sg_len++]; | |
860 | sg_dma_address(sg) = phys_addr; | |
861 | sg_dma_len(sg) = part1_len; | |
862 | ||
863 | phys_addr += part1_len; | |
864 | } | |
865 | ||
866 | if (part2_len) { | |
867 | sg = &sgl[sg_len++]; | |
868 | sg_dma_address(sg) = phys_addr; | |
869 | sg_dma_len(sg) = part2_len; | |
870 | } | |
871 | ||
872 | /* | |
873 | * save tx_len so atmel_complete_tx_dma() will increase | |
874 | * xmit->tail correctly | |
875 | */ | |
876 | atmel_port->tx_len = tx_len; | |
08f738be ES |
877 | |
878 | desc = dmaengine_prep_slave_sg(chan, | |
5f258b3e CP |
879 | sgl, |
880 | sg_len, | |
1842dc2e CP |
881 | DMA_MEM_TO_DEV, |
882 | DMA_PREP_INTERRUPT | | |
883 | DMA_CTRL_ACK); | |
08f738be ES |
884 | if (!desc) { |
885 | dev_err(port->dev, "Failed to send via dma!\n"); | |
886 | return; | |
887 | } | |
888 | ||
5f258b3e | 889 | dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE); |
08f738be ES |
890 | |
891 | atmel_port->desc_tx = desc; | |
892 | desc->callback = atmel_complete_tx_dma; | |
893 | desc->callback_param = atmel_port; | |
894 | atmel_port->cookie_tx = dmaengine_submit(desc); | |
895 | ||
896 | } else { | |
13bd3e6f | 897 | if (port->rs485.flags & SER_RS485_ENABLED) { |
08f738be ES |
898 | /* DMA done, stop TX, start RX for RS485 */ |
899 | atmel_start_rx(port); | |
900 | } | |
901 | } | |
902 | ||
903 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
904 | uart_write_wakeup(port); | |
905 | } | |
906 | ||
907 | static int atmel_prepare_tx_dma(struct uart_port *port) | |
908 | { | |
909 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
910 | dma_cap_mask_t mask; | |
911 | struct dma_slave_config config; | |
912 | int ret, nent; | |
913 | ||
914 | dma_cap_zero(mask); | |
915 | dma_cap_set(DMA_SLAVE, mask); | |
916 | ||
917 | atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx"); | |
918 | if (atmel_port->chan_tx == NULL) | |
919 | goto chan_err; | |
920 | dev_info(port->dev, "using %s for tx DMA transfers\n", | |
921 | dma_chan_name(atmel_port->chan_tx)); | |
922 | ||
923 | spin_lock_init(&atmel_port->lock_tx); | |
924 | sg_init_table(&atmel_port->sg_tx, 1); | |
925 | /* UART circular tx buffer is an aligned page. */ | |
2c277054 | 926 | BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf)); |
08f738be ES |
927 | sg_set_page(&atmel_port->sg_tx, |
928 | virt_to_page(port->state->xmit.buf), | |
929 | UART_XMIT_SIZE, | |
930 | (int)port->state->xmit.buf & ~PAGE_MASK); | |
931 | nent = dma_map_sg(port->dev, | |
932 | &atmel_port->sg_tx, | |
933 | 1, | |
48479148 | 934 | DMA_TO_DEVICE); |
08f738be ES |
935 | |
936 | if (!nent) { | |
937 | dev_dbg(port->dev, "need to release resource of dma\n"); | |
938 | goto chan_err; | |
939 | } else { | |
940 | dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, | |
941 | sg_dma_len(&atmel_port->sg_tx), | |
942 | port->state->xmit.buf, | |
943 | sg_dma_address(&atmel_port->sg_tx)); | |
944 | } | |
945 | ||
946 | /* Configure the slave DMA */ | |
947 | memset(&config, 0, sizeof(config)); | |
948 | config.direction = DMA_MEM_TO_DEV; | |
5f258b3e CP |
949 | config.dst_addr_width = (atmel_port->fifo_size) ? |
950 | DMA_SLAVE_BUSWIDTH_4_BYTES : | |
951 | DMA_SLAVE_BUSWIDTH_1_BYTE; | |
08f738be | 952 | config.dst_addr = port->mapbase + ATMEL_US_THR; |
a8d4e016 | 953 | config.dst_maxburst = 1; |
08f738be | 954 | |
5483c10e MR |
955 | ret = dmaengine_slave_config(atmel_port->chan_tx, |
956 | &config); | |
08f738be ES |
957 | if (ret) { |
958 | dev_err(port->dev, "DMA tx slave configuration failed\n"); | |
959 | goto chan_err; | |
960 | } | |
961 | ||
962 | return 0; | |
963 | ||
964 | chan_err: | |
965 | dev_err(port->dev, "TX channel not available, switch to pio\n"); | |
966 | atmel_port->use_dma_tx = 0; | |
967 | if (atmel_port->chan_tx) | |
968 | atmel_release_tx_dma(port); | |
969 | return -EINVAL; | |
970 | } | |
971 | ||
34df42f5 ES |
972 | static void atmel_complete_rx_dma(void *arg) |
973 | { | |
974 | struct uart_port *port = arg; | |
975 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
976 | ||
977 | tasklet_schedule(&atmel_port->tasklet); | |
978 | } | |
979 | ||
980 | static void atmel_release_rx_dma(struct uart_port *port) | |
981 | { | |
982 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
983 | struct dma_chan *chan = atmel_port->chan_rx; | |
984 | ||
985 | if (chan) { | |
986 | dmaengine_terminate_all(chan); | |
987 | dma_release_channel(chan); | |
988 | dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1, | |
48479148 | 989 | DMA_FROM_DEVICE); |
34df42f5 ES |
990 | } |
991 | ||
992 | atmel_port->desc_rx = NULL; | |
993 | atmel_port->chan_rx = NULL; | |
994 | atmel_port->cookie_rx = -EINVAL; | |
995 | } | |
996 | ||
997 | static void atmel_rx_from_dma(struct uart_port *port) | |
998 | { | |
999 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
66f37aaf | 1000 | struct tty_port *tport = &port->state->port; |
34df42f5 ES |
1001 | struct circ_buf *ring = &atmel_port->rx_ring; |
1002 | struct dma_chan *chan = atmel_port->chan_rx; | |
1003 | struct dma_tx_state state; | |
1004 | enum dma_status dmastat; | |
66f37aaf | 1005 | size_t count; |
34df42f5 ES |
1006 | |
1007 | ||
1008 | /* Reset the UART timeout early so that we don't miss one */ | |
4e7decda | 1009 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); |
34df42f5 ES |
1010 | dmastat = dmaengine_tx_status(chan, |
1011 | atmel_port->cookie_rx, | |
1012 | &state); | |
1013 | /* Restart a new tasklet if DMA status is error */ | |
1014 | if (dmastat == DMA_ERROR) { | |
1015 | dev_dbg(port->dev, "Get residue error, restart tasklet\n"); | |
4e7decda | 1016 | atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT); |
34df42f5 ES |
1017 | tasklet_schedule(&atmel_port->tasklet); |
1018 | return; | |
1019 | } | |
34df42f5 | 1020 | |
66f37aaf CP |
1021 | /* CPU claims ownership of RX DMA buffer */ |
1022 | dma_sync_sg_for_cpu(port->dev, | |
1023 | &atmel_port->sg_rx, | |
1024 | 1, | |
485819b5 | 1025 | DMA_FROM_DEVICE); |
66f37aaf CP |
1026 | |
1027 | /* | |
1028 | * ring->head points to the end of data already written by the DMA. | |
1029 | * ring->tail points to the beginning of data to be read by the | |
1030 | * framework. | |
1031 | * The current transfer size should not be larger than the dma buffer | |
1032 | * length. | |
1033 | */ | |
1034 | ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue; | |
1035 | BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx)); | |
34df42f5 | 1036 | /* |
66f37aaf CP |
1037 | * At this point ring->head may point to the first byte right after the |
1038 | * last byte of the dma buffer: | |
1039 | * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx) | |
1040 | * | |
1041 | * However ring->tail must always points inside the dma buffer: | |
1042 | * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1 | |
1043 | * | |
1044 | * Since we use a ring buffer, we have to handle the case | |
1045 | * where head is lower than tail. In such a case, we first read from | |
1046 | * tail to the end of the buffer then reset tail. | |
34df42f5 | 1047 | */ |
66f37aaf CP |
1048 | if (ring->head < ring->tail) { |
1049 | count = sg_dma_len(&atmel_port->sg_rx) - ring->tail; | |
34df42f5 | 1050 | |
66f37aaf CP |
1051 | tty_insert_flip_string(tport, ring->buf + ring->tail, count); |
1052 | ring->tail = 0; | |
1053 | port->icount.rx += count; | |
1054 | } | |
34df42f5 | 1055 | |
66f37aaf CP |
1056 | /* Finally we read data from tail to head */ |
1057 | if (ring->tail < ring->head) { | |
1058 | count = ring->head - ring->tail; | |
34df42f5 | 1059 | |
66f37aaf CP |
1060 | tty_insert_flip_string(tport, ring->buf + ring->tail, count); |
1061 | /* Wrap ring->head if needed */ | |
1062 | if (ring->head >= sg_dma_len(&atmel_port->sg_rx)) | |
1063 | ring->head = 0; | |
1064 | ring->tail = ring->head; | |
34df42f5 ES |
1065 | port->icount.rx += count; |
1066 | } | |
1067 | ||
66f37aaf CP |
1068 | /* USART retreives ownership of RX DMA buffer */ |
1069 | dma_sync_sg_for_device(port->dev, | |
1070 | &atmel_port->sg_rx, | |
1071 | 1, | |
485819b5 | 1072 | DMA_FROM_DEVICE); |
66f37aaf CP |
1073 | |
1074 | /* | |
1075 | * Drop the lock here since it might end up calling | |
1076 | * uart_start(), which takes the lock. | |
1077 | */ | |
1078 | spin_unlock(&port->lock); | |
1079 | tty_flip_buffer_push(tport); | |
1080 | spin_lock(&port->lock); | |
1081 | ||
4e7decda | 1082 | atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT); |
34df42f5 ES |
1083 | } |
1084 | ||
1085 | static int atmel_prepare_rx_dma(struct uart_port *port) | |
1086 | { | |
1087 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1088 | struct dma_async_tx_descriptor *desc; | |
1089 | dma_cap_mask_t mask; | |
1090 | struct dma_slave_config config; | |
1091 | struct circ_buf *ring; | |
1092 | int ret, nent; | |
1093 | ||
1094 | ring = &atmel_port->rx_ring; | |
1095 | ||
1096 | dma_cap_zero(mask); | |
1097 | dma_cap_set(DMA_CYCLIC, mask); | |
1098 | ||
1099 | atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx"); | |
1100 | if (atmel_port->chan_rx == NULL) | |
1101 | goto chan_err; | |
1102 | dev_info(port->dev, "using %s for rx DMA transfers\n", | |
1103 | dma_chan_name(atmel_port->chan_rx)); | |
1104 | ||
1105 | spin_lock_init(&atmel_port->lock_rx); | |
1106 | sg_init_table(&atmel_port->sg_rx, 1); | |
1107 | /* UART circular rx buffer is an aligned page. */ | |
2c277054 | 1108 | BUG_ON(!PAGE_ALIGNED(ring->buf)); |
34df42f5 | 1109 | sg_set_page(&atmel_port->sg_rx, |
1842dc2e | 1110 | virt_to_page(ring->buf), |
a510880f | 1111 | sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE, |
1842dc2e CP |
1112 | (int)ring->buf & ~PAGE_MASK); |
1113 | nent = dma_map_sg(port->dev, | |
1114 | &atmel_port->sg_rx, | |
1115 | 1, | |
1116 | DMA_FROM_DEVICE); | |
34df42f5 ES |
1117 | |
1118 | if (!nent) { | |
1119 | dev_dbg(port->dev, "need to release resource of dma\n"); | |
1120 | goto chan_err; | |
1121 | } else { | |
1122 | dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__, | |
1123 | sg_dma_len(&atmel_port->sg_rx), | |
1124 | ring->buf, | |
1125 | sg_dma_address(&atmel_port->sg_rx)); | |
1126 | } | |
1127 | ||
1128 | /* Configure the slave DMA */ | |
1129 | memset(&config, 0, sizeof(config)); | |
1130 | config.direction = DMA_DEV_TO_MEM; | |
1131 | config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
1132 | config.src_addr = port->mapbase + ATMEL_US_RHR; | |
a8d4e016 | 1133 | config.src_maxburst = 1; |
34df42f5 | 1134 | |
5483c10e MR |
1135 | ret = dmaengine_slave_config(atmel_port->chan_rx, |
1136 | &config); | |
34df42f5 ES |
1137 | if (ret) { |
1138 | dev_err(port->dev, "DMA rx slave configuration failed\n"); | |
1139 | goto chan_err; | |
1140 | } | |
1141 | /* | |
1142 | * Prepare a cyclic dma transfer, assign 2 descriptors, | |
1143 | * each one is half ring buffer size | |
1144 | */ | |
1145 | desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx, | |
1842dc2e CP |
1146 | sg_dma_address(&atmel_port->sg_rx), |
1147 | sg_dma_len(&atmel_port->sg_rx), | |
1148 | sg_dma_len(&atmel_port->sg_rx)/2, | |
1149 | DMA_DEV_TO_MEM, | |
1150 | DMA_PREP_INTERRUPT); | |
34df42f5 ES |
1151 | desc->callback = atmel_complete_rx_dma; |
1152 | desc->callback_param = port; | |
1153 | atmel_port->desc_rx = desc; | |
1154 | atmel_port->cookie_rx = dmaengine_submit(desc); | |
1155 | ||
1156 | return 0; | |
1157 | ||
1158 | chan_err: | |
1159 | dev_err(port->dev, "RX channel not available, switch to pio\n"); | |
1160 | atmel_port->use_dma_rx = 0; | |
1161 | if (atmel_port->chan_rx) | |
1162 | atmel_release_rx_dma(port); | |
1163 | return -EINVAL; | |
1164 | } | |
1165 | ||
2e68c22f ES |
1166 | static void atmel_uart_timer_callback(unsigned long data) |
1167 | { | |
1168 | struct uart_port *port = (void *)data; | |
1169 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1170 | ||
1171 | tasklet_schedule(&atmel_port->tasklet); | |
1172 | mod_timer(&atmel_port->uart_timer, jiffies + uart_poll_timeout(port)); | |
1173 | } | |
1174 | ||
b843aa21 RB |
1175 | /* |
1176 | * receive interrupt handler. | |
1177 | */ | |
1178 | static void | |
1179 | atmel_handle_receive(struct uart_port *port, unsigned int pending) | |
1180 | { | |
c811ab8c | 1181 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
b843aa21 | 1182 | |
64e22ebe | 1183 | if (atmel_use_pdc_rx(port)) { |
a6670615 CC |
1184 | /* |
1185 | * PDC receive. Just schedule the tasklet and let it | |
1186 | * figure out the details. | |
1187 | * | |
1188 | * TODO: We're not handling error flags correctly at | |
1189 | * the moment. | |
1190 | */ | |
1191 | if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) { | |
4e7decda CP |
1192 | atmel_uart_writel(port, ATMEL_US_IDR, |
1193 | (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)); | |
a6670615 CC |
1194 | tasklet_schedule(&atmel_port->tasklet); |
1195 | } | |
1196 | ||
1197 | if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE | | |
1198 | ATMEL_US_FRAME | ATMEL_US_PARE)) | |
1199 | atmel_pdc_rxerr(port, pending); | |
1200 | } | |
1201 | ||
34df42f5 ES |
1202 | if (atmel_use_dma_rx(port)) { |
1203 | if (pending & ATMEL_US_TIMEOUT) { | |
4e7decda CP |
1204 | atmel_uart_writel(port, ATMEL_US_IDR, |
1205 | ATMEL_US_TIMEOUT); | |
34df42f5 ES |
1206 | tasklet_schedule(&atmel_port->tasklet); |
1207 | } | |
1208 | } | |
1209 | ||
b843aa21 RB |
1210 | /* Interrupt receive */ |
1211 | if (pending & ATMEL_US_RXRDY) | |
1212 | atmel_rx_chars(port); | |
1213 | else if (pending & ATMEL_US_RXBRK) { | |
1214 | /* | |
1215 | * End of break detected. If it came along with a | |
1216 | * character, atmel_rx_chars will handle it. | |
1217 | */ | |
4e7decda CP |
1218 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); |
1219 | atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK); | |
b843aa21 RB |
1220 | atmel_port->break_active = 0; |
1221 | } | |
1222 | } | |
1223 | ||
1224 | /* | |
1ecc26bd | 1225 | * transmit interrupt handler. (Transmit is IRQF_NODELAY safe) |
b843aa21 RB |
1226 | */ |
1227 | static void | |
1228 | atmel_handle_transmit(struct uart_port *port, unsigned int pending) | |
1229 | { | |
c811ab8c | 1230 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 1231 | |
e8faff73 CS |
1232 | if (pending & atmel_port->tx_done_mask) { |
1233 | /* Either PDC or interrupt transmission */ | |
4e7decda CP |
1234 | atmel_uart_writel(port, ATMEL_US_IDR, |
1235 | atmel_port->tx_done_mask); | |
e8faff73 | 1236 | tasklet_schedule(&atmel_port->tasklet); |
1ecc26bd | 1237 | } |
b843aa21 RB |
1238 | } |
1239 | ||
1240 | /* | |
1241 | * status flags interrupt handler. | |
1242 | */ | |
1243 | static void | |
1244 | atmel_handle_status(struct uart_port *port, unsigned int pending, | |
1245 | unsigned int status) | |
1246 | { | |
c811ab8c | 1247 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd | 1248 | |
b843aa21 | 1249 | if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC |
1ecc26bd RB |
1250 | | ATMEL_US_CTSIC)) { |
1251 | atmel_port->irq_status = status; | |
d033e82d LZ |
1252 | atmel_port->status_change = atmel_port->irq_status ^ |
1253 | atmel_port->irq_status_prev; | |
1254 | atmel_port->irq_status_prev = status; | |
1ecc26bd RB |
1255 | tasklet_schedule(&atmel_port->tasklet); |
1256 | } | |
b843aa21 RB |
1257 | } |
1258 | ||
1e6c9c28 AV |
1259 | /* |
1260 | * Interrupt handler | |
1261 | */ | |
7d12e780 | 1262 | static irqreturn_t atmel_interrupt(int irq, void *dev_id) |
1e6c9c28 AV |
1263 | { |
1264 | struct uart_port *port = dev_id; | |
ab5e4e41 | 1265 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
2c7af5ba | 1266 | unsigned int status, pending, mask, pass_counter = 0; |
ab5e4e41 | 1267 | bool gpio_handled = false; |
1e6c9c28 | 1268 | |
2c7af5ba BB |
1269 | spin_lock(&atmel_port->lock_suspended); |
1270 | ||
a6670615 | 1271 | do { |
e0b0baad | 1272 | status = atmel_get_lines_status(port); |
4e7decda | 1273 | mask = atmel_uart_readl(port, ATMEL_US_IMR); |
2c7af5ba | 1274 | pending = status & mask; |
ab5e4e41 RG |
1275 | if (!gpio_handled) { |
1276 | /* | |
1277 | * Dealing with GPIO interrupt | |
1278 | */ | |
1279 | if (irq == atmel_port->gpio_irq[UART_GPIO_CTS]) | |
1280 | pending |= ATMEL_US_CTSIC; | |
1281 | ||
1282 | if (irq == atmel_port->gpio_irq[UART_GPIO_DSR]) | |
1283 | pending |= ATMEL_US_DSRIC; | |
1284 | ||
1285 | if (irq == atmel_port->gpio_irq[UART_GPIO_RI]) | |
1286 | pending |= ATMEL_US_RIIC; | |
1287 | ||
1288 | if (irq == atmel_port->gpio_irq[UART_GPIO_DCD]) | |
1289 | pending |= ATMEL_US_DCDIC; | |
1290 | ||
1291 | gpio_handled = true; | |
1292 | } | |
a6670615 CC |
1293 | if (!pending) |
1294 | break; | |
1295 | ||
2c7af5ba BB |
1296 | if (atmel_port->suspended) { |
1297 | atmel_port->pending |= pending; | |
1298 | atmel_port->pending_status = status; | |
4e7decda | 1299 | atmel_uart_writel(port, ATMEL_US_IDR, mask); |
2c7af5ba BB |
1300 | pm_system_wakeup(); |
1301 | break; | |
1302 | } | |
1303 | ||
b843aa21 RB |
1304 | atmel_handle_receive(port, pending); |
1305 | atmel_handle_status(port, pending, status); | |
1306 | atmel_handle_transmit(port, pending); | |
a6670615 | 1307 | } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT); |
afefc415 | 1308 | |
2c7af5ba BB |
1309 | spin_unlock(&atmel_port->lock_suspended); |
1310 | ||
0400b697 | 1311 | return pass_counter ? IRQ_HANDLED : IRQ_NONE; |
a6670615 | 1312 | } |
1e6c9c28 | 1313 | |
a930e528 ES |
1314 | static void atmel_release_tx_pdc(struct uart_port *port) |
1315 | { | |
1316 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1317 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
1318 | ||
1319 | dma_unmap_single(port->dev, | |
1320 | pdc->dma_addr, | |
1321 | pdc->dma_size, | |
1322 | DMA_TO_DEVICE); | |
1323 | } | |
1324 | ||
a6670615 CC |
1325 | /* |
1326 | * Called from tasklet with ENDTX and TXBUFE interrupts disabled. | |
1327 | */ | |
64e22ebe | 1328 | static void atmel_tx_pdc(struct uart_port *port) |
a6670615 | 1329 | { |
c811ab8c | 1330 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
ebd2c8f6 | 1331 | struct circ_buf *xmit = &port->state->xmit; |
a6670615 CC |
1332 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; |
1333 | int count; | |
1334 | ||
ba0657ff | 1335 | /* nothing left to transmit? */ |
4e7decda | 1336 | if (atmel_uart_readl(port, ATMEL_PDC_TCR)) |
ba0657ff MT |
1337 | return; |
1338 | ||
a6670615 CC |
1339 | xmit->tail += pdc->ofs; |
1340 | xmit->tail &= UART_XMIT_SIZE - 1; | |
1341 | ||
1342 | port->icount.tx += pdc->ofs; | |
1343 | pdc->ofs = 0; | |
1344 | ||
ba0657ff | 1345 | /* more to transmit - setup next transfer */ |
a6670615 | 1346 | |
ba0657ff | 1347 | /* disable PDC transmit */ |
4e7decda | 1348 | atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); |
ba0657ff | 1349 | |
1f14081d | 1350 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) { |
a6670615 CC |
1351 | dma_sync_single_for_device(port->dev, |
1352 | pdc->dma_addr, | |
1353 | pdc->dma_size, | |
1354 | DMA_TO_DEVICE); | |
1355 | ||
1356 | count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); | |
1357 | pdc->ofs = count; | |
1358 | ||
4e7decda CP |
1359 | atmel_uart_writel(port, ATMEL_PDC_TPR, |
1360 | pdc->dma_addr + xmit->tail); | |
1361 | atmel_uart_writel(port, ATMEL_PDC_TCR, count); | |
e8faff73 | 1362 | /* re-enable PDC transmit */ |
4e7decda | 1363 | atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); |
e8faff73 | 1364 | /* Enable interrupts */ |
4e7decda CP |
1365 | atmel_uart_writel(port, ATMEL_US_IER, |
1366 | atmel_port->tx_done_mask); | |
e8faff73 | 1367 | } else { |
13bd3e6f RRD |
1368 | if ((port->rs485.flags & SER_RS485_ENABLED) && |
1369 | !(port->rs485.flags & SER_RS485_RX_DURING_TX)) { | |
e8faff73 CS |
1370 | /* DMA done, stop TX, start RX for RS485 */ |
1371 | atmel_start_rx(port); | |
1372 | } | |
1e6c9c28 | 1373 | } |
a6670615 CC |
1374 | |
1375 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1376 | uart_write_wakeup(port); | |
1e6c9c28 AV |
1377 | } |
1378 | ||
a930e528 ES |
1379 | static int atmel_prepare_tx_pdc(struct uart_port *port) |
1380 | { | |
1381 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1382 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx; | |
1383 | struct circ_buf *xmit = &port->state->xmit; | |
1384 | ||
1385 | pdc->buf = xmit->buf; | |
1386 | pdc->dma_addr = dma_map_single(port->dev, | |
1387 | pdc->buf, | |
1388 | UART_XMIT_SIZE, | |
1389 | DMA_TO_DEVICE); | |
1390 | pdc->dma_size = UART_XMIT_SIZE; | |
1391 | pdc->ofs = 0; | |
1392 | ||
1393 | return 0; | |
1394 | } | |
1395 | ||
1ecc26bd RB |
1396 | static void atmel_rx_from_ring(struct uart_port *port) |
1397 | { | |
c811ab8c | 1398 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
1ecc26bd RB |
1399 | struct circ_buf *ring = &atmel_port->rx_ring; |
1400 | unsigned int flg; | |
1401 | unsigned int status; | |
1402 | ||
1403 | while (ring->head != ring->tail) { | |
1404 | struct atmel_uart_char c; | |
1405 | ||
1406 | /* Make sure c is loaded after head. */ | |
1407 | smp_rmb(); | |
1408 | ||
1409 | c = ((struct atmel_uart_char *)ring->buf)[ring->tail]; | |
1410 | ||
1411 | ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1); | |
1412 | ||
1413 | port->icount.rx++; | |
1414 | status = c.status; | |
1415 | flg = TTY_NORMAL; | |
1416 | ||
1417 | /* | |
1418 | * note that the error handling code is | |
1419 | * out of the main execution path | |
1420 | */ | |
1421 | if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME | |
1422 | | ATMEL_US_OVRE | ATMEL_US_RXBRK))) { | |
1423 | if (status & ATMEL_US_RXBRK) { | |
1424 | /* ignore side-effect */ | |
1425 | status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME); | |
1426 | ||
1427 | port->icount.brk++; | |
1428 | if (uart_handle_break(port)) | |
1429 | continue; | |
1430 | } | |
1431 | if (status & ATMEL_US_PARE) | |
1432 | port->icount.parity++; | |
1433 | if (status & ATMEL_US_FRAME) | |
1434 | port->icount.frame++; | |
1435 | if (status & ATMEL_US_OVRE) | |
1436 | port->icount.overrun++; | |
1437 | ||
1438 | status &= port->read_status_mask; | |
1439 | ||
1440 | if (status & ATMEL_US_RXBRK) | |
1441 | flg = TTY_BREAK; | |
1442 | else if (status & ATMEL_US_PARE) | |
1443 | flg = TTY_PARITY; | |
1444 | else if (status & ATMEL_US_FRAME) | |
1445 | flg = TTY_FRAME; | |
1446 | } | |
1447 | ||
1448 | ||
1449 | if (uart_handle_sysrq_char(port, c.ch)) | |
1450 | continue; | |
1451 | ||
1452 | uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg); | |
1453 | } | |
1454 | ||
1455 | /* | |
1456 | * Drop the lock here since it might end up calling | |
1457 | * uart_start(), which takes the lock. | |
1458 | */ | |
1459 | spin_unlock(&port->lock); | |
2e124b4a | 1460 | tty_flip_buffer_push(&port->state->port); |
1ecc26bd RB |
1461 | spin_lock(&port->lock); |
1462 | } | |
1463 | ||
a930e528 ES |
1464 | static void atmel_release_rx_pdc(struct uart_port *port) |
1465 | { | |
1466 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1467 | int i; | |
1468 | ||
1469 | for (i = 0; i < 2; i++) { | |
1470 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; | |
1471 | ||
1472 | dma_unmap_single(port->dev, | |
1473 | pdc->dma_addr, | |
1474 | pdc->dma_size, | |
1475 | DMA_FROM_DEVICE); | |
1476 | kfree(pdc->buf); | |
1477 | } | |
1478 | } | |
1479 | ||
64e22ebe | 1480 | static void atmel_rx_from_pdc(struct uart_port *port) |
a6670615 | 1481 | { |
c811ab8c | 1482 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
05c7cd39 | 1483 | struct tty_port *tport = &port->state->port; |
a6670615 CC |
1484 | struct atmel_dma_buffer *pdc; |
1485 | int rx_idx = atmel_port->pdc_rx_idx; | |
1486 | unsigned int head; | |
1487 | unsigned int tail; | |
1488 | unsigned int count; | |
1489 | ||
1490 | do { | |
1491 | /* Reset the UART timeout early so that we don't miss one */ | |
4e7decda | 1492 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); |
a6670615 CC |
1493 | |
1494 | pdc = &atmel_port->pdc_rx[rx_idx]; | |
4e7decda | 1495 | head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr; |
a6670615 CC |
1496 | tail = pdc->ofs; |
1497 | ||
1498 | /* If the PDC has switched buffers, RPR won't contain | |
1499 | * any address within the current buffer. Since head | |
1500 | * is unsigned, we just need a one-way comparison to | |
1501 | * find out. | |
1502 | * | |
1503 | * In this case, we just need to consume the entire | |
1504 | * buffer and resubmit it for DMA. This will clear the | |
1505 | * ENDRX bit as well, so that we can safely re-enable | |
1506 | * all interrupts below. | |
1507 | */ | |
1508 | head = min(head, pdc->dma_size); | |
1509 | ||
1510 | if (likely(head != tail)) { | |
1511 | dma_sync_single_for_cpu(port->dev, pdc->dma_addr, | |
1512 | pdc->dma_size, DMA_FROM_DEVICE); | |
1513 | ||
1514 | /* | |
1515 | * head will only wrap around when we recycle | |
1516 | * the DMA buffer, and when that happens, we | |
1517 | * explicitly set tail to 0. So head will | |
1518 | * always be greater than tail. | |
1519 | */ | |
1520 | count = head - tail; | |
1521 | ||
05c7cd39 JS |
1522 | tty_insert_flip_string(tport, pdc->buf + pdc->ofs, |
1523 | count); | |
a6670615 CC |
1524 | |
1525 | dma_sync_single_for_device(port->dev, pdc->dma_addr, | |
1526 | pdc->dma_size, DMA_FROM_DEVICE); | |
1527 | ||
1528 | port->icount.rx += count; | |
1529 | pdc->ofs = head; | |
1530 | } | |
1531 | ||
1532 | /* | |
1533 | * If the current buffer is full, we need to check if | |
1534 | * the next one contains any additional data. | |
1535 | */ | |
1536 | if (head >= pdc->dma_size) { | |
1537 | pdc->ofs = 0; | |
4e7decda CP |
1538 | atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr); |
1539 | atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size); | |
a6670615 CC |
1540 | |
1541 | rx_idx = !rx_idx; | |
1542 | atmel_port->pdc_rx_idx = rx_idx; | |
1543 | } | |
1544 | } while (head >= pdc->dma_size); | |
1545 | ||
1546 | /* | |
1547 | * Drop the lock here since it might end up calling | |
1548 | * uart_start(), which takes the lock. | |
1549 | */ | |
1550 | spin_unlock(&port->lock); | |
2e124b4a | 1551 | tty_flip_buffer_push(tport); |
a6670615 CC |
1552 | spin_lock(&port->lock); |
1553 | ||
4e7decda CP |
1554 | atmel_uart_writel(port, ATMEL_US_IER, |
1555 | ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); | |
a6670615 CC |
1556 | } |
1557 | ||
a930e528 ES |
1558 | static int atmel_prepare_rx_pdc(struct uart_port *port) |
1559 | { | |
1560 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1561 | int i; | |
1562 | ||
1563 | for (i = 0; i < 2; i++) { | |
1564 | struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i]; | |
1565 | ||
1566 | pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL); | |
1567 | if (pdc->buf == NULL) { | |
1568 | if (i != 0) { | |
1569 | dma_unmap_single(port->dev, | |
1570 | atmel_port->pdc_rx[0].dma_addr, | |
1571 | PDC_BUFFER_SIZE, | |
1572 | DMA_FROM_DEVICE); | |
1573 | kfree(atmel_port->pdc_rx[0].buf); | |
1574 | } | |
1575 | atmel_port->use_pdc_rx = 0; | |
1576 | return -ENOMEM; | |
1577 | } | |
1578 | pdc->dma_addr = dma_map_single(port->dev, | |
1579 | pdc->buf, | |
1580 | PDC_BUFFER_SIZE, | |
1581 | DMA_FROM_DEVICE); | |
1582 | pdc->dma_size = PDC_BUFFER_SIZE; | |
1583 | pdc->ofs = 0; | |
1584 | } | |
1585 | ||
1586 | atmel_port->pdc_rx_idx = 0; | |
1587 | ||
4e7decda CP |
1588 | atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr); |
1589 | atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE); | |
a930e528 | 1590 | |
4e7decda CP |
1591 | atmel_uart_writel(port, ATMEL_PDC_RNPR, |
1592 | atmel_port->pdc_rx[1].dma_addr); | |
1593 | atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE); | |
a930e528 ES |
1594 | |
1595 | return 0; | |
1596 | } | |
1597 | ||
1ecc26bd RB |
1598 | /* |
1599 | * tasklet handling tty stuff outside the interrupt handler. | |
1600 | */ | |
1601 | static void atmel_tasklet_func(unsigned long data) | |
1602 | { | |
1603 | struct uart_port *port = (struct uart_port *)data; | |
c811ab8c | 1604 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
d033e82d LZ |
1605 | unsigned int status = atmel_port->irq_status; |
1606 | unsigned int status_change = atmel_port->status_change; | |
1ecc26bd RB |
1607 | |
1608 | /* The interrupt handler does not take the lock */ | |
1609 | spin_lock(&port->lock); | |
1610 | ||
a930e528 | 1611 | atmel_port->schedule_tx(port); |
1ecc26bd | 1612 | |
1ecc26bd RB |
1613 | if (status_change & (ATMEL_US_RI | ATMEL_US_DSR |
1614 | | ATMEL_US_DCD | ATMEL_US_CTS)) { | |
1615 | /* TODO: All reads to CSR will clear these interrupts! */ | |
1616 | if (status_change & ATMEL_US_RI) | |
1617 | port->icount.rng++; | |
1618 | if (status_change & ATMEL_US_DSR) | |
1619 | port->icount.dsr++; | |
1620 | if (status_change & ATMEL_US_DCD) | |
1621 | uart_handle_dcd_change(port, !(status & ATMEL_US_DCD)); | |
1622 | if (status_change & ATMEL_US_CTS) | |
1623 | uart_handle_cts_change(port, !(status & ATMEL_US_CTS)); | |
1624 | ||
bdc04e31 | 1625 | wake_up_interruptible(&port->state->port.delta_msr_wait); |
1ecc26bd | 1626 | |
d033e82d | 1627 | atmel_port->status_change = 0; |
1ecc26bd RB |
1628 | } |
1629 | ||
a930e528 | 1630 | atmel_port->schedule_rx(port); |
1ecc26bd RB |
1631 | |
1632 | spin_unlock(&port->lock); | |
1633 | } | |
1634 | ||
4a1e8888 | 1635 | static void atmel_init_property(struct atmel_uart_port *atmel_port, |
33d64c4f ES |
1636 | struct platform_device *pdev) |
1637 | { | |
1638 | struct device_node *np = pdev->dev.of_node; | |
574de559 | 1639 | struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); |
33d64c4f ES |
1640 | |
1641 | if (np) { | |
1642 | /* DMA/PDC usage specification */ | |
1643 | if (of_get_property(np, "atmel,use-dma-rx", NULL)) { | |
1644 | if (of_get_property(np, "dmas", NULL)) { | |
1645 | atmel_port->use_dma_rx = true; | |
1646 | atmel_port->use_pdc_rx = false; | |
1647 | } else { | |
1648 | atmel_port->use_dma_rx = false; | |
1649 | atmel_port->use_pdc_rx = true; | |
1650 | } | |
1651 | } else { | |
1652 | atmel_port->use_dma_rx = false; | |
1653 | atmel_port->use_pdc_rx = false; | |
1654 | } | |
1655 | ||
1656 | if (of_get_property(np, "atmel,use-dma-tx", NULL)) { | |
1657 | if (of_get_property(np, "dmas", NULL)) { | |
1658 | atmel_port->use_dma_tx = true; | |
1659 | atmel_port->use_pdc_tx = false; | |
1660 | } else { | |
1661 | atmel_port->use_dma_tx = false; | |
1662 | atmel_port->use_pdc_tx = true; | |
1663 | } | |
1664 | } else { | |
1665 | atmel_port->use_dma_tx = false; | |
1666 | atmel_port->use_pdc_tx = false; | |
1667 | } | |
1668 | ||
1669 | } else { | |
1670 | atmel_port->use_pdc_rx = pdata->use_dma_rx; | |
1671 | atmel_port->use_pdc_tx = pdata->use_dma_tx; | |
1672 | atmel_port->use_dma_rx = false; | |
1673 | atmel_port->use_dma_tx = false; | |
1674 | } | |
1675 | ||
33d64c4f ES |
1676 | } |
1677 | ||
13bd3e6f | 1678 | static void atmel_init_rs485(struct uart_port *port, |
33d64c4f ES |
1679 | struct platform_device *pdev) |
1680 | { | |
1681 | struct device_node *np = pdev->dev.of_node; | |
574de559 | 1682 | struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); |
33d64c4f ES |
1683 | |
1684 | if (np) { | |
1685 | u32 rs485_delay[2]; | |
1686 | /* rs485 properties */ | |
1687 | if (of_property_read_u32_array(np, "rs485-rts-delay", | |
1688 | rs485_delay, 2) == 0) { | |
13bd3e6f | 1689 | struct serial_rs485 *rs485conf = &port->rs485; |
33d64c4f ES |
1690 | |
1691 | rs485conf->delay_rts_before_send = rs485_delay[0]; | |
1692 | rs485conf->delay_rts_after_send = rs485_delay[1]; | |
1693 | rs485conf->flags = 0; | |
1694 | ||
1695 | if (of_get_property(np, "rs485-rx-during-tx", NULL)) | |
1696 | rs485conf->flags |= SER_RS485_RX_DURING_TX; | |
1697 | ||
1698 | if (of_get_property(np, "linux,rs485-enabled-at-boot-time", | |
1699 | NULL)) | |
1700 | rs485conf->flags |= SER_RS485_ENABLED; | |
1701 | } | |
1702 | } else { | |
13bd3e6f | 1703 | port->rs485 = pdata->rs485; |
33d64c4f ES |
1704 | } |
1705 | ||
1706 | } | |
1707 | ||
a930e528 ES |
1708 | static void atmel_set_ops(struct uart_port *port) |
1709 | { | |
1710 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1711 | ||
34df42f5 ES |
1712 | if (atmel_use_dma_rx(port)) { |
1713 | atmel_port->prepare_rx = &atmel_prepare_rx_dma; | |
1714 | atmel_port->schedule_rx = &atmel_rx_from_dma; | |
1715 | atmel_port->release_rx = &atmel_release_rx_dma; | |
1716 | } else if (atmel_use_pdc_rx(port)) { | |
a930e528 ES |
1717 | atmel_port->prepare_rx = &atmel_prepare_rx_pdc; |
1718 | atmel_port->schedule_rx = &atmel_rx_from_pdc; | |
1719 | atmel_port->release_rx = &atmel_release_rx_pdc; | |
1720 | } else { | |
1721 | atmel_port->prepare_rx = NULL; | |
1722 | atmel_port->schedule_rx = &atmel_rx_from_ring; | |
1723 | atmel_port->release_rx = NULL; | |
1724 | } | |
1725 | ||
08f738be ES |
1726 | if (atmel_use_dma_tx(port)) { |
1727 | atmel_port->prepare_tx = &atmel_prepare_tx_dma; | |
1728 | atmel_port->schedule_tx = &atmel_tx_dma; | |
1729 | atmel_port->release_tx = &atmel_release_tx_dma; | |
1730 | } else if (atmel_use_pdc_tx(port)) { | |
a930e528 ES |
1731 | atmel_port->prepare_tx = &atmel_prepare_tx_pdc; |
1732 | atmel_port->schedule_tx = &atmel_tx_pdc; | |
1733 | atmel_port->release_tx = &atmel_release_tx_pdc; | |
1734 | } else { | |
1735 | atmel_port->prepare_tx = NULL; | |
1736 | atmel_port->schedule_tx = &atmel_tx_chars; | |
1737 | atmel_port->release_tx = NULL; | |
1738 | } | |
1739 | } | |
1740 | ||
055560b0 ES |
1741 | /* |
1742 | * Get ip name usart or uart | |
1743 | */ | |
892db58b | 1744 | static void atmel_get_ip_name(struct uart_port *port) |
055560b0 ES |
1745 | { |
1746 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
4e7decda | 1747 | int name = atmel_uart_readl(port, ATMEL_US_NAME); |
731d9cae | 1748 | u32 version; |
055560b0 ES |
1749 | int usart, uart; |
1750 | /* usart and uart ascii */ | |
1751 | usart = 0x55534152; | |
1752 | uart = 0x44424755; | |
1753 | ||
1754 | atmel_port->is_usart = false; | |
1755 | ||
1756 | if (name == usart) { | |
1757 | dev_dbg(port->dev, "This is usart\n"); | |
1758 | atmel_port->is_usart = true; | |
1759 | } else if (name == uart) { | |
1760 | dev_dbg(port->dev, "This is uart\n"); | |
1761 | atmel_port->is_usart = false; | |
1762 | } else { | |
731d9cae | 1763 | /* fallback for older SoCs: use version field */ |
4e7decda | 1764 | version = atmel_uart_readl(port, ATMEL_US_VERSION); |
731d9cae NF |
1765 | switch (version) { |
1766 | case 0x302: | |
1767 | case 0x10213: | |
1768 | dev_dbg(port->dev, "This version is usart\n"); | |
1769 | atmel_port->is_usart = true; | |
1770 | break; | |
1771 | case 0x203: | |
1772 | case 0x10202: | |
1773 | dev_dbg(port->dev, "This version is uart\n"); | |
1774 | atmel_port->is_usart = false; | |
1775 | break; | |
1776 | default: | |
1777 | dev_err(port->dev, "Not supported ip name nor version, set to uart\n"); | |
1778 | } | |
055560b0 | 1779 | } |
055560b0 ES |
1780 | } |
1781 | ||
ab5e4e41 RG |
1782 | static void atmel_free_gpio_irq(struct uart_port *port) |
1783 | { | |
1784 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1785 | enum mctrl_gpio_idx i; | |
1786 | ||
1787 | for (i = 0; i < UART_GPIO_MAX; i++) | |
1788 | if (atmel_port->gpio_irq[i] >= 0) | |
1789 | free_irq(atmel_port->gpio_irq[i], port); | |
1790 | } | |
1791 | ||
1792 | static int atmel_request_gpio_irq(struct uart_port *port) | |
1793 | { | |
1794 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1795 | int *irq = atmel_port->gpio_irq; | |
1796 | enum mctrl_gpio_idx i; | |
1797 | int err = 0; | |
1798 | ||
1799 | for (i = 0; (i < UART_GPIO_MAX) && !err; i++) { | |
1800 | if (irq[i] < 0) | |
1801 | continue; | |
1802 | ||
1803 | irq_set_status_flags(irq[i], IRQ_NOAUTOEN); | |
1804 | err = request_irq(irq[i], atmel_interrupt, IRQ_TYPE_EDGE_BOTH, | |
1805 | "atmel_serial", port); | |
1806 | if (err) | |
1807 | dev_err(port->dev, "atmel_startup - Can't get %d irq\n", | |
1808 | irq[i]); | |
1809 | } | |
1810 | ||
1811 | /* | |
1812 | * If something went wrong, rollback. | |
1813 | */ | |
1814 | while (err && (--i >= 0)) | |
1815 | if (irq[i] >= 0) | |
1816 | free_irq(irq[i], port); | |
1817 | ||
1818 | return err; | |
1819 | } | |
1820 | ||
1e6c9c28 AV |
1821 | /* |
1822 | * Perform initialization and enable port for reception | |
1823 | */ | |
7192f92c | 1824 | static int atmel_startup(struct uart_port *port) |
1e6c9c28 | 1825 | { |
33d64c4f | 1826 | struct platform_device *pdev = to_platform_device(port->dev); |
c811ab8c | 1827 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
ebd2c8f6 | 1828 | struct tty_struct *tty = port->state->port.tty; |
1e6c9c28 AV |
1829 | int retval; |
1830 | ||
1831 | /* | |
1832 | * Ensure that no interrupts are enabled otherwise when | |
1833 | * request_irq() is called we could get stuck trying to | |
1834 | * handle an unexpected interrupt | |
1835 | */ | |
4e7decda | 1836 | atmel_uart_writel(port, ATMEL_US_IDR, -1); |
ab5e4e41 | 1837 | atmel_port->ms_irq_enabled = false; |
1e6c9c28 AV |
1838 | |
1839 | /* | |
1840 | * Allocate the IRQ | |
1841 | */ | |
2c7af5ba BB |
1842 | retval = request_irq(port->irq, atmel_interrupt, |
1843 | IRQF_SHARED | IRQF_COND_SUSPEND, | |
ae161068 | 1844 | tty ? tty->name : "atmel_serial", port); |
1e6c9c28 | 1845 | if (retval) { |
ddaa6037 | 1846 | dev_err(port->dev, "atmel_startup - Can't get irq\n"); |
1e6c9c28 AV |
1847 | return retval; |
1848 | } | |
1849 | ||
ab5e4e41 RG |
1850 | /* |
1851 | * Get the GPIO lines IRQ | |
1852 | */ | |
1853 | retval = atmel_request_gpio_irq(port); | |
1854 | if (retval) | |
1855 | goto free_irq; | |
1856 | ||
1e125786 LZ |
1857 | tasklet_enable(&atmel_port->tasklet); |
1858 | ||
a6670615 CC |
1859 | /* |
1860 | * Initialize DMA (if necessary) | |
1861 | */ | |
33d64c4f | 1862 | atmel_init_property(atmel_port, pdev); |
4d9628a1 | 1863 | atmel_set_ops(port); |
33d64c4f | 1864 | |
a930e528 ES |
1865 | if (atmel_port->prepare_rx) { |
1866 | retval = atmel_port->prepare_rx(port); | |
1867 | if (retval < 0) | |
1868 | atmel_set_ops(port); | |
a6670615 | 1869 | } |
a6670615 | 1870 | |
a930e528 ES |
1871 | if (atmel_port->prepare_tx) { |
1872 | retval = atmel_port->prepare_tx(port); | |
1873 | if (retval < 0) | |
1874 | atmel_set_ops(port); | |
a6670615 | 1875 | } |
1e6c9c28 | 1876 | |
b5199d46 CP |
1877 | /* |
1878 | * Enable FIFO when available | |
1879 | */ | |
1880 | if (atmel_port->fifo_size) { | |
1881 | unsigned int txrdym = ATMEL_US_ONE_DATA; | |
1882 | unsigned int rxrdym = ATMEL_US_ONE_DATA; | |
1883 | unsigned int fmr; | |
1884 | ||
1885 | atmel_uart_writel(port, ATMEL_US_CR, | |
1886 | ATMEL_US_FIFOEN | | |
1887 | ATMEL_US_RXFCLR | | |
1888 | ATMEL_US_TXFLCLR); | |
1889 | ||
5f258b3e CP |
1890 | if (atmel_use_dma_tx(port)) |
1891 | txrdym = ATMEL_US_FOUR_DATA; | |
1892 | ||
b5199d46 CP |
1893 | fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym); |
1894 | if (atmel_port->rts_high && | |
1895 | atmel_port->rts_low) | |
1896 | fmr |= ATMEL_US_FRTSC | | |
1897 | ATMEL_US_RXFTHRES(atmel_port->rts_high) | | |
1898 | ATMEL_US_RXFTHRES2(atmel_port->rts_low); | |
1899 | ||
1900 | atmel_uart_writel(port, ATMEL_US_FMR, fmr); | |
1901 | } | |
1902 | ||
27c0c8e5 | 1903 | /* Save current CSR for comparison in atmel_tasklet_func() */ |
e0b0baad | 1904 | atmel_port->irq_status_prev = atmel_get_lines_status(port); |
27c0c8e5 AN |
1905 | atmel_port->irq_status = atmel_port->irq_status_prev; |
1906 | ||
1e6c9c28 AV |
1907 | /* |
1908 | * Finally, enable the serial port | |
1909 | */ | |
4e7decda | 1910 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); |
b843aa21 | 1911 | /* enable xmit & rcvr */ |
4e7decda | 1912 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); |
afefc415 | 1913 | |
8bc661bf MR |
1914 | setup_timer(&atmel_port->uart_timer, |
1915 | atmel_uart_timer_callback, | |
1916 | (unsigned long)port); | |
1917 | ||
64e22ebe | 1918 | if (atmel_use_pdc_rx(port)) { |
a6670615 | 1919 | /* set UART timeout */ |
2e68c22f | 1920 | if (!atmel_port->is_usart) { |
2e68c22f ES |
1921 | mod_timer(&atmel_port->uart_timer, |
1922 | jiffies + uart_poll_timeout(port)); | |
1923 | /* set USART timeout */ | |
1924 | } else { | |
4e7decda CP |
1925 | atmel_uart_writel(port, ATMEL_US_RTOR, PDC_RX_TIMEOUT); |
1926 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); | |
a6670615 | 1927 | |
4e7decda CP |
1928 | atmel_uart_writel(port, ATMEL_US_IER, |
1929 | ATMEL_US_ENDRX | ATMEL_US_TIMEOUT); | |
2e68c22f | 1930 | } |
a6670615 | 1931 | /* enable PDC controller */ |
4e7decda | 1932 | atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN); |
34df42f5 | 1933 | } else if (atmel_use_dma_rx(port)) { |
2e68c22f ES |
1934 | /* set UART timeout */ |
1935 | if (!atmel_port->is_usart) { | |
2e68c22f ES |
1936 | mod_timer(&atmel_port->uart_timer, |
1937 | jiffies + uart_poll_timeout(port)); | |
1938 | /* set USART timeout */ | |
1939 | } else { | |
4e7decda CP |
1940 | atmel_uart_writel(port, ATMEL_US_RTOR, PDC_RX_TIMEOUT); |
1941 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO); | |
34df42f5 | 1942 | |
4e7decda CP |
1943 | atmel_uart_writel(port, ATMEL_US_IER, |
1944 | ATMEL_US_TIMEOUT); | |
2e68c22f | 1945 | } |
a6670615 CC |
1946 | } else { |
1947 | /* enable receive only */ | |
4e7decda | 1948 | atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY); |
a6670615 | 1949 | } |
afefc415 | 1950 | |
1e6c9c28 | 1951 | return 0; |
ab5e4e41 RG |
1952 | |
1953 | free_irq: | |
1954 | free_irq(port->irq, port); | |
1955 | ||
1956 | return retval; | |
1e6c9c28 AV |
1957 | } |
1958 | ||
479e9b94 PH |
1959 | /* |
1960 | * Flush any TX data submitted for DMA. Called when the TX circular | |
1961 | * buffer is reset. | |
1962 | */ | |
1963 | static void atmel_flush_buffer(struct uart_port *port) | |
1964 | { | |
1965 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); | |
1966 | ||
1967 | if (atmel_use_pdc_tx(port)) { | |
4e7decda | 1968 | atmel_uart_writel(port, ATMEL_PDC_TCR, 0); |
479e9b94 PH |
1969 | atmel_port->pdc_tx.ofs = 0; |
1970 | } | |
1971 | } | |
1972 | ||
1e6c9c28 AV |
1973 | /* |
1974 | * Disable the port | |
1975 | */ | |
7192f92c | 1976 | static void atmel_shutdown(struct uart_port *port) |
1e6c9c28 | 1977 | { |
c811ab8c | 1978 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
0cc7c6c7 | 1979 | |
8bc661bf MR |
1980 | /* |
1981 | * Prevent any tasklets being scheduled during | |
1982 | * cleanup | |
1983 | */ | |
1984 | del_timer_sync(&atmel_port->uart_timer); | |
1985 | ||
0cc7c6c7 MR |
1986 | /* |
1987 | * Clear out any scheduled tasklets before | |
1988 | * we destroy the buffers | |
1989 | */ | |
1e125786 | 1990 | tasklet_disable(&atmel_port->tasklet); |
0cc7c6c7 MR |
1991 | tasklet_kill(&atmel_port->tasklet); |
1992 | ||
a6670615 | 1993 | /* |
0cc7c6c7 MR |
1994 | * Ensure everything is stopped and |
1995 | * disable all interrupts, port and break condition. | |
a6670615 CC |
1996 | */ |
1997 | atmel_stop_rx(port); | |
1998 | atmel_stop_tx(port); | |
1999 | ||
4e7decda CP |
2000 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA); |
2001 | atmel_uart_writel(port, ATMEL_US_IDR, -1); | |
0cc7c6c7 MR |
2002 | |
2003 | ||
a6670615 CC |
2004 | /* |
2005 | * Shut-down the DMA. | |
2006 | */ | |
a930e528 ES |
2007 | if (atmel_port->release_rx) |
2008 | atmel_port->release_rx(port); | |
2009 | if (atmel_port->release_tx) | |
2010 | atmel_port->release_tx(port); | |
a6670615 | 2011 | |
bb7e73c5 MD |
2012 | /* |
2013 | * Reset ring buffer pointers | |
2014 | */ | |
2015 | atmel_port->rx_ring.head = 0; | |
2016 | atmel_port->rx_ring.tail = 0; | |
2017 | ||
1e6c9c28 | 2018 | /* |
ab5e4e41 | 2019 | * Free the interrupts |
1e6c9c28 AV |
2020 | */ |
2021 | free_irq(port->irq, port); | |
ab5e4e41 RG |
2022 | atmel_free_gpio_irq(port); |
2023 | ||
2024 | atmel_port->ms_irq_enabled = false; | |
1e6c9c28 | 2025 | |
479e9b94 | 2026 | atmel_flush_buffer(port); |
9afd561a HS |
2027 | } |
2028 | ||
1e6c9c28 AV |
2029 | /* |
2030 | * Power / Clock management. | |
2031 | */ | |
b843aa21 RB |
2032 | static void atmel_serial_pm(struct uart_port *port, unsigned int state, |
2033 | unsigned int oldstate) | |
1e6c9c28 | 2034 | { |
c811ab8c | 2035 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 | 2036 | |
1e6c9c28 | 2037 | switch (state) { |
b843aa21 RB |
2038 | case 0: |
2039 | /* | |
2040 | * Enable the peripheral clock for this serial port. | |
2041 | * This is called on uart_open() or a resume event. | |
2042 | */ | |
91f8c2d8 | 2043 | clk_prepare_enable(atmel_port->clk); |
f05596db AS |
2044 | |
2045 | /* re-enable interrupts if we disabled some on suspend */ | |
4e7decda | 2046 | atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr); |
b843aa21 RB |
2047 | break; |
2048 | case 3: | |
f05596db | 2049 | /* Back up the interrupt mask and disable all interrupts */ |
4e7decda CP |
2050 | atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR); |
2051 | atmel_uart_writel(port, ATMEL_US_IDR, -1); | |
f05596db | 2052 | |
b843aa21 RB |
2053 | /* |
2054 | * Disable the peripheral clock for this serial port. | |
2055 | * This is called on uart_close() or a suspend event. | |
2056 | */ | |
91f8c2d8 | 2057 | clk_disable_unprepare(atmel_port->clk); |
b843aa21 RB |
2058 | break; |
2059 | default: | |
ddaa6037 | 2060 | dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); |
1e6c9c28 AV |
2061 | } |
2062 | } | |
2063 | ||
2064 | /* | |
2065 | * Change the port parameters | |
2066 | */ | |
b843aa21 RB |
2067 | static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, |
2068 | struct ktermios *old) | |
1e6c9c28 AV |
2069 | { |
2070 | unsigned long flags; | |
1cf6e8fc CP |
2071 | unsigned int old_mode, mode, imr, quot, baud; |
2072 | ||
2073 | /* save the current mode register */ | |
4e7decda | 2074 | mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR); |
1e6c9c28 | 2075 | |
1cf6e8fc CP |
2076 | /* reset the mode, clock divisor, parity, stop bits and data size */ |
2077 | mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | | |
2078 | ATMEL_US_PAR | ATMEL_US_USMODE); | |
03abeac0 | 2079 | |
b843aa21 | 2080 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); |
1e6c9c28 AV |
2081 | quot = uart_get_divisor(port, baud); |
2082 | ||
b843aa21 | 2083 | if (quot > 65535) { /* BRGR is 16-bit, so switch to slower clock */ |
03abeac0 AV |
2084 | quot /= 8; |
2085 | mode |= ATMEL_US_USCLKS_MCK_DIV8; | |
2086 | } | |
1e6c9c28 AV |
2087 | |
2088 | /* byte size */ | |
2089 | switch (termios->c_cflag & CSIZE) { | |
2090 | case CS5: | |
7192f92c | 2091 | mode |= ATMEL_US_CHRL_5; |
1e6c9c28 AV |
2092 | break; |
2093 | case CS6: | |
7192f92c | 2094 | mode |= ATMEL_US_CHRL_6; |
1e6c9c28 AV |
2095 | break; |
2096 | case CS7: | |
7192f92c | 2097 | mode |= ATMEL_US_CHRL_7; |
1e6c9c28 AV |
2098 | break; |
2099 | default: | |
7192f92c | 2100 | mode |= ATMEL_US_CHRL_8; |
1e6c9c28 AV |
2101 | break; |
2102 | } | |
2103 | ||
2104 | /* stop bits */ | |
2105 | if (termios->c_cflag & CSTOPB) | |
7192f92c | 2106 | mode |= ATMEL_US_NBSTOP_2; |
1e6c9c28 AV |
2107 | |
2108 | /* parity */ | |
2109 | if (termios->c_cflag & PARENB) { | |
b843aa21 RB |
2110 | /* Mark or Space parity */ |
2111 | if (termios->c_cflag & CMSPAR) { | |
1e6c9c28 | 2112 | if (termios->c_cflag & PARODD) |
7192f92c | 2113 | mode |= ATMEL_US_PAR_MARK; |
1e6c9c28 | 2114 | else |
7192f92c | 2115 | mode |= ATMEL_US_PAR_SPACE; |
b843aa21 | 2116 | } else if (termios->c_cflag & PARODD) |
7192f92c | 2117 | mode |= ATMEL_US_PAR_ODD; |
1e6c9c28 | 2118 | else |
7192f92c | 2119 | mode |= ATMEL_US_PAR_EVEN; |
b843aa21 | 2120 | } else |
7192f92c | 2121 | mode |= ATMEL_US_PAR_NONE; |
1e6c9c28 AV |
2122 | |
2123 | spin_lock_irqsave(&port->lock, flags); | |
2124 | ||
7192f92c | 2125 | port->read_status_mask = ATMEL_US_OVRE; |
1e6c9c28 | 2126 | if (termios->c_iflag & INPCK) |
7192f92c | 2127 | port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
ef8b9ddc | 2128 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
7192f92c | 2129 | port->read_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 | 2130 | |
64e22ebe | 2131 | if (atmel_use_pdc_rx(port)) |
a6670615 | 2132 | /* need to enable error interrupts */ |
4e7decda | 2133 | atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask); |
a6670615 | 2134 | |
1e6c9c28 AV |
2135 | /* |
2136 | * Characters to ignore | |
2137 | */ | |
2138 | port->ignore_status_mask = 0; | |
2139 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 2140 | port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE); |
1e6c9c28 | 2141 | if (termios->c_iflag & IGNBRK) { |
7192f92c | 2142 | port->ignore_status_mask |= ATMEL_US_RXBRK; |
1e6c9c28 AV |
2143 | /* |
2144 | * If we're ignoring parity and break indicators, | |
2145 | * ignore overruns too (for real raw support). | |
2146 | */ | |
2147 | if (termios->c_iflag & IGNPAR) | |
7192f92c | 2148 | port->ignore_status_mask |= ATMEL_US_OVRE; |
1e6c9c28 | 2149 | } |
b843aa21 | 2150 | /* TODO: Ignore all characters if CREAD is set.*/ |
1e6c9c28 AV |
2151 | |
2152 | /* update the per-port timeout */ | |
2153 | uart_update_timeout(port, termios->c_cflag, baud); | |
2154 | ||
0ccad870 HS |
2155 | /* |
2156 | * save/disable interrupts. The tty layer will ensure that the | |
2157 | * transmitter is empty if requested by the caller, so there's | |
2158 | * no need to wait for it here. | |
2159 | */ | |
4e7decda CP |
2160 | imr = atmel_uart_readl(port, ATMEL_US_IMR); |
2161 | atmel_uart_writel(port, ATMEL_US_IDR, -1); | |
1e6c9c28 AV |
2162 | |
2163 | /* disable receiver and transmitter */ | |
4e7decda | 2164 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS); |
1e6c9c28 | 2165 | |
1cf6e8fc | 2166 | /* mode */ |
13bd3e6f | 2167 | if (port->rs485.flags & SER_RS485_ENABLED) { |
4e7decda CP |
2168 | atmel_uart_writel(port, ATMEL_US_TTGR, |
2169 | port->rs485.delay_rts_after_send); | |
e8faff73 | 2170 | mode |= ATMEL_US_USMODE_RS485; |
1cf6e8fc CP |
2171 | } else if (termios->c_cflag & CRTSCTS) { |
2172 | /* RS232 with hardware handshake (RTS/CTS) */ | |
2173 | mode |= ATMEL_US_USMODE_HWHS; | |
2174 | } else { | |
2175 | /* RS232 without hadware handshake */ | |
2176 | mode |= ATMEL_US_USMODE_NORMAL; | |
e8faff73 CS |
2177 | } |
2178 | ||
1cf6e8fc | 2179 | /* set the mode, clock divisor, parity, stop bits and data size */ |
4e7decda | 2180 | atmel_uart_writel(port, ATMEL_US_MR, mode); |
1e6c9c28 | 2181 | |
1cf6e8fc CP |
2182 | /* |
2183 | * when switching the mode, set the RTS line state according to the | |
2184 | * new mode, otherwise keep the former state | |
2185 | */ | |
2186 | if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) { | |
2187 | unsigned int rts_state; | |
2188 | ||
2189 | if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) { | |
2190 | /* let the hardware control the RTS line */ | |
2191 | rts_state = ATMEL_US_RTSDIS; | |
2192 | } else { | |
2193 | /* force RTS line to low level */ | |
2194 | rts_state = ATMEL_US_RTSEN; | |
2195 | } | |
2196 | ||
4e7decda | 2197 | atmel_uart_writel(port, ATMEL_US_CR, rts_state); |
1cf6e8fc CP |
2198 | } |
2199 | ||
1e6c9c28 | 2200 | /* set the baud rate */ |
4e7decda CP |
2201 | atmel_uart_writel(port, ATMEL_US_BRGR, quot); |
2202 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); | |
2203 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
2204 | |
2205 | /* restore interrupts */ | |
4e7decda | 2206 | atmel_uart_writel(port, ATMEL_US_IER, imr); |
1e6c9c28 AV |
2207 | |
2208 | /* CTS flow-control and modem-status interrupts */ | |
2209 | if (UART_ENABLE_MS(port, termios->c_cflag)) | |
35b675b9 RG |
2210 | atmel_enable_ms(port); |
2211 | else | |
2212 | atmel_disable_ms(port); | |
1e6c9c28 AV |
2213 | |
2214 | spin_unlock_irqrestore(&port->lock, flags); | |
2215 | } | |
2216 | ||
732a84a0 | 2217 | static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios) |
42bd7a4f | 2218 | { |
732a84a0 | 2219 | if (termios->c_line == N_PPS) { |
42bd7a4f | 2220 | port->flags |= UPF_HARDPPS_CD; |
d41510ce | 2221 | spin_lock_irq(&port->lock); |
42bd7a4f | 2222 | atmel_enable_ms(port); |
d41510ce | 2223 | spin_unlock_irq(&port->lock); |
42bd7a4f VP |
2224 | } else { |
2225 | port->flags &= ~UPF_HARDPPS_CD; | |
cab68f89 PH |
2226 | if (!UART_ENABLE_MS(port, termios->c_cflag)) { |
2227 | spin_lock_irq(&port->lock); | |
2228 | atmel_disable_ms(port); | |
2229 | spin_unlock_irq(&port->lock); | |
2230 | } | |
42bd7a4f VP |
2231 | } |
2232 | } | |
2233 | ||
1e6c9c28 AV |
2234 | /* |
2235 | * Return string describing the specified port | |
2236 | */ | |
7192f92c | 2237 | static const char *atmel_type(struct uart_port *port) |
1e6c9c28 | 2238 | { |
9ab4f88b | 2239 | return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL; |
1e6c9c28 AV |
2240 | } |
2241 | ||
2242 | /* | |
2243 | * Release the memory region(s) being used by 'port'. | |
2244 | */ | |
7192f92c | 2245 | static void atmel_release_port(struct uart_port *port) |
1e6c9c28 | 2246 | { |
afefc415 AV |
2247 | struct platform_device *pdev = to_platform_device(port->dev); |
2248 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
2249 | ||
2250 | release_mem_region(port->mapbase, size); | |
2251 | ||
2252 | if (port->flags & UPF_IOREMAP) { | |
2253 | iounmap(port->membase); | |
2254 | port->membase = NULL; | |
2255 | } | |
1e6c9c28 AV |
2256 | } |
2257 | ||
2258 | /* | |
2259 | * Request the memory region(s) being used by 'port'. | |
2260 | */ | |
7192f92c | 2261 | static int atmel_request_port(struct uart_port *port) |
1e6c9c28 | 2262 | { |
afefc415 AV |
2263 | struct platform_device *pdev = to_platform_device(port->dev); |
2264 | int size = pdev->resource[0].end - pdev->resource[0].start + 1; | |
2265 | ||
7192f92c | 2266 | if (!request_mem_region(port->mapbase, size, "atmel_serial")) |
afefc415 AV |
2267 | return -EBUSY; |
2268 | ||
2269 | if (port->flags & UPF_IOREMAP) { | |
2270 | port->membase = ioremap(port->mapbase, size); | |
2271 | if (port->membase == NULL) { | |
2272 | release_mem_region(port->mapbase, size); | |
2273 | return -ENOMEM; | |
2274 | } | |
2275 | } | |
1e6c9c28 | 2276 | |
afefc415 | 2277 | return 0; |
1e6c9c28 AV |
2278 | } |
2279 | ||
2280 | /* | |
2281 | * Configure/autoconfigure the port. | |
2282 | */ | |
7192f92c | 2283 | static void atmel_config_port(struct uart_port *port, int flags) |
1e6c9c28 AV |
2284 | { |
2285 | if (flags & UART_CONFIG_TYPE) { | |
9ab4f88b | 2286 | port->type = PORT_ATMEL; |
7192f92c | 2287 | atmel_request_port(port); |
1e6c9c28 AV |
2288 | } |
2289 | } | |
2290 | ||
2291 | /* | |
2292 | * Verify the new serial_struct (for TIOCSSERIAL). | |
2293 | */ | |
7192f92c | 2294 | static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser) |
1e6c9c28 AV |
2295 | { |
2296 | int ret = 0; | |
9ab4f88b | 2297 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL) |
1e6c9c28 AV |
2298 | ret = -EINVAL; |
2299 | if (port->irq != ser->irq) | |
2300 | ret = -EINVAL; | |
2301 | if (ser->io_type != SERIAL_IO_MEM) | |
2302 | ret = -EINVAL; | |
2303 | if (port->uartclk / 16 != ser->baud_base) | |
2304 | ret = -EINVAL; | |
2305 | if ((void *)port->mapbase != ser->iomem_base) | |
2306 | ret = -EINVAL; | |
2307 | if (port->iobase != ser->port) | |
2308 | ret = -EINVAL; | |
2309 | if (ser->hub6 != 0) | |
2310 | ret = -EINVAL; | |
2311 | return ret; | |
2312 | } | |
2313 | ||
8fe2d541 AT |
2314 | #ifdef CONFIG_CONSOLE_POLL |
2315 | static int atmel_poll_get_char(struct uart_port *port) | |
2316 | { | |
4e7decda | 2317 | while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY)) |
8fe2d541 AT |
2318 | cpu_relax(); |
2319 | ||
a6499435 | 2320 | return atmel_uart_read_char(port); |
8fe2d541 AT |
2321 | } |
2322 | ||
2323 | static void atmel_poll_put_char(struct uart_port *port, unsigned char ch) | |
2324 | { | |
4e7decda | 2325 | while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) |
8fe2d541 AT |
2326 | cpu_relax(); |
2327 | ||
a6499435 | 2328 | atmel_uart_write_char(port, ch); |
8fe2d541 AT |
2329 | } |
2330 | #endif | |
2331 | ||
7192f92c HS |
2332 | static struct uart_ops atmel_pops = { |
2333 | .tx_empty = atmel_tx_empty, | |
2334 | .set_mctrl = atmel_set_mctrl, | |
2335 | .get_mctrl = atmel_get_mctrl, | |
2336 | .stop_tx = atmel_stop_tx, | |
2337 | .start_tx = atmel_start_tx, | |
2338 | .stop_rx = atmel_stop_rx, | |
2339 | .enable_ms = atmel_enable_ms, | |
2340 | .break_ctl = atmel_break_ctl, | |
2341 | .startup = atmel_startup, | |
2342 | .shutdown = atmel_shutdown, | |
9afd561a | 2343 | .flush_buffer = atmel_flush_buffer, |
7192f92c | 2344 | .set_termios = atmel_set_termios, |
42bd7a4f | 2345 | .set_ldisc = atmel_set_ldisc, |
7192f92c HS |
2346 | .type = atmel_type, |
2347 | .release_port = atmel_release_port, | |
2348 | .request_port = atmel_request_port, | |
2349 | .config_port = atmel_config_port, | |
2350 | .verify_port = atmel_verify_port, | |
2351 | .pm = atmel_serial_pm, | |
8fe2d541 AT |
2352 | #ifdef CONFIG_CONSOLE_POLL |
2353 | .poll_get_char = atmel_poll_get_char, | |
2354 | .poll_put_char = atmel_poll_put_char, | |
2355 | #endif | |
1e6c9c28 AV |
2356 | }; |
2357 | ||
afefc415 AV |
2358 | /* |
2359 | * Configure the port from the platform device resource info. | |
2360 | */ | |
91f8c2d8 | 2361 | static int atmel_init_port(struct atmel_uart_port *atmel_port, |
b843aa21 | 2362 | struct platform_device *pdev) |
1e6c9c28 | 2363 | { |
91f8c2d8 | 2364 | int ret; |
7192f92c | 2365 | struct uart_port *port = &atmel_port->uart; |
574de559 | 2366 | struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); |
afefc415 | 2367 | |
4a1e8888 LZ |
2368 | atmel_init_property(atmel_port, pdev); |
2369 | atmel_set_ops(port); | |
afefc415 | 2370 | |
13bd3e6f | 2371 | atmel_init_rs485(port, pdev); |
a930e528 | 2372 | |
e8faff73 CS |
2373 | port->iotype = UPIO_MEM; |
2374 | port->flags = UPF_BOOT_AUTOCONF; | |
2375 | port->ops = &atmel_pops; | |
2376 | port->fifosize = 1; | |
e8faff73 | 2377 | port->dev = &pdev->dev; |
afefc415 AV |
2378 | port->mapbase = pdev->resource[0].start; |
2379 | port->irq = pdev->resource[1].start; | |
13bd3e6f | 2380 | port->rs485_config = atmel_config_rs485; |
afefc415 | 2381 | |
1ecc26bd RB |
2382 | tasklet_init(&atmel_port->tasklet, atmel_tasklet_func, |
2383 | (unsigned long)port); | |
1e125786 | 2384 | tasklet_disable(&atmel_port->tasklet); |
1ecc26bd RB |
2385 | |
2386 | memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring)); | |
2387 | ||
5fbe46b6 | 2388 | if (pdata && pdata->regs) { |
75d35213 | 2389 | /* Already mapped by setup code */ |
1acfc7ec | 2390 | port->membase = pdata->regs; |
588edbf3 | 2391 | } else { |
afefc415 AV |
2392 | port->flags |= UPF_IOREMAP; |
2393 | port->membase = NULL; | |
2394 | } | |
1e6c9c28 | 2395 | |
b843aa21 RB |
2396 | /* for console, the clock could already be configured */ |
2397 | if (!atmel_port->clk) { | |
7192f92c | 2398 | atmel_port->clk = clk_get(&pdev->dev, "usart"); |
91f8c2d8 BB |
2399 | if (IS_ERR(atmel_port->clk)) { |
2400 | ret = PTR_ERR(atmel_port->clk); | |
2401 | atmel_port->clk = NULL; | |
2402 | return ret; | |
2403 | } | |
2404 | ret = clk_prepare_enable(atmel_port->clk); | |
2405 | if (ret) { | |
2406 | clk_put(atmel_port->clk); | |
2407 | atmel_port->clk = NULL; | |
2408 | return ret; | |
2409 | } | |
7192f92c | 2410 | port->uartclk = clk_get_rate(atmel_port->clk); |
91f8c2d8 | 2411 | clk_disable_unprepare(atmel_port->clk); |
06a7f058 | 2412 | /* only enable clock when USART is in use */ |
afefc415 | 2413 | } |
a6670615 | 2414 | |
e8faff73 | 2415 | /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */ |
13bd3e6f | 2416 | if (port->rs485.flags & SER_RS485_ENABLED) |
e8faff73 | 2417 | atmel_port->tx_done_mask = ATMEL_US_TXEMPTY; |
64e22ebe | 2418 | else if (atmel_use_pdc_tx(port)) { |
a6670615 | 2419 | port->fifosize = PDC_BUFFER_SIZE; |
e8faff73 CS |
2420 | atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE; |
2421 | } else { | |
2422 | atmel_port->tx_done_mask = ATMEL_US_TXRDY; | |
2423 | } | |
91f8c2d8 BB |
2424 | |
2425 | return 0; | |
1e6c9c28 AV |
2426 | } |
2427 | ||
69f6a27b JCPV |
2428 | struct platform_device *atmel_default_console_device; /* the serial console device */ |
2429 | ||
749c4e60 | 2430 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
7192f92c | 2431 | static void atmel_console_putchar(struct uart_port *port, int ch) |
d358788f | 2432 | { |
4e7decda | 2433 | while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) |
829dd811 | 2434 | cpu_relax(); |
a6499435 | 2435 | atmel_uart_write_char(port, ch); |
d358788f | 2436 | } |
1e6c9c28 AV |
2437 | |
2438 | /* | |
2439 | * Interrupts are disabled on entering | |
2440 | */ | |
7192f92c | 2441 | static void atmel_console_write(struct console *co, const char *s, u_int count) |
1e6c9c28 | 2442 | { |
7192f92c | 2443 | struct uart_port *port = &atmel_ports[co->index].uart; |
e8faff73 | 2444 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
d358788f | 2445 | unsigned int status, imr; |
39d4c922 | 2446 | unsigned int pdc_tx; |
1e6c9c28 AV |
2447 | |
2448 | /* | |
b843aa21 | 2449 | * First, save IMR and then disable interrupts |
1e6c9c28 | 2450 | */ |
4e7decda CP |
2451 | imr = atmel_uart_readl(port, ATMEL_US_IMR); |
2452 | atmel_uart_writel(port, ATMEL_US_IDR, | |
2453 | ATMEL_US_RXRDY | atmel_port->tx_done_mask); | |
1e6c9c28 | 2454 | |
39d4c922 | 2455 | /* Store PDC transmit status and disable it */ |
4e7decda CP |
2456 | pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN; |
2457 | atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS); | |
39d4c922 | 2458 | |
7192f92c | 2459 | uart_console_write(port, s, count, atmel_console_putchar); |
1e6c9c28 AV |
2460 | |
2461 | /* | |
b843aa21 RB |
2462 | * Finally, wait for transmitter to become empty |
2463 | * and restore IMR | |
1e6c9c28 AV |
2464 | */ |
2465 | do { | |
4e7decda | 2466 | status = atmel_uart_readl(port, ATMEL_US_CSR); |
7192f92c | 2467 | } while (!(status & ATMEL_US_TXRDY)); |
39d4c922 MP |
2468 | |
2469 | /* Restore PDC transmit status */ | |
2470 | if (pdc_tx) | |
4e7decda | 2471 | atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN); |
39d4c922 | 2472 | |
b843aa21 | 2473 | /* set interrupts back the way they were */ |
4e7decda | 2474 | atmel_uart_writel(port, ATMEL_US_IER, imr); |
1e6c9c28 AV |
2475 | } |
2476 | ||
2477 | /* | |
b843aa21 RB |
2478 | * If the port was already initialised (eg, by a boot loader), |
2479 | * try to determine the current setup. | |
1e6c9c28 | 2480 | */ |
b843aa21 RB |
2481 | static void __init atmel_console_get_options(struct uart_port *port, int *baud, |
2482 | int *parity, int *bits) | |
1e6c9c28 AV |
2483 | { |
2484 | unsigned int mr, quot; | |
2485 | ||
1c0fd82f HS |
2486 | /* |
2487 | * If the baud rate generator isn't running, the port wasn't | |
2488 | * initialized by the boot loader. | |
2489 | */ | |
4e7decda | 2490 | quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD; |
1c0fd82f HS |
2491 | if (!quot) |
2492 | return; | |
1e6c9c28 | 2493 | |
4e7decda | 2494 | mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL; |
7192f92c | 2495 | if (mr == ATMEL_US_CHRL_8) |
1e6c9c28 AV |
2496 | *bits = 8; |
2497 | else | |
2498 | *bits = 7; | |
2499 | ||
4e7decda | 2500 | mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR; |
7192f92c | 2501 | if (mr == ATMEL_US_PAR_EVEN) |
1e6c9c28 | 2502 | *parity = 'e'; |
7192f92c | 2503 | else if (mr == ATMEL_US_PAR_ODD) |
1e6c9c28 AV |
2504 | *parity = 'o'; |
2505 | ||
4d5e392c HS |
2506 | /* |
2507 | * The serial core only rounds down when matching this to a | |
2508 | * supported baud rate. Make sure we don't end up slightly | |
2509 | * lower than one of those, as it would make us fall through | |
2510 | * to a much lower baud rate than we really want. | |
2511 | */ | |
4d5e392c | 2512 | *baud = port->uartclk / (16 * (quot - 1)); |
1e6c9c28 AV |
2513 | } |
2514 | ||
7192f92c | 2515 | static int __init atmel_console_setup(struct console *co, char *options) |
1e6c9c28 | 2516 | { |
91f8c2d8 | 2517 | int ret; |
7192f92c | 2518 | struct uart_port *port = &atmel_ports[co->index].uart; |
1e6c9c28 AV |
2519 | int baud = 115200; |
2520 | int bits = 8; | |
2521 | int parity = 'n'; | |
2522 | int flow = 'n'; | |
2523 | ||
b843aa21 RB |
2524 | if (port->membase == NULL) { |
2525 | /* Port not initialized yet - delay setup */ | |
afefc415 | 2526 | return -ENODEV; |
b843aa21 | 2527 | } |
1e6c9c28 | 2528 | |
91f8c2d8 BB |
2529 | ret = clk_prepare_enable(atmel_ports[co->index].clk); |
2530 | if (ret) | |
2531 | return ret; | |
06a7f058 | 2532 | |
4e7decda CP |
2533 | atmel_uart_writel(port, ATMEL_US_IDR, -1); |
2534 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX); | |
2535 | atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN); | |
1e6c9c28 AV |
2536 | |
2537 | if (options) | |
2538 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2539 | else | |
7192f92c | 2540 | atmel_console_get_options(port, &baud, &parity, &bits); |
1e6c9c28 AV |
2541 | |
2542 | return uart_set_options(port, co, baud, parity, bits, flow); | |
2543 | } | |
2544 | ||
7192f92c | 2545 | static struct uart_driver atmel_uart; |
1e6c9c28 | 2546 | |
7192f92c HS |
2547 | static struct console atmel_console = { |
2548 | .name = ATMEL_DEVICENAME, | |
2549 | .write = atmel_console_write, | |
1e6c9c28 | 2550 | .device = uart_console_device, |
7192f92c | 2551 | .setup = atmel_console_setup, |
1e6c9c28 AV |
2552 | .flags = CON_PRINTBUFFER, |
2553 | .index = -1, | |
7192f92c | 2554 | .data = &atmel_uart, |
1e6c9c28 AV |
2555 | }; |
2556 | ||
06a7f058 | 2557 | #define ATMEL_CONSOLE_DEVICE (&atmel_console) |
1e6c9c28 | 2558 | |
afefc415 AV |
2559 | /* |
2560 | * Early console initialization (before VM subsystem initialized). | |
2561 | */ | |
7192f92c | 2562 | static int __init atmel_console_init(void) |
1e6c9c28 | 2563 | { |
91f8c2d8 | 2564 | int ret; |
73e2798b | 2565 | if (atmel_default_console_device) { |
0d0a3cc1 | 2566 | struct atmel_uart_data *pdata = |
574de559 | 2567 | dev_get_platdata(&atmel_default_console_device->dev); |
efb8d21b | 2568 | int id = pdata->num; |
4cbf9f48 NF |
2569 | struct atmel_uart_port *port = &atmel_ports[id]; |
2570 | ||
4cbf9f48 NF |
2571 | port->backup_imr = 0; |
2572 | port->uart.line = id; | |
0d0a3cc1 | 2573 | |
4cbf9f48 | 2574 | add_preferred_console(ATMEL_DEVICENAME, id, NULL); |
91f8c2d8 BB |
2575 | ret = atmel_init_port(port, atmel_default_console_device); |
2576 | if (ret) | |
2577 | return ret; | |
7192f92c | 2578 | register_console(&atmel_console); |
afefc415 | 2579 | } |
1e6c9c28 | 2580 | |
1e6c9c28 AV |
2581 | return 0; |
2582 | } | |
b843aa21 | 2583 | |
7192f92c | 2584 | console_initcall(atmel_console_init); |
1e6c9c28 | 2585 | |
afefc415 AV |
2586 | /* |
2587 | * Late console initialization. | |
2588 | */ | |
7192f92c | 2589 | static int __init atmel_late_console_init(void) |
afefc415 | 2590 | { |
b843aa21 RB |
2591 | if (atmel_default_console_device |
2592 | && !(atmel_console.flags & CON_ENABLED)) | |
7192f92c | 2593 | register_console(&atmel_console); |
afefc415 AV |
2594 | |
2595 | return 0; | |
2596 | } | |
b843aa21 | 2597 | |
7192f92c | 2598 | core_initcall(atmel_late_console_init); |
afefc415 | 2599 | |
dfa7f343 HS |
2600 | static inline bool atmel_is_console_port(struct uart_port *port) |
2601 | { | |
2602 | return port->cons && port->cons->index == port->line; | |
2603 | } | |
2604 | ||
1e6c9c28 | 2605 | #else |
7192f92c | 2606 | #define ATMEL_CONSOLE_DEVICE NULL |
dfa7f343 HS |
2607 | |
2608 | static inline bool atmel_is_console_port(struct uart_port *port) | |
2609 | { | |
2610 | return false; | |
2611 | } | |
1e6c9c28 AV |
2612 | #endif |
2613 | ||
7192f92c | 2614 | static struct uart_driver atmel_uart = { |
b843aa21 RB |
2615 | .owner = THIS_MODULE, |
2616 | .driver_name = "atmel_serial", | |
2617 | .dev_name = ATMEL_DEVICENAME, | |
2618 | .major = SERIAL_ATMEL_MAJOR, | |
2619 | .minor = MINOR_START, | |
2620 | .nr = ATMEL_MAX_UART, | |
2621 | .cons = ATMEL_CONSOLE_DEVICE, | |
1e6c9c28 AV |
2622 | }; |
2623 | ||
afefc415 | 2624 | #ifdef CONFIG_PM |
f826caa4 HS |
2625 | static bool atmel_serial_clk_will_stop(void) |
2626 | { | |
2627 | #ifdef CONFIG_ARCH_AT91 | |
2628 | return at91_suspend_entering_slow_clock(); | |
2629 | #else | |
2630 | return false; | |
2631 | #endif | |
2632 | } | |
2633 | ||
b843aa21 RB |
2634 | static int atmel_serial_suspend(struct platform_device *pdev, |
2635 | pm_message_t state) | |
1e6c9c28 | 2636 | { |
afefc415 | 2637 | struct uart_port *port = platform_get_drvdata(pdev); |
c811ab8c | 2638 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 | 2639 | |
e1c609ef HS |
2640 | if (atmel_is_console_port(port) && console_suspend_enabled) { |
2641 | /* Drain the TX shifter */ | |
4e7decda CP |
2642 | while (!(atmel_uart_readl(port, ATMEL_US_CSR) & |
2643 | ATMEL_US_TXEMPTY)) | |
e1c609ef HS |
2644 | cpu_relax(); |
2645 | } | |
2646 | ||
f05596db AS |
2647 | /* we can not wake up if we're running on slow clock */ |
2648 | atmel_port->may_wakeup = device_may_wakeup(&pdev->dev); | |
2c7af5ba BB |
2649 | if (atmel_serial_clk_will_stop()) { |
2650 | unsigned long flags; | |
2651 | ||
2652 | spin_lock_irqsave(&atmel_port->lock_suspended, flags); | |
2653 | atmel_port->suspended = true; | |
2654 | spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); | |
f05596db | 2655 | device_set_wakeup_enable(&pdev->dev, 0); |
2c7af5ba | 2656 | } |
f05596db AS |
2657 | |
2658 | uart_suspend_port(&atmel_uart, port); | |
1e6c9c28 | 2659 | |
afefc415 AV |
2660 | return 0; |
2661 | } | |
1e6c9c28 | 2662 | |
7192f92c | 2663 | static int atmel_serial_resume(struct platform_device *pdev) |
afefc415 AV |
2664 | { |
2665 | struct uart_port *port = platform_get_drvdata(pdev); | |
c811ab8c | 2666 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
2c7af5ba BB |
2667 | unsigned long flags; |
2668 | ||
2669 | spin_lock_irqsave(&atmel_port->lock_suspended, flags); | |
2670 | if (atmel_port->pending) { | |
2671 | atmel_handle_receive(port, atmel_port->pending); | |
2672 | atmel_handle_status(port, atmel_port->pending, | |
2673 | atmel_port->pending_status); | |
2674 | atmel_handle_transmit(port, atmel_port->pending); | |
2675 | atmel_port->pending = 0; | |
2676 | } | |
2677 | atmel_port->suspended = false; | |
2678 | spin_unlock_irqrestore(&atmel_port->lock_suspended, flags); | |
1e6c9c28 | 2679 | |
f05596db AS |
2680 | uart_resume_port(&atmel_uart, port); |
2681 | device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup); | |
1e6c9c28 AV |
2682 | |
2683 | return 0; | |
2684 | } | |
afefc415 | 2685 | #else |
7192f92c HS |
2686 | #define atmel_serial_suspend NULL |
2687 | #define atmel_serial_resume NULL | |
afefc415 | 2688 | #endif |
1e6c9c28 | 2689 | |
e0b0baad RG |
2690 | static int atmel_init_gpios(struct atmel_uart_port *p, struct device *dev) |
2691 | { | |
ab5e4e41 RG |
2692 | enum mctrl_gpio_idx i; |
2693 | struct gpio_desc *gpiod; | |
2694 | ||
e0b0baad | 2695 | p->gpios = mctrl_gpio_init(dev, 0); |
722ccf41 UKK |
2696 | if (IS_ERR(p->gpios)) |
2697 | return PTR_ERR(p->gpios); | |
e0b0baad | 2698 | |
ab5e4e41 RG |
2699 | for (i = 0; i < UART_GPIO_MAX; i++) { |
2700 | gpiod = mctrl_gpio_to_gpiod(p->gpios, i); | |
2701 | if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN)) | |
2702 | p->gpio_irq[i] = gpiod_to_irq(gpiod); | |
2703 | else | |
2704 | p->gpio_irq[i] = -EINVAL; | |
2705 | } | |
2706 | ||
e0b0baad RG |
2707 | return 0; |
2708 | } | |
2709 | ||
b5199d46 CP |
2710 | static void atmel_serial_probe_fifos(struct atmel_uart_port *port, |
2711 | struct platform_device *pdev) | |
2712 | { | |
2713 | port->fifo_size = 0; | |
2714 | port->rts_low = 0; | |
2715 | port->rts_high = 0; | |
2716 | ||
2717 | if (of_property_read_u32(pdev->dev.of_node, | |
2718 | "atmel,fifo-size", | |
2719 | &port->fifo_size)) | |
2720 | return; | |
2721 | ||
2722 | if (!port->fifo_size) | |
2723 | return; | |
2724 | ||
2725 | if (port->fifo_size < ATMEL_MIN_FIFO_SIZE) { | |
2726 | port->fifo_size = 0; | |
2727 | dev_err(&pdev->dev, "Invalid FIFO size\n"); | |
2728 | return; | |
2729 | } | |
2730 | ||
2731 | /* | |
2732 | * 0 <= rts_low <= rts_high <= fifo_size | |
2733 | * Once their CTS line asserted by the remote peer, some x86 UARTs tend | |
2734 | * to flush their internal TX FIFO, commonly up to 16 data, before | |
2735 | * actually stopping to send new data. So we try to set the RTS High | |
2736 | * Threshold to a reasonably high value respecting this 16 data | |
2737 | * empirical rule when possible. | |
2738 | */ | |
2739 | port->rts_high = max_t(int, port->fifo_size >> 1, | |
2740 | port->fifo_size - ATMEL_RTS_HIGH_OFFSET); | |
2741 | port->rts_low = max_t(int, port->fifo_size >> 2, | |
2742 | port->fifo_size - ATMEL_RTS_LOW_OFFSET); | |
2743 | ||
2744 | dev_info(&pdev->dev, "Using FIFO (%u data)\n", | |
2745 | port->fifo_size); | |
2746 | dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n", | |
2747 | port->rts_high); | |
2748 | dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n", | |
2749 | port->rts_low); | |
2750 | } | |
2751 | ||
9671f099 | 2752 | static int atmel_serial_probe(struct platform_device *pdev) |
1e6c9c28 | 2753 | { |
7192f92c | 2754 | struct atmel_uart_port *port; |
5fbe46b6 | 2755 | struct device_node *np = pdev->dev.of_node; |
574de559 | 2756 | struct atmel_uart_data *pdata = dev_get_platdata(&pdev->dev); |
1ecc26bd | 2757 | void *data; |
4cbf9f48 | 2758 | int ret = -ENODEV; |
bd737f87 | 2759 | bool rs485_enabled; |
1e6c9c28 | 2760 | |
9d09daf8 | 2761 | BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1)); |
1ecc26bd | 2762 | |
5fbe46b6 NF |
2763 | if (np) |
2764 | ret = of_alias_get_id(np, "serial"); | |
2765 | else | |
2766 | if (pdata) | |
2767 | ret = pdata->num; | |
4cbf9f48 NF |
2768 | |
2769 | if (ret < 0) | |
5fbe46b6 | 2770 | /* port id not found in platform data nor device-tree aliases: |
4cbf9f48 | 2771 | * auto-enumerate it */ |
503bded9 | 2772 | ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART); |
4cbf9f48 | 2773 | |
503bded9 | 2774 | if (ret >= ATMEL_MAX_UART) { |
4cbf9f48 NF |
2775 | ret = -ENODEV; |
2776 | goto err; | |
2777 | } | |
2778 | ||
503bded9 | 2779 | if (test_and_set_bit(ret, atmel_ports_in_use)) { |
4cbf9f48 NF |
2780 | /* port already in use */ |
2781 | ret = -EBUSY; | |
2782 | goto err; | |
2783 | } | |
2784 | ||
2785 | port = &atmel_ports[ret]; | |
f05596db | 2786 | port->backup_imr = 0; |
4cbf9f48 | 2787 | port->uart.line = ret; |
b5199d46 | 2788 | atmel_serial_probe_fifos(port, pdev); |
e0b0baad | 2789 | |
2c7af5ba BB |
2790 | spin_lock_init(&port->lock_suspended); |
2791 | ||
e0b0baad | 2792 | ret = atmel_init_gpios(port, &pdev->dev); |
722ccf41 UKK |
2793 | if (ret < 0) { |
2794 | dev_err(&pdev->dev, "Failed to initialize GPIOs."); | |
2795 | goto err; | |
2796 | } | |
f05596db | 2797 | |
91f8c2d8 BB |
2798 | ret = atmel_init_port(port, pdev); |
2799 | if (ret) | |
6fbb9bdf | 2800 | goto err_clear_bit; |
1e6c9c28 | 2801 | |
64e22ebe | 2802 | if (!atmel_use_pdc_rx(&port->uart)) { |
a6670615 | 2803 | ret = -ENOMEM; |
6433471d HS |
2804 | data = kmalloc(sizeof(struct atmel_uart_char) |
2805 | * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL); | |
a6670615 CC |
2806 | if (!data) |
2807 | goto err_alloc_ring; | |
2808 | port->rx_ring.buf = data; | |
2809 | } | |
1ecc26bd | 2810 | |
bd737f87 RRD |
2811 | rs485_enabled = port->uart.rs485.flags & SER_RS485_ENABLED; |
2812 | ||
7192f92c | 2813 | ret = uart_add_one_port(&atmel_uart, &port->uart); |
dfa7f343 HS |
2814 | if (ret) |
2815 | goto err_add_port; | |
2816 | ||
8da14b5f | 2817 | #ifdef CONFIG_SERIAL_ATMEL_CONSOLE |
06a7f058 DB |
2818 | if (atmel_is_console_port(&port->uart) |
2819 | && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) { | |
2820 | /* | |
2821 | * The serial core enabled the clock for us, so undo | |
91f8c2d8 | 2822 | * the clk_prepare_enable() in atmel_console_setup() |
06a7f058 | 2823 | */ |
91f8c2d8 | 2824 | clk_disable_unprepare(port->clk); |
06a7f058 | 2825 | } |
8da14b5f | 2826 | #endif |
06a7f058 | 2827 | |
dfa7f343 HS |
2828 | device_init_wakeup(&pdev->dev, 1); |
2829 | platform_set_drvdata(pdev, port); | |
2830 | ||
d4f64187 CP |
2831 | /* |
2832 | * The peripheral clock has been disabled by atmel_init_port(): | |
2833 | * enable it before accessing I/O registers | |
2834 | */ | |
2835 | clk_prepare_enable(port->clk); | |
2836 | ||
bd737f87 | 2837 | if (rs485_enabled) { |
4e7decda CP |
2838 | atmel_uart_writel(&port->uart, ATMEL_US_MR, |
2839 | ATMEL_US_USMODE_NORMAL); | |
2840 | atmel_uart_writel(&port->uart, ATMEL_US_CR, ATMEL_US_RTSEN); | |
5dfbd1d7 CS |
2841 | } |
2842 | ||
055560b0 ES |
2843 | /* |
2844 | * Get port name of usart or uart | |
2845 | */ | |
892db58b | 2846 | atmel_get_ip_name(&port->uart); |
055560b0 | 2847 | |
d4f64187 CP |
2848 | /* |
2849 | * The peripheral clock can now safely be disabled till the port | |
2850 | * is used | |
2851 | */ | |
2852 | clk_disable_unprepare(port->clk); | |
2853 | ||
dfa7f343 HS |
2854 | return 0; |
2855 | ||
2856 | err_add_port: | |
1ecc26bd RB |
2857 | kfree(port->rx_ring.buf); |
2858 | port->rx_ring.buf = NULL; | |
2859 | err_alloc_ring: | |
dfa7f343 | 2860 | if (!atmel_is_console_port(&port->uart)) { |
dfa7f343 HS |
2861 | clk_put(port->clk); |
2862 | port->clk = NULL; | |
afefc415 | 2863 | } |
6fbb9bdf CP |
2864 | err_clear_bit: |
2865 | clear_bit(port->uart.line, atmel_ports_in_use); | |
4cbf9f48 | 2866 | err: |
afefc415 AV |
2867 | return ret; |
2868 | } | |
2869 | ||
ae8d8a14 | 2870 | static int atmel_serial_remove(struct platform_device *pdev) |
afefc415 AV |
2871 | { |
2872 | struct uart_port *port = platform_get_drvdata(pdev); | |
c811ab8c | 2873 | struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); |
afefc415 AV |
2874 | int ret = 0; |
2875 | ||
f50c995f MR |
2876 | tasklet_kill(&atmel_port->tasklet); |
2877 | ||
afefc415 | 2878 | device_init_wakeup(&pdev->dev, 0); |
afefc415 | 2879 | |
dfa7f343 HS |
2880 | ret = uart_remove_one_port(&atmel_uart, port); |
2881 | ||
1ecc26bd RB |
2882 | kfree(atmel_port->rx_ring.buf); |
2883 | ||
dfa7f343 HS |
2884 | /* "port" is allocated statically, so we shouldn't free it */ |
2885 | ||
503bded9 | 2886 | clear_bit(port->line, atmel_ports_in_use); |
4cbf9f48 | 2887 | |
dfa7f343 | 2888 | clk_put(atmel_port->clk); |
afefc415 AV |
2889 | |
2890 | return ret; | |
2891 | } | |
2892 | ||
7192f92c HS |
2893 | static struct platform_driver atmel_serial_driver = { |
2894 | .probe = atmel_serial_probe, | |
2d47b716 | 2895 | .remove = atmel_serial_remove, |
7192f92c HS |
2896 | .suspend = atmel_serial_suspend, |
2897 | .resume = atmel_serial_resume, | |
afefc415 | 2898 | .driver = { |
1e8ea802 | 2899 | .name = "atmel_usart", |
5fbe46b6 | 2900 | .of_match_table = of_match_ptr(atmel_serial_dt_ids), |
afefc415 AV |
2901 | }, |
2902 | }; | |
2903 | ||
7192f92c | 2904 | static int __init atmel_serial_init(void) |
afefc415 AV |
2905 | { |
2906 | int ret; | |
2907 | ||
7192f92c | 2908 | ret = uart_register_driver(&atmel_uart); |
afefc415 AV |
2909 | if (ret) |
2910 | return ret; | |
2911 | ||
7192f92c | 2912 | ret = platform_driver_register(&atmel_serial_driver); |
afefc415 | 2913 | if (ret) |
7192f92c | 2914 | uart_unregister_driver(&atmel_uart); |
afefc415 AV |
2915 | |
2916 | return ret; | |
2917 | } | |
2918 | ||
7192f92c | 2919 | static void __exit atmel_serial_exit(void) |
afefc415 | 2920 | { |
7192f92c HS |
2921 | platform_driver_unregister(&atmel_serial_driver); |
2922 | uart_unregister_driver(&atmel_uart); | |
1e6c9c28 AV |
2923 | } |
2924 | ||
7192f92c HS |
2925 | module_init(atmel_serial_init); |
2926 | module_exit(atmel_serial_exit); | |
1e6c9c28 AV |
2927 | |
2928 | MODULE_AUTHOR("Rick Bronson"); | |
7192f92c | 2929 | MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver"); |
1e6c9c28 | 2930 | MODULE_LICENSE("GPL"); |
e169c139 | 2931 | MODULE_ALIAS("platform:atmel_usart"); |