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Merge tag 'for-linus-4.4-rc2-tag' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / tty / serial / bfin_sport_uart.c
CommitLineData
2f351741 1/*
ccf68e59 2 * Blackfin On-Chip Sport Emulated UART Driver
2f351741 3 *
ccf68e59 4 * Copyright 2006-2009 Analog Devices Inc.
2f351741 5 *
ccf68e59 6 * Enter bugs at http://blackfin.uclinux.org/
2f351741 7 *
ccf68e59 8 * Licensed under the GPL-2 or later.
2f351741
BW		 9 */
10
11/*
12 * This driver and the hardware supported are in term of EE-191 of ADI.
631dd1a8 13 * http://www.analog.com/static/imported-files/application_notes/EE191.pdf
2f351741
BW		 14 * This application note describe how to implement a UART on a Sharc DSP,
15 * but this driver is implemented on Blackfin Processor.
ccf68e59 16 * Transmit Frame Sync is not used by this driver to transfer data out.
2f351741
BW		 17 */
18
ccf68e59 19/* #define DEBUG */
2f351741 20
ccf68e59 21#define DRV_NAME "bfin-sport-uart"
22#define DEVICE_NAME "ttySS"
23#define pr_fmt(fmt) DRV_NAME ": " fmt
2f351741
BW		 24
25#include <linux/module.h>
26#include <linux/ioport.h>
ccf68e59 27#include <linux/io.h>
2f351741
BW		 28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
5a0e3ad6 31#include <linux/slab.h>
2f351741
BW		 32#include <linux/platform_device.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_core.h>
16020b98 36#include <linux/gpio.h>
2f351741 37
2ce1efc9 38#include <asm/bfin_sport.h>
2f351741
BW		 39#include <asm/delay.h>
40#include <asm/portmux.h>
41
42#include "bfin_sport_uart.h"
43
2f351741
BW		 44struct sport_uart_port {
45 struct uart_port port;
2f351741 46 int err_irq;
ccf68e59 47 unsigned short csize;
48 unsigned short rxmask;
49 unsigned short txmask1;
50 unsigned short txmask2;
51 unsigned char stopb;
52/* unsigned char parib; */
1f7d1c85
SZ		 53#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
54 int cts_pin;
55 int rts_pin;
56#endif
2f351741
BW		 57};
58
9356c461 59static int sport_uart_tx_chars(struct sport_uart_port *up);
2f351741
BW		 60static void sport_stop_tx(struct uart_port *port);
61
62static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
63{
ccf68e59 64 pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
65 up->txmask1, up->txmask2);
66
67 /* Place Start and Stop bits */
4328e3e5 68 __asm__ __volatile__ (
ccf68e59 69 "%[val] <<= 1;"
70 "%[val] = %[val] & %[mask1];"
71 "%[val] = %[val] | %[mask2];"
72 : [val]"+d"(value)
73 : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
74 : "ASTAT"
4328e3e5 75 );
6ef53066 76 pr_debug("%s value:%x\n", __func__, value);
2f351741
BW		 77
78 SPORT_PUT_TX(up, value);
79}
80
ccf68e59 81static inline unsigned char rx_one_byte(struct sport_uart_port *up)
2f351741 82{
ccf68e59 83 unsigned int value;
84 unsigned char extract;
4328e3e5 85 u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
2f351741 86
ccf68e59 87 if ((up->csize + up->stopb) > 7)
88 value = SPORT_GET_RX32(up);
89 else
90 value = SPORT_GET_RX(up);
91
92 pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
93 up->csize, up->rxmask);
2f351741 94
ccf68e59 95 /* Extract data */
4328e3e5
MF		 96 __asm__ __volatile__ (
97 "%[extr] = 0;"
ccf68e59 98 "%[mask1] = %[rxmask];"
99 "%[mask2] = 0x0200(Z);"
4328e3e5
MF		 100 "%[shift] = 0;"
101 "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
102 ".Lloop_s:"
103 "%[tmp] = extract(%[val], %[mask1].L)(Z);"
104 "%[tmp] <<= %[shift];"
105 "%[extr] = %[extr] | %[tmp];"
106 "%[mask1] = %[mask1] - %[mask2];"
107 ".Lloop_e:"
108 "%[shift] += 1;"
ccf68e59 109 : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
110 [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
111 : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
4328e3e5
MF		 112 : "ASTAT", "LB0", "LC0", "LT0"
113 );
2f351741
BW		 114
115 pr_debug(" extract:%x\n", extract);
116 return extract;
117}
118
ccf68e59 119static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
2f351741 120{
ccf68e59 121 int tclkdiv, rclkdiv;
122 unsigned int sclk = get_sclk();
2f351741 123
ccf68e59 124 /* Set TCR1 and TCR2, TFSR is not enabled for uart */
33674691 125 SPORT_PUT_TCR1(up, (LATFS | ITFS | TFSR | TLSBIT | ITCLK));
ccf68e59 126 SPORT_PUT_TCR2(up, size + 1);
6ef53066 127 pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
2f351741
BW		 128
129 /* Set RCR1 and RCR2 */
130 SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
ccf68e59 131 SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
6ef53066 132 pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
2f351741 133
ccf68e59 134 tclkdiv = sclk / (2 * baud_rate) - 1;
0dd25df1
SZ		 135 /* The actual uart baud rate of devices vary between +/-2%. The sport
136 * RX sample rate should be faster than the double of the worst case,
137 * otherwise, wrong data are received. So, set sport RX clock to be
138 * 3% faster.
139 */
140 rclkdiv = sclk / (2 * baud_rate * 2 * 97 / 100) - 1;
2f351741 141 SPORT_PUT_TCLKDIV(up, tclkdiv);
2f351741
BW		 142 SPORT_PUT_RCLKDIV(up, rclkdiv);
143 SSYNC();
ccf68e59 144 pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
145 __func__, sclk, baud_rate, tclkdiv, rclkdiv);
2f351741
BW		 146
147 return 0;
148}
149
150static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
151{
152 struct sport_uart_port *up = dev_id;
92a19f9c 153 struct tty_port *port = &up->port.state->port;
2f351741
BW		 154 unsigned int ch;
155
ccf68e59 156 spin_lock(&up->port.lock);
157
158 while (SPORT_GET_STAT(up) & RXNE) {
2f351741
BW		 159 ch = rx_one_byte(up);
160 up->port.icount.rx++;
161
ccf68e59 162 if (!uart_handle_sysrq_char(&up->port, ch))
92a19f9c 163 tty_insert_flip_char(port, ch, TTY_NORMAL);
ccf68e59 164 }
2f351741 165
ccf68e59 166 spin_unlock(&up->port.lock);
167
88c54a68
VK		 168 /* XXX this won't deadlock with lowlat? */
169 tty_flip_buffer_push(port);
170
2f351741
BW		 171 return IRQ_HANDLED;
172}
173
174static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
175{
ccf68e59 176 struct sport_uart_port *up = dev_id;
177
178 spin_lock(&up->port.lock);
179 sport_uart_tx_chars(up);
180 spin_unlock(&up->port.lock);
2f351741
BW		 181
182 return IRQ_HANDLED;
183}
184
185static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
186{
187 struct sport_uart_port *up = dev_id;
2f351741
BW		 188 unsigned int stat = SPORT_GET_STAT(up);
189
ccf68e59 190 spin_lock(&up->port.lock);
191
2f351741
BW		 192 /* Overflow in RX FIFO */
193 if (stat & ROVF) {
194 up->port.icount.overrun++;
92a19f9c 195 tty_insert_flip_char(&up->port.state->port, 0, TTY_OVERRUN);
2f351741
BW		 196 SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
197 }
198 /* These should not happen */
199 if (stat & (TOVF | TUVF | RUVF)) {
ccf68e59 200 pr_err("SPORT Error:%s %s %s\n",
201 (stat & TOVF) ? "TX overflow" : "",
202 (stat & TUVF) ? "TX underflow" : "",
203 (stat & RUVF) ? "RX underflow" : "");
2f351741
BW		 204 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
205 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
206 }
207 SSYNC();
208
ccf68e59 209 spin_unlock(&up->port.lock);
92a19f9c
JS		 210 /* XXX we don't push the overrun bit to TTY? */
211
2f351741
BW		 212 return IRQ_HANDLED;
213}
214
1f7d1c85
SZ		 215#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
216static unsigned int sport_get_mctrl(struct uart_port *port)
217{
218 struct sport_uart_port *up = (struct sport_uart_port *)port;
219 if (up->cts_pin < 0)
220 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
221
222 /* CTS PIN is negative assertive. */
223 if (SPORT_UART_GET_CTS(up))
224 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
225 else
226 return TIOCM_DSR | TIOCM_CAR;
227}
228
229static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
230{
231 struct sport_uart_port *up = (struct sport_uart_port *)port;
232 if (up->rts_pin < 0)
233 return;
234
235 /* RTS PIN is negative assertive. */
236 if (mctrl & TIOCM_RTS)
237 SPORT_UART_ENABLE_RTS(up);
238 else
239 SPORT_UART_DISABLE_RTS(up);
240}
241
242/*
243 * Handle any change of modem status signal.
244 */
245static irqreturn_t sport_mctrl_cts_int(int irq, void *dev_id)
246{
247 struct sport_uart_port *up = (struct sport_uart_port *)dev_id;
248 unsigned int status;
249
250 status = sport_get_mctrl(&up->port);
251 uart_handle_cts_change(&up->port, status & TIOCM_CTS);
252
253 return IRQ_HANDLED;
254}
255#else
256static unsigned int sport_get_mctrl(struct uart_port *port)
257{
258 pr_debug("%s enter\n", __func__);
259 return TIOCM_CTS | TIOCM_CD | TIOCM_DSR;
260}
261
262static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
263{
264 pr_debug("%s enter\n", __func__);
265}
266#endif
267
2f351741
BW		 268/* Reqeust IRQ, Setup clock */
269static int sport_startup(struct uart_port *port)
270{
271 struct sport_uart_port *up = (struct sport_uart_port *)port;
ccf68e59 272 int ret;
2f351741 273
6ef53066 274 pr_debug("%s enter\n", __func__);
ccf68e59 275 ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
276 "SPORT_UART_RX", up);
277 if (ret) {
278 dev_err(port->dev, "unable to request SPORT RX interrupt\n");
279 return ret;
2f351741
BW		 280 }
281
ccf68e59 282 ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
283 "SPORT_UART_TX", up);
284 if (ret) {
285 dev_err(port->dev, "unable to request SPORT TX interrupt\n");
2f351741
BW		 286 goto fail1;
287 }
288
ccf68e59 289 ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
290 "SPORT_UART_STATUS", up);
291 if (ret) {
292 dev_err(port->dev, "unable to request SPORT status interrupt\n");
2f351741
BW		 293 goto fail2;
294 }
295
1f7d1c85
SZ		 296#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
297 if (up->cts_pin >= 0) {
298 if (request_irq(gpio_to_irq(up->cts_pin),
299 sport_mctrl_cts_int,
300 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
9cfb5c05 301 0, "BFIN_SPORT_UART_CTS", up)) {
1f7d1c85 302 up->cts_pin = -1;
85ee7a1d 303 dev_info(port->dev, "Unable to attach BlackFin UART over SPORT CTS interrupt. So, disable it.\n");
1f7d1c85
SZ		 304 }
305 }
dc8f3703
SZ		 306 if (up->rts_pin >= 0) {
307 if (gpio_request(up->rts_pin, DRV_NAME)) {
308 dev_info(port->dev, "fail to request RTS PIN at GPIO_%d\n", up->rts_pin);
309 up->rts_pin = -1;
310 } else
311 gpio_direction_output(up->rts_pin, 0);
312 }
1f7d1c85
SZ		 313#endif
314
2f351741 315 return 0;
ccf68e59 316 fail2:
317 free_irq(up->port.irq+1, up);
318 fail1:
319 free_irq(up->port.irq, up);
2f351741 320
ccf68e59 321 return ret;
2f351741
BW		 322}
323
9356c461
SZ		 324/*
325 * sport_uart_tx_chars
326 *
327 * ret 1 means need to enable sport.
328 * ret 0 means do nothing.
329 */
330static int sport_uart_tx_chars(struct sport_uart_port *up)
2f351741 331{
ebd2c8f6 332 struct circ_buf *xmit = &up->port.state->xmit;
2f351741
BW		 333
334 if (SPORT_GET_STAT(up) & TXF)
9356c461 335 return 0;
2f351741
BW		 336
337 if (up->port.x_char) {
338 tx_one_byte(up, up->port.x_char);
339 up->port.icount.tx++;
340 up->port.x_char = 0;
9356c461 341 return 1;
2f351741
BW		 342 }
343
344 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
3f3a978b
SZ		 345 /* The waiting loop to stop SPORT TX from TX interrupt is
346 * too long. This may block SPORT RX interrupts and cause
347 * RX FIFO overflow. So, do stop sport TX only after the last
348 * char in TX FIFO is moved into the shift register.
349 */
350 if (SPORT_GET_STAT(up) & TXHRE)
351 sport_stop_tx(&up->port);
9356c461 352 return 0;
2f351741
BW		 353 }
354
355 while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
356 tx_one_byte(up, xmit->buf[xmit->tail]);
357 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
358 up->port.icount.tx++;
359 }
360
361 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
362 uart_write_wakeup(&up->port);
9356c461
SZ		 363
364 return 1;
2f351741
BW		 365}
366
367static unsigned int sport_tx_empty(struct uart_port *port)
368{
369 struct sport_uart_port *up = (struct sport_uart_port *)port;
370 unsigned int stat;
371
372 stat = SPORT_GET_STAT(up);
6ef53066 373 pr_debug("%s stat:%04x\n", __func__, stat);
2f351741
BW		 374 if (stat & TXHRE) {
375 return TIOCSER_TEMT;
376 } else
377 return 0;
378}
379
2f351741
BW		 380static void sport_stop_tx(struct uart_port *port)
381{
382 struct sport_uart_port *up = (struct sport_uart_port *)port;
2f351741 383
6ef53066 384 pr_debug("%s enter\n", __func__);
2f351741 385
9356c461
SZ		 386 if (!(SPORT_GET_TCR1(up) & TSPEN))
387 return;
388
2f351741 389 /* Although the hold register is empty, last byte is still in shift
ccf68e59 390 * register and not sent out yet. So, put a dummy data into TX FIFO.
391 * Then, sport tx stops when last byte is shift out and the dummy
392 * data is moved into the shift register.
393 */
394 SPORT_PUT_TX(up, 0xffff);
395 while (!(SPORT_GET_STAT(up) & TXHRE))
396 cpu_relax();
2f351741
BW		 397
398 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
399 SSYNC();
400
401 return;
402}
403
404static void sport_start_tx(struct uart_port *port)
405{
406 struct sport_uart_port *up = (struct sport_uart_port *)port;
407
6ef53066 408 pr_debug("%s enter\n", __func__);
ccf68e59 409
2f351741 410 /* Write data into SPORT FIFO before enable SPROT to transmit */
9356c461
SZ		 411 if (sport_uart_tx_chars(up)) {
412 /* Enable transmit, then an interrupt will generated */
413 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
414 SSYNC();
415 }
2f351741 416
6ef53066 417 pr_debug("%s exit\n", __func__);
2f351741
BW		 418}
419
420static void sport_stop_rx(struct uart_port *port)
421{
422 struct sport_uart_port *up = (struct sport_uart_port *)port;
423
6ef53066 424 pr_debug("%s enter\n", __func__);
2f351741
BW		 425 /* Disable sport to stop rx */
426 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
427 SSYNC();
428}
429
2f351741
BW		 430static void sport_break_ctl(struct uart_port *port, int break_state)
431{
6ef53066 432 pr_debug("%s enter\n", __func__);
2f351741
BW		 433}
434
435static void sport_shutdown(struct uart_port *port)
436{
437 struct sport_uart_port *up = (struct sport_uart_port *)port;
438
ccf68e59 439 dev_dbg(port->dev, "%s enter\n", __func__);
2f351741
BW		 440
441 /* Disable sport */
442 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
443 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
444 SSYNC();
445
ccf68e59 446 free_irq(up->port.irq, up);
447 free_irq(up->port.irq+1, up);
2f351741 448 free_irq(up->err_irq, up);
1f7d1c85
SZ		 449#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
450 if (up->cts_pin >= 0)
451 free_irq(gpio_to_irq(up->cts_pin), up);
dc8f3703
SZ		 452 if (up->rts_pin >= 0)
453 gpio_free(up->rts_pin);
1f7d1c85 454#endif
2f351741
BW		 455}
456
2f351741
BW		 457static const char *sport_type(struct uart_port *port)
458{
459 struct sport_uart_port *up = (struct sport_uart_port *)port;
460
6ef53066 461 pr_debug("%s enter\n", __func__);
ccf68e59 462 return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
2f351741
BW		 463}
464
465static void sport_release_port(struct uart_port *port)
466{
6ef53066 467 pr_debug("%s enter\n", __func__);
2f351741
BW		 468}
469
470static int sport_request_port(struct uart_port *port)
471{
6ef53066 472 pr_debug("%s enter\n", __func__);
2f351741
BW		 473 return 0;
474}
475
476static void sport_config_port(struct uart_port *port, int flags)
477{
478 struct sport_uart_port *up = (struct sport_uart_port *)port;
479
6ef53066 480 pr_debug("%s enter\n", __func__);
2f351741
BW		 481 up->port.type = PORT_BFIN_SPORT;
482}
483
484static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
485{
6ef53066 486 pr_debug("%s enter\n", __func__);
2f351741
BW		 487 return 0;
488}
489
ccf68e59 490static void sport_set_termios(struct uart_port *port,
491 struct ktermios *termios, struct ktermios *old)
492{
493 struct sport_uart_port *up = (struct sport_uart_port *)port;
494 unsigned long flags;
495 int i;
496
497 pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
498
8bd67d7d
PH		 499#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
500 if (old == NULL && up->cts_pin != -1)
501 termios->c_cflag |= CRTSCTS;
502 else if (up->cts_pin == -1)
503 termios->c_cflag &= ~CRTSCTS;
504#endif
505
ccf68e59 506 switch (termios->c_cflag & CSIZE) {
507 case CS8:
508 up->csize = 8;
509 break;
510 case CS7:
511 up->csize = 7;
512 break;
513 case CS6:
514 up->csize = 6;
515 break;
516 case CS5:
517 up->csize = 5;
518 break;
519 default:
e620e548
JP		 520 pr_warn("requested word length not supported\n");
521 break;
ccf68e59 522 }
523
524 if (termios->c_cflag & CSTOPB) {
525 up->stopb = 1;
526 }
527 if (termios->c_cflag & PARENB) {
e620e548 528 pr_warn("PAREN bit is not supported yet\n");
ccf68e59 529 /* up->parib = 1; */
530 }
531
9498dc95
SZ		 532 spin_lock_irqsave(&up->port.lock, flags);
533
60bd940f 534 port->read_status_mask = 0;
ccf68e59 535
536 /*
537 * Characters to ignore
538 */
539 port->ignore_status_mask = 0;
ccf68e59 540
541 /* RX extract mask */
542 up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
543 /* TX masks, 8 bit data and 1 bit stop for example:
544 * mask1 = b#0111111110
545 * mask2 = b#1000000000
546 */
547 for (i = 0, up->txmask1 = 0; i < up->csize; i++)
548 up->txmask1 |= (1<<i);
549 up->txmask2 = (1<<i);
550 if (up->stopb) {
551 ++i;
552 up->txmask2 |= (1<<i);
553 }
554 up->txmask1 <<= 1;
555 up->txmask2 <<= 1;
556 /* uart baud rate */
557 port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
558
ccf68e59 559 /* Disable UART */
560 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
561 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
562
563 sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
564
565 /* driver TX line high after config, one dummy data is
566 * necessary to stop sport after shift one byte
567 */
568 SPORT_PUT_TX(up, 0xffff);
569 SPORT_PUT_TX(up, 0xffff);
570 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
571 SSYNC();
572 while (!(SPORT_GET_STAT(up) & TXHRE))
573 cpu_relax();
574 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
575 SSYNC();
576
577 /* Port speed changed, update the per-port timeout. */
578 uart_update_timeout(port, termios->c_cflag, port->uartclk);
579
580 /* Enable sport rx */
581 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
582 SSYNC();
583
584 spin_unlock_irqrestore(&up->port.lock, flags);
585}
586
2f351741
BW		 587struct uart_ops sport_uart_ops = {
588 .tx_empty = sport_tx_empty,
589 .set_mctrl = sport_set_mctrl,
590 .get_mctrl = sport_get_mctrl,
591 .stop_tx = sport_stop_tx,
592 .start_tx = sport_start_tx,
593 .stop_rx = sport_stop_rx,
2f351741
BW		 594 .break_ctl = sport_break_ctl,
595 .startup = sport_startup,
596 .shutdown = sport_shutdown,
597 .set_termios = sport_set_termios,
598 .type = sport_type,
599 .release_port = sport_release_port,
600 .request_port = sport_request_port,
601 .config_port = sport_config_port,
602 .verify_port = sport_verify_port,
603};
604
ccf68e59 605#define BFIN_SPORT_UART_MAX_PORTS 4
606
607static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
608
609#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
b59588aa
SZ		 610#define CLASS_BFIN_SPORT_CONSOLE "bfin-sport-console"
611
ccf68e59 612static int __init
613sport_uart_console_setup(struct console *co, char *options)
614{
615 struct sport_uart_port *up;
616 int baud = 57600;
617 int bits = 8;
618 int parity = 'n';
1f7d1c85
SZ		 619# ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
620 int flow = 'r';
621# else
ccf68e59 622 int flow = 'n';
1f7d1c85 623# endif
ccf68e59 624
625 /* Check whether an invalid uart number has been specified */
626 if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
627 return -ENODEV;
628
629 up = bfin_sport_uart_ports[co->index];
630 if (!up)
631 return -ENODEV;
632
633 if (options)
634 uart_parse_options(options, &baud, &parity, &bits, &flow);
635
636 return uart_set_options(&up->port, co, baud, parity, bits, flow);
637}
638
639static void sport_uart_console_putchar(struct uart_port *port, int ch)
640{
641 struct sport_uart_port *up = (struct sport_uart_port *)port;
642
643 while (SPORT_GET_STAT(up) & TXF)
644 barrier();
645
646 tx_one_byte(up, ch);
647}
648
649/*
650 * Interrupts are disabled on entering
651 */
652static void
653sport_uart_console_write(struct console *co, const char *s, unsigned int count)
654{
655 struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
656 unsigned long flags;
657
658 spin_lock_irqsave(&up->port.lock, flags);
659
660 if (SPORT_GET_TCR1(up) & TSPEN)
661 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
662 else {
663 /* dummy data to start sport */
664 while (SPORT_GET_STAT(up) & TXF)
665 barrier();
666 SPORT_PUT_TX(up, 0xffff);
667 /* Enable transmit, then an interrupt will generated */
668 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
669 SSYNC();
670
671 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
672
673 /* Although the hold register is empty, last byte is still in shift
674 * register and not sent out yet. So, put a dummy data into TX FIFO.
675 * Then, sport tx stops when last byte is shift out and the dummy
676 * data is moved into the shift register.
677 */
678 while (SPORT_GET_STAT(up) & TXF)
679 barrier();
680 SPORT_PUT_TX(up, 0xffff);
681 while (!(SPORT_GET_STAT(up) & TXHRE))
682 barrier();
683
684 /* Stop sport tx transfer */
685 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
686 SSYNC();
2f351741 687 }
ccf68e59 688
689 spin_unlock_irqrestore(&up->port.lock, flags);
690}
691
692static struct uart_driver sport_uart_reg;
693
694static struct console sport_uart_console = {
695 .name = DEVICE_NAME,
696 .write = sport_uart_console_write,
697 .device = uart_console_device,
698 .setup = sport_uart_console_setup,
699 .flags = CON_PRINTBUFFER,
700 .index = -1,
701 .data = &sport_uart_reg,
2f351741
BW		 702};
703
ccf68e59 704#define SPORT_UART_CONSOLE (&sport_uart_console)
705#else
706#define SPORT_UART_CONSOLE NULL
707#endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
708
709
2f351741
BW		 710static struct uart_driver sport_uart_reg = {
711 .owner = THIS_MODULE,
ccf68e59 712 .driver_name = DRV_NAME,
713 .dev_name = DEVICE_NAME,
2f351741
BW		 714 .major = 204,
715 .minor = 84,
ccf68e59 716 .nr = BFIN_SPORT_UART_MAX_PORTS,
717 .cons = SPORT_UART_CONSOLE,
2f351741
BW		 718};
719
ccf68e59 720#ifdef CONFIG_PM
721static int sport_uart_suspend(struct device *dev)
2f351741 722{
ccf68e59 723 struct sport_uart_port *sport = dev_get_drvdata(dev);
2f351741 724
ccf68e59 725 dev_dbg(dev, "%s enter\n", __func__);
2f351741
BW		 726 if (sport)
727 uart_suspend_port(&sport_uart_reg, &sport->port);
728
729 return 0;
730}
731
ccf68e59 732static int sport_uart_resume(struct device *dev)
2f351741 733{
ccf68e59 734 struct sport_uart_port *sport = dev_get_drvdata(dev);
2f351741 735
ccf68e59 736 dev_dbg(dev, "%s enter\n", __func__);
2f351741
BW		 737 if (sport)
738 uart_resume_port(&sport_uart_reg, &sport->port);
739
740 return 0;
741}
742
ccf68e59 743static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
744 .suspend = sport_uart_suspend,
745 .resume = sport_uart_resume,
746};
747#endif
748
9671f099 749static int sport_uart_probe(struct platform_device *pdev)
2f351741 750{
ccf68e59 751 struct resource *res;
752 struct sport_uart_port *sport;
753 int ret = 0;
2f351741 754
ccf68e59 755 dev_dbg(&pdev->dev, "%s enter\n", __func__);
756
757 if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
758 dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
759 return -ENOENT;
760 }
761
762 if (bfin_sport_uart_ports[pdev->id] == NULL) {
763 bfin_sport_uart_ports[pdev->id] =
f4d10ca8 764 kzalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
ccf68e59 765 sport = bfin_sport_uart_ports[pdev->id];
766 if (!sport) {
767 dev_err(&pdev->dev,
f4d10ca8 768 "Fail to malloc sport_uart_port\n");
ccf68e59 769 return -ENOMEM;
770 }
771
aaba105e
JH		 772 ret = peripheral_request_list(dev_get_platdata(&pdev->dev),
773 DRV_NAME);
ccf68e59 774 if (ret) {
775 dev_err(&pdev->dev,
776 "Fail to request SPORT peripherals\n");
777 goto out_error_free_mem;
778 }
779
780 spin_lock_init(&sport->port.lock);
781 sport->port.fifosize = SPORT_TX_FIFO_SIZE,
782 sport->port.ops = &sport_uart_ops;
783 sport->port.line = pdev->id;
784 sport->port.iotype = UPIO_MEM;
785 sport->port.flags = UPF_BOOT_AUTOCONF;
786
787 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
788 if (res == NULL) {
789 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
790 ret = -ENOENT;
791 goto out_error_free_peripherals;
792 }
793
e114474c 794 sport->port.membase = ioremap(res->start, resource_size(res));
ccf68e59 795 if (!sport->port.membase) {
796 dev_err(&pdev->dev, "Cannot map sport IO\n");
797 ret = -ENXIO;
798 goto out_error_free_peripherals;
799 }
e8126b32 800 sport->port.mapbase = res->start;
ccf68e59 801
802 sport->port.irq = platform_get_irq(pdev, 0);
940f3be4 803 if ((int)sport->port.irq < 0) {
ccf68e59 804 dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
805 ret = -ENOENT;
806 goto out_error_unmap;
807 }
808
809 sport->err_irq = platform_get_irq(pdev, 1);
810 if (sport->err_irq < 0) {
811 dev_err(&pdev->dev, "No sport status IRQ specified\n");
812 ret = -ENOENT;
813 goto out_error_unmap;
814 }
1f7d1c85
SZ		 815#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
816 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
817 if (res == NULL)
818 sport->cts_pin = -1;
8bd67d7d 819 else
1f7d1c85
SZ		 820 sport->cts_pin = res->start;
821
822 res = platform_get_resource(pdev, IORESOURCE_IO, 1);
823 if (res == NULL)
824 sport->rts_pin = -1;
825 else
826 sport->rts_pin = res->start;
1f7d1c85 827#endif
ccf68e59 828 }
829
830#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
831 if (!is_early_platform_device(pdev)) {
832#endif
833 sport = bfin_sport_uart_ports[pdev->id];
834 sport->port.dev = &pdev->dev;
835 dev_set_drvdata(&pdev->dev, sport);
836 ret = uart_add_one_port(&sport_uart_reg, &sport->port);
837#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
838 }
839#endif
840 if (!ret)
841 return 0;
842
843 if (sport) {
844out_error_unmap:
845 iounmap(sport->port.membase);
846out_error_free_peripherals:
aaba105e 847 peripheral_free_list(dev_get_platdata(&pdev->dev));
ccf68e59 848out_error_free_mem:
849 kfree(sport);
850 bfin_sport_uart_ports[pdev->id] = NULL;
851 }
852
853 return ret;
2f351741
BW		 854}
855
ae8d8a14 856static int sport_uart_remove(struct platform_device *pdev)
2f351741 857{
ccf68e59 858 struct sport_uart_port *sport = platform_get_drvdata(pdev);
2f351741 859
ccf68e59 860 dev_dbg(&pdev->dev, "%s enter\n", __func__);
861 dev_set_drvdata(&pdev->dev, NULL);
2f351741 862
ccf68e59 863 if (sport) {
2f351741 864 uart_remove_one_port(&sport_uart_reg, &sport->port);
ccf68e59 865 iounmap(sport->port.membase);
aaba105e 866 peripheral_free_list(dev_get_platdata(&pdev->dev));
ccf68e59 867 kfree(sport);
868 bfin_sport_uart_ports[pdev->id] = NULL;
869 }
2f351741
BW		 870
871 return 0;
872}
873
874static struct platform_driver sport_uart_driver = {
875 .probe = sport_uart_probe,
2d47b716 876 .remove = sport_uart_remove,
2f351741
BW		 877 .driver = {
878 .name = DRV_NAME,
ccf68e59 879#ifdef CONFIG_PM
880 .pm = &bfin_sport_uart_dev_pm_ops,
881#endif
2f351741
BW		 882 },
883};
884
ccf68e59 885#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
20246fdf 886static struct early_platform_driver early_sport_uart_driver __initdata = {
b59588aa 887 .class_str = CLASS_BFIN_SPORT_CONSOLE,
ccf68e59 888 .pdrv = &sport_uart_driver,
889 .requested_id = EARLY_PLATFORM_ID_UNSET,
890};
891
892static int __init sport_uart_rs_console_init(void)
893{
894 early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
895
b59588aa
SZ		 896 early_platform_driver_probe(CLASS_BFIN_SPORT_CONSOLE,
897 BFIN_SPORT_UART_MAX_PORTS, 0);
ccf68e59 898
899 register_console(&sport_uart_console);
900
901 return 0;
902}
903console_initcall(sport_uart_rs_console_init);
904#endif
905
2f351741
BW		 906static int __init sport_uart_init(void)
907{
908 int ret;
909
e8126b32 910 pr_info("Blackfin uart over sport driver\n");
ccf68e59 911
2f351741 912 ret = uart_register_driver(&sport_uart_reg);
ccf68e59 913 if (ret) {
914 pr_err("failed to register %s:%d\n",
2f351741
BW		 915 sport_uart_reg.driver_name, ret);
916 return ret;
917 }
918
919 ret = platform_driver_register(&sport_uart_driver);
ccf68e59 920 if (ret) {
921 pr_err("failed to register sport uart driver:%d\n", ret);
2f351741
BW		 922 uart_unregister_driver(&sport_uart_reg);
923 }
924
2f351741
BW		 925 return ret;
926}
ccf68e59 927module_init(sport_uart_init);
2f351741
BW		 928
929static void __exit sport_uart_exit(void)
930{
2f351741
BW		 931 platform_driver_unregister(&sport_uart_driver);
932 uart_unregister_driver(&sport_uart_reg);
933}
2f351741
BW		 934module_exit(sport_uart_exit);
935
ccf68e59 936MODULE_AUTHOR("Sonic Zhang, Roy Huang");
937MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
2f351741 938MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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