Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for CPM (SCC/SMC) serial ports; core driver |
3 | * | |
4 | * Based on arch/ppc/cpm2_io/uart.c by Dan Malek | |
5 | * Based on ppc8xx.c by Thomas Gleixner | |
6 | * Based on drivers/serial/amba.c by Russell King | |
7 | * | |
4c8d3d99 | 8 | * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2) |
1da177e4 | 9 | * Pantelis Antoniou (panto@intracom.gr) (CPM1) |
311c4627 | 10 | * |
7ae87036 | 11 | * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc. |
1da177e4 | 12 | * (C) 2004 Intracom, S.A. |
6e197696 | 13 | * (C) 2005-2006 MontaVista Software, Inc. |
0d844065 | 14 | * Vitaly Bordug <vbordug@ru.mvista.com> |
1da177e4 LT |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or | |
19 | * (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
29 | * | |
30 | */ | |
31 | ||
1da177e4 LT |
32 | #include <linux/module.h> |
33 | #include <linux/tty.h> | |
ee160a38 | 34 | #include <linux/tty_flip.h> |
1da177e4 LT |
35 | #include <linux/ioport.h> |
36 | #include <linux/init.h> | |
37 | #include <linux/serial.h> | |
38 | #include <linux/console.h> | |
39 | #include <linux/sysrq.h> | |
40 | #include <linux/device.h> | |
41 | #include <linux/bootmem.h> | |
42 | #include <linux/dma-mapping.h> | |
e27987cd | 43 | #include <linux/fs_uart_pd.h> |
5af50730 RH |
44 | #include <linux/of_address.h> |
45 | #include <linux/of_irq.h> | |
0b2a2e5b | 46 | #include <linux/of_platform.h> |
7485d26b LP |
47 | #include <linux/gpio.h> |
48 | #include <linux/of_gpio.h> | |
80776554 | 49 | #include <linux/clk.h> |
1da177e4 LT |
50 | |
51 | #include <asm/io.h> | |
52 | #include <asm/irq.h> | |
53 | #include <asm/delay.h> | |
3dd0dcbe | 54 | #include <asm/fs_pd.h> |
7ae87036 SW |
55 | #include <asm/udbg.h> |
56 | ||
1da177e4 LT |
57 | #if defined(CONFIG_SERIAL_CPM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
58 | #define SUPPORT_SYSRQ | |
59 | #endif | |
60 | ||
61 | #include <linux/serial_core.h> | |
62 | #include <linux/kernel.h> | |
63 | ||
64 | #include "cpm_uart.h" | |
65 | ||
1da177e4 LT |
66 | |
67 | /**************************************************************/ | |
68 | ||
69 | static int cpm_uart_tx_pump(struct uart_port *port); | |
70 | static void cpm_uart_init_smc(struct uart_cpm_port *pinfo); | |
71 | static void cpm_uart_init_scc(struct uart_cpm_port *pinfo); | |
72 | static void cpm_uart_initbd(struct uart_cpm_port *pinfo); | |
73 | ||
74 | /**************************************************************/ | |
75 | ||
59733ef7 | 76 | #define HW_BUF_SPD_THRESHOLD 2400 |
5b04ec4a | 77 | |
1da177e4 | 78 | /* |
311c4627 | 79 | * Check, if transmit buffers are processed |
1da177e4 LT |
80 | */ |
81 | static unsigned int cpm_uart_tx_empty(struct uart_port *port) | |
82 | { | |
83 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d | 84 | cbd_t __iomem *bdp = pinfo->tx_bd_base; |
1da177e4 LT |
85 | int ret = 0; |
86 | ||
87 | while (1) { | |
c1dcfd9d | 88 | if (in_be16(&bdp->cbd_sc) & BD_SC_READY) |
1da177e4 LT |
89 | break; |
90 | ||
c1dcfd9d | 91 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) { |
1da177e4 LT |
92 | ret = TIOCSER_TEMT; |
93 | break; | |
94 | } | |
95 | bdp++; | |
96 | } | |
97 | ||
98 | pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret); | |
99 | ||
100 | return ret; | |
101 | } | |
102 | ||
103 | static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
104 | { | |
7485d26b LP |
105 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; |
106 | ||
107 | if (pinfo->gpios[GPIO_RTS] >= 0) | |
108 | gpio_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS)); | |
109 | ||
110 | if (pinfo->gpios[GPIO_DTR] >= 0) | |
111 | gpio_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR)); | |
1da177e4 LT |
112 | } |
113 | ||
114 | static unsigned int cpm_uart_get_mctrl(struct uart_port *port) | |
115 | { | |
7485d26b LP |
116 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; |
117 | unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
118 | ||
119 | if (pinfo->gpios[GPIO_CTS] >= 0) { | |
120 | if (gpio_get_value(pinfo->gpios[GPIO_CTS])) | |
121 | mctrl &= ~TIOCM_CTS; | |
122 | } | |
123 | ||
124 | if (pinfo->gpios[GPIO_DSR] >= 0) { | |
125 | if (gpio_get_value(pinfo->gpios[GPIO_DSR])) | |
126 | mctrl &= ~TIOCM_DSR; | |
127 | } | |
128 | ||
129 | if (pinfo->gpios[GPIO_DCD] >= 0) { | |
130 | if (gpio_get_value(pinfo->gpios[GPIO_DCD])) | |
131 | mctrl &= ~TIOCM_CAR; | |
132 | } | |
133 | ||
134 | if (pinfo->gpios[GPIO_RI] >= 0) { | |
135 | if (!gpio_get_value(pinfo->gpios[GPIO_RI])) | |
136 | mctrl |= TIOCM_RNG; | |
137 | } | |
138 | ||
139 | return mctrl; | |
1da177e4 LT |
140 | } |
141 | ||
142 | /* | |
143 | * Stop transmitter | |
144 | */ | |
b129a8cc | 145 | static void cpm_uart_stop_tx(struct uart_port *port) |
1da177e4 LT |
146 | { |
147 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d SW |
148 | smc_t __iomem *smcp = pinfo->smcp; |
149 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
150 | |
151 | pr_debug("CPM uart[%d]:stop tx\n", port->line); | |
152 | ||
153 | if (IS_SMC(pinfo)) | |
c1dcfd9d | 154 | clrbits8(&smcp->smc_smcm, SMCM_TX); |
1da177e4 | 155 | else |
c1dcfd9d | 156 | clrbits16(&sccp->scc_sccm, UART_SCCM_TX); |
1da177e4 LT |
157 | } |
158 | ||
159 | /* | |
160 | * Start transmitter | |
161 | */ | |
b129a8cc | 162 | static void cpm_uart_start_tx(struct uart_port *port) |
1da177e4 LT |
163 | { |
164 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d SW |
165 | smc_t __iomem *smcp = pinfo->smcp; |
166 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
167 | |
168 | pr_debug("CPM uart[%d]:start tx\n", port->line); | |
169 | ||
170 | if (IS_SMC(pinfo)) { | |
c1dcfd9d | 171 | if (in_8(&smcp->smc_smcm) & SMCM_TX) |
1da177e4 LT |
172 | return; |
173 | } else { | |
c1dcfd9d | 174 | if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX) |
1da177e4 LT |
175 | return; |
176 | } | |
177 | ||
178 | if (cpm_uart_tx_pump(port) != 0) { | |
311c4627 | 179 | if (IS_SMC(pinfo)) { |
c1dcfd9d | 180 | setbits8(&smcp->smc_smcm, SMCM_TX); |
311c4627 | 181 | } else { |
c1dcfd9d | 182 | setbits16(&sccp->scc_sccm, UART_SCCM_TX); |
311c4627 | 183 | } |
1da177e4 LT |
184 | } |
185 | } | |
186 | ||
187 | /* | |
311c4627 | 188 | * Stop receiver |
1da177e4 LT |
189 | */ |
190 | static void cpm_uart_stop_rx(struct uart_port *port) | |
191 | { | |
192 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d SW |
193 | smc_t __iomem *smcp = pinfo->smcp; |
194 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
195 | |
196 | pr_debug("CPM uart[%d]:stop rx\n", port->line); | |
197 | ||
198 | if (IS_SMC(pinfo)) | |
c1dcfd9d | 199 | clrbits8(&smcp->smc_smcm, SMCM_RX); |
1da177e4 | 200 | else |
c1dcfd9d | 201 | clrbits16(&sccp->scc_sccm, UART_SCCM_RX); |
1da177e4 LT |
202 | } |
203 | ||
204 | /* | |
205 | * Enable Modem status interrupts | |
206 | */ | |
207 | static void cpm_uart_enable_ms(struct uart_port *port) | |
208 | { | |
209 | pr_debug("CPM uart[%d]:enable ms\n", port->line); | |
210 | } | |
211 | ||
212 | /* | |
311c4627 | 213 | * Generate a break. |
1da177e4 LT |
214 | */ |
215 | static void cpm_uart_break_ctl(struct uart_port *port, int break_state) | |
216 | { | |
217 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
1da177e4 LT |
218 | |
219 | pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line, | |
220 | break_state); | |
221 | ||
222 | if (break_state) | |
7ae87036 | 223 | cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); |
1da177e4 | 224 | else |
7ae87036 | 225 | cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); |
1da177e4 LT |
226 | } |
227 | ||
228 | /* | |
229 | * Transmit characters, refill buffer descriptor, if possible | |
230 | */ | |
7d12e780 | 231 | static void cpm_uart_int_tx(struct uart_port *port) |
1da177e4 LT |
232 | { |
233 | pr_debug("CPM uart[%d]:TX INT\n", port->line); | |
234 | ||
235 | cpm_uart_tx_pump(port); | |
236 | } | |
237 | ||
8e21d04c JW |
238 | #ifdef CONFIG_CONSOLE_POLL |
239 | static int serial_polled; | |
240 | #endif | |
241 | ||
1da177e4 LT |
242 | /* |
243 | * Receive characters | |
244 | */ | |
7d12e780 | 245 | static void cpm_uart_int_rx(struct uart_port *port) |
1da177e4 LT |
246 | { |
247 | int i; | |
c1dcfd9d SW |
248 | unsigned char ch; |
249 | u8 *cp; | |
227434f8 | 250 | struct tty_port *tport = &port->state->port; |
1da177e4 | 251 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; |
c1dcfd9d | 252 | cbd_t __iomem *bdp; |
1da177e4 LT |
253 | u16 status; |
254 | unsigned int flg; | |
255 | ||
256 | pr_debug("CPM uart[%d]:RX INT\n", port->line); | |
257 | ||
258 | /* Just loop through the closed BDs and copy the characters into | |
259 | * the buffer. | |
260 | */ | |
261 | bdp = pinfo->rx_cur; | |
262 | for (;;) { | |
8e21d04c JW |
263 | #ifdef CONFIG_CONSOLE_POLL |
264 | if (unlikely(serial_polled)) { | |
265 | serial_polled = 0; | |
266 | return; | |
267 | } | |
268 | #endif | |
1da177e4 | 269 | /* get status */ |
c1dcfd9d | 270 | status = in_be16(&bdp->cbd_sc); |
1da177e4 LT |
271 | /* If this one is empty, return happy */ |
272 | if (status & BD_SC_EMPTY) | |
273 | break; | |
274 | ||
275 | /* get number of characters, and check spce in flip-buffer */ | |
c1dcfd9d | 276 | i = in_be16(&bdp->cbd_datlen); |
1da177e4 | 277 | |
311c4627 | 278 | /* If we have not enough room in tty flip buffer, then we try |
1da177e4 LT |
279 | * later, which will be the next rx-interrupt or a timeout |
280 | */ | |
227434f8 | 281 | if (tty_buffer_request_room(tport, i) < i) { |
76a55431 VB |
282 | printk(KERN_WARNING "No room in flip buffer\n"); |
283 | return; | |
1da177e4 LT |
284 | } |
285 | ||
286 | /* get pointer */ | |
c1dcfd9d | 287 | cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
1da177e4 LT |
288 | |
289 | /* loop through the buffer */ | |
290 | while (i-- > 0) { | |
291 | ch = *cp++; | |
292 | port->icount.rx++; | |
293 | flg = TTY_NORMAL; | |
294 | ||
295 | if (status & | |
296 | (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) | |
297 | goto handle_error; | |
7d12e780 | 298 | if (uart_handle_sysrq_char(port, ch)) |
1da177e4 | 299 | continue; |
8e21d04c JW |
300 | #ifdef CONFIG_CONSOLE_POLL |
301 | if (unlikely(serial_polled)) { | |
302 | serial_polled = 0; | |
303 | return; | |
304 | } | |
305 | #endif | |
1da177e4 | 306 | error_return: |
92a19f9c | 307 | tty_insert_flip_char(tport, ch, flg); |
1da177e4 LT |
308 | |
309 | } /* End while (i--) */ | |
310 | ||
311 | /* This BD is ready to be used again. Clear status. get next */ | |
c1dcfd9d SW |
312 | clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR | |
313 | BD_SC_OV | BD_SC_ID); | |
314 | setbits16(&bdp->cbd_sc, BD_SC_EMPTY); | |
1da177e4 | 315 | |
c1dcfd9d | 316 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) |
1da177e4 LT |
317 | bdp = pinfo->rx_bd_base; |
318 | else | |
319 | bdp++; | |
311c4627 | 320 | |
1da177e4 LT |
321 | } /* End for (;;) */ |
322 | ||
323 | /* Write back buffer pointer */ | |
c1dcfd9d | 324 | pinfo->rx_cur = bdp; |
1da177e4 LT |
325 | |
326 | /* activate BH processing */ | |
2e124b4a | 327 | tty_flip_buffer_push(tport); |
1da177e4 LT |
328 | |
329 | return; | |
330 | ||
331 | /* Error processing */ | |
332 | ||
333 | handle_error: | |
334 | /* Statistics */ | |
335 | if (status & BD_SC_BR) | |
336 | port->icount.brk++; | |
337 | if (status & BD_SC_PR) | |
338 | port->icount.parity++; | |
339 | if (status & BD_SC_FR) | |
340 | port->icount.frame++; | |
341 | if (status & BD_SC_OV) | |
342 | port->icount.overrun++; | |
343 | ||
344 | /* Mask out ignored conditions */ | |
345 | status &= port->read_status_mask; | |
346 | ||
347 | /* Handle the remaining ones */ | |
348 | if (status & BD_SC_BR) | |
349 | flg = TTY_BREAK; | |
350 | else if (status & BD_SC_PR) | |
351 | flg = TTY_PARITY; | |
352 | else if (status & BD_SC_FR) | |
353 | flg = TTY_FRAME; | |
354 | ||
355 | /* overrun does not affect the current character ! */ | |
356 | if (status & BD_SC_OV) { | |
357 | ch = 0; | |
358 | flg = TTY_OVERRUN; | |
359 | /* We skip this buffer */ | |
360 | /* CHECK: Is really nothing senseful there */ | |
361 | /* ASSUMPTION: it contains nothing valid */ | |
362 | i = 0; | |
363 | } | |
364 | #ifdef SUPPORT_SYSRQ | |
365 | port->sysrq = 0; | |
366 | #endif | |
367 | goto error_return; | |
368 | } | |
369 | ||
370 | /* | |
371 | * Asynchron mode interrupt handler | |
372 | */ | |
7d12e780 | 373 | static irqreturn_t cpm_uart_int(int irq, void *data) |
1da177e4 LT |
374 | { |
375 | u8 events; | |
15aafa2f | 376 | struct uart_port *port = data; |
1da177e4 | 377 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; |
c1dcfd9d SW |
378 | smc_t __iomem *smcp = pinfo->smcp; |
379 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
380 | |
381 | pr_debug("CPM uart[%d]:IRQ\n", port->line); | |
382 | ||
383 | if (IS_SMC(pinfo)) { | |
c1dcfd9d SW |
384 | events = in_8(&smcp->smc_smce); |
385 | out_8(&smcp->smc_smce, events); | |
1da177e4 LT |
386 | if (events & SMCM_BRKE) |
387 | uart_handle_break(port); | |
388 | if (events & SMCM_RX) | |
7d12e780 | 389 | cpm_uart_int_rx(port); |
1da177e4 | 390 | if (events & SMCM_TX) |
7d12e780 | 391 | cpm_uart_int_tx(port); |
1da177e4 | 392 | } else { |
c1dcfd9d SW |
393 | events = in_be16(&sccp->scc_scce); |
394 | out_be16(&sccp->scc_scce, events); | |
1da177e4 LT |
395 | if (events & UART_SCCM_BRKE) |
396 | uart_handle_break(port); | |
397 | if (events & UART_SCCM_RX) | |
7d12e780 | 398 | cpm_uart_int_rx(port); |
1da177e4 | 399 | if (events & UART_SCCM_TX) |
7d12e780 | 400 | cpm_uart_int_tx(port); |
1da177e4 LT |
401 | } |
402 | return (events) ? IRQ_HANDLED : IRQ_NONE; | |
403 | } | |
404 | ||
405 | static int cpm_uart_startup(struct uart_port *port) | |
406 | { | |
407 | int retval; | |
408 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
409 | ||
410 | pr_debug("CPM uart[%d]:startup\n", port->line); | |
411 | ||
9ab92120 XF |
412 | /* If the port is not the console, make sure rx is disabled. */ |
413 | if (!(pinfo->flags & FLAG_CONSOLE)) { | |
414 | /* Disable UART rx */ | |
415 | if (IS_SMC(pinfo)) { | |
416 | clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN); | |
417 | clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX); | |
418 | } else { | |
419 | clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR); | |
420 | clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); | |
421 | } | |
725ef4a3 | 422 | cpm_uart_initbd(pinfo); |
9ab92120 XF |
423 | cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); |
424 | } | |
1da177e4 LT |
425 | /* Install interrupt handler. */ |
426 | retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port); | |
427 | if (retval) | |
428 | return retval; | |
429 | ||
430 | /* Startup rx-int */ | |
431 | if (IS_SMC(pinfo)) { | |
c1dcfd9d SW |
432 | setbits8(&pinfo->smcp->smc_smcm, SMCM_RX); |
433 | setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN)); | |
1da177e4 | 434 | } else { |
c1dcfd9d SW |
435 | setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); |
436 | setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT)); | |
1da177e4 LT |
437 | } |
438 | ||
439 | return 0; | |
440 | } | |
441 | ||
311c4627 KG |
442 | inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo) |
443 | { | |
638861d5 KG |
444 | set_current_state(TASK_UNINTERRUPTIBLE); |
445 | schedule_timeout(pinfo->wait_closing); | |
311c4627 KG |
446 | } |
447 | ||
1da177e4 LT |
448 | /* |
449 | * Shutdown the uart | |
450 | */ | |
451 | static void cpm_uart_shutdown(struct uart_port *port) | |
452 | { | |
453 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
1da177e4 LT |
454 | |
455 | pr_debug("CPM uart[%d]:shutdown\n", port->line); | |
456 | ||
457 | /* free interrupt handler */ | |
458 | free_irq(port->irq, port); | |
459 | ||
460 | /* If the port is not the console, disable Rx and Tx. */ | |
461 | if (!(pinfo->flags & FLAG_CONSOLE)) { | |
311c4627 | 462 | /* Wait for all the BDs marked sent */ |
638861d5 KG |
463 | while(!cpm_uart_tx_empty(port)) { |
464 | set_current_state(TASK_UNINTERRUPTIBLE); | |
311c4627 | 465 | schedule_timeout(2); |
638861d5 KG |
466 | } |
467 | ||
468 | if (pinfo->wait_closing) | |
311c4627 KG |
469 | cpm_uart_wait_until_send(pinfo); |
470 | ||
1da177e4 LT |
471 | /* Stop uarts */ |
472 | if (IS_SMC(pinfo)) { | |
c1dcfd9d SW |
473 | smc_t __iomem *smcp = pinfo->smcp; |
474 | clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); | |
475 | clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX); | |
1da177e4 | 476 | } else { |
c1dcfd9d SW |
477 | scc_t __iomem *sccp = pinfo->sccp; |
478 | clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
479 | clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); | |
1da177e4 LT |
480 | } |
481 | ||
482 | /* Shut them really down and reinit buffer descriptors */ | |
ae2d4c39 NL |
483 | if (IS_SMC(pinfo)) { |
484 | out_be16(&pinfo->smcup->smc_brkcr, 0); | |
7ae87036 | 485 | cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); |
ae2d4c39 NL |
486 | } else { |
487 | out_be16(&pinfo->sccup->scc_brkcr, 0); | |
7ae87036 | 488 | cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); |
ae2d4c39 | 489 | } |
61f5657c | 490 | |
1da177e4 LT |
491 | cpm_uart_initbd(pinfo); |
492 | } | |
493 | } | |
494 | ||
495 | static void cpm_uart_set_termios(struct uart_port *port, | |
1bda8f30 SW |
496 | struct ktermios *termios, |
497 | struct ktermios *old) | |
1da177e4 LT |
498 | { |
499 | int baud; | |
500 | unsigned long flags; | |
501 | u16 cval, scval, prev_mode; | |
502 | int bits, sbits; | |
503 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d SW |
504 | smc_t __iomem *smcp = pinfo->smcp; |
505 | scc_t __iomem *sccp = pinfo->sccp; | |
6e62bdc0 | 506 | int maxidl; |
1da177e4 LT |
507 | |
508 | pr_debug("CPM uart[%d]:set_termios\n", port->line); | |
509 | ||
510 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); | |
59733ef7 | 511 | if (baud < HW_BUF_SPD_THRESHOLD || |
d6c53c0e | 512 | (pinfo->port.state && pinfo->port.state->port.low_latency)) |
5b04ec4a BI |
513 | pinfo->rx_fifosize = 1; |
514 | else | |
515 | pinfo->rx_fifosize = RX_BUF_SIZE; | |
1da177e4 | 516 | |
6e62bdc0 CL |
517 | /* MAXIDL is the timeout after which a receive buffer is closed |
518 | * when not full if no more characters are received. | |
519 | * We calculate it from the baudrate so that the duration is | |
520 | * always the same at standard rates: about 4ms. | |
521 | */ | |
522 | maxidl = baud / 2400; | |
523 | if (maxidl < 1) | |
524 | maxidl = 1; | |
525 | if (maxidl > 0x10) | |
526 | maxidl = 0x10; | |
527 | ||
1da177e4 LT |
528 | /* Character length programmed into the mode register is the |
529 | * sum of: 1 start bit, number of data bits, 0 or 1 parity bit, | |
530 | * 1 or 2 stop bits, minus 1. | |
531 | * The value 'bits' counts this for us. | |
532 | */ | |
533 | cval = 0; | |
534 | scval = 0; | |
535 | ||
536 | /* byte size */ | |
537 | switch (termios->c_cflag & CSIZE) { | |
538 | case CS5: | |
539 | bits = 5; | |
540 | break; | |
541 | case CS6: | |
542 | bits = 6; | |
543 | break; | |
544 | case CS7: | |
545 | bits = 7; | |
546 | break; | |
547 | case CS8: | |
548 | bits = 8; | |
549 | break; | |
550 | /* Never happens, but GCC is too dumb to figure it out */ | |
551 | default: | |
552 | bits = 8; | |
553 | break; | |
554 | } | |
555 | sbits = bits - 5; | |
556 | ||
557 | if (termios->c_cflag & CSTOPB) { | |
558 | cval |= SMCMR_SL; /* Two stops */ | |
559 | scval |= SCU_PSMR_SL; | |
560 | bits++; | |
561 | } | |
562 | ||
563 | if (termios->c_cflag & PARENB) { | |
564 | cval |= SMCMR_PEN; | |
565 | scval |= SCU_PSMR_PEN; | |
566 | bits++; | |
567 | if (!(termios->c_cflag & PARODD)) { | |
568 | cval |= SMCMR_PM_EVEN; | |
569 | scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP); | |
570 | } | |
571 | } | |
572 | ||
dc320815 LP |
573 | /* |
574 | * Update the timeout | |
575 | */ | |
576 | uart_update_timeout(port, termios->c_cflag, baud); | |
577 | ||
1da177e4 LT |
578 | /* |
579 | * Set up parity check flag | |
580 | */ | |
581 | #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) | |
582 | ||
583 | port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV); | |
584 | if (termios->c_iflag & INPCK) | |
585 | port->read_status_mask |= BD_SC_FR | BD_SC_PR; | |
586 | if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK)) | |
587 | port->read_status_mask |= BD_SC_BR; | |
588 | ||
589 | /* | |
590 | * Characters to ignore | |
591 | */ | |
592 | port->ignore_status_mask = 0; | |
593 | if (termios->c_iflag & IGNPAR) | |
594 | port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; | |
595 | if (termios->c_iflag & IGNBRK) { | |
596 | port->ignore_status_mask |= BD_SC_BR; | |
597 | /* | |
598 | * If we're ignore parity and break indicators, ignore | |
599 | * overruns too. (For real raw support). | |
600 | */ | |
601 | if (termios->c_iflag & IGNPAR) | |
602 | port->ignore_status_mask |= BD_SC_OV; | |
603 | } | |
604 | /* | |
605 | * !!! ignore all characters if CREAD is not set | |
606 | */ | |
607 | if ((termios->c_cflag & CREAD) == 0) | |
608 | port->read_status_mask &= ~BD_SC_EMPTY; | |
311c4627 | 609 | |
1da177e4 LT |
610 | spin_lock_irqsave(&port->lock, flags); |
611 | ||
612 | /* Start bit has not been added (so don't, because we would just | |
613 | * subtract it later), and we need to add one for the number of | |
614 | * stops bits (there is always at least one). | |
615 | */ | |
616 | bits++; | |
617 | if (IS_SMC(pinfo)) { | |
5b04ec4a BI |
618 | /* |
619 | * MRBLR can be changed while an SMC/SCC is operating only | |
620 | * if it is done in a single bus cycle with one 16-bit move | |
621 | * (not two 8-bit bus cycles back-to-back). This occurs when | |
622 | * the cp shifts control to the next RxBD, so the change does | |
623 | * not take effect immediately. To guarantee the exact RxBD | |
624 | * on which the change occurs, change MRBLR only while the | |
625 | * SMC/SCC receiver is disabled. | |
626 | */ | |
627 | out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize); | |
6e62bdc0 | 628 | out_be16(&pinfo->smcup->smc_maxidl, maxidl); |
5b04ec4a | 629 | |
1da177e4 LT |
630 | /* Set the mode register. We want to keep a copy of the |
631 | * enables, because we want to put them back if they were | |
632 | * present. | |
633 | */ | |
ae2d4c39 NL |
634 | prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN); |
635 | /* Output in *one* operation, so we don't interrupt RX/TX if they | |
636 | * were already enabled. */ | |
637 | out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval | | |
638 | SMCMR_SM_UART | prev_mode); | |
1da177e4 | 639 | } else { |
5b04ec4a | 640 | out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); |
6e62bdc0 | 641 | out_be16(&pinfo->sccup->scc_maxidl, maxidl); |
c1dcfd9d | 642 | out_be16(&sccp->scc_psmr, (sbits << 12) | scval); |
1da177e4 LT |
643 | } |
644 | ||
80776554 LP |
645 | if (pinfo->clk) |
646 | clk_set_rate(pinfo->clk, baud); | |
647 | else | |
648 | cpm_set_brg(pinfo->brg - 1, baud); | |
1da177e4 | 649 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
650 | } |
651 | ||
652 | static const char *cpm_uart_type(struct uart_port *port) | |
653 | { | |
654 | pr_debug("CPM uart[%d]:uart_type\n", port->line); | |
655 | ||
656 | return port->type == PORT_CPM ? "CPM UART" : NULL; | |
657 | } | |
658 | ||
659 | /* | |
660 | * verify the new serial_struct (for TIOCSSERIAL). | |
661 | */ | |
662 | static int cpm_uart_verify_port(struct uart_port *port, | |
663 | struct serial_struct *ser) | |
664 | { | |
665 | int ret = 0; | |
666 | ||
667 | pr_debug("CPM uart[%d]:verify_port\n", port->line); | |
668 | ||
669 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) | |
670 | ret = -EINVAL; | |
a62c4133 | 671 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
672 | ret = -EINVAL; |
673 | if (ser->baud_base < 9600) | |
674 | ret = -EINVAL; | |
675 | return ret; | |
676 | } | |
677 | ||
678 | /* | |
679 | * Transmit characters, refill buffer descriptor, if possible | |
680 | */ | |
681 | static int cpm_uart_tx_pump(struct uart_port *port) | |
682 | { | |
c1dcfd9d SW |
683 | cbd_t __iomem *bdp; |
684 | u8 *p; | |
1da177e4 LT |
685 | int count; |
686 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
09dd3fc1 | 687 | struct circ_buf *xmit = &port->state->xmit; |
1da177e4 LT |
688 | |
689 | /* Handle xon/xoff */ | |
690 | if (port->x_char) { | |
691 | /* Pick next descriptor and fill from buffer */ | |
692 | bdp = pinfo->tx_cur; | |
693 | ||
c1dcfd9d | 694 | p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
311c4627 | 695 | |
03929c76 | 696 | *p++ = port->x_char; |
c1dcfd9d SW |
697 | |
698 | out_be16(&bdp->cbd_datlen, 1); | |
699 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1da177e4 | 700 | /* Get next BD. */ |
c1dcfd9d | 701 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) |
1da177e4 LT |
702 | bdp = pinfo->tx_bd_base; |
703 | else | |
704 | bdp++; | |
705 | pinfo->tx_cur = bdp; | |
706 | ||
707 | port->icount.tx++; | |
708 | port->x_char = 0; | |
709 | return 1; | |
710 | } | |
711 | ||
712 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
b129a8cc | 713 | cpm_uart_stop_tx(port); |
1da177e4 LT |
714 | return 0; |
715 | } | |
716 | ||
717 | /* Pick next descriptor and fill from buffer */ | |
718 | bdp = pinfo->tx_cur; | |
719 | ||
c1dcfd9d SW |
720 | while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) && |
721 | xmit->tail != xmit->head) { | |
1da177e4 | 722 | count = 0; |
c1dcfd9d | 723 | p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
1da177e4 LT |
724 | while (count < pinfo->tx_fifosize) { |
725 | *p++ = xmit->buf[xmit->tail]; | |
726 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
727 | port->icount.tx++; | |
728 | count++; | |
729 | if (xmit->head == xmit->tail) | |
730 | break; | |
731 | } | |
c1dcfd9d SW |
732 | out_be16(&bdp->cbd_datlen, count); |
733 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1da177e4 | 734 | /* Get next BD. */ |
c1dcfd9d | 735 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) |
1da177e4 LT |
736 | bdp = pinfo->tx_bd_base; |
737 | else | |
738 | bdp++; | |
739 | } | |
740 | pinfo->tx_cur = bdp; | |
741 | ||
742 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
743 | uart_write_wakeup(port); | |
744 | ||
745 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 746 | cpm_uart_stop_tx(port); |
1da177e4 LT |
747 | return 0; |
748 | } | |
749 | ||
750 | return 1; | |
751 | } | |
752 | ||
753 | /* | |
754 | * init buffer descriptors | |
755 | */ | |
756 | static void cpm_uart_initbd(struct uart_cpm_port *pinfo) | |
757 | { | |
758 | int i; | |
759 | u8 *mem_addr; | |
c1dcfd9d | 760 | cbd_t __iomem *bdp; |
1da177e4 LT |
761 | |
762 | pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line); | |
763 | ||
764 | /* Set the physical address of the host memory | |
765 | * buffers in the buffer descriptors, and the | |
766 | * virtual address for us to work with. | |
767 | */ | |
768 | mem_addr = pinfo->mem_addr; | |
769 | bdp = pinfo->rx_cur = pinfo->rx_bd_base; | |
770 | for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) { | |
c1dcfd9d SW |
771 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
772 | out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT); | |
1da177e4 LT |
773 | mem_addr += pinfo->rx_fifosize; |
774 | } | |
311c4627 | 775 | |
c1dcfd9d SW |
776 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
777 | out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT); | |
1da177e4 LT |
778 | |
779 | /* Set the physical address of the host memory | |
780 | * buffers in the buffer descriptors, and the | |
781 | * virtual address for us to work with. | |
782 | */ | |
783 | mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize); | |
784 | bdp = pinfo->tx_cur = pinfo->tx_bd_base; | |
785 | for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) { | |
c1dcfd9d SW |
786 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
787 | out_be16(&bdp->cbd_sc, BD_SC_INTRPT); | |
1da177e4 LT |
788 | mem_addr += pinfo->tx_fifosize; |
789 | } | |
311c4627 | 790 | |
c1dcfd9d SW |
791 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
792 | out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT); | |
1da177e4 LT |
793 | } |
794 | ||
795 | static void cpm_uart_init_scc(struct uart_cpm_port *pinfo) | |
796 | { | |
c1dcfd9d SW |
797 | scc_t __iomem *scp; |
798 | scc_uart_t __iomem *sup; | |
1da177e4 LT |
799 | |
800 | pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line); | |
801 | ||
802 | scp = pinfo->sccp; | |
803 | sup = pinfo->sccup; | |
804 | ||
805 | /* Store address */ | |
c1dcfd9d SW |
806 | out_be16(&pinfo->sccup->scc_genscc.scc_rbase, |
807 | (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); | |
808 | out_be16(&pinfo->sccup->scc_genscc.scc_tbase, | |
809 | (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); | |
1da177e4 LT |
810 | |
811 | /* Set up the uart parameters in the | |
812 | * parameter ram. | |
813 | */ | |
814 | ||
815 | cpm_set_scc_fcr(sup); | |
816 | ||
c1dcfd9d | 817 | out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); |
fbbb9d96 | 818 | out_be16(&sup->scc_maxidl, 0x10); |
c1dcfd9d SW |
819 | out_be16(&sup->scc_brkcr, 1); |
820 | out_be16(&sup->scc_parec, 0); | |
821 | out_be16(&sup->scc_frmec, 0); | |
822 | out_be16(&sup->scc_nosec, 0); | |
823 | out_be16(&sup->scc_brkec, 0); | |
824 | out_be16(&sup->scc_uaddr1, 0); | |
825 | out_be16(&sup->scc_uaddr2, 0); | |
826 | out_be16(&sup->scc_toseq, 0); | |
827 | out_be16(&sup->scc_char1, 0x8000); | |
828 | out_be16(&sup->scc_char2, 0x8000); | |
829 | out_be16(&sup->scc_char3, 0x8000); | |
830 | out_be16(&sup->scc_char4, 0x8000); | |
831 | out_be16(&sup->scc_char5, 0x8000); | |
832 | out_be16(&sup->scc_char6, 0x8000); | |
833 | out_be16(&sup->scc_char7, 0x8000); | |
834 | out_be16(&sup->scc_char8, 0x8000); | |
835 | out_be16(&sup->scc_rccm, 0xc0ff); | |
1da177e4 LT |
836 | |
837 | /* Send the CPM an initialize command. | |
838 | */ | |
7ae87036 | 839 | cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); |
1da177e4 LT |
840 | |
841 | /* Set UART mode, 8 bit, no parity, one stop. | |
842 | * Enable receive and transmit. | |
843 | */ | |
c1dcfd9d SW |
844 | out_be32(&scp->scc_gsmrh, 0); |
845 | out_be32(&scp->scc_gsmrl, | |
846 | SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); | |
1da177e4 LT |
847 | |
848 | /* Enable rx interrupts and clear all pending events. */ | |
c1dcfd9d SW |
849 | out_be16(&scp->scc_sccm, 0); |
850 | out_be16(&scp->scc_scce, 0xffff); | |
851 | out_be16(&scp->scc_dsr, 0x7e7e); | |
852 | out_be16(&scp->scc_psmr, 0x3000); | |
1da177e4 | 853 | |
c1dcfd9d | 854 | setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); |
1da177e4 LT |
855 | } |
856 | ||
857 | static void cpm_uart_init_smc(struct uart_cpm_port *pinfo) | |
858 | { | |
c1dcfd9d SW |
859 | smc_t __iomem *sp; |
860 | smc_uart_t __iomem *up; | |
1da177e4 LT |
861 | |
862 | pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line); | |
863 | ||
864 | sp = pinfo->smcp; | |
865 | up = pinfo->smcup; | |
866 | ||
867 | /* Store address */ | |
c1dcfd9d SW |
868 | out_be16(&pinfo->smcup->smc_rbase, |
869 | (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); | |
870 | out_be16(&pinfo->smcup->smc_tbase, | |
871 | (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); | |
1da177e4 LT |
872 | |
873 | /* | |
874 | * In case SMC1 is being relocated... | |
875 | */ | |
876 | #if defined (CONFIG_I2C_SPI_SMC1_UCODE_PATCH) | |
c1dcfd9d SW |
877 | out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase)); |
878 | out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase)); | |
879 | out_be32(&up->smc_rstate, 0); | |
880 | out_be32(&up->smc_tstate, 0); | |
881 | out_be16(&up->smc_brkcr, 1); /* number of break chars */ | |
882 | out_be16(&up->smc_brkec, 0); | |
1da177e4 LT |
883 | #endif |
884 | ||
885 | /* Set up the uart parameters in the | |
886 | * parameter ram. | |
887 | */ | |
888 | cpm_set_smc_fcr(up); | |
889 | ||
b770ffd4 | 890 | /* Using idle character time requires some additional tuning. */ |
c1dcfd9d | 891 | out_be16(&up->smc_mrblr, pinfo->rx_fifosize); |
fbbb9d96 | 892 | out_be16(&up->smc_maxidl, 0x10); |
c1dcfd9d SW |
893 | out_be16(&up->smc_brklen, 0); |
894 | out_be16(&up->smc_brkec, 0); | |
895 | out_be16(&up->smc_brkcr, 1); | |
1da177e4 | 896 | |
7ae87036 | 897 | cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); |
1da177e4 LT |
898 | |
899 | /* Set UART mode, 8 bit, no parity, one stop. | |
900 | * Enable receive and transmit. | |
901 | */ | |
c1dcfd9d | 902 | out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART); |
1da177e4 LT |
903 | |
904 | /* Enable only rx interrupts clear all pending events. */ | |
c1dcfd9d SW |
905 | out_8(&sp->smc_smcm, 0); |
906 | out_8(&sp->smc_smce, 0xff); | |
1da177e4 | 907 | |
c1dcfd9d | 908 | setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN); |
1da177e4 LT |
909 | } |
910 | ||
911 | /* | |
912 | * Initialize port. This is called from early_console stuff | |
913 | * so we have to be careful here ! | |
914 | */ | |
915 | static int cpm_uart_request_port(struct uart_port *port) | |
916 | { | |
917 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
918 | int ret; | |
919 | ||
920 | pr_debug("CPM uart[%d]:request port\n", port->line); | |
921 | ||
922 | if (pinfo->flags & FLAG_CONSOLE) | |
923 | return 0; | |
924 | ||
1da177e4 | 925 | if (IS_SMC(pinfo)) { |
c1dcfd9d SW |
926 | clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); |
927 | clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); | |
1da177e4 | 928 | } else { |
c1dcfd9d SW |
929 | clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); |
930 | clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
1da177e4 LT |
931 | } |
932 | ||
933 | ret = cpm_uart_allocbuf(pinfo, 0); | |
934 | ||
935 | if (ret) | |
936 | return ret; | |
937 | ||
938 | cpm_uart_initbd(pinfo); | |
311c4627 KG |
939 | if (IS_SMC(pinfo)) |
940 | cpm_uart_init_smc(pinfo); | |
941 | else | |
942 | cpm_uart_init_scc(pinfo); | |
1da177e4 LT |
943 | |
944 | return 0; | |
945 | } | |
946 | ||
947 | static void cpm_uart_release_port(struct uart_port *port) | |
948 | { | |
949 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
950 | ||
951 | if (!(pinfo->flags & FLAG_CONSOLE)) | |
952 | cpm_uart_freebuf(pinfo); | |
953 | } | |
954 | ||
955 | /* | |
956 | * Configure/autoconfigure the port. | |
957 | */ | |
958 | static void cpm_uart_config_port(struct uart_port *port, int flags) | |
959 | { | |
960 | pr_debug("CPM uart[%d]:config_port\n", port->line); | |
961 | ||
962 | if (flags & UART_CONFIG_TYPE) { | |
963 | port->type = PORT_CPM; | |
964 | cpm_uart_request_port(port); | |
965 | } | |
966 | } | |
8e21d04c | 967 | |
8cd774ad DD |
968 | #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE) |
969 | /* | |
970 | * Write a string to the serial port | |
971 | * Note that this is called with interrupts already disabled | |
972 | */ | |
973 | static void cpm_uart_early_write(struct uart_cpm_port *pinfo, | |
974 | const char *string, u_int count) | |
975 | { | |
976 | unsigned int i; | |
977 | cbd_t __iomem *bdp, *bdbase; | |
978 | unsigned char *cpm_outp_addr; | |
979 | ||
980 | /* Get the address of the host memory buffer. | |
981 | */ | |
982 | bdp = pinfo->tx_cur; | |
983 | bdbase = pinfo->tx_bd_base; | |
984 | ||
985 | /* | |
986 | * Now, do each character. This is not as bad as it looks | |
987 | * since this is a holding FIFO and not a transmitting FIFO. | |
988 | * We could add the complexity of filling the entire transmit | |
989 | * buffer, but we would just wait longer between accesses...... | |
990 | */ | |
991 | for (i = 0; i < count; i++, string++) { | |
992 | /* Wait for transmitter fifo to empty. | |
993 | * Ready indicates output is ready, and xmt is doing | |
994 | * that, not that it is ready for us to send. | |
995 | */ | |
996 | while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) | |
997 | ; | |
998 | ||
999 | /* Send the character out. | |
1000 | * If the buffer address is in the CPM DPRAM, don't | |
1001 | * convert it. | |
1002 | */ | |
1003 | cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), | |
1004 | pinfo); | |
1005 | *cpm_outp_addr = *string; | |
1006 | ||
1007 | out_be16(&bdp->cbd_datlen, 1); | |
1008 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1009 | ||
1010 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) | |
1011 | bdp = bdbase; | |
1012 | else | |
1013 | bdp++; | |
1014 | ||
1015 | /* if a LF, also do CR... */ | |
1016 | if (*string == 10) { | |
1017 | while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) | |
1018 | ; | |
1019 | ||
1020 | cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), | |
1021 | pinfo); | |
1022 | *cpm_outp_addr = 13; | |
1023 | ||
1024 | out_be16(&bdp->cbd_datlen, 1); | |
1025 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1026 | ||
1027 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) | |
1028 | bdp = bdbase; | |
1029 | else | |
1030 | bdp++; | |
1031 | } | |
1032 | } | |
1033 | ||
1034 | /* | |
1035 | * Finally, Wait for transmitter & holding register to empty | |
1036 | * and restore the IER | |
1037 | */ | |
1038 | while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) | |
1039 | ; | |
1040 | ||
1041 | pinfo->tx_cur = bdp; | |
1042 | } | |
1043 | #endif | |
1044 | ||
8e21d04c JW |
1045 | #ifdef CONFIG_CONSOLE_POLL |
1046 | /* Serial polling routines for writing and reading from the uart while | |
1047 | * in an interrupt or debug context. | |
1048 | */ | |
1049 | ||
1050 | #define GDB_BUF_SIZE 512 /* power of 2, please */ | |
1051 | ||
1052 | static char poll_buf[GDB_BUF_SIZE]; | |
1053 | static char *pollp; | |
1054 | static int poll_chars; | |
1055 | ||
1056 | static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo) | |
1057 | { | |
1058 | u_char c, *cp; | |
1059 | volatile cbd_t *bdp; | |
1060 | int i; | |
1061 | ||
1062 | /* Get the address of the host memory buffer. | |
1063 | */ | |
1064 | bdp = pinfo->rx_cur; | |
1065 | while (bdp->cbd_sc & BD_SC_EMPTY) | |
1066 | ; | |
1067 | ||
1068 | /* If the buffer address is in the CPM DPRAM, don't | |
1069 | * convert it. | |
1070 | */ | |
1071 | cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo); | |
1072 | ||
1073 | if (obuf) { | |
1074 | i = c = bdp->cbd_datlen; | |
1075 | while (i-- > 0) | |
1076 | *obuf++ = *cp++; | |
1077 | } else | |
1078 | c = *cp; | |
1079 | bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID); | |
1080 | bdp->cbd_sc |= BD_SC_EMPTY; | |
1081 | ||
1082 | if (bdp->cbd_sc & BD_SC_WRAP) | |
1083 | bdp = pinfo->rx_bd_base; | |
1084 | else | |
1085 | bdp++; | |
1086 | pinfo->rx_cur = (cbd_t *)bdp; | |
1087 | ||
1088 | return (int)c; | |
1089 | } | |
1090 | ||
1091 | static int cpm_get_poll_char(struct uart_port *port) | |
1092 | { | |
1093 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
1094 | ||
1095 | if (!serial_polled) { | |
1096 | serial_polled = 1; | |
1097 | poll_chars = 0; | |
1098 | } | |
1099 | if (poll_chars <= 0) { | |
1100 | poll_chars = poll_wait_key(poll_buf, pinfo); | |
1101 | pollp = poll_buf; | |
1102 | } | |
1103 | poll_chars--; | |
1104 | return *pollp++; | |
1105 | } | |
1106 | ||
1107 | static void cpm_put_poll_char(struct uart_port *port, | |
1108 | unsigned char c) | |
1109 | { | |
1110 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
1111 | static char ch[2]; | |
1112 | ||
1113 | ch[0] = (char)c; | |
8cd774ad | 1114 | cpm_uart_early_write(pinfo, ch, 1); |
8e21d04c JW |
1115 | } |
1116 | #endif /* CONFIG_CONSOLE_POLL */ | |
1117 | ||
1da177e4 LT |
1118 | static struct uart_ops cpm_uart_pops = { |
1119 | .tx_empty = cpm_uart_tx_empty, | |
1120 | .set_mctrl = cpm_uart_set_mctrl, | |
1121 | .get_mctrl = cpm_uart_get_mctrl, | |
1122 | .stop_tx = cpm_uart_stop_tx, | |
1123 | .start_tx = cpm_uart_start_tx, | |
1124 | .stop_rx = cpm_uart_stop_rx, | |
1125 | .enable_ms = cpm_uart_enable_ms, | |
1126 | .break_ctl = cpm_uart_break_ctl, | |
1127 | .startup = cpm_uart_startup, | |
1128 | .shutdown = cpm_uart_shutdown, | |
1129 | .set_termios = cpm_uart_set_termios, | |
1130 | .type = cpm_uart_type, | |
1131 | .release_port = cpm_uart_release_port, | |
1132 | .request_port = cpm_uart_request_port, | |
1133 | .config_port = cpm_uart_config_port, | |
1134 | .verify_port = cpm_uart_verify_port, | |
8e21d04c JW |
1135 | #ifdef CONFIG_CONSOLE_POLL |
1136 | .poll_get_char = cpm_get_poll_char, | |
1137 | .poll_put_char = cpm_put_poll_char, | |
1138 | #endif | |
1da177e4 LT |
1139 | }; |
1140 | ||
7ae87036 SW |
1141 | struct uart_cpm_port cpm_uart_ports[UART_NR]; |
1142 | ||
c1dcfd9d SW |
1143 | static int cpm_uart_init_port(struct device_node *np, |
1144 | struct uart_cpm_port *pinfo) | |
7ae87036 SW |
1145 | { |
1146 | const u32 *data; | |
c1dcfd9d | 1147 | void __iomem *mem, *pram; |
7ae87036 SW |
1148 | int len; |
1149 | int ret; | |
7485d26b | 1150 | int i; |
7ae87036 | 1151 | |
80776554 LP |
1152 | data = of_get_property(np, "clock", NULL); |
1153 | if (data) { | |
1154 | struct clk *clk = clk_get(NULL, (const char*)data); | |
1155 | if (!IS_ERR(clk)) | |
1156 | pinfo->clk = clk; | |
1157 | } | |
1158 | if (!pinfo->clk) { | |
1159 | data = of_get_property(np, "fsl,cpm-brg", &len); | |
1160 | if (!data || len != 4) { | |
1161 | printk(KERN_ERR "CPM UART %s has no/invalid " | |
1162 | "fsl,cpm-brg property.\n", np->name); | |
1163 | return -EINVAL; | |
1164 | } | |
1165 | pinfo->brg = *data; | |
7ae87036 | 1166 | } |
7ae87036 SW |
1167 | |
1168 | data = of_get_property(np, "fsl,cpm-command", &len); | |
1169 | if (!data || len != 4) { | |
1170 | printk(KERN_ERR "CPM UART %s has no/invalid " | |
1171 | "fsl,cpm-command property.\n", np->name); | |
1172 | return -EINVAL; | |
1173 | } | |
1174 | pinfo->command = *data; | |
1175 | ||
1176 | mem = of_iomap(np, 0); | |
1177 | if (!mem) | |
1178 | return -ENOMEM; | |
1179 | ||
7ae87036 SW |
1180 | if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") || |
1181 | of_device_is_compatible(np, "fsl,cpm2-scc-uart")) { | |
1182 | pinfo->sccp = mem; | |
d464df26 | 1183 | pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np); |
7ae87036 SW |
1184 | } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") || |
1185 | of_device_is_compatible(np, "fsl,cpm2-smc-uart")) { | |
1186 | pinfo->flags |= FLAG_SMC; | |
1187 | pinfo->smcp = mem; | |
d464df26 | 1188 | pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np); |
7ae87036 SW |
1189 | } else { |
1190 | ret = -ENODEV; | |
d464df26 LP |
1191 | goto out_mem; |
1192 | } | |
1193 | ||
1194 | if (!pram) { | |
1195 | ret = -ENOMEM; | |
1196 | goto out_mem; | |
7ae87036 SW |
1197 | } |
1198 | ||
1199 | pinfo->tx_nrfifos = TX_NUM_FIFO; | |
1200 | pinfo->tx_fifosize = TX_BUF_SIZE; | |
1201 | pinfo->rx_nrfifos = RX_NUM_FIFO; | |
1202 | pinfo->rx_fifosize = RX_BUF_SIZE; | |
1203 | ||
1204 | pinfo->port.uartclk = ppc_proc_freq; | |
1205 | pinfo->port.mapbase = (unsigned long)mem; | |
1206 | pinfo->port.type = PORT_CPM; | |
1207 | pinfo->port.ops = &cpm_uart_pops, | |
1208 | pinfo->port.iotype = UPIO_MEM; | |
dc320815 | 1209 | pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize; |
7ae87036 SW |
1210 | spin_lock_init(&pinfo->port.lock); |
1211 | ||
1212 | pinfo->port.irq = of_irq_to_resource(np, 0, NULL); | |
1213 | if (pinfo->port.irq == NO_IRQ) { | |
1214 | ret = -EINVAL; | |
1215 | goto out_pram; | |
1216 | } | |
1217 | ||
a416bfa2 CL |
1218 | for (i = 0; i < NUM_GPIOS; i++) { |
1219 | int gpio; | |
1220 | ||
1221 | pinfo->gpios[i] = -1; | |
1222 | ||
1223 | gpio = of_get_gpio(np, i); | |
1224 | ||
1225 | if (gpio_is_valid(gpio)) { | |
1226 | ret = gpio_request(gpio, "cpm_uart"); | |
1227 | if (ret) { | |
1228 | pr_err("can't request gpio #%d: %d\n", i, ret); | |
1229 | continue; | |
1230 | } | |
1231 | if (i == GPIO_RTS || i == GPIO_DTR) | |
1232 | ret = gpio_direction_output(gpio, 0); | |
1233 | else | |
1234 | ret = gpio_direction_input(gpio); | |
1235 | if (ret) { | |
1236 | pr_err("can't set direction for gpio #%d: %d\n", | |
1237 | i, ret); | |
1238 | gpio_free(gpio); | |
1239 | continue; | |
1240 | } | |
1241 | pinfo->gpios[i] = gpio; | |
1242 | } | |
1243 | } | |
7485d26b | 1244 | |
4d8107f4 SW |
1245 | #ifdef CONFIG_PPC_EARLY_DEBUG_CPM |
1246 | udbg_putc = NULL; | |
1247 | #endif | |
1248 | ||
7ae87036 SW |
1249 | return cpm_uart_request_port(&pinfo->port); |
1250 | ||
1251 | out_pram: | |
d464df26 | 1252 | cpm_uart_unmap_pram(pinfo, pram); |
7ae87036 SW |
1253 | out_mem: |
1254 | iounmap(mem); | |
1255 | return ret; | |
1256 | } | |
1257 | ||
1da177e4 LT |
1258 | #ifdef CONFIG_SERIAL_CPM_CONSOLE |
1259 | /* | |
1260 | * Print a string to the serial port trying not to disturb | |
1261 | * any possible real use of the port... | |
1262 | * | |
1263 | * Note that this is called with interrupts already disabled | |
1264 | */ | |
1265 | static void cpm_uart_console_write(struct console *co, const char *s, | |
1266 | u_int count) | |
1267 | { | |
7ae87036 | 1268 | struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index]; |
491a7a43 RT |
1269 | unsigned long flags; |
1270 | int nolock = oops_in_progress; | |
1271 | ||
1272 | if (unlikely(nolock)) { | |
1273 | local_irq_save(flags); | |
1274 | } else { | |
1275 | spin_lock_irqsave(&pinfo->port.lock, flags); | |
1276 | } | |
1da177e4 | 1277 | |
8cd774ad | 1278 | cpm_uart_early_write(pinfo, s, count); |
491a7a43 RT |
1279 | |
1280 | if (unlikely(nolock)) { | |
1281 | local_irq_restore(flags); | |
1282 | } else { | |
1283 | spin_unlock_irqrestore(&pinfo->port.lock, flags); | |
1284 | } | |
1da177e4 LT |
1285 | } |
1286 | ||
e27987cd | 1287 | |
1da177e4 LT |
1288 | static int __init cpm_uart_console_setup(struct console *co, char *options) |
1289 | { | |
1da177e4 LT |
1290 | int baud = 38400; |
1291 | int bits = 8; | |
1292 | int parity = 'n'; | |
1293 | int flow = 'n'; | |
1294 | int ret; | |
7ae87036 SW |
1295 | struct uart_cpm_port *pinfo; |
1296 | struct uart_port *port; | |
1297 | ||
7ae87036 SW |
1298 | struct device_node *np = NULL; |
1299 | int i = 0; | |
1300 | ||
1301 | if (co->index >= UART_NR) { | |
1302 | printk(KERN_ERR "cpm_uart: console index %d too high\n", | |
1303 | co->index); | |
1304 | return -ENODEV; | |
1305 | } | |
1306 | ||
1307 | do { | |
1308 | np = of_find_node_by_type(np, "serial"); | |
1309 | if (!np) | |
1310 | return -ENODEV; | |
1311 | ||
1312 | if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") && | |
1313 | !of_device_is_compatible(np, "fsl,cpm1-scc-uart") && | |
1314 | !of_device_is_compatible(np, "fsl,cpm2-smc-uart") && | |
1315 | !of_device_is_compatible(np, "fsl,cpm2-scc-uart")) | |
1316 | i--; | |
1317 | } while (i++ != co->index); | |
1318 | ||
1319 | pinfo = &cpm_uart_ports[co->index]; | |
1320 | ||
1321 | pinfo->flags |= FLAG_CONSOLE; | |
1322 | port = &pinfo->port; | |
1323 | ||
1324 | ret = cpm_uart_init_port(np, pinfo); | |
1325 | of_node_put(np); | |
1326 | if (ret) | |
1327 | return ret; | |
1328 | ||
1da177e4 LT |
1329 | if (options) { |
1330 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1331 | } else { | |
3dd0dcbe | 1332 | if ((baud = uart_baudrate()) == -1) |
1da177e4 LT |
1333 | baud = 9600; |
1334 | } | |
1335 | ||
1da177e4 | 1336 | if (IS_SMC(pinfo)) { |
ae2d4c39 NL |
1337 | out_be16(&pinfo->smcup->smc_brkcr, 0); |
1338 | cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); | |
c1dcfd9d SW |
1339 | clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); |
1340 | clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); | |
1da177e4 | 1341 | } else { |
ae2d4c39 NL |
1342 | out_be16(&pinfo->sccup->scc_brkcr, 0); |
1343 | cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); | |
c1dcfd9d SW |
1344 | clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); |
1345 | clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
1da177e4 LT |
1346 | } |
1347 | ||
1348 | ret = cpm_uart_allocbuf(pinfo, 1); | |
1349 | ||
1350 | if (ret) | |
1351 | return ret; | |
1352 | ||
1353 | cpm_uart_initbd(pinfo); | |
1354 | ||
1355 | if (IS_SMC(pinfo)) | |
1356 | cpm_uart_init_smc(pinfo); | |
1357 | else | |
1358 | cpm_uart_init_scc(pinfo); | |
1359 | ||
1360 | uart_set_options(port, co, baud, parity, bits, flow); | |
d948a29e | 1361 | cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); |
1da177e4 LT |
1362 | |
1363 | return 0; | |
1364 | } | |
1365 | ||
36d2f5a1 | 1366 | static struct uart_driver cpm_reg; |
1da177e4 | 1367 | static struct console cpm_scc_uart_console = { |
36d2f5a1 KG |
1368 | .name = "ttyCPM", |
1369 | .write = cpm_uart_console_write, | |
1370 | .device = uart_console_device, | |
1371 | .setup = cpm_uart_console_setup, | |
1372 | .flags = CON_PRINTBUFFER, | |
1373 | .index = -1, | |
1da177e4 LT |
1374 | .data = &cpm_reg, |
1375 | }; | |
1376 | ||
c1dcfd9d | 1377 | static int __init cpm_uart_console_init(void) |
1da177e4 | 1378 | { |
e27987cd VB |
1379 | register_console(&cpm_scc_uart_console); |
1380 | return 0; | |
1da177e4 LT |
1381 | } |
1382 | ||
1383 | console_initcall(cpm_uart_console_init); | |
1384 | ||
1385 | #define CPM_UART_CONSOLE &cpm_scc_uart_console | |
1386 | #else | |
1387 | #define CPM_UART_CONSOLE NULL | |
1388 | #endif | |
1389 | ||
1390 | static struct uart_driver cpm_reg = { | |
1391 | .owner = THIS_MODULE, | |
1392 | .driver_name = "ttyCPM", | |
1393 | .dev_name = "ttyCPM", | |
1394 | .major = SERIAL_CPM_MAJOR, | |
1395 | .minor = SERIAL_CPM_MINOR, | |
1396 | .cons = CPM_UART_CONSOLE, | |
7ae87036 SW |
1397 | .nr = UART_NR, |
1398 | }; | |
1399 | ||
7ae87036 SW |
1400 | static int probe_index; |
1401 | ||
9671f099 | 1402 | static int cpm_uart_probe(struct platform_device *ofdev) |
7ae87036 SW |
1403 | { |
1404 | int index = probe_index++; | |
1405 | struct uart_cpm_port *pinfo = &cpm_uart_ports[index]; | |
1406 | int ret; | |
1407 | ||
1408 | pinfo->port.line = index; | |
1409 | ||
1410 | if (index >= UART_NR) | |
1411 | return -ENODEV; | |
1412 | ||
696faedd | 1413 | platform_set_drvdata(ofdev, pinfo); |
7ae87036 | 1414 | |
bd86ef37 SW |
1415 | /* initialize the device pointer for the port */ |
1416 | pinfo->port.dev = &ofdev->dev; | |
1417 | ||
61c7a080 | 1418 | ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo); |
7ae87036 SW |
1419 | if (ret) |
1420 | return ret; | |
1421 | ||
1422 | return uart_add_one_port(&cpm_reg, &pinfo->port); | |
1423 | } | |
1424 | ||
ae8d8a14 | 1425 | static int cpm_uart_remove(struct platform_device *ofdev) |
7ae87036 | 1426 | { |
696faedd | 1427 | struct uart_cpm_port *pinfo = platform_get_drvdata(ofdev); |
7ae87036 SW |
1428 | return uart_remove_one_port(&cpm_reg, &pinfo->port); |
1429 | } | |
1430 | ||
1431 | static struct of_device_id cpm_uart_match[] = { | |
1432 | { | |
1433 | .compatible = "fsl,cpm1-smc-uart", | |
1434 | }, | |
1435 | { | |
1436 | .compatible = "fsl,cpm1-scc-uart", | |
1437 | }, | |
1438 | { | |
1439 | .compatible = "fsl,cpm2-smc-uart", | |
1440 | }, | |
1441 | { | |
1442 | .compatible = "fsl,cpm2-scc-uart", | |
1443 | }, | |
1444 | {} | |
1da177e4 | 1445 | }; |
7ae87036 | 1446 | |
793218df | 1447 | static struct platform_driver cpm_uart_driver = { |
4018294b GL |
1448 | .driver = { |
1449 | .name = "cpm_uart", | |
1450 | .owner = THIS_MODULE, | |
1451 | .of_match_table = cpm_uart_match, | |
1452 | }, | |
7ae87036 SW |
1453 | .probe = cpm_uart_probe, |
1454 | .remove = cpm_uart_remove, | |
1455 | }; | |
1456 | ||
1457 | static int __init cpm_uart_init(void) | |
1458 | { | |
1459 | int ret = uart_register_driver(&cpm_reg); | |
1460 | if (ret) | |
1461 | return ret; | |
1462 | ||
793218df | 1463 | ret = platform_driver_register(&cpm_uart_driver); |
7ae87036 SW |
1464 | if (ret) |
1465 | uart_unregister_driver(&cpm_reg); | |
1466 | ||
1467 | return ret; | |
1468 | } | |
1469 | ||
1470 | static void __exit cpm_uart_exit(void) | |
1471 | { | |
793218df | 1472 | platform_driver_unregister(&cpm_uart_driver); |
7ae87036 SW |
1473 | uart_unregister_driver(&cpm_reg); |
1474 | } | |
1da177e4 LT |
1475 | |
1476 | module_init(cpm_uart_init); | |
1477 | module_exit(cpm_uart_exit); | |
1478 | ||
1479 | MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis"); | |
1480 | MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $"); | |
1481 | MODULE_LICENSE("GPL"); | |
1482 | MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR); |