Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for CPM (SCC/SMC) serial ports; core driver |
3 | * | |
4 | * Based on arch/ppc/cpm2_io/uart.c by Dan Malek | |
5 | * Based on ppc8xx.c by Thomas Gleixner | |
6 | * Based on drivers/serial/amba.c by Russell King | |
7 | * | |
4c8d3d99 | 8 | * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2) |
1da177e4 | 9 | * Pantelis Antoniou (panto@intracom.gr) (CPM1) |
311c4627 | 10 | * |
7ae87036 | 11 | * Copyright (C) 2004, 2007 Freescale Semiconductor, Inc. |
1da177e4 | 12 | * (C) 2004 Intracom, S.A. |
6e197696 | 13 | * (C) 2005-2006 MontaVista Software, Inc. |
0d844065 | 14 | * Vitaly Bordug <vbordug@ru.mvista.com> |
1da177e4 LT |
15 | * |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation; either version 2 of the License, or | |
19 | * (at your option) any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program; if not, write to the Free Software | |
28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
29 | * | |
30 | */ | |
31 | ||
1da177e4 LT |
32 | #include <linux/module.h> |
33 | #include <linux/tty.h> | |
ee160a38 | 34 | #include <linux/tty_flip.h> |
1da177e4 LT |
35 | #include <linux/ioport.h> |
36 | #include <linux/init.h> | |
37 | #include <linux/serial.h> | |
38 | #include <linux/console.h> | |
39 | #include <linux/sysrq.h> | |
40 | #include <linux/device.h> | |
41 | #include <linux/bootmem.h> | |
42 | #include <linux/dma-mapping.h> | |
e27987cd | 43 | #include <linux/fs_uart_pd.h> |
0b2a2e5b | 44 | #include <linux/of_platform.h> |
7485d26b LP |
45 | #include <linux/gpio.h> |
46 | #include <linux/of_gpio.h> | |
80776554 | 47 | #include <linux/clk.h> |
1da177e4 LT |
48 | |
49 | #include <asm/io.h> | |
50 | #include <asm/irq.h> | |
51 | #include <asm/delay.h> | |
3dd0dcbe | 52 | #include <asm/fs_pd.h> |
7ae87036 SW |
53 | #include <asm/udbg.h> |
54 | ||
1da177e4 LT |
55 | #if defined(CONFIG_SERIAL_CPM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
56 | #define SUPPORT_SYSRQ | |
57 | #endif | |
58 | ||
59 | #include <linux/serial_core.h> | |
60 | #include <linux/kernel.h> | |
61 | ||
62 | #include "cpm_uart.h" | |
63 | ||
1da177e4 LT |
64 | |
65 | /**************************************************************/ | |
66 | ||
67 | static int cpm_uart_tx_pump(struct uart_port *port); | |
68 | static void cpm_uart_init_smc(struct uart_cpm_port *pinfo); | |
69 | static void cpm_uart_init_scc(struct uart_cpm_port *pinfo); | |
70 | static void cpm_uart_initbd(struct uart_cpm_port *pinfo); | |
71 | ||
72 | /**************************************************************/ | |
73 | ||
59733ef7 | 74 | #define HW_BUF_SPD_THRESHOLD 2400 |
5b04ec4a | 75 | |
1da177e4 | 76 | /* |
311c4627 | 77 | * Check, if transmit buffers are processed |
1da177e4 LT |
78 | */ |
79 | static unsigned int cpm_uart_tx_empty(struct uart_port *port) | |
80 | { | |
81 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d | 82 | cbd_t __iomem *bdp = pinfo->tx_bd_base; |
1da177e4 LT |
83 | int ret = 0; |
84 | ||
85 | while (1) { | |
c1dcfd9d | 86 | if (in_be16(&bdp->cbd_sc) & BD_SC_READY) |
1da177e4 LT |
87 | break; |
88 | ||
c1dcfd9d | 89 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) { |
1da177e4 LT |
90 | ret = TIOCSER_TEMT; |
91 | break; | |
92 | } | |
93 | bdp++; | |
94 | } | |
95 | ||
96 | pr_debug("CPM uart[%d]:tx_empty: %d\n", port->line, ret); | |
97 | ||
98 | return ret; | |
99 | } | |
100 | ||
101 | static void cpm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
102 | { | |
7485d26b LP |
103 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; |
104 | ||
105 | if (pinfo->gpios[GPIO_RTS] >= 0) | |
106 | gpio_set_value(pinfo->gpios[GPIO_RTS], !(mctrl & TIOCM_RTS)); | |
107 | ||
108 | if (pinfo->gpios[GPIO_DTR] >= 0) | |
109 | gpio_set_value(pinfo->gpios[GPIO_DTR], !(mctrl & TIOCM_DTR)); | |
1da177e4 LT |
110 | } |
111 | ||
112 | static unsigned int cpm_uart_get_mctrl(struct uart_port *port) | |
113 | { | |
7485d26b LP |
114 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; |
115 | unsigned int mctrl = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
116 | ||
117 | if (pinfo->gpios[GPIO_CTS] >= 0) { | |
118 | if (gpio_get_value(pinfo->gpios[GPIO_CTS])) | |
119 | mctrl &= ~TIOCM_CTS; | |
120 | } | |
121 | ||
122 | if (pinfo->gpios[GPIO_DSR] >= 0) { | |
123 | if (gpio_get_value(pinfo->gpios[GPIO_DSR])) | |
124 | mctrl &= ~TIOCM_DSR; | |
125 | } | |
126 | ||
127 | if (pinfo->gpios[GPIO_DCD] >= 0) { | |
128 | if (gpio_get_value(pinfo->gpios[GPIO_DCD])) | |
129 | mctrl &= ~TIOCM_CAR; | |
130 | } | |
131 | ||
132 | if (pinfo->gpios[GPIO_RI] >= 0) { | |
133 | if (!gpio_get_value(pinfo->gpios[GPIO_RI])) | |
134 | mctrl |= TIOCM_RNG; | |
135 | } | |
136 | ||
137 | return mctrl; | |
1da177e4 LT |
138 | } |
139 | ||
140 | /* | |
141 | * Stop transmitter | |
142 | */ | |
b129a8cc | 143 | static void cpm_uart_stop_tx(struct uart_port *port) |
1da177e4 LT |
144 | { |
145 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d SW |
146 | smc_t __iomem *smcp = pinfo->smcp; |
147 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
148 | |
149 | pr_debug("CPM uart[%d]:stop tx\n", port->line); | |
150 | ||
151 | if (IS_SMC(pinfo)) | |
c1dcfd9d | 152 | clrbits8(&smcp->smc_smcm, SMCM_TX); |
1da177e4 | 153 | else |
c1dcfd9d | 154 | clrbits16(&sccp->scc_sccm, UART_SCCM_TX); |
1da177e4 LT |
155 | } |
156 | ||
157 | /* | |
158 | * Start transmitter | |
159 | */ | |
b129a8cc | 160 | static void cpm_uart_start_tx(struct uart_port *port) |
1da177e4 LT |
161 | { |
162 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d SW |
163 | smc_t __iomem *smcp = pinfo->smcp; |
164 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
165 | |
166 | pr_debug("CPM uart[%d]:start tx\n", port->line); | |
167 | ||
168 | if (IS_SMC(pinfo)) { | |
c1dcfd9d | 169 | if (in_8(&smcp->smc_smcm) & SMCM_TX) |
1da177e4 LT |
170 | return; |
171 | } else { | |
c1dcfd9d | 172 | if (in_be16(&sccp->scc_sccm) & UART_SCCM_TX) |
1da177e4 LT |
173 | return; |
174 | } | |
175 | ||
176 | if (cpm_uart_tx_pump(port) != 0) { | |
311c4627 | 177 | if (IS_SMC(pinfo)) { |
c1dcfd9d | 178 | setbits8(&smcp->smc_smcm, SMCM_TX); |
311c4627 | 179 | } else { |
c1dcfd9d | 180 | setbits16(&sccp->scc_sccm, UART_SCCM_TX); |
311c4627 | 181 | } |
1da177e4 LT |
182 | } |
183 | } | |
184 | ||
185 | /* | |
311c4627 | 186 | * Stop receiver |
1da177e4 LT |
187 | */ |
188 | static void cpm_uart_stop_rx(struct uart_port *port) | |
189 | { | |
190 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d SW |
191 | smc_t __iomem *smcp = pinfo->smcp; |
192 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
193 | |
194 | pr_debug("CPM uart[%d]:stop rx\n", port->line); | |
195 | ||
196 | if (IS_SMC(pinfo)) | |
c1dcfd9d | 197 | clrbits8(&smcp->smc_smcm, SMCM_RX); |
1da177e4 | 198 | else |
c1dcfd9d | 199 | clrbits16(&sccp->scc_sccm, UART_SCCM_RX); |
1da177e4 LT |
200 | } |
201 | ||
202 | /* | |
203 | * Enable Modem status interrupts | |
204 | */ | |
205 | static void cpm_uart_enable_ms(struct uart_port *port) | |
206 | { | |
207 | pr_debug("CPM uart[%d]:enable ms\n", port->line); | |
208 | } | |
209 | ||
210 | /* | |
311c4627 | 211 | * Generate a break. |
1da177e4 LT |
212 | */ |
213 | static void cpm_uart_break_ctl(struct uart_port *port, int break_state) | |
214 | { | |
215 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
1da177e4 LT |
216 | |
217 | pr_debug("CPM uart[%d]:break ctrl, break_state: %d\n", port->line, | |
218 | break_state); | |
219 | ||
220 | if (break_state) | |
7ae87036 | 221 | cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); |
1da177e4 | 222 | else |
7ae87036 | 223 | cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); |
1da177e4 LT |
224 | } |
225 | ||
226 | /* | |
227 | * Transmit characters, refill buffer descriptor, if possible | |
228 | */ | |
7d12e780 | 229 | static void cpm_uart_int_tx(struct uart_port *port) |
1da177e4 LT |
230 | { |
231 | pr_debug("CPM uart[%d]:TX INT\n", port->line); | |
232 | ||
233 | cpm_uart_tx_pump(port); | |
234 | } | |
235 | ||
8e21d04c JW |
236 | #ifdef CONFIG_CONSOLE_POLL |
237 | static int serial_polled; | |
238 | #endif | |
239 | ||
1da177e4 LT |
240 | /* |
241 | * Receive characters | |
242 | */ | |
7d12e780 | 243 | static void cpm_uart_int_rx(struct uart_port *port) |
1da177e4 LT |
244 | { |
245 | int i; | |
c1dcfd9d SW |
246 | unsigned char ch; |
247 | u8 *cp; | |
227434f8 | 248 | struct tty_port *tport = &port->state->port; |
1da177e4 | 249 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; |
c1dcfd9d | 250 | cbd_t __iomem *bdp; |
1da177e4 LT |
251 | u16 status; |
252 | unsigned int flg; | |
253 | ||
254 | pr_debug("CPM uart[%d]:RX INT\n", port->line); | |
255 | ||
256 | /* Just loop through the closed BDs and copy the characters into | |
257 | * the buffer. | |
258 | */ | |
259 | bdp = pinfo->rx_cur; | |
260 | for (;;) { | |
8e21d04c JW |
261 | #ifdef CONFIG_CONSOLE_POLL |
262 | if (unlikely(serial_polled)) { | |
263 | serial_polled = 0; | |
264 | return; | |
265 | } | |
266 | #endif | |
1da177e4 | 267 | /* get status */ |
c1dcfd9d | 268 | status = in_be16(&bdp->cbd_sc); |
1da177e4 LT |
269 | /* If this one is empty, return happy */ |
270 | if (status & BD_SC_EMPTY) | |
271 | break; | |
272 | ||
273 | /* get number of characters, and check spce in flip-buffer */ | |
c1dcfd9d | 274 | i = in_be16(&bdp->cbd_datlen); |
1da177e4 | 275 | |
311c4627 | 276 | /* If we have not enough room in tty flip buffer, then we try |
1da177e4 LT |
277 | * later, which will be the next rx-interrupt or a timeout |
278 | */ | |
227434f8 | 279 | if (tty_buffer_request_room(tport, i) < i) { |
76a55431 VB |
280 | printk(KERN_WARNING "No room in flip buffer\n"); |
281 | return; | |
1da177e4 LT |
282 | } |
283 | ||
284 | /* get pointer */ | |
c1dcfd9d | 285 | cp = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
1da177e4 LT |
286 | |
287 | /* loop through the buffer */ | |
288 | while (i-- > 0) { | |
289 | ch = *cp++; | |
290 | port->icount.rx++; | |
291 | flg = TTY_NORMAL; | |
292 | ||
293 | if (status & | |
294 | (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) | |
295 | goto handle_error; | |
7d12e780 | 296 | if (uart_handle_sysrq_char(port, ch)) |
1da177e4 | 297 | continue; |
8e21d04c JW |
298 | #ifdef CONFIG_CONSOLE_POLL |
299 | if (unlikely(serial_polled)) { | |
300 | serial_polled = 0; | |
301 | return; | |
302 | } | |
303 | #endif | |
1da177e4 | 304 | error_return: |
92a19f9c | 305 | tty_insert_flip_char(tport, ch, flg); |
1da177e4 LT |
306 | |
307 | } /* End while (i--) */ | |
308 | ||
309 | /* This BD is ready to be used again. Clear status. get next */ | |
c1dcfd9d SW |
310 | clrbits16(&bdp->cbd_sc, BD_SC_BR | BD_SC_FR | BD_SC_PR | |
311 | BD_SC_OV | BD_SC_ID); | |
312 | setbits16(&bdp->cbd_sc, BD_SC_EMPTY); | |
1da177e4 | 313 | |
c1dcfd9d | 314 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) |
1da177e4 LT |
315 | bdp = pinfo->rx_bd_base; |
316 | else | |
317 | bdp++; | |
311c4627 | 318 | |
1da177e4 LT |
319 | } /* End for (;;) */ |
320 | ||
321 | /* Write back buffer pointer */ | |
c1dcfd9d | 322 | pinfo->rx_cur = bdp; |
1da177e4 LT |
323 | |
324 | /* activate BH processing */ | |
2e124b4a | 325 | tty_flip_buffer_push(tport); |
1da177e4 LT |
326 | |
327 | return; | |
328 | ||
329 | /* Error processing */ | |
330 | ||
331 | handle_error: | |
332 | /* Statistics */ | |
333 | if (status & BD_SC_BR) | |
334 | port->icount.brk++; | |
335 | if (status & BD_SC_PR) | |
336 | port->icount.parity++; | |
337 | if (status & BD_SC_FR) | |
338 | port->icount.frame++; | |
339 | if (status & BD_SC_OV) | |
340 | port->icount.overrun++; | |
341 | ||
342 | /* Mask out ignored conditions */ | |
343 | status &= port->read_status_mask; | |
344 | ||
345 | /* Handle the remaining ones */ | |
346 | if (status & BD_SC_BR) | |
347 | flg = TTY_BREAK; | |
348 | else if (status & BD_SC_PR) | |
349 | flg = TTY_PARITY; | |
350 | else if (status & BD_SC_FR) | |
351 | flg = TTY_FRAME; | |
352 | ||
353 | /* overrun does not affect the current character ! */ | |
354 | if (status & BD_SC_OV) { | |
355 | ch = 0; | |
356 | flg = TTY_OVERRUN; | |
357 | /* We skip this buffer */ | |
358 | /* CHECK: Is really nothing senseful there */ | |
359 | /* ASSUMPTION: it contains nothing valid */ | |
360 | i = 0; | |
361 | } | |
362 | #ifdef SUPPORT_SYSRQ | |
363 | port->sysrq = 0; | |
364 | #endif | |
365 | goto error_return; | |
366 | } | |
367 | ||
368 | /* | |
369 | * Asynchron mode interrupt handler | |
370 | */ | |
7d12e780 | 371 | static irqreturn_t cpm_uart_int(int irq, void *data) |
1da177e4 LT |
372 | { |
373 | u8 events; | |
15aafa2f | 374 | struct uart_port *port = data; |
1da177e4 | 375 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; |
c1dcfd9d SW |
376 | smc_t __iomem *smcp = pinfo->smcp; |
377 | scc_t __iomem *sccp = pinfo->sccp; | |
1da177e4 LT |
378 | |
379 | pr_debug("CPM uart[%d]:IRQ\n", port->line); | |
380 | ||
381 | if (IS_SMC(pinfo)) { | |
c1dcfd9d SW |
382 | events = in_8(&smcp->smc_smce); |
383 | out_8(&smcp->smc_smce, events); | |
1da177e4 LT |
384 | if (events & SMCM_BRKE) |
385 | uart_handle_break(port); | |
386 | if (events & SMCM_RX) | |
7d12e780 | 387 | cpm_uart_int_rx(port); |
1da177e4 | 388 | if (events & SMCM_TX) |
7d12e780 | 389 | cpm_uart_int_tx(port); |
1da177e4 | 390 | } else { |
c1dcfd9d SW |
391 | events = in_be16(&sccp->scc_scce); |
392 | out_be16(&sccp->scc_scce, events); | |
1da177e4 LT |
393 | if (events & UART_SCCM_BRKE) |
394 | uart_handle_break(port); | |
395 | if (events & UART_SCCM_RX) | |
7d12e780 | 396 | cpm_uart_int_rx(port); |
1da177e4 | 397 | if (events & UART_SCCM_TX) |
7d12e780 | 398 | cpm_uart_int_tx(port); |
1da177e4 LT |
399 | } |
400 | return (events) ? IRQ_HANDLED : IRQ_NONE; | |
401 | } | |
402 | ||
403 | static int cpm_uart_startup(struct uart_port *port) | |
404 | { | |
405 | int retval; | |
406 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
407 | ||
408 | pr_debug("CPM uart[%d]:startup\n", port->line); | |
409 | ||
9ab92120 XF |
410 | /* If the port is not the console, make sure rx is disabled. */ |
411 | if (!(pinfo->flags & FLAG_CONSOLE)) { | |
412 | /* Disable UART rx */ | |
413 | if (IS_SMC(pinfo)) { | |
414 | clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN); | |
415 | clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX); | |
416 | } else { | |
417 | clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR); | |
418 | clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); | |
419 | } | |
725ef4a3 | 420 | cpm_uart_initbd(pinfo); |
9ab92120 XF |
421 | cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); |
422 | } | |
1da177e4 LT |
423 | /* Install interrupt handler. */ |
424 | retval = request_irq(port->irq, cpm_uart_int, 0, "cpm_uart", port); | |
425 | if (retval) | |
426 | return retval; | |
427 | ||
428 | /* Startup rx-int */ | |
429 | if (IS_SMC(pinfo)) { | |
c1dcfd9d SW |
430 | setbits8(&pinfo->smcp->smc_smcm, SMCM_RX); |
431 | setbits16(&pinfo->smcp->smc_smcmr, (SMCMR_REN | SMCMR_TEN)); | |
1da177e4 | 432 | } else { |
c1dcfd9d SW |
433 | setbits16(&pinfo->sccp->scc_sccm, UART_SCCM_RX); |
434 | setbits32(&pinfo->sccp->scc_gsmrl, (SCC_GSMRL_ENR | SCC_GSMRL_ENT)); | |
1da177e4 LT |
435 | } |
436 | ||
437 | return 0; | |
438 | } | |
439 | ||
311c4627 KG |
440 | inline void cpm_uart_wait_until_send(struct uart_cpm_port *pinfo) |
441 | { | |
638861d5 KG |
442 | set_current_state(TASK_UNINTERRUPTIBLE); |
443 | schedule_timeout(pinfo->wait_closing); | |
311c4627 KG |
444 | } |
445 | ||
1da177e4 LT |
446 | /* |
447 | * Shutdown the uart | |
448 | */ | |
449 | static void cpm_uart_shutdown(struct uart_port *port) | |
450 | { | |
451 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
1da177e4 LT |
452 | |
453 | pr_debug("CPM uart[%d]:shutdown\n", port->line); | |
454 | ||
455 | /* free interrupt handler */ | |
456 | free_irq(port->irq, port); | |
457 | ||
458 | /* If the port is not the console, disable Rx and Tx. */ | |
459 | if (!(pinfo->flags & FLAG_CONSOLE)) { | |
311c4627 | 460 | /* Wait for all the BDs marked sent */ |
638861d5 KG |
461 | while(!cpm_uart_tx_empty(port)) { |
462 | set_current_state(TASK_UNINTERRUPTIBLE); | |
311c4627 | 463 | schedule_timeout(2); |
638861d5 KG |
464 | } |
465 | ||
466 | if (pinfo->wait_closing) | |
311c4627 KG |
467 | cpm_uart_wait_until_send(pinfo); |
468 | ||
1da177e4 LT |
469 | /* Stop uarts */ |
470 | if (IS_SMC(pinfo)) { | |
c1dcfd9d SW |
471 | smc_t __iomem *smcp = pinfo->smcp; |
472 | clrbits16(&smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); | |
473 | clrbits8(&smcp->smc_smcm, SMCM_RX | SMCM_TX); | |
1da177e4 | 474 | } else { |
c1dcfd9d SW |
475 | scc_t __iomem *sccp = pinfo->sccp; |
476 | clrbits32(&sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
477 | clrbits16(&sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); | |
1da177e4 LT |
478 | } |
479 | ||
480 | /* Shut them really down and reinit buffer descriptors */ | |
ae2d4c39 NL |
481 | if (IS_SMC(pinfo)) { |
482 | out_be16(&pinfo->smcup->smc_brkcr, 0); | |
7ae87036 | 483 | cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); |
ae2d4c39 NL |
484 | } else { |
485 | out_be16(&pinfo->sccup->scc_brkcr, 0); | |
7ae87036 | 486 | cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); |
ae2d4c39 | 487 | } |
61f5657c | 488 | |
1da177e4 LT |
489 | cpm_uart_initbd(pinfo); |
490 | } | |
491 | } | |
492 | ||
493 | static void cpm_uart_set_termios(struct uart_port *port, | |
1bda8f30 SW |
494 | struct ktermios *termios, |
495 | struct ktermios *old) | |
1da177e4 LT |
496 | { |
497 | int baud; | |
498 | unsigned long flags; | |
499 | u16 cval, scval, prev_mode; | |
500 | int bits, sbits; | |
501 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
c1dcfd9d SW |
502 | smc_t __iomem *smcp = pinfo->smcp; |
503 | scc_t __iomem *sccp = pinfo->sccp; | |
6e62bdc0 | 504 | int maxidl; |
1da177e4 LT |
505 | |
506 | pr_debug("CPM uart[%d]:set_termios\n", port->line); | |
507 | ||
508 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); | |
59733ef7 | 509 | if (baud < HW_BUF_SPD_THRESHOLD || |
d6c53c0e | 510 | (pinfo->port.state && pinfo->port.state->port.low_latency)) |
5b04ec4a BI |
511 | pinfo->rx_fifosize = 1; |
512 | else | |
513 | pinfo->rx_fifosize = RX_BUF_SIZE; | |
1da177e4 | 514 | |
6e62bdc0 CL |
515 | /* MAXIDL is the timeout after which a receive buffer is closed |
516 | * when not full if no more characters are received. | |
517 | * We calculate it from the baudrate so that the duration is | |
518 | * always the same at standard rates: about 4ms. | |
519 | */ | |
520 | maxidl = baud / 2400; | |
521 | if (maxidl < 1) | |
522 | maxidl = 1; | |
523 | if (maxidl > 0x10) | |
524 | maxidl = 0x10; | |
525 | ||
1da177e4 LT |
526 | /* Character length programmed into the mode register is the |
527 | * sum of: 1 start bit, number of data bits, 0 or 1 parity bit, | |
528 | * 1 or 2 stop bits, minus 1. | |
529 | * The value 'bits' counts this for us. | |
530 | */ | |
531 | cval = 0; | |
532 | scval = 0; | |
533 | ||
534 | /* byte size */ | |
535 | switch (termios->c_cflag & CSIZE) { | |
536 | case CS5: | |
537 | bits = 5; | |
538 | break; | |
539 | case CS6: | |
540 | bits = 6; | |
541 | break; | |
542 | case CS7: | |
543 | bits = 7; | |
544 | break; | |
545 | case CS8: | |
546 | bits = 8; | |
547 | break; | |
548 | /* Never happens, but GCC is too dumb to figure it out */ | |
549 | default: | |
550 | bits = 8; | |
551 | break; | |
552 | } | |
553 | sbits = bits - 5; | |
554 | ||
555 | if (termios->c_cflag & CSTOPB) { | |
556 | cval |= SMCMR_SL; /* Two stops */ | |
557 | scval |= SCU_PSMR_SL; | |
558 | bits++; | |
559 | } | |
560 | ||
561 | if (termios->c_cflag & PARENB) { | |
562 | cval |= SMCMR_PEN; | |
563 | scval |= SCU_PSMR_PEN; | |
564 | bits++; | |
565 | if (!(termios->c_cflag & PARODD)) { | |
566 | cval |= SMCMR_PM_EVEN; | |
567 | scval |= (SCU_PSMR_REVP | SCU_PSMR_TEVP); | |
568 | } | |
569 | } | |
570 | ||
dc320815 LP |
571 | /* |
572 | * Update the timeout | |
573 | */ | |
574 | uart_update_timeout(port, termios->c_cflag, baud); | |
575 | ||
1da177e4 LT |
576 | /* |
577 | * Set up parity check flag | |
578 | */ | |
579 | #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK)) | |
580 | ||
581 | port->read_status_mask = (BD_SC_EMPTY | BD_SC_OV); | |
582 | if (termios->c_iflag & INPCK) | |
583 | port->read_status_mask |= BD_SC_FR | BD_SC_PR; | |
584 | if ((termios->c_iflag & BRKINT) || (termios->c_iflag & PARMRK)) | |
585 | port->read_status_mask |= BD_SC_BR; | |
586 | ||
587 | /* | |
588 | * Characters to ignore | |
589 | */ | |
590 | port->ignore_status_mask = 0; | |
591 | if (termios->c_iflag & IGNPAR) | |
592 | port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; | |
593 | if (termios->c_iflag & IGNBRK) { | |
594 | port->ignore_status_mask |= BD_SC_BR; | |
595 | /* | |
596 | * If we're ignore parity and break indicators, ignore | |
597 | * overruns too. (For real raw support). | |
598 | */ | |
599 | if (termios->c_iflag & IGNPAR) | |
600 | port->ignore_status_mask |= BD_SC_OV; | |
601 | } | |
602 | /* | |
603 | * !!! ignore all characters if CREAD is not set | |
604 | */ | |
605 | if ((termios->c_cflag & CREAD) == 0) | |
606 | port->read_status_mask &= ~BD_SC_EMPTY; | |
311c4627 | 607 | |
1da177e4 LT |
608 | spin_lock_irqsave(&port->lock, flags); |
609 | ||
610 | /* Start bit has not been added (so don't, because we would just | |
611 | * subtract it later), and we need to add one for the number of | |
612 | * stops bits (there is always at least one). | |
613 | */ | |
614 | bits++; | |
615 | if (IS_SMC(pinfo)) { | |
5b04ec4a BI |
616 | /* |
617 | * MRBLR can be changed while an SMC/SCC is operating only | |
618 | * if it is done in a single bus cycle with one 16-bit move | |
619 | * (not two 8-bit bus cycles back-to-back). This occurs when | |
620 | * the cp shifts control to the next RxBD, so the change does | |
621 | * not take effect immediately. To guarantee the exact RxBD | |
622 | * on which the change occurs, change MRBLR only while the | |
623 | * SMC/SCC receiver is disabled. | |
624 | */ | |
625 | out_be16(&pinfo->smcup->smc_mrblr, pinfo->rx_fifosize); | |
6e62bdc0 | 626 | out_be16(&pinfo->smcup->smc_maxidl, maxidl); |
5b04ec4a | 627 | |
1da177e4 LT |
628 | /* Set the mode register. We want to keep a copy of the |
629 | * enables, because we want to put them back if they were | |
630 | * present. | |
631 | */ | |
ae2d4c39 NL |
632 | prev_mode = in_be16(&smcp->smc_smcmr) & (SMCMR_REN | SMCMR_TEN); |
633 | /* Output in *one* operation, so we don't interrupt RX/TX if they | |
634 | * were already enabled. */ | |
635 | out_be16(&smcp->smc_smcmr, smcr_mk_clen(bits) | cval | | |
636 | SMCMR_SM_UART | prev_mode); | |
1da177e4 | 637 | } else { |
5b04ec4a | 638 | out_be16(&pinfo->sccup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); |
6e62bdc0 | 639 | out_be16(&pinfo->sccup->scc_maxidl, maxidl); |
c1dcfd9d | 640 | out_be16(&sccp->scc_psmr, (sbits << 12) | scval); |
1da177e4 LT |
641 | } |
642 | ||
80776554 LP |
643 | if (pinfo->clk) |
644 | clk_set_rate(pinfo->clk, baud); | |
645 | else | |
646 | cpm_set_brg(pinfo->brg - 1, baud); | |
1da177e4 | 647 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
648 | } |
649 | ||
650 | static const char *cpm_uart_type(struct uart_port *port) | |
651 | { | |
652 | pr_debug("CPM uart[%d]:uart_type\n", port->line); | |
653 | ||
654 | return port->type == PORT_CPM ? "CPM UART" : NULL; | |
655 | } | |
656 | ||
657 | /* | |
658 | * verify the new serial_struct (for TIOCSSERIAL). | |
659 | */ | |
660 | static int cpm_uart_verify_port(struct uart_port *port, | |
661 | struct serial_struct *ser) | |
662 | { | |
663 | int ret = 0; | |
664 | ||
665 | pr_debug("CPM uart[%d]:verify_port\n", port->line); | |
666 | ||
667 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) | |
668 | ret = -EINVAL; | |
a62c4133 | 669 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
1da177e4 LT |
670 | ret = -EINVAL; |
671 | if (ser->baud_base < 9600) | |
672 | ret = -EINVAL; | |
673 | return ret; | |
674 | } | |
675 | ||
676 | /* | |
677 | * Transmit characters, refill buffer descriptor, if possible | |
678 | */ | |
679 | static int cpm_uart_tx_pump(struct uart_port *port) | |
680 | { | |
c1dcfd9d SW |
681 | cbd_t __iomem *bdp; |
682 | u8 *p; | |
1da177e4 LT |
683 | int count; |
684 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
09dd3fc1 | 685 | struct circ_buf *xmit = &port->state->xmit; |
1da177e4 LT |
686 | |
687 | /* Handle xon/xoff */ | |
688 | if (port->x_char) { | |
689 | /* Pick next descriptor and fill from buffer */ | |
690 | bdp = pinfo->tx_cur; | |
691 | ||
c1dcfd9d | 692 | p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
311c4627 | 693 | |
03929c76 | 694 | *p++ = port->x_char; |
c1dcfd9d SW |
695 | |
696 | out_be16(&bdp->cbd_datlen, 1); | |
697 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1da177e4 | 698 | /* Get next BD. */ |
c1dcfd9d | 699 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) |
1da177e4 LT |
700 | bdp = pinfo->tx_bd_base; |
701 | else | |
702 | bdp++; | |
703 | pinfo->tx_cur = bdp; | |
704 | ||
705 | port->icount.tx++; | |
706 | port->x_char = 0; | |
707 | return 1; | |
708 | } | |
709 | ||
710 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
b129a8cc | 711 | cpm_uart_stop_tx(port); |
1da177e4 LT |
712 | return 0; |
713 | } | |
714 | ||
715 | /* Pick next descriptor and fill from buffer */ | |
716 | bdp = pinfo->tx_cur; | |
717 | ||
c1dcfd9d SW |
718 | while (!(in_be16(&bdp->cbd_sc) & BD_SC_READY) && |
719 | xmit->tail != xmit->head) { | |
1da177e4 | 720 | count = 0; |
c1dcfd9d | 721 | p = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), pinfo); |
1da177e4 LT |
722 | while (count < pinfo->tx_fifosize) { |
723 | *p++ = xmit->buf[xmit->tail]; | |
724 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
725 | port->icount.tx++; | |
726 | count++; | |
727 | if (xmit->head == xmit->tail) | |
728 | break; | |
729 | } | |
c1dcfd9d SW |
730 | out_be16(&bdp->cbd_datlen, count); |
731 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1da177e4 | 732 | /* Get next BD. */ |
c1dcfd9d | 733 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) |
1da177e4 LT |
734 | bdp = pinfo->tx_bd_base; |
735 | else | |
736 | bdp++; | |
737 | } | |
738 | pinfo->tx_cur = bdp; | |
739 | ||
740 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
741 | uart_write_wakeup(port); | |
742 | ||
743 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 744 | cpm_uart_stop_tx(port); |
1da177e4 LT |
745 | return 0; |
746 | } | |
747 | ||
748 | return 1; | |
749 | } | |
750 | ||
751 | /* | |
752 | * init buffer descriptors | |
753 | */ | |
754 | static void cpm_uart_initbd(struct uart_cpm_port *pinfo) | |
755 | { | |
756 | int i; | |
757 | u8 *mem_addr; | |
c1dcfd9d | 758 | cbd_t __iomem *bdp; |
1da177e4 LT |
759 | |
760 | pr_debug("CPM uart[%d]:initbd\n", pinfo->port.line); | |
761 | ||
762 | /* Set the physical address of the host memory | |
763 | * buffers in the buffer descriptors, and the | |
764 | * virtual address for us to work with. | |
765 | */ | |
766 | mem_addr = pinfo->mem_addr; | |
767 | bdp = pinfo->rx_cur = pinfo->rx_bd_base; | |
768 | for (i = 0; i < (pinfo->rx_nrfifos - 1); i++, bdp++) { | |
c1dcfd9d SW |
769 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
770 | out_be16(&bdp->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT); | |
1da177e4 LT |
771 | mem_addr += pinfo->rx_fifosize; |
772 | } | |
311c4627 | 773 | |
c1dcfd9d SW |
774 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
775 | out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT); | |
1da177e4 LT |
776 | |
777 | /* Set the physical address of the host memory | |
778 | * buffers in the buffer descriptors, and the | |
779 | * virtual address for us to work with. | |
780 | */ | |
781 | mem_addr = pinfo->mem_addr + L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize); | |
782 | bdp = pinfo->tx_cur = pinfo->tx_bd_base; | |
783 | for (i = 0; i < (pinfo->tx_nrfifos - 1); i++, bdp++) { | |
c1dcfd9d SW |
784 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
785 | out_be16(&bdp->cbd_sc, BD_SC_INTRPT); | |
1da177e4 LT |
786 | mem_addr += pinfo->tx_fifosize; |
787 | } | |
311c4627 | 788 | |
c1dcfd9d SW |
789 | out_be32(&bdp->cbd_bufaddr, cpu2cpm_addr(mem_addr, pinfo)); |
790 | out_be16(&bdp->cbd_sc, BD_SC_WRAP | BD_SC_INTRPT); | |
1da177e4 LT |
791 | } |
792 | ||
793 | static void cpm_uart_init_scc(struct uart_cpm_port *pinfo) | |
794 | { | |
c1dcfd9d SW |
795 | scc_t __iomem *scp; |
796 | scc_uart_t __iomem *sup; | |
1da177e4 LT |
797 | |
798 | pr_debug("CPM uart[%d]:init_scc\n", pinfo->port.line); | |
799 | ||
800 | scp = pinfo->sccp; | |
801 | sup = pinfo->sccup; | |
802 | ||
803 | /* Store address */ | |
c1dcfd9d SW |
804 | out_be16(&pinfo->sccup->scc_genscc.scc_rbase, |
805 | (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); | |
806 | out_be16(&pinfo->sccup->scc_genscc.scc_tbase, | |
807 | (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); | |
1da177e4 LT |
808 | |
809 | /* Set up the uart parameters in the | |
810 | * parameter ram. | |
811 | */ | |
812 | ||
813 | cpm_set_scc_fcr(sup); | |
814 | ||
c1dcfd9d | 815 | out_be16(&sup->scc_genscc.scc_mrblr, pinfo->rx_fifosize); |
fbbb9d96 | 816 | out_be16(&sup->scc_maxidl, 0x10); |
c1dcfd9d SW |
817 | out_be16(&sup->scc_brkcr, 1); |
818 | out_be16(&sup->scc_parec, 0); | |
819 | out_be16(&sup->scc_frmec, 0); | |
820 | out_be16(&sup->scc_nosec, 0); | |
821 | out_be16(&sup->scc_brkec, 0); | |
822 | out_be16(&sup->scc_uaddr1, 0); | |
823 | out_be16(&sup->scc_uaddr2, 0); | |
824 | out_be16(&sup->scc_toseq, 0); | |
825 | out_be16(&sup->scc_char1, 0x8000); | |
826 | out_be16(&sup->scc_char2, 0x8000); | |
827 | out_be16(&sup->scc_char3, 0x8000); | |
828 | out_be16(&sup->scc_char4, 0x8000); | |
829 | out_be16(&sup->scc_char5, 0x8000); | |
830 | out_be16(&sup->scc_char6, 0x8000); | |
831 | out_be16(&sup->scc_char7, 0x8000); | |
832 | out_be16(&sup->scc_char8, 0x8000); | |
833 | out_be16(&sup->scc_rccm, 0xc0ff); | |
1da177e4 LT |
834 | |
835 | /* Send the CPM an initialize command. | |
836 | */ | |
7ae87036 | 837 | cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); |
1da177e4 LT |
838 | |
839 | /* Set UART mode, 8 bit, no parity, one stop. | |
840 | * Enable receive and transmit. | |
841 | */ | |
c1dcfd9d SW |
842 | out_be32(&scp->scc_gsmrh, 0); |
843 | out_be32(&scp->scc_gsmrl, | |
844 | SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); | |
1da177e4 LT |
845 | |
846 | /* Enable rx interrupts and clear all pending events. */ | |
c1dcfd9d SW |
847 | out_be16(&scp->scc_sccm, 0); |
848 | out_be16(&scp->scc_scce, 0xffff); | |
849 | out_be16(&scp->scc_dsr, 0x7e7e); | |
850 | out_be16(&scp->scc_psmr, 0x3000); | |
1da177e4 | 851 | |
c1dcfd9d | 852 | setbits32(&scp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); |
1da177e4 LT |
853 | } |
854 | ||
855 | static void cpm_uart_init_smc(struct uart_cpm_port *pinfo) | |
856 | { | |
c1dcfd9d SW |
857 | smc_t __iomem *sp; |
858 | smc_uart_t __iomem *up; | |
1da177e4 LT |
859 | |
860 | pr_debug("CPM uart[%d]:init_smc\n", pinfo->port.line); | |
861 | ||
862 | sp = pinfo->smcp; | |
863 | up = pinfo->smcup; | |
864 | ||
865 | /* Store address */ | |
c1dcfd9d SW |
866 | out_be16(&pinfo->smcup->smc_rbase, |
867 | (u8 __iomem *)pinfo->rx_bd_base - DPRAM_BASE); | |
868 | out_be16(&pinfo->smcup->smc_tbase, | |
869 | (u8 __iomem *)pinfo->tx_bd_base - DPRAM_BASE); | |
1da177e4 LT |
870 | |
871 | /* | |
872 | * In case SMC1 is being relocated... | |
873 | */ | |
874 | #if defined (CONFIG_I2C_SPI_SMC1_UCODE_PATCH) | |
c1dcfd9d SW |
875 | out_be16(&up->smc_rbptr, in_be16(&pinfo->smcup->smc_rbase)); |
876 | out_be16(&up->smc_tbptr, in_be16(&pinfo->smcup->smc_tbase)); | |
877 | out_be32(&up->smc_rstate, 0); | |
878 | out_be32(&up->smc_tstate, 0); | |
879 | out_be16(&up->smc_brkcr, 1); /* number of break chars */ | |
880 | out_be16(&up->smc_brkec, 0); | |
1da177e4 LT |
881 | #endif |
882 | ||
883 | /* Set up the uart parameters in the | |
884 | * parameter ram. | |
885 | */ | |
886 | cpm_set_smc_fcr(up); | |
887 | ||
b770ffd4 | 888 | /* Using idle character time requires some additional tuning. */ |
c1dcfd9d | 889 | out_be16(&up->smc_mrblr, pinfo->rx_fifosize); |
fbbb9d96 | 890 | out_be16(&up->smc_maxidl, 0x10); |
c1dcfd9d SW |
891 | out_be16(&up->smc_brklen, 0); |
892 | out_be16(&up->smc_brkec, 0); | |
893 | out_be16(&up->smc_brkcr, 1); | |
1da177e4 | 894 | |
7ae87036 | 895 | cpm_line_cr_cmd(pinfo, CPM_CR_INIT_TRX); |
1da177e4 LT |
896 | |
897 | /* Set UART mode, 8 bit, no parity, one stop. | |
898 | * Enable receive and transmit. | |
899 | */ | |
c1dcfd9d | 900 | out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART); |
1da177e4 LT |
901 | |
902 | /* Enable only rx interrupts clear all pending events. */ | |
c1dcfd9d SW |
903 | out_8(&sp->smc_smcm, 0); |
904 | out_8(&sp->smc_smce, 0xff); | |
1da177e4 | 905 | |
c1dcfd9d | 906 | setbits16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN); |
1da177e4 LT |
907 | } |
908 | ||
909 | /* | |
910 | * Initialize port. This is called from early_console stuff | |
911 | * so we have to be careful here ! | |
912 | */ | |
913 | static int cpm_uart_request_port(struct uart_port *port) | |
914 | { | |
915 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
916 | int ret; | |
917 | ||
918 | pr_debug("CPM uart[%d]:request port\n", port->line); | |
919 | ||
920 | if (pinfo->flags & FLAG_CONSOLE) | |
921 | return 0; | |
922 | ||
1da177e4 | 923 | if (IS_SMC(pinfo)) { |
c1dcfd9d SW |
924 | clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); |
925 | clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); | |
1da177e4 | 926 | } else { |
c1dcfd9d SW |
927 | clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); |
928 | clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
1da177e4 LT |
929 | } |
930 | ||
931 | ret = cpm_uart_allocbuf(pinfo, 0); | |
932 | ||
933 | if (ret) | |
934 | return ret; | |
935 | ||
936 | cpm_uart_initbd(pinfo); | |
311c4627 KG |
937 | if (IS_SMC(pinfo)) |
938 | cpm_uart_init_smc(pinfo); | |
939 | else | |
940 | cpm_uart_init_scc(pinfo); | |
1da177e4 LT |
941 | |
942 | return 0; | |
943 | } | |
944 | ||
945 | static void cpm_uart_release_port(struct uart_port *port) | |
946 | { | |
947 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
948 | ||
949 | if (!(pinfo->flags & FLAG_CONSOLE)) | |
950 | cpm_uart_freebuf(pinfo); | |
951 | } | |
952 | ||
953 | /* | |
954 | * Configure/autoconfigure the port. | |
955 | */ | |
956 | static void cpm_uart_config_port(struct uart_port *port, int flags) | |
957 | { | |
958 | pr_debug("CPM uart[%d]:config_port\n", port->line); | |
959 | ||
960 | if (flags & UART_CONFIG_TYPE) { | |
961 | port->type = PORT_CPM; | |
962 | cpm_uart_request_port(port); | |
963 | } | |
964 | } | |
8e21d04c | 965 | |
8cd774ad DD |
966 | #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_CPM_CONSOLE) |
967 | /* | |
968 | * Write a string to the serial port | |
969 | * Note that this is called with interrupts already disabled | |
970 | */ | |
971 | static void cpm_uart_early_write(struct uart_cpm_port *pinfo, | |
972 | const char *string, u_int count) | |
973 | { | |
974 | unsigned int i; | |
975 | cbd_t __iomem *bdp, *bdbase; | |
976 | unsigned char *cpm_outp_addr; | |
977 | ||
978 | /* Get the address of the host memory buffer. | |
979 | */ | |
980 | bdp = pinfo->tx_cur; | |
981 | bdbase = pinfo->tx_bd_base; | |
982 | ||
983 | /* | |
984 | * Now, do each character. This is not as bad as it looks | |
985 | * since this is a holding FIFO and not a transmitting FIFO. | |
986 | * We could add the complexity of filling the entire transmit | |
987 | * buffer, but we would just wait longer between accesses...... | |
988 | */ | |
989 | for (i = 0; i < count; i++, string++) { | |
990 | /* Wait for transmitter fifo to empty. | |
991 | * Ready indicates output is ready, and xmt is doing | |
992 | * that, not that it is ready for us to send. | |
993 | */ | |
994 | while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) | |
995 | ; | |
996 | ||
997 | /* Send the character out. | |
998 | * If the buffer address is in the CPM DPRAM, don't | |
999 | * convert it. | |
1000 | */ | |
1001 | cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), | |
1002 | pinfo); | |
1003 | *cpm_outp_addr = *string; | |
1004 | ||
1005 | out_be16(&bdp->cbd_datlen, 1); | |
1006 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1007 | ||
1008 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) | |
1009 | bdp = bdbase; | |
1010 | else | |
1011 | bdp++; | |
1012 | ||
1013 | /* if a LF, also do CR... */ | |
1014 | if (*string == 10) { | |
1015 | while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) | |
1016 | ; | |
1017 | ||
1018 | cpm_outp_addr = cpm2cpu_addr(in_be32(&bdp->cbd_bufaddr), | |
1019 | pinfo); | |
1020 | *cpm_outp_addr = 13; | |
1021 | ||
1022 | out_be16(&bdp->cbd_datlen, 1); | |
1023 | setbits16(&bdp->cbd_sc, BD_SC_READY); | |
1024 | ||
1025 | if (in_be16(&bdp->cbd_sc) & BD_SC_WRAP) | |
1026 | bdp = bdbase; | |
1027 | else | |
1028 | bdp++; | |
1029 | } | |
1030 | } | |
1031 | ||
1032 | /* | |
1033 | * Finally, Wait for transmitter & holding register to empty | |
1034 | * and restore the IER | |
1035 | */ | |
1036 | while ((in_be16(&bdp->cbd_sc) & BD_SC_READY) != 0) | |
1037 | ; | |
1038 | ||
1039 | pinfo->tx_cur = bdp; | |
1040 | } | |
1041 | #endif | |
1042 | ||
8e21d04c JW |
1043 | #ifdef CONFIG_CONSOLE_POLL |
1044 | /* Serial polling routines for writing and reading from the uart while | |
1045 | * in an interrupt or debug context. | |
1046 | */ | |
1047 | ||
1048 | #define GDB_BUF_SIZE 512 /* power of 2, please */ | |
1049 | ||
1050 | static char poll_buf[GDB_BUF_SIZE]; | |
1051 | static char *pollp; | |
1052 | static int poll_chars; | |
1053 | ||
1054 | static int poll_wait_key(char *obuf, struct uart_cpm_port *pinfo) | |
1055 | { | |
1056 | u_char c, *cp; | |
1057 | volatile cbd_t *bdp; | |
1058 | int i; | |
1059 | ||
1060 | /* Get the address of the host memory buffer. | |
1061 | */ | |
1062 | bdp = pinfo->rx_cur; | |
1063 | while (bdp->cbd_sc & BD_SC_EMPTY) | |
1064 | ; | |
1065 | ||
1066 | /* If the buffer address is in the CPM DPRAM, don't | |
1067 | * convert it. | |
1068 | */ | |
1069 | cp = cpm2cpu_addr(bdp->cbd_bufaddr, pinfo); | |
1070 | ||
1071 | if (obuf) { | |
1072 | i = c = bdp->cbd_datlen; | |
1073 | while (i-- > 0) | |
1074 | *obuf++ = *cp++; | |
1075 | } else | |
1076 | c = *cp; | |
1077 | bdp->cbd_sc &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID); | |
1078 | bdp->cbd_sc |= BD_SC_EMPTY; | |
1079 | ||
1080 | if (bdp->cbd_sc & BD_SC_WRAP) | |
1081 | bdp = pinfo->rx_bd_base; | |
1082 | else | |
1083 | bdp++; | |
1084 | pinfo->rx_cur = (cbd_t *)bdp; | |
1085 | ||
1086 | return (int)c; | |
1087 | } | |
1088 | ||
1089 | static int cpm_get_poll_char(struct uart_port *port) | |
1090 | { | |
1091 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
1092 | ||
1093 | if (!serial_polled) { | |
1094 | serial_polled = 1; | |
1095 | poll_chars = 0; | |
1096 | } | |
1097 | if (poll_chars <= 0) { | |
1098 | poll_chars = poll_wait_key(poll_buf, pinfo); | |
1099 | pollp = poll_buf; | |
1100 | } | |
1101 | poll_chars--; | |
1102 | return *pollp++; | |
1103 | } | |
1104 | ||
1105 | static void cpm_put_poll_char(struct uart_port *port, | |
1106 | unsigned char c) | |
1107 | { | |
1108 | struct uart_cpm_port *pinfo = (struct uart_cpm_port *)port; | |
1109 | static char ch[2]; | |
1110 | ||
1111 | ch[0] = (char)c; | |
8cd774ad | 1112 | cpm_uart_early_write(pinfo, ch, 1); |
8e21d04c JW |
1113 | } |
1114 | #endif /* CONFIG_CONSOLE_POLL */ | |
1115 | ||
1da177e4 LT |
1116 | static struct uart_ops cpm_uart_pops = { |
1117 | .tx_empty = cpm_uart_tx_empty, | |
1118 | .set_mctrl = cpm_uart_set_mctrl, | |
1119 | .get_mctrl = cpm_uart_get_mctrl, | |
1120 | .stop_tx = cpm_uart_stop_tx, | |
1121 | .start_tx = cpm_uart_start_tx, | |
1122 | .stop_rx = cpm_uart_stop_rx, | |
1123 | .enable_ms = cpm_uart_enable_ms, | |
1124 | .break_ctl = cpm_uart_break_ctl, | |
1125 | .startup = cpm_uart_startup, | |
1126 | .shutdown = cpm_uart_shutdown, | |
1127 | .set_termios = cpm_uart_set_termios, | |
1128 | .type = cpm_uart_type, | |
1129 | .release_port = cpm_uart_release_port, | |
1130 | .request_port = cpm_uart_request_port, | |
1131 | .config_port = cpm_uart_config_port, | |
1132 | .verify_port = cpm_uart_verify_port, | |
8e21d04c JW |
1133 | #ifdef CONFIG_CONSOLE_POLL |
1134 | .poll_get_char = cpm_get_poll_char, | |
1135 | .poll_put_char = cpm_put_poll_char, | |
1136 | #endif | |
1da177e4 LT |
1137 | }; |
1138 | ||
7ae87036 SW |
1139 | struct uart_cpm_port cpm_uart_ports[UART_NR]; |
1140 | ||
c1dcfd9d SW |
1141 | static int cpm_uart_init_port(struct device_node *np, |
1142 | struct uart_cpm_port *pinfo) | |
7ae87036 SW |
1143 | { |
1144 | const u32 *data; | |
c1dcfd9d | 1145 | void __iomem *mem, *pram; |
7ae87036 SW |
1146 | int len; |
1147 | int ret; | |
7485d26b | 1148 | int i; |
7ae87036 | 1149 | |
80776554 LP |
1150 | data = of_get_property(np, "clock", NULL); |
1151 | if (data) { | |
1152 | struct clk *clk = clk_get(NULL, (const char*)data); | |
1153 | if (!IS_ERR(clk)) | |
1154 | pinfo->clk = clk; | |
1155 | } | |
1156 | if (!pinfo->clk) { | |
1157 | data = of_get_property(np, "fsl,cpm-brg", &len); | |
1158 | if (!data || len != 4) { | |
1159 | printk(KERN_ERR "CPM UART %s has no/invalid " | |
1160 | "fsl,cpm-brg property.\n", np->name); | |
1161 | return -EINVAL; | |
1162 | } | |
1163 | pinfo->brg = *data; | |
7ae87036 | 1164 | } |
7ae87036 SW |
1165 | |
1166 | data = of_get_property(np, "fsl,cpm-command", &len); | |
1167 | if (!data || len != 4) { | |
1168 | printk(KERN_ERR "CPM UART %s has no/invalid " | |
1169 | "fsl,cpm-command property.\n", np->name); | |
1170 | return -EINVAL; | |
1171 | } | |
1172 | pinfo->command = *data; | |
1173 | ||
1174 | mem = of_iomap(np, 0); | |
1175 | if (!mem) | |
1176 | return -ENOMEM; | |
1177 | ||
7ae87036 SW |
1178 | if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") || |
1179 | of_device_is_compatible(np, "fsl,cpm2-scc-uart")) { | |
1180 | pinfo->sccp = mem; | |
d464df26 | 1181 | pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np); |
7ae87036 SW |
1182 | } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") || |
1183 | of_device_is_compatible(np, "fsl,cpm2-smc-uart")) { | |
1184 | pinfo->flags |= FLAG_SMC; | |
1185 | pinfo->smcp = mem; | |
d464df26 | 1186 | pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np); |
7ae87036 SW |
1187 | } else { |
1188 | ret = -ENODEV; | |
d464df26 LP |
1189 | goto out_mem; |
1190 | } | |
1191 | ||
1192 | if (!pram) { | |
1193 | ret = -ENOMEM; | |
1194 | goto out_mem; | |
7ae87036 SW |
1195 | } |
1196 | ||
1197 | pinfo->tx_nrfifos = TX_NUM_FIFO; | |
1198 | pinfo->tx_fifosize = TX_BUF_SIZE; | |
1199 | pinfo->rx_nrfifos = RX_NUM_FIFO; | |
1200 | pinfo->rx_fifosize = RX_BUF_SIZE; | |
1201 | ||
1202 | pinfo->port.uartclk = ppc_proc_freq; | |
1203 | pinfo->port.mapbase = (unsigned long)mem; | |
1204 | pinfo->port.type = PORT_CPM; | |
1205 | pinfo->port.ops = &cpm_uart_pops, | |
1206 | pinfo->port.iotype = UPIO_MEM; | |
dc320815 | 1207 | pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize; |
7ae87036 SW |
1208 | spin_lock_init(&pinfo->port.lock); |
1209 | ||
f7578496 | 1210 | pinfo->port.irq = irq_of_parse_and_map(np, 0); |
7ae87036 SW |
1211 | if (pinfo->port.irq == NO_IRQ) { |
1212 | ret = -EINVAL; | |
1213 | goto out_pram; | |
1214 | } | |
1215 | ||
a416bfa2 CL |
1216 | for (i = 0; i < NUM_GPIOS; i++) { |
1217 | int gpio; | |
1218 | ||
1219 | pinfo->gpios[i] = -1; | |
1220 | ||
1221 | gpio = of_get_gpio(np, i); | |
1222 | ||
1223 | if (gpio_is_valid(gpio)) { | |
1224 | ret = gpio_request(gpio, "cpm_uart"); | |
1225 | if (ret) { | |
1226 | pr_err("can't request gpio #%d: %d\n", i, ret); | |
1227 | continue; | |
1228 | } | |
1229 | if (i == GPIO_RTS || i == GPIO_DTR) | |
1230 | ret = gpio_direction_output(gpio, 0); | |
1231 | else | |
1232 | ret = gpio_direction_input(gpio); | |
1233 | if (ret) { | |
1234 | pr_err("can't set direction for gpio #%d: %d\n", | |
1235 | i, ret); | |
1236 | gpio_free(gpio); | |
1237 | continue; | |
1238 | } | |
1239 | pinfo->gpios[i] = gpio; | |
1240 | } | |
1241 | } | |
7485d26b | 1242 | |
4d8107f4 SW |
1243 | #ifdef CONFIG_PPC_EARLY_DEBUG_CPM |
1244 | udbg_putc = NULL; | |
1245 | #endif | |
1246 | ||
7ae87036 SW |
1247 | return cpm_uart_request_port(&pinfo->port); |
1248 | ||
1249 | out_pram: | |
d464df26 | 1250 | cpm_uart_unmap_pram(pinfo, pram); |
7ae87036 SW |
1251 | out_mem: |
1252 | iounmap(mem); | |
1253 | return ret; | |
1254 | } | |
1255 | ||
1da177e4 LT |
1256 | #ifdef CONFIG_SERIAL_CPM_CONSOLE |
1257 | /* | |
1258 | * Print a string to the serial port trying not to disturb | |
1259 | * any possible real use of the port... | |
1260 | * | |
1261 | * Note that this is called with interrupts already disabled | |
1262 | */ | |
1263 | static void cpm_uart_console_write(struct console *co, const char *s, | |
1264 | u_int count) | |
1265 | { | |
7ae87036 | 1266 | struct uart_cpm_port *pinfo = &cpm_uart_ports[co->index]; |
491a7a43 RT |
1267 | unsigned long flags; |
1268 | int nolock = oops_in_progress; | |
1269 | ||
1270 | if (unlikely(nolock)) { | |
1271 | local_irq_save(flags); | |
1272 | } else { | |
1273 | spin_lock_irqsave(&pinfo->port.lock, flags); | |
1274 | } | |
1da177e4 | 1275 | |
8cd774ad | 1276 | cpm_uart_early_write(pinfo, s, count); |
491a7a43 RT |
1277 | |
1278 | if (unlikely(nolock)) { | |
1279 | local_irq_restore(flags); | |
1280 | } else { | |
1281 | spin_unlock_irqrestore(&pinfo->port.lock, flags); | |
1282 | } | |
1da177e4 LT |
1283 | } |
1284 | ||
e27987cd | 1285 | |
1da177e4 LT |
1286 | static int __init cpm_uart_console_setup(struct console *co, char *options) |
1287 | { | |
1da177e4 LT |
1288 | int baud = 38400; |
1289 | int bits = 8; | |
1290 | int parity = 'n'; | |
1291 | int flow = 'n'; | |
1292 | int ret; | |
7ae87036 SW |
1293 | struct uart_cpm_port *pinfo; |
1294 | struct uart_port *port; | |
1295 | ||
7ae87036 SW |
1296 | struct device_node *np = NULL; |
1297 | int i = 0; | |
1298 | ||
1299 | if (co->index >= UART_NR) { | |
1300 | printk(KERN_ERR "cpm_uart: console index %d too high\n", | |
1301 | co->index); | |
1302 | return -ENODEV; | |
1303 | } | |
1304 | ||
1305 | do { | |
1306 | np = of_find_node_by_type(np, "serial"); | |
1307 | if (!np) | |
1308 | return -ENODEV; | |
1309 | ||
1310 | if (!of_device_is_compatible(np, "fsl,cpm1-smc-uart") && | |
1311 | !of_device_is_compatible(np, "fsl,cpm1-scc-uart") && | |
1312 | !of_device_is_compatible(np, "fsl,cpm2-smc-uart") && | |
1313 | !of_device_is_compatible(np, "fsl,cpm2-scc-uart")) | |
1314 | i--; | |
1315 | } while (i++ != co->index); | |
1316 | ||
1317 | pinfo = &cpm_uart_ports[co->index]; | |
1318 | ||
1319 | pinfo->flags |= FLAG_CONSOLE; | |
1320 | port = &pinfo->port; | |
1321 | ||
1322 | ret = cpm_uart_init_port(np, pinfo); | |
1323 | of_node_put(np); | |
1324 | if (ret) | |
1325 | return ret; | |
1326 | ||
1da177e4 LT |
1327 | if (options) { |
1328 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1329 | } else { | |
3dd0dcbe | 1330 | if ((baud = uart_baudrate()) == -1) |
1da177e4 LT |
1331 | baud = 9600; |
1332 | } | |
1333 | ||
1da177e4 | 1334 | if (IS_SMC(pinfo)) { |
ae2d4c39 NL |
1335 | out_be16(&pinfo->smcup->smc_brkcr, 0); |
1336 | cpm_line_cr_cmd(pinfo, CPM_CR_STOP_TX); | |
c1dcfd9d SW |
1337 | clrbits8(&pinfo->smcp->smc_smcm, SMCM_RX | SMCM_TX); |
1338 | clrbits16(&pinfo->smcp->smc_smcmr, SMCMR_REN | SMCMR_TEN); | |
1da177e4 | 1339 | } else { |
ae2d4c39 NL |
1340 | out_be16(&pinfo->sccup->scc_brkcr, 0); |
1341 | cpm_line_cr_cmd(pinfo, CPM_CR_GRA_STOP_TX); | |
c1dcfd9d SW |
1342 | clrbits16(&pinfo->sccp->scc_sccm, UART_SCCM_TX | UART_SCCM_RX); |
1343 | clrbits32(&pinfo->sccp->scc_gsmrl, SCC_GSMRL_ENR | SCC_GSMRL_ENT); | |
1da177e4 LT |
1344 | } |
1345 | ||
1346 | ret = cpm_uart_allocbuf(pinfo, 1); | |
1347 | ||
1348 | if (ret) | |
1349 | return ret; | |
1350 | ||
1351 | cpm_uart_initbd(pinfo); | |
1352 | ||
1353 | if (IS_SMC(pinfo)) | |
1354 | cpm_uart_init_smc(pinfo); | |
1355 | else | |
1356 | cpm_uart_init_scc(pinfo); | |
1357 | ||
1358 | uart_set_options(port, co, baud, parity, bits, flow); | |
d948a29e | 1359 | cpm_line_cr_cmd(pinfo, CPM_CR_RESTART_TX); |
1da177e4 LT |
1360 | |
1361 | return 0; | |
1362 | } | |
1363 | ||
36d2f5a1 | 1364 | static struct uart_driver cpm_reg; |
1da177e4 | 1365 | static struct console cpm_scc_uart_console = { |
36d2f5a1 KG |
1366 | .name = "ttyCPM", |
1367 | .write = cpm_uart_console_write, | |
1368 | .device = uart_console_device, | |
1369 | .setup = cpm_uart_console_setup, | |
1370 | .flags = CON_PRINTBUFFER, | |
1371 | .index = -1, | |
1da177e4 LT |
1372 | .data = &cpm_reg, |
1373 | }; | |
1374 | ||
c1dcfd9d | 1375 | static int __init cpm_uart_console_init(void) |
1da177e4 | 1376 | { |
e27987cd VB |
1377 | register_console(&cpm_scc_uart_console); |
1378 | return 0; | |
1da177e4 LT |
1379 | } |
1380 | ||
1381 | console_initcall(cpm_uart_console_init); | |
1382 | ||
1383 | #define CPM_UART_CONSOLE &cpm_scc_uart_console | |
1384 | #else | |
1385 | #define CPM_UART_CONSOLE NULL | |
1386 | #endif | |
1387 | ||
1388 | static struct uart_driver cpm_reg = { | |
1389 | .owner = THIS_MODULE, | |
1390 | .driver_name = "ttyCPM", | |
1391 | .dev_name = "ttyCPM", | |
1392 | .major = SERIAL_CPM_MAJOR, | |
1393 | .minor = SERIAL_CPM_MINOR, | |
1394 | .cons = CPM_UART_CONSOLE, | |
7ae87036 SW |
1395 | .nr = UART_NR, |
1396 | }; | |
1397 | ||
7ae87036 SW |
1398 | static int probe_index; |
1399 | ||
9671f099 | 1400 | static int cpm_uart_probe(struct platform_device *ofdev) |
7ae87036 SW |
1401 | { |
1402 | int index = probe_index++; | |
1403 | struct uart_cpm_port *pinfo = &cpm_uart_ports[index]; | |
1404 | int ret; | |
1405 | ||
1406 | pinfo->port.line = index; | |
1407 | ||
1408 | if (index >= UART_NR) | |
1409 | return -ENODEV; | |
1410 | ||
696faedd | 1411 | platform_set_drvdata(ofdev, pinfo); |
7ae87036 | 1412 | |
bd86ef37 SW |
1413 | /* initialize the device pointer for the port */ |
1414 | pinfo->port.dev = &ofdev->dev; | |
1415 | ||
61c7a080 | 1416 | ret = cpm_uart_init_port(ofdev->dev.of_node, pinfo); |
7ae87036 SW |
1417 | if (ret) |
1418 | return ret; | |
1419 | ||
1420 | return uart_add_one_port(&cpm_reg, &pinfo->port); | |
1421 | } | |
1422 | ||
ae8d8a14 | 1423 | static int cpm_uart_remove(struct platform_device *ofdev) |
7ae87036 | 1424 | { |
696faedd | 1425 | struct uart_cpm_port *pinfo = platform_get_drvdata(ofdev); |
7ae87036 SW |
1426 | return uart_remove_one_port(&cpm_reg, &pinfo->port); |
1427 | } | |
1428 | ||
1429 | static struct of_device_id cpm_uart_match[] = { | |
1430 | { | |
1431 | .compatible = "fsl,cpm1-smc-uart", | |
1432 | }, | |
1433 | { | |
1434 | .compatible = "fsl,cpm1-scc-uart", | |
1435 | }, | |
1436 | { | |
1437 | .compatible = "fsl,cpm2-smc-uart", | |
1438 | }, | |
1439 | { | |
1440 | .compatible = "fsl,cpm2-scc-uart", | |
1441 | }, | |
1442 | {} | |
1da177e4 | 1443 | }; |
7ae87036 | 1444 | |
793218df | 1445 | static struct platform_driver cpm_uart_driver = { |
4018294b GL |
1446 | .driver = { |
1447 | .name = "cpm_uart", | |
1448 | .owner = THIS_MODULE, | |
1449 | .of_match_table = cpm_uart_match, | |
1450 | }, | |
7ae87036 SW |
1451 | .probe = cpm_uart_probe, |
1452 | .remove = cpm_uart_remove, | |
1453 | }; | |
1454 | ||
1455 | static int __init cpm_uart_init(void) | |
1456 | { | |
1457 | int ret = uart_register_driver(&cpm_reg); | |
1458 | if (ret) | |
1459 | return ret; | |
1460 | ||
793218df | 1461 | ret = platform_driver_register(&cpm_uart_driver); |
7ae87036 SW |
1462 | if (ret) |
1463 | uart_unregister_driver(&cpm_reg); | |
1464 | ||
1465 | return ret; | |
1466 | } | |
1467 | ||
1468 | static void __exit cpm_uart_exit(void) | |
1469 | { | |
793218df | 1470 | platform_driver_unregister(&cpm_uart_driver); |
7ae87036 SW |
1471 | uart_unregister_driver(&cpm_reg); |
1472 | } | |
1da177e4 LT |
1473 | |
1474 | module_init(cpm_uart_init); | |
1475 | module_exit(cpm_uart_exit); | |
1476 | ||
1477 | MODULE_AUTHOR("Kumar Gala/Antoniou Pantelis"); | |
1478 | MODULE_DESCRIPTION("CPM SCC/SMC port driver $Revision: 0.01 $"); | |
1479 | MODULE_LICENSE("GPL"); | |
1480 | MODULE_ALIAS_CHARDEV(SERIAL_CPM_MAJOR, SERIAL_CPM_MINOR); |