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drivers/tty/serial/crisv10.c: remove dead #ifdef blocks
[deliverable/linux.git] / drivers / tty / serial / crisv10.c
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77accbf5 1/*
1da177e4
LT		 2 * Serial port driver for the ETRAX 100LX chip
3 *
77accbf5 4 * Copyright (C) 1998-2007 Axis Communications AB
1da177e4
LT		 5 *
6 * Many, many authors. Based once upon a time on serial.c for 16x50.
7 *
1da177e4
LT		 8 */
9
10static char *serial_version = "$Revision: 1.25 $";
11
1da177e4
LT		 12#include <linux/types.h>
13#include <linux/errno.h>
14#include <linux/signal.h>
15#include <linux/sched.h>
16#include <linux/timer.h>
17#include <linux/interrupt.h>
18#include <linux/tty.h>
19#include <linux/tty_flip.h>
20#include <linux/major.h>
21#include <linux/string.h>
22#include <linux/fcntl.h>
23#include <linux/mm.h>
24#include <linux/slab.h>
25#include <linux/init.h>
1da177e4 26#include <linux/kernel.h>
f392ecfa 27#include <linux/mutex.h>
1977f032 28#include <linux/bitops.h>
9e040a3e
JN		 29#include <linux/seq_file.h>
30#include <linux/delay.h>
31#include <linux/module.h>
32#include <linux/uaccess.h>
33#include <linux/io.h>
1da177e4 34
1da177e4 35#include <asm/irq.h>
77accbf5 36#include <asm/dma.h>
1da177e4 37
556dcee7 38#include <arch/svinto.h>
b1a154db 39#include <arch/system.h>
1da177e4
LT		 40
41/* non-arch dependent serial structures are in linux/serial.h */
42#include <linux/serial.h>
43/* while we keep our own stuff (struct e100_serial) in a local .h file */
77accbf5 44#include "crisv10.h"
1da177e4 45#include <asm/fasttimer.h>
556dcee7 46#include <arch/io_interface_mux.h>
1da177e4
LT		 47
48#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
49#ifndef CONFIG_ETRAX_FAST_TIMER
50#error "Enable FAST_TIMER to use SERIAL_FAST_TIMER"
51#endif
52#endif
53
54#if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \
55 (CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0)
56#error "RX_TIMEOUT_TICKS == 0 not allowed, use 1"
57#endif
58
1da177e4
LT		 59/*
60 * All of the compatibilty code so we can compile serial.c against
61 * older kernels is hidden in serial_compat.h
62 */
63#if defined(LOCAL_HEADERS)
64#include "serial_compat.h"
65#endif
66
1da177e4
LT		 67struct tty_driver *serial_driver;
68
1da177e4
LT		 69/* number of characters left in xmit buffer before we ask for more */
70#define WAKEUP_CHARS 256
71
72//#define SERIAL_DEBUG_INTR
73//#define SERIAL_DEBUG_OPEN
74//#define SERIAL_DEBUG_FLOW
75//#define SERIAL_DEBUG_DATA
76//#define SERIAL_DEBUG_THROTTLE
77//#define SERIAL_DEBUG_IO /* Debug for Extra control and status pins */
78//#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */
79
80/* Enable this to use serial interrupts to handle when you
81 expect the first received event on the serial port to
82 be an error, break or similar. Used to be able to flash IRMA
83 from eLinux */
84#define SERIAL_HANDLE_EARLY_ERRORS
85
1da177e4
LT		 86/* Currently 16 descriptors x 128 bytes = 2048 bytes */
87#define SERIAL_DESCR_BUF_SIZE 256
88
89#define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */
90#define DEF_BAUD_BASE SERIAL_PRESCALE_BASE
91
92/* We don't want to load the system with massive fast timer interrupt
93 * on high baudrates so limit it to 250 us (4kHz) */
94#define MIN_FLUSH_TIME_USEC 250
95
96/* Add an x here to log a lot of timer stuff */
97#define TIMERD(x)
98/* Debug details of interrupt handling */
99#define DINTR1(x) /* irq on/off, errors */
100#define DINTR2(x) /* tx and rx */
101/* Debug flip buffer stuff */
102#define DFLIP(x)
103/* Debug flow control and overview of data flow */
104#define DFLOW(x)
105#define DBAUD(x)
106#define DLOG_INT_TRIG(x)
107
108//#define DEBUG_LOG_INCLUDED
109#ifndef DEBUG_LOG_INCLUDED
110#define DEBUG_LOG(line, string, value)
111#else
112struct debug_log_info
113{
114 unsigned long time;
115 unsigned long timer_data;
116// int line;
117 const char *string;
118 int value;
119};
120#define DEBUG_LOG_SIZE 4096
121
122struct debug_log_info debug_log[DEBUG_LOG_SIZE];
123int debug_log_pos = 0;
124
125#define DEBUG_LOG(_line, _string, _value) do { \
126 if ((_line) == SERIAL_DEBUG_LINE) {\
127 debug_log_func(_line, _string, _value); \
128 }\
129}while(0)
130
131void debug_log_func(int line, const char *string, int value)
132{
133 if (debug_log_pos < DEBUG_LOG_SIZE) {
134 debug_log[debug_log_pos].time = jiffies;
135 debug_log[debug_log_pos].timer_data = *R_TIMER_DATA;
136// debug_log[debug_log_pos].line = line;
137 debug_log[debug_log_pos].string = string;
138 debug_log[debug_log_pos].value = value;
139 debug_log_pos++;
140 }
141 /*printk(string, value);*/
142}
143#endif
144
145#ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS
146/* Default number of timer ticks before flushing rx fifo
147 * When using "little data, low latency applications: use 0
148 * When using "much data applications (PPP)" use ~5
149 */
150#define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5
151#endif
152
153unsigned long timer_data_to_ns(unsigned long timer_data);
154
155static void change_speed(struct e100_serial *info);
156static void rs_throttle(struct tty_struct * tty);
157static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
77accbf5
JN		 158static int rs_write(struct tty_struct *tty,
159 const unsigned char *buf, int count);
1da177e4 160#ifdef CONFIG_ETRAX_RS485
77accbf5
JN		 161static int e100_write_rs485(struct tty_struct *tty,
162 const unsigned char *buf, int count);
1da177e4 163#endif
77accbf5 164static int get_lsr_info(struct e100_serial *info, unsigned int *value);
1da177e4
LT		 165
166
167#define DEF_BAUD 115200 /* 115.2 kbit/s */
1da177e4
LT		 168#define DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */
169/* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */
170#define DEF_TX 0x80 /* or SERIAL_CTRL_B */
171
172/* offsets from R_SERIALx_CTRL */
173
174#define REG_DATA 0
175#define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */
176#define REG_TR_DATA 0
177#define REG_STATUS 1
178#define REG_TR_CTRL 1
179#define REG_REC_CTRL 2
180#define REG_BAUD 3
181#define REG_XOFF 4 /* this is a 32 bit register */
182
183/* The bitfields are the same for all serial ports */
184#define SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd)
185#define SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail)
186#define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
187#define SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err)
188#define SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun)
189
190#define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK)
191
192/* Values for info->errorcode */
193#define ERRCODE_SET_BREAK (TTY_BREAK)
194#define ERRCODE_INSERT 0x100
195#define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK)
196
197#define FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop;
198
199/*
200 * General note regarding the use of IO_* macros in this file:
201 *
202 * We will use the bits defined for DMA channel 6 when using various
203 * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are
204 * the same for all channels (which of course they are).
205 *
206 * We will also use the bits defined for serial port 0 when writing commands
207 * to the different ports, as these bits too are the same for all ports.
208 */
209
210
211/* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */
212static const unsigned long e100_ser_int_mask = 0
213#ifdef CONFIG_ETRAX_SERIAL_PORT0
214| IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
215#endif
216#ifdef CONFIG_ETRAX_SERIAL_PORT1
217| IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
218#endif
219#ifdef CONFIG_ETRAX_SERIAL_PORT2
220| IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
221#endif
222#ifdef CONFIG_ETRAX_SERIAL_PORT3
223| IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
224#endif
225;
226unsigned long r_alt_ser_baudrate_shadow = 0;
227
228/* this is the data for the four serial ports in the etrax100 */
229/* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */
230/* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */
231
232static struct e100_serial rs_table[] = {
233 { .baud = DEF_BAUD,
d7283353 234 .ioport = (unsigned char *)R_SERIAL0_CTRL,
1da177e4
LT		 235 .irq = 1U << 12, /* uses DMA 6 and 7 */
236 .oclrintradr = R_DMA_CH6_CLR_INTR,
237 .ofirstadr = R_DMA_CH6_FIRST,
238 .ocmdadr = R_DMA_CH6_CMD,
239 .ostatusadr = R_DMA_CH6_STATUS,
240 .iclrintradr = R_DMA_CH7_CLR_INTR,
241 .ifirstadr = R_DMA_CH7_FIRST,
242 .icmdadr = R_DMA_CH7_CMD,
243 .idescradr = R_DMA_CH7_DESCR,
1da177e4
LT		 244 .rx_ctrl = DEF_RX,
245 .tx_ctrl = DEF_TX,
246 .iseteop = 2,
77accbf5
JN		 247 .dma_owner = dma_ser0,
248 .io_if = if_serial_0,
1da177e4
LT		 249#ifdef CONFIG_ETRAX_SERIAL_PORT0
250 .enabled = 1,
251#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
252 .dma_out_enabled = 1,
77accbf5
JN		 253 .dma_out_nbr = SER0_TX_DMA_NBR,
254 .dma_out_irq_nbr = SER0_DMA_TX_IRQ_NBR,
9cfb5c05 255 .dma_out_irq_flags = 0,
77accbf5 256 .dma_out_irq_description = "serial 0 dma tr",
1da177e4
LT		 257#else
258 .dma_out_enabled = 0,
77accbf5
JN		 259 .dma_out_nbr = UINT_MAX,
260 .dma_out_irq_nbr = 0,
261 .dma_out_irq_flags = 0,
262 .dma_out_irq_description = NULL,
1da177e4
LT		 263#endif
264#ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
265 .dma_in_enabled = 1,
77accbf5
JN		 266 .dma_in_nbr = SER0_RX_DMA_NBR,
267 .dma_in_irq_nbr = SER0_DMA_RX_IRQ_NBR,
9cfb5c05 268 .dma_in_irq_flags = 0,
77accbf5 269 .dma_in_irq_description = "serial 0 dma rec",
1da177e4 270#else
77accbf5
JN		 271 .dma_in_enabled = 0,
272 .dma_in_nbr = UINT_MAX,
273 .dma_in_irq_nbr = 0,
274 .dma_in_irq_flags = 0,
275 .dma_in_irq_description = NULL,
1da177e4
LT		 276#endif
277#else
278 .enabled = 0,
77accbf5 279 .io_if_description = NULL,
1da177e4
LT		 280 .dma_out_enabled = 0,
281 .dma_in_enabled = 0
282#endif
283
284}, /* ttyS0 */
1da177e4 285 { .baud = DEF_BAUD,
d7283353 286 .ioport = (unsigned char *)R_SERIAL1_CTRL,
1da177e4
LT		 287 .irq = 1U << 16, /* uses DMA 8 and 9 */
288 .oclrintradr = R_DMA_CH8_CLR_INTR,
289 .ofirstadr = R_DMA_CH8_FIRST,
290 .ocmdadr = R_DMA_CH8_CMD,
291 .ostatusadr = R_DMA_CH8_STATUS,
292 .iclrintradr = R_DMA_CH9_CLR_INTR,
293 .ifirstadr = R_DMA_CH9_FIRST,
294 .icmdadr = R_DMA_CH9_CMD,
295 .idescradr = R_DMA_CH9_DESCR,
1da177e4
LT		 296 .rx_ctrl = DEF_RX,
297 .tx_ctrl = DEF_TX,
298 .iseteop = 3,
77accbf5
JN		 299 .dma_owner = dma_ser1,
300 .io_if = if_serial_1,
1da177e4
LT		 301#ifdef CONFIG_ETRAX_SERIAL_PORT1
302 .enabled = 1,
77accbf5 303 .io_if_description = "ser1",
1da177e4
LT		 304#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
305 .dma_out_enabled = 1,
77accbf5
JN		 306 .dma_out_nbr = SER1_TX_DMA_NBR,
307 .dma_out_irq_nbr = SER1_DMA_TX_IRQ_NBR,
9cfb5c05 308 .dma_out_irq_flags = 0,
77accbf5 309 .dma_out_irq_description = "serial 1 dma tr",
1da177e4
LT		 310#else
311 .dma_out_enabled = 0,
77accbf5
JN		 312 .dma_out_nbr = UINT_MAX,
313 .dma_out_irq_nbr = 0,
314 .dma_out_irq_flags = 0,
315 .dma_out_irq_description = NULL,
1da177e4
LT		 316#endif
317#ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
318 .dma_in_enabled = 1,
77accbf5
JN		 319 .dma_in_nbr = SER1_RX_DMA_NBR,
320 .dma_in_irq_nbr = SER1_DMA_RX_IRQ_NBR,
9cfb5c05 321 .dma_in_irq_flags = 0,
77accbf5 322 .dma_in_irq_description = "serial 1 dma rec",
1da177e4 323#else
77accbf5
JN		 324 .dma_in_enabled = 0,
325 .dma_in_enabled = 0,
326 .dma_in_nbr = UINT_MAX,
327 .dma_in_irq_nbr = 0,
328 .dma_in_irq_flags = 0,
329 .dma_in_irq_description = NULL,
1da177e4
LT		 330#endif
331#else
332 .enabled = 0,
77accbf5
JN		 333 .io_if_description = NULL,
334 .dma_in_irq_nbr = 0,
1da177e4
LT		 335 .dma_out_enabled = 0,
336 .dma_in_enabled = 0
337#endif
338}, /* ttyS1 */
339
340 { .baud = DEF_BAUD,
d7283353 341 .ioport = (unsigned char *)R_SERIAL2_CTRL,
1da177e4
LT		 342 .irq = 1U << 4, /* uses DMA 2 and 3 */
343 .oclrintradr = R_DMA_CH2_CLR_INTR,
344 .ofirstadr = R_DMA_CH2_FIRST,
345 .ocmdadr = R_DMA_CH2_CMD,
346 .ostatusadr = R_DMA_CH2_STATUS,
347 .iclrintradr = R_DMA_CH3_CLR_INTR,
348 .ifirstadr = R_DMA_CH3_FIRST,
349 .icmdadr = R_DMA_CH3_CMD,
350 .idescradr = R_DMA_CH3_DESCR,
1da177e4
LT		 351 .rx_ctrl = DEF_RX,
352 .tx_ctrl = DEF_TX,
353 .iseteop = 0,
77accbf5
JN		 354 .dma_owner = dma_ser2,
355 .io_if = if_serial_2,
1da177e4
LT		 356#ifdef CONFIG_ETRAX_SERIAL_PORT2
357 .enabled = 1,
77accbf5 358 .io_if_description = "ser2",
1da177e4
LT		 359#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
360 .dma_out_enabled = 1,
77accbf5
JN		 361 .dma_out_nbr = SER2_TX_DMA_NBR,
362 .dma_out_irq_nbr = SER2_DMA_TX_IRQ_NBR,
9cfb5c05 363 .dma_out_irq_flags = 0,
77accbf5 364 .dma_out_irq_description = "serial 2 dma tr",
1da177e4
LT		 365#else
366 .dma_out_enabled = 0,
77accbf5
JN		 367 .dma_out_nbr = UINT_MAX,
368 .dma_out_irq_nbr = 0,
369 .dma_out_irq_flags = 0,
370 .dma_out_irq_description = NULL,
1da177e4
LT		 371#endif
372#ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
373 .dma_in_enabled = 1,
77accbf5
JN		 374 .dma_in_nbr = SER2_RX_DMA_NBR,
375 .dma_in_irq_nbr = SER2_DMA_RX_IRQ_NBR,
9cfb5c05 376 .dma_in_irq_flags = 0,
77accbf5 377 .dma_in_irq_description = "serial 2 dma rec",
1da177e4 378#else
77accbf5
JN		 379 .dma_in_enabled = 0,
380 .dma_in_nbr = UINT_MAX,
381 .dma_in_irq_nbr = 0,
382 .dma_in_irq_flags = 0,
383 .dma_in_irq_description = NULL,
1da177e4
LT		 384#endif
385#else
386 .enabled = 0,
77accbf5 387 .io_if_description = NULL,
1da177e4
LT		 388 .dma_out_enabled = 0,
389 .dma_in_enabled = 0
390#endif
391 }, /* ttyS2 */
392
393 { .baud = DEF_BAUD,
d7283353 394 .ioport = (unsigned char *)R_SERIAL3_CTRL,
1da177e4
LT		 395 .irq = 1U << 8, /* uses DMA 4 and 5 */
396 .oclrintradr = R_DMA_CH4_CLR_INTR,
397 .ofirstadr = R_DMA_CH4_FIRST,
398 .ocmdadr = R_DMA_CH4_CMD,
399 .ostatusadr = R_DMA_CH4_STATUS,
400 .iclrintradr = R_DMA_CH5_CLR_INTR,
401 .ifirstadr = R_DMA_CH5_FIRST,
402 .icmdadr = R_DMA_CH5_CMD,
403 .idescradr = R_DMA_CH5_DESCR,
1da177e4
LT		 404 .rx_ctrl = DEF_RX,
405 .tx_ctrl = DEF_TX,
406 .iseteop = 1,
77accbf5
JN		 407 .dma_owner = dma_ser3,
408 .io_if = if_serial_3,
1da177e4
LT		 409#ifdef CONFIG_ETRAX_SERIAL_PORT3
410 .enabled = 1,
77accbf5 411 .io_if_description = "ser3",
1da177e4
LT		 412#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
413 .dma_out_enabled = 1,
77accbf5
JN		 414 .dma_out_nbr = SER3_TX_DMA_NBR,
415 .dma_out_irq_nbr = SER3_DMA_TX_IRQ_NBR,
9cfb5c05 416 .dma_out_irq_flags = 0,
77accbf5 417 .dma_out_irq_description = "serial 3 dma tr",
1da177e4
LT		 418#else
419 .dma_out_enabled = 0,
77accbf5
JN		 420 .dma_out_nbr = UINT_MAX,
421 .dma_out_irq_nbr = 0,
422 .dma_out_irq_flags = 0,
423 .dma_out_irq_description = NULL,
1da177e4
LT		 424#endif
425#ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
426 .dma_in_enabled = 1,
77accbf5
JN		 427 .dma_in_nbr = SER3_RX_DMA_NBR,
428 .dma_in_irq_nbr = SER3_DMA_RX_IRQ_NBR,
9cfb5c05 429 .dma_in_irq_flags = 0,
77accbf5 430 .dma_in_irq_description = "serial 3 dma rec",
1da177e4 431#else
77accbf5
JN		 432 .dma_in_enabled = 0,
433 .dma_in_nbr = UINT_MAX,
434 .dma_in_irq_nbr = 0,
435 .dma_in_irq_flags = 0,
436 .dma_in_irq_description = NULL
1da177e4
LT		 437#endif
438#else
439 .enabled = 0,
77accbf5 440 .io_if_description = NULL,
1da177e4
LT		 441 .dma_out_enabled = 0,
442 .dma_in_enabled = 0
443#endif
444 } /* ttyS3 */
1da177e4
LT		 445};
446
447
448#define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial))
449
1da177e4
LT		 450#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
451static struct fast_timer fast_timers[NR_PORTS];
452#endif
453
454#ifdef CONFIG_ETRAX_SERIAL_PROC_ENTRY
455#define PROCSTAT(x) x
456struct ser_statistics_type {
457 int overrun_cnt;
458 int early_errors_cnt;
459 int ser_ints_ok_cnt;
460 int errors_cnt;
461 unsigned long int processing_flip;
462 unsigned long processing_flip_still_room;
463 unsigned long int timeout_flush_cnt;
464 int rx_dma_ints;
465 int tx_dma_ints;
466 int rx_tot;
467 int tx_tot;
468};
469
470static struct ser_statistics_type ser_stat[NR_PORTS];
471
472#else
473
474#define PROCSTAT(x)
475
476#endif /* CONFIG_ETRAX_SERIAL_PROC_ENTRY */
477
478/* RS-485 */
479#if defined(CONFIG_ETRAX_RS485)
480#ifdef CONFIG_ETRAX_FAST_TIMER
481static struct fast_timer fast_timers_rs485[NR_PORTS];
482#endif
483#if defined(CONFIG_ETRAX_RS485_ON_PA)
484static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT;
485#endif
1da177e4
LT		 486#endif
487
488/* Info and macros needed for each ports extra control/status signals. */
489#define E100_STRUCT_PORT(line, pinname) \
490 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
491 (R_PORT_PA_DATA): ( \
492 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
493 (R_PORT_PB_DATA):&dummy_ser[line]))
494
495#define E100_STRUCT_SHADOW(line, pinname) \
496 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
497 (&port_pa_data_shadow): ( \
498 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
499 (&port_pb_data_shadow):&dummy_ser[line]))
500#define E100_STRUCT_MASK(line, pinname) \
501 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
502 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT): ( \
503 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
504 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT):DUMMY_##pinname##_MASK))
505
506#define DUMMY_DTR_MASK 1
507#define DUMMY_RI_MASK 2
508#define DUMMY_DSR_MASK 4
509#define DUMMY_CD_MASK 8
510static unsigned char dummy_ser[NR_PORTS] = {0xFF, 0xFF, 0xFF,0xFF};
511
512/* If not all status pins are used or disabled, use mixed mode */
513#ifdef CONFIG_ETRAX_SERIAL_PORT0
514
515#define SER0_PA_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PA_BIT+CONFIG_ETRAX_SER0_RI_ON_PA_BIT+CONFIG_ETRAX_SER0_DSR_ON_PA_BIT+CONFIG_ETRAX_SER0_CD_ON_PA_BIT)
516
517#if SER0_PA_BITSUM != -4
518# if CONFIG_ETRAX_SER0_DTR_ON_PA_BIT == -1
519# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
520# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
521# endif
522# endif
523# if CONFIG_ETRAX_SER0_RI_ON_PA_BIT == -1
524# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
525# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
526# endif
527# endif
528# if CONFIG_ETRAX_SER0_DSR_ON_PA_BIT == -1
529# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
530# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
531# endif
532# endif
533# if CONFIG_ETRAX_SER0_CD_ON_PA_BIT == -1
534# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
535# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
536# endif
537# endif
538#endif
539
540#define SER0_PB_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PB_BIT+CONFIG_ETRAX_SER0_RI_ON_PB_BIT+CONFIG_ETRAX_SER0_DSR_ON_PB_BIT+CONFIG_ETRAX_SER0_CD_ON_PB_BIT)
541
542#if SER0_PB_BITSUM != -4
543# if CONFIG_ETRAX_SER0_DTR_ON_PB_BIT == -1
544# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
545# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
546# endif
547# endif
548# if CONFIG_ETRAX_SER0_RI_ON_PB_BIT == -1
549# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
550# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
551# endif
552# endif
553# if CONFIG_ETRAX_SER0_DSR_ON_PB_BIT == -1
554# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
555# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
556# endif
557# endif
558# if CONFIG_ETRAX_SER0_CD_ON_PB_BIT == -1
559# ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
560# define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
561# endif
562# endif
563#endif
564
565#endif /* PORT0 */
566
567
568#ifdef CONFIG_ETRAX_SERIAL_PORT1
569
570#define SER1_PA_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PA_BIT+CONFIG_ETRAX_SER1_RI_ON_PA_BIT+CONFIG_ETRAX_SER1_DSR_ON_PA_BIT+CONFIG_ETRAX_SER1_CD_ON_PA_BIT)
571
572#if SER1_PA_BITSUM != -4
573# if CONFIG_ETRAX_SER1_DTR_ON_PA_BIT == -1
574# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
575# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
576# endif
577# endif
578# if CONFIG_ETRAX_SER1_RI_ON_PA_BIT == -1
579# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
580# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
581# endif
582# endif
583# if CONFIG_ETRAX_SER1_DSR_ON_PA_BIT == -1
584# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
585# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
586# endif
587# endif
588# if CONFIG_ETRAX_SER1_CD_ON_PA_BIT == -1
589# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
590# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
591# endif
592# endif
593#endif
594
595#define SER1_PB_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PB_BIT+CONFIG_ETRAX_SER1_RI_ON_PB_BIT+CONFIG_ETRAX_SER1_DSR_ON_PB_BIT+CONFIG_ETRAX_SER1_CD_ON_PB_BIT)
596
597#if SER1_PB_BITSUM != -4
598# if CONFIG_ETRAX_SER1_DTR_ON_PB_BIT == -1
599# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
600# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
601# endif
602# endif
603# if CONFIG_ETRAX_SER1_RI_ON_PB_BIT == -1
604# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
605# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
606# endif
607# endif
608# if CONFIG_ETRAX_SER1_DSR_ON_PB_BIT == -1
609# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
610# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
611# endif
612# endif
613# if CONFIG_ETRAX_SER1_CD_ON_PB_BIT == -1
614# ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
615# define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
616# endif
617# endif
618#endif
619
620#endif /* PORT1 */
621
622#ifdef CONFIG_ETRAX_SERIAL_PORT2
623
624#define SER2_PA_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PA_BIT+CONFIG_ETRAX_SER2_RI_ON_PA_BIT+CONFIG_ETRAX_SER2_DSR_ON_PA_BIT+CONFIG_ETRAX_SER2_CD_ON_PA_BIT)
625
626#if SER2_PA_BITSUM != -4
627# if CONFIG_ETRAX_SER2_DTR_ON_PA_BIT == -1
628# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
629# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
630# endif
631# endif
632# if CONFIG_ETRAX_SER2_RI_ON_PA_BIT == -1
633# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
634# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
635# endif
636# endif
637# if CONFIG_ETRAX_SER2_DSR_ON_PA_BIT == -1
638# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
639# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
640# endif
641# endif
642# if CONFIG_ETRAX_SER2_CD_ON_PA_BIT == -1
643# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
644# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
645# endif
646# endif
647#endif
648
649#define SER2_PB_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PB_BIT+CONFIG_ETRAX_SER2_RI_ON_PB_BIT+CONFIG_ETRAX_SER2_DSR_ON_PB_BIT+CONFIG_ETRAX_SER2_CD_ON_PB_BIT)
650
651#if SER2_PB_BITSUM != -4
652# if CONFIG_ETRAX_SER2_DTR_ON_PB_BIT == -1
653# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
654# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
655# endif
656# endif
657# if CONFIG_ETRAX_SER2_RI_ON_PB_BIT == -1
658# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
659# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
660# endif
661# endif
662# if CONFIG_ETRAX_SER2_DSR_ON_PB_BIT == -1
663# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
664# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
665# endif
666# endif
667# if CONFIG_ETRAX_SER2_CD_ON_PB_BIT == -1
668# ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
669# define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
670# endif
671# endif
672#endif
673
674#endif /* PORT2 */
675
676#ifdef CONFIG_ETRAX_SERIAL_PORT3
677
678#define SER3_PA_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PA_BIT+CONFIG_ETRAX_SER3_RI_ON_PA_BIT+CONFIG_ETRAX_SER3_DSR_ON_PA_BIT+CONFIG_ETRAX_SER3_CD_ON_PA_BIT)
679
680#if SER3_PA_BITSUM != -4
681# if CONFIG_ETRAX_SER3_DTR_ON_PA_BIT == -1
682# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
683# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
684# endif
685# endif
686# if CONFIG_ETRAX_SER3_RI_ON_PA_BIT == -1
687# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
688# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
689# endif
690# endif
691# if CONFIG_ETRAX_SER3_DSR_ON_PA_BIT == -1
692# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
693# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
694# endif
695# endif
696# if CONFIG_ETRAX_SER3_CD_ON_PA_BIT == -1
697# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
698# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
699# endif
700# endif
701#endif
702
703#define SER3_PB_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PB_BIT+CONFIG_ETRAX_SER3_RI_ON_PB_BIT+CONFIG_ETRAX_SER3_DSR_ON_PB_BIT+CONFIG_ETRAX_SER3_CD_ON_PB_BIT)
704
705#if SER3_PB_BITSUM != -4
706# if CONFIG_ETRAX_SER3_DTR_ON_PB_BIT == -1
707# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
708# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
709# endif
710# endif
711# if CONFIG_ETRAX_SER3_RI_ON_PB_BIT == -1
712# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
713# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
714# endif
715# endif
716# if CONFIG_ETRAX_SER3_DSR_ON_PB_BIT == -1
717# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
718# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
719# endif
720# endif
721# if CONFIG_ETRAX_SER3_CD_ON_PB_BIT == -1
722# ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
723# define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
724# endif
725# endif
726#endif
727
728#endif /* PORT3 */
729
730
731#if defined(CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED) || \
732 defined(CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED) || \
733 defined(CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED) || \
734 defined(CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED)
735#define CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
736#endif
737
738#ifdef CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED
739/* The pins can be mixed on PA and PB */
740#define CONTROL_PINS_PORT_NOT_USED(line) \
741 &dummy_ser[line], &dummy_ser[line], \
742 &dummy_ser[line], &dummy_ser[line], \
743 &dummy_ser[line], &dummy_ser[line], \
744 &dummy_ser[line], &dummy_ser[line], \
745 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
746
747
748struct control_pins
749{
750 volatile unsigned char *dtr_port;
751 unsigned char *dtr_shadow;
752 volatile unsigned char *ri_port;
753 unsigned char *ri_shadow;
754 volatile unsigned char *dsr_port;
755 unsigned char *dsr_shadow;
756 volatile unsigned char *cd_port;
757 unsigned char *cd_shadow;
758
759 unsigned char dtr_mask;
760 unsigned char ri_mask;
761 unsigned char dsr_mask;
762 unsigned char cd_mask;
763};
764
765static const struct control_pins e100_modem_pins[NR_PORTS] =
766{
767 /* Ser 0 */
768 {
769#ifdef CONFIG_ETRAX_SERIAL_PORT0
770 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
771 E100_STRUCT_PORT(0,RI), E100_STRUCT_SHADOW(0,RI),
772 E100_STRUCT_PORT(0,DSR), E100_STRUCT_SHADOW(0,DSR),
773 E100_STRUCT_PORT(0,CD), E100_STRUCT_SHADOW(0,CD),
774 E100_STRUCT_MASK(0,DTR),
775 E100_STRUCT_MASK(0,RI),
776 E100_STRUCT_MASK(0,DSR),
777 E100_STRUCT_MASK(0,CD)
778#else
779 CONTROL_PINS_PORT_NOT_USED(0)
780#endif
781 },
782
783 /* Ser 1 */
784 {
785#ifdef CONFIG_ETRAX_SERIAL_PORT1
786 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
787 E100_STRUCT_PORT(1,RI), E100_STRUCT_SHADOW(1,RI),
788 E100_STRUCT_PORT(1,DSR), E100_STRUCT_SHADOW(1,DSR),
789 E100_STRUCT_PORT(1,CD), E100_STRUCT_SHADOW(1,CD),
790 E100_STRUCT_MASK(1,DTR),
791 E100_STRUCT_MASK(1,RI),
792 E100_STRUCT_MASK(1,DSR),
793 E100_STRUCT_MASK(1,CD)
794#else
795 CONTROL_PINS_PORT_NOT_USED(1)
796#endif
797 },
798
799 /* Ser 2 */
800 {
801#ifdef CONFIG_ETRAX_SERIAL_PORT2
802 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
803 E100_STRUCT_PORT(2,RI), E100_STRUCT_SHADOW(2,RI),
804 E100_STRUCT_PORT(2,DSR), E100_STRUCT_SHADOW(2,DSR),
805 E100_STRUCT_PORT(2,CD), E100_STRUCT_SHADOW(2,CD),
806 E100_STRUCT_MASK(2,DTR),
807 E100_STRUCT_MASK(2,RI),
808 E100_STRUCT_MASK(2,DSR),
809 E100_STRUCT_MASK(2,CD)
810#else
811 CONTROL_PINS_PORT_NOT_USED(2)
812#endif
813 },
814
815 /* Ser 3 */
816 {
817#ifdef CONFIG_ETRAX_SERIAL_PORT3
818 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
819 E100_STRUCT_PORT(3,RI), E100_STRUCT_SHADOW(3,RI),
820 E100_STRUCT_PORT(3,DSR), E100_STRUCT_SHADOW(3,DSR),
821 E100_STRUCT_PORT(3,CD), E100_STRUCT_SHADOW(3,CD),
822 E100_STRUCT_MASK(3,DTR),
823 E100_STRUCT_MASK(3,RI),
824 E100_STRUCT_MASK(3,DSR),
825 E100_STRUCT_MASK(3,CD)
826#else
827 CONTROL_PINS_PORT_NOT_USED(3)
828#endif
829 }
830};
831#else /* CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
832
833/* All pins are on either PA or PB for each serial port */
834#define CONTROL_PINS_PORT_NOT_USED(line) \
835 &dummy_ser[line], &dummy_ser[line], \
836 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
837
838
839struct control_pins
840{
841 volatile unsigned char *port;
842 unsigned char *shadow;
843
844 unsigned char dtr_mask;
845 unsigned char ri_mask;
846 unsigned char dsr_mask;
847 unsigned char cd_mask;
848};
849
850#define dtr_port port
851#define dtr_shadow shadow
852#define ri_port port
853#define ri_shadow shadow
854#define dsr_port port
855#define dsr_shadow shadow
856#define cd_port port
857#define cd_shadow shadow
858
859static const struct control_pins e100_modem_pins[NR_PORTS] =
860{
861 /* Ser 0 */
862 {
863#ifdef CONFIG_ETRAX_SERIAL_PORT0
864 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
865 E100_STRUCT_MASK(0,DTR),
866 E100_STRUCT_MASK(0,RI),
867 E100_STRUCT_MASK(0,DSR),
868 E100_STRUCT_MASK(0,CD)
869#else
870 CONTROL_PINS_PORT_NOT_USED(0)
871#endif
872 },
873
874 /* Ser 1 */
875 {
876#ifdef CONFIG_ETRAX_SERIAL_PORT1
877 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
878 E100_STRUCT_MASK(1,DTR),
879 E100_STRUCT_MASK(1,RI),
880 E100_STRUCT_MASK(1,DSR),
881 E100_STRUCT_MASK(1,CD)
882#else
883 CONTROL_PINS_PORT_NOT_USED(1)
884#endif
885 },
886
887 /* Ser 2 */
888 {
889#ifdef CONFIG_ETRAX_SERIAL_PORT2
890 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
891 E100_STRUCT_MASK(2,DTR),
892 E100_STRUCT_MASK(2,RI),
893 E100_STRUCT_MASK(2,DSR),
894 E100_STRUCT_MASK(2,CD)
895#else
896 CONTROL_PINS_PORT_NOT_USED(2)
897#endif
898 },
899
900 /* Ser 3 */
901 {
902#ifdef CONFIG_ETRAX_SERIAL_PORT3
903 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
904 E100_STRUCT_MASK(3,DTR),
905 E100_STRUCT_MASK(3,RI),
906 E100_STRUCT_MASK(3,DSR),
907 E100_STRUCT_MASK(3,CD)
908#else
909 CONTROL_PINS_PORT_NOT_USED(3)
910#endif
911 }
912};
913#endif /* !CONFIG_ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
914
915#define E100_RTS_MASK 0x20
916#define E100_CTS_MASK 0x40
917
918/* All serial port signals are active low:
919 * active = 0 -> 3.3V to RS-232 driver -> -12V on RS-232 level
920 * inactive = 1 -> 0V to RS-232 driver -> +12V on RS-232 level
921 *
922 * These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip
923 */
924
925/* Output */
926#define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK)
927/* Input */
d7283353 928#define E100_CTS_GET(info) ((info)->ioport[REG_STATUS] & E100_CTS_MASK)
1da177e4
LT		 929
930/* These are typically PA or PB and 0 means 0V, 1 means 3.3V */
931/* Is an output */
932#define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask)
933
934/* Normally inputs */
935#define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask)
936#define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask)
937
938/* Input */
939#define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask)
940
1da177e4
LT		 941/* Calculate the chartime depending on baudrate, numbor of bits etc. */
942static void update_char_time(struct e100_serial * info)
943{
adc8d746 944 tcflag_t cflags = info->port.tty->termios.c_cflag;
1da177e4
LT		 945 int bits;
946
947 /* calc. number of bits / data byte */
948 /* databits + startbit and 1 stopbit */
949 if ((cflags & CSIZE) == CS7)
950 bits = 9;
951 else
952 bits = 10;
953
954 if (cflags & CSTOPB) /* 2 stopbits ? */
955 bits++;
956
957 if (cflags & PARENB) /* parity bit ? */
958 bits++;
959
960 /* calc timeout */
961 info->char_time_usec = ((bits * 1000000) / info->baud) + 1;
962 info->flush_time_usec = 4*info->char_time_usec;
963 if (info->flush_time_usec < MIN_FLUSH_TIME_USEC)
964 info->flush_time_usec = MIN_FLUSH_TIME_USEC;
965
966}
967
968/*
969 * This function maps from the Bxxxx defines in asm/termbits.h into real
970 * baud rates.
971 */
972
973static int
974cflag_to_baud(unsigned int cflag)
975{
976 static int baud_table[] = {
977 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
978 4800, 9600, 19200, 38400 };
979
980 static int ext_baud_table[] = {
981 0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000,
982 0, 0, 0, 0, 0, 0, 0, 0 };
983
984 if (cflag & CBAUDEX)
985 return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
986 else
987 return baud_table[cflag & CBAUD];
988}
989
990/* and this maps to an etrax100 hardware baud constant */
991
992static unsigned char
993cflag_to_etrax_baud(unsigned int cflag)
994{
995 char retval;
996
997 static char baud_table[] = {
998 -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 };
999
1000 static char ext_baud_table[] = {
1001 -1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 };
1002
1003 if (cflag & CBAUDEX)
1004 retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
1005 else
1006 retval = baud_table[cflag & CBAUD];
1007
1008 if (retval < 0) {
1009 printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag);
1010 retval = 5; /* choose default 9600 instead */
1011 }
1012
1013 return retval | (retval << 4); /* choose same for both TX and RX */
1014}
1015
1016
1017/* Various static support functions */
1018
1019/* Functions to set or clear DTR/RTS on the requested line */
1020/* It is complicated by the fact that RTS is a serial port register, while
1021 * DTR might not be implemented in the HW at all, and if it is, it can be on
1022 * any general port.
1023 */
1024
1025
1026static inline void
1027e100_dtr(struct e100_serial *info, int set)
1028{
1da177e4
LT		 1029 unsigned char mask = e100_modem_pins[info->line].dtr_mask;
1030
1031#ifdef SERIAL_DEBUG_IO
1032 printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask);
1033 printk("ser%i shadow before 0x%02X get: %i\n",
1034 info->line, *e100_modem_pins[info->line].dtr_shadow,
1035 E100_DTR_GET(info));
1036#endif
1037 /* DTR is active low */
1038 {
1039 unsigned long flags;
1040
77accbf5 1041 local_irq_save(flags);
1da177e4
LT		 1042 *e100_modem_pins[info->line].dtr_shadow &= ~mask;
1043 *e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask);
1044 *e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow;
77accbf5 1045 local_irq_restore(flags);
1da177e4
LT		 1046 }
1047
1048#ifdef SERIAL_DEBUG_IO
1049 printk("ser%i shadow after 0x%02X get: %i\n",
1050 info->line, *e100_modem_pins[info->line].dtr_shadow,
1051 E100_DTR_GET(info));
1052#endif
1da177e4
LT		 1053}
1054
1055/* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive
1056 * 0=0V , 1=3.3V
1057 */
1058static inline void
1059e100_rts(struct e100_serial *info, int set)
1060{
1da177e4 1061 unsigned long flags;
77accbf5 1062 local_irq_save(flags);
1da177e4
LT		 1063 info->rx_ctrl &= ~E100_RTS_MASK;
1064 info->rx_ctrl |= (set ? 0 : E100_RTS_MASK); /* RTS is active low */
d7283353 1065 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
77accbf5 1066 local_irq_restore(flags);
1da177e4
LT		 1067#ifdef SERIAL_DEBUG_IO
1068 printk("ser%i rts %i\n", info->line, set);
1069#endif
1da177e4
LT		 1070}
1071
1072
1073/* If this behaves as a modem, RI and CD is an output */
1074static inline void
1075e100_ri_out(struct e100_serial *info, int set)
1076{
1da177e4
LT		 1077 /* RI is active low */
1078 {
1079 unsigned char mask = e100_modem_pins[info->line].ri_mask;
1080 unsigned long flags;
1081
77accbf5 1082 local_irq_save(flags);
1da177e4
LT		 1083 *e100_modem_pins[info->line].ri_shadow &= ~mask;
1084 *e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask);
1085 *e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow;
77accbf5 1086 local_irq_restore(flags);
1da177e4 1087 }
1da177e4
LT		 1088}
1089static inline void
1090e100_cd_out(struct e100_serial *info, int set)
1091{
1da177e4
LT		 1092 /* CD is active low */
1093 {
1094 unsigned char mask = e100_modem_pins[info->line].cd_mask;
1095 unsigned long flags;
1096
77accbf5 1097 local_irq_save(flags);
1da177e4
LT		 1098 *e100_modem_pins[info->line].cd_shadow &= ~mask;
1099 *e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask);
1100 *e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow;
77accbf5 1101 local_irq_restore(flags);
1da177e4 1102 }
1da177e4
LT		 1103}
1104
1105static inline void
1106e100_disable_rx(struct e100_serial *info)
1107{
1da177e4 1108 /* disable the receiver */
d7283353 1109 info->ioport[REG_REC_CTRL] =
1da177e4 1110 (info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1da177e4
LT		 1111}
1112
1113static inline void
1114e100_enable_rx(struct e100_serial *info)
1115{
1da177e4 1116 /* enable the receiver */
d7283353 1117 info->ioport[REG_REC_CTRL] =
1da177e4 1118 (info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1da177e4
LT		 1119}
1120
1121/* the rx DMA uses both the dma_descr and the dma_eop interrupts */
1122
1123static inline void
1124e100_disable_rxdma_irq(struct e100_serial *info)
1125{
1126#ifdef SERIAL_DEBUG_INTR
1127 printk("rxdma_irq(%d): 0\n",info->line);
1128#endif
1129 DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line));
1130 *R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3);
1131}
1132
1133static inline void
1134e100_enable_rxdma_irq(struct e100_serial *info)
1135{
1136#ifdef SERIAL_DEBUG_INTR
1137 printk("rxdma_irq(%d): 1\n",info->line);
1138#endif
1139 DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line));
1140 *R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3);
1141}
1142
1143/* the tx DMA uses only dma_descr interrupt */
1144
41c28ff1 1145static void e100_disable_txdma_irq(struct e100_serial *info)
1da177e4
LT		 1146{
1147#ifdef SERIAL_DEBUG_INTR
1148 printk("txdma_irq(%d): 0\n",info->line);
1149#endif
1150 DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line));
1151 *R_IRQ_MASK2_CLR = info->irq;
1152}
1153
41c28ff1 1154static void e100_enable_txdma_irq(struct e100_serial *info)
1da177e4
LT		 1155{
1156#ifdef SERIAL_DEBUG_INTR
1157 printk("txdma_irq(%d): 1\n",info->line);
1158#endif
1159 DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line));
1160 *R_IRQ_MASK2_SET = info->irq;
1161}
1162
41c28ff1 1163static void e100_disable_txdma_channel(struct e100_serial *info)
1da177e4
LT		 1164{
1165 unsigned long flags;
1166
1167 /* Disable output DMA channel for the serial port in question
025dfdaf 1168 * ( set to something other than serialX)
1da177e4 1169 */
77accbf5 1170 local_irq_save(flags);
1da177e4
LT		 1171 DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line));
1172 if (info->line == 0) {
1173 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==
1174 IO_STATE(R_GEN_CONFIG, dma6, serial0)) {
1175 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1176 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
1177 }
1178 } else if (info->line == 1) {
1179 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==
1180 IO_STATE(R_GEN_CONFIG, dma8, serial1)) {
1181 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1182 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
1183 }
1184 } else if (info->line == 2) {
1185 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==
1186 IO_STATE(R_GEN_CONFIG, dma2, serial2)) {
1187 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1188 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
1189 }
1190 } else if (info->line == 3) {
1191 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==
1192 IO_STATE(R_GEN_CONFIG, dma4, serial3)) {
1193 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1194 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
1195 }
1196 }
1197 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1198 local_irq_restore(flags);
1da177e4
LT		 1199}
1200
1201
41c28ff1 1202static void e100_enable_txdma_channel(struct e100_serial *info)
1da177e4
LT		 1203{
1204 unsigned long flags;
1205
77accbf5 1206 local_irq_save(flags);
1da177e4
LT		 1207 DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line));
1208 /* Enable output DMA channel for the serial port in question */
1209 if (info->line == 0) {
1210 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1211 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0);
1212 } else if (info->line == 1) {
1213 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1214 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1);
1215 } else if (info->line == 2) {
1216 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1217 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2);
1218 } else if (info->line == 3) {
1219 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1220 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3);
1221 }
1222 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1223 local_irq_restore(flags);
1da177e4
LT		 1224}
1225
41c28ff1 1226static void e100_disable_rxdma_channel(struct e100_serial *info)
1da177e4
LT		 1227{
1228 unsigned long flags;
1229
1230 /* Disable input DMA channel for the serial port in question
025dfdaf 1231 * ( set to something other than serialX)
1da177e4 1232 */
77accbf5 1233 local_irq_save(flags);
1da177e4
LT		 1234 if (info->line == 0) {
1235 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==
1236 IO_STATE(R_GEN_CONFIG, dma7, serial0)) {
1237 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1238 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused);
1239 }
1240 } else if (info->line == 1) {
1241 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==
1242 IO_STATE(R_GEN_CONFIG, dma9, serial1)) {
1243 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1244 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb);
1245 }
1246 } else if (info->line == 2) {
1247 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==
1248 IO_STATE(R_GEN_CONFIG, dma3, serial2)) {
1249 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1250 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0);
1251 }
1252 } else if (info->line == 3) {
1253 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==
1254 IO_STATE(R_GEN_CONFIG, dma5, serial3)) {
1255 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1256 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1);
1257 }
1258 }
1259 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1260 local_irq_restore(flags);
1da177e4
LT		 1261}
1262
1263
41c28ff1 1264static void e100_enable_rxdma_channel(struct e100_serial *info)
1da177e4
LT		 1265{
1266 unsigned long flags;
1267
77accbf5 1268 local_irq_save(flags);
1da177e4
LT		 1269 /* Enable input DMA channel for the serial port in question */
1270 if (info->line == 0) {
1271 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1272 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0);
1273 } else if (info->line == 1) {
1274 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1275 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1);
1276 } else if (info->line == 2) {
1277 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1278 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2);
1279 } else if (info->line == 3) {
1280 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1281 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3);
1282 }
1283 *R_GEN_CONFIG = genconfig_shadow;
77accbf5 1284 local_irq_restore(flags);
1da177e4
LT		 1285}
1286
1287#ifdef SERIAL_HANDLE_EARLY_ERRORS
1288/* in order to detect and fix errors on the first byte
1289 we have to use the serial interrupts as well. */
1290
1291static inline void
1292e100_disable_serial_data_irq(struct e100_serial *info)
1293{
1294#ifdef SERIAL_DEBUG_INTR
1295 printk("ser_irq(%d): 0\n",info->line);
1296#endif
1297 DINTR1(DEBUG_LOG(info->line,"IRQ disable data_irq %i\n", info->line));
1298 *R_IRQ_MASK1_CLR = (1U << (8+2*info->line));
1299}
1300
1301static inline void
1302e100_enable_serial_data_irq(struct e100_serial *info)
1303{
1304#ifdef SERIAL_DEBUG_INTR
1305 printk("ser_irq(%d): 1\n",info->line);
1306 printk("**** %d = %d\n",
1307 (8+2*info->line),
1308 (1U << (8+2*info->line)));
1309#endif
1310 DINTR1(DEBUG_LOG(info->line,"IRQ enable data_irq %i\n", info->line));
1311 *R_IRQ_MASK1_SET = (1U << (8+2*info->line));
1312}
1313#endif
1314
1315static inline void
1316e100_disable_serial_tx_ready_irq(struct e100_serial *info)
1317{
1318#ifdef SERIAL_DEBUG_INTR
1319 printk("ser_tx_irq(%d): 0\n",info->line);
1320#endif
1321 DINTR1(DEBUG_LOG(info->line,"IRQ disable ready_irq %i\n", info->line));
1322 *R_IRQ_MASK1_CLR = (1U << (8+1+2*info->line));
1323}
1324
1325static inline void
1326e100_enable_serial_tx_ready_irq(struct e100_serial *info)
1327{
1328#ifdef SERIAL_DEBUG_INTR
1329 printk("ser_tx_irq(%d): 1\n",info->line);
1330 printk("**** %d = %d\n",
1331 (8+1+2*info->line),
1332 (1U << (8+1+2*info->line)));
1333#endif
1334 DINTR2(DEBUG_LOG(info->line,"IRQ enable ready_irq %i\n", info->line));
1335 *R_IRQ_MASK1_SET = (1U << (8+1+2*info->line));
1336}
1337
1338static inline void e100_enable_rx_irq(struct e100_serial *info)
1339{
1340 if (info->uses_dma_in)
1341 e100_enable_rxdma_irq(info);
1342 else
1343 e100_enable_serial_data_irq(info);
1344}
1345static inline void e100_disable_rx_irq(struct e100_serial *info)
1346{
1347 if (info->uses_dma_in)
1348 e100_disable_rxdma_irq(info);
1349 else
1350 e100_disable_serial_data_irq(info);
1351}
1352
1353#if defined(CONFIG_ETRAX_RS485)
1354/* Enable RS-485 mode on selected port. This is UGLY. */
1355static int
6fd1af4c 1356e100_enable_rs485(struct tty_struct *tty, struct serial_rs485 *r)
1da177e4
LT		 1357{
1358 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1359
1360#if defined(CONFIG_ETRAX_RS485_ON_PA)
1361 *R_PORT_PA_DATA = port_pa_data_shadow |= (1 << rs485_pa_bit);
1362#endif
1da177e4 1363
c7213fc4
JN		 1364 info->rs485 = *r;
1365
1366 /* Maximum delay before RTS equal to 1000 */
1367 if (info->rs485.delay_rts_before_send >= 1000)
1da177e4 1368 info->rs485.delay_rts_before_send = 1000;
c7213fc4 1369
1da177e4
LT		 1370/* printk("rts: on send = %i, after = %i, enabled = %i",
1371 info->rs485.rts_on_send,
1372 info->rs485.rts_after_sent,
1373 info->rs485.enabled
1374 );
1375*/
1376 return 0;
1377}
1378
1379static int
77accbf5 1380e100_write_rs485(struct tty_struct *tty,
1da177e4
LT		 1381 const unsigned char *buf, int count)
1382{
1383 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
6fd1af4c 1384 int old_value = (info->rs485.flags) & SER_RS485_ENABLED;
1da177e4
LT		 1385
1386 /* rs485 is always implicitly enabled if we're using the ioctl()
6fd1af4c 1387 * but it doesn't have to be set in the serial_rs485
1da177e4
LT		 1388 * (to be backward compatible with old apps)
1389 * So we store, set and restore it.
1390 */
6fd1af4c 1391 info->rs485.flags |= SER_RS485_ENABLED;
1da177e4 1392 /* rs_write now deals with RS485 if enabled */
77accbf5 1393 count = rs_write(tty, buf, count);
6fd1af4c
CS		 1394 if (!old_value)
1395 info->rs485.flags &= ~(SER_RS485_ENABLED);
1da177e4
LT		 1396 return count;
1397}
1398
1399#ifdef CONFIG_ETRAX_FAST_TIMER
1400/* Timer function to toggle RTS when using FAST_TIMER */
1401static void rs485_toggle_rts_timer_function(unsigned long data)
1402{
1403 struct e100_serial *info = (struct e100_serial *)data;
1404
1405 fast_timers_rs485[info->line].function = NULL;
6fd1af4c 1406 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1da177e4
LT		 1407#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
1408 e100_enable_rx(info);
1409 e100_enable_rx_irq(info);
1410#endif
1411}
1412#endif
1413#endif /* CONFIG_ETRAX_RS485 */
1414
1415/*
1416 * ------------------------------------------------------------
1417 * rs_stop() and rs_start()
1418 *
1419 * This routines are called before setting or resetting tty->stopped.
1420 * They enable or disable transmitter using the XOFF registers, as necessary.
1421 * ------------------------------------------------------------
1422 */
1423
1424static void
1425rs_stop(struct tty_struct *tty)
1426{
1427 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1428 if (info) {
1429 unsigned long flags;
1430 unsigned long xoff;
1431
77accbf5 1432 local_irq_save(flags);
1da177e4
LT		 1433 DFLOW(DEBUG_LOG(info->line, "XOFF rs_stop xmit %i\n",
1434 CIRC_CNT(info->xmit.head,
1435 info->xmit.tail,SERIAL_XMIT_SIZE)));
1436
a88487c7
TI		 1437 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char,
1438 STOP_CHAR(info->port.tty));
1da177e4 1439 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop);
adc8d746 1440 if (tty->termios.c_iflag & IXON ) {
1da177e4
LT		 1441 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1442 }
1443
d7283353 1444 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
77accbf5 1445 local_irq_restore(flags);
1da177e4
LT		 1446 }
1447}
1448
1449static void
1450rs_start(struct tty_struct *tty)
1451{
1452 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1453 if (info) {
1454 unsigned long flags;
1455 unsigned long xoff;
1456
77accbf5 1457 local_irq_save(flags);
1da177e4
LT		 1458 DFLOW(DEBUG_LOG(info->line, "XOFF rs_start xmit %i\n",
1459 CIRC_CNT(info->xmit.head,
1460 info->xmit.tail,SERIAL_XMIT_SIZE)));
1461 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty));
1462 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
adc8d746 1463 if (tty->termios.c_iflag & IXON ) {
1da177e4
LT		 1464 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1465 }
1466
d7283353 1467 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1da177e4
LT		 1468 if (!info->uses_dma_out &&
1469 info->xmit.head != info->xmit.tail && info->xmit.buf)
1470 e100_enable_serial_tx_ready_irq(info);
1471
77accbf5 1472 local_irq_restore(flags);
1da177e4
LT		 1473 }
1474}
1475
1476/*
1477 * ----------------------------------------------------------------------
1478 *
1479 * Here starts the interrupt handling routines. All of the following
1480 * subroutines are declared as inline and are folded into
1481 * rs_interrupt(). They were separated out for readability's sake.
1482 *
1483 * Note: rs_interrupt() is a "fast" interrupt, which means that it
1484 * runs with interrupts turned off. People who may want to modify
1485 * rs_interrupt() should try to keep the interrupt handler as fast as
1486 * possible. After you are done making modifications, it is not a bad
1487 * idea to do:
1488 *
1489 * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
1490 *
1491 * and look at the resulting assemble code in serial.s.
1492 *
1493 * - Ted Ts'o (tytso@mit.edu), 7-Mar-93
1494 * -----------------------------------------------------------------------
1495 */
1496
1497/*
1498 * This routine is used by the interrupt handler to schedule
1499 * processing in the software interrupt portion of the driver.
1500 */
41c28ff1 1501static void rs_sched_event(struct e100_serial *info, int event)
1da177e4
LT		 1502{
1503 if (info->event & (1 << event))
1504 return;
1505 info->event |= 1 << event;
1506 schedule_work(&info->work);
1507}
1508
1509/* The output DMA channel is free - use it to send as many chars as possible
1510 * NOTES:
1511 * We don't pay attention to info->x_char, which means if the TTY wants to
1512 * use XON/XOFF it will set info->x_char but we won't send any X char!
1513 *
1514 * To implement this, we'd just start a DMA send of 1 byte pointing at a
1515 * buffer containing the X char, and skip updating xmit. We'd also have to
1516 * check if the last sent char was the X char when we enter this function
1517 * the next time, to avoid updating xmit with the sent X value.
1518 */
1519
1520static void
1521transmit_chars_dma(struct e100_serial *info)
1522{
1523 unsigned int c, sentl;
1524 struct etrax_dma_descr *descr;
1525
1da177e4
LT		 1526 /* acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1527 *info->oclrintradr =
1528 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1529 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1530
1531#ifdef SERIAL_DEBUG_INTR
1532 if (info->line == SERIAL_DEBUG_LINE)
1533 printk("tc\n");
1534#endif
1535 if (!info->tr_running) {
1536 /* weirdo... we shouldn't get here! */
1537 printk(KERN_WARNING "Achtung: transmit_chars_dma with !tr_running\n");
1538 return;
1539 }
1540
1541 descr = &info->tr_descr;
1542
1543 /* first get the amount of bytes sent during the last DMA transfer,
1544 and update xmit accordingly */
1545
1546 /* if the stop bit was not set, all data has been sent */
1547 if (!(descr->status & d_stop)) {
1548 sentl = descr->sw_len;
1549 } else
1550 /* otherwise we find the amount of data sent here */
1551 sentl = descr->hw_len;
1552
1553 DFLOW(DEBUG_LOG(info->line, "TX %i done\n", sentl));
1554
1555 /* update stats */
1556 info->icount.tx += sentl;
1557
1558 /* update xmit buffer */
1559 info->xmit.tail = (info->xmit.tail + sentl) & (SERIAL_XMIT_SIZE - 1);
1560
1561 /* if there is only a few chars left in the buf, wake up the blocked
1562 write if any */
1563 if (CIRC_CNT(info->xmit.head,
1564 info->xmit.tail,
1565 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
1566 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
1567
1568 /* find out the largest amount of consecutive bytes we want to send now */
1569
1570 c = CIRC_CNT_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
1571
1572 /* Don't send all in one DMA transfer - divide it so we wake up
1573 * application before all is sent
1574 */
1575
1576 if (c >= 4*WAKEUP_CHARS)
1577 c = c/2;
1578
1579 if (c <= 0) {
1580 /* our job here is done, don't schedule any new DMA transfer */
1581 info->tr_running = 0;
1582
1583#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
6fd1af4c 1584 if (info->rs485.flags & SER_RS485_ENABLED) {
1da177e4
LT		 1585 /* Set a short timer to toggle RTS */
1586 start_one_shot_timer(&fast_timers_rs485[info->line],
1587 rs485_toggle_rts_timer_function,
1588 (unsigned long)info,
1589 info->char_time_usec*2,
1590 "RS-485");
1591 }
1592#endif /* RS485 */
1593 return;
1594 }
1595
1596 /* ok we can schedule a dma send of c chars starting at info->xmit.tail */
1597 /* set up the descriptor correctly for output */
1598 DFLOW(DEBUG_LOG(info->line, "TX %i\n", c));
1599 descr->ctrl = d_int | d_eol | d_wait; /* Wait needed for tty_wait_until_sent() */
1600 descr->sw_len = c;
1601 descr->buf = virt_to_phys(info->xmit.buf + info->xmit.tail);
1602 descr->status = 0;
1603
1604 *info->ofirstadr = virt_to_phys(descr); /* write to R_DMAx_FIRST */
1605 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1606
1607 /* DMA is now running (hopefully) */
1608} /* transmit_chars_dma */
1609
1610static void
1611start_transmit(struct e100_serial *info)
1612{
1613#if 0
1614 if (info->line == SERIAL_DEBUG_LINE)
1615 printk("x\n");
1616#endif
1617
1618 info->tr_descr.sw_len = 0;
1619 info->tr_descr.hw_len = 0;
1620 info->tr_descr.status = 0;
1621 info->tr_running = 1;
1622 if (info->uses_dma_out)
1623 transmit_chars_dma(info);
1624 else
1625 e100_enable_serial_tx_ready_irq(info);
1626} /* start_transmit */
1627
1628#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
1629static int serial_fast_timer_started = 0;
1630static int serial_fast_timer_expired = 0;
1631static void flush_timeout_function(unsigned long data);
1632#define START_FLUSH_FAST_TIMER_TIME(info, string, usec) {\
1633 unsigned long timer_flags; \
77accbf5 1634 local_irq_save(timer_flags); \
1da177e4
LT		 1635 if (fast_timers[info->line].function == NULL) { \
1636 serial_fast_timer_started++; \
1637 TIMERD(DEBUG_LOG(info->line, "start_timer %i ", info->line)); \
1638 TIMERD(DEBUG_LOG(info->line, "num started: %i\n", serial_fast_timer_started)); \
1639 start_one_shot_timer(&fast_timers[info->line], \
1640 flush_timeout_function, \
1641 (unsigned long)info, \
1642 (usec), \
1643 string); \
1644 } \
1645 else { \
1646 TIMERD(DEBUG_LOG(info->line, "timer %i already running\n", info->line)); \
1647 } \
77accbf5 1648 local_irq_restore(timer_flags); \
1da177e4
LT		 1649}
1650#define START_FLUSH_FAST_TIMER(info, string) START_FLUSH_FAST_TIMER_TIME(info, string, info->flush_time_usec)
1651
1652#else
1653#define START_FLUSH_FAST_TIMER_TIME(info, string, usec)
1654#define START_FLUSH_FAST_TIMER(info, string)
1655#endif
1656
1657static struct etrax_recv_buffer *
1658alloc_recv_buffer(unsigned int size)
1659{
1660 struct etrax_recv_buffer *buffer;
1661
1662 if (!(buffer = kmalloc(sizeof *buffer + size, GFP_ATOMIC)))
1663 return NULL;
1664
1665 buffer->next = NULL;
1666 buffer->length = 0;
1667 buffer->error = TTY_NORMAL;
1668
1669 return buffer;
1670}
1671
1672static void
1673append_recv_buffer(struct e100_serial *info, struct etrax_recv_buffer *buffer)
1674{
1675 unsigned long flags;
1676
77accbf5 1677 local_irq_save(flags);
1da177e4
LT		 1678
1679 if (!info->first_recv_buffer)
1680 info->first_recv_buffer = buffer;
1681 else
1682 info->last_recv_buffer->next = buffer;
1683
1684 info->last_recv_buffer = buffer;
1685
1686 info->recv_cnt += buffer->length;
1687 if (info->recv_cnt > info->max_recv_cnt)
1688 info->max_recv_cnt = info->recv_cnt;
1689
77accbf5 1690 local_irq_restore(flags);
1da177e4
LT		 1691}
1692
1693static int
1694add_char_and_flag(struct e100_serial *info, unsigned char data, unsigned char flag)
1695{
1696 struct etrax_recv_buffer *buffer;
1697 if (info->uses_dma_in) {
1698 if (!(buffer = alloc_recv_buffer(4)))
1699 return 0;
1700
1701 buffer->length = 1;
1702 buffer->error = flag;
1703 buffer->buffer[0] = data;
1704
1705 append_recv_buffer(info, buffer);
1706
1707 info->icount.rx++;
1708 } else {
92a19f9c 1709 tty_insert_flip_char(&info->port, data, flag);
1da177e4
LT		 1710 info->icount.rx++;
1711 }
1712
1713 return 1;
1714}
1715
41c28ff1
AB		 1716static unsigned int handle_descr_data(struct e100_serial *info,
1717 struct etrax_dma_descr *descr,
1718 unsigned int recvl)
1da177e4
LT		 1719{
1720 struct etrax_recv_buffer *buffer = phys_to_virt(descr->buf) - sizeof *buffer;
1721
1722 if (info->recv_cnt + recvl > 65536) {
3d43b7d5 1723 printk(KERN_WARNING
71cc2c21 1724 "%s: Too much pending incoming serial data! Dropping %u bytes.\n", __func__, recvl);
1da177e4
LT		 1725 return 0;
1726 }
1727
1728 buffer->length = recvl;
1729
1730 if (info->errorcode == ERRCODE_SET_BREAK)
1731 buffer->error = TTY_BREAK;
1732 info->errorcode = 0;
1733
1734 append_recv_buffer(info, buffer);
1735
1736 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
71cc2c21 1737 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1da177e4
LT		 1738
1739 descr->buf = virt_to_phys(buffer->buffer);
1740
1741 return recvl;
1742}
1743
41c28ff1 1744static unsigned int handle_all_descr_data(struct e100_serial *info)
1da177e4
LT		 1745{
1746 struct etrax_dma_descr *descr;
1747 unsigned int recvl;
1748 unsigned int ret = 0;
1749
1750 while (1)
1751 {
1752 descr = &info->rec_descr[info->cur_rec_descr];
1753
1754 if (descr == phys_to_virt(*info->idescradr))
1755 break;
1756
1757 if (++info->cur_rec_descr == SERIAL_RECV_DESCRIPTORS)
1758 info->cur_rec_descr = 0;
1759
1760 /* find out how many bytes were read */
1761
1762 /* if the eop bit was not set, all data has been received */
1763 if (!(descr->status & d_eop)) {
1764 recvl = descr->sw_len;
1765 } else {
1766 /* otherwise we find the amount of data received here */
1767 recvl = descr->hw_len;
1768 }
1769
1770 /* Reset the status information */
1771 descr->status = 0;
1772
1773 DFLOW( DEBUG_LOG(info->line, "RX %lu\n", recvl);
a88487c7 1774 if (info->port.tty->stopped) {
1da177e4
LT		 1775 unsigned char *buf = phys_to_virt(descr->buf);
1776 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[0]);
1777 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[1]);
1778 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[2]);
1779 }
1780 );
1781
1782 /* update stats */
1783 info->icount.rx += recvl;
1784
1785 ret += handle_descr_data(info, descr, recvl);
1786 }
1787
1788 return ret;
1789}
1790
41c28ff1 1791static void receive_chars_dma(struct e100_serial *info)
1da177e4
LT		 1792{
1793 struct tty_struct *tty;
1794 unsigned char rstat;
1795
1da177e4
LT		 1796 /* Acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1797 *info->iclrintradr =
1798 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1799 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1800
a88487c7 1801 tty = info->port.tty;
1da177e4
LT		 1802 if (!tty) /* Something wrong... */
1803 return;
1804
1805#ifdef SERIAL_HANDLE_EARLY_ERRORS
1806 if (info->uses_dma_in)
1807 e100_enable_serial_data_irq(info);
1808#endif
1809
1810 if (info->errorcode == ERRCODE_INSERT_BREAK)
1811 add_char_and_flag(info, '\0', TTY_BREAK);
1812
1813 handle_all_descr_data(info);
1814
1815 /* Read the status register to detect errors */
d7283353 1816 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 1817 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
1818 DFLOW(DEBUG_LOG(info->line, "XOFF detect stat %x\n", rstat));
1819 }
1820
1821 if (rstat & SER_ERROR_MASK) {
1822 /* If we got an error, we must reset it by reading the
1823 * data_in field
1824 */
d7283353 1825 unsigned char data = info->ioport[REG_DATA];
1da177e4
LT		 1826
1827 PROCSTAT(ser_stat[info->line].errors_cnt++);
1828 DEBUG_LOG(info->line, "#dERR: s d 0x%04X\n",
1829 ((rstat & SER_ERROR_MASK) << 8) | data);
1830
1831 if (rstat & SER_PAR_ERR_MASK)
1832 add_char_and_flag(info, data, TTY_PARITY);
1833 else if (rstat & SER_OVERRUN_MASK)
1834 add_char_and_flag(info, data, TTY_OVERRUN);
1835 else if (rstat & SER_FRAMING_ERR_MASK)
1836 add_char_and_flag(info, data, TTY_FRAME);
1837 }
1838
1839 START_FLUSH_FAST_TIMER(info, "receive_chars");
1840
1841 /* Restart the receiving DMA */
1842 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
1843}
1844
41c28ff1 1845static int start_recv_dma(struct e100_serial *info)
1da177e4
LT		 1846{
1847 struct etrax_dma_descr *descr = info->rec_descr;
1848 struct etrax_recv_buffer *buffer;
1849 int i;
1850
1851 /* Set up the receiving descriptors */
1852 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) {
1853 if (!(buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE)))
71cc2c21 1854 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1da177e4
LT		 1855
1856 descr[i].ctrl = d_int;
1857 descr[i].buf = virt_to_phys(buffer->buffer);
1858 descr[i].sw_len = SERIAL_DESCR_BUF_SIZE;
1859 descr[i].hw_len = 0;
1860 descr[i].status = 0;
1861 descr[i].next = virt_to_phys(&descr[i+1]);
1862 }
1863
1864 /* Link the last descriptor to the first */
1865 descr[i-1].next = virt_to_phys(&descr[0]);
1866
1867 /* Start with the first descriptor in the list */
1868 info->cur_rec_descr = 0;
1869
1870 /* Start the DMA */
1871 *info->ifirstadr = virt_to_phys(&descr[info->cur_rec_descr]);
1872 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1873
1874 /* Input DMA should be running now */
1875 return 1;
1876}
1877
1878static void
1879start_receive(struct e100_serial *info)
1880{
1da177e4
LT		 1881 if (info->uses_dma_in) {
1882 /* reset the input dma channel to be sure it works */
1883
1884 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
1885 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
1886 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
1887
1888 start_recv_dma(info);
1889 }
1890}
1891
1892
1da177e4
LT		 1893/* the bits in the MASK2 register are laid out like this:
1894 DMAI_EOP DMAI_DESCR DMAO_EOP DMAO_DESCR
1895 where I is the input channel and O is the output channel for the port.
1896 info->irq is the bit number for the DMAO_DESCR so to check the others we
1897 shift info->irq to the left.
1898*/
1899
1900/* dma output channel interrupt handler
1901 this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or
1902 DMA8(ser1) when they have finished a descriptor with the intr flag set.
1903*/
1904
1905static irqreturn_t
7d12e780 1906tr_interrupt(int irq, void *dev_id)
1da177e4
LT		 1907{
1908 struct e100_serial *info;
1909 unsigned long ireg;
1910 int i;
1911 int handled = 0;
1912
1da177e4
LT		 1913 /* find out the line that caused this irq and get it from rs_table */
1914
1915 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
1916
1917 for (i = 0; i < NR_PORTS; i++) {
1918 info = rs_table + i;
1919 if (!info->enabled || !info->uses_dma_out)
1920 continue;
1921 /* check for dma_descr (don't need to check for dma_eop in output dma for serial */
1922 if (ireg & info->irq) {
1923 handled = 1;
1924 /* we can send a new dma bunch. make it so. */
1925 DINTR2(DEBUG_LOG(info->line, "tr_interrupt %i\n", i));
1926 /* Read jiffies_usec first,
1927 * we want this time to be as late as possible
1928 */
1929 PROCSTAT(ser_stat[info->line].tx_dma_ints++);
1930 info->last_tx_active_usec = GET_JIFFIES_USEC();
1931 info->last_tx_active = jiffies;
1932 transmit_chars_dma(info);
1933 }
1934
1935 /* FIXME: here we should really check for a change in the
1936 status lines and if so call status_handle(info) */
1937 }
1938 return IRQ_RETVAL(handled);
1939} /* tr_interrupt */
1940
1941/* dma input channel interrupt handler */
1942
1943static irqreturn_t
7d12e780 1944rec_interrupt(int irq, void *dev_id)
1da177e4
LT		 1945{
1946 struct e100_serial *info;
1947 unsigned long ireg;
1948 int i;
1949 int handled = 0;
1950
1da177e4
LT		 1951 /* find out the line that caused this irq and get it from rs_table */
1952
1953 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
1954
1955 for (i = 0; i < NR_PORTS; i++) {
1956 info = rs_table + i;
1957 if (!info->enabled || !info->uses_dma_in)
1958 continue;
1959 /* check for both dma_eop and dma_descr for the input dma channel */
1960 if (ireg & ((info->irq << 2) | (info->irq << 3))) {
1961 handled = 1;
1962 /* we have received something */
1963 receive_chars_dma(info);
1964 }
1965
1966 /* FIXME: here we should really check for a change in the
1967 status lines and if so call status_handle(info) */
1968 }
1969 return IRQ_RETVAL(handled);
1970} /* rec_interrupt */
1971
41c28ff1 1972static int force_eop_if_needed(struct e100_serial *info)
1da177e4
LT		 1973{
1974 /* We check data_avail bit to determine if data has
1975 * arrived since last time
1976 */
d7283353 1977 unsigned char rstat = info->ioport[REG_STATUS];
1da177e4
LT		 1978
1979 /* error or datavail? */
1980 if (rstat & SER_ERROR_MASK) {
1981 /* Some error has occurred. If there has been valid data, an
1982 * EOP interrupt will be made automatically. If no data, the
1983 * normal ser_interrupt should be enabled and handle it.
1984 * So do nothing!
1985 */
1986 DEBUG_LOG(info->line, "timeout err: rstat 0x%03X\n",
1987 rstat | (info->line << 8));
1988 return 0;
1989 }
1990
1991 if (rstat & SER_DATA_AVAIL_MASK) {
1992 /* Ok data, no error, count it */
1993 TIMERD(DEBUG_LOG(info->line, "timeout: rstat 0x%03X\n",
1994 rstat | (info->line << 8)));
1995 /* Read data to clear status flags */
d7283353 1996 (void)info->ioport[REG_DATA];
1da177e4
LT		 1997
1998 info->forced_eop = 0;
1999 START_FLUSH_FAST_TIMER(info, "magic");
2000 return 0;
2001 }
2002
2003 /* hit the timeout, force an EOP for the input
2004 * dma channel if we haven't already
2005 */
2006 if (!info->forced_eop) {
2007 info->forced_eop = 1;
2008 PROCSTAT(ser_stat[info->line].timeout_flush_cnt++);
2009 TIMERD(DEBUG_LOG(info->line, "timeout EOP %i\n", info->line));
2010 FORCE_EOP(info);
2011 }
2012
2013 return 1;
2014}
2015
41c28ff1 2016static void flush_to_flip_buffer(struct e100_serial *info)
1da177e4 2017{
1da177e4 2018 struct etrax_recv_buffer *buffer;
1da177e4 2019 unsigned long flags;
1da177e4 2020
77accbf5 2021 local_irq_save(flags);
1da177e4 2022
2090ab05 2023 while ((buffer = info->first_recv_buffer) != NULL) {
1da177e4
LT		 2024 unsigned int count = buffer->length;
2025
05c7cd39 2026 tty_insert_flip_string(&info->port, buffer->buffer, count);
1da177e4 2027 info->recv_cnt -= count;
1da177e4
LT		 2028
2029 if (count == buffer->length) {
2030 info->first_recv_buffer = buffer->next;
2031 kfree(buffer);
2032 } else {
2033 buffer->length -= count;
2034 memmove(buffer->buffer, buffer->buffer + count, buffer->length);
2035 buffer->error = TTY_NORMAL;
2036 }
2037 }
2038
2039 if (!info->first_recv_buffer)
2040 info->last_recv_buffer = NULL;
2041
77accbf5 2042 local_irq_restore(flags);
1da177e4 2043
77accbf5 2044 /* This includes a check for low-latency */
2e124b4a 2045 tty_flip_buffer_push(&info->port);
1da177e4
LT		 2046}
2047
41c28ff1 2048static void check_flush_timeout(struct e100_serial *info)
1da177e4
LT		 2049{
2050 /* Flip what we've got (if we can) */
2051 flush_to_flip_buffer(info);
2052
2053 /* We might need to flip later, but not to fast
2054 * since the system is busy processing input... */
2055 if (info->first_recv_buffer)
2056 START_FLUSH_FAST_TIMER_TIME(info, "flip", 2000);
2057
2058 /* Force eop last, since data might have come while we're processing
2059 * and if we started the slow timer above, we won't start a fast
2060 * below.
2061 */
2062 force_eop_if_needed(info);
2063}
2064
2065#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
2066static void flush_timeout_function(unsigned long data)
2067{
2068 struct e100_serial *info = (struct e100_serial *)data;
2069
2070 fast_timers[info->line].function = NULL;
2071 serial_fast_timer_expired++;
8faaaead 2072 TIMERD(DEBUG_LOG(info->line, "flush_timeout %i ", info->line));
1da177e4
LT		 2073 TIMERD(DEBUG_LOG(info->line, "num expired: %i\n", serial_fast_timer_expired));
2074 check_flush_timeout(info);
2075}
2076
2077#else
2078
2079/* dma fifo/buffer timeout handler
2080 forces an end-of-packet for the dma input channel if no chars
2081 have been received for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS/100 s.
2082*/
2083
2084static struct timer_list flush_timer;
2085
2086static void
2087timed_flush_handler(unsigned long ptr)
2088{
2089 struct e100_serial *info;
2090 int i;
2091
1da177e4
LT		 2092 for (i = 0; i < NR_PORTS; i++) {
2093 info = rs_table + i;
2094 if (info->uses_dma_in)
2095 check_flush_timeout(info);
2096 }
2097
2098 /* restart flush timer */
2099 mod_timer(&flush_timer, jiffies + CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS);
2100}
2101#endif
2102
2103#ifdef SERIAL_HANDLE_EARLY_ERRORS
2104
2105/* If there is an error (ie break) when the DMA is running and
2106 * there are no bytes in the fifo the DMA is stopped and we get no
2107 * eop interrupt. Thus we have to monitor the first bytes on a DMA
2108 * transfer, and if it is without error we can turn the serial
2109 * interrupts off.
2110 */
2111
2112/*
2113BREAK handling on ETRAX 100:
2114ETRAX will generate interrupt although there is no stop bit between the
2115characters.
2116
2117Depending on how long the break sequence is, the end of the breaksequence
2118will look differently:
2119| indicates start/end of a character.
2120
2121B= Break character (0x00) with framing error.
2122E= Error byte with parity error received after B characters.
2123F= "Faked" valid byte received immediately after B characters.
2124V= Valid byte
2125
21261.
2127 B BL ___________________________ V
2128.._|__________|__________| |valid data |
2129
2130Multiple frame errors with data == 0x00 (B),
2131the timing matches up "perfectly" so no extra ending char is detected.
2132The RXD pin is 1 in the last interrupt, in that case
2133we set info->errorcode = ERRCODE_INSERT_BREAK, but we can't really
2134know if another byte will come and this really is case 2. below
2135(e.g F=0xFF or 0xFE)
2136If RXD pin is 0 we can expect another character (see 2. below).
2137
2138
21392.
2140
2141 B B E or F__________________..__ V
2142.._|__________|__________|______ | |valid data
2143 "valid" or
2144 parity error
2145
2146Multiple frame errors with data == 0x00 (B),
2147but the part of the break trigs is interpreted as a start bit (and possibly
2148some 0 bits followed by a number of 1 bits and a stop bit).
2149Depending on parity settings etc. this last character can be either
2150a fake "valid" char (F) or have a parity error (E).
2151
2152If the character is valid it will be put in the buffer,
2153we set info->errorcode = ERRCODE_SET_BREAK so the receive interrupt
2154will set the flags so the tty will handle it,
2155if it's an error byte it will not be put in the buffer
2156and we set info->errorcode = ERRCODE_INSERT_BREAK.
2157
2158To distinguish a V byte in 1. from an F byte in 2. we keep a timestamp
2159of the last faulty char (B) and compares it with the current time:
2160If the time elapsed time is less then 2*char_time_usec we will assume
2161it's a faked F char and not a Valid char and set
2162info->errorcode = ERRCODE_SET_BREAK.
2163
2164Flaws in the above solution:
2165~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2166We use the timer to distinguish a F character from a V character,
2167if a V character is to close after the break we might make the wrong decision.
2168
2169TODO: The break will be delayed until an F or V character is received.
2170
2171*/
2172
12aad550 2173static void handle_ser_rx_interrupt_no_dma(struct e100_serial *info)
1da177e4
LT		 2174{
2175 unsigned long data_read;
77accbf5 2176
1da177e4 2177 /* Read data and status at the same time */
d7283353 2178 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
1da177e4
LT		 2179more_data:
2180 if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {
2181 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2182 }
2183 DINTR2(DEBUG_LOG(info->line, "ser_rx %c\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read)));
2184
2185 if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |
2186 IO_MASK(R_SERIAL0_READ, par_err) |
2187 IO_MASK(R_SERIAL0_READ, overrun) )) {
2188 /* An error */
2189 info->last_rx_active_usec = GET_JIFFIES_USEC();
2190 info->last_rx_active = jiffies;
2191 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat_data %04X\n", data_read));
2192 DLOG_INT_TRIG(
2193 if (!log_int_trig1_pos) {
2194 log_int_trig1_pos = log_int_pos;
2195 log_int(rdpc(), 0, 0);
2196 }
2197 );
2198
2199
2200 if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&
2201 (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {
2202 /* Most likely a break, but we get interrupts over and
2203 * over again.
2204 */
2205
2206 if (!info->break_detected_cnt) {
2207 DEBUG_LOG(info->line, "#BRK start\n", 0);
2208 }
2209 if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {
2210 /* The RX pin is high now, so the break
2211 * must be over, but....
2212 * we can't really know if we will get another
2213 * last byte ending the break or not.
2214 * And we don't know if the byte (if any) will
2215 * have an error or look valid.
2216 */
2217 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2218 info->errorcode = ERRCODE_INSERT_BREAK;
2219 }
2220 info->break_detected_cnt++;
2221 } else {
2222 /* The error does not look like a break, but could be
2223 * the end of one
2224 */
2225 if (info->break_detected_cnt) {
2226 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2227 info->errorcode = ERRCODE_INSERT_BREAK;
2228 } else {
77accbf5
JN		 2229 unsigned char data = IO_EXTRACT(R_SERIAL0_READ,
2230 data_in, data_read);
2231 char flag = TTY_NORMAL;
1da177e4 2232 if (info->errorcode == ERRCODE_INSERT_BREAK) {
92a19f9c 2233 tty_insert_flip_char(&info->port, 0, flag);
1da177e4
LT		 2234 info->icount.rx++;
2235 }
1da177e4
LT		 2236
2237 if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {
2238 info->icount.parity++;
77accbf5 2239 flag = TTY_PARITY;
1da177e4
LT		 2240 } else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {
2241 info->icount.overrun++;
77accbf5 2242 flag = TTY_OVERRUN;
1da177e4
LT		 2243 } else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {
2244 info->icount.frame++;
77accbf5 2245 flag = TTY_FRAME;
1da177e4 2246 }
92a19f9c 2247 tty_insert_flip_char(&info->port, data, flag);
1da177e4
LT		 2248 info->errorcode = 0;
2249 }
2250 info->break_detected_cnt = 0;
2251 }
2252 } else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2253 /* No error */
2254 DLOG_INT_TRIG(
2255 if (!log_int_trig1_pos) {
2256 if (log_int_pos >= log_int_size) {
2257 log_int_pos = 0;
2258 }
2259 log_int_trig0_pos = log_int_pos;
2260 log_int(rdpc(), 0, 0);
2261 }
2262 );
92a19f9c 2263 tty_insert_flip_char(&info->port,
77accbf5
JN		 2264 IO_EXTRACT(R_SERIAL0_READ, data_in, data_read),
2265 TTY_NORMAL);
1da177e4
LT		 2266 } else {
2267 DEBUG_LOG(info->line, "ser_rx int but no data_avail %08lX\n", data_read);
2268 }
2269
2270
1da177e4 2271 info->icount.rx++;
d7283353 2272 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
1da177e4
LT		 2273 if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2274 DEBUG_LOG(info->line, "ser_rx %c in loop\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read));
2275 goto more_data;
2276 }
2277
2e124b4a 2278 tty_flip_buffer_push(&info->port);
1da177e4
LT		 2279}
2280
12aad550 2281static void handle_ser_rx_interrupt(struct e100_serial *info)
1da177e4
LT		 2282{
2283 unsigned char rstat;
2284
2285#ifdef SERIAL_DEBUG_INTR
2286 printk("Interrupt from serport %d\n", i);
2287#endif
2288/* DEBUG_LOG(info->line, "ser_interrupt stat %03X\n", rstat | (i << 8)); */
2289 if (!info->uses_dma_in) {
12aad550
JS		 2290 handle_ser_rx_interrupt_no_dma(info);
2291 return;
1da177e4
LT		 2292 }
2293 /* DMA is used */
d7283353 2294 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 2295 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
2296 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2297 }
2298
2299 if (rstat & SER_ERROR_MASK) {
2300 unsigned char data;
2301
2302 info->last_rx_active_usec = GET_JIFFIES_USEC();
2303 info->last_rx_active = jiffies;
2304 /* If we got an error, we must reset it by reading the
2305 * data_in field
2306 */
d7283353 2307 data = info->ioport[REG_DATA];
1da177e4
LT		 2308 DINTR1(DEBUG_LOG(info->line, "ser_rx! %c\n", data));
2309 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat %02X\n", rstat));
2310 if (!data && (rstat & SER_FRAMING_ERR_MASK)) {
2311 /* Most likely a break, but we get interrupts over and
2312 * over again.
2313 */
2314
2315 if (!info->break_detected_cnt) {
2316 DEBUG_LOG(info->line, "#BRK start\n", 0);
2317 }
2318 if (rstat & SER_RXD_MASK) {
2319 /* The RX pin is high now, so the break
2320 * must be over, but....
2321 * we can't really know if we will get another
2322 * last byte ending the break or not.
2323 * And we don't know if the byte (if any) will
2324 * have an error or look valid.
2325 */
2326 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2327 info->errorcode = ERRCODE_INSERT_BREAK;
2328 }
2329 info->break_detected_cnt++;
2330 } else {
2331 /* The error does not look like a break, but could be
2332 * the end of one
2333 */
2334 if (info->break_detected_cnt) {
2335 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2336 info->errorcode = ERRCODE_INSERT_BREAK;
2337 } else {
2338 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2339 info->icount.brk++;
2340 add_char_and_flag(info, '\0', TTY_BREAK);
2341 }
2342
2343 if (rstat & SER_PAR_ERR_MASK) {
2344 info->icount.parity++;
2345 add_char_and_flag(info, data, TTY_PARITY);
2346 } else if (rstat & SER_OVERRUN_MASK) {
2347 info->icount.overrun++;
2348 add_char_and_flag(info, data, TTY_OVERRUN);
2349 } else if (rstat & SER_FRAMING_ERR_MASK) {
2350 info->icount.frame++;
2351 add_char_and_flag(info, data, TTY_FRAME);
2352 }
2353
2354 info->errorcode = 0;
2355 }
2356 info->break_detected_cnt = 0;
2357 DEBUG_LOG(info->line, "#iERR s d %04X\n",
2358 ((rstat & SER_ERROR_MASK) << 8) | data);
2359 }
2360 PROCSTAT(ser_stat[info->line].early_errors_cnt++);
2361 } else { /* It was a valid byte, now let the DMA do the rest */
2362 unsigned long curr_time_u = GET_JIFFIES_USEC();
2363 unsigned long curr_time = jiffies;
2364
2365 if (info->break_detected_cnt) {
2366 /* Detect if this character is a new valid char or the
2367 * last char in a break sequence: If LSBits are 0 and
2368 * MSBits are high AND the time is close to the
2369 * previous interrupt we should discard it.
2370 */
2371 long elapsed_usec =
2372 (curr_time - info->last_rx_active) * (1000000/HZ) +
2373 curr_time_u - info->last_rx_active_usec;
2374 if (elapsed_usec < 2*info->char_time_usec) {
2375 DEBUG_LOG(info->line, "FBRK %i\n", info->line);
2376 /* Report as BREAK (error) and let
2377 * receive_chars_dma() handle it
2378 */
2379 info->errorcode = ERRCODE_SET_BREAK;
2380 } else {
2381 DEBUG_LOG(info->line, "Not end of BRK (V)%i\n", info->line);
2382 }
2383 DEBUG_LOG(info->line, "num brk %i\n", info->break_detected_cnt);
2384 }
2385
2386#ifdef SERIAL_DEBUG_INTR
2387 printk("** OK, disabling ser_interrupts\n");
2388#endif
2389 e100_disable_serial_data_irq(info);
2390 DINTR2(DEBUG_LOG(info->line, "ser_rx OK %d\n", info->line));
2391 info->break_detected_cnt = 0;
2392
2393 PROCSTAT(ser_stat[info->line].ser_ints_ok_cnt++);
2394 }
2395 /* Restarting the DMA never hurts */
2396 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
2397 START_FLUSH_FAST_TIMER(info, "ser_int");
1da177e4
LT		 2398} /* handle_ser_rx_interrupt */
2399
41c28ff1 2400static void handle_ser_tx_interrupt(struct e100_serial *info)
1da177e4
LT		 2401{
2402 unsigned long flags;
2403
2404 if (info->x_char) {
2405 unsigned char rstat;
2406 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar 0x%02X\n", info->x_char));
77accbf5 2407 local_irq_save(flags);
d7283353 2408 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 2409 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2410
d7283353 2411 info->ioport[REG_TR_DATA] = info->x_char;
1da177e4
LT		 2412 info->icount.tx++;
2413 info->x_char = 0;
2414 /* We must enable since it is disabled in ser_interrupt */
2415 e100_enable_serial_tx_ready_irq(info);
77accbf5 2416 local_irq_restore(flags);
1da177e4
LT		 2417 return;
2418 }
2419 if (info->uses_dma_out) {
2420 unsigned char rstat;
2421 int i;
2422 /* We only use normal tx interrupt when sending x_char */
2423 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar sent\n", 0));
77accbf5 2424 local_irq_save(flags);
d7283353 2425 rstat = info->ioport[REG_STATUS];
1da177e4
LT		 2426 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2427 e100_disable_serial_tx_ready_irq(info);
a88487c7
TI		 2428 if (info->port.tty->stopped)
2429 rs_stop(info->port.tty);
1da177e4
LT		 2430 /* Enable the DMA channel and tell it to continue */
2431 e100_enable_txdma_channel(info);
2432 /* Wait 12 cycles before doing the DMA command */
2433 for(i = 6; i > 0; i--)
2434 nop();
2435
2436 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, continue);
77accbf5 2437 local_irq_restore(flags);
1da177e4
LT		 2438 return;
2439 }
2440 /* Normal char-by-char interrupt */
2441 if (info->xmit.head == info->xmit.tail
ee797069 2442 || info->port.tty->stopped) {
a88487c7
TI		 2443 DFLOW(DEBUG_LOG(info->line, "tx_int: stopped %i\n",
2444 info->port.tty->stopped));
1da177e4
LT		 2445 e100_disable_serial_tx_ready_irq(info);
2446 info->tr_running = 0;
2447 return;
2448 }
2449 DINTR2(DEBUG_LOG(info->line, "tx_int %c\n", info->xmit.buf[info->xmit.tail]));
2450 /* Send a byte, rs485 timing is critical so turn of ints */
77accbf5 2451 local_irq_save(flags);
d7283353 2452 info->ioport[REG_TR_DATA] = info->xmit.buf[info->xmit.tail];
1da177e4
LT		 2453 info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1);
2454 info->icount.tx++;
2455 if (info->xmit.head == info->xmit.tail) {
2456#if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
6fd1af4c 2457 if (info->rs485.flags & SER_RS485_ENABLED) {
1da177e4
LT		 2458 /* Set a short timer to toggle RTS */
2459 start_one_shot_timer(&fast_timers_rs485[info->line],
2460 rs485_toggle_rts_timer_function,
2461 (unsigned long)info,
2462 info->char_time_usec*2,
2463 "RS-485");
2464 }
2465#endif /* RS485 */
2466 info->last_tx_active_usec = GET_JIFFIES_USEC();
2467 info->last_tx_active = jiffies;
2468 e100_disable_serial_tx_ready_irq(info);
2469 info->tr_running = 0;
2470 DFLOW(DEBUG_LOG(info->line, "tx_int: stop2\n", 0));
2471 } else {
2472 /* We must enable since it is disabled in ser_interrupt */
2473 e100_enable_serial_tx_ready_irq(info);
2474 }
77accbf5 2475 local_irq_restore(flags);
1da177e4
LT		 2476
2477 if (CIRC_CNT(info->xmit.head,
2478 info->xmit.tail,
2479 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
2480 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
2481
2482} /* handle_ser_tx_interrupt */
2483
2484/* result of time measurements:
2485 * RX duration 54-60 us when doing something, otherwise 6-9 us
2486 * ser_int duration: just sending: 8-15 us normally, up to 73 us
2487 */
2488static irqreturn_t
7d12e780 2489ser_interrupt(int irq, void *dev_id)
1da177e4
LT		 2490{
2491 static volatile int tx_started = 0;
2492 struct e100_serial *info;
2493 int i;
2494 unsigned long flags;
2495 unsigned long irq_mask1_rd;
2496 unsigned long data_mask = (1 << (8+2*0)); /* ser0 data_avail */
2497 int handled = 0;
2498 static volatile unsigned long reentered_ready_mask = 0;
2499
77accbf5 2500 local_irq_save(flags);
1da177e4
LT		 2501 irq_mask1_rd = *R_IRQ_MASK1_RD;
2502 /* First handle all rx interrupts with ints disabled */
2503 info = rs_table;
2504 irq_mask1_rd &= e100_ser_int_mask;
2505 for (i = 0; i < NR_PORTS; i++) {
2506 /* Which line caused the data irq? */
2507 if (irq_mask1_rd & data_mask) {
2508 handled = 1;
2509 handle_ser_rx_interrupt(info);
2510 }
2511 info += 1;
2512 data_mask <<= 2;
2513 }
2514 /* Handle tx interrupts with interrupts enabled so we
2515 * can take care of new data interrupts while transmitting
2516 * We protect the tx part with the tx_started flag.
2517 * We disable the tr_ready interrupts we are about to handle and
2518 * unblock the serial interrupt so new serial interrupts may come.
2519 *
2520 * If we get a new interrupt:
2521 * - it migth be due to synchronous serial ports.
2522 * - serial irq will be blocked by general irq handler.
2523 * - async data will be handled above (sync will be ignored).
2524 * - tx_started flag will prevent us from trying to send again and
2525 * we will exit fast - no need to unblock serial irq.
2526 * - Next (sync) serial interrupt handler will be runned with
2527 * disabled interrupt due to restore_flags() at end of function,
2528 * so sync handler will not be preempted or reentered.
2529 */
2530 if (!tx_started) {
2531 unsigned long ready_mask;
2532 unsigned long
2533 tx_started = 1;
2534 /* Only the tr_ready interrupts left */
2535 irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2536 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2537 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2538 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2539 while (irq_mask1_rd) {
2540 /* Disable those we are about to handle */
2541 *R_IRQ_MASK1_CLR = irq_mask1_rd;
2542 /* Unblock the serial interrupt */
2543 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
2544
77accbf5 2545 local_irq_enable();
1da177e4
LT		 2546 ready_mask = (1 << (8+1+2*0)); /* ser0 tr_ready */
2547 info = rs_table;
2548 for (i = 0; i < NR_PORTS; i++) {
2549 /* Which line caused the ready irq? */
2550 if (irq_mask1_rd & ready_mask) {
2551 handled = 1;
2552 handle_ser_tx_interrupt(info);
2553 }
2554 info += 1;
2555 ready_mask <<= 2;
2556 }
2557 /* handle_ser_tx_interrupt enables tr_ready interrupts */
77accbf5 2558 local_irq_disable();
1da177e4
LT		 2559 /* Handle reentered TX interrupt */
2560 irq_mask1_rd = reentered_ready_mask;
2561 }
77accbf5 2562 local_irq_disable();
1da177e4
LT		 2563 tx_started = 0;
2564 } else {
2565 unsigned long ready_mask;
2566 ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2567 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2568 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2569 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2570 if (ready_mask) {
2571 reentered_ready_mask |= ready_mask;
2572 /* Disable those we are about to handle */
2573 *R_IRQ_MASK1_CLR = ready_mask;
2574 DFLOW(DEBUG_LOG(SERIAL_DEBUG_LINE, "ser_int reentered with TX %X\n", ready_mask));
2575 }
2576 }
2577
77accbf5 2578 local_irq_restore(flags);
1da177e4
LT		 2579 return IRQ_RETVAL(handled);
2580} /* ser_interrupt */
2581#endif
2582
2583/*
2584 * -------------------------------------------------------------------
2585 * Here ends the serial interrupt routines.
2586 * -------------------------------------------------------------------
2587 */
2588
2589/*
2590 * This routine is used to handle the "bottom half" processing for the
2591 * serial driver, known also the "software interrupt" processing.
2592 * This processing is done at the kernel interrupt level, after the
2593 * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
2594 * is where time-consuming activities which can not be done in the
2595 * interrupt driver proper are done; the interrupt driver schedules
2596 * them using rs_sched_event(), and they get done here.
2597 */
2598static void
77accbf5 2599do_softint(struct work_struct *work)
1da177e4 2600{
77accbf5 2601 struct e100_serial *info;
1da177e4
LT		 2602 struct tty_struct *tty;
2603
77accbf5
JN		 2604 info = container_of(work, struct e100_serial, work);
2605
a88487c7 2606 tty = info->port.tty;
1da177e4
LT		 2607 if (!tty)
2608 return;
2609
b963a844
JS		 2610 if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event))
2611 tty_wakeup(tty);
1da177e4
LT		 2612}
2613
2614static int
2615startup(struct e100_serial * info)
2616{
2617 unsigned long flags;
2618 unsigned long xmit_page;
2619 int i;
2620
2621 xmit_page = get_zeroed_page(GFP_KERNEL);
2622 if (!xmit_page)
2623 return -ENOMEM;
2624
77accbf5 2625 local_irq_save(flags);
1da177e4
LT		 2626
2627 /* if it was already initialized, skip this */
2628
b1d984cf 2629 if (info->port.flags & ASYNC_INITIALIZED) {
77accbf5 2630 local_irq_restore(flags);
1da177e4
LT		 2631 free_page(xmit_page);
2632 return 0;
2633 }
2634
2635 if (info->xmit.buf)
2636 free_page(xmit_page);
2637 else
2638 info->xmit.buf = (unsigned char *) xmit_page;
2639
2640#ifdef SERIAL_DEBUG_OPEN
2641 printk("starting up ttyS%d (xmit_buf 0x%p)...\n", info->line, info->xmit.buf);
2642#endif
2643
1da177e4
LT		 2644 /*
2645 * Clear the FIFO buffers and disable them
2646 * (they will be reenabled in change_speed())
2647 */
2648
2649 /*
2650 * Reset the DMA channels and make sure their interrupts are cleared
2651 */
2652
2653 if (info->dma_in_enabled) {
2654 info->uses_dma_in = 1;
2655 e100_enable_rxdma_channel(info);
2656
2657 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2658
2659 /* Wait until reset cycle is complete */
2660 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
2661 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2662
2663 /* Make sure the irqs are cleared */
2664 *info->iclrintradr =
2665 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2666 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2667 } else {
2668 e100_disable_rxdma_channel(info);
2669 }
2670
2671 if (info->dma_out_enabled) {
2672 info->uses_dma_out = 1;
2673 e100_enable_txdma_channel(info);
2674 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2675
2676 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) ==
2677 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2678
2679 /* Make sure the irqs are cleared */
2680 *info->oclrintradr =
2681 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2682 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2683 } else {
2684 e100_disable_txdma_channel(info);
2685 }
2686
a88487c7
TI		 2687 if (info->port.tty)
2688 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4
LT		 2689
2690 info->xmit.head = info->xmit.tail = 0;
2691 info->first_recv_buffer = info->last_recv_buffer = NULL;
2692 info->recv_cnt = info->max_recv_cnt = 0;
2693
2694 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2695 info->rec_descr[i].buf = 0;
2696
2697 /*
2698 * and set the speed and other flags of the serial port
2699 * this will start the rx/tx as well
2700 */
2701#ifdef SERIAL_HANDLE_EARLY_ERRORS
2702 e100_enable_serial_data_irq(info);
2703#endif
2704 change_speed(info);
2705
2706 /* dummy read to reset any serial errors */
2707
d7283353 2708 (void)info->ioport[REG_DATA];
1da177e4
LT		 2709
2710 /* enable the interrupts */
2711 if (info->uses_dma_out)
2712 e100_enable_txdma_irq(info);
2713
2714 e100_enable_rx_irq(info);
2715
2716 info->tr_running = 0; /* to be sure we don't lock up the transmitter */
2717
2718 /* setup the dma input descriptor and start dma */
2719
2720 start_receive(info);
2721
2722 /* for safety, make sure the descriptors last result is 0 bytes written */
2723
2724 info->tr_descr.sw_len = 0;
2725 info->tr_descr.hw_len = 0;
2726 info->tr_descr.status = 0;
2727
2728 /* enable RTS/DTR last */
2729
2730 e100_rts(info, 1);
2731 e100_dtr(info, 1);
2732
b1d984cf 2733 info->port.flags |= ASYNC_INITIALIZED;
1da177e4 2734
77accbf5 2735 local_irq_restore(flags);
1da177e4
LT		 2736 return 0;
2737}
2738
2739/*
2740 * This routine will shutdown a serial port; interrupts are disabled, and
2741 * DTR is dropped if the hangup on close termio flag is on.
2742 */
2743static void
2744shutdown(struct e100_serial * info)
2745{
2746 unsigned long flags;
2747 struct etrax_dma_descr *descr = info->rec_descr;
2748 struct etrax_recv_buffer *buffer;
2749 int i;
2750
1da177e4
LT		 2751 /* shut down the transmitter and receiver */
2752 DFLOW(DEBUG_LOG(info->line, "shutdown %i\n", info->line));
2753 e100_disable_rx(info);
d7283353 2754 info->ioport[REG_TR_CTRL] = (info->tx_ctrl &= ~0x40);
1da177e4
LT		 2755
2756 /* disable interrupts, reset dma channels */
2757 if (info->uses_dma_in) {
2758 e100_disable_rxdma_irq(info);
2759 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2760 info->uses_dma_in = 0;
2761 } else {
2762 e100_disable_serial_data_irq(info);
2763 }
2764
2765 if (info->uses_dma_out) {
2766 e100_disable_txdma_irq(info);
2767 info->tr_running = 0;
2768 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2769 info->uses_dma_out = 0;
2770 } else {
2771 e100_disable_serial_tx_ready_irq(info);
2772 info->tr_running = 0;
2773 }
2774
b1d984cf 2775 if (!(info->port.flags & ASYNC_INITIALIZED))
1da177e4
LT		 2776 return;
2777
2778#ifdef SERIAL_DEBUG_OPEN
2779 printk("Shutting down serial port %d (irq %d)....\n", info->line,
2780 info->irq);
2781#endif
2782
77accbf5 2783 local_irq_save(flags);
1da177e4
LT		 2784
2785 if (info->xmit.buf) {
2786 free_page((unsigned long)info->xmit.buf);
2787 info->xmit.buf = NULL;
2788 }
2789
2790 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2791 if (descr[i].buf) {
2792 buffer = phys_to_virt(descr[i].buf) - sizeof *buffer;
2793 kfree(buffer);
2794 descr[i].buf = 0;
2795 }
2796
adc8d746 2797 if (!info->port.tty || (info->port.tty->termios.c_cflag & HUPCL)) {
1da177e4
LT		 2798 /* hang up DTR and RTS if HUPCL is enabled */
2799 e100_dtr(info, 0);
2800 e100_rts(info, 0); /* could check CRTSCTS before doing this */
2801 }
2802
a88487c7
TI		 2803 if (info->port.tty)
2804 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
1da177e4 2805
b1d984cf 2806 info->port.flags &= ~ASYNC_INITIALIZED;
77accbf5 2807 local_irq_restore(flags);
1da177e4
LT		 2808}
2809
2810
2811/* change baud rate and other assorted parameters */
2812
2813static void
2814change_speed(struct e100_serial *info)
2815{
2816 unsigned int cflag;
2817 unsigned long xoff;
2818 unsigned long flags;
2819 /* first some safety checks */
2820
adc8d746 2821 if (!info->port.tty)
1da177e4 2822 return;
d7283353 2823 if (!info->ioport)
1da177e4
LT		 2824 return;
2825
adc8d746 2826 cflag = info->port.tty->termios.c_cflag;
1da177e4
LT		 2827
2828 /* possibly, the tx/rx should be disabled first to do this safely */
2829
2830 /* change baud-rate and write it to the hardware */
b1d984cf 2831 if ((info->port.flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST) {
1da177e4
LT		 2832 /* Special baudrate */
2833 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2834 unsigned long alt_source =
2835 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2836 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2837 /* R_ALT_SER_BAUDRATE selects the source */
2838 DBAUD(printk("Custom baudrate: baud_base/divisor %lu/%i\n",
2839 (unsigned long)info->baud_base, info->custom_divisor));
2840 if (info->baud_base == SERIAL_PRESCALE_BASE) {
2841 /* 0, 2-65535 (0=65536) */
2842 u16 divisor = info->custom_divisor;
2843 /* R_SERIAL_PRESCALE (upper 16 bits of R_CLOCK_PRESCALE) */
2844 /* baudrate is 3.125MHz/custom_divisor */
2845 alt_source =
2846 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, prescale) |
2847 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, prescale);
2848 alt_source = 0x11;
2849 DBAUD(printk("Writing SERIAL_PRESCALE: divisor %i\n", divisor));
2850 *R_SERIAL_PRESCALE = divisor;
2851 info->baud = SERIAL_PRESCALE_BASE/divisor;
2852 }
1da177e4
LT		 2853 else
2854 {
2855 /* Bad baudbase, we don't support using timer0
2856 * for baudrate.
2857 */
2858 printk(KERN_WARNING "Bad baud_base/custom_divisor: %lu/%i\n",
2859 (unsigned long)info->baud_base, info->custom_divisor);
2860 }
2861 r_alt_ser_baudrate_shadow &= ~mask;
2862 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
2863 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
2864 } else {
2865 /* Normal baudrate */
2866 /* Make sure we use normal baudrate */
2867 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2868 unsigned long alt_source =
2869 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2870 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2871 r_alt_ser_baudrate_shadow &= ~mask;
2872 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
1da177e4 2873 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
1da177e4
LT		 2874
2875 info->baud = cflag_to_baud(cflag);
d7283353 2876 info->ioport[REG_BAUD] = cflag_to_etrax_baud(cflag);
1da177e4
LT		 2877 }
2878
1da177e4 2879 /* start with default settings and then fill in changes */
77accbf5 2880 local_irq_save(flags);
1da177e4
LT		 2881 /* 8 bit, no/even parity */
2882 info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |
2883 IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |
2884 IO_MASK(R_SERIAL0_REC_CTRL, rec_par));
2885
2886 /* 8 bit, no/even parity, 1 stop bit, no cts */
2887 info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |
2888 IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |
2889 IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |
2890 IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |
2891 IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));
2892
2893 if ((cflag & CSIZE) == CS7) {
2894 /* set 7 bit mode */
2895 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit);
2896 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit);
2897 }
2898
2899 if (cflag & CSTOPB) {
2900 /* set 2 stop bit mode */
2901 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits);
2902 }
2903
2904 if (cflag & PARENB) {
2905 /* enable parity */
2906 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
2907 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
2908 }
2909
2910 if (cflag & CMSPAR) {
2911 /* enable stick parity, PARODD mean Mark which matches ETRAX */
2912 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick);
2913 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, stick);
2914 }
2915 if (cflag & PARODD) {
2916 /* set odd parity (or Mark if CMSPAR) */
2917 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd);
2918 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd);
2919 }
2920
2921 if (cflag & CRTSCTS) {
2922 /* enable automatic CTS handling */
2923 DFLOW(DEBUG_LOG(info->line, "FLOW auto_cts enabled\n", 0));
2924 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, active);
2925 }
2926
2927 /* make sure the tx and rx are enabled */
2928
2929 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable);
2930 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
2931
2932 /* actually write the control regs to the hardware */
2933
d7283353
AC		 2934 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
2935 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
a88487c7 2936 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->port.tty));
1da177e4 2937 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
adc8d746 2938 if (info->port.tty->termios.c_iflag & IXON ) {
a88487c7
TI		 2939 DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n",
2940 STOP_CHAR(info->port.tty)));
1da177e4
LT		 2941 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
2942 }
2943
d7283353 2944 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
77accbf5 2945 local_irq_restore(flags);
1da177e4
LT		 2946
2947 update_char_time(info);
2948
2949} /* change_speed */
2950
2951/* start transmitting chars NOW */
2952
2953static void
2954rs_flush_chars(struct tty_struct *tty)
2955{
2956 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
2957 unsigned long flags;
2958
2959 if (info->tr_running ||
2960 info->xmit.head == info->xmit.tail ||
2961 tty->stopped ||
1da177e4
LT		 2962 !info->xmit.buf)
2963 return;
2964
2965#ifdef SERIAL_DEBUG_FLOW
2966 printk("rs_flush_chars\n");
2967#endif
2968
2969 /* this protection might not exactly be necessary here */
2970
77accbf5 2971 local_irq_save(flags);
1da177e4 2972 start_transmit(info);
77accbf5 2973 local_irq_restore(flags);
1da177e4
LT		 2974}
2975
77accbf5 2976static int rs_raw_write(struct tty_struct *tty,
41c28ff1 2977 const unsigned char *buf, int count)
1da177e4
LT		 2978{
2979 int c, ret = 0;
2980 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
2981 unsigned long flags;
2982
2983 /* first some sanity checks */
2984
f938f378 2985 if (!info->xmit.buf)
1da177e4
LT		 2986 return 0;
2987
2988#ifdef SERIAL_DEBUG_DATA
2989 if (info->line == SERIAL_DEBUG_LINE)
2990 printk("rs_raw_write (%d), status %d\n",
d7283353 2991 count, info->ioport[REG_STATUS]);
1da177e4
LT		 2992#endif
2993
77accbf5 2994 local_save_flags(flags);
1da177e4
LT		 2995 DFLOW(DEBUG_LOG(info->line, "write count %i ", count));
2996 DFLOW(DEBUG_LOG(info->line, "ldisc %i\n", tty->ldisc.chars_in_buffer(tty)));
2997
2998
77accbf5
JN		 2999 /* The local_irq_disable/restore_flags pairs below are needed
3000 * because the DMA interrupt handler moves the info->xmit values.
3001 * the memcpy needs to be in the critical region unfortunately,
3002 * because we need to read xmit values, memcpy, write xmit values
3003 * in one atomic operation... this could perhaps be avoided by
3004 * more clever design.
1da177e4 3005 */
77accbf5 3006 local_irq_disable();
1da177e4
LT		 3007 while (count) {
3008 c = CIRC_SPACE_TO_END(info->xmit.head,
3009 info->xmit.tail,
3010 SERIAL_XMIT_SIZE);
3011
3012 if (count < c)
3013 c = count;
3014 if (c <= 0)
3015 break;
3016
3017 memcpy(info->xmit.buf + info->xmit.head, buf, c);
3018 info->xmit.head = (info->xmit.head + c) &
3019 (SERIAL_XMIT_SIZE-1);
3020 buf += c;
3021 count -= c;
3022 ret += c;
3023 }
77accbf5 3024 local_irq_restore(flags);
1da177e4
LT		 3025
3026 /* enable transmitter if not running, unless the tty is stopped
3027 * this does not need IRQ protection since if tr_running == 0
3028 * the IRQ's are not running anyway for this port.
3029 */
3030 DFLOW(DEBUG_LOG(info->line, "write ret %i\n", ret));
3031
3032 if (info->xmit.head != info->xmit.tail &&
3033 !tty->stopped &&
1da177e4
LT		 3034 !info->tr_running) {
3035 start_transmit(info);
3036 }
3037
3038 return ret;
3039} /* raw_raw_write() */
3040
3041static int
77accbf5 3042rs_write(struct tty_struct *tty,
1da177e4
LT		 3043 const unsigned char *buf, int count)
3044{
3045#if defined(CONFIG_ETRAX_RS485)
3046 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3047
6fd1af4c 3048 if (info->rs485.flags & SER_RS485_ENABLED)
1da177e4
LT		 3049 {
3050 /* If we are in RS-485 mode, we need to toggle RTS and disable
3051 * the receiver before initiating a DMA transfer
3052 */
3053#ifdef CONFIG_ETRAX_FAST_TIMER
3054 /* Abort any started timer */
3055 fast_timers_rs485[info->line].function = NULL;
3056 del_fast_timer(&fast_timers_rs485[info->line]);
3057#endif
6fd1af4c 3058 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_ON_SEND));
1da177e4
LT		 3059#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3060 e100_disable_rx(info);
3061 e100_enable_rx_irq(info);
3062#endif
93f3350c
CS		 3063 if (info->rs485.delay_rts_before_send > 0)
3064 msleep(info->rs485.delay_rts_before_send);
1da177e4
LT		 3065 }
3066#endif /* CONFIG_ETRAX_RS485 */
3067
77accbf5 3068 count = rs_raw_write(tty, buf, count);
1da177e4
LT		 3069
3070#if defined(CONFIG_ETRAX_RS485)
6fd1af4c 3071 if (info->rs485.flags & SER_RS485_ENABLED)
1da177e4
LT		 3072 {
3073 unsigned int val;
3074 /* If we are in RS-485 mode the following has to be done:
3075 * wait until DMA is ready
3076 * wait on transmit shift register
3077 * toggle RTS
3078 * enable the receiver
3079 */
3080
3081 /* Sleep until all sent */
3082 tty_wait_until_sent(tty, 0);
3083#ifdef CONFIG_ETRAX_FAST_TIMER
3084 /* Now sleep a little more so that shift register is empty */
3085 schedule_usleep(info->char_time_usec * 2);
3086#endif
3087 /* wait on transmit shift register */
3088 do{
3089 get_lsr_info(info, &val);
3090 }while (!(val & TIOCSER_TEMT));
3091
6fd1af4c 3092 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1da177e4
LT		 3093
3094#if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3095 e100_enable_rx(info);
3096 e100_enable_rxdma_irq(info);
3097#endif
3098 }
3099#endif /* CONFIG_ETRAX_RS485 */
3100
3101 return count;
3102} /* rs_write */
3103
3104
3105/* how much space is available in the xmit buffer? */
3106
3107static int
3108rs_write_room(struct tty_struct *tty)
3109{
3110 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3111
3112 return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3113}
3114
3115/* How many chars are in the xmit buffer?
3116 * This does not include any chars in the transmitter FIFO.
3117 * Use wait_until_sent for waiting for FIFO drain.
3118 */
3119
3120static int
3121rs_chars_in_buffer(struct tty_struct *tty)
3122{
3123 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3124
3125 return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3126}
3127
3128/* discard everything in the xmit buffer */
3129
3130static void
3131rs_flush_buffer(struct tty_struct *tty)
3132{
3133 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3134 unsigned long flags;
3135
77accbf5 3136 local_irq_save(flags);
1da177e4 3137 info->xmit.head = info->xmit.tail = 0;
77accbf5 3138 local_irq_restore(flags);
1da177e4 3139
b963a844 3140 tty_wakeup(tty);
1da177e4
LT		 3141}
3142
3143/*
3144 * This function is used to send a high-priority XON/XOFF character to
3145 * the device
3146 *
3147 * Since we use DMA we don't check for info->x_char in transmit_chars_dma(),
3148 * but we do it in handle_ser_tx_interrupt().
3149 * We disable DMA channel and enable tx ready interrupt and write the
3150 * character when possible.
3151 */
3152static void rs_send_xchar(struct tty_struct *tty, char ch)
3153{
3154 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3155 unsigned long flags;
77accbf5 3156 local_irq_save(flags);
1da177e4
LT		 3157 if (info->uses_dma_out) {
3158 /* Put the DMA on hold and disable the channel */
3159 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, hold);
3160 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) !=
3161 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, hold));
3162 e100_disable_txdma_channel(info);
3163 }
3164
3165 /* Must make sure transmitter is not stopped before we can transmit */
3166 if (tty->stopped)
3167 rs_start(tty);
3168
3169 /* Enable manual transmit interrupt and send from there */
3170 DFLOW(DEBUG_LOG(info->line, "rs_send_xchar 0x%02X\n", ch));
3171 info->x_char = ch;
3172 e100_enable_serial_tx_ready_irq(info);
77accbf5 3173 local_irq_restore(flags);
1da177e4
LT		 3174}
3175
3176/*
3177 * ------------------------------------------------------------
3178 * rs_throttle()
3179 *
3180 * This routine is called by the upper-layer tty layer to signal that
3181 * incoming characters should be throttled.
3182 * ------------------------------------------------------------
3183 */
3184static void
3185rs_throttle(struct tty_struct * tty)
3186{
3187 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3188#ifdef SERIAL_DEBUG_THROTTLE
429b4749 3189 printk("throttle %s: %lu....\n", tty_name(tty),
1da177e4
LT		 3190 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3191#endif
3192 DFLOW(DEBUG_LOG(info->line,"rs_throttle %lu\n", tty->ldisc.chars_in_buffer(tty)));
3193
3194 /* Do RTS before XOFF since XOFF might take some time */
adc8d746 3195 if (tty->termios.c_cflag & CRTSCTS) {
1da177e4
LT		 3196 /* Turn off RTS line */
3197 e100_rts(info, 0);
3198 }
3199 if (I_IXOFF(tty))
3200 rs_send_xchar(tty, STOP_CHAR(tty));
3201
3202}
3203
3204static void
3205rs_unthrottle(struct tty_struct * tty)
3206{
3207 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3208#ifdef SERIAL_DEBUG_THROTTLE
429b4749 3209 printk("unthrottle %s: %lu....\n", tty_name(tty),
1da177e4
LT		 3210 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3211#endif
3212 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc %d\n", tty->ldisc.chars_in_buffer(tty)));
3213 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count));
3214 /* Do RTS before XOFF since XOFF might take some time */
adc8d746 3215 if (tty->termios.c_cflag & CRTSCTS) {
1da177e4
LT		 3216 /* Assert RTS line */
3217 e100_rts(info, 1);
3218 }
3219
3220 if (I_IXOFF(tty)) {
3221 if (info->x_char)
3222 info->x_char = 0;
3223 else
3224 rs_send_xchar(tty, START_CHAR(tty));
3225 }
3226
3227}
3228
3229/*
3230 * ------------------------------------------------------------
3231 * rs_ioctl() and friends
3232 * ------------------------------------------------------------
3233 */
3234
3235static int
3236get_serial_info(struct e100_serial * info,
3237 struct serial_struct * retinfo)
3238{
3239 struct serial_struct tmp;
3240
3241 /* this is all probably wrong, there are a lot of fields
3242 * here that we don't have in e100_serial and maybe we
3243 * should set them to something else than 0.
3244 */
3245
3246 if (!retinfo)
3247 return -EFAULT;
3248 memset(&tmp, 0, sizeof(tmp));
3249 tmp.type = info->type;
3250 tmp.line = info->line;
d7283353 3251 tmp.port = (int)info->ioport;
1da177e4 3252 tmp.irq = info->irq;
b1d984cf 3253 tmp.flags = info->port.flags;
1da177e4 3254 tmp.baud_base = info->baud_base;
892c7cfc
JS		 3255 tmp.close_delay = info->port.close_delay;
3256 tmp.closing_wait = info->port.closing_wait;
1da177e4
LT		 3257 tmp.custom_divisor = info->custom_divisor;
3258 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
3259 return -EFAULT;
3260 return 0;
3261}
3262
3263static int
3264set_serial_info(struct e100_serial *info,
3265 struct serial_struct *new_info)
3266{
3267 struct serial_struct new_serial;
3268 struct e100_serial old_info;
3269 int retval = 0;
3270
3271 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
3272 return -EFAULT;
3273
3274 old_info = *info;
3275
3276 if (!capable(CAP_SYS_ADMIN)) {
3277 if ((new_serial.type != info->type) ||
892c7cfc 3278 (new_serial.close_delay != info->port.close_delay) ||
1da177e4 3279 ((new_serial.flags & ~ASYNC_USR_MASK) !=
b1d984cf 3280 (info->port.flags & ~ASYNC_USR_MASK)))
1da177e4 3281 return -EPERM;
b1d984cf 3282 info->port.flags = ((info->port.flags & ~ASYNC_USR_MASK) |
1da177e4
LT		 3283 (new_serial.flags & ASYNC_USR_MASK));
3284 goto check_and_exit;
3285 }
3286
b12d8dc2 3287 if (info->port.count > 1)
1da177e4
LT		 3288 return -EBUSY;
3289
3290 /*
3291 * OK, past this point, all the error checking has been done.
3292 * At this point, we start making changes.....
3293 */
3294
3295 info->baud_base = new_serial.baud_base;
b1d984cf 3296 info->port.flags = ((info->port.flags & ~ASYNC_FLAGS) |
1da177e4
LT		 3297 (new_serial.flags & ASYNC_FLAGS));
3298 info->custom_divisor = new_serial.custom_divisor;
3299 info->type = new_serial.type;
892c7cfc
JS		 3300 info->port.close_delay = new_serial.close_delay;
3301 info->port.closing_wait = new_serial.closing_wait;
b1d984cf 3302 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
1da177e4
LT		 3303
3304 check_and_exit:
b1d984cf 3305 if (info->port.flags & ASYNC_INITIALIZED) {
1da177e4
LT		 3306 change_speed(info);
3307 } else
3308 retval = startup(info);
3309 return retval;
3310}
3311
3312/*
3313 * get_lsr_info - get line status register info
3314 *
3315 * Purpose: Let user call ioctl() to get info when the UART physically
3316 * is emptied. On bus types like RS485, the transmitter must
3317 * release the bus after transmitting. This must be done when
3318 * the transmit shift register is empty, not be done when the
3319 * transmit holding register is empty. This functionality
3320 * allows an RS485 driver to be written in user space.
3321 */
3322static int
3323get_lsr_info(struct e100_serial * info, unsigned int *value)
3324{
3325 unsigned int result = TIOCSER_TEMT;
1da177e4
LT		 3326 unsigned long curr_time = jiffies;
3327 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3328 unsigned long elapsed_usec =
3329 (curr_time - info->last_tx_active) * 1000000/HZ +
3330 curr_time_usec - info->last_tx_active_usec;
3331
3332 if (info->xmit.head != info->xmit.tail ||
3333 elapsed_usec < 2*info->char_time_usec) {
3334 result = 0;
3335 }
1da177e4
LT		 3336
3337 if (copy_to_user(value, &result, sizeof(int)))
3338 return -EFAULT;
3339 return 0;
3340}
3341
3342#ifdef SERIAL_DEBUG_IO
3343struct state_str
3344{
3345 int state;
3346 const char *str;
3347};
3348
3349const struct state_str control_state_str[] = {
3350 {TIOCM_DTR, "DTR" },
3351 {TIOCM_RTS, "RTS"},
3352 {TIOCM_ST, "ST?" },
3353 {TIOCM_SR, "SR?" },
3354 {TIOCM_CTS, "CTS" },
3355 {TIOCM_CD, "CD" },
3356 {TIOCM_RI, "RI" },
3357 {TIOCM_DSR, "DSR" },
3358 {0, NULL }
3359};
3360
3361char *get_control_state_str(int MLines, char *s)
3362{
3363 int i = 0;
3364
3365 s[0]='\0';
3366 while (control_state_str[i].str != NULL) {
3367 if (MLines & control_state_str[i].state) {
3368 if (s[0] != '\0') {
3369 strcat(s, ", ");
3370 }
3371 strcat(s, control_state_str[i].str);
3372 }
3373 i++;
3374 }
3375 return s;
3376}
3377#endif
3378
d7283353 3379static int
77accbf5
JN		 3380rs_break(struct tty_struct *tty, int break_state)
3381{
3382 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3383 unsigned long flags;
3384
d7283353
AC		 3385 if (!info->ioport)
3386 return -EIO;
77accbf5
JN		 3387
3388 local_irq_save(flags);
3389 if (break_state == -1) {
3390 /* Go to manual mode and set the txd pin to 0 */
3391 /* Clear bit 7 (txd) and 6 (tr_enable) */
3392 info->tx_ctrl &= 0x3F;
3393 } else {
3394 /* Set bit 7 (txd) and 6 (tr_enable) */
3395 info->tx_ctrl |= (0x80 | 0x40);
3396 }
d7283353 3397 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
77accbf5 3398 local_irq_restore(flags);
d7283353 3399 return 0;
77accbf5
JN		 3400}
3401
1da177e4 3402static int
20b9d177 3403rs_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear)
1da177e4 3404{
77accbf5 3405 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
978e595f 3406 unsigned long flags;
1da177e4 3407
978e595f 3408 local_irq_save(flags);
032c17e8 3409
77accbf5
JN		 3410 if (clear & TIOCM_RTS)
3411 e100_rts(info, 0);
3412 if (clear & TIOCM_DTR)
3413 e100_dtr(info, 0);
3414 /* Handle FEMALE behaviour */
3415 if (clear & TIOCM_RI)
3416 e100_ri_out(info, 0);
3417 if (clear & TIOCM_CD)
3418 e100_cd_out(info, 0);
3419
3420 if (set & TIOCM_RTS)
3421 e100_rts(info, 1);
3422 if (set & TIOCM_DTR)
3423 e100_dtr(info, 1);
3424 /* Handle FEMALE behaviour */
3425 if (set & TIOCM_RI)
3426 e100_ri_out(info, 1);
3427 if (set & TIOCM_CD)
3428 e100_cd_out(info, 1);
032c17e8 3429
978e595f 3430 local_irq_restore(flags);
77accbf5
JN		 3431 return 0;
3432}
3433
3434static int
60b33c13 3435rs_tiocmget(struct tty_struct *tty)
77accbf5
JN		 3436{
3437 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3438 unsigned int result;
978e595f
AC		 3439 unsigned long flags;
3440
3441 local_irq_save(flags);
1da177e4
LT		 3442
3443 result =
3444 (!E100_RTS_GET(info) ? TIOCM_RTS : 0)
3445 | (!E100_DTR_GET(info) ? TIOCM_DTR : 0)
3446 | (!E100_RI_GET(info) ? TIOCM_RNG : 0)
3447 | (!E100_DSR_GET(info) ? TIOCM_DSR : 0)
3448 | (!E100_CD_GET(info) ? TIOCM_CAR : 0)
3449 | (!E100_CTS_GET(info) ? TIOCM_CTS : 0);
3450
978e595f 3451 local_irq_restore(flags);
032c17e8 3452
1da177e4 3453#ifdef SERIAL_DEBUG_IO
77accbf5
JN		 3454 printk(KERN_DEBUG "ser%i: modem state: %i 0x%08X\n",
3455 info->line, result, result);
1da177e4
LT		 3456 {
3457 char s[100];
3458
3459 get_control_state_str(result, s);
77accbf5 3460 printk(KERN_DEBUG "state: %s\n", s);
1da177e4
LT		 3461 }
3462#endif
77accbf5 3463 return result;
1da177e4 3464
1da177e4
LT		 3465}
3466
3467
1da177e4 3468static int
6caa76b7 3469rs_ioctl(struct tty_struct *tty,
1da177e4
LT		 3470 unsigned int cmd, unsigned long arg)
3471{
3472 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3473
3474 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
3475 (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) &&
3476 (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) {
3477 if (tty->flags & (1 << TTY_IO_ERROR))
3478 return -EIO;
3479 }
3480
3481 switch (cmd) {
77accbf5
JN		 3482 case TIOCGSERIAL:
3483 return get_serial_info(info,
3484 (struct serial_struct *) arg);
3485 case TIOCSSERIAL:
3486 return set_serial_info(info,
3487 (struct serial_struct *) arg);
3488 case TIOCSERGETLSR: /* Get line status register */
3489 return get_lsr_info(info, (unsigned int *) arg);
3490
3491 case TIOCSERGSTRUCT:
3492 if (copy_to_user((struct e100_serial *) arg,
3493 info, sizeof(struct e100_serial)))
3494 return -EFAULT;
3495 return 0;
1da177e4
LT		 3496
3497#if defined(CONFIG_ETRAX_RS485)
77accbf5
JN		 3498 case TIOCSERSETRS485:
3499 {
6fd1af4c
CS		 3500 /* In this ioctl we still use the old structure
3501 * rs485_control for backward compatibility
3502 * (if we use serial_rs485, then old user-level code
3503 * wouldn't work anymore...).
3504 * The use of this ioctl is deprecated: use TIOCSRS485
3505 * instead.*/
77accbf5 3506 struct rs485_control rs485ctrl;
6fd1af4c
CS		 3507 struct serial_rs485 rs485data;
3508 printk(KERN_DEBUG "The use of this ioctl is deprecated. Use TIOCSRS485 instead\n");
77accbf5
JN		 3509 if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg,
3510 sizeof(rs485ctrl)))
3511 return -EFAULT;
1da177e4 3512
6fd1af4c
CS		 3513 rs485data.delay_rts_before_send = rs485ctrl.delay_rts_before_send;
3514 rs485data.flags = 0;
c7213fc4 3515
6fd1af4c
CS		 3516 if (rs485ctrl.enabled)
3517 rs485data.flags |= SER_RS485_ENABLED;
3518 else
3519 rs485data.flags &= ~(SER_RS485_ENABLED);
3520
3521 if (rs485ctrl.rts_on_send)
3522 rs485data.flags |= SER_RS485_RTS_ON_SEND;
3523 else
3524 rs485data.flags &= ~(SER_RS485_RTS_ON_SEND);
3525
3526 if (rs485ctrl.rts_after_sent)
3527 rs485data.flags |= SER_RS485_RTS_AFTER_SEND;
3528 else
3529 rs485data.flags &= ~(SER_RS485_RTS_AFTER_SEND);
3530
3531 return e100_enable_rs485(tty, &rs485data);
77accbf5 3532 }
1da177e4 3533
6fd1af4c
CS		 3534 case TIOCSRS485:
3535 {
3536 /* This is the new version of TIOCSRS485, with new
3537 * data structure serial_rs485 */
3538 struct serial_rs485 rs485data;
3539 if (copy_from_user(&rs485data, (struct rs485_control *)arg,
3540 sizeof(rs485data)))
3541 return -EFAULT;
3542
3543 return e100_enable_rs485(tty, &rs485data);
3544 }
3545
f1d23ed8
CS		 3546 case TIOCGRS485:
3547 {
3548 struct serial_rs485 *rs485data =
3549 &(((struct e100_serial *)tty->driver_data)->rs485);
3550 /* This is the ioctl to get RS485 data from user-space */
3551 if (copy_to_user((struct serial_rs485 *) arg,
3552 rs485data,
94479c01 3553 sizeof(struct serial_rs485)))
f1d23ed8
CS		 3554 return -EFAULT;
3555 break;
3556 }
6fd1af4c 3557
77accbf5
JN		 3558 case TIOCSERWRRS485:
3559 {
3560 struct rs485_write rs485wr;
3561 if (copy_from_user(&rs485wr, (struct rs485_write *)arg,
3562 sizeof(rs485wr)))
3563 return -EFAULT;
1da177e4 3564
77accbf5
JN		 3565 return e100_write_rs485(tty, rs485wr.outc, rs485wr.outc_size);
3566 }
1da177e4
LT		 3567#endif
3568
77accbf5
JN		 3569 default:
3570 return -ENOIOCTLCMD;
1da177e4
LT		 3571 }
3572 return 0;
3573}
3574
3575static void
606d099c 3576rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
1da177e4
LT		 3577{
3578 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3579
1da177e4
LT		 3580 change_speed(info);
3581
3582 /* Handle turning off CRTSCTS */
3583 if ((old_termios->c_cflag & CRTSCTS) &&
ee797069 3584 !(tty->termios.c_cflag & CRTSCTS))
1da177e4 3585 rs_start(tty);
1da177e4
LT		 3586
3587}
3588
1da177e4
LT		 3589/*
3590 * ------------------------------------------------------------
3591 * rs_close()
3592 *
3593 * This routine is called when the serial port gets closed. First, we
3594 * wait for the last remaining data to be sent. Then, we unlink its
3595 * S structure from the interrupt chain if necessary, and we free
3596 * that IRQ if nothing is left in the chain.
3597 * ------------------------------------------------------------
3598 */
3599static void
3600rs_close(struct tty_struct *tty, struct file * filp)
3601{
3602 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3603 unsigned long flags;
3604
3605 if (!info)
3606 return;
3607
3608 /* interrupts are disabled for this entire function */
3609
77accbf5 3610 local_irq_save(flags);
1da177e4
LT		 3611
3612 if (tty_hung_up_p(filp)) {
77accbf5 3613 local_irq_restore(flags);
1da177e4
LT		 3614 return;
3615 }
3616
3617#ifdef SERIAL_DEBUG_OPEN
3618 printk("[%d] rs_close ttyS%d, count = %d\n", current->pid,
3619 info->line, info->count);
3620#endif
b12d8dc2 3621 if ((tty->count == 1) && (info->port.count != 1)) {
1da177e4
LT		 3622 /*
3623 * Uh, oh. tty->count is 1, which means that the tty
3624 * structure will be freed. Info->count should always
3625 * be one in these conditions. If it's greater than
3626 * one, we've got real problems, since it means the
3627 * serial port won't be shutdown.
3628 */
3d43b7d5 3629 printk(KERN_ERR
1da177e4 3630 "rs_close: bad serial port count; tty->count is 1, "
b12d8dc2
JS		 3631 "info->count is %d\n", info->port.count);
3632 info->port.count = 1;
1da177e4 3633 }
b12d8dc2 3634 if (--info->port.count < 0) {
3d43b7d5 3635 printk(KERN_ERR "rs_close: bad serial port count for ttyS%d: %d\n",
b12d8dc2
JS		 3636 info->line, info->port.count);
3637 info->port.count = 0;
1da177e4 3638 }
b12d8dc2 3639 if (info->port.count) {
77accbf5 3640 local_irq_restore(flags);
1da177e4
LT		 3641 return;
3642 }
b1d984cf 3643 info->port.flags |= ASYNC_CLOSING;
1da177e4
LT		 3644 /*
3645 * Now we wait for the transmit buffer to clear; and we notify
3646 * the line discipline to only process XON/XOFF characters.
3647 */
3648 tty->closing = 1;
892c7cfc
JS		 3649 if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE)
3650 tty_wait_until_sent(tty, info->port.closing_wait);
1da177e4
LT		 3651 /*
3652 * At this point we stop accepting input. To do this, we
3653 * disable the serial receiver and the DMA receive interrupt.
3654 */
3655#ifdef SERIAL_HANDLE_EARLY_ERRORS
3656 e100_disable_serial_data_irq(info);
3657#endif
3658
1da177e4
LT		 3659 e100_disable_rx(info);
3660 e100_disable_rx_irq(info);
3661
b1d984cf 3662 if (info->port.flags & ASYNC_INITIALIZED) {
1da177e4
LT		 3663 /*
3664 * Before we drop DTR, make sure the UART transmitter
3665 * has completely drained; this is especially
3666 * important as we have a transmit FIFO!
3667 */
3668 rs_wait_until_sent(tty, HZ);
3669 }
1da177e4
LT		 3670
3671 shutdown(info);
978e595f 3672 rs_flush_buffer(tty);
454aa389 3673 tty_ldisc_flush(tty);
1da177e4
LT		 3674 tty->closing = 0;
3675 info->event = 0;
a88487c7 3676 info->port.tty = NULL;
b12d8dc2 3677 if (info->port.blocked_open) {
892c7cfc
JS		 3678 if (info->port.close_delay)
3679 schedule_timeout_interruptible(info->port.close_delay);
4aeaeb0c 3680 wake_up_interruptible(&info->port.open_wait);
1da177e4 3681 }
b1d984cf 3682 info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
4aeaeb0c 3683 wake_up_interruptible(&info->port.close_wait);
77accbf5 3684 local_irq_restore(flags);
1da177e4
LT		 3685
3686 /* port closed */
3687
3688#if defined(CONFIG_ETRAX_RS485)
6fd1af4c
CS		 3689 if (info->rs485.flags & SER_RS485_ENABLED) {
3690 info->rs485.flags &= ~(SER_RS485_ENABLED);
1da177e4
LT		 3691#if defined(CONFIG_ETRAX_RS485_ON_PA)
3692 *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit);
1da177e4
LT		 3693#endif
3694 }
3695#endif
77accbf5
JN		 3696
3697 /*
3698 * Release any allocated DMA irq's.
3699 */
3700 if (info->dma_in_enabled) {
3701 free_irq(info->dma_in_irq_nbr, info);
3702 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3703 info->uses_dma_in = 0;
3704#ifdef SERIAL_DEBUG_OPEN
3705 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3706 info->dma_in_irq_description);
3707#endif
3708 }
3709 if (info->dma_out_enabled) {
3710 free_irq(info->dma_out_irq_nbr, info);
3711 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3712 info->uses_dma_out = 0;
3713#ifdef SERIAL_DEBUG_OPEN
3714 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3715 info->dma_out_irq_description);
3716#endif
3717 }
1da177e4
LT		 3718}
3719
3720/*
3721 * rs_wait_until_sent() --- wait until the transmitter is empty
3722 */
3723static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
3724{
3725 unsigned long orig_jiffies;
3726 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3727 unsigned long curr_time = jiffies;
3728 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3729 long elapsed_usec =
3730 (curr_time - info->last_tx_active) * (1000000/HZ) +
3731 curr_time_usec - info->last_tx_active_usec;
3732
3733 /*
3734 * Check R_DMA_CHx_STATUS bit 0-6=number of available bytes in FIFO
3735 * R_DMA_CHx_HWSW bit 31-16=nbr of bytes left in DMA buffer (0=64k)
3736 */
3737 orig_jiffies = jiffies;
3738 while (info->xmit.head != info->xmit.tail || /* More in send queue */
3739 (*info->ostatusadr & 0x007f) || /* more in FIFO */
3740 (elapsed_usec < 2*info->char_time_usec)) {
3c76bc5b 3741 schedule_timeout_interruptible(1);
1da177e4
LT		 3742 if (signal_pending(current))
3743 break;
3744 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3745 break;
3746 curr_time = jiffies;
3747 curr_time_usec = GET_JIFFIES_USEC();
3748 elapsed_usec =
3749 (curr_time - info->last_tx_active) * (1000000/HZ) +
3750 curr_time_usec - info->last_tx_active_usec;
3751 }
3752 set_current_state(TASK_RUNNING);
3753}
3754
3755/*
3756 * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
3757 */
3758void
3759rs_hangup(struct tty_struct *tty)
3760{
3761 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3762
3763 rs_flush_buffer(tty);
3764 shutdown(info);
3765 info->event = 0;
b12d8dc2 3766 info->port.count = 0;
b1d984cf 3767 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
a88487c7 3768 info->port.tty = NULL;
4aeaeb0c 3769 wake_up_interruptible(&info->port.open_wait);
1da177e4
LT		 3770}
3771
3772/*
3773 * ------------------------------------------------------------
3774 * rs_open() and friends
3775 * ------------------------------------------------------------
3776 */
3777static int
3778block_til_ready(struct tty_struct *tty, struct file * filp,
3779 struct e100_serial *info)
3780{
3781 DECLARE_WAITQUEUE(wait, current);
3782 unsigned long flags;
3783 int retval;
e359a4e3 3784 int do_clocal = 0;
1da177e4
LT		 3785
3786 /*
3787 * If the device is in the middle of being closed, then block
3788 * until it's done, and then try again.
3789 */
e359a4e3 3790 if (info->port.flags & ASYNC_CLOSING) {
4aeaeb0c 3791 wait_event_interruptible_tty(tty, info->port.close_wait,
b1d984cf 3792 !(info->port.flags & ASYNC_CLOSING));
1da177e4 3793#ifdef SERIAL_DO_RESTART
b1d984cf 3794 if (info->port.flags & ASYNC_HUP_NOTIFY)
1da177e4
LT		 3795 return -EAGAIN;
3796 else
3797 return -ERESTARTSYS;
3798#else
3799 return -EAGAIN;
3800#endif
3801 }
3802
3803 /*
3804 * If non-blocking mode is set, or the port is not enabled,
3805 * then make the check up front and then exit.
3806 */
3807 if ((filp->f_flags & O_NONBLOCK) ||
3808 (tty->flags & (1 << TTY_IO_ERROR))) {
b1d984cf 3809 info->port.flags |= ASYNC_NORMAL_ACTIVE;
1da177e4
LT		 3810 return 0;
3811 }
3812
adc8d746 3813 if (tty->termios.c_cflag & CLOCAL) {
1da177e4
LT		 3814 do_clocal = 1;
3815 }
3816
3817 /*
3818 * Block waiting for the carrier detect and the line to become
3819 * free (i.e., not in use by the callout). While we are in
b12d8dc2 3820 * this loop, info->port.count is dropped by one, so that
1da177e4
LT		 3821 * rs_close() knows when to free things. We restore it upon
3822 * exit, either normal or abnormal.
3823 */
3824 retval = 0;
4aeaeb0c 3825 add_wait_queue(&info->port.open_wait, &wait);
1da177e4
LT		 3826#ifdef SERIAL_DEBUG_OPEN
3827 printk("block_til_ready before block: ttyS%d, count = %d\n",
b12d8dc2 3828 info->line, info->port.count);
1da177e4 3829#endif
77accbf5 3830 local_irq_save(flags);
e359a4e3 3831 info->port.count--;
77accbf5 3832 local_irq_restore(flags);
b12d8dc2 3833 info->port.blocked_open++;
1da177e4 3834 while (1) {
77accbf5 3835 local_irq_save(flags);
1da177e4
LT		 3836 /* assert RTS and DTR */
3837 e100_rts(info, 1);
3838 e100_dtr(info, 1);
77accbf5 3839 local_irq_restore(flags);
1da177e4
LT		 3840 set_current_state(TASK_INTERRUPTIBLE);
3841 if (tty_hung_up_p(filp) ||
b1d984cf 3842 !(info->port.flags & ASYNC_INITIALIZED)) {
1da177e4 3843#ifdef SERIAL_DO_RESTART
b1d984cf 3844 if (info->port.flags & ASYNC_HUP_NOTIFY)
1da177e4
LT		 3845 retval = -EAGAIN;
3846 else
3847 retval = -ERESTARTSYS;
3848#else
3849 retval = -EAGAIN;
3850#endif
3851 break;
3852 }
b1d984cf 3853 if (!(info->port.flags & ASYNC_CLOSING) && do_clocal)
1da177e4
LT		 3854 /* && (do_clocal || DCD_IS_ASSERTED) */
3855 break;
3856 if (signal_pending(current)) {
3857 retval = -ERESTARTSYS;
3858 break;
3859 }
3860#ifdef SERIAL_DEBUG_OPEN
3861 printk("block_til_ready blocking: ttyS%d, count = %d\n",
b12d8dc2 3862 info->line, info->port.count);
1da177e4 3863#endif
89c8d91e 3864 tty_unlock(tty);
1da177e4 3865 schedule();
89c8d91e 3866 tty_lock(tty);
1da177e4
LT		 3867 }
3868 set_current_state(TASK_RUNNING);
4aeaeb0c 3869 remove_wait_queue(&info->port.open_wait, &wait);
e359a4e3 3870 if (!tty_hung_up_p(filp))
b12d8dc2
JS		 3871 info->port.count++;
3872 info->port.blocked_open--;
1da177e4
LT		 3873#ifdef SERIAL_DEBUG_OPEN
3874 printk("block_til_ready after blocking: ttyS%d, count = %d\n",
b12d8dc2 3875 info->line, info->port.count);
1da177e4
LT		 3876#endif
3877 if (retval)
3878 return retval;
b1d984cf 3879 info->port.flags |= ASYNC_NORMAL_ACTIVE;
1da177e4
LT		 3880 return 0;
3881}
3882
77accbf5
JN		 3883static void
3884deinit_port(struct e100_serial *info)
3885{
3886 if (info->dma_out_enabled) {
3887 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3888 free_irq(info->dma_out_irq_nbr, info);
3889 }
3890 if (info->dma_in_enabled) {
3891 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3892 free_irq(info->dma_in_irq_nbr, info);
3893 }
3894}
3895
1da177e4
LT		 3896/*
3897 * This routine is called whenever a serial port is opened.
3898 * It performs the serial-specific initialization for the tty structure.
3899 */
3900static int
3901rs_open(struct tty_struct *tty, struct file * filp)
3902{
3903 struct e100_serial *info;
410235fd 3904 int retval;
77accbf5 3905 int allocated_resources = 0;
1da177e4 3906
410235fd 3907 info = rs_table + tty->index;
1da177e4
LT		 3908 if (!info->enabled)
3909 return -ENODEV;
3910
3911#ifdef SERIAL_DEBUG_OPEN
3912 printk("[%d] rs_open %s, count = %d\n", current->pid, tty->name,
b12d8dc2 3913 info->port.count);
1da177e4
LT		 3914#endif
3915
b12d8dc2 3916 info->port.count++;
1da177e4 3917 tty->driver_data = info;
a88487c7 3918 info->port.tty = tty;
1da177e4 3919
b1d984cf 3920 info->port.low_latency = !!(info->port.flags & ASYNC_LOW_LATENCY);
1da177e4 3921
1da177e4
LT		 3922 /*
3923 * If the port is in the middle of closing, bail out now
3924 */
e359a4e3 3925 if (info->port.flags & ASYNC_CLOSING) {
4aeaeb0c 3926 wait_event_interruptible_tty(tty, info->port.close_wait,
b1d984cf 3927 !(info->port.flags & ASYNC_CLOSING));
1da177e4 3928#ifdef SERIAL_DO_RESTART
b1d984cf 3929 return ((info->port.flags & ASYNC_HUP_NOTIFY) ?
1da177e4
LT		 3930 -EAGAIN : -ERESTARTSYS);
3931#else
3932 return -EAGAIN;
3933#endif
3934 }
3935
77accbf5
JN		 3936 /*
3937 * If DMA is enabled try to allocate the irq's.
3938 */
b12d8dc2 3939 if (info->port.count == 1) {
77accbf5
JN		 3940 allocated_resources = 1;
3941 if (info->dma_in_enabled) {
3942 if (request_irq(info->dma_in_irq_nbr,
3943 rec_interrupt,
3944 info->dma_in_irq_flags,
3945 info->dma_in_irq_description,
3946 info)) {
3947 printk(KERN_WARNING "DMA irq '%s' busy; "
3948 "falling back to non-DMA mode\n",
3949 info->dma_in_irq_description);
3950 /* Make sure we never try to use DMA in */
3951 /* for the port again. */
3952 info->dma_in_enabled = 0;
3953 } else if (cris_request_dma(info->dma_in_nbr,
3954 info->dma_in_irq_description,
3955 DMA_VERBOSE_ON_ERROR,
3956 info->dma_owner)) {
3957 free_irq(info->dma_in_irq_nbr, info);
3958 printk(KERN_WARNING "DMA '%s' busy; "
3959 "falling back to non-DMA mode\n",
3960 info->dma_in_irq_description);
3961 /* Make sure we never try to use DMA in */
3962 /* for the port again. */
3963 info->dma_in_enabled = 0;
3964 }
3965#ifdef SERIAL_DEBUG_OPEN
3966 else
3967 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
3968 info->dma_in_irq_description);
3969#endif
3970 }
3971 if (info->dma_out_enabled) {
3972 if (request_irq(info->dma_out_irq_nbr,
3973 tr_interrupt,
3974 info->dma_out_irq_flags,
3975 info->dma_out_irq_description,
3976 info)) {
3977 printk(KERN_WARNING "DMA irq '%s' busy; "
3978 "falling back to non-DMA mode\n",
3979 info->dma_out_irq_description);
3980 /* Make sure we never try to use DMA out */
3981 /* for the port again. */
3982 info->dma_out_enabled = 0;
3983 } else if (cris_request_dma(info->dma_out_nbr,
3984 info->dma_out_irq_description,
3985 DMA_VERBOSE_ON_ERROR,
3986 info->dma_owner)) {
3987 free_irq(info->dma_out_irq_nbr, info);
3988 printk(KERN_WARNING "DMA '%s' busy; "
3989 "falling back to non-DMA mode\n",
3990 info->dma_out_irq_description);
3991 /* Make sure we never try to use DMA out */
3992 /* for the port again. */
3993 info->dma_out_enabled = 0;
3994 }
3995#ifdef SERIAL_DEBUG_OPEN
3996 else
3997 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
3998 info->dma_out_irq_description);
3999#endif
4000 }
4001 }
4002
1da177e4
LT		 4003 /*
4004 * Start up the serial port
4005 */
4006
4007 retval = startup(info);
77accbf5
JN		 4008 if (retval) {
4009 if (allocated_resources)
4010 deinit_port(info);
4011
b12d8dc2 4012 /* FIXME Decrease count info->port.count here too? */
1da177e4 4013 return retval;
77accbf5
JN		 4014 }
4015
1da177e4
LT		 4016
4017 retval = block_til_ready(tty, filp, info);
4018 if (retval) {
4019#ifdef SERIAL_DEBUG_OPEN
4020 printk("rs_open returning after block_til_ready with %d\n",
4021 retval);
4022#endif
77accbf5
JN		 4023 if (allocated_resources)
4024 deinit_port(info);
4025
1da177e4
LT		 4026 return retval;
4027 }
4028
1da177e4
LT		 4029#ifdef SERIAL_DEBUG_OPEN
4030 printk("rs_open ttyS%d successful...\n", info->line);
4031#endif
4032 DLOG_INT_TRIG( log_int_pos = 0);
4033
4034 DFLIP( if (info->line == SERIAL_DEBUG_LINE) {
4035 info->icount.rx = 0;
4036 } );
4037
4038 return 0;
4039}
4040
9e040a3e 4041#ifdef CONFIG_PROC_FS
1da177e4
LT		 4042/*
4043 * /proc fs routines....
4044 */
4045
9e040a3e 4046static void seq_line_info(struct seq_file *m, struct e100_serial *info)
1da177e4 4047{
1da177e4
LT		 4048 unsigned long tmp;
4049
9e040a3e
JN		 4050 seq_printf(m, "%d: uart:E100 port:%lX irq:%d",
4051 info->line, (unsigned long)info->ioport, info->irq);
1da177e4 4052
d7283353 4053 if (!info->ioport || (info->type == PORT_UNKNOWN)) {
9e040a3e
JN		 4054 seq_printf(m, "\n");
4055 return;
1da177e4
LT		 4056 }
4057
9e040a3e
JN		 4058 seq_printf(m, " baud:%d", info->baud);
4059 seq_printf(m, " tx:%lu rx:%lu",
1da177e4
LT		 4060 (unsigned long)info->icount.tx,
4061 (unsigned long)info->icount.rx);
4062 tmp = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
9e040a3e
JN		 4063 if (tmp)
4064 seq_printf(m, " tx_pend:%lu/%lu",
4065 (unsigned long)tmp,
4066 (unsigned long)SERIAL_XMIT_SIZE);
1da177e4 4067
9e040a3e
JN		 4068 seq_printf(m, " rx_pend:%lu/%lu",
4069 (unsigned long)info->recv_cnt,
4070 (unsigned long)info->max_recv_cnt);
1da177e4
LT		 4071
4072#if 1
a88487c7 4073 if (info->port.tty) {
a88487c7 4074 if (info->port.tty->stopped)
9e040a3e
JN		 4075 seq_printf(m, " stopped:%i",
4076 (int)info->port.tty->stopped);
1da177e4
LT		 4077 }
4078
4079 {
d7283353 4080 unsigned char rstat = info->ioport[REG_STATUS];
9e040a3e
JN		 4081 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect))
4082 seq_printf(m, " xoff_detect:1");
1da177e4
LT		 4083 }
4084
4085#endif
4086
1da177e4 4087 if (info->icount.frame)
9e040a3e 4088 seq_printf(m, " fe:%lu", (unsigned long)info->icount.frame);
1da177e4
LT		 4089
4090 if (info->icount.parity)
9e040a3e 4091 seq_printf(m, " pe:%lu", (unsigned long)info->icount.parity);
1da177e4
LT		 4092
4093 if (info->icount.brk)
9e040a3e 4094 seq_printf(m, " brk:%lu", (unsigned long)info->icount.brk);
1da177e4
LT		 4095
4096 if (info->icount.overrun)
9e040a3e 4097 seq_printf(m, " oe:%lu", (unsigned long)info->icount.overrun);
1da177e4
LT		 4098
4099 /*
4100 * Last thing is the RS-232 status lines
4101 */
9e040a3e
JN		 4102 if (!E100_RTS_GET(info))
4103 seq_puts(m, "|RTS");
4104 if (!E100_CTS_GET(info))
4105 seq_puts(m, "|CTS");
4106 if (!E100_DTR_GET(info))
4107 seq_puts(m, "|DTR");
4108 if (!E100_DSR_GET(info))
4109 seq_puts(m, "|DSR");
4110 if (!E100_CD_GET(info))
4111 seq_puts(m, "|CD");
4112 if (!E100_RI_GET(info))
4113 seq_puts(m, "|RI");
4114 seq_puts(m, "\n");
1da177e4
LT		 4115}
4116
9e040a3e
JN		 4117
4118static int crisv10_proc_show(struct seq_file *m, void *v)
1da177e4 4119{
9e040a3e 4120 int i;
1da177e4 4121
9e040a3e
JN		 4122 seq_printf(m, "serinfo:1.0 driver:%s\n", serial_version);
4123
4124 for (i = 0; i < NR_PORTS; i++) {
1da177e4
LT		 4125 if (!rs_table[i].enabled)
4126 continue;
9e040a3e 4127 seq_line_info(m, &rs_table[i]);
1da177e4
LT		 4128 }
4129#ifdef DEBUG_LOG_INCLUDED
4130 for (i = 0; i < debug_log_pos; i++) {
9e040a3e
JN		 4131 seq_printf(m, "%-4i %lu.%lu ",
4132 i, debug_log[i].time,
4133 timer_data_to_ns(debug_log[i].timer_data));
4134 seq_printf(m, debug_log[i].string, debug_log[i].value);
1da177e4 4135 }
9e040a3e 4136 seq_printf(m, "debug_log %i/%i\n", i, DEBUG_LOG_SIZE);
1da177e4
LT		 4137 debug_log_pos = 0;
4138#endif
9e040a3e
JN		 4139 return 0;
4140}
1da177e4 4141
9e040a3e
JN		 4142static int crisv10_proc_open(struct inode *inode, struct file *file)
4143{
4144 return single_open(file, crisv10_proc_show, NULL);
1da177e4
LT		 4145}
4146
9e040a3e
JN		 4147static const struct file_operations crisv10_proc_fops = {
4148 .owner = THIS_MODULE,
4149 .open = crisv10_proc_open,
4150 .read = seq_read,
4151 .llseek = seq_lseek,
4152 .release = single_release,
4153};
4154#endif
4155
4156
1da177e4
LT		 4157/* Finally, routines used to initialize the serial driver. */
4158
9e040a3e 4159static void show_serial_version(void)
1da177e4
LT		 4160{
4161 printk(KERN_INFO
9e040a3e
JN		 4162 "ETRAX 100LX serial-driver %s, "
4163 "(c) 2000-2004 Axis Communications AB\r\n",
1da177e4
LT		 4164 &serial_version[11]); /* "$Revision: x.yy" */
4165}
4166
4167/* rs_init inits the driver at boot (using the module_init chain) */
4168
b68e31d0 4169static const struct tty_operations rs_ops = {
1da177e4
LT		 4170 .open = rs_open,
4171 .close = rs_close,
4172 .write = rs_write,
4173 .flush_chars = rs_flush_chars,
4174 .write_room = rs_write_room,
4175 .chars_in_buffer = rs_chars_in_buffer,
4176 .flush_buffer = rs_flush_buffer,
4177 .ioctl = rs_ioctl,
4178 .throttle = rs_throttle,
4179 .unthrottle = rs_unthrottle,
4180 .set_termios = rs_set_termios,
4181 .stop = rs_stop,
4182 .start = rs_start,
4183 .hangup = rs_hangup,
4184 .break_ctl = rs_break,
4185 .send_xchar = rs_send_xchar,
4186 .wait_until_sent = rs_wait_until_sent,
77accbf5 4187 .tiocmget = rs_tiocmget,
9e040a3e
JN		 4188 .tiocmset = rs_tiocmset,
4189#ifdef CONFIG_PROC_FS
4190 .proc_fops = &crisv10_proc_fops,
4191#endif
1da177e4
LT		 4192};
4193
9e040a3e 4194static int __init rs_init(void)
1da177e4
LT		 4195{
4196 int i;
4197 struct e100_serial *info;
4198 struct tty_driver *driver = alloc_tty_driver(NR_PORTS);
4199
4200 if (!driver)
4201 return -ENOMEM;
4202
4203 show_serial_version();
4204
4205 /* Setup the timed flush handler system */
4206
4207#if !defined(CONFIG_ETRAX_SERIAL_FAST_TIMER)
77accbf5
JN		 4208 setup_timer(&flush_timer, timed_flush_handler, 0);
4209 mod_timer(&flush_timer, jiffies + 5);
4210#endif
4211
4212#if defined(CONFIG_ETRAX_RS485)
4213#if defined(CONFIG_ETRAX_RS485_ON_PA)
2f7861de 4214 if (cris_io_interface_allocate_pins(if_serial_0, 'a', rs485_pa_bit,
77accbf5 4215 rs485_pa_bit)) {
3d43b7d5 4216 printk(KERN_ERR "ETRAX100LX serial: Could not allocate "
77accbf5 4217 "RS485 pin\n");
41ca7322 4218 put_tty_driver(driver);
77accbf5
JN		 4219 return -EBUSY;
4220 }
4221#endif
1da177e4
LT		 4222#endif
4223
4224 /* Initialize the tty_driver structure */
4225
4226 driver->driver_name = "serial";
4227 driver->name = "ttyS";
4228 driver->major = TTY_MAJOR;
4229 driver->minor_start = 64;
4230 driver->type = TTY_DRIVER_TYPE_SERIAL;
4231 driver->subtype = SERIAL_TYPE_NORMAL;
4232 driver->init_termios = tty_std_termios;
4233 driver->init_termios.c_cflag =
4234 B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
606d099c
AC		 4235 driver->init_termios.c_ispeed = 115200;
4236 driver->init_termios.c_ospeed = 115200;
c4d6ebeb 4237 driver->flags = TTY_DRIVER_REAL_RAW;
1da177e4
LT		 4238
4239 tty_set_operations(driver, &rs_ops);
4240 serial_driver = driver;
1da177e4 4241
b19e2ca7 4242 /* do some initializing for the separate ports */
1da177e4 4243 for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) {
77accbf5
JN		 4244 if (info->enabled) {
4245 if (cris_request_io_interface(info->io_if,
4246 info->io_if_description)) {
3d43b7d5 4247 printk(KERN_ERR "ETRAX100LX async serial: "
77accbf5
JN		 4248 "Could not allocate IO pins for "
4249 "%s, port %d\n",
4250 info->io_if_description, i);
4251 info->enabled = 0;
4252 }
4253 }
953756e2 4254 tty_port_init(&info->port);
1da177e4
LT		 4255 info->uses_dma_in = 0;
4256 info->uses_dma_out = 0;
4257 info->line = i;
a88487c7 4258 info->port.tty = NULL;
1da177e4
LT		 4259 info->type = PORT_ETRAX;
4260 info->tr_running = 0;
4261 info->forced_eop = 0;
4262 info->baud_base = DEF_BAUD_BASE;
4263 info->custom_divisor = 0;
1da177e4
LT		 4264 info->x_char = 0;
4265 info->event = 0;
1da177e4
LT		 4266 info->xmit.buf = NULL;
4267 info->xmit.tail = info->xmit.head = 0;
4268 info->first_recv_buffer = info->last_recv_buffer = NULL;
4269 info->recv_cnt = info->max_recv_cnt = 0;
4270 info->last_tx_active_usec = 0;
4271 info->last_tx_active = 0;
4272
4273#if defined(CONFIG_ETRAX_RS485)
4274 /* Set sane defaults */
6fd1af4c
CS		 4275 info->rs485.flags &= ~(SER_RS485_RTS_ON_SEND);
4276 info->rs485.flags |= SER_RS485_RTS_AFTER_SEND;
1da177e4 4277 info->rs485.delay_rts_before_send = 0;
6fd1af4c 4278 info->rs485.flags &= ~(SER_RS485_ENABLED);
1da177e4 4279#endif
77accbf5 4280 INIT_WORK(&info->work, do_softint);
1da177e4
LT		 4281
4282 if (info->enabled) {
078dee2d
KV		 4283 printk(KERN_INFO "%s%d at %p is a builtin UART with DMA\n",
4284 serial_driver->name, info->line, info->ioport);
1da177e4 4285 }
b19e2ca7 4286 tty_port_link_device(&info->port, driver, i);
1da177e4 4287 }
b19e2ca7
JS		 4288
4289 if (tty_register_driver(driver))
4290 panic("Couldn't register serial driver\n");
4291
1da177e4
LT		 4292#ifdef CONFIG_ETRAX_FAST_TIMER
4293#ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
4294 memset(fast_timers, 0, sizeof(fast_timers));
4295#endif
4296#ifdef CONFIG_ETRAX_RS485
4297 memset(fast_timers_rs485, 0, sizeof(fast_timers_rs485));
4298#endif
4299 fast_timer_init();
4300#endif
4301
77accbf5 4302#ifndef CONFIG_ETRAX_KGDB
1da177e4
LT		 4303 /* Not needed in simulator. May only complicate stuff. */
4304 /* hook the irq's for DMA channel 6 and 7, serial output and input, and some more... */
4305
77accbf5 4306 if (request_irq(SERIAL_IRQ_NBR, ser_interrupt,
9cfb5c05 4307 IRQF_SHARED, "serial ", driver))
71cc2c21 4308 panic("%s: Failed to request irq8", __func__);
1da177e4 4309
1da177e4 4310#endif
77accbf5 4311
1da177e4
LT		 4312 return 0;
4313}
4314
4315/* this makes sure that rs_init is called during kernel boot */
4316
4317module_init(rs_init);
Linux kernel - Deliverables
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