Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
9399575d | 2 | * dz.c: Serial port driver for DECstations equipped |
1da177e4 LT |
3 | * with the DZ chipset. |
4 | * | |
fd8c5972 RB |
5 | * Copyright (C) 1998 Olivier A. D. Lebaillif |
6 | * | |
1da177e4 LT |
7 | * Email: olivier.lebaillif@ifrsys.com |
8 | * | |
87cff7fb | 9 | * Copyright (C) 2004, 2006, 2007 Maciej W. Rozycki |
9399575d | 10 | * |
1da177e4 LT |
11 | * [31-AUG-98] triemer |
12 | * Changed IRQ to use Harald's dec internals interrupts.h | |
13 | * removed base_addr code - moving address assignment to setup.c | |
14 | * Changed name of dz_init to rs_init to be consistent with tc code | |
15 | * [13-NOV-98] triemer fixed code to receive characters | |
fd8c5972 | 16 | * after patches by harald to irq code. |
1da177e4 LT |
17 | * [09-JAN-99] triemer minor fix for schedule - due to removal of timeout |
18 | * field from "current" - somewhere between 2.1.121 and 2.1.131 | |
19 | Qua Jun 27 15:02:26 BRT 2001 | |
20 | * [27-JUN-2001] Arnaldo Carvalho de Melo <acme@conectiva.com.br> - cleanups | |
fd8c5972 RB |
21 | * |
22 | * Parts (C) 1999 David Airlie, airlied@linux.ie | |
23 | * [07-SEP-99] Bugfixes | |
1da177e4 LT |
24 | * |
25 | * [06-Jan-2002] Russell King <rmk@arm.linux.org.uk> | |
26 | * Converted to new serial core | |
27 | */ | |
28 | ||
29 | #undef DEBUG_DZ | |
30 | ||
9399575d MR |
31 | #if defined(CONFIG_SERIAL_DZ_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
32 | #define SUPPORT_SYSRQ | |
33 | #endif | |
34 | ||
87cff7fb MR |
35 | #include <linux/bitops.h> |
36 | #include <linux/compiler.h> | |
37 | #include <linux/console.h> | |
9399575d | 38 | #include <linux/delay.h> |
87cff7fb | 39 | #include <linux/errno.h> |
1da177e4 | 40 | #include <linux/init.h> |
87cff7fb | 41 | #include <linux/interrupt.h> |
e6ee512f | 42 | #include <linux/ioport.h> |
87cff7fb MR |
43 | #include <linux/kernel.h> |
44 | #include <linux/major.h> | |
45 | #include <linux/module.h> | |
46 | #include <linux/serial.h> | |
47 | #include <linux/serial_core.h> | |
9399575d | 48 | #include <linux/sysrq.h> |
1da177e4 | 49 | #include <linux/tty.h> |
ee160a38 | 50 | #include <linux/tty_flip.h> |
1da177e4 | 51 | |
60063497 | 52 | #include <linux/atomic.h> |
1da177e4 | 53 | #include <asm/bootinfo.h> |
e6ee512f | 54 | #include <asm/io.h> |
87cff7fb | 55 | |
1da177e4 LT |
56 | #include <asm/dec/interrupts.h> |
57 | #include <asm/dec/kn01.h> | |
58 | #include <asm/dec/kn02.h> | |
59 | #include <asm/dec/machtype.h> | |
60 | #include <asm/dec/prom.h> | |
e6ee512f | 61 | #include <asm/dec/system.h> |
1da177e4 | 62 | |
1da177e4 LT |
63 | #include "dz.h" |
64 | ||
e6ee512f MR |
65 | |
66 | MODULE_DESCRIPTION("DECstation DZ serial driver"); | |
67 | MODULE_LICENSE("GPL"); | |
68 | ||
69 | ||
70 | static char dz_name[] __initdata = "DECstation DZ serial driver version "; | |
71 | static char dz_version[] __initdata = "1.04"; | |
1da177e4 LT |
72 | |
73 | struct dz_port { | |
e6ee512f | 74 | struct dz_mux *mux; |
1da177e4 LT |
75 | struct uart_port port; |
76 | unsigned int cflag; | |
77 | }; | |
78 | ||
e6ee512f MR |
79 | struct dz_mux { |
80 | struct dz_port dport[DZ_NB_PORT]; | |
81 | atomic_t map_guard; | |
82 | atomic_t irq_guard; | |
83 | int initialised; | |
84 | }; | |
85 | ||
86 | static struct dz_mux dz_mux; | |
1da177e4 | 87 | |
f5519caa MR |
88 | static inline struct dz_port *to_dport(struct uart_port *uport) |
89 | { | |
90 | return container_of(uport, struct dz_port, port); | |
91 | } | |
92 | ||
1da177e4 LT |
93 | /* |
94 | * ------------------------------------------------------------ | |
95 | * dz_in () and dz_out () | |
96 | * | |
fd8c5972 | 97 | * These routines are used to access the registers of the DZ |
1da177e4 LT |
98 | * chip, hiding relocation differences between implementation. |
99 | * ------------------------------------------------------------ | |
100 | */ | |
101 | ||
e6ee512f | 102 | static u16 dz_in(struct dz_port *dport, unsigned offset) |
1da177e4 | 103 | { |
e6ee512f | 104 | void __iomem *addr = dport->port.membase + offset; |
9399575d | 105 | |
e6ee512f | 106 | return readw(addr); |
1da177e4 LT |
107 | } |
108 | ||
e6ee512f | 109 | static void dz_out(struct dz_port *dport, unsigned offset, u16 value) |
1da177e4 | 110 | { |
e6ee512f | 111 | void __iomem *addr = dport->port.membase + offset; |
9399575d | 112 | |
e6ee512f | 113 | writew(value, addr); |
1da177e4 LT |
114 | } |
115 | ||
116 | /* | |
117 | * ------------------------------------------------------------ | |
118 | * rs_stop () and rs_start () | |
119 | * | |
fd8c5972 RB |
120 | * These routines are called before setting or resetting |
121 | * tty->stopped. They enable or disable transmitter interrupts, | |
1da177e4 LT |
122 | * as necessary. |
123 | * ------------------------------------------------------------ | |
124 | */ | |
125 | ||
b129a8cc | 126 | static void dz_stop_tx(struct uart_port *uport) |
1da177e4 | 127 | { |
f5519caa | 128 | struct dz_port *dport = to_dport(uport); |
e6ee512f | 129 | u16 tmp, mask = 1 << dport->port.line; |
1da177e4 | 130 | |
1da177e4 LT |
131 | tmp = dz_in(dport, DZ_TCR); /* read the TX flag */ |
132 | tmp &= ~mask; /* clear the TX flag */ | |
133 | dz_out(dport, DZ_TCR, tmp); | |
1da177e4 LT |
134 | } |
135 | ||
b129a8cc | 136 | static void dz_start_tx(struct uart_port *uport) |
1da177e4 | 137 | { |
f5519caa | 138 | struct dz_port *dport = to_dport(uport); |
e6ee512f | 139 | u16 tmp, mask = 1 << dport->port.line; |
1da177e4 | 140 | |
1da177e4 LT |
141 | tmp = dz_in(dport, DZ_TCR); /* read the TX flag */ |
142 | tmp |= mask; /* set the TX flag */ | |
143 | dz_out(dport, DZ_TCR, tmp); | |
1da177e4 LT |
144 | } |
145 | ||
146 | static void dz_stop_rx(struct uart_port *uport) | |
147 | { | |
f5519caa | 148 | struct dz_port *dport = to_dport(uport); |
1da177e4 | 149 | |
ff11d078 MR |
150 | dport->cflag &= ~DZ_RXENAB; |
151 | dz_out(dport, DZ_LPR, dport->cflag); | |
1da177e4 LT |
152 | } |
153 | ||
1da177e4 LT |
154 | /* |
155 | * ------------------------------------------------------------ | |
1da177e4 | 156 | * |
9399575d MR |
157 | * Here start the interrupt handling routines. All of the following |
158 | * subroutines are declared as inline and are folded into | |
159 | * dz_interrupt. They were separated out for readability's sake. | |
160 | * | |
161 | * Note: dz_interrupt() is a "fast" interrupt, which means that it | |
1da177e4 | 162 | * runs with interrupts turned off. People who may want to modify |
9399575d | 163 | * dz_interrupt() should try to keep the interrupt handler as fast as |
1da177e4 LT |
164 | * possible. After you are done making modifications, it is not a bad |
165 | * idea to do: | |
fd8c5972 | 166 | * |
1da177e4 LT |
167 | * make drivers/serial/dz.s |
168 | * | |
169 | * and look at the resulting assemble code in dz.s. | |
170 | * | |
171 | * ------------------------------------------------------------ | |
172 | */ | |
173 | ||
174 | /* | |
175 | * ------------------------------------------------------------ | |
176 | * receive_char () | |
177 | * | |
178 | * This routine deals with inputs from any lines. | |
179 | * ------------------------------------------------------------ | |
180 | */ | |
e6ee512f | 181 | static inline void dz_receive_chars(struct dz_mux *mux) |
1da177e4 | 182 | { |
54c0f37e | 183 | struct uart_port *uport; |
e6ee512f | 184 | struct dz_port *dport = &mux->dport[0]; |
1da177e4 | 185 | struct uart_icount *icount; |
9399575d | 186 | int lines_rx[DZ_NB_PORT] = { [0 ... DZ_NB_PORT - 1] = 0 }; |
1da177e4 | 187 | unsigned char ch, flag; |
e6ee512f | 188 | u16 status; |
9399575d | 189 | int i; |
1da177e4 | 190 | |
e6ee512f MR |
191 | while ((status = dz_in(dport, DZ_RBUF)) & DZ_DVAL) { |
192 | dport = &mux->dport[LINE(status)]; | |
54c0f37e | 193 | uport = &dport->port; |
1da177e4 | 194 | |
9399575d | 195 | ch = UCHAR(status); /* grab the char */ |
54c0f37e | 196 | flag = TTY_NORMAL; |
1da177e4 | 197 | |
54c0f37e | 198 | icount = &uport->icount; |
1da177e4 LT |
199 | icount->rx++; |
200 | ||
54c0f37e MR |
201 | if (unlikely(status & (DZ_OERR | DZ_FERR | DZ_PERR))) { |
202 | ||
9399575d | 203 | /* |
54c0f37e MR |
204 | * There is no separate BREAK status bit, so treat |
205 | * null characters with framing errors as BREAKs; | |
206 | * normally, otherwise. For this move the Framing | |
207 | * Error bit to a simulated BREAK bit. | |
1da177e4 | 208 | */ |
54c0f37e MR |
209 | if (!ch) { |
210 | status |= (status & DZ_FERR) >> | |
211 | (ffs(DZ_FERR) - ffs(DZ_BREAK)); | |
212 | status &= ~DZ_FERR; | |
213 | } | |
214 | ||
215 | /* Handle SysRq/SAK & keep track of the statistics. */ | |
216 | if (status & DZ_BREAK) { | |
217 | icount->brk++; | |
218 | if (uart_handle_break(uport)) | |
219 | continue; | |
220 | } else if (status & DZ_FERR) | |
221 | icount->frame++; | |
222 | else if (status & DZ_PERR) | |
223 | icount->parity++; | |
224 | if (status & DZ_OERR) | |
225 | icount->overrun++; | |
226 | ||
227 | status &= uport->read_status_mask; | |
228 | if (status & DZ_BREAK) | |
9399575d | 229 | flag = TTY_BREAK; |
54c0f37e | 230 | else if (status & DZ_FERR) |
1da177e4 | 231 | flag = TTY_FRAME; |
54c0f37e MR |
232 | else if (status & DZ_PERR) |
233 | flag = TTY_PARITY; | |
234 | ||
1da177e4 | 235 | } |
1da177e4 | 236 | |
54c0f37e | 237 | if (uart_handle_sysrq_char(uport, ch)) |
9399575d MR |
238 | continue; |
239 | ||
54c0f37e MR |
240 | uart_insert_char(uport, status, DZ_OERR, ch, flag); |
241 | lines_rx[LINE(status)] = 1; | |
9399575d MR |
242 | } |
243 | for (i = 0; i < DZ_NB_PORT; i++) | |
244 | if (lines_rx[i]) | |
2e124b4a | 245 | tty_flip_buffer_push(&mux->dport[i].port.state->port); |
1da177e4 LT |
246 | } |
247 | ||
248 | /* | |
249 | * ------------------------------------------------------------ | |
250 | * transmit_char () | |
251 | * | |
252 | * This routine deals with outputs to any lines. | |
253 | * ------------------------------------------------------------ | |
254 | */ | |
e6ee512f | 255 | static inline void dz_transmit_chars(struct dz_mux *mux) |
1da177e4 | 256 | { |
e6ee512f | 257 | struct dz_port *dport = &mux->dport[0]; |
9399575d | 258 | struct circ_buf *xmit; |
1da177e4 | 259 | unsigned char tmp; |
e6ee512f | 260 | u16 status; |
1da177e4 | 261 | |
e6ee512f MR |
262 | status = dz_in(dport, DZ_CSR); |
263 | dport = &mux->dport[LINE(status)]; | |
ebd2c8f6 | 264 | xmit = &dport->port.state->xmit; |
9399575d MR |
265 | |
266 | if (dport->port.x_char) { /* XON/XOFF chars */ | |
1da177e4 LT |
267 | dz_out(dport, DZ_TDR, dport->port.x_char); |
268 | dport->port.icount.tx++; | |
269 | dport->port.x_char = 0; | |
270 | return; | |
271 | } | |
9399575d | 272 | /* If nothing to do or stopped or hardware stopped. */ |
1da177e4 | 273 | if (uart_circ_empty(xmit) || uart_tx_stopped(&dport->port)) { |
43d46ab1 | 274 | spin_lock(&dport->port.lock); |
b129a8cc | 275 | dz_stop_tx(&dport->port); |
43d46ab1 | 276 | spin_unlock(&dport->port.lock); |
1da177e4 LT |
277 | return; |
278 | } | |
279 | ||
280 | /* | |
9399575d MR |
281 | * If something to do... (remember the dz has no output fifo, |
282 | * so we go one char at a time) :-< | |
1da177e4 LT |
283 | */ |
284 | tmp = xmit->buf[xmit->tail]; | |
285 | xmit->tail = (xmit->tail + 1) & (DZ_XMIT_SIZE - 1); | |
286 | dz_out(dport, DZ_TDR, tmp); | |
287 | dport->port.icount.tx++; | |
288 | ||
289 | if (uart_circ_chars_pending(xmit) < DZ_WAKEUP_CHARS) | |
290 | uart_write_wakeup(&dport->port); | |
291 | ||
9399575d | 292 | /* Are we are done. */ |
43d46ab1 MR |
293 | if (uart_circ_empty(xmit)) { |
294 | spin_lock(&dport->port.lock); | |
b129a8cc | 295 | dz_stop_tx(&dport->port); |
43d46ab1 MR |
296 | spin_unlock(&dport->port.lock); |
297 | } | |
1da177e4 LT |
298 | } |
299 | ||
300 | /* | |
301 | * ------------------------------------------------------------ | |
9399575d | 302 | * check_modem_status() |
1da177e4 | 303 | * |
9399575d MR |
304 | * DS 3100 & 5100: Only valid for the MODEM line, duh! |
305 | * DS 5000/200: Valid for the MODEM and PRINTER line. | |
1da177e4 LT |
306 | * ------------------------------------------------------------ |
307 | */ | |
308 | static inline void check_modem_status(struct dz_port *dport) | |
309 | { | |
9399575d MR |
310 | /* |
311 | * FIXME: | |
312 | * 1. No status change interrupt; use a timer. | |
313 | * 2. Handle the 3100/5000 as appropriate. --macro | |
314 | */ | |
e6ee512f | 315 | u16 status; |
1da177e4 | 316 | |
9399575d | 317 | /* If not the modem line just return. */ |
1da177e4 LT |
318 | if (dport->port.line != DZ_MODEM) |
319 | return; | |
320 | ||
321 | status = dz_in(dport, DZ_MSR); | |
322 | ||
323 | /* it's easy, since DSR2 is the only bit in the register */ | |
324 | if (status) | |
325 | dport->port.icount.dsr++; | |
326 | } | |
327 | ||
328 | /* | |
329 | * ------------------------------------------------------------ | |
330 | * dz_interrupt () | |
331 | * | |
332 | * this is the main interrupt routine for the DZ chip. | |
333 | * It deals with the multiple ports. | |
334 | * ------------------------------------------------------------ | |
335 | */ | |
e6ee512f | 336 | static irqreturn_t dz_interrupt(int irq, void *dev_id) |
1da177e4 | 337 | { |
e6ee512f MR |
338 | struct dz_mux *mux = dev_id; |
339 | struct dz_port *dport = &mux->dport[0]; | |
340 | u16 status; | |
1da177e4 LT |
341 | |
342 | /* get the reason why we just got an irq */ | |
9399575d | 343 | status = dz_in(dport, DZ_CSR); |
1da177e4 | 344 | |
9399575d | 345 | if ((status & (DZ_RDONE | DZ_RIE)) == (DZ_RDONE | DZ_RIE)) |
e6ee512f | 346 | dz_receive_chars(mux); |
1da177e4 | 347 | |
9399575d | 348 | if ((status & (DZ_TRDY | DZ_TIE)) == (DZ_TRDY | DZ_TIE)) |
e6ee512f | 349 | dz_transmit_chars(mux); |
1da177e4 | 350 | |
1da177e4 LT |
351 | return IRQ_HANDLED; |
352 | } | |
353 | ||
354 | /* | |
355 | * ------------------------------------------------------------------- | |
356 | * Here ends the DZ interrupt routines. | |
357 | * ------------------------------------------------------------------- | |
358 | */ | |
359 | ||
360 | static unsigned int dz_get_mctrl(struct uart_port *uport) | |
361 | { | |
9399575d MR |
362 | /* |
363 | * FIXME: Handle the 3100/5000 as appropriate. --macro | |
364 | */ | |
f5519caa | 365 | struct dz_port *dport = to_dport(uport); |
1da177e4 LT |
366 | unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; |
367 | ||
368 | if (dport->port.line == DZ_MODEM) { | |
1da177e4 LT |
369 | if (dz_in(dport, DZ_MSR) & DZ_MODEM_DSR) |
370 | mctrl &= ~TIOCM_DSR; | |
371 | } | |
372 | ||
373 | return mctrl; | |
374 | } | |
375 | ||
376 | static void dz_set_mctrl(struct uart_port *uport, unsigned int mctrl) | |
377 | { | |
9399575d MR |
378 | /* |
379 | * FIXME: Handle the 3100/5000 as appropriate. --macro | |
380 | */ | |
f5519caa | 381 | struct dz_port *dport = to_dport(uport); |
e6ee512f | 382 | u16 tmp; |
1da177e4 LT |
383 | |
384 | if (dport->port.line == DZ_MODEM) { | |
385 | tmp = dz_in(dport, DZ_TCR); | |
386 | if (mctrl & TIOCM_DTR) | |
387 | tmp &= ~DZ_MODEM_DTR; | |
388 | else | |
389 | tmp |= DZ_MODEM_DTR; | |
390 | dz_out(dport, DZ_TCR, tmp); | |
391 | } | |
392 | } | |
393 | ||
394 | /* | |
395 | * ------------------------------------------------------------------- | |
396 | * startup () | |
397 | * | |
398 | * various initialization tasks | |
fd8c5972 | 399 | * ------------------------------------------------------------------- |
1da177e4 LT |
400 | */ |
401 | static int dz_startup(struct uart_port *uport) | |
402 | { | |
f5519caa | 403 | struct dz_port *dport = to_dport(uport); |
e6ee512f | 404 | struct dz_mux *mux = dport->mux; |
1da177e4 | 405 | unsigned long flags; |
e6ee512f MR |
406 | int irq_guard; |
407 | int ret; | |
408 | u16 tmp; | |
409 | ||
410 | irq_guard = atomic_add_return(1, &mux->irq_guard); | |
411 | if (irq_guard != 1) | |
412 | return 0; | |
413 | ||
414 | ret = request_irq(dport->port.irq, dz_interrupt, | |
415 | IRQF_SHARED, "dz", mux); | |
416 | if (ret) { | |
417 | atomic_add(-1, &mux->irq_guard); | |
418 | printk(KERN_ERR "dz: Cannot get IRQ %d!\n", dport->port.irq); | |
419 | return ret; | |
420 | } | |
1da177e4 | 421 | |
1da177e4 LT |
422 | spin_lock_irqsave(&dport->port.lock, flags); |
423 | ||
e6ee512f | 424 | /* Enable interrupts. */ |
1da177e4 | 425 | tmp = dz_in(dport, DZ_CSR); |
e6ee512f | 426 | tmp |= DZ_RIE | DZ_TIE; |
1da177e4 LT |
427 | dz_out(dport, DZ_CSR, tmp); |
428 | ||
429 | spin_unlock_irqrestore(&dport->port.lock, flags); | |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
fd8c5972 | 434 | /* |
1da177e4 LT |
435 | * ------------------------------------------------------------------- |
436 | * shutdown () | |
437 | * | |
438 | * This routine will shutdown a serial port; interrupts are disabled, and | |
439 | * DTR is dropped if the hangup on close termio flag is on. | |
fd8c5972 | 440 | * ------------------------------------------------------------------- |
1da177e4 LT |
441 | */ |
442 | static void dz_shutdown(struct uart_port *uport) | |
443 | { | |
f5519caa | 444 | struct dz_port *dport = to_dport(uport); |
e6ee512f | 445 | struct dz_mux *mux = dport->mux; |
43d46ab1 | 446 | unsigned long flags; |
e6ee512f MR |
447 | int irq_guard; |
448 | u16 tmp; | |
43d46ab1 MR |
449 | |
450 | spin_lock_irqsave(&dport->port.lock, flags); | |
451 | dz_stop_tx(&dport->port); | |
452 | spin_unlock_irqrestore(&dport->port.lock, flags); | |
e6ee512f MR |
453 | |
454 | irq_guard = atomic_add_return(-1, &mux->irq_guard); | |
455 | if (!irq_guard) { | |
456 | /* Disable interrupts. */ | |
457 | tmp = dz_in(dport, DZ_CSR); | |
458 | tmp &= ~(DZ_RIE | DZ_TIE); | |
459 | dz_out(dport, DZ_CSR, tmp); | |
460 | ||
461 | free_irq(dport->port.irq, mux); | |
462 | } | |
1da177e4 LT |
463 | } |
464 | ||
465 | /* | |
9399575d MR |
466 | * ------------------------------------------------------------------- |
467 | * dz_tx_empty() -- get the transmitter empty status | |
1da177e4 LT |
468 | * |
469 | * Purpose: Let user call ioctl() to get info when the UART physically | |
470 | * is emptied. On bus types like RS485, the transmitter must | |
471 | * release the bus after transmitting. This must be done when | |
472 | * the transmit shift register is empty, not be done when the | |
473 | * transmit holding register is empty. This functionality | |
fd8c5972 | 474 | * allows an RS485 driver to be written in user space. |
9399575d | 475 | * ------------------------------------------------------------------- |
1da177e4 LT |
476 | */ |
477 | static unsigned int dz_tx_empty(struct uart_port *uport) | |
478 | { | |
f5519caa | 479 | struct dz_port *dport = to_dport(uport); |
9399575d | 480 | unsigned short tmp, mask = 1 << dport->port.line; |
1da177e4 | 481 | |
9399575d MR |
482 | tmp = dz_in(dport, DZ_TCR); |
483 | tmp &= mask; | |
484 | ||
485 | return tmp ? 0 : TIOCSER_TEMT; | |
1da177e4 LT |
486 | } |
487 | ||
488 | static void dz_break_ctl(struct uart_port *uport, int break_state) | |
489 | { | |
9399575d MR |
490 | /* |
491 | * FIXME: Can't access BREAK bits in TDR easily; | |
492 | * reuse the code for polled TX. --macro | |
493 | */ | |
f5519caa | 494 | struct dz_port *dport = to_dport(uport); |
1da177e4 | 495 | unsigned long flags; |
9399575d | 496 | unsigned short tmp, mask = 1 << dport->port.line; |
1da177e4 LT |
497 | |
498 | spin_lock_irqsave(&uport->lock, flags); | |
499 | tmp = dz_in(dport, DZ_TCR); | |
500 | if (break_state) | |
501 | tmp |= mask; | |
502 | else | |
503 | tmp &= ~mask; | |
504 | dz_out(dport, DZ_TCR, tmp); | |
505 | spin_unlock_irqrestore(&uport->lock, flags); | |
506 | } | |
507 | ||
ff11d078 MR |
508 | static int dz_encode_baud_rate(unsigned int baud) |
509 | { | |
510 | switch (baud) { | |
511 | case 50: | |
512 | return DZ_B50; | |
513 | case 75: | |
514 | return DZ_B75; | |
515 | case 110: | |
516 | return DZ_B110; | |
517 | case 134: | |
518 | return DZ_B134; | |
519 | case 150: | |
520 | return DZ_B150; | |
521 | case 300: | |
522 | return DZ_B300; | |
523 | case 600: | |
524 | return DZ_B600; | |
525 | case 1200: | |
526 | return DZ_B1200; | |
527 | case 1800: | |
528 | return DZ_B1800; | |
529 | case 2000: | |
530 | return DZ_B2000; | |
531 | case 2400: | |
532 | return DZ_B2400; | |
533 | case 3600: | |
534 | return DZ_B3600; | |
535 | case 4800: | |
536 | return DZ_B4800; | |
537 | case 7200: | |
538 | return DZ_B7200; | |
539 | case 9600: | |
540 | return DZ_B9600; | |
541 | default: | |
542 | return -1; | |
543 | } | |
544 | } | |
545 | ||
e6ee512f MR |
546 | |
547 | static void dz_reset(struct dz_port *dport) | |
548 | { | |
549 | struct dz_mux *mux = dport->mux; | |
550 | ||
551 | if (mux->initialised) | |
552 | return; | |
553 | ||
554 | dz_out(dport, DZ_CSR, DZ_CLR); | |
555 | while (dz_in(dport, DZ_CSR) & DZ_CLR); | |
556 | iob(); | |
557 | ||
558 | /* Enable scanning. */ | |
559 | dz_out(dport, DZ_CSR, DZ_MSE); | |
560 | ||
561 | mux->initialised = 1; | |
562 | } | |
563 | ||
606d099c AC |
564 | static void dz_set_termios(struct uart_port *uport, struct ktermios *termios, |
565 | struct ktermios *old_termios) | |
1da177e4 | 566 | { |
f5519caa | 567 | struct dz_port *dport = to_dport(uport); |
1da177e4 LT |
568 | unsigned long flags; |
569 | unsigned int cflag, baud; | |
ff11d078 | 570 | int bflag; |
1da177e4 LT |
571 | |
572 | cflag = dport->port.line; | |
573 | ||
574 | switch (termios->c_cflag & CSIZE) { | |
575 | case CS5: | |
576 | cflag |= DZ_CS5; | |
577 | break; | |
578 | case CS6: | |
579 | cflag |= DZ_CS6; | |
580 | break; | |
581 | case CS7: | |
582 | cflag |= DZ_CS7; | |
583 | break; | |
584 | case CS8: | |
585 | default: | |
586 | cflag |= DZ_CS8; | |
587 | } | |
588 | ||
589 | if (termios->c_cflag & CSTOPB) | |
590 | cflag |= DZ_CSTOPB; | |
591 | if (termios->c_cflag & PARENB) | |
592 | cflag |= DZ_PARENB; | |
593 | if (termios->c_cflag & PARODD) | |
594 | cflag |= DZ_PARODD; | |
595 | ||
596 | baud = uart_get_baud_rate(uport, termios, old_termios, 50, 9600); | |
ff11d078 MR |
597 | bflag = dz_encode_baud_rate(baud); |
598 | if (bflag < 0) { /* Try to keep unchanged. */ | |
599 | baud = uart_get_baud_rate(uport, old_termios, NULL, 50, 9600); | |
600 | bflag = dz_encode_baud_rate(baud); | |
601 | if (bflag < 0) { /* Resort to 9600. */ | |
602 | baud = 9600; | |
603 | bflag = DZ_B9600; | |
604 | } | |
605 | tty_termios_encode_baud_rate(termios, baud, baud); | |
1da177e4 | 606 | } |
ff11d078 | 607 | cflag |= bflag; |
1da177e4 LT |
608 | |
609 | if (termios->c_cflag & CREAD) | |
610 | cflag |= DZ_RXENAB; | |
611 | ||
612 | spin_lock_irqsave(&dport->port.lock, flags); | |
613 | ||
ff11d078 MR |
614 | uart_update_timeout(uport, termios->c_cflag, baud); |
615 | ||
616 | dz_out(dport, DZ_LPR, cflag); | |
1da177e4 LT |
617 | dport->cflag = cflag; |
618 | ||
619 | /* setup accept flag */ | |
620 | dport->port.read_status_mask = DZ_OERR; | |
621 | if (termios->c_iflag & INPCK) | |
622 | dport->port.read_status_mask |= DZ_FERR | DZ_PERR; | |
ef8b9ddc | 623 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
54c0f37e | 624 | dport->port.read_status_mask |= DZ_BREAK; |
1da177e4 LT |
625 | |
626 | /* characters to ignore */ | |
627 | uport->ignore_status_mask = 0; | |
54c0f37e MR |
628 | if ((termios->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK)) |
629 | dport->port.ignore_status_mask |= DZ_OERR; | |
1da177e4 LT |
630 | if (termios->c_iflag & IGNPAR) |
631 | dport->port.ignore_status_mask |= DZ_FERR | DZ_PERR; | |
54c0f37e MR |
632 | if (termios->c_iflag & IGNBRK) |
633 | dport->port.ignore_status_mask |= DZ_BREAK; | |
1da177e4 LT |
634 | |
635 | spin_unlock_irqrestore(&dport->port.lock, flags); | |
636 | } | |
637 | ||
e9a8f4d1 MR |
638 | /* |
639 | * Hack alert! | |
640 | * Required solely so that the initial PROM-based console | |
641 | * works undisturbed in parallel with this one. | |
642 | */ | |
643 | static void dz_pm(struct uart_port *uport, unsigned int state, | |
644 | unsigned int oldstate) | |
645 | { | |
646 | struct dz_port *dport = to_dport(uport); | |
647 | unsigned long flags; | |
648 | ||
649 | spin_lock_irqsave(&dport->port.lock, flags); | |
650 | if (state < 3) | |
651 | dz_start_tx(&dport->port); | |
652 | else | |
653 | dz_stop_tx(&dport->port); | |
654 | spin_unlock_irqrestore(&dport->port.lock, flags); | |
655 | } | |
656 | ||
657 | ||
e6ee512f | 658 | static const char *dz_type(struct uart_port *uport) |
1da177e4 LT |
659 | { |
660 | return "DZ"; | |
661 | } | |
662 | ||
e6ee512f | 663 | static void dz_release_port(struct uart_port *uport) |
1da177e4 | 664 | { |
e6ee512f MR |
665 | struct dz_mux *mux = to_dport(uport)->mux; |
666 | int map_guard; | |
667 | ||
668 | iounmap(uport->membase); | |
669 | uport->membase = NULL; | |
670 | ||
671 | map_guard = atomic_add_return(-1, &mux->map_guard); | |
672 | if (!map_guard) | |
673 | release_mem_region(uport->mapbase, dec_kn_slot_size); | |
1da177e4 LT |
674 | } |
675 | ||
e6ee512f | 676 | static int dz_map_port(struct uart_port *uport) |
1da177e4 | 677 | { |
e6ee512f MR |
678 | if (!uport->membase) |
679 | uport->membase = ioremap_nocache(uport->mapbase, | |
680 | dec_kn_slot_size); | |
681 | if (!uport->membase) { | |
682 | printk(KERN_ERR "dz: Cannot map MMIO\n"); | |
683 | return -ENOMEM; | |
684 | } | |
1da177e4 LT |
685 | return 0; |
686 | } | |
687 | ||
e6ee512f | 688 | static int dz_request_port(struct uart_port *uport) |
1da177e4 | 689 | { |
e6ee512f MR |
690 | struct dz_mux *mux = to_dport(uport)->mux; |
691 | int map_guard; | |
692 | int ret; | |
693 | ||
694 | map_guard = atomic_add_return(1, &mux->map_guard); | |
695 | if (map_guard == 1) { | |
696 | if (!request_mem_region(uport->mapbase, dec_kn_slot_size, | |
697 | "dz")) { | |
698 | atomic_add(-1, &mux->map_guard); | |
699 | printk(KERN_ERR | |
700 | "dz: Unable to reserve MMIO resource\n"); | |
701 | return -EBUSY; | |
702 | } | |
703 | } | |
704 | ret = dz_map_port(uport); | |
705 | if (ret) { | |
706 | map_guard = atomic_add_return(-1, &mux->map_guard); | |
707 | if (!map_guard) | |
708 | release_mem_region(uport->mapbase, dec_kn_slot_size); | |
709 | return ret; | |
710 | } | |
711 | return 0; | |
712 | } | |
713 | ||
714 | static void dz_config_port(struct uart_port *uport, int flags) | |
715 | { | |
716 | struct dz_port *dport = to_dport(uport); | |
717 | ||
718 | if (flags & UART_CONFIG_TYPE) { | |
719 | if (dz_request_port(uport)) | |
720 | return; | |
721 | ||
722 | uport->type = PORT_DZ; | |
723 | ||
724 | dz_reset(dport); | |
725 | } | |
1da177e4 LT |
726 | } |
727 | ||
728 | /* | |
e6ee512f | 729 | * Verify the new serial_struct (for TIOCSSERIAL). |
1da177e4 | 730 | */ |
e6ee512f | 731 | static int dz_verify_port(struct uart_port *uport, struct serial_struct *ser) |
1da177e4 LT |
732 | { |
733 | int ret = 0; | |
e6ee512f | 734 | |
1da177e4 LT |
735 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_DZ) |
736 | ret = -EINVAL; | |
e6ee512f | 737 | if (ser->irq != uport->irq) |
1da177e4 LT |
738 | ret = -EINVAL; |
739 | return ret; | |
740 | } | |
741 | ||
742 | static struct uart_ops dz_ops = { | |
743 | .tx_empty = dz_tx_empty, | |
744 | .get_mctrl = dz_get_mctrl, | |
745 | .set_mctrl = dz_set_mctrl, | |
746 | .stop_tx = dz_stop_tx, | |
747 | .start_tx = dz_start_tx, | |
748 | .stop_rx = dz_stop_rx, | |
1da177e4 LT |
749 | .break_ctl = dz_break_ctl, |
750 | .startup = dz_startup, | |
751 | .shutdown = dz_shutdown, | |
752 | .set_termios = dz_set_termios, | |
e9a8f4d1 | 753 | .pm = dz_pm, |
1da177e4 LT |
754 | .type = dz_type, |
755 | .release_port = dz_release_port, | |
756 | .request_port = dz_request_port, | |
757 | .config_port = dz_config_port, | |
758 | .verify_port = dz_verify_port, | |
759 | }; | |
760 | ||
761 | static void __init dz_init_ports(void) | |
762 | { | |
763 | static int first = 1; | |
1da177e4 | 764 | unsigned long base; |
e6ee512f | 765 | int line; |
1da177e4 LT |
766 | |
767 | if (!first) | |
768 | return; | |
769 | first = 0; | |
770 | ||
e6ee512f MR |
771 | if (mips_machtype == MACH_DS23100 || mips_machtype == MACH_DS5100) |
772 | base = dec_kn_slot_base + KN01_DZ11; | |
1da177e4 | 773 | else |
e6ee512f | 774 | base = dec_kn_slot_base + KN02_DZ11; |
1da177e4 | 775 | |
e6ee512f MR |
776 | for (line = 0; line < DZ_NB_PORT; line++) { |
777 | struct dz_port *dport = &dz_mux.dport[line]; | |
778 | struct uart_port *uport = &dport->port; | |
1da177e4 | 779 | |
e6ee512f MR |
780 | dport->mux = &dz_mux; |
781 | ||
782 | uport->irq = dec_interrupt[DEC_IRQ_DZ11]; | |
783 | uport->fifosize = 1; | |
784 | uport->iotype = UPIO_MEM; | |
785 | uport->flags = UPF_BOOT_AUTOCONF; | |
786 | uport->ops = &dz_ops; | |
787 | uport->line = line; | |
788 | uport->mapbase = base; | |
789 | } | |
1da177e4 LT |
790 | } |
791 | ||
792 | #ifdef CONFIG_SERIAL_DZ_CONSOLE | |
9399575d MR |
793 | /* |
794 | * ------------------------------------------------------------------- | |
795 | * dz_console_putchar() -- transmit a character | |
796 | * | |
797 | * Polled transmission. This is tricky. We need to mask transmit | |
798 | * interrupts so that they do not interfere, enable the transmitter | |
799 | * for the line requested and then wait till the transmit scanner | |
800 | * requests data for this line. But it may request data for another | |
801 | * line first, in which case we have to disable its transmitter and | |
802 | * repeat waiting till our line pops up. Only then the character may | |
803 | * be transmitted. Finally, the state of the transmitter mask is | |
804 | * restored. Welcome to the world of PDP-11! | |
805 | * ------------------------------------------------------------------- | |
806 | */ | |
d608ab99 | 807 | static void dz_console_putchar(struct uart_port *uport, int ch) |
1da177e4 | 808 | { |
f5519caa | 809 | struct dz_port *dport = to_dport(uport); |
1da177e4 | 810 | unsigned long flags; |
9399575d MR |
811 | unsigned short csr, tcr, trdy, mask; |
812 | int loops = 10000; | |
1da177e4 LT |
813 | |
814 | spin_lock_irqsave(&dport->port.lock, flags); | |
9399575d MR |
815 | csr = dz_in(dport, DZ_CSR); |
816 | dz_out(dport, DZ_CSR, csr & ~DZ_TIE); | |
817 | tcr = dz_in(dport, DZ_TCR); | |
818 | tcr |= 1 << dport->port.line; | |
819 | mask = tcr; | |
820 | dz_out(dport, DZ_TCR, mask); | |
821 | iob(); | |
822 | spin_unlock_irqrestore(&dport->port.lock, flags); | |
1da177e4 | 823 | |
dbab8128 | 824 | do { |
9399575d MR |
825 | trdy = dz_in(dport, DZ_CSR); |
826 | if (!(trdy & DZ_TRDY)) | |
827 | continue; | |
828 | trdy = (trdy & DZ_TLINE) >> 8; | |
829 | if (trdy == dport->port.line) | |
830 | break; | |
831 | mask &= ~(1 << trdy); | |
832 | dz_out(dport, DZ_TCR, mask); | |
833 | iob(); | |
834 | udelay(2); | |
1ecf0d0c | 835 | } while (--loops); |
1da177e4 | 836 | |
9399575d MR |
837 | if (loops) /* Cannot send otherwise. */ |
838 | dz_out(dport, DZ_TDR, ch); | |
1da177e4 | 839 | |
9399575d MR |
840 | dz_out(dport, DZ_TCR, tcr); |
841 | dz_out(dport, DZ_CSR, csr); | |
1da177e4 | 842 | } |
d358788f | 843 | |
fd8c5972 | 844 | /* |
1da177e4 LT |
845 | * ------------------------------------------------------------------- |
846 | * dz_console_print () | |
847 | * | |
848 | * dz_console_print is registered for printk. | |
849 | * The console must be locked when we get here. | |
fd8c5972 | 850 | * ------------------------------------------------------------------- |
1da177e4 | 851 | */ |
9399575d | 852 | static void dz_console_print(struct console *co, |
1da177e4 LT |
853 | const char *str, |
854 | unsigned int count) | |
855 | { | |
e6ee512f | 856 | struct dz_port *dport = &dz_mux.dport[co->index]; |
1da177e4 LT |
857 | #ifdef DEBUG_DZ |
858 | prom_printf((char *) str); | |
859 | #endif | |
d358788f | 860 | uart_console_write(&dport->port, str, count, dz_console_putchar); |
1da177e4 LT |
861 | } |
862 | ||
863 | static int __init dz_console_setup(struct console *co, char *options) | |
864 | { | |
e6ee512f MR |
865 | struct dz_port *dport = &dz_mux.dport[co->index]; |
866 | struct uart_port *uport = &dport->port; | |
1da177e4 LT |
867 | int baud = 9600; |
868 | int bits = 8; | |
869 | int parity = 'n'; | |
870 | int flow = 'n'; | |
e6ee512f | 871 | int ret; |
1da177e4 | 872 | |
e6ee512f MR |
873 | ret = dz_map_port(uport); |
874 | if (ret) | |
875 | return ret; | |
1da177e4 | 876 | |
e9a8f4d1 MR |
877 | spin_lock_init(&dport->port.lock); /* For dz_pm(). */ |
878 | ||
1da177e4 | 879 | dz_reset(dport); |
e9a8f4d1 | 880 | dz_pm(uport, 0, -1); |
1da177e4 | 881 | |
e6ee512f MR |
882 | if (options) |
883 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
884 | ||
9399575d | 885 | return uart_set_options(&dport->port, co, baud, parity, bits, flow); |
1da177e4 LT |
886 | } |
887 | ||
9399575d | 888 | static struct uart_driver dz_reg; |
6d83c067 | 889 | static struct console dz_console = { |
1da177e4 LT |
890 | .name = "ttyS", |
891 | .write = dz_console_print, | |
892 | .device = uart_console_device, | |
893 | .setup = dz_console_setup, | |
9399575d MR |
894 | .flags = CON_PRINTBUFFER, |
895 | .index = -1, | |
896 | .data = &dz_reg, | |
1da177e4 LT |
897 | }; |
898 | ||
9399575d | 899 | static int __init dz_serial_console_init(void) |
1da177e4 | 900 | { |
9399575d MR |
901 | if (!IOASIC) { |
902 | dz_init_ports(); | |
6d83c067 | 903 | register_console(&dz_console); |
9399575d MR |
904 | return 0; |
905 | } else | |
906 | return -ENXIO; | |
1da177e4 LT |
907 | } |
908 | ||
9399575d MR |
909 | console_initcall(dz_serial_console_init); |
910 | ||
6d83c067 | 911 | #define SERIAL_DZ_CONSOLE &dz_console |
1da177e4 LT |
912 | #else |
913 | #define SERIAL_DZ_CONSOLE NULL | |
914 | #endif /* CONFIG_SERIAL_DZ_CONSOLE */ | |
915 | ||
916 | static struct uart_driver dz_reg = { | |
917 | .owner = THIS_MODULE, | |
918 | .driver_name = "serial", | |
9399575d | 919 | .dev_name = "ttyS", |
1da177e4 LT |
920 | .major = TTY_MAJOR, |
921 | .minor = 64, | |
922 | .nr = DZ_NB_PORT, | |
923 | .cons = SERIAL_DZ_CONSOLE, | |
924 | }; | |
925 | ||
9399575d | 926 | static int __init dz_init(void) |
1da177e4 | 927 | { |
1da177e4 LT |
928 | int ret, i; |
929 | ||
9399575d MR |
930 | if (IOASIC) |
931 | return -ENXIO; | |
932 | ||
1da177e4 LT |
933 | printk("%s%s\n", dz_name, dz_version); |
934 | ||
935 | dz_init_ports(); | |
936 | ||
1da177e4 | 937 | ret = uart_register_driver(&dz_reg); |
e6ee512f MR |
938 | if (ret) |
939 | return ret; | |
1da177e4 LT |
940 | |
941 | for (i = 0; i < DZ_NB_PORT; i++) | |
e6ee512f | 942 | uart_add_one_port(&dz_reg, &dz_mux.dport[i].port); |
0ba137e2 | 943 | |
e6ee512f | 944 | return 0; |
1da177e4 LT |
945 | } |
946 | ||
9399575d | 947 | module_init(dz_init); |