Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for Motorola IMX serial ports |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * | |
6 | * Author: Sascha Hauer <sascha@saschahauer.de> | |
7 | * Copyright (C) 2004 Pengutronix | |
8 | * | |
b6e49138 FG |
9 | * Copyright (C) 2009 emlix GmbH |
10 | * Author: Fabian Godehardt (added IrDA support for iMX) | |
11 | * | |
1da177e4 LT |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | * | |
26 | * [29-Mar-2005] Mike Lee | |
27 | * Added hardware handshake | |
28 | */ | |
1da177e4 LT |
29 | |
30 | #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
31 | #define SUPPORT_SYSRQ | |
32 | #endif | |
33 | ||
34 | #include <linux/module.h> | |
35 | #include <linux/ioport.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/console.h> | |
38 | #include <linux/sysrq.h> | |
d052d1be | 39 | #include <linux/platform_device.h> |
1da177e4 LT |
40 | #include <linux/tty.h> |
41 | #include <linux/tty_flip.h> | |
42 | #include <linux/serial_core.h> | |
43 | #include <linux/serial.h> | |
38a41fdf | 44 | #include <linux/clk.h> |
b6e49138 | 45 | #include <linux/delay.h> |
534fca06 | 46 | #include <linux/rational.h> |
5a0e3ad6 | 47 | #include <linux/slab.h> |
22698aa2 SG |
48 | #include <linux/of.h> |
49 | #include <linux/of_device.h> | |
e32a9f8f | 50 | #include <linux/io.h> |
1da177e4 | 51 | |
1da177e4 | 52 | #include <asm/irq.h> |
82906b13 | 53 | #include <linux/platform_data/serial-imx.h> |
1da177e4 | 54 | |
ff4bfb21 SH |
55 | /* Register definitions */ |
56 | #define URXD0 0x0 /* Receiver Register */ | |
57 | #define URTX0 0x40 /* Transmitter Register */ | |
58 | #define UCR1 0x80 /* Control Register 1 */ | |
59 | #define UCR2 0x84 /* Control Register 2 */ | |
60 | #define UCR3 0x88 /* Control Register 3 */ | |
61 | #define UCR4 0x8c /* Control Register 4 */ | |
62 | #define UFCR 0x90 /* FIFO Control Register */ | |
63 | #define USR1 0x94 /* Status Register 1 */ | |
64 | #define USR2 0x98 /* Status Register 2 */ | |
65 | #define UESC 0x9c /* Escape Character Register */ | |
66 | #define UTIM 0xa0 /* Escape Timer Register */ | |
67 | #define UBIR 0xa4 /* BRM Incremental Register */ | |
68 | #define UBMR 0xa8 /* BRM Modulator Register */ | |
69 | #define UBRC 0xac /* Baud Rate Count Register */ | |
fe6b540a SG |
70 | #define IMX21_ONEMS 0xb0 /* One Millisecond register */ |
71 | #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ | |
72 | #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ | |
ff4bfb21 SH |
73 | |
74 | /* UART Control Register Bit Fields.*/ | |
82313e66 SK |
75 | #define URXD_CHARRDY (1<<15) |
76 | #define URXD_ERR (1<<14) | |
77 | #define URXD_OVRRUN (1<<13) | |
78 | #define URXD_FRMERR (1<<12) | |
79 | #define URXD_BRK (1<<11) | |
80 | #define URXD_PRERR (1<<10) | |
81 | #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ | |
82 | #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ | |
83 | #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ | |
84 | #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ | |
85 | #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ | |
86 | #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ | |
87 | #define UCR1_IREN (1<<7) /* Infrared interface enable */ | |
88 | #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ | |
89 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ | |
90 | #define UCR1_SNDBRK (1<<4) /* Send break */ | |
91 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ | |
92 | #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ | |
93 | #define UCR1_DOZE (1<<1) /* Doze */ | |
94 | #define UCR1_UARTEN (1<<0) /* UART enabled */ | |
95 | #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ | |
96 | #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ | |
97 | #define UCR2_CTSC (1<<13) /* CTS pin control */ | |
98 | #define UCR2_CTS (1<<12) /* Clear to send */ | |
99 | #define UCR2_ESCEN (1<<11) /* Escape enable */ | |
100 | #define UCR2_PREN (1<<8) /* Parity enable */ | |
101 | #define UCR2_PROE (1<<7) /* Parity odd/even */ | |
102 | #define UCR2_STPB (1<<6) /* Stop */ | |
103 | #define UCR2_WS (1<<5) /* Word size */ | |
104 | #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ | |
105 | #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ | |
106 | #define UCR2_TXEN (1<<2) /* Transmitter enabled */ | |
107 | #define UCR2_RXEN (1<<1) /* Receiver enabled */ | |
108 | #define UCR2_SRST (1<<0) /* SW reset */ | |
109 | #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ | |
110 | #define UCR3_PARERREN (1<<12) /* Parity enable */ | |
111 | #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ | |
112 | #define UCR3_DSR (1<<10) /* Data set ready */ | |
113 | #define UCR3_DCD (1<<9) /* Data carrier detect */ | |
114 | #define UCR3_RI (1<<8) /* Ring indicator */ | |
115 | #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ | |
116 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ | |
117 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ | |
118 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ | |
119 | #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ | |
120 | #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ | |
121 | #define UCR3_BPEN (1<<0) /* Preset registers enable */ | |
122 | #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ | |
123 | #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ | |
124 | #define UCR4_INVR (1<<9) /* Inverted infrared reception */ | |
125 | #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ | |
126 | #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ | |
127 | #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ | |
128 | #define UCR4_IRSC (1<<5) /* IR special case */ | |
129 | #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ | |
130 | #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ | |
131 | #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ | |
132 | #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ | |
133 | #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ | |
134 | #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ | |
135 | #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ | |
136 | #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) | |
137 | #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ | |
138 | #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ | |
139 | #define USR1_RTSS (1<<14) /* RTS pin status */ | |
140 | #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ | |
141 | #define USR1_RTSD (1<<12) /* RTS delta */ | |
142 | #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ | |
143 | #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ | |
144 | #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ | |
145 | #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ | |
146 | #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ | |
147 | #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ | |
148 | #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ | |
149 | #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ | |
150 | #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ | |
151 | #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ | |
152 | #define USR2_IDLE (1<<12) /* Idle condition */ | |
153 | #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ | |
154 | #define USR2_WAKE (1<<7) /* Wake */ | |
155 | #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ | |
156 | #define USR2_TXDC (1<<3) /* Transmitter complete */ | |
157 | #define USR2_BRCD (1<<2) /* Break condition */ | |
158 | #define USR2_ORE (1<<1) /* Overrun error */ | |
159 | #define USR2_RDR (1<<0) /* Recv data ready */ | |
160 | #define UTS_FRCPERR (1<<13) /* Force parity error */ | |
161 | #define UTS_LOOP (1<<12) /* Loop tx and rx */ | |
162 | #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ | |
163 | #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ | |
164 | #define UTS_TXFULL (1<<4) /* TxFIFO full */ | |
165 | #define UTS_RXFULL (1<<3) /* RxFIFO full */ | |
166 | #define UTS_SOFTRST (1<<0) /* Software reset */ | |
ff4bfb21 | 167 | |
1da177e4 | 168 | /* We've been assigned a range on the "Low-density serial ports" major */ |
82313e66 SK |
169 | #define SERIAL_IMX_MAJOR 207 |
170 | #define MINOR_START 16 | |
e3d13ff4 | 171 | #define DEV_NAME "ttymxc" |
1da177e4 | 172 | |
1da177e4 LT |
173 | /* |
174 | * This determines how often we check the modem status signals | |
175 | * for any change. They generally aren't connected to an IRQ | |
176 | * so we have to poll them. We also check immediately before | |
177 | * filling the TX fifo incase CTS has been dropped. | |
178 | */ | |
179 | #define MCTRL_TIMEOUT (250*HZ/1000) | |
180 | ||
181 | #define DRIVER_NAME "IMX-uart" | |
182 | ||
dbff4e9e SH |
183 | #define UART_NR 8 |
184 | ||
fe6b540a SG |
185 | /* i.mx21 type uart runs on all i.mx except i.mx1 */ |
186 | enum imx_uart_type { | |
187 | IMX1_UART, | |
188 | IMX21_UART, | |
189 | }; | |
190 | ||
191 | /* device type dependent stuff */ | |
192 | struct imx_uart_data { | |
193 | unsigned uts_reg; | |
194 | enum imx_uart_type devtype; | |
195 | }; | |
196 | ||
1da177e4 LT |
197 | struct imx_port { |
198 | struct uart_port port; | |
199 | struct timer_list timer; | |
200 | unsigned int old_status; | |
82313e66 | 201 | int txirq, rxirq, rtsirq; |
26bbb3ff | 202 | unsigned int have_rtscts:1; |
20ff2fe6 | 203 | unsigned int dte_mode:1; |
b6e49138 FG |
204 | unsigned int use_irda:1; |
205 | unsigned int irda_inv_rx:1; | |
206 | unsigned int irda_inv_tx:1; | |
207 | unsigned short trcv_delay; /* transceiver delay */ | |
3a9465fa SH |
208 | struct clk *clk_ipg; |
209 | struct clk *clk_per; | |
7d0b066f | 210 | const struct imx_uart_data *devdata; |
1da177e4 LT |
211 | }; |
212 | ||
0ad5a814 DB |
213 | struct imx_port_ucrs { |
214 | unsigned int ucr1; | |
215 | unsigned int ucr2; | |
216 | unsigned int ucr3; | |
217 | }; | |
218 | ||
b6e49138 FG |
219 | #ifdef CONFIG_IRDA |
220 | #define USE_IRDA(sport) ((sport)->use_irda) | |
221 | #else | |
222 | #define USE_IRDA(sport) (0) | |
223 | #endif | |
224 | ||
fe6b540a SG |
225 | static struct imx_uart_data imx_uart_devdata[] = { |
226 | [IMX1_UART] = { | |
227 | .uts_reg = IMX1_UTS, | |
228 | .devtype = IMX1_UART, | |
229 | }, | |
230 | [IMX21_UART] = { | |
231 | .uts_reg = IMX21_UTS, | |
232 | .devtype = IMX21_UART, | |
233 | }, | |
234 | }; | |
235 | ||
236 | static struct platform_device_id imx_uart_devtype[] = { | |
237 | { | |
238 | .name = "imx1-uart", | |
239 | .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], | |
240 | }, { | |
241 | .name = "imx21-uart", | |
242 | .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], | |
243 | }, { | |
244 | /* sentinel */ | |
245 | } | |
246 | }; | |
247 | MODULE_DEVICE_TABLE(platform, imx_uart_devtype); | |
248 | ||
22698aa2 SG |
249 | static struct of_device_id imx_uart_dt_ids[] = { |
250 | { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, | |
251 | { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, | |
252 | { /* sentinel */ } | |
253 | }; | |
254 | MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); | |
255 | ||
fe6b540a SG |
256 | static inline unsigned uts_reg(struct imx_port *sport) |
257 | { | |
258 | return sport->devdata->uts_reg; | |
259 | } | |
260 | ||
261 | static inline int is_imx1_uart(struct imx_port *sport) | |
262 | { | |
263 | return sport->devdata->devtype == IMX1_UART; | |
264 | } | |
265 | ||
266 | static inline int is_imx21_uart(struct imx_port *sport) | |
267 | { | |
268 | return sport->devdata->devtype == IMX21_UART; | |
269 | } | |
270 | ||
44a75411 | 271 | /* |
272 | * Save and restore functions for UCR1, UCR2 and UCR3 registers | |
273 | */ | |
e8bfa760 | 274 | #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_IMX_CONSOLE) |
44a75411 | 275 | static void imx_port_ucrs_save(struct uart_port *port, |
276 | struct imx_port_ucrs *ucr) | |
277 | { | |
278 | /* save control registers */ | |
279 | ucr->ucr1 = readl(port->membase + UCR1); | |
280 | ucr->ucr2 = readl(port->membase + UCR2); | |
281 | ucr->ucr3 = readl(port->membase + UCR3); | |
282 | } | |
283 | ||
284 | static void imx_port_ucrs_restore(struct uart_port *port, | |
285 | struct imx_port_ucrs *ucr) | |
286 | { | |
287 | /* restore control registers */ | |
288 | writel(ucr->ucr1, port->membase + UCR1); | |
289 | writel(ucr->ucr2, port->membase + UCR2); | |
290 | writel(ucr->ucr3, port->membase + UCR3); | |
291 | } | |
e8bfa760 | 292 | #endif |
44a75411 | 293 | |
1da177e4 LT |
294 | /* |
295 | * Handle any change of modem status signal since we were last called. | |
296 | */ | |
297 | static void imx_mctrl_check(struct imx_port *sport) | |
298 | { | |
299 | unsigned int status, changed; | |
300 | ||
301 | status = sport->port.ops->get_mctrl(&sport->port); | |
302 | changed = status ^ sport->old_status; | |
303 | ||
304 | if (changed == 0) | |
305 | return; | |
306 | ||
307 | sport->old_status = status; | |
308 | ||
309 | if (changed & TIOCM_RI) | |
310 | sport->port.icount.rng++; | |
311 | if (changed & TIOCM_DSR) | |
312 | sport->port.icount.dsr++; | |
313 | if (changed & TIOCM_CAR) | |
314 | uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); | |
315 | if (changed & TIOCM_CTS) | |
316 | uart_handle_cts_change(&sport->port, status & TIOCM_CTS); | |
317 | ||
bdc04e31 | 318 | wake_up_interruptible(&sport->port.state->port.delta_msr_wait); |
1da177e4 LT |
319 | } |
320 | ||
321 | /* | |
322 | * This is our per-port timeout handler, for checking the | |
323 | * modem status signals. | |
324 | */ | |
325 | static void imx_timeout(unsigned long data) | |
326 | { | |
327 | struct imx_port *sport = (struct imx_port *)data; | |
328 | unsigned long flags; | |
329 | ||
ebd2c8f6 | 330 | if (sport->port.state) { |
1da177e4 LT |
331 | spin_lock_irqsave(&sport->port.lock, flags); |
332 | imx_mctrl_check(sport); | |
333 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
334 | ||
335 | mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); | |
336 | } | |
337 | } | |
338 | ||
339 | /* | |
340 | * interrupts disabled on entry | |
341 | */ | |
b129a8cc | 342 | static void imx_stop_tx(struct uart_port *port) |
1da177e4 LT |
343 | { |
344 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 SH |
345 | unsigned long temp; |
346 | ||
b6e49138 FG |
347 | if (USE_IRDA(sport)) { |
348 | /* half duplex - wait for end of transmission */ | |
349 | int n = 256; | |
350 | while ((--n > 0) && | |
351 | !(readl(sport->port.membase + USR2) & USR2_TXDC)) { | |
352 | udelay(5); | |
353 | barrier(); | |
354 | } | |
355 | /* | |
356 | * irda transceiver - wait a bit more to avoid | |
357 | * cutoff, hardware dependent | |
358 | */ | |
359 | udelay(sport->trcv_delay); | |
360 | ||
361 | /* | |
362 | * half duplex - reactivate receive mode, | |
363 | * flush receive pipe echo crap | |
364 | */ | |
365 | if (readl(sport->port.membase + USR2) & USR2_TXDC) { | |
366 | temp = readl(sport->port.membase + UCR1); | |
367 | temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN); | |
368 | writel(temp, sport->port.membase + UCR1); | |
369 | ||
370 | temp = readl(sport->port.membase + UCR4); | |
371 | temp &= ~(UCR4_TCEN); | |
372 | writel(temp, sport->port.membase + UCR4); | |
373 | ||
374 | while (readl(sport->port.membase + URXD0) & | |
375 | URXD_CHARRDY) | |
376 | barrier(); | |
377 | ||
378 | temp = readl(sport->port.membase + UCR1); | |
379 | temp |= UCR1_RRDYEN; | |
380 | writel(temp, sport->port.membase + UCR1); | |
381 | ||
382 | temp = readl(sport->port.membase + UCR4); | |
383 | temp |= UCR4_DREN; | |
384 | writel(temp, sport->port.membase + UCR4); | |
385 | } | |
386 | return; | |
387 | } | |
388 | ||
ff4bfb21 SH |
389 | temp = readl(sport->port.membase + UCR1); |
390 | writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1); | |
1da177e4 LT |
391 | } |
392 | ||
393 | /* | |
394 | * interrupts disabled on entry | |
395 | */ | |
396 | static void imx_stop_rx(struct uart_port *port) | |
397 | { | |
398 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 SH |
399 | unsigned long temp; |
400 | ||
401 | temp = readl(sport->port.membase + UCR2); | |
82313e66 | 402 | writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); |
1da177e4 LT |
403 | } |
404 | ||
405 | /* | |
406 | * Set the modem control timer to fire immediately. | |
407 | */ | |
408 | static void imx_enable_ms(struct uart_port *port) | |
409 | { | |
410 | struct imx_port *sport = (struct imx_port *)port; | |
411 | ||
412 | mod_timer(&sport->timer, jiffies); | |
413 | } | |
414 | ||
415 | static inline void imx_transmit_buffer(struct imx_port *sport) | |
416 | { | |
ebd2c8f6 | 417 | struct circ_buf *xmit = &sport->port.state->xmit; |
1da177e4 | 418 | |
4e4e6602 | 419 | while (!uart_circ_empty(xmit) && |
fe6b540a SG |
420 | !(readl(sport->port.membase + uts_reg(sport)) |
421 | & UTS_TXFULL)) { | |
1da177e4 LT |
422 | /* send xmit->buf[xmit->tail] |
423 | * out the port here */ | |
ff4bfb21 | 424 | writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); |
d3810cd4 | 425 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
1da177e4 | 426 | sport->port.icount.tx++; |
8c0b254b | 427 | } |
1da177e4 | 428 | |
97775731 FG |
429 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
430 | uart_write_wakeup(&sport->port); | |
431 | ||
1da177e4 | 432 | if (uart_circ_empty(xmit)) |
b129a8cc | 433 | imx_stop_tx(&sport->port); |
1da177e4 LT |
434 | } |
435 | ||
436 | /* | |
437 | * interrupts disabled on entry | |
438 | */ | |
b129a8cc | 439 | static void imx_start_tx(struct uart_port *port) |
1da177e4 LT |
440 | { |
441 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 | 442 | unsigned long temp; |
1da177e4 | 443 | |
b6e49138 FG |
444 | if (USE_IRDA(sport)) { |
445 | /* half duplex in IrDA mode; have to disable receive mode */ | |
446 | temp = readl(sport->port.membase + UCR4); | |
447 | temp &= ~(UCR4_DREN); | |
448 | writel(temp, sport->port.membase + UCR4); | |
449 | ||
450 | temp = readl(sport->port.membase + UCR1); | |
451 | temp &= ~(UCR1_RRDYEN); | |
452 | writel(temp, sport->port.membase + UCR1); | |
453 | } | |
f1f836e4 AS |
454 | /* Clear any pending ORE flag before enabling interrupt */ |
455 | temp = readl(sport->port.membase + USR2); | |
456 | writel(temp | USR2_ORE, sport->port.membase + USR2); | |
457 | ||
458 | temp = readl(sport->port.membase + UCR4); | |
459 | temp |= UCR4_OREN; | |
460 | writel(temp, sport->port.membase + UCR4); | |
b6e49138 | 461 | |
ff4bfb21 SH |
462 | temp = readl(sport->port.membase + UCR1); |
463 | writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); | |
1da177e4 | 464 | |
b6e49138 FG |
465 | if (USE_IRDA(sport)) { |
466 | temp = readl(sport->port.membase + UCR1); | |
467 | temp |= UCR1_TRDYEN; | |
468 | writel(temp, sport->port.membase + UCR1); | |
469 | ||
470 | temp = readl(sport->port.membase + UCR4); | |
471 | temp |= UCR4_TCEN; | |
472 | writel(temp, sport->port.membase + UCR4); | |
473 | } | |
474 | ||
fe6b540a | 475 | if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY) |
ff4bfb21 | 476 | imx_transmit_buffer(sport); |
1da177e4 LT |
477 | } |
478 | ||
7d12e780 | 479 | static irqreturn_t imx_rtsint(int irq, void *dev_id) |
ceca629e | 480 | { |
15aafa2f | 481 | struct imx_port *sport = dev_id; |
5680e941 | 482 | unsigned int val; |
ceca629e SH |
483 | unsigned long flags; |
484 | ||
485 | spin_lock_irqsave(&sport->port.lock, flags); | |
486 | ||
ff4bfb21 | 487 | writel(USR1_RTSD, sport->port.membase + USR1); |
5680e941 | 488 | val = readl(sport->port.membase + USR1) & USR1_RTSS; |
ceca629e | 489 | uart_handle_cts_change(&sport->port, !!val); |
bdc04e31 | 490 | wake_up_interruptible(&sport->port.state->port.delta_msr_wait); |
ceca629e SH |
491 | |
492 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
493 | return IRQ_HANDLED; | |
494 | } | |
495 | ||
7d12e780 | 496 | static irqreturn_t imx_txint(int irq, void *dev_id) |
1da177e4 | 497 | { |
15aafa2f | 498 | struct imx_port *sport = dev_id; |
ebd2c8f6 | 499 | struct circ_buf *xmit = &sport->port.state->xmit; |
1da177e4 LT |
500 | unsigned long flags; |
501 | ||
82313e66 | 502 | spin_lock_irqsave(&sport->port.lock, flags); |
699cbd67 | 503 | if (sport->port.x_char) { |
1da177e4 | 504 | /* Send next char */ |
ff4bfb21 | 505 | writel(sport->port.x_char, sport->port.membase + URTX0); |
1da177e4 LT |
506 | goto out; |
507 | } | |
508 | ||
509 | if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { | |
b129a8cc | 510 | imx_stop_tx(&sport->port); |
1da177e4 LT |
511 | goto out; |
512 | } | |
513 | ||
514 | imx_transmit_buffer(sport); | |
515 | ||
516 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
517 | uart_write_wakeup(&sport->port); | |
518 | ||
519 | out: | |
82313e66 | 520 | spin_unlock_irqrestore(&sport->port.lock, flags); |
1da177e4 LT |
521 | return IRQ_HANDLED; |
522 | } | |
523 | ||
7d12e780 | 524 | static irqreturn_t imx_rxint(int irq, void *dev_id) |
1da177e4 LT |
525 | { |
526 | struct imx_port *sport = dev_id; | |
82313e66 | 527 | unsigned int rx, flg, ignored = 0; |
92a19f9c | 528 | struct tty_port *port = &sport->port.state->port; |
ff4bfb21 | 529 | unsigned long flags, temp; |
1da177e4 | 530 | |
82313e66 | 531 | spin_lock_irqsave(&sport->port.lock, flags); |
1da177e4 | 532 | |
0d3c3938 | 533 | while (readl(sport->port.membase + USR2) & USR2_RDR) { |
1da177e4 LT |
534 | flg = TTY_NORMAL; |
535 | sport->port.icount.rx++; | |
536 | ||
0d3c3938 SH |
537 | rx = readl(sport->port.membase + URXD0); |
538 | ||
ff4bfb21 | 539 | temp = readl(sport->port.membase + USR2); |
864eeed0 | 540 | if (temp & USR2_BRCD) { |
94d32f99 | 541 | writel(USR2_BRCD, sport->port.membase + USR2); |
864eeed0 SH |
542 | if (uart_handle_break(&sport->port)) |
543 | continue; | |
1da177e4 LT |
544 | } |
545 | ||
d3810cd4 | 546 | if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) |
864eeed0 SH |
547 | continue; |
548 | ||
019dc9ea HW |
549 | if (unlikely(rx & URXD_ERR)) { |
550 | if (rx & URXD_BRK) | |
551 | sport->port.icount.brk++; | |
552 | else if (rx & URXD_PRERR) | |
864eeed0 SH |
553 | sport->port.icount.parity++; |
554 | else if (rx & URXD_FRMERR) | |
555 | sport->port.icount.frame++; | |
556 | if (rx & URXD_OVRRUN) | |
557 | sport->port.icount.overrun++; | |
558 | ||
559 | if (rx & sport->port.ignore_status_mask) { | |
560 | if (++ignored > 100) | |
561 | goto out; | |
562 | continue; | |
563 | } | |
564 | ||
565 | rx &= sport->port.read_status_mask; | |
566 | ||
019dc9ea HW |
567 | if (rx & URXD_BRK) |
568 | flg = TTY_BREAK; | |
569 | else if (rx & URXD_PRERR) | |
864eeed0 SH |
570 | flg = TTY_PARITY; |
571 | else if (rx & URXD_FRMERR) | |
572 | flg = TTY_FRAME; | |
573 | if (rx & URXD_OVRRUN) | |
574 | flg = TTY_OVERRUN; | |
1da177e4 | 575 | |
864eeed0 SH |
576 | #ifdef SUPPORT_SYSRQ |
577 | sport->port.sysrq = 0; | |
578 | #endif | |
579 | } | |
1da177e4 | 580 | |
92a19f9c | 581 | tty_insert_flip_char(port, rx, flg); |
864eeed0 | 582 | } |
1da177e4 LT |
583 | |
584 | out: | |
82313e66 | 585 | spin_unlock_irqrestore(&sport->port.lock, flags); |
2e124b4a | 586 | tty_flip_buffer_push(port); |
1da177e4 | 587 | return IRQ_HANDLED; |
1da177e4 LT |
588 | } |
589 | ||
e3d13ff4 SH |
590 | static irqreturn_t imx_int(int irq, void *dev_id) |
591 | { | |
592 | struct imx_port *sport = dev_id; | |
593 | unsigned int sts; | |
f1f836e4 | 594 | unsigned int sts2; |
e3d13ff4 SH |
595 | |
596 | sts = readl(sport->port.membase + USR1); | |
597 | ||
598 | if (sts & USR1_RRDY) | |
599 | imx_rxint(irq, dev_id); | |
600 | ||
601 | if (sts & USR1_TRDY && | |
602 | readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) | |
603 | imx_txint(irq, dev_id); | |
604 | ||
9fbe6044 | 605 | if (sts & USR1_RTSD) |
e3d13ff4 SH |
606 | imx_rtsint(irq, dev_id); |
607 | ||
db1a9b55 FE |
608 | if (sts & USR1_AWAKE) |
609 | writel(USR1_AWAKE, sport->port.membase + USR1); | |
610 | ||
f1f836e4 AS |
611 | sts2 = readl(sport->port.membase + USR2); |
612 | if (sts2 & USR2_ORE) { | |
613 | dev_err(sport->port.dev, "Rx FIFO overrun\n"); | |
614 | sport->port.icount.overrun++; | |
615 | writel(sts2 | USR2_ORE, sport->port.membase + USR2); | |
616 | } | |
617 | ||
e3d13ff4 SH |
618 | return IRQ_HANDLED; |
619 | } | |
620 | ||
1da177e4 LT |
621 | /* |
622 | * Return TIOCSER_TEMT when transmitter is not busy. | |
623 | */ | |
624 | static unsigned int imx_tx_empty(struct uart_port *port) | |
625 | { | |
626 | struct imx_port *sport = (struct imx_port *)port; | |
627 | ||
ff4bfb21 | 628 | return (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; |
1da177e4 LT |
629 | } |
630 | ||
0f302dc3 SH |
631 | /* |
632 | * We have a modem side uart, so the meanings of RTS and CTS are inverted. | |
633 | */ | |
1da177e4 LT |
634 | static unsigned int imx_get_mctrl(struct uart_port *port) |
635 | { | |
d3810cd4 OS |
636 | struct imx_port *sport = (struct imx_port *)port; |
637 | unsigned int tmp = TIOCM_DSR | TIOCM_CAR; | |
0f302dc3 | 638 | |
d3810cd4 OS |
639 | if (readl(sport->port.membase + USR1) & USR1_RTSS) |
640 | tmp |= TIOCM_CTS; | |
0f302dc3 | 641 | |
d3810cd4 OS |
642 | if (readl(sport->port.membase + UCR2) & UCR2_CTS) |
643 | tmp |= TIOCM_RTS; | |
0f302dc3 | 644 | |
d3810cd4 | 645 | return tmp; |
1da177e4 LT |
646 | } |
647 | ||
648 | static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
649 | { | |
d3810cd4 | 650 | struct imx_port *sport = (struct imx_port *)port; |
ff4bfb21 SH |
651 | unsigned long temp; |
652 | ||
653 | temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS; | |
0f302dc3 | 654 | |
d3810cd4 | 655 | if (mctrl & TIOCM_RTS) |
ff4bfb21 SH |
656 | temp |= UCR2_CTS; |
657 | ||
658 | writel(temp, sport->port.membase + UCR2); | |
1da177e4 LT |
659 | } |
660 | ||
661 | /* | |
662 | * Interrupts always disabled. | |
663 | */ | |
664 | static void imx_break_ctl(struct uart_port *port, int break_state) | |
665 | { | |
666 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 | 667 | unsigned long flags, temp; |
1da177e4 LT |
668 | |
669 | spin_lock_irqsave(&sport->port.lock, flags); | |
670 | ||
ff4bfb21 SH |
671 | temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; |
672 | ||
82313e66 | 673 | if (break_state != 0) |
ff4bfb21 SH |
674 | temp |= UCR1_SNDBRK; |
675 | ||
676 | writel(temp, sport->port.membase + UCR1); | |
1da177e4 LT |
677 | |
678 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
679 | } | |
680 | ||
681 | #define TXTL 2 /* reset default */ | |
682 | #define RXTL 1 /* reset default */ | |
683 | ||
587897f5 SH |
684 | static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) |
685 | { | |
686 | unsigned int val; | |
587897f5 | 687 | |
7be0670f DB |
688 | /* set receiver / transmitter trigger level */ |
689 | val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); | |
690 | val |= TXTL << UFCR_TXTL_SHF | RXTL; | |
ff4bfb21 | 691 | writel(val, sport->port.membase + UFCR); |
587897f5 SH |
692 | return 0; |
693 | } | |
694 | ||
1c5250d6 VL |
695 | /* half the RX buffer size */ |
696 | #define CTSTL 16 | |
697 | ||
1da177e4 LT |
698 | static int imx_startup(struct uart_port *port) |
699 | { | |
700 | struct imx_port *sport = (struct imx_port *)port; | |
701 | int retval; | |
ff4bfb21 | 702 | unsigned long flags, temp; |
1da177e4 | 703 | |
0c375501 HS |
704 | if (!uart_console(port)) { |
705 | retval = clk_prepare_enable(sport->clk_per); | |
706 | if (retval) | |
707 | goto error_out1; | |
708 | retval = clk_prepare_enable(sport->clk_ipg); | |
709 | if (retval) { | |
710 | clk_disable_unprepare(sport->clk_per); | |
711 | goto error_out1; | |
712 | } | |
713 | } | |
28eb4274 | 714 | |
587897f5 | 715 | imx_setup_ufcr(sport, 0); |
1da177e4 LT |
716 | |
717 | /* disable the DREN bit (Data Ready interrupt enable) before | |
718 | * requesting IRQs | |
719 | */ | |
ff4bfb21 | 720 | temp = readl(sport->port.membase + UCR4); |
b6e49138 FG |
721 | |
722 | if (USE_IRDA(sport)) | |
723 | temp |= UCR4_IRSC; | |
724 | ||
1c5250d6 | 725 | /* set the trigger level for CTS */ |
82313e66 SK |
726 | temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); |
727 | temp |= CTSTL << UCR4_CTSTL_SHF; | |
1c5250d6 | 728 | |
ff4bfb21 | 729 | writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); |
1da177e4 | 730 | |
b6e49138 FG |
731 | if (USE_IRDA(sport)) { |
732 | /* reset fifo's and state machines */ | |
733 | int i = 100; | |
734 | temp = readl(sport->port.membase + UCR2); | |
735 | temp &= ~UCR2_SRST; | |
736 | writel(temp, sport->port.membase + UCR2); | |
737 | while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && | |
738 | (--i > 0)) { | |
739 | udelay(1); | |
740 | } | |
741 | } | |
742 | ||
1da177e4 | 743 | /* |
e3d13ff4 SH |
744 | * Allocate the IRQ(s) i.MX1 has three interrupts whereas later |
745 | * chips only have one interrupt. | |
1da177e4 | 746 | */ |
e3d13ff4 SH |
747 | if (sport->txirq > 0) { |
748 | retval = request_irq(sport->rxirq, imx_rxint, 0, | |
749 | DRIVER_NAME, sport); | |
750 | if (retval) | |
751 | goto error_out1; | |
752 | ||
753 | retval = request_irq(sport->txirq, imx_txint, 0, | |
754 | DRIVER_NAME, sport); | |
755 | if (retval) | |
756 | goto error_out2; | |
757 | ||
b6e49138 FG |
758 | /* do not use RTS IRQ on IrDA */ |
759 | if (!USE_IRDA(sport)) { | |
1ee8f65b | 760 | retval = request_irq(sport->rtsirq, imx_rtsint, 0, |
b6e49138 FG |
761 | DRIVER_NAME, sport); |
762 | if (retval) | |
763 | goto error_out3; | |
764 | } | |
e3d13ff4 SH |
765 | } else { |
766 | retval = request_irq(sport->port.irq, imx_int, 0, | |
767 | DRIVER_NAME, sport); | |
768 | if (retval) { | |
769 | free_irq(sport->port.irq, sport); | |
770 | goto error_out1; | |
771 | } | |
772 | } | |
ceca629e | 773 | |
9ec1882d | 774 | spin_lock_irqsave(&sport->port.lock, flags); |
1da177e4 LT |
775 | /* |
776 | * Finally, clear and enable interrupts | |
777 | */ | |
ff4bfb21 SH |
778 | writel(USR1_RTSD, sport->port.membase + USR1); |
779 | ||
780 | temp = readl(sport->port.membase + UCR1); | |
789d5258 | 781 | temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; |
b6e49138 FG |
782 | |
783 | if (USE_IRDA(sport)) { | |
784 | temp |= UCR1_IREN; | |
785 | temp &= ~(UCR1_RTSDEN); | |
786 | } | |
787 | ||
ff4bfb21 | 788 | writel(temp, sport->port.membase + UCR1); |
1da177e4 | 789 | |
ff4bfb21 SH |
790 | temp = readl(sport->port.membase + UCR2); |
791 | temp |= (UCR2_RXEN | UCR2_TXEN); | |
bff09b09 LS |
792 | if (!sport->have_rtscts) |
793 | temp |= UCR2_IRTS; | |
ff4bfb21 | 794 | writel(temp, sport->port.membase + UCR2); |
1da177e4 | 795 | |
b6e49138 FG |
796 | if (USE_IRDA(sport)) { |
797 | /* clear RX-FIFO */ | |
798 | int i = 64; | |
799 | while ((--i > 0) && | |
800 | (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) { | |
801 | barrier(); | |
802 | } | |
803 | } | |
804 | ||
fe6b540a | 805 | if (is_imx21_uart(sport)) { |
37d6fb62 | 806 | temp = readl(sport->port.membase + UCR3); |
fe6b540a | 807 | temp |= IMX21_UCR3_RXDMUXSEL; |
37d6fb62 SH |
808 | writel(temp, sport->port.membase + UCR3); |
809 | } | |
4411805b | 810 | |
b6e49138 FG |
811 | if (USE_IRDA(sport)) { |
812 | temp = readl(sport->port.membase + UCR4); | |
813 | if (sport->irda_inv_rx) | |
814 | temp |= UCR4_INVR; | |
815 | else | |
816 | temp &= ~(UCR4_INVR); | |
817 | writel(temp | UCR4_DREN, sport->port.membase + UCR4); | |
818 | ||
819 | temp = readl(sport->port.membase + UCR3); | |
820 | if (sport->irda_inv_tx) | |
821 | temp |= UCR3_INVT; | |
822 | else | |
823 | temp &= ~(UCR3_INVT); | |
824 | writel(temp, sport->port.membase + UCR3); | |
825 | } | |
826 | ||
1da177e4 LT |
827 | /* |
828 | * Enable modem status interrupts | |
829 | */ | |
1da177e4 | 830 | imx_enable_ms(&sport->port); |
82313e66 | 831 | spin_unlock_irqrestore(&sport->port.lock, flags); |
1da177e4 | 832 | |
b6e49138 FG |
833 | if (USE_IRDA(sport)) { |
834 | struct imxuart_platform_data *pdata; | |
835 | pdata = sport->port.dev->platform_data; | |
836 | sport->irda_inv_rx = pdata->irda_inv_rx; | |
837 | sport->irda_inv_tx = pdata->irda_inv_tx; | |
838 | sport->trcv_delay = pdata->transceiver_delay; | |
839 | if (pdata->irda_enable) | |
840 | pdata->irda_enable(1); | |
841 | } | |
842 | ||
1da177e4 LT |
843 | return 0; |
844 | ||
ceca629e | 845 | error_out3: |
e3d13ff4 SH |
846 | if (sport->txirq) |
847 | free_irq(sport->txirq, sport); | |
1da177e4 | 848 | error_out2: |
e3d13ff4 SH |
849 | if (sport->rxirq) |
850 | free_irq(sport->rxirq, sport); | |
86371d07 | 851 | error_out1: |
1da177e4 LT |
852 | return retval; |
853 | } | |
854 | ||
855 | static void imx_shutdown(struct uart_port *port) | |
856 | { | |
857 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 | 858 | unsigned long temp; |
9ec1882d | 859 | unsigned long flags; |
1da177e4 | 860 | |
9ec1882d | 861 | spin_lock_irqsave(&sport->port.lock, flags); |
2e146392 FG |
862 | temp = readl(sport->port.membase + UCR2); |
863 | temp &= ~(UCR2_TXEN); | |
864 | writel(temp, sport->port.membase + UCR2); | |
9ec1882d | 865 | spin_unlock_irqrestore(&sport->port.lock, flags); |
2e146392 | 866 | |
b6e49138 FG |
867 | if (USE_IRDA(sport)) { |
868 | struct imxuart_platform_data *pdata; | |
869 | pdata = sport->port.dev->platform_data; | |
870 | if (pdata->irda_enable) | |
871 | pdata->irda_enable(0); | |
872 | } | |
873 | ||
1da177e4 LT |
874 | /* |
875 | * Stop our timer. | |
876 | */ | |
877 | del_timer_sync(&sport->timer); | |
878 | ||
879 | /* | |
880 | * Free the interrupts | |
881 | */ | |
e3d13ff4 | 882 | if (sport->txirq > 0) { |
b6e49138 FG |
883 | if (!USE_IRDA(sport)) |
884 | free_irq(sport->rtsirq, sport); | |
e3d13ff4 SH |
885 | free_irq(sport->txirq, sport); |
886 | free_irq(sport->rxirq, sport); | |
887 | } else | |
888 | free_irq(sport->port.irq, sport); | |
1da177e4 LT |
889 | |
890 | /* | |
891 | * Disable all interrupts, port and break condition. | |
892 | */ | |
893 | ||
9ec1882d | 894 | spin_lock_irqsave(&sport->port.lock, flags); |
ff4bfb21 SH |
895 | temp = readl(sport->port.membase + UCR1); |
896 | temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); | |
b6e49138 FG |
897 | if (USE_IRDA(sport)) |
898 | temp &= ~(UCR1_IREN); | |
899 | ||
ff4bfb21 | 900 | writel(temp, sport->port.membase + UCR1); |
9ec1882d | 901 | spin_unlock_irqrestore(&sport->port.lock, flags); |
28eb4274 | 902 | |
80c48497 FE |
903 | if (!uart_console(&sport->port)) { |
904 | clk_disable_unprepare(sport->clk_per); | |
905 | clk_disable_unprepare(sport->clk_ipg); | |
906 | } | |
1da177e4 LT |
907 | } |
908 | ||
909 | static void | |
606d099c AC |
910 | imx_set_termios(struct uart_port *port, struct ktermios *termios, |
911 | struct ktermios *old) | |
1da177e4 LT |
912 | { |
913 | struct imx_port *sport = (struct imx_port *)port; | |
914 | unsigned long flags; | |
915 | unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; | |
916 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; | |
534fca06 OS |
917 | unsigned int div, ufcr; |
918 | unsigned long num, denom; | |
d7f8d437 | 919 | uint64_t tdiv64; |
1da177e4 LT |
920 | |
921 | /* | |
922 | * If we don't support modem control lines, don't allow | |
923 | * these to be set. | |
924 | */ | |
925 | if (0) { | |
926 | termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR); | |
927 | termios->c_cflag |= CLOCAL; | |
928 | } | |
929 | ||
930 | /* | |
931 | * We only support CS7 and CS8. | |
932 | */ | |
933 | while ((termios->c_cflag & CSIZE) != CS7 && | |
934 | (termios->c_cflag & CSIZE) != CS8) { | |
935 | termios->c_cflag &= ~CSIZE; | |
936 | termios->c_cflag |= old_csize; | |
937 | old_csize = CS8; | |
938 | } | |
939 | ||
940 | if ((termios->c_cflag & CSIZE) == CS8) | |
941 | ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; | |
942 | else | |
943 | ucr2 = UCR2_SRST | UCR2_IRTS; | |
944 | ||
945 | if (termios->c_cflag & CRTSCTS) { | |
82313e66 | 946 | if (sport->have_rtscts) { |
5b802344 SH |
947 | ucr2 &= ~UCR2_IRTS; |
948 | ucr2 |= UCR2_CTSC; | |
949 | } else { | |
950 | termios->c_cflag &= ~CRTSCTS; | |
951 | } | |
1da177e4 LT |
952 | } |
953 | ||
954 | if (termios->c_cflag & CSTOPB) | |
955 | ucr2 |= UCR2_STPB; | |
956 | if (termios->c_cflag & PARENB) { | |
957 | ucr2 |= UCR2_PREN; | |
3261e362 | 958 | if (termios->c_cflag & PARODD) |
1da177e4 LT |
959 | ucr2 |= UCR2_PROE; |
960 | } | |
961 | ||
995234da EM |
962 | del_timer_sync(&sport->timer); |
963 | ||
1da177e4 LT |
964 | /* |
965 | * Ask the core to calculate the divisor for us. | |
966 | */ | |
036bb15e | 967 | baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); |
1da177e4 LT |
968 | quot = uart_get_divisor(port, baud); |
969 | ||
970 | spin_lock_irqsave(&sport->port.lock, flags); | |
971 | ||
972 | sport->port.read_status_mask = 0; | |
973 | if (termios->c_iflag & INPCK) | |
974 | sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); | |
975 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
976 | sport->port.read_status_mask |= URXD_BRK; | |
977 | ||
978 | /* | |
979 | * Characters to ignore | |
980 | */ | |
981 | sport->port.ignore_status_mask = 0; | |
982 | if (termios->c_iflag & IGNPAR) | |
983 | sport->port.ignore_status_mask |= URXD_PRERR; | |
984 | if (termios->c_iflag & IGNBRK) { | |
985 | sport->port.ignore_status_mask |= URXD_BRK; | |
986 | /* | |
987 | * If we're ignoring parity and break indicators, | |
988 | * ignore overruns too (for real raw support). | |
989 | */ | |
990 | if (termios->c_iflag & IGNPAR) | |
991 | sport->port.ignore_status_mask |= URXD_OVRRUN; | |
992 | } | |
993 | ||
1da177e4 LT |
994 | /* |
995 | * Update the per-port timeout. | |
996 | */ | |
997 | uart_update_timeout(port, termios->c_cflag, baud); | |
998 | ||
999 | /* | |
1000 | * disable interrupts and drain transmitter | |
1001 | */ | |
ff4bfb21 SH |
1002 | old_ucr1 = readl(sport->port.membase + UCR1); |
1003 | writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), | |
1004 | sport->port.membase + UCR1); | |
1da177e4 | 1005 | |
82313e66 | 1006 | while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) |
1da177e4 LT |
1007 | barrier(); |
1008 | ||
1009 | /* then, disable everything */ | |
ff4bfb21 | 1010 | old_txrxen = readl(sport->port.membase + UCR2); |
82313e66 | 1011 | writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN), |
ff4bfb21 SH |
1012 | sport->port.membase + UCR2); |
1013 | old_txrxen &= (UCR2_TXEN | UCR2_RXEN); | |
1da177e4 | 1014 | |
b6e49138 FG |
1015 | if (USE_IRDA(sport)) { |
1016 | /* | |
1017 | * use maximum available submodule frequency to | |
1018 | * avoid missing short pulses due to low sampling rate | |
1019 | */ | |
036bb15e | 1020 | div = 1; |
b6e49138 FG |
1021 | } else { |
1022 | div = sport->port.uartclk / (baud * 16); | |
1023 | if (div > 7) | |
1024 | div = 7; | |
1025 | if (!div) | |
1026 | div = 1; | |
1027 | } | |
036bb15e | 1028 | |
534fca06 OS |
1029 | rational_best_approximation(16 * div * baud, sport->port.uartclk, |
1030 | 1 << 16, 1 << 16, &num, &denom); | |
036bb15e | 1031 | |
eab4f5af AC |
1032 | tdiv64 = sport->port.uartclk; |
1033 | tdiv64 *= num; | |
1034 | do_div(tdiv64, denom * 16 * div); | |
1035 | tty_termios_encode_baud_rate(termios, | |
1a2c4b31 | 1036 | (speed_t)tdiv64, (speed_t)tdiv64); |
d7f8d437 | 1037 | |
534fca06 OS |
1038 | num -= 1; |
1039 | denom -= 1; | |
036bb15e SH |
1040 | |
1041 | ufcr = readl(sport->port.membase + UFCR); | |
b6e49138 | 1042 | ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); |
20ff2fe6 HS |
1043 | if (sport->dte_mode) |
1044 | ufcr |= UFCR_DCEDTE; | |
036bb15e SH |
1045 | writel(ufcr, sport->port.membase + UFCR); |
1046 | ||
534fca06 OS |
1047 | writel(num, sport->port.membase + UBIR); |
1048 | writel(denom, sport->port.membase + UBMR); | |
1049 | ||
fe6b540a | 1050 | if (is_imx21_uart(sport)) |
37d6fb62 | 1051 | writel(sport->port.uartclk / div / 1000, |
fe6b540a | 1052 | sport->port.membase + IMX21_ONEMS); |
ff4bfb21 SH |
1053 | |
1054 | writel(old_ucr1, sport->port.membase + UCR1); | |
1da177e4 | 1055 | |
ff4bfb21 SH |
1056 | /* set the parity, stop bits and data size */ |
1057 | writel(ucr2 | old_txrxen, sport->port.membase + UCR2); | |
1da177e4 LT |
1058 | |
1059 | if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) | |
1060 | imx_enable_ms(&sport->port); | |
1061 | ||
1062 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
1063 | } | |
1064 | ||
1065 | static const char *imx_type(struct uart_port *port) | |
1066 | { | |
1067 | struct imx_port *sport = (struct imx_port *)port; | |
1068 | ||
1069 | return sport->port.type == PORT_IMX ? "IMX" : NULL; | |
1070 | } | |
1071 | ||
1072 | /* | |
1073 | * Release the memory region(s) being used by 'port'. | |
1074 | */ | |
1075 | static void imx_release_port(struct uart_port *port) | |
1076 | { | |
3d454446 SH |
1077 | struct platform_device *pdev = to_platform_device(port->dev); |
1078 | struct resource *mmres; | |
1da177e4 | 1079 | |
3d454446 | 1080 | mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
28f65c11 | 1081 | release_mem_region(mmres->start, resource_size(mmres)); |
1da177e4 LT |
1082 | } |
1083 | ||
1084 | /* | |
1085 | * Request the memory region(s) being used by 'port'. | |
1086 | */ | |
1087 | static int imx_request_port(struct uart_port *port) | |
1088 | { | |
3d454446 SH |
1089 | struct platform_device *pdev = to_platform_device(port->dev); |
1090 | struct resource *mmres; | |
1091 | void *ret; | |
1092 | ||
1093 | mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1094 | if (!mmres) | |
1095 | return -ENODEV; | |
1096 | ||
28f65c11 | 1097 | ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart"); |
1da177e4 | 1098 | |
3d454446 | 1099 | return ret ? 0 : -EBUSY; |
1da177e4 LT |
1100 | } |
1101 | ||
1102 | /* | |
1103 | * Configure/autoconfigure the port. | |
1104 | */ | |
1105 | static void imx_config_port(struct uart_port *port, int flags) | |
1106 | { | |
1107 | struct imx_port *sport = (struct imx_port *)port; | |
1108 | ||
1109 | if (flags & UART_CONFIG_TYPE && | |
1110 | imx_request_port(&sport->port) == 0) | |
1111 | sport->port.type = PORT_IMX; | |
1112 | } | |
1113 | ||
1114 | /* | |
1115 | * Verify the new serial_struct (for TIOCSSERIAL). | |
1116 | * The only change we allow are to the flags and type, and | |
1117 | * even then only between PORT_IMX and PORT_UNKNOWN | |
1118 | */ | |
1119 | static int | |
1120 | imx_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1121 | { | |
1122 | struct imx_port *sport = (struct imx_port *)port; | |
1123 | int ret = 0; | |
1124 | ||
1125 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) | |
1126 | ret = -EINVAL; | |
1127 | if (sport->port.irq != ser->irq) | |
1128 | ret = -EINVAL; | |
1129 | if (ser->io_type != UPIO_MEM) | |
1130 | ret = -EINVAL; | |
1131 | if (sport->port.uartclk / 16 != ser->baud_base) | |
1132 | ret = -EINVAL; | |
1133 | if ((void *)sport->port.mapbase != ser->iomem_base) | |
1134 | ret = -EINVAL; | |
1135 | if (sport->port.iobase != ser->port) | |
1136 | ret = -EINVAL; | |
1137 | if (ser->hub6 != 0) | |
1138 | ret = -EINVAL; | |
1139 | return ret; | |
1140 | } | |
1141 | ||
01f56abd SA |
1142 | #if defined(CONFIG_CONSOLE_POLL) |
1143 | static int imx_poll_get_char(struct uart_port *port) | |
1144 | { | |
1145 | struct imx_port_ucrs old_ucr; | |
1146 | unsigned int status; | |
1147 | unsigned char c; | |
1148 | ||
1149 | /* save control registers */ | |
1150 | imx_port_ucrs_save(port, &old_ucr); | |
1151 | ||
1152 | /* disable interrupts */ | |
1153 | writel(UCR1_UARTEN, port->membase + UCR1); | |
1154 | writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), | |
1155 | port->membase + UCR2); | |
1156 | writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), | |
1157 | port->membase + UCR3); | |
1158 | ||
1159 | /* poll */ | |
1160 | do { | |
1161 | status = readl(port->membase + USR2); | |
1162 | } while (~status & USR2_RDR); | |
1163 | ||
1164 | /* read */ | |
1165 | c = readl(port->membase + URXD0); | |
1166 | ||
1167 | /* restore control registers */ | |
1168 | imx_port_ucrs_restore(port, &old_ucr); | |
1169 | ||
1170 | return c; | |
1171 | } | |
1172 | ||
1173 | static void imx_poll_put_char(struct uart_port *port, unsigned char c) | |
1174 | { | |
1175 | struct imx_port_ucrs old_ucr; | |
1176 | unsigned int status; | |
1177 | ||
1178 | /* save control registers */ | |
1179 | imx_port_ucrs_save(port, &old_ucr); | |
1180 | ||
1181 | /* disable interrupts */ | |
1182 | writel(UCR1_UARTEN, port->membase + UCR1); | |
1183 | writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI), | |
1184 | port->membase + UCR2); | |
1185 | writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN), | |
1186 | port->membase + UCR3); | |
1187 | ||
1188 | /* drain */ | |
1189 | do { | |
1190 | status = readl(port->membase + USR1); | |
1191 | } while (~status & USR1_TRDY); | |
1192 | ||
1193 | /* write */ | |
1194 | writel(c, port->membase + URTX0); | |
1195 | ||
1196 | /* flush */ | |
1197 | do { | |
1198 | status = readl(port->membase + USR2); | |
1199 | } while (~status & USR2_TXDC); | |
1200 | ||
1201 | /* restore control registers */ | |
1202 | imx_port_ucrs_restore(port, &old_ucr); | |
1203 | } | |
1204 | #endif | |
1205 | ||
1da177e4 LT |
1206 | static struct uart_ops imx_pops = { |
1207 | .tx_empty = imx_tx_empty, | |
1208 | .set_mctrl = imx_set_mctrl, | |
1209 | .get_mctrl = imx_get_mctrl, | |
1210 | .stop_tx = imx_stop_tx, | |
1211 | .start_tx = imx_start_tx, | |
1212 | .stop_rx = imx_stop_rx, | |
1213 | .enable_ms = imx_enable_ms, | |
1214 | .break_ctl = imx_break_ctl, | |
1215 | .startup = imx_startup, | |
1216 | .shutdown = imx_shutdown, | |
1217 | .set_termios = imx_set_termios, | |
1218 | .type = imx_type, | |
1219 | .release_port = imx_release_port, | |
1220 | .request_port = imx_request_port, | |
1221 | .config_port = imx_config_port, | |
1222 | .verify_port = imx_verify_port, | |
01f56abd SA |
1223 | #if defined(CONFIG_CONSOLE_POLL) |
1224 | .poll_get_char = imx_poll_get_char, | |
1225 | .poll_put_char = imx_poll_put_char, | |
1226 | #endif | |
1da177e4 LT |
1227 | }; |
1228 | ||
dbff4e9e | 1229 | static struct imx_port *imx_ports[UART_NR]; |
1da177e4 LT |
1230 | |
1231 | #ifdef CONFIG_SERIAL_IMX_CONSOLE | |
d358788f RK |
1232 | static void imx_console_putchar(struct uart_port *port, int ch) |
1233 | { | |
1234 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 | 1235 | |
fe6b540a | 1236 | while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) |
d358788f | 1237 | barrier(); |
ff4bfb21 SH |
1238 | |
1239 | writel(ch, sport->port.membase + URTX0); | |
d358788f | 1240 | } |
1da177e4 LT |
1241 | |
1242 | /* | |
1243 | * Interrupts are disabled on entering | |
1244 | */ | |
1245 | static void | |
1246 | imx_console_write(struct console *co, const char *s, unsigned int count) | |
1247 | { | |
dbff4e9e | 1248 | struct imx_port *sport = imx_ports[co->index]; |
0ad5a814 DB |
1249 | struct imx_port_ucrs old_ucr; |
1250 | unsigned int ucr1; | |
f30e8260 | 1251 | unsigned long flags = 0; |
677fe555 | 1252 | int locked = 1; |
9ec1882d | 1253 | |
677fe555 TG |
1254 | if (sport->port.sysrq) |
1255 | locked = 0; | |
1256 | else if (oops_in_progress) | |
1257 | locked = spin_trylock_irqsave(&sport->port.lock, flags); | |
1258 | else | |
1259 | spin_lock_irqsave(&sport->port.lock, flags); | |
1da177e4 LT |
1260 | |
1261 | /* | |
0ad5a814 | 1262 | * First, save UCR1/2/3 and then disable interrupts |
1da177e4 | 1263 | */ |
0ad5a814 DB |
1264 | imx_port_ucrs_save(&sport->port, &old_ucr); |
1265 | ucr1 = old_ucr.ucr1; | |
1da177e4 | 1266 | |
fe6b540a SG |
1267 | if (is_imx1_uart(sport)) |
1268 | ucr1 |= IMX1_UCR1_UARTCLKEN; | |
37d6fb62 SH |
1269 | ucr1 |= UCR1_UARTEN; |
1270 | ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); | |
1271 | ||
1272 | writel(ucr1, sport->port.membase + UCR1); | |
ff4bfb21 | 1273 | |
0ad5a814 | 1274 | writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); |
1da177e4 | 1275 | |
d358788f | 1276 | uart_console_write(&sport->port, s, count, imx_console_putchar); |
1da177e4 LT |
1277 | |
1278 | /* | |
1279 | * Finally, wait for transmitter to become empty | |
0ad5a814 | 1280 | * and restore UCR1/2/3 |
1da177e4 | 1281 | */ |
ff4bfb21 | 1282 | while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); |
1da177e4 | 1283 | |
0ad5a814 | 1284 | imx_port_ucrs_restore(&sport->port, &old_ucr); |
9ec1882d | 1285 | |
677fe555 TG |
1286 | if (locked) |
1287 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
1da177e4 LT |
1288 | } |
1289 | ||
1290 | /* | |
1291 | * If the port was already initialised (eg, by a boot loader), | |
1292 | * try to determine the current setup. | |
1293 | */ | |
1294 | static void __init | |
1295 | imx_console_get_options(struct imx_port *sport, int *baud, | |
1296 | int *parity, int *bits) | |
1297 | { | |
587897f5 | 1298 | |
2e2eb509 | 1299 | if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { |
1da177e4 | 1300 | /* ok, the port was enabled */ |
82313e66 | 1301 | unsigned int ucr2, ubir, ubmr, uartclk; |
587897f5 SH |
1302 | unsigned int baud_raw; |
1303 | unsigned int ucfr_rfdiv; | |
1da177e4 | 1304 | |
ff4bfb21 | 1305 | ucr2 = readl(sport->port.membase + UCR2); |
1da177e4 LT |
1306 | |
1307 | *parity = 'n'; | |
1308 | if (ucr2 & UCR2_PREN) { | |
1309 | if (ucr2 & UCR2_PROE) | |
1310 | *parity = 'o'; | |
1311 | else | |
1312 | *parity = 'e'; | |
1313 | } | |
1314 | ||
1315 | if (ucr2 & UCR2_WS) | |
1316 | *bits = 8; | |
1317 | else | |
1318 | *bits = 7; | |
1319 | ||
ff4bfb21 SH |
1320 | ubir = readl(sport->port.membase + UBIR) & 0xffff; |
1321 | ubmr = readl(sport->port.membase + UBMR) & 0xffff; | |
587897f5 | 1322 | |
ff4bfb21 | 1323 | ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; |
587897f5 SH |
1324 | if (ucfr_rfdiv == 6) |
1325 | ucfr_rfdiv = 7; | |
1326 | else | |
1327 | ucfr_rfdiv = 6 - ucfr_rfdiv; | |
1328 | ||
3a9465fa | 1329 | uartclk = clk_get_rate(sport->clk_per); |
587897f5 SH |
1330 | uartclk /= ucfr_rfdiv; |
1331 | ||
1332 | { /* | |
1333 | * The next code provides exact computation of | |
1334 | * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) | |
1335 | * without need of float support or long long division, | |
1336 | * which would be required to prevent 32bit arithmetic overflow | |
1337 | */ | |
1338 | unsigned int mul = ubir + 1; | |
1339 | unsigned int div = 16 * (ubmr + 1); | |
1340 | unsigned int rem = uartclk % div; | |
1341 | ||
1342 | baud_raw = (uartclk / div) * mul; | |
1343 | baud_raw += (rem * mul + div / 2) / div; | |
1344 | *baud = (baud_raw + 50) / 100 * 100; | |
1345 | } | |
1346 | ||
82313e66 | 1347 | if (*baud != baud_raw) |
50bbdba3 | 1348 | pr_info("Console IMX rounded baud rate from %d to %d\n", |
587897f5 | 1349 | baud_raw, *baud); |
1da177e4 LT |
1350 | } |
1351 | } | |
1352 | ||
1353 | static int __init | |
1354 | imx_console_setup(struct console *co, char *options) | |
1355 | { | |
1356 | struct imx_port *sport; | |
1357 | int baud = 9600; | |
1358 | int bits = 8; | |
1359 | int parity = 'n'; | |
1360 | int flow = 'n'; | |
1361 | ||
1362 | /* | |
1363 | * Check whether an invalid uart number has been specified, and | |
1364 | * if so, search for the first available port that does have | |
1365 | * console support. | |
1366 | */ | |
1367 | if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) | |
1368 | co->index = 0; | |
dbff4e9e | 1369 | sport = imx_ports[co->index]; |
82313e66 | 1370 | if (sport == NULL) |
e76afc4e | 1371 | return -ENODEV; |
1da177e4 LT |
1372 | |
1373 | if (options) | |
1374 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1375 | else | |
1376 | imx_console_get_options(sport, &baud, &parity, &bits); | |
1377 | ||
587897f5 SH |
1378 | imx_setup_ufcr(sport, 0); |
1379 | ||
1da177e4 LT |
1380 | return uart_set_options(&sport->port, co, baud, parity, bits, flow); |
1381 | } | |
1382 | ||
9f4426dd | 1383 | static struct uart_driver imx_reg; |
1da177e4 | 1384 | static struct console imx_console = { |
e3d13ff4 | 1385 | .name = DEV_NAME, |
1da177e4 LT |
1386 | .write = imx_console_write, |
1387 | .device = uart_console_device, | |
1388 | .setup = imx_console_setup, | |
1389 | .flags = CON_PRINTBUFFER, | |
1390 | .index = -1, | |
1391 | .data = &imx_reg, | |
1392 | }; | |
1393 | ||
1da177e4 LT |
1394 | #define IMX_CONSOLE &imx_console |
1395 | #else | |
1396 | #define IMX_CONSOLE NULL | |
1397 | #endif | |
1398 | ||
1399 | static struct uart_driver imx_reg = { | |
1400 | .owner = THIS_MODULE, | |
1401 | .driver_name = DRIVER_NAME, | |
e3d13ff4 | 1402 | .dev_name = DEV_NAME, |
1da177e4 LT |
1403 | .major = SERIAL_IMX_MAJOR, |
1404 | .minor = MINOR_START, | |
1405 | .nr = ARRAY_SIZE(imx_ports), | |
1406 | .cons = IMX_CONSOLE, | |
1407 | }; | |
1408 | ||
3ae5eaec | 1409 | static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 1410 | { |
d3810cd4 | 1411 | struct imx_port *sport = platform_get_drvdata(dev); |
db1a9b55 FE |
1412 | unsigned int val; |
1413 | ||
1414 | /* enable wakeup from i.MX UART */ | |
1415 | val = readl(sport->port.membase + UCR3); | |
1416 | val |= UCR3_AWAKEN; | |
1417 | writel(val, sport->port.membase + UCR3); | |
1da177e4 | 1418 | |
034dc4db | 1419 | uart_suspend_port(&imx_reg, &sport->port); |
1da177e4 | 1420 | |
d3810cd4 | 1421 | return 0; |
1da177e4 LT |
1422 | } |
1423 | ||
3ae5eaec | 1424 | static int serial_imx_resume(struct platform_device *dev) |
1da177e4 | 1425 | { |
d3810cd4 | 1426 | struct imx_port *sport = platform_get_drvdata(dev); |
db1a9b55 FE |
1427 | unsigned int val; |
1428 | ||
1429 | /* disable wakeup from i.MX UART */ | |
1430 | val = readl(sport->port.membase + UCR3); | |
1431 | val &= ~UCR3_AWAKEN; | |
1432 | writel(val, sport->port.membase + UCR3); | |
1da177e4 | 1433 | |
034dc4db | 1434 | uart_resume_port(&imx_reg, &sport->port); |
1da177e4 | 1435 | |
d3810cd4 | 1436 | return 0; |
1da177e4 LT |
1437 | } |
1438 | ||
22698aa2 | 1439 | #ifdef CONFIG_OF |
20bb8095 UKK |
1440 | /* |
1441 | * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it | |
1442 | * could successfully get all information from dt or a negative errno. | |
1443 | */ | |
22698aa2 SG |
1444 | static int serial_imx_probe_dt(struct imx_port *sport, |
1445 | struct platform_device *pdev) | |
1446 | { | |
1447 | struct device_node *np = pdev->dev.of_node; | |
1448 | const struct of_device_id *of_id = | |
1449 | of_match_device(imx_uart_dt_ids, &pdev->dev); | |
ff05967a | 1450 | int ret; |
22698aa2 SG |
1451 | |
1452 | if (!np) | |
20bb8095 UKK |
1453 | /* no device tree device */ |
1454 | return 1; | |
22698aa2 | 1455 | |
ff05967a SG |
1456 | ret = of_alias_get_id(np, "serial"); |
1457 | if (ret < 0) { | |
1458 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); | |
a197a191 | 1459 | return ret; |
ff05967a SG |
1460 | } |
1461 | sport->port.line = ret; | |
22698aa2 SG |
1462 | |
1463 | if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) | |
1464 | sport->have_rtscts = 1; | |
1465 | ||
1466 | if (of_get_property(np, "fsl,irda-mode", NULL)) | |
1467 | sport->use_irda = 1; | |
1468 | ||
20ff2fe6 HS |
1469 | if (of_get_property(np, "fsl,dte-mode", NULL)) |
1470 | sport->dte_mode = 1; | |
1471 | ||
22698aa2 SG |
1472 | sport->devdata = of_id->data; |
1473 | ||
1474 | return 0; | |
1475 | } | |
1476 | #else | |
1477 | static inline int serial_imx_probe_dt(struct imx_port *sport, | |
1478 | struct platform_device *pdev) | |
1479 | { | |
20bb8095 | 1480 | return 1; |
22698aa2 SG |
1481 | } |
1482 | #endif | |
1483 | ||
1484 | static void serial_imx_probe_pdata(struct imx_port *sport, | |
1485 | struct platform_device *pdev) | |
1486 | { | |
1487 | struct imxuart_platform_data *pdata = pdev->dev.platform_data; | |
1488 | ||
1489 | sport->port.line = pdev->id; | |
1490 | sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; | |
1491 | ||
1492 | if (!pdata) | |
1493 | return; | |
1494 | ||
1495 | if (pdata->flags & IMXUART_HAVE_RTSCTS) | |
1496 | sport->have_rtscts = 1; | |
1497 | ||
1498 | if (pdata->flags & IMXUART_IRDA) | |
1499 | sport->use_irda = 1; | |
1500 | } | |
1501 | ||
2582d8c1 | 1502 | static int serial_imx_probe(struct platform_device *pdev) |
1da177e4 | 1503 | { |
dbff4e9e | 1504 | struct imx_port *sport; |
5b802344 | 1505 | struct imxuart_platform_data *pdata; |
dbff4e9e SH |
1506 | void __iomem *base; |
1507 | int ret = 0; | |
1508 | struct resource *res; | |
1509 | ||
42d34191 | 1510 | sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); |
dbff4e9e SH |
1511 | if (!sport) |
1512 | return -ENOMEM; | |
5b802344 | 1513 | |
22698aa2 | 1514 | ret = serial_imx_probe_dt(sport, pdev); |
20bb8095 | 1515 | if (ret > 0) |
22698aa2 | 1516 | serial_imx_probe_pdata(sport, pdev); |
20bb8095 | 1517 | else if (ret < 0) |
42d34191 | 1518 | return ret; |
22698aa2 | 1519 | |
dbff4e9e | 1520 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
42d34191 SK |
1521 | if (!res) |
1522 | return -ENODEV; | |
dbff4e9e | 1523 | |
42d34191 SK |
1524 | base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE); |
1525 | if (!base) | |
1526 | return -ENOMEM; | |
dbff4e9e SH |
1527 | |
1528 | sport->port.dev = &pdev->dev; | |
1529 | sport->port.mapbase = res->start; | |
1530 | sport->port.membase = base; | |
1531 | sport->port.type = PORT_IMX, | |
1532 | sport->port.iotype = UPIO_MEM; | |
1533 | sport->port.irq = platform_get_irq(pdev, 0); | |
1534 | sport->rxirq = platform_get_irq(pdev, 0); | |
1535 | sport->txirq = platform_get_irq(pdev, 1); | |
1536 | sport->rtsirq = platform_get_irq(pdev, 2); | |
1537 | sport->port.fifosize = 32; | |
1538 | sport->port.ops = &imx_pops; | |
1539 | sport->port.flags = UPF_BOOT_AUTOCONF; | |
dbff4e9e SH |
1540 | init_timer(&sport->timer); |
1541 | sport->timer.function = imx_timeout; | |
1542 | sport->timer.data = (unsigned long)sport; | |
38a41fdf | 1543 | |
3a9465fa SH |
1544 | sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1545 | if (IS_ERR(sport->clk_ipg)) { | |
1546 | ret = PTR_ERR(sport->clk_ipg); | |
833462e9 | 1547 | dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); |
42d34191 | 1548 | return ret; |
38a41fdf | 1549 | } |
38a41fdf | 1550 | |
3a9465fa SH |
1551 | sport->clk_per = devm_clk_get(&pdev->dev, "per"); |
1552 | if (IS_ERR(sport->clk_per)) { | |
1553 | ret = PTR_ERR(sport->clk_per); | |
833462e9 | 1554 | dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); |
42d34191 | 1555 | return ret; |
3a9465fa SH |
1556 | } |
1557 | ||
1558 | clk_prepare_enable(sport->clk_per); | |
1559 | clk_prepare_enable(sport->clk_ipg); | |
1560 | ||
1561 | sport->port.uartclk = clk_get_rate(sport->clk_per); | |
dbff4e9e | 1562 | |
22698aa2 | 1563 | imx_ports[sport->port.line] = sport; |
5b802344 | 1564 | |
2582d8c1 | 1565 | pdata = pdev->dev.platform_data; |
bbcd18d1 | 1566 | if (pdata && pdata->init) { |
c45e7d7b DA |
1567 | ret = pdata->init(pdev); |
1568 | if (ret) | |
1569 | goto clkput; | |
1570 | } | |
2582d8c1 | 1571 | |
9f322ad0 DG |
1572 | ret = uart_add_one_port(&imx_reg, &sport->port); |
1573 | if (ret) | |
1574 | goto deinit; | |
0a86a86b | 1575 | platform_set_drvdata(pdev, sport); |
5b802344 | 1576 | |
0c375501 HS |
1577 | if (!uart_console(&sport->port)) { |
1578 | clk_disable_unprepare(sport->clk_per); | |
1579 | clk_disable_unprepare(sport->clk_ipg); | |
1580 | } | |
28eb4274 | 1581 | |
1da177e4 | 1582 | return 0; |
9f322ad0 | 1583 | deinit: |
bbcd18d1 | 1584 | if (pdata && pdata->exit) |
9f322ad0 | 1585 | pdata->exit(pdev); |
c45e7d7b | 1586 | clkput: |
3a9465fa SH |
1587 | clk_disable_unprepare(sport->clk_per); |
1588 | clk_disable_unprepare(sport->clk_ipg); | |
dbff4e9e | 1589 | return ret; |
1da177e4 LT |
1590 | } |
1591 | ||
2582d8c1 | 1592 | static int serial_imx_remove(struct platform_device *pdev) |
1da177e4 | 1593 | { |
2582d8c1 SH |
1594 | struct imxuart_platform_data *pdata; |
1595 | struct imx_port *sport = platform_get_drvdata(pdev); | |
1da177e4 | 1596 | |
2582d8c1 SH |
1597 | pdata = pdev->dev.platform_data; |
1598 | ||
3a9465fa SH |
1599 | uart_remove_one_port(&imx_reg, &sport->port); |
1600 | ||
bbcd18d1 | 1601 | if (pdata && pdata->exit) |
2582d8c1 SH |
1602 | pdata->exit(pdev); |
1603 | ||
1da177e4 LT |
1604 | return 0; |
1605 | } | |
1606 | ||
3ae5eaec | 1607 | static struct platform_driver serial_imx_driver = { |
d3810cd4 OS |
1608 | .probe = serial_imx_probe, |
1609 | .remove = serial_imx_remove, | |
1da177e4 LT |
1610 | |
1611 | .suspend = serial_imx_suspend, | |
1612 | .resume = serial_imx_resume, | |
fe6b540a | 1613 | .id_table = imx_uart_devtype, |
3ae5eaec | 1614 | .driver = { |
d3810cd4 | 1615 | .name = "imx-uart", |
e169c139 | 1616 | .owner = THIS_MODULE, |
22698aa2 | 1617 | .of_match_table = imx_uart_dt_ids, |
3ae5eaec | 1618 | }, |
1da177e4 LT |
1619 | }; |
1620 | ||
1621 | static int __init imx_serial_init(void) | |
1622 | { | |
1623 | int ret; | |
1624 | ||
50bbdba3 | 1625 | pr_info("Serial: IMX driver\n"); |
1da177e4 | 1626 | |
1da177e4 LT |
1627 | ret = uart_register_driver(&imx_reg); |
1628 | if (ret) | |
1629 | return ret; | |
1630 | ||
3ae5eaec | 1631 | ret = platform_driver_register(&serial_imx_driver); |
1da177e4 LT |
1632 | if (ret != 0) |
1633 | uart_unregister_driver(&imx_reg); | |
1634 | ||
f227824e | 1635 | return ret; |
1da177e4 LT |
1636 | } |
1637 | ||
1638 | static void __exit imx_serial_exit(void) | |
1639 | { | |
c889b896 | 1640 | platform_driver_unregister(&serial_imx_driver); |
4b300c36 | 1641 | uart_unregister_driver(&imx_reg); |
1da177e4 LT |
1642 | } |
1643 | ||
1644 | module_init(imx_serial_init); | |
1645 | module_exit(imx_serial_exit); | |
1646 | ||
1647 | MODULE_AUTHOR("Sascha Hauer"); | |
1648 | MODULE_DESCRIPTION("IMX generic serial port driver"); | |
1649 | MODULE_LICENSE("GPL"); | |
e169c139 | 1650 | MODULE_ALIAS("platform:imx-uart"); |