Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for Motorola IMX serial ports |
3 | * | |
4 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
5 | * | |
6 | * Author: Sascha Hauer <sascha@saschahauer.de> | |
7 | * Copyright (C) 2004 Pengutronix | |
8 | * | |
b6e49138 FG |
9 | * Copyright (C) 2009 emlix GmbH |
10 | * Author: Fabian Godehardt (added IrDA support for iMX) | |
11 | * | |
1da177e4 LT |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | * | |
26 | * [29-Mar-2005] Mike Lee | |
27 | * Added hardware handshake | |
28 | */ | |
1da177e4 LT |
29 | |
30 | #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
31 | #define SUPPORT_SYSRQ | |
32 | #endif | |
33 | ||
34 | #include <linux/module.h> | |
35 | #include <linux/ioport.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/console.h> | |
38 | #include <linux/sysrq.h> | |
d052d1be | 39 | #include <linux/platform_device.h> |
1da177e4 LT |
40 | #include <linux/tty.h> |
41 | #include <linux/tty_flip.h> | |
42 | #include <linux/serial_core.h> | |
43 | #include <linux/serial.h> | |
38a41fdf | 44 | #include <linux/clk.h> |
b6e49138 | 45 | #include <linux/delay.h> |
534fca06 | 46 | #include <linux/rational.h> |
5a0e3ad6 | 47 | #include <linux/slab.h> |
22698aa2 SG |
48 | #include <linux/of.h> |
49 | #include <linux/of_device.h> | |
e32a9f8f | 50 | #include <linux/io.h> |
b4cdc8f6 | 51 | #include <linux/dma-mapping.h> |
1da177e4 | 52 | |
1da177e4 | 53 | #include <asm/irq.h> |
82906b13 | 54 | #include <linux/platform_data/serial-imx.h> |
b4cdc8f6 | 55 | #include <linux/platform_data/dma-imx.h> |
1da177e4 | 56 | |
ff4bfb21 SH |
57 | /* Register definitions */ |
58 | #define URXD0 0x0 /* Receiver Register */ | |
59 | #define URTX0 0x40 /* Transmitter Register */ | |
60 | #define UCR1 0x80 /* Control Register 1 */ | |
61 | #define UCR2 0x84 /* Control Register 2 */ | |
62 | #define UCR3 0x88 /* Control Register 3 */ | |
63 | #define UCR4 0x8c /* Control Register 4 */ | |
64 | #define UFCR 0x90 /* FIFO Control Register */ | |
65 | #define USR1 0x94 /* Status Register 1 */ | |
66 | #define USR2 0x98 /* Status Register 2 */ | |
67 | #define UESC 0x9c /* Escape Character Register */ | |
68 | #define UTIM 0xa0 /* Escape Timer Register */ | |
69 | #define UBIR 0xa4 /* BRM Incremental Register */ | |
70 | #define UBMR 0xa8 /* BRM Modulator Register */ | |
71 | #define UBRC 0xac /* Baud Rate Count Register */ | |
fe6b540a SG |
72 | #define IMX21_ONEMS 0xb0 /* One Millisecond register */ |
73 | #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */ | |
74 | #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/ | |
ff4bfb21 SH |
75 | |
76 | /* UART Control Register Bit Fields.*/ | |
55d8693a | 77 | #define URXD_DUMMY_READ (1<<16) |
82313e66 SK |
78 | #define URXD_CHARRDY (1<<15) |
79 | #define URXD_ERR (1<<14) | |
80 | #define URXD_OVRRUN (1<<13) | |
81 | #define URXD_FRMERR (1<<12) | |
82 | #define URXD_BRK (1<<11) | |
83 | #define URXD_PRERR (1<<10) | |
26c47412 | 84 | #define URXD_RX_DATA (0xFF<<0) |
82313e66 SK |
85 | #define UCR1_ADEN (1<<15) /* Auto detect interrupt */ |
86 | #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ | |
87 | #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ | |
88 | #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ | |
b4cdc8f6 | 89 | #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */ |
82313e66 SK |
90 | #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ |
91 | #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ | |
92 | #define UCR1_IREN (1<<7) /* Infrared interface enable */ | |
93 | #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ | |
94 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ | |
95 | #define UCR1_SNDBRK (1<<4) /* Send break */ | |
96 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ | |
97 | #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */ | |
b4cdc8f6 | 98 | #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */ |
82313e66 SK |
99 | #define UCR1_DOZE (1<<1) /* Doze */ |
100 | #define UCR1_UARTEN (1<<0) /* UART enabled */ | |
101 | #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ | |
102 | #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ | |
103 | #define UCR2_CTSC (1<<13) /* CTS pin control */ | |
104 | #define UCR2_CTS (1<<12) /* Clear to send */ | |
105 | #define UCR2_ESCEN (1<<11) /* Escape enable */ | |
106 | #define UCR2_PREN (1<<8) /* Parity enable */ | |
107 | #define UCR2_PROE (1<<7) /* Parity odd/even */ | |
108 | #define UCR2_STPB (1<<6) /* Stop */ | |
109 | #define UCR2_WS (1<<5) /* Word size */ | |
110 | #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ | |
111 | #define UCR2_ATEN (1<<3) /* Aging Timer Enable */ | |
112 | #define UCR2_TXEN (1<<2) /* Transmitter enabled */ | |
113 | #define UCR2_RXEN (1<<1) /* Receiver enabled */ | |
114 | #define UCR2_SRST (1<<0) /* SW reset */ | |
115 | #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ | |
116 | #define UCR3_PARERREN (1<<12) /* Parity enable */ | |
117 | #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ | |
118 | #define UCR3_DSR (1<<10) /* Data set ready */ | |
119 | #define UCR3_DCD (1<<9) /* Data carrier detect */ | |
120 | #define UCR3_RI (1<<8) /* Ring indicator */ | |
b38cb7d2 | 121 | #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */ |
82313e66 SK |
122 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ |
123 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ | |
124 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ | |
125 | #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */ | |
126 | #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ | |
127 | #define UCR3_BPEN (1<<0) /* Preset registers enable */ | |
128 | #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */ | |
129 | #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */ | |
130 | #define UCR4_INVR (1<<9) /* Inverted infrared reception */ | |
131 | #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ | |
132 | #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ | |
133 | #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ | |
b4cdc8f6 | 134 | #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */ |
82313e66 SK |
135 | #define UCR4_IRSC (1<<5) /* IR special case */ |
136 | #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ | |
137 | #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ | |
138 | #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ | |
139 | #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ | |
140 | #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ | |
141 | #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */ | |
142 | #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ | |
143 | #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7) | |
144 | #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ | |
145 | #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ | |
146 | #define USR1_RTSS (1<<14) /* RTS pin status */ | |
147 | #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ | |
148 | #define USR1_RTSD (1<<12) /* RTS delta */ | |
149 | #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ | |
150 | #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ | |
151 | #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ | |
152 | #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ | |
153 | #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ | |
154 | #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ | |
155 | #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ | |
156 | #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ | |
157 | #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ | |
158 | #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ | |
159 | #define USR2_IDLE (1<<12) /* Idle condition */ | |
160 | #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ | |
161 | #define USR2_WAKE (1<<7) /* Wake */ | |
162 | #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ | |
163 | #define USR2_TXDC (1<<3) /* Transmitter complete */ | |
164 | #define USR2_BRCD (1<<2) /* Break condition */ | |
165 | #define USR2_ORE (1<<1) /* Overrun error */ | |
166 | #define USR2_RDR (1<<0) /* Recv data ready */ | |
167 | #define UTS_FRCPERR (1<<13) /* Force parity error */ | |
168 | #define UTS_LOOP (1<<12) /* Loop tx and rx */ | |
169 | #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ | |
170 | #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ | |
171 | #define UTS_TXFULL (1<<4) /* TxFIFO full */ | |
172 | #define UTS_RXFULL (1<<3) /* RxFIFO full */ | |
173 | #define UTS_SOFTRST (1<<0) /* Software reset */ | |
ff4bfb21 | 174 | |
1da177e4 | 175 | /* We've been assigned a range on the "Low-density serial ports" major */ |
82313e66 SK |
176 | #define SERIAL_IMX_MAJOR 207 |
177 | #define MINOR_START 16 | |
e3d13ff4 | 178 | #define DEV_NAME "ttymxc" |
1da177e4 | 179 | |
1da177e4 LT |
180 | /* |
181 | * This determines how often we check the modem status signals | |
182 | * for any change. They generally aren't connected to an IRQ | |
183 | * so we have to poll them. We also check immediately before | |
184 | * filling the TX fifo incase CTS has been dropped. | |
185 | */ | |
186 | #define MCTRL_TIMEOUT (250*HZ/1000) | |
187 | ||
188 | #define DRIVER_NAME "IMX-uart" | |
189 | ||
dbff4e9e SH |
190 | #define UART_NR 8 |
191 | ||
fe6b540a SG |
192 | /* i.mx21 type uart runs on all i.mx except i.mx1 */ |
193 | enum imx_uart_type { | |
194 | IMX1_UART, | |
195 | IMX21_UART, | |
a496e628 | 196 | IMX6Q_UART, |
fe6b540a SG |
197 | }; |
198 | ||
199 | /* device type dependent stuff */ | |
200 | struct imx_uart_data { | |
201 | unsigned uts_reg; | |
202 | enum imx_uart_type devtype; | |
203 | }; | |
204 | ||
1da177e4 LT |
205 | struct imx_port { |
206 | struct uart_port port; | |
207 | struct timer_list timer; | |
208 | unsigned int old_status; | |
82313e66 | 209 | int txirq, rxirq, rtsirq; |
26bbb3ff | 210 | unsigned int have_rtscts:1; |
20ff2fe6 | 211 | unsigned int dte_mode:1; |
b6e49138 FG |
212 | unsigned int use_irda:1; |
213 | unsigned int irda_inv_rx:1; | |
214 | unsigned int irda_inv_tx:1; | |
215 | unsigned short trcv_delay; /* transceiver delay */ | |
3a9465fa SH |
216 | struct clk *clk_ipg; |
217 | struct clk *clk_per; | |
7d0b066f | 218 | const struct imx_uart_data *devdata; |
b4cdc8f6 HS |
219 | |
220 | /* DMA fields */ | |
221 | unsigned int dma_is_inited:1; | |
222 | unsigned int dma_is_enabled:1; | |
223 | unsigned int dma_is_rxing:1; | |
224 | unsigned int dma_is_txing:1; | |
225 | struct dma_chan *dma_chan_rx, *dma_chan_tx; | |
226 | struct scatterlist rx_sgl, tx_sgl[2]; | |
227 | void *rx_buf; | |
7cb92fd2 | 228 | unsigned int tx_bytes; |
b4cdc8f6 | 229 | unsigned int dma_tx_nents; |
9ce4f8f3 | 230 | wait_queue_head_t dma_wait; |
1da177e4 LT |
231 | }; |
232 | ||
0ad5a814 DB |
233 | struct imx_port_ucrs { |
234 | unsigned int ucr1; | |
235 | unsigned int ucr2; | |
236 | unsigned int ucr3; | |
237 | }; | |
238 | ||
b6e49138 FG |
239 | #ifdef CONFIG_IRDA |
240 | #define USE_IRDA(sport) ((sport)->use_irda) | |
241 | #else | |
242 | #define USE_IRDA(sport) (0) | |
243 | #endif | |
244 | ||
fe6b540a SG |
245 | static struct imx_uart_data imx_uart_devdata[] = { |
246 | [IMX1_UART] = { | |
247 | .uts_reg = IMX1_UTS, | |
248 | .devtype = IMX1_UART, | |
249 | }, | |
250 | [IMX21_UART] = { | |
251 | .uts_reg = IMX21_UTS, | |
252 | .devtype = IMX21_UART, | |
253 | }, | |
a496e628 HS |
254 | [IMX6Q_UART] = { |
255 | .uts_reg = IMX21_UTS, | |
256 | .devtype = IMX6Q_UART, | |
257 | }, | |
fe6b540a SG |
258 | }; |
259 | ||
260 | static struct platform_device_id imx_uart_devtype[] = { | |
261 | { | |
262 | .name = "imx1-uart", | |
263 | .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART], | |
264 | }, { | |
265 | .name = "imx21-uart", | |
266 | .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART], | |
a496e628 HS |
267 | }, { |
268 | .name = "imx6q-uart", | |
269 | .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART], | |
fe6b540a SG |
270 | }, { |
271 | /* sentinel */ | |
272 | } | |
273 | }; | |
274 | MODULE_DEVICE_TABLE(platform, imx_uart_devtype); | |
275 | ||
ad3d4fdc | 276 | static const struct of_device_id imx_uart_dt_ids[] = { |
a496e628 | 277 | { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, |
22698aa2 SG |
278 | { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, |
279 | { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, | |
280 | { /* sentinel */ } | |
281 | }; | |
282 | MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); | |
283 | ||
fe6b540a SG |
284 | static inline unsigned uts_reg(struct imx_port *sport) |
285 | { | |
286 | return sport->devdata->uts_reg; | |
287 | } | |
288 | ||
289 | static inline int is_imx1_uart(struct imx_port *sport) | |
290 | { | |
291 | return sport->devdata->devtype == IMX1_UART; | |
292 | } | |
293 | ||
294 | static inline int is_imx21_uart(struct imx_port *sport) | |
295 | { | |
296 | return sport->devdata->devtype == IMX21_UART; | |
297 | } | |
298 | ||
a496e628 HS |
299 | static inline int is_imx6q_uart(struct imx_port *sport) |
300 | { | |
301 | return sport->devdata->devtype == IMX6Q_UART; | |
302 | } | |
44a75411 | 303 | /* |
304 | * Save and restore functions for UCR1, UCR2 and UCR3 registers | |
305 | */ | |
93d94b37 | 306 | #if defined(CONFIG_SERIAL_IMX_CONSOLE) |
44a75411 | 307 | static void imx_port_ucrs_save(struct uart_port *port, |
308 | struct imx_port_ucrs *ucr) | |
309 | { | |
310 | /* save control registers */ | |
311 | ucr->ucr1 = readl(port->membase + UCR1); | |
312 | ucr->ucr2 = readl(port->membase + UCR2); | |
313 | ucr->ucr3 = readl(port->membase + UCR3); | |
314 | } | |
315 | ||
316 | static void imx_port_ucrs_restore(struct uart_port *port, | |
317 | struct imx_port_ucrs *ucr) | |
318 | { | |
319 | /* restore control registers */ | |
320 | writel(ucr->ucr1, port->membase + UCR1); | |
321 | writel(ucr->ucr2, port->membase + UCR2); | |
322 | writel(ucr->ucr3, port->membase + UCR3); | |
323 | } | |
e8bfa760 | 324 | #endif |
44a75411 | 325 | |
1da177e4 LT |
326 | /* |
327 | * Handle any change of modem status signal since we were last called. | |
328 | */ | |
329 | static void imx_mctrl_check(struct imx_port *sport) | |
330 | { | |
331 | unsigned int status, changed; | |
332 | ||
333 | status = sport->port.ops->get_mctrl(&sport->port); | |
334 | changed = status ^ sport->old_status; | |
335 | ||
336 | if (changed == 0) | |
337 | return; | |
338 | ||
339 | sport->old_status = status; | |
340 | ||
341 | if (changed & TIOCM_RI) | |
342 | sport->port.icount.rng++; | |
343 | if (changed & TIOCM_DSR) | |
344 | sport->port.icount.dsr++; | |
345 | if (changed & TIOCM_CAR) | |
346 | uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); | |
347 | if (changed & TIOCM_CTS) | |
348 | uart_handle_cts_change(&sport->port, status & TIOCM_CTS); | |
349 | ||
bdc04e31 | 350 | wake_up_interruptible(&sport->port.state->port.delta_msr_wait); |
1da177e4 LT |
351 | } |
352 | ||
353 | /* | |
354 | * This is our per-port timeout handler, for checking the | |
355 | * modem status signals. | |
356 | */ | |
357 | static void imx_timeout(unsigned long data) | |
358 | { | |
359 | struct imx_port *sport = (struct imx_port *)data; | |
360 | unsigned long flags; | |
361 | ||
ebd2c8f6 | 362 | if (sport->port.state) { |
1da177e4 LT |
363 | spin_lock_irqsave(&sport->port.lock, flags); |
364 | imx_mctrl_check(sport); | |
365 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
366 | ||
367 | mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); | |
368 | } | |
369 | } | |
370 | ||
371 | /* | |
372 | * interrupts disabled on entry | |
373 | */ | |
b129a8cc | 374 | static void imx_stop_tx(struct uart_port *port) |
1da177e4 LT |
375 | { |
376 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 SH |
377 | unsigned long temp; |
378 | ||
b6e49138 FG |
379 | if (USE_IRDA(sport)) { |
380 | /* half duplex - wait for end of transmission */ | |
381 | int n = 256; | |
382 | while ((--n > 0) && | |
383 | !(readl(sport->port.membase + USR2) & USR2_TXDC)) { | |
384 | udelay(5); | |
385 | barrier(); | |
386 | } | |
387 | /* | |
388 | * irda transceiver - wait a bit more to avoid | |
389 | * cutoff, hardware dependent | |
390 | */ | |
391 | udelay(sport->trcv_delay); | |
392 | ||
393 | /* | |
394 | * half duplex - reactivate receive mode, | |
395 | * flush receive pipe echo crap | |
396 | */ | |
397 | if (readl(sport->port.membase + USR2) & USR2_TXDC) { | |
398 | temp = readl(sport->port.membase + UCR1); | |
399 | temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN); | |
400 | writel(temp, sport->port.membase + UCR1); | |
401 | ||
402 | temp = readl(sport->port.membase + UCR4); | |
403 | temp &= ~(UCR4_TCEN); | |
404 | writel(temp, sport->port.membase + UCR4); | |
405 | ||
406 | while (readl(sport->port.membase + URXD0) & | |
407 | URXD_CHARRDY) | |
408 | barrier(); | |
409 | ||
410 | temp = readl(sport->port.membase + UCR1); | |
411 | temp |= UCR1_RRDYEN; | |
412 | writel(temp, sport->port.membase + UCR1); | |
413 | ||
414 | temp = readl(sport->port.membase + UCR4); | |
415 | temp |= UCR4_DREN; | |
416 | writel(temp, sport->port.membase + UCR4); | |
417 | } | |
418 | return; | |
419 | } | |
420 | ||
9ce4f8f3 GKH |
421 | /* |
422 | * We are maybe in the SMP context, so if the DMA TX thread is running | |
423 | * on other cpu, we have to wait for it to finish. | |
424 | */ | |
425 | if (sport->dma_is_enabled && sport->dma_is_txing) | |
426 | return; | |
b4cdc8f6 | 427 | |
ff4bfb21 SH |
428 | temp = readl(sport->port.membase + UCR1); |
429 | writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1); | |
1da177e4 LT |
430 | } |
431 | ||
432 | /* | |
433 | * interrupts disabled on entry | |
434 | */ | |
435 | static void imx_stop_rx(struct uart_port *port) | |
436 | { | |
437 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 SH |
438 | unsigned long temp; |
439 | ||
45564a66 HS |
440 | if (sport->dma_is_enabled && sport->dma_is_rxing) { |
441 | if (sport->port.suspended) { | |
442 | dmaengine_terminate_all(sport->dma_chan_rx); | |
443 | sport->dma_is_rxing = 0; | |
444 | } else { | |
445 | return; | |
446 | } | |
447 | } | |
b4cdc8f6 | 448 | |
ff4bfb21 | 449 | temp = readl(sport->port.membase + UCR2); |
82313e66 | 450 | writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); |
85878399 HS |
451 | |
452 | /* disable the `Receiver Ready Interrrupt` */ | |
453 | temp = readl(sport->port.membase + UCR1); | |
454 | writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); | |
1da177e4 LT |
455 | } |
456 | ||
457 | /* | |
458 | * Set the modem control timer to fire immediately. | |
459 | */ | |
460 | static void imx_enable_ms(struct uart_port *port) | |
461 | { | |
462 | struct imx_port *sport = (struct imx_port *)port; | |
463 | ||
464 | mod_timer(&sport->timer, jiffies); | |
465 | } | |
466 | ||
91a1a909 | 467 | static void imx_dma_tx(struct imx_port *sport); |
1da177e4 LT |
468 | static inline void imx_transmit_buffer(struct imx_port *sport) |
469 | { | |
ebd2c8f6 | 470 | struct circ_buf *xmit = &sport->port.state->xmit; |
91a1a909 | 471 | unsigned long temp; |
1da177e4 | 472 | |
5e42e9a3 PH |
473 | if (sport->port.x_char) { |
474 | /* Send next char */ | |
475 | writel(sport->port.x_char, sport->port.membase + URTX0); | |
7e2fb5aa JW |
476 | sport->port.icount.tx++; |
477 | sport->port.x_char = 0; | |
5e42e9a3 PH |
478 | return; |
479 | } | |
480 | ||
481 | if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { | |
482 | imx_stop_tx(&sport->port); | |
483 | return; | |
484 | } | |
485 | ||
91a1a909 JW |
486 | if (sport->dma_is_enabled) { |
487 | /* | |
488 | * We've just sent a X-char Ensure the TX DMA is enabled | |
489 | * and the TX IRQ is disabled. | |
490 | **/ | |
491 | temp = readl(sport->port.membase + UCR1); | |
492 | temp &= ~UCR1_TXMPTYEN; | |
493 | if (sport->dma_is_txing) { | |
494 | temp |= UCR1_TDMAEN; | |
495 | writel(temp, sport->port.membase + UCR1); | |
496 | } else { | |
497 | writel(temp, sport->port.membase + UCR1); | |
498 | imx_dma_tx(sport); | |
499 | } | |
500 | } | |
501 | ||
4e4e6602 | 502 | while (!uart_circ_empty(xmit) && |
5e42e9a3 | 503 | !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) { |
1da177e4 LT |
504 | /* send xmit->buf[xmit->tail] |
505 | * out the port here */ | |
ff4bfb21 | 506 | writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); |
d3810cd4 | 507 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
1da177e4 | 508 | sport->port.icount.tx++; |
8c0b254b | 509 | } |
1da177e4 | 510 | |
97775731 FG |
511 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
512 | uart_write_wakeup(&sport->port); | |
513 | ||
1da177e4 | 514 | if (uart_circ_empty(xmit)) |
b129a8cc | 515 | imx_stop_tx(&sport->port); |
1da177e4 LT |
516 | } |
517 | ||
b4cdc8f6 HS |
518 | static void dma_tx_callback(void *data) |
519 | { | |
520 | struct imx_port *sport = data; | |
521 | struct scatterlist *sgl = &sport->tx_sgl[0]; | |
522 | struct circ_buf *xmit = &sport->port.state->xmit; | |
523 | unsigned long flags; | |
a2c718ce | 524 | unsigned long temp; |
b4cdc8f6 | 525 | |
42f752b3 | 526 | spin_lock_irqsave(&sport->port.lock, flags); |
b4cdc8f6 | 527 | |
42f752b3 | 528 | dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); |
b4cdc8f6 | 529 | |
a2c718ce DB |
530 | temp = readl(sport->port.membase + UCR1); |
531 | temp &= ~UCR1_TDMAEN; | |
532 | writel(temp, sport->port.membase + UCR1); | |
533 | ||
b4cdc8f6 | 534 | /* update the stat */ |
b4cdc8f6 HS |
535 | xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1); |
536 | sport->port.icount.tx += sport->tx_bytes; | |
b4cdc8f6 HS |
537 | |
538 | dev_dbg(sport->port.dev, "we finish the TX DMA.\n"); | |
539 | ||
42f752b3 DB |
540 | sport->dma_is_txing = 0; |
541 | ||
542 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
543 | ||
d64b8607 JW |
544 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
545 | uart_write_wakeup(&sport->port); | |
9ce4f8f3 GKH |
546 | |
547 | if (waitqueue_active(&sport->dma_wait)) { | |
548 | wake_up(&sport->dma_wait); | |
549 | dev_dbg(sport->port.dev, "exit in %s.\n", __func__); | |
550 | return; | |
551 | } | |
0bbc9b81 JW |
552 | |
553 | spin_lock_irqsave(&sport->port.lock, flags); | |
554 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) | |
555 | imx_dma_tx(sport); | |
556 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
b4cdc8f6 HS |
557 | } |
558 | ||
7cb92fd2 | 559 | static void imx_dma_tx(struct imx_port *sport) |
b4cdc8f6 | 560 | { |
b4cdc8f6 HS |
561 | struct circ_buf *xmit = &sport->port.state->xmit; |
562 | struct scatterlist *sgl = sport->tx_sgl; | |
563 | struct dma_async_tx_descriptor *desc; | |
564 | struct dma_chan *chan = sport->dma_chan_tx; | |
565 | struct device *dev = sport->port.dev; | |
a2c718ce | 566 | unsigned long temp; |
b4cdc8f6 HS |
567 | int ret; |
568 | ||
42f752b3 | 569 | if (sport->dma_is_txing) |
b4cdc8f6 HS |
570 | return; |
571 | ||
b4cdc8f6 | 572 | sport->tx_bytes = uart_circ_chars_pending(xmit); |
b4cdc8f6 | 573 | |
7942f857 DB |
574 | if (xmit->tail < xmit->head) { |
575 | sport->dma_tx_nents = 1; | |
576 | sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes); | |
577 | } else { | |
b4cdc8f6 HS |
578 | sport->dma_tx_nents = 2; |
579 | sg_init_table(sgl, 2); | |
580 | sg_set_buf(sgl, xmit->buf + xmit->tail, | |
581 | UART_XMIT_SIZE - xmit->tail); | |
582 | sg_set_buf(sgl + 1, xmit->buf, xmit->head); | |
b4cdc8f6 | 583 | } |
b4cdc8f6 HS |
584 | |
585 | ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); | |
586 | if (ret == 0) { | |
587 | dev_err(dev, "DMA mapping error for TX.\n"); | |
588 | return; | |
589 | } | |
590 | desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents, | |
591 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); | |
592 | if (!desc) { | |
24649821 DB |
593 | dma_unmap_sg(dev, sgl, sport->dma_tx_nents, |
594 | DMA_TO_DEVICE); | |
b4cdc8f6 HS |
595 | dev_err(dev, "We cannot prepare for the TX slave dma!\n"); |
596 | return; | |
597 | } | |
598 | desc->callback = dma_tx_callback; | |
599 | desc->callback_param = sport; | |
600 | ||
601 | dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n", | |
602 | uart_circ_chars_pending(xmit)); | |
a2c718ce DB |
603 | |
604 | temp = readl(sport->port.membase + UCR1); | |
605 | temp |= UCR1_TDMAEN; | |
606 | writel(temp, sport->port.membase + UCR1); | |
607 | ||
b4cdc8f6 HS |
608 | /* fire it */ |
609 | sport->dma_is_txing = 1; | |
610 | dmaengine_submit(desc); | |
611 | dma_async_issue_pending(chan); | |
612 | return; | |
613 | } | |
614 | ||
1da177e4 LT |
615 | /* |
616 | * interrupts disabled on entry | |
617 | */ | |
b129a8cc | 618 | static void imx_start_tx(struct uart_port *port) |
1da177e4 LT |
619 | { |
620 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 | 621 | unsigned long temp; |
1da177e4 | 622 | |
b6e49138 FG |
623 | if (USE_IRDA(sport)) { |
624 | /* half duplex in IrDA mode; have to disable receive mode */ | |
625 | temp = readl(sport->port.membase + UCR4); | |
626 | temp &= ~(UCR4_DREN); | |
627 | writel(temp, sport->port.membase + UCR4); | |
628 | ||
629 | temp = readl(sport->port.membase + UCR1); | |
630 | temp &= ~(UCR1_RRDYEN); | |
631 | writel(temp, sport->port.membase + UCR1); | |
632 | } | |
633 | ||
b4cdc8f6 HS |
634 | if (!sport->dma_is_enabled) { |
635 | temp = readl(sport->port.membase + UCR1); | |
636 | writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); | |
637 | } | |
1da177e4 | 638 | |
b6e49138 FG |
639 | if (USE_IRDA(sport)) { |
640 | temp = readl(sport->port.membase + UCR1); | |
641 | temp |= UCR1_TRDYEN; | |
642 | writel(temp, sport->port.membase + UCR1); | |
643 | ||
644 | temp = readl(sport->port.membase + UCR4); | |
645 | temp |= UCR4_TCEN; | |
646 | writel(temp, sport->port.membase + UCR4); | |
647 | } | |
648 | ||
b4cdc8f6 | 649 | if (sport->dma_is_enabled) { |
91a1a909 JW |
650 | if (sport->port.x_char) { |
651 | /* We have X-char to send, so enable TX IRQ and | |
652 | * disable TX DMA to let TX interrupt to send X-char */ | |
653 | temp = readl(sport->port.membase + UCR1); | |
654 | temp &= ~UCR1_TDMAEN; | |
655 | temp |= UCR1_TXMPTYEN; | |
656 | writel(temp, sport->port.membase + UCR1); | |
657 | return; | |
658 | } | |
659 | ||
5e42e9a3 PH |
660 | if (!uart_circ_empty(&port->state->xmit) && |
661 | !uart_tx_stopped(port)) | |
662 | imx_dma_tx(sport); | |
b4cdc8f6 HS |
663 | return; |
664 | } | |
1da177e4 LT |
665 | } |
666 | ||
7d12e780 | 667 | static irqreturn_t imx_rtsint(int irq, void *dev_id) |
ceca629e | 668 | { |
15aafa2f | 669 | struct imx_port *sport = dev_id; |
5680e941 | 670 | unsigned int val; |
ceca629e SH |
671 | unsigned long flags; |
672 | ||
673 | spin_lock_irqsave(&sport->port.lock, flags); | |
674 | ||
ff4bfb21 | 675 | writel(USR1_RTSD, sport->port.membase + USR1); |
5680e941 | 676 | val = readl(sport->port.membase + USR1) & USR1_RTSS; |
ceca629e | 677 | uart_handle_cts_change(&sport->port, !!val); |
bdc04e31 | 678 | wake_up_interruptible(&sport->port.state->port.delta_msr_wait); |
ceca629e SH |
679 | |
680 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
681 | return IRQ_HANDLED; | |
682 | } | |
683 | ||
7d12e780 | 684 | static irqreturn_t imx_txint(int irq, void *dev_id) |
1da177e4 | 685 | { |
15aafa2f | 686 | struct imx_port *sport = dev_id; |
1da177e4 LT |
687 | unsigned long flags; |
688 | ||
82313e66 | 689 | spin_lock_irqsave(&sport->port.lock, flags); |
1da177e4 | 690 | imx_transmit_buffer(sport); |
82313e66 | 691 | spin_unlock_irqrestore(&sport->port.lock, flags); |
1da177e4 LT |
692 | return IRQ_HANDLED; |
693 | } | |
694 | ||
7d12e780 | 695 | static irqreturn_t imx_rxint(int irq, void *dev_id) |
1da177e4 LT |
696 | { |
697 | struct imx_port *sport = dev_id; | |
82313e66 | 698 | unsigned int rx, flg, ignored = 0; |
92a19f9c | 699 | struct tty_port *port = &sport->port.state->port; |
ff4bfb21 | 700 | unsigned long flags, temp; |
1da177e4 | 701 | |
82313e66 | 702 | spin_lock_irqsave(&sport->port.lock, flags); |
1da177e4 | 703 | |
0d3c3938 | 704 | while (readl(sport->port.membase + USR2) & USR2_RDR) { |
1da177e4 LT |
705 | flg = TTY_NORMAL; |
706 | sport->port.icount.rx++; | |
707 | ||
0d3c3938 SH |
708 | rx = readl(sport->port.membase + URXD0); |
709 | ||
ff4bfb21 | 710 | temp = readl(sport->port.membase + USR2); |
864eeed0 | 711 | if (temp & USR2_BRCD) { |
94d32f99 | 712 | writel(USR2_BRCD, sport->port.membase + USR2); |
864eeed0 SH |
713 | if (uart_handle_break(&sport->port)) |
714 | continue; | |
1da177e4 LT |
715 | } |
716 | ||
d3810cd4 | 717 | if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) |
864eeed0 SH |
718 | continue; |
719 | ||
019dc9ea HW |
720 | if (unlikely(rx & URXD_ERR)) { |
721 | if (rx & URXD_BRK) | |
722 | sport->port.icount.brk++; | |
723 | else if (rx & URXD_PRERR) | |
864eeed0 SH |
724 | sport->port.icount.parity++; |
725 | else if (rx & URXD_FRMERR) | |
726 | sport->port.icount.frame++; | |
727 | if (rx & URXD_OVRRUN) | |
728 | sport->port.icount.overrun++; | |
729 | ||
730 | if (rx & sport->port.ignore_status_mask) { | |
731 | if (++ignored > 100) | |
732 | goto out; | |
733 | continue; | |
734 | } | |
735 | ||
8d267fd9 | 736 | rx &= (sport->port.read_status_mask | 0xFF); |
864eeed0 | 737 | |
019dc9ea HW |
738 | if (rx & URXD_BRK) |
739 | flg = TTY_BREAK; | |
740 | else if (rx & URXD_PRERR) | |
864eeed0 SH |
741 | flg = TTY_PARITY; |
742 | else if (rx & URXD_FRMERR) | |
743 | flg = TTY_FRAME; | |
744 | if (rx & URXD_OVRRUN) | |
745 | flg = TTY_OVERRUN; | |
1da177e4 | 746 | |
864eeed0 SH |
747 | #ifdef SUPPORT_SYSRQ |
748 | sport->port.sysrq = 0; | |
749 | #endif | |
750 | } | |
1da177e4 | 751 | |
55d8693a JW |
752 | if (sport->port.ignore_status_mask & URXD_DUMMY_READ) |
753 | goto out; | |
754 | ||
92a19f9c | 755 | tty_insert_flip_char(port, rx, flg); |
864eeed0 | 756 | } |
1da177e4 LT |
757 | |
758 | out: | |
82313e66 | 759 | spin_unlock_irqrestore(&sport->port.lock, flags); |
2e124b4a | 760 | tty_flip_buffer_push(port); |
1da177e4 | 761 | return IRQ_HANDLED; |
1da177e4 LT |
762 | } |
763 | ||
7cb92fd2 | 764 | static int start_rx_dma(struct imx_port *sport); |
b4cdc8f6 HS |
765 | /* |
766 | * If the RXFIFO is filled with some data, and then we | |
767 | * arise a DMA operation to receive them. | |
768 | */ | |
769 | static void imx_dma_rxint(struct imx_port *sport) | |
770 | { | |
771 | unsigned long temp; | |
73631813 JW |
772 | unsigned long flags; |
773 | ||
774 | spin_lock_irqsave(&sport->port.lock, flags); | |
b4cdc8f6 HS |
775 | |
776 | temp = readl(sport->port.membase + USR2); | |
777 | if ((temp & USR2_RDR) && !sport->dma_is_rxing) { | |
778 | sport->dma_is_rxing = 1; | |
779 | ||
780 | /* disable the `Recerver Ready Interrrupt` */ | |
781 | temp = readl(sport->port.membase + UCR1); | |
782 | temp &= ~(UCR1_RRDYEN); | |
783 | writel(temp, sport->port.membase + UCR1); | |
784 | ||
785 | /* tell the DMA to receive the data. */ | |
7cb92fd2 | 786 | start_rx_dma(sport); |
b4cdc8f6 | 787 | } |
73631813 JW |
788 | |
789 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
b4cdc8f6 HS |
790 | } |
791 | ||
e3d13ff4 SH |
792 | static irqreturn_t imx_int(int irq, void *dev_id) |
793 | { | |
794 | struct imx_port *sport = dev_id; | |
795 | unsigned int sts; | |
f1f836e4 | 796 | unsigned int sts2; |
e3d13ff4 SH |
797 | |
798 | sts = readl(sport->port.membase + USR1); | |
799 | ||
b4cdc8f6 HS |
800 | if (sts & USR1_RRDY) { |
801 | if (sport->dma_is_enabled) | |
802 | imx_dma_rxint(sport); | |
803 | else | |
804 | imx_rxint(irq, dev_id); | |
805 | } | |
e3d13ff4 SH |
806 | |
807 | if (sts & USR1_TRDY && | |
808 | readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) | |
809 | imx_txint(irq, dev_id); | |
810 | ||
9fbe6044 | 811 | if (sts & USR1_RTSD) |
e3d13ff4 SH |
812 | imx_rtsint(irq, dev_id); |
813 | ||
db1a9b55 FE |
814 | if (sts & USR1_AWAKE) |
815 | writel(USR1_AWAKE, sport->port.membase + USR1); | |
816 | ||
f1f836e4 AS |
817 | sts2 = readl(sport->port.membase + USR2); |
818 | if (sts2 & USR2_ORE) { | |
819 | dev_err(sport->port.dev, "Rx FIFO overrun\n"); | |
820 | sport->port.icount.overrun++; | |
91555ce9 | 821 | writel(USR2_ORE, sport->port.membase + USR2); |
f1f836e4 AS |
822 | } |
823 | ||
e3d13ff4 SH |
824 | return IRQ_HANDLED; |
825 | } | |
826 | ||
1da177e4 LT |
827 | /* |
828 | * Return TIOCSER_TEMT when transmitter is not busy. | |
829 | */ | |
830 | static unsigned int imx_tx_empty(struct uart_port *port) | |
831 | { | |
832 | struct imx_port *sport = (struct imx_port *)port; | |
1ce43e58 | 833 | unsigned int ret; |
1da177e4 | 834 | |
1ce43e58 | 835 | ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0; |
1da177e4 | 836 | |
1ce43e58 HS |
837 | /* If the TX DMA is working, return 0. */ |
838 | if (sport->dma_is_enabled && sport->dma_is_txing) | |
839 | ret = 0; | |
840 | ||
841 | return ret; | |
1da177e4 LT |
842 | } |
843 | ||
0f302dc3 SH |
844 | /* |
845 | * We have a modem side uart, so the meanings of RTS and CTS are inverted. | |
846 | */ | |
1da177e4 LT |
847 | static unsigned int imx_get_mctrl(struct uart_port *port) |
848 | { | |
d3810cd4 OS |
849 | struct imx_port *sport = (struct imx_port *)port; |
850 | unsigned int tmp = TIOCM_DSR | TIOCM_CAR; | |
0f302dc3 | 851 | |
d3810cd4 OS |
852 | if (readl(sport->port.membase + USR1) & USR1_RTSS) |
853 | tmp |= TIOCM_CTS; | |
0f302dc3 | 854 | |
d3810cd4 OS |
855 | if (readl(sport->port.membase + UCR2) & UCR2_CTS) |
856 | tmp |= TIOCM_RTS; | |
0f302dc3 | 857 | |
6b471a98 HS |
858 | if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP) |
859 | tmp |= TIOCM_LOOP; | |
860 | ||
d3810cd4 | 861 | return tmp; |
1da177e4 LT |
862 | } |
863 | ||
864 | static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
865 | { | |
d3810cd4 | 866 | struct imx_port *sport = (struct imx_port *)port; |
ff4bfb21 SH |
867 | unsigned long temp; |
868 | ||
bb2f861a | 869 | temp = readl(sport->port.membase + UCR2) & ~(UCR2_CTS | UCR2_CTSC); |
d3810cd4 | 870 | if (mctrl & TIOCM_RTS) |
bb2f861a | 871 | temp |= UCR2_CTS | UCR2_CTSC; |
ff4bfb21 SH |
872 | |
873 | writel(temp, sport->port.membase + UCR2); | |
6b471a98 HS |
874 | |
875 | temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; | |
876 | if (mctrl & TIOCM_LOOP) | |
877 | temp |= UTS_LOOP; | |
878 | writel(temp, sport->port.membase + uts_reg(sport)); | |
1da177e4 LT |
879 | } |
880 | ||
881 | /* | |
882 | * Interrupts always disabled. | |
883 | */ | |
884 | static void imx_break_ctl(struct uart_port *port, int break_state) | |
885 | { | |
886 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 | 887 | unsigned long flags, temp; |
1da177e4 LT |
888 | |
889 | spin_lock_irqsave(&sport->port.lock, flags); | |
890 | ||
ff4bfb21 SH |
891 | temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK; |
892 | ||
82313e66 | 893 | if (break_state != 0) |
ff4bfb21 SH |
894 | temp |= UCR1_SNDBRK; |
895 | ||
896 | writel(temp, sport->port.membase + UCR1); | |
1da177e4 LT |
897 | |
898 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
899 | } | |
900 | ||
901 | #define TXTL 2 /* reset default */ | |
902 | #define RXTL 1 /* reset default */ | |
903 | ||
587897f5 SH |
904 | static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode) |
905 | { | |
906 | unsigned int val; | |
587897f5 | 907 | |
7be0670f DB |
908 | /* set receiver / transmitter trigger level */ |
909 | val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE); | |
910 | val |= TXTL << UFCR_TXTL_SHF | RXTL; | |
ff4bfb21 | 911 | writel(val, sport->port.membase + UFCR); |
587897f5 SH |
912 | return 0; |
913 | } | |
914 | ||
b4cdc8f6 | 915 | #define RX_BUF_SIZE (PAGE_SIZE) |
b4cdc8f6 HS |
916 | static void imx_rx_dma_done(struct imx_port *sport) |
917 | { | |
918 | unsigned long temp; | |
73631813 JW |
919 | unsigned long flags; |
920 | ||
921 | spin_lock_irqsave(&sport->port.lock, flags); | |
b4cdc8f6 HS |
922 | |
923 | /* Enable this interrupt when the RXFIFO is empty. */ | |
924 | temp = readl(sport->port.membase + UCR1); | |
925 | temp |= UCR1_RRDYEN; | |
926 | writel(temp, sport->port.membase + UCR1); | |
927 | ||
928 | sport->dma_is_rxing = 0; | |
9ce4f8f3 GKH |
929 | |
930 | /* Is the shutdown waiting for us? */ | |
931 | if (waitqueue_active(&sport->dma_wait)) | |
932 | wake_up(&sport->dma_wait); | |
73631813 JW |
933 | |
934 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
b4cdc8f6 HS |
935 | } |
936 | ||
937 | /* | |
938 | * There are three kinds of RX DMA interrupts(such as in the MX6Q): | |
939 | * [1] the RX DMA buffer is full. | |
940 | * [2] the Aging timer expires(wait for 8 bytes long) | |
941 | * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN). | |
942 | * | |
943 | * The [2] is trigger when a character was been sitting in the FIFO | |
944 | * meanwhile [3] can wait for 32 bytes long when the RX line is | |
945 | * on IDLE state and RxFIFO is empty. | |
946 | */ | |
947 | static void dma_rx_callback(void *data) | |
948 | { | |
949 | struct imx_port *sport = data; | |
950 | struct dma_chan *chan = sport->dma_chan_rx; | |
951 | struct scatterlist *sgl = &sport->rx_sgl; | |
7cb92fd2 | 952 | struct tty_port *port = &sport->port.state->port; |
b4cdc8f6 HS |
953 | struct dma_tx_state state; |
954 | enum dma_status status; | |
955 | unsigned int count; | |
956 | ||
957 | /* unmap it first */ | |
958 | dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE); | |
959 | ||
f0ef8834 | 960 | status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state); |
b4cdc8f6 HS |
961 | count = RX_BUF_SIZE - state.residue; |
962 | dev_dbg(sport->port.dev, "We get %d bytes.\n", count); | |
963 | ||
964 | if (count) { | |
55d8693a JW |
965 | if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) |
966 | tty_insert_flip_string(port, sport->rx_buf, count); | |
7cb92fd2 HS |
967 | tty_flip_buffer_push(port); |
968 | ||
969 | start_rx_dma(sport); | |
ee5e7c10 RG |
970 | } else if (readl(sport->port.membase + USR2) & USR2_RDR) { |
971 | /* | |
972 | * start rx_dma directly once data in RXFIFO, more efficient | |
973 | * than before: | |
974 | * 1. call imx_rx_dma_done to stop dma if no data received | |
975 | * 2. wait next RDR interrupt to start dma transfer. | |
976 | */ | |
977 | start_rx_dma(sport); | |
978 | } else { | |
979 | /* | |
980 | * stop dma to prevent too many IDLE event trigged if no data | |
981 | * in RXFIFO | |
982 | */ | |
b4cdc8f6 | 983 | imx_rx_dma_done(sport); |
ee5e7c10 | 984 | } |
b4cdc8f6 HS |
985 | } |
986 | ||
987 | static int start_rx_dma(struct imx_port *sport) | |
988 | { | |
989 | struct scatterlist *sgl = &sport->rx_sgl; | |
990 | struct dma_chan *chan = sport->dma_chan_rx; | |
991 | struct device *dev = sport->port.dev; | |
992 | struct dma_async_tx_descriptor *desc; | |
993 | int ret; | |
994 | ||
995 | sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE); | |
996 | ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE); | |
997 | if (ret == 0) { | |
998 | dev_err(dev, "DMA mapping error for RX.\n"); | |
999 | return -EINVAL; | |
1000 | } | |
1001 | desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM, | |
1002 | DMA_PREP_INTERRUPT); | |
1003 | if (!desc) { | |
24649821 | 1004 | dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE); |
b4cdc8f6 HS |
1005 | dev_err(dev, "We cannot prepare for the RX slave dma!\n"); |
1006 | return -EINVAL; | |
1007 | } | |
1008 | desc->callback = dma_rx_callback; | |
1009 | desc->callback_param = sport; | |
1010 | ||
1011 | dev_dbg(dev, "RX: prepare for the DMA.\n"); | |
1012 | dmaengine_submit(desc); | |
1013 | dma_async_issue_pending(chan); | |
1014 | return 0; | |
1015 | } | |
1016 | ||
1017 | static void imx_uart_dma_exit(struct imx_port *sport) | |
1018 | { | |
1019 | if (sport->dma_chan_rx) { | |
1020 | dma_release_channel(sport->dma_chan_rx); | |
1021 | sport->dma_chan_rx = NULL; | |
1022 | ||
1023 | kfree(sport->rx_buf); | |
1024 | sport->rx_buf = NULL; | |
1025 | } | |
1026 | ||
1027 | if (sport->dma_chan_tx) { | |
1028 | dma_release_channel(sport->dma_chan_tx); | |
1029 | sport->dma_chan_tx = NULL; | |
1030 | } | |
1031 | ||
1032 | sport->dma_is_inited = 0; | |
1033 | } | |
1034 | ||
1035 | static int imx_uart_dma_init(struct imx_port *sport) | |
1036 | { | |
b09c74ae | 1037 | struct dma_slave_config slave_config = {}; |
b4cdc8f6 HS |
1038 | struct device *dev = sport->port.dev; |
1039 | int ret; | |
1040 | ||
1041 | /* Prepare for RX : */ | |
1042 | sport->dma_chan_rx = dma_request_slave_channel(dev, "rx"); | |
1043 | if (!sport->dma_chan_rx) { | |
1044 | dev_dbg(dev, "cannot get the DMA channel.\n"); | |
1045 | ret = -EINVAL; | |
1046 | goto err; | |
1047 | } | |
1048 | ||
1049 | slave_config.direction = DMA_DEV_TO_MEM; | |
1050 | slave_config.src_addr = sport->port.mapbase + URXD0; | |
1051 | slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
1052 | slave_config.src_maxburst = RXTL; | |
1053 | ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config); | |
1054 | if (ret) { | |
1055 | dev_err(dev, "error in RX dma configuration.\n"); | |
1056 | goto err; | |
1057 | } | |
1058 | ||
1059 | sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL); | |
1060 | if (!sport->rx_buf) { | |
b4cdc8f6 HS |
1061 | ret = -ENOMEM; |
1062 | goto err; | |
1063 | } | |
b4cdc8f6 HS |
1064 | |
1065 | /* Prepare for TX : */ | |
1066 | sport->dma_chan_tx = dma_request_slave_channel(dev, "tx"); | |
1067 | if (!sport->dma_chan_tx) { | |
1068 | dev_err(dev, "cannot get the TX DMA channel!\n"); | |
1069 | ret = -EINVAL; | |
1070 | goto err; | |
1071 | } | |
1072 | ||
1073 | slave_config.direction = DMA_MEM_TO_DEV; | |
1074 | slave_config.dst_addr = sport->port.mapbase + URTX0; | |
1075 | slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
1076 | slave_config.dst_maxburst = TXTL; | |
1077 | ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config); | |
1078 | if (ret) { | |
1079 | dev_err(dev, "error in TX dma configuration."); | |
1080 | goto err; | |
1081 | } | |
1082 | ||
1083 | sport->dma_is_inited = 1; | |
1084 | ||
1085 | return 0; | |
1086 | err: | |
1087 | imx_uart_dma_exit(sport); | |
1088 | return ret; | |
1089 | } | |
1090 | ||
1091 | static void imx_enable_dma(struct imx_port *sport) | |
1092 | { | |
1093 | unsigned long temp; | |
b4cdc8f6 | 1094 | |
9ce4f8f3 GKH |
1095 | init_waitqueue_head(&sport->dma_wait); |
1096 | ||
b4cdc8f6 HS |
1097 | /* set UCR1 */ |
1098 | temp = readl(sport->port.membase + UCR1); | |
1099 | temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN | | |
1100 | /* wait for 32 idle frames for IDDMA interrupt */ | |
1101 | UCR1_ICD_REG(3); | |
1102 | writel(temp, sport->port.membase + UCR1); | |
1103 | ||
1104 | /* set UCR4 */ | |
1105 | temp = readl(sport->port.membase + UCR4); | |
1106 | temp |= UCR4_IDDMAEN; | |
1107 | writel(temp, sport->port.membase + UCR4); | |
1108 | ||
1109 | sport->dma_is_enabled = 1; | |
1110 | } | |
1111 | ||
1112 | static void imx_disable_dma(struct imx_port *sport) | |
1113 | { | |
1114 | unsigned long temp; | |
b4cdc8f6 HS |
1115 | |
1116 | /* clear UCR1 */ | |
1117 | temp = readl(sport->port.membase + UCR1); | |
1118 | temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN); | |
1119 | writel(temp, sport->port.membase + UCR1); | |
1120 | ||
1121 | /* clear UCR2 */ | |
1122 | temp = readl(sport->port.membase + UCR2); | |
1123 | temp &= ~(UCR2_CTSC | UCR2_CTS); | |
1124 | writel(temp, sport->port.membase + UCR2); | |
1125 | ||
1126 | /* clear UCR4 */ | |
1127 | temp = readl(sport->port.membase + UCR4); | |
1128 | temp &= ~UCR4_IDDMAEN; | |
1129 | writel(temp, sport->port.membase + UCR4); | |
1130 | ||
1131 | sport->dma_is_enabled = 0; | |
b4cdc8f6 HS |
1132 | } |
1133 | ||
1c5250d6 VL |
1134 | /* half the RX buffer size */ |
1135 | #define CTSTL 16 | |
1136 | ||
1da177e4 LT |
1137 | static int imx_startup(struct uart_port *port) |
1138 | { | |
1139 | struct imx_port *sport = (struct imx_port *)port; | |
772f8991 | 1140 | int retval, i; |
ff4bfb21 | 1141 | unsigned long flags, temp; |
1da177e4 | 1142 | |
1cf93e0d HS |
1143 | retval = clk_prepare_enable(sport->clk_per); |
1144 | if (retval) | |
cb0f0a5f | 1145 | return retval; |
1cf93e0d HS |
1146 | retval = clk_prepare_enable(sport->clk_ipg); |
1147 | if (retval) { | |
1148 | clk_disable_unprepare(sport->clk_per); | |
cb0f0a5f | 1149 | return retval; |
0c375501 | 1150 | } |
28eb4274 | 1151 | |
587897f5 | 1152 | imx_setup_ufcr(sport, 0); |
1da177e4 LT |
1153 | |
1154 | /* disable the DREN bit (Data Ready interrupt enable) before | |
1155 | * requesting IRQs | |
1156 | */ | |
ff4bfb21 | 1157 | temp = readl(sport->port.membase + UCR4); |
b6e49138 FG |
1158 | |
1159 | if (USE_IRDA(sport)) | |
1160 | temp |= UCR4_IRSC; | |
1161 | ||
1c5250d6 | 1162 | /* set the trigger level for CTS */ |
82313e66 SK |
1163 | temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF); |
1164 | temp |= CTSTL << UCR4_CTSTL_SHF; | |
1c5250d6 | 1165 | |
ff4bfb21 | 1166 | writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); |
1da177e4 | 1167 | |
772f8991 HS |
1168 | /* Reset fifo's and state machines */ |
1169 | i = 100; | |
1170 | ||
1171 | temp = readl(sport->port.membase + UCR2); | |
1172 | temp &= ~UCR2_SRST; | |
1173 | writel(temp, sport->port.membase + UCR2); | |
1174 | ||
1175 | while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) | |
1176 | udelay(1); | |
b6e49138 | 1177 | |
068500e0 AB |
1178 | /* Can we enable the DMA support? */ |
1179 | if (is_imx6q_uart(sport) && !uart_console(port) && | |
1180 | !sport->dma_is_inited) | |
1181 | imx_uart_dma_init(sport); | |
1182 | ||
9ec1882d | 1183 | spin_lock_irqsave(&sport->port.lock, flags); |
91555ce9 | 1184 | |
1da177e4 LT |
1185 | /* |
1186 | * Finally, clear and enable interrupts | |
1187 | */ | |
ff4bfb21 | 1188 | writel(USR1_RTSD, sport->port.membase + USR1); |
91555ce9 | 1189 | writel(USR2_ORE, sport->port.membase + USR2); |
ff4bfb21 | 1190 | |
068500e0 AB |
1191 | if (sport->dma_is_inited && !sport->dma_is_enabled) |
1192 | imx_enable_dma(sport); | |
1193 | ||
ff4bfb21 | 1194 | temp = readl(sport->port.membase + UCR1); |
789d5258 | 1195 | temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN; |
b6e49138 FG |
1196 | |
1197 | if (USE_IRDA(sport)) { | |
1198 | temp |= UCR1_IREN; | |
1199 | temp &= ~(UCR1_RTSDEN); | |
1200 | } | |
1201 | ||
ff4bfb21 | 1202 | writel(temp, sport->port.membase + UCR1); |
1da177e4 | 1203 | |
6f026d6b JW |
1204 | temp = readl(sport->port.membase + UCR4); |
1205 | temp |= UCR4_OREN; | |
1206 | writel(temp, sport->port.membase + UCR4); | |
1207 | ||
ff4bfb21 SH |
1208 | temp = readl(sport->port.membase + UCR2); |
1209 | temp |= (UCR2_RXEN | UCR2_TXEN); | |
bff09b09 LS |
1210 | if (!sport->have_rtscts) |
1211 | temp |= UCR2_IRTS; | |
ff4bfb21 | 1212 | writel(temp, sport->port.membase + UCR2); |
1da177e4 | 1213 | |
a496e628 | 1214 | if (!is_imx1_uart(sport)) { |
37d6fb62 | 1215 | temp = readl(sport->port.membase + UCR3); |
b38cb7d2 | 1216 | temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; |
37d6fb62 SH |
1217 | writel(temp, sport->port.membase + UCR3); |
1218 | } | |
4411805b | 1219 | |
b6e49138 FG |
1220 | if (USE_IRDA(sport)) { |
1221 | temp = readl(sport->port.membase + UCR4); | |
1222 | if (sport->irda_inv_rx) | |
1223 | temp |= UCR4_INVR; | |
1224 | else | |
1225 | temp &= ~(UCR4_INVR); | |
1226 | writel(temp | UCR4_DREN, sport->port.membase + UCR4); | |
1227 | ||
1228 | temp = readl(sport->port.membase + UCR3); | |
1229 | if (sport->irda_inv_tx) | |
1230 | temp |= UCR3_INVT; | |
1231 | else | |
1232 | temp &= ~(UCR3_INVT); | |
1233 | writel(temp, sport->port.membase + UCR3); | |
1234 | } | |
1235 | ||
1da177e4 LT |
1236 | /* |
1237 | * Enable modem status interrupts | |
1238 | */ | |
1da177e4 | 1239 | imx_enable_ms(&sport->port); |
82313e66 | 1240 | spin_unlock_irqrestore(&sport->port.lock, flags); |
1da177e4 | 1241 | |
b6e49138 FG |
1242 | if (USE_IRDA(sport)) { |
1243 | struct imxuart_platform_data *pdata; | |
574de559 | 1244 | pdata = dev_get_platdata(sport->port.dev); |
b6e49138 FG |
1245 | sport->irda_inv_rx = pdata->irda_inv_rx; |
1246 | sport->irda_inv_tx = pdata->irda_inv_tx; | |
1247 | sport->trcv_delay = pdata->transceiver_delay; | |
1248 | if (pdata->irda_enable) | |
1249 | pdata->irda_enable(1); | |
1250 | } | |
1251 | ||
1da177e4 | 1252 | return 0; |
1da177e4 LT |
1253 | } |
1254 | ||
1255 | static void imx_shutdown(struct uart_port *port) | |
1256 | { | |
1257 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 | 1258 | unsigned long temp; |
9ec1882d | 1259 | unsigned long flags; |
1da177e4 | 1260 | |
b4cdc8f6 | 1261 | if (sport->dma_is_enabled) { |
a4688bcd HS |
1262 | int ret; |
1263 | ||
9ce4f8f3 | 1264 | /* We have to wait for the DMA to finish. */ |
a4688bcd | 1265 | ret = wait_event_interruptible(sport->dma_wait, |
9ce4f8f3 | 1266 | !sport->dma_is_rxing && !sport->dma_is_txing); |
a4688bcd HS |
1267 | if (ret != 0) { |
1268 | sport->dma_is_rxing = 0; | |
1269 | sport->dma_is_txing = 0; | |
1270 | dmaengine_terminate_all(sport->dma_chan_tx); | |
1271 | dmaengine_terminate_all(sport->dma_chan_rx); | |
1272 | } | |
73631813 | 1273 | spin_lock_irqsave(&sport->port.lock, flags); |
a4688bcd | 1274 | imx_stop_tx(port); |
b4cdc8f6 HS |
1275 | imx_stop_rx(port); |
1276 | imx_disable_dma(sport); | |
73631813 | 1277 | spin_unlock_irqrestore(&sport->port.lock, flags); |
b4cdc8f6 HS |
1278 | imx_uart_dma_exit(sport); |
1279 | } | |
1280 | ||
9ec1882d | 1281 | spin_lock_irqsave(&sport->port.lock, flags); |
2e146392 FG |
1282 | temp = readl(sport->port.membase + UCR2); |
1283 | temp &= ~(UCR2_TXEN); | |
1284 | writel(temp, sport->port.membase + UCR2); | |
9ec1882d | 1285 | spin_unlock_irqrestore(&sport->port.lock, flags); |
2e146392 | 1286 | |
b6e49138 FG |
1287 | if (USE_IRDA(sport)) { |
1288 | struct imxuart_platform_data *pdata; | |
574de559 | 1289 | pdata = dev_get_platdata(sport->port.dev); |
b6e49138 FG |
1290 | if (pdata->irda_enable) |
1291 | pdata->irda_enable(0); | |
1292 | } | |
1293 | ||
1da177e4 LT |
1294 | /* |
1295 | * Stop our timer. | |
1296 | */ | |
1297 | del_timer_sync(&sport->timer); | |
1298 | ||
1da177e4 LT |
1299 | /* |
1300 | * Disable all interrupts, port and break condition. | |
1301 | */ | |
1302 | ||
9ec1882d | 1303 | spin_lock_irqsave(&sport->port.lock, flags); |
ff4bfb21 SH |
1304 | temp = readl(sport->port.membase + UCR1); |
1305 | temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN); | |
b6e49138 FG |
1306 | if (USE_IRDA(sport)) |
1307 | temp &= ~(UCR1_IREN); | |
1308 | ||
ff4bfb21 | 1309 | writel(temp, sport->port.membase + UCR1); |
9ec1882d | 1310 | spin_unlock_irqrestore(&sport->port.lock, flags); |
28eb4274 | 1311 | |
1cf93e0d HS |
1312 | clk_disable_unprepare(sport->clk_per); |
1313 | clk_disable_unprepare(sport->clk_ipg); | |
1da177e4 LT |
1314 | } |
1315 | ||
eb56b7ed HS |
1316 | static void imx_flush_buffer(struct uart_port *port) |
1317 | { | |
1318 | struct imx_port *sport = (struct imx_port *)port; | |
82e86ae9 | 1319 | struct scatterlist *sgl = &sport->tx_sgl[0]; |
a2c718ce | 1320 | unsigned long temp; |
4f86a95d | 1321 | int i = 100, ubir, ubmr, uts; |
eb56b7ed | 1322 | |
82e86ae9 DB |
1323 | if (!sport->dma_chan_tx) |
1324 | return; | |
1325 | ||
1326 | sport->tx_bytes = 0; | |
1327 | dmaengine_terminate_all(sport->dma_chan_tx); | |
1328 | if (sport->dma_is_txing) { | |
1329 | dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, | |
1330 | DMA_TO_DEVICE); | |
a2c718ce DB |
1331 | temp = readl(sport->port.membase + UCR1); |
1332 | temp &= ~UCR1_TDMAEN; | |
1333 | writel(temp, sport->port.membase + UCR1); | |
82e86ae9 | 1334 | sport->dma_is_txing = false; |
eb56b7ed | 1335 | } |
934084a9 FE |
1336 | |
1337 | /* | |
1338 | * According to the Reference Manual description of the UART SRST bit: | |
1339 | * "Reset the transmit and receive state machines, | |
1340 | * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD | |
1341 | * and UTS[6-3]". As we don't need to restore the old values from | |
1342 | * USR1, USR2, URXD, UTXD, only save/restore the other four registers | |
1343 | */ | |
1344 | ubir = readl(sport->port.membase + UBIR); | |
1345 | ubmr = readl(sport->port.membase + UBMR); | |
934084a9 FE |
1346 | uts = readl(sport->port.membase + IMX21_UTS); |
1347 | ||
1348 | temp = readl(sport->port.membase + UCR2); | |
1349 | temp &= ~UCR2_SRST; | |
1350 | writel(temp, sport->port.membase + UCR2); | |
1351 | ||
1352 | while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0)) | |
1353 | udelay(1); | |
1354 | ||
1355 | /* Restore the registers */ | |
1356 | writel(ubir, sport->port.membase + UBIR); | |
1357 | writel(ubmr, sport->port.membase + UBMR); | |
934084a9 | 1358 | writel(uts, sport->port.membase + IMX21_UTS); |
eb56b7ed HS |
1359 | } |
1360 | ||
1da177e4 | 1361 | static void |
606d099c AC |
1362 | imx_set_termios(struct uart_port *port, struct ktermios *termios, |
1363 | struct ktermios *old) | |
1da177e4 LT |
1364 | { |
1365 | struct imx_port *sport = (struct imx_port *)port; | |
1366 | unsigned long flags; | |
1367 | unsigned int ucr2, old_ucr1, old_txrxen, baud, quot; | |
1368 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; | |
534fca06 OS |
1369 | unsigned int div, ufcr; |
1370 | unsigned long num, denom; | |
d7f8d437 | 1371 | uint64_t tdiv64; |
1da177e4 | 1372 | |
1da177e4 LT |
1373 | /* |
1374 | * We only support CS7 and CS8. | |
1375 | */ | |
1376 | while ((termios->c_cflag & CSIZE) != CS7 && | |
1377 | (termios->c_cflag & CSIZE) != CS8) { | |
1378 | termios->c_cflag &= ~CSIZE; | |
1379 | termios->c_cflag |= old_csize; | |
1380 | old_csize = CS8; | |
1381 | } | |
1382 | ||
1383 | if ((termios->c_cflag & CSIZE) == CS8) | |
1384 | ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS; | |
1385 | else | |
1386 | ucr2 = UCR2_SRST | UCR2_IRTS; | |
1387 | ||
1388 | if (termios->c_cflag & CRTSCTS) { | |
82313e66 | 1389 | if (sport->have_rtscts) { |
5b802344 SH |
1390 | ucr2 &= ~UCR2_IRTS; |
1391 | ucr2 |= UCR2_CTSC; | |
1392 | } else { | |
1393 | termios->c_cflag &= ~CRTSCTS; | |
1394 | } | |
1da177e4 LT |
1395 | } |
1396 | ||
1397 | if (termios->c_cflag & CSTOPB) | |
1398 | ucr2 |= UCR2_STPB; | |
1399 | if (termios->c_cflag & PARENB) { | |
1400 | ucr2 |= UCR2_PREN; | |
3261e362 | 1401 | if (termios->c_cflag & PARODD) |
1da177e4 LT |
1402 | ucr2 |= UCR2_PROE; |
1403 | } | |
1404 | ||
995234da EM |
1405 | del_timer_sync(&sport->timer); |
1406 | ||
1da177e4 LT |
1407 | /* |
1408 | * Ask the core to calculate the divisor for us. | |
1409 | */ | |
036bb15e | 1410 | baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); |
1da177e4 LT |
1411 | quot = uart_get_divisor(port, baud); |
1412 | ||
1413 | spin_lock_irqsave(&sport->port.lock, flags); | |
1414 | ||
1415 | sport->port.read_status_mask = 0; | |
1416 | if (termios->c_iflag & INPCK) | |
1417 | sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR); | |
1418 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
1419 | sport->port.read_status_mask |= URXD_BRK; | |
1420 | ||
1421 | /* | |
1422 | * Characters to ignore | |
1423 | */ | |
1424 | sport->port.ignore_status_mask = 0; | |
1425 | if (termios->c_iflag & IGNPAR) | |
865cea85 | 1426 | sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR; |
1da177e4 LT |
1427 | if (termios->c_iflag & IGNBRK) { |
1428 | sport->port.ignore_status_mask |= URXD_BRK; | |
1429 | /* | |
1430 | * If we're ignoring parity and break indicators, | |
1431 | * ignore overruns too (for real raw support). | |
1432 | */ | |
1433 | if (termios->c_iflag & IGNPAR) | |
1434 | sport->port.ignore_status_mask |= URXD_OVRRUN; | |
1435 | } | |
1436 | ||
55d8693a JW |
1437 | if ((termios->c_cflag & CREAD) == 0) |
1438 | sport->port.ignore_status_mask |= URXD_DUMMY_READ; | |
1439 | ||
1da177e4 LT |
1440 | /* |
1441 | * Update the per-port timeout. | |
1442 | */ | |
1443 | uart_update_timeout(port, termios->c_cflag, baud); | |
1444 | ||
1445 | /* | |
1446 | * disable interrupts and drain transmitter | |
1447 | */ | |
ff4bfb21 SH |
1448 | old_ucr1 = readl(sport->port.membase + UCR1); |
1449 | writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), | |
1450 | sport->port.membase + UCR1); | |
1da177e4 | 1451 | |
82313e66 | 1452 | while (!(readl(sport->port.membase + USR2) & USR2_TXDC)) |
1da177e4 LT |
1453 | barrier(); |
1454 | ||
1455 | /* then, disable everything */ | |
ff4bfb21 | 1456 | old_txrxen = readl(sport->port.membase + UCR2); |
82313e66 | 1457 | writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN), |
ff4bfb21 SH |
1458 | sport->port.membase + UCR2); |
1459 | old_txrxen &= (UCR2_TXEN | UCR2_RXEN); | |
1da177e4 | 1460 | |
b6e49138 FG |
1461 | if (USE_IRDA(sport)) { |
1462 | /* | |
1463 | * use maximum available submodule frequency to | |
1464 | * avoid missing short pulses due to low sampling rate | |
1465 | */ | |
036bb15e | 1466 | div = 1; |
b6e49138 | 1467 | } else { |
09bd00f6 HF |
1468 | /* custom-baudrate handling */ |
1469 | div = sport->port.uartclk / (baud * 16); | |
1470 | if (baud == 38400 && quot != div) | |
1471 | baud = sport->port.uartclk / (quot * 16); | |
1472 | ||
b6e49138 FG |
1473 | div = sport->port.uartclk / (baud * 16); |
1474 | if (div > 7) | |
1475 | div = 7; | |
1476 | if (!div) | |
1477 | div = 1; | |
1478 | } | |
036bb15e | 1479 | |
534fca06 OS |
1480 | rational_best_approximation(16 * div * baud, sport->port.uartclk, |
1481 | 1 << 16, 1 << 16, &num, &denom); | |
036bb15e | 1482 | |
eab4f5af AC |
1483 | tdiv64 = sport->port.uartclk; |
1484 | tdiv64 *= num; | |
1485 | do_div(tdiv64, denom * 16 * div); | |
1486 | tty_termios_encode_baud_rate(termios, | |
1a2c4b31 | 1487 | (speed_t)tdiv64, (speed_t)tdiv64); |
d7f8d437 | 1488 | |
534fca06 OS |
1489 | num -= 1; |
1490 | denom -= 1; | |
036bb15e SH |
1491 | |
1492 | ufcr = readl(sport->port.membase + UFCR); | |
b6e49138 | 1493 | ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div); |
20ff2fe6 HS |
1494 | if (sport->dte_mode) |
1495 | ufcr |= UFCR_DCEDTE; | |
036bb15e SH |
1496 | writel(ufcr, sport->port.membase + UFCR); |
1497 | ||
534fca06 OS |
1498 | writel(num, sport->port.membase + UBIR); |
1499 | writel(denom, sport->port.membase + UBMR); | |
1500 | ||
a496e628 | 1501 | if (!is_imx1_uart(sport)) |
37d6fb62 | 1502 | writel(sport->port.uartclk / div / 1000, |
fe6b540a | 1503 | sport->port.membase + IMX21_ONEMS); |
ff4bfb21 SH |
1504 | |
1505 | writel(old_ucr1, sport->port.membase + UCR1); | |
1da177e4 | 1506 | |
ff4bfb21 SH |
1507 | /* set the parity, stop bits and data size */ |
1508 | writel(ucr2 | old_txrxen, sport->port.membase + UCR2); | |
1da177e4 LT |
1509 | |
1510 | if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) | |
1511 | imx_enable_ms(&sport->port); | |
1512 | ||
1513 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
1514 | } | |
1515 | ||
1516 | static const char *imx_type(struct uart_port *port) | |
1517 | { | |
1518 | struct imx_port *sport = (struct imx_port *)port; | |
1519 | ||
1520 | return sport->port.type == PORT_IMX ? "IMX" : NULL; | |
1521 | } | |
1522 | ||
1da177e4 LT |
1523 | /* |
1524 | * Configure/autoconfigure the port. | |
1525 | */ | |
1526 | static void imx_config_port(struct uart_port *port, int flags) | |
1527 | { | |
1528 | struct imx_port *sport = (struct imx_port *)port; | |
1529 | ||
da82f997 | 1530 | if (flags & UART_CONFIG_TYPE) |
1da177e4 LT |
1531 | sport->port.type = PORT_IMX; |
1532 | } | |
1533 | ||
1534 | /* | |
1535 | * Verify the new serial_struct (for TIOCSSERIAL). | |
1536 | * The only change we allow are to the flags and type, and | |
1537 | * even then only between PORT_IMX and PORT_UNKNOWN | |
1538 | */ | |
1539 | static int | |
1540 | imx_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1541 | { | |
1542 | struct imx_port *sport = (struct imx_port *)port; | |
1543 | int ret = 0; | |
1544 | ||
1545 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX) | |
1546 | ret = -EINVAL; | |
1547 | if (sport->port.irq != ser->irq) | |
1548 | ret = -EINVAL; | |
1549 | if (ser->io_type != UPIO_MEM) | |
1550 | ret = -EINVAL; | |
1551 | if (sport->port.uartclk / 16 != ser->baud_base) | |
1552 | ret = -EINVAL; | |
a50c44ce | 1553 | if (sport->port.mapbase != (unsigned long)ser->iomem_base) |
1da177e4 LT |
1554 | ret = -EINVAL; |
1555 | if (sport->port.iobase != ser->port) | |
1556 | ret = -EINVAL; | |
1557 | if (ser->hub6 != 0) | |
1558 | ret = -EINVAL; | |
1559 | return ret; | |
1560 | } | |
1561 | ||
01f56abd | 1562 | #if defined(CONFIG_CONSOLE_POLL) |
6b8bdad9 DT |
1563 | |
1564 | static int imx_poll_init(struct uart_port *port) | |
1565 | { | |
1566 | struct imx_port *sport = (struct imx_port *)port; | |
1567 | unsigned long flags; | |
1568 | unsigned long temp; | |
1569 | int retval; | |
1570 | ||
1571 | retval = clk_prepare_enable(sport->clk_ipg); | |
1572 | if (retval) | |
1573 | return retval; | |
1574 | retval = clk_prepare_enable(sport->clk_per); | |
1575 | if (retval) | |
1576 | clk_disable_unprepare(sport->clk_ipg); | |
1577 | ||
1578 | imx_setup_ufcr(sport, 0); | |
1579 | ||
1580 | spin_lock_irqsave(&sport->port.lock, flags); | |
1581 | ||
1582 | temp = readl(sport->port.membase + UCR1); | |
1583 | if (is_imx1_uart(sport)) | |
1584 | temp |= IMX1_UCR1_UARTCLKEN; | |
1585 | temp |= UCR1_UARTEN | UCR1_RRDYEN; | |
1586 | temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN); | |
1587 | writel(temp, sport->port.membase + UCR1); | |
1588 | ||
1589 | temp = readl(sport->port.membase + UCR2); | |
1590 | temp |= UCR2_RXEN; | |
1591 | writel(temp, sport->port.membase + UCR2); | |
1592 | ||
1593 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
1594 | ||
1595 | return 0; | |
1596 | } | |
1597 | ||
01f56abd SA |
1598 | static int imx_poll_get_char(struct uart_port *port) |
1599 | { | |
f968ef34 | 1600 | if (!(readl_relaxed(port->membase + USR2) & USR2_RDR)) |
26c47412 | 1601 | return NO_POLL_CHAR; |
01f56abd | 1602 | |
f968ef34 | 1603 | return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA; |
01f56abd SA |
1604 | } |
1605 | ||
1606 | static void imx_poll_put_char(struct uart_port *port, unsigned char c) | |
1607 | { | |
01f56abd SA |
1608 | unsigned int status; |
1609 | ||
01f56abd SA |
1610 | /* drain */ |
1611 | do { | |
f968ef34 | 1612 | status = readl_relaxed(port->membase + USR1); |
01f56abd SA |
1613 | } while (~status & USR1_TRDY); |
1614 | ||
1615 | /* write */ | |
f968ef34 | 1616 | writel_relaxed(c, port->membase + URTX0); |
01f56abd SA |
1617 | |
1618 | /* flush */ | |
1619 | do { | |
f968ef34 | 1620 | status = readl_relaxed(port->membase + USR2); |
01f56abd | 1621 | } while (~status & USR2_TXDC); |
01f56abd SA |
1622 | } |
1623 | #endif | |
1624 | ||
1da177e4 LT |
1625 | static struct uart_ops imx_pops = { |
1626 | .tx_empty = imx_tx_empty, | |
1627 | .set_mctrl = imx_set_mctrl, | |
1628 | .get_mctrl = imx_get_mctrl, | |
1629 | .stop_tx = imx_stop_tx, | |
1630 | .start_tx = imx_start_tx, | |
1631 | .stop_rx = imx_stop_rx, | |
1632 | .enable_ms = imx_enable_ms, | |
1633 | .break_ctl = imx_break_ctl, | |
1634 | .startup = imx_startup, | |
1635 | .shutdown = imx_shutdown, | |
eb56b7ed | 1636 | .flush_buffer = imx_flush_buffer, |
1da177e4 LT |
1637 | .set_termios = imx_set_termios, |
1638 | .type = imx_type, | |
1da177e4 LT |
1639 | .config_port = imx_config_port, |
1640 | .verify_port = imx_verify_port, | |
01f56abd | 1641 | #if defined(CONFIG_CONSOLE_POLL) |
6b8bdad9 | 1642 | .poll_init = imx_poll_init, |
01f56abd SA |
1643 | .poll_get_char = imx_poll_get_char, |
1644 | .poll_put_char = imx_poll_put_char, | |
1645 | #endif | |
1da177e4 LT |
1646 | }; |
1647 | ||
dbff4e9e | 1648 | static struct imx_port *imx_ports[UART_NR]; |
1da177e4 LT |
1649 | |
1650 | #ifdef CONFIG_SERIAL_IMX_CONSOLE | |
d358788f RK |
1651 | static void imx_console_putchar(struct uart_port *port, int ch) |
1652 | { | |
1653 | struct imx_port *sport = (struct imx_port *)port; | |
ff4bfb21 | 1654 | |
fe6b540a | 1655 | while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL) |
d358788f | 1656 | barrier(); |
ff4bfb21 SH |
1657 | |
1658 | writel(ch, sport->port.membase + URTX0); | |
d358788f | 1659 | } |
1da177e4 LT |
1660 | |
1661 | /* | |
1662 | * Interrupts are disabled on entering | |
1663 | */ | |
1664 | static void | |
1665 | imx_console_write(struct console *co, const char *s, unsigned int count) | |
1666 | { | |
dbff4e9e | 1667 | struct imx_port *sport = imx_ports[co->index]; |
0ad5a814 DB |
1668 | struct imx_port_ucrs old_ucr; |
1669 | unsigned int ucr1; | |
f30e8260 | 1670 | unsigned long flags = 0; |
677fe555 | 1671 | int locked = 1; |
1cf93e0d HS |
1672 | int retval; |
1673 | ||
1674 | retval = clk_enable(sport->clk_per); | |
1675 | if (retval) | |
1676 | return; | |
1677 | retval = clk_enable(sport->clk_ipg); | |
1678 | if (retval) { | |
1679 | clk_disable(sport->clk_per); | |
1680 | return; | |
1681 | } | |
9ec1882d | 1682 | |
677fe555 TG |
1683 | if (sport->port.sysrq) |
1684 | locked = 0; | |
1685 | else if (oops_in_progress) | |
1686 | locked = spin_trylock_irqsave(&sport->port.lock, flags); | |
1687 | else | |
1688 | spin_lock_irqsave(&sport->port.lock, flags); | |
1da177e4 LT |
1689 | |
1690 | /* | |
0ad5a814 | 1691 | * First, save UCR1/2/3 and then disable interrupts |
1da177e4 | 1692 | */ |
0ad5a814 DB |
1693 | imx_port_ucrs_save(&sport->port, &old_ucr); |
1694 | ucr1 = old_ucr.ucr1; | |
1da177e4 | 1695 | |
fe6b540a SG |
1696 | if (is_imx1_uart(sport)) |
1697 | ucr1 |= IMX1_UCR1_UARTCLKEN; | |
37d6fb62 SH |
1698 | ucr1 |= UCR1_UARTEN; |
1699 | ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN); | |
1700 | ||
1701 | writel(ucr1, sport->port.membase + UCR1); | |
ff4bfb21 | 1702 | |
0ad5a814 | 1703 | writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); |
1da177e4 | 1704 | |
d358788f | 1705 | uart_console_write(&sport->port, s, count, imx_console_putchar); |
1da177e4 LT |
1706 | |
1707 | /* | |
1708 | * Finally, wait for transmitter to become empty | |
0ad5a814 | 1709 | * and restore UCR1/2/3 |
1da177e4 | 1710 | */ |
ff4bfb21 | 1711 | while (!(readl(sport->port.membase + USR2) & USR2_TXDC)); |
1da177e4 | 1712 | |
0ad5a814 | 1713 | imx_port_ucrs_restore(&sport->port, &old_ucr); |
9ec1882d | 1714 | |
677fe555 TG |
1715 | if (locked) |
1716 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
1cf93e0d HS |
1717 | |
1718 | clk_disable(sport->clk_ipg); | |
1719 | clk_disable(sport->clk_per); | |
1da177e4 LT |
1720 | } |
1721 | ||
1722 | /* | |
1723 | * If the port was already initialised (eg, by a boot loader), | |
1724 | * try to determine the current setup. | |
1725 | */ | |
1726 | static void __init | |
1727 | imx_console_get_options(struct imx_port *sport, int *baud, | |
1728 | int *parity, int *bits) | |
1729 | { | |
587897f5 | 1730 | |
2e2eb509 | 1731 | if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) { |
1da177e4 | 1732 | /* ok, the port was enabled */ |
82313e66 | 1733 | unsigned int ucr2, ubir, ubmr, uartclk; |
587897f5 SH |
1734 | unsigned int baud_raw; |
1735 | unsigned int ucfr_rfdiv; | |
1da177e4 | 1736 | |
ff4bfb21 | 1737 | ucr2 = readl(sport->port.membase + UCR2); |
1da177e4 LT |
1738 | |
1739 | *parity = 'n'; | |
1740 | if (ucr2 & UCR2_PREN) { | |
1741 | if (ucr2 & UCR2_PROE) | |
1742 | *parity = 'o'; | |
1743 | else | |
1744 | *parity = 'e'; | |
1745 | } | |
1746 | ||
1747 | if (ucr2 & UCR2_WS) | |
1748 | *bits = 8; | |
1749 | else | |
1750 | *bits = 7; | |
1751 | ||
ff4bfb21 SH |
1752 | ubir = readl(sport->port.membase + UBIR) & 0xffff; |
1753 | ubmr = readl(sport->port.membase + UBMR) & 0xffff; | |
587897f5 | 1754 | |
ff4bfb21 | 1755 | ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7; |
587897f5 SH |
1756 | if (ucfr_rfdiv == 6) |
1757 | ucfr_rfdiv = 7; | |
1758 | else | |
1759 | ucfr_rfdiv = 6 - ucfr_rfdiv; | |
1760 | ||
3a9465fa | 1761 | uartclk = clk_get_rate(sport->clk_per); |
587897f5 SH |
1762 | uartclk /= ucfr_rfdiv; |
1763 | ||
1764 | { /* | |
1765 | * The next code provides exact computation of | |
1766 | * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1)) | |
1767 | * without need of float support or long long division, | |
1768 | * which would be required to prevent 32bit arithmetic overflow | |
1769 | */ | |
1770 | unsigned int mul = ubir + 1; | |
1771 | unsigned int div = 16 * (ubmr + 1); | |
1772 | unsigned int rem = uartclk % div; | |
1773 | ||
1774 | baud_raw = (uartclk / div) * mul; | |
1775 | baud_raw += (rem * mul + div / 2) / div; | |
1776 | *baud = (baud_raw + 50) / 100 * 100; | |
1777 | } | |
1778 | ||
82313e66 | 1779 | if (*baud != baud_raw) |
50bbdba3 | 1780 | pr_info("Console IMX rounded baud rate from %d to %d\n", |
587897f5 | 1781 | baud_raw, *baud); |
1da177e4 LT |
1782 | } |
1783 | } | |
1784 | ||
1785 | static int __init | |
1786 | imx_console_setup(struct console *co, char *options) | |
1787 | { | |
1788 | struct imx_port *sport; | |
1789 | int baud = 9600; | |
1790 | int bits = 8; | |
1791 | int parity = 'n'; | |
1792 | int flow = 'n'; | |
1cf93e0d | 1793 | int retval; |
1da177e4 LT |
1794 | |
1795 | /* | |
1796 | * Check whether an invalid uart number has been specified, and | |
1797 | * if so, search for the first available port that does have | |
1798 | * console support. | |
1799 | */ | |
1800 | if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports)) | |
1801 | co->index = 0; | |
dbff4e9e | 1802 | sport = imx_ports[co->index]; |
82313e66 | 1803 | if (sport == NULL) |
e76afc4e | 1804 | return -ENODEV; |
1da177e4 | 1805 | |
1cf93e0d HS |
1806 | /* For setting the registers, we only need to enable the ipg clock. */ |
1807 | retval = clk_prepare_enable(sport->clk_ipg); | |
1808 | if (retval) | |
1809 | goto error_console; | |
1810 | ||
1da177e4 LT |
1811 | if (options) |
1812 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1813 | else | |
1814 | imx_console_get_options(sport, &baud, &parity, &bits); | |
1815 | ||
587897f5 SH |
1816 | imx_setup_ufcr(sport, 0); |
1817 | ||
1cf93e0d HS |
1818 | retval = uart_set_options(&sport->port, co, baud, parity, bits, flow); |
1819 | ||
1820 | clk_disable(sport->clk_ipg); | |
1821 | if (retval) { | |
1822 | clk_unprepare(sport->clk_ipg); | |
1823 | goto error_console; | |
1824 | } | |
1825 | ||
1826 | retval = clk_prepare(sport->clk_per); | |
1827 | if (retval) | |
1828 | clk_disable_unprepare(sport->clk_ipg); | |
1829 | ||
1830 | error_console: | |
1831 | return retval; | |
1da177e4 LT |
1832 | } |
1833 | ||
9f4426dd | 1834 | static struct uart_driver imx_reg; |
1da177e4 | 1835 | static struct console imx_console = { |
e3d13ff4 | 1836 | .name = DEV_NAME, |
1da177e4 LT |
1837 | .write = imx_console_write, |
1838 | .device = uart_console_device, | |
1839 | .setup = imx_console_setup, | |
1840 | .flags = CON_PRINTBUFFER, | |
1841 | .index = -1, | |
1842 | .data = &imx_reg, | |
1843 | }; | |
1844 | ||
1da177e4 LT |
1845 | #define IMX_CONSOLE &imx_console |
1846 | #else | |
1847 | #define IMX_CONSOLE NULL | |
1848 | #endif | |
1849 | ||
1850 | static struct uart_driver imx_reg = { | |
1851 | .owner = THIS_MODULE, | |
1852 | .driver_name = DRIVER_NAME, | |
e3d13ff4 | 1853 | .dev_name = DEV_NAME, |
1da177e4 LT |
1854 | .major = SERIAL_IMX_MAJOR, |
1855 | .minor = MINOR_START, | |
1856 | .nr = ARRAY_SIZE(imx_ports), | |
1857 | .cons = IMX_CONSOLE, | |
1858 | }; | |
1859 | ||
3ae5eaec | 1860 | static int serial_imx_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 1861 | { |
d3810cd4 | 1862 | struct imx_port *sport = platform_get_drvdata(dev); |
db1a9b55 FE |
1863 | unsigned int val; |
1864 | ||
1865 | /* enable wakeup from i.MX UART */ | |
1866 | val = readl(sport->port.membase + UCR3); | |
1867 | val |= UCR3_AWAKEN; | |
1868 | writel(val, sport->port.membase + UCR3); | |
1da177e4 | 1869 | |
034dc4db | 1870 | uart_suspend_port(&imx_reg, &sport->port); |
1da177e4 | 1871 | |
d3810cd4 | 1872 | return 0; |
1da177e4 LT |
1873 | } |
1874 | ||
3ae5eaec | 1875 | static int serial_imx_resume(struct platform_device *dev) |
1da177e4 | 1876 | { |
d3810cd4 | 1877 | struct imx_port *sport = platform_get_drvdata(dev); |
db1a9b55 FE |
1878 | unsigned int val; |
1879 | ||
1880 | /* disable wakeup from i.MX UART */ | |
1881 | val = readl(sport->port.membase + UCR3); | |
1882 | val &= ~UCR3_AWAKEN; | |
1883 | writel(val, sport->port.membase + UCR3); | |
1da177e4 | 1884 | |
034dc4db | 1885 | uart_resume_port(&imx_reg, &sport->port); |
1da177e4 | 1886 | |
d3810cd4 | 1887 | return 0; |
1da177e4 LT |
1888 | } |
1889 | ||
22698aa2 | 1890 | #ifdef CONFIG_OF |
20bb8095 UKK |
1891 | /* |
1892 | * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it | |
1893 | * could successfully get all information from dt or a negative errno. | |
1894 | */ | |
22698aa2 SG |
1895 | static int serial_imx_probe_dt(struct imx_port *sport, |
1896 | struct platform_device *pdev) | |
1897 | { | |
1898 | struct device_node *np = pdev->dev.of_node; | |
1899 | const struct of_device_id *of_id = | |
1900 | of_match_device(imx_uart_dt_ids, &pdev->dev); | |
ff05967a | 1901 | int ret; |
22698aa2 SG |
1902 | |
1903 | if (!np) | |
20bb8095 UKK |
1904 | /* no device tree device */ |
1905 | return 1; | |
22698aa2 | 1906 | |
ff05967a SG |
1907 | ret = of_alias_get_id(np, "serial"); |
1908 | if (ret < 0) { | |
1909 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); | |
a197a191 | 1910 | return ret; |
ff05967a SG |
1911 | } |
1912 | sport->port.line = ret; | |
22698aa2 SG |
1913 | |
1914 | if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) | |
1915 | sport->have_rtscts = 1; | |
1916 | ||
1917 | if (of_get_property(np, "fsl,irda-mode", NULL)) | |
1918 | sport->use_irda = 1; | |
1919 | ||
20ff2fe6 HS |
1920 | if (of_get_property(np, "fsl,dte-mode", NULL)) |
1921 | sport->dte_mode = 1; | |
1922 | ||
22698aa2 SG |
1923 | sport->devdata = of_id->data; |
1924 | ||
1925 | return 0; | |
1926 | } | |
1927 | #else | |
1928 | static inline int serial_imx_probe_dt(struct imx_port *sport, | |
1929 | struct platform_device *pdev) | |
1930 | { | |
20bb8095 | 1931 | return 1; |
22698aa2 SG |
1932 | } |
1933 | #endif | |
1934 | ||
1935 | static void serial_imx_probe_pdata(struct imx_port *sport, | |
1936 | struct platform_device *pdev) | |
1937 | { | |
574de559 | 1938 | struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev); |
22698aa2 SG |
1939 | |
1940 | sport->port.line = pdev->id; | |
1941 | sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data; | |
1942 | ||
1943 | if (!pdata) | |
1944 | return; | |
1945 | ||
1946 | if (pdata->flags & IMXUART_HAVE_RTSCTS) | |
1947 | sport->have_rtscts = 1; | |
1948 | ||
1949 | if (pdata->flags & IMXUART_IRDA) | |
1950 | sport->use_irda = 1; | |
1951 | } | |
1952 | ||
2582d8c1 | 1953 | static int serial_imx_probe(struct platform_device *pdev) |
1da177e4 | 1954 | { |
dbff4e9e | 1955 | struct imx_port *sport; |
dbff4e9e SH |
1956 | void __iomem *base; |
1957 | int ret = 0; | |
1958 | struct resource *res; | |
1959 | ||
42d34191 | 1960 | sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); |
dbff4e9e SH |
1961 | if (!sport) |
1962 | return -ENOMEM; | |
5b802344 | 1963 | |
22698aa2 | 1964 | ret = serial_imx_probe_dt(sport, pdev); |
20bb8095 | 1965 | if (ret > 0) |
22698aa2 | 1966 | serial_imx_probe_pdata(sport, pdev); |
20bb8095 | 1967 | else if (ret < 0) |
42d34191 | 1968 | return ret; |
22698aa2 | 1969 | |
dbff4e9e | 1970 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
da82f997 AS |
1971 | base = devm_ioremap_resource(&pdev->dev, res); |
1972 | if (IS_ERR(base)) | |
1973 | return PTR_ERR(base); | |
dbff4e9e SH |
1974 | |
1975 | sport->port.dev = &pdev->dev; | |
1976 | sport->port.mapbase = res->start; | |
1977 | sport->port.membase = base; | |
1978 | sport->port.type = PORT_IMX, | |
1979 | sport->port.iotype = UPIO_MEM; | |
1980 | sport->port.irq = platform_get_irq(pdev, 0); | |
1981 | sport->rxirq = platform_get_irq(pdev, 0); | |
1982 | sport->txirq = platform_get_irq(pdev, 1); | |
1983 | sport->rtsirq = platform_get_irq(pdev, 2); | |
1984 | sport->port.fifosize = 32; | |
1985 | sport->port.ops = &imx_pops; | |
1986 | sport->port.flags = UPF_BOOT_AUTOCONF; | |
dbff4e9e SH |
1987 | init_timer(&sport->timer); |
1988 | sport->timer.function = imx_timeout; | |
1989 | sport->timer.data = (unsigned long)sport; | |
38a41fdf | 1990 | |
3a9465fa SH |
1991 | sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
1992 | if (IS_ERR(sport->clk_ipg)) { | |
1993 | ret = PTR_ERR(sport->clk_ipg); | |
833462e9 | 1994 | dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret); |
42d34191 | 1995 | return ret; |
38a41fdf | 1996 | } |
38a41fdf | 1997 | |
3a9465fa SH |
1998 | sport->clk_per = devm_clk_get(&pdev->dev, "per"); |
1999 | if (IS_ERR(sport->clk_per)) { | |
2000 | ret = PTR_ERR(sport->clk_per); | |
833462e9 | 2001 | dev_err(&pdev->dev, "failed to get per clk: %d\n", ret); |
42d34191 | 2002 | return ret; |
3a9465fa SH |
2003 | } |
2004 | ||
3a9465fa | 2005 | sport->port.uartclk = clk_get_rate(sport->clk_per); |
dbff4e9e | 2006 | |
c0d1c6b0 FE |
2007 | /* |
2008 | * Allocate the IRQ(s) i.MX1 has three interrupts whereas later | |
2009 | * chips only have one interrupt. | |
2010 | */ | |
2011 | if (sport->txirq > 0) { | |
2012 | ret = devm_request_irq(&pdev->dev, sport->rxirq, imx_rxint, 0, | |
2013 | dev_name(&pdev->dev), sport); | |
2014 | if (ret) | |
2015 | return ret; | |
2016 | ||
2017 | ret = devm_request_irq(&pdev->dev, sport->txirq, imx_txint, 0, | |
2018 | dev_name(&pdev->dev), sport); | |
2019 | if (ret) | |
2020 | return ret; | |
2021 | ||
2022 | /* do not use RTS IRQ on IrDA */ | |
2023 | if (!USE_IRDA(sport)) { | |
2024 | ret = devm_request_irq(&pdev->dev, sport->rtsirq, | |
2025 | imx_rtsint, 0, | |
2026 | dev_name(&pdev->dev), sport); | |
2027 | if (ret) | |
2028 | return ret; | |
2029 | } | |
2030 | } else { | |
2031 | ret = devm_request_irq(&pdev->dev, sport->port.irq, imx_int, 0, | |
2032 | dev_name(&pdev->dev), sport); | |
2033 | if (ret) | |
2034 | return ret; | |
2035 | } | |
2036 | ||
22698aa2 | 2037 | imx_ports[sport->port.line] = sport; |
5b802344 | 2038 | |
0a86a86b | 2039 | platform_set_drvdata(pdev, sport); |
5b802344 | 2040 | |
45af780a | 2041 | return uart_add_one_port(&imx_reg, &sport->port); |
1da177e4 LT |
2042 | } |
2043 | ||
2582d8c1 | 2044 | static int serial_imx_remove(struct platform_device *pdev) |
1da177e4 | 2045 | { |
2582d8c1 | 2046 | struct imx_port *sport = platform_get_drvdata(pdev); |
1da177e4 | 2047 | |
45af780a | 2048 | return uart_remove_one_port(&imx_reg, &sport->port); |
1da177e4 LT |
2049 | } |
2050 | ||
3ae5eaec | 2051 | static struct platform_driver serial_imx_driver = { |
d3810cd4 OS |
2052 | .probe = serial_imx_probe, |
2053 | .remove = serial_imx_remove, | |
1da177e4 LT |
2054 | |
2055 | .suspend = serial_imx_suspend, | |
2056 | .resume = serial_imx_resume, | |
fe6b540a | 2057 | .id_table = imx_uart_devtype, |
3ae5eaec | 2058 | .driver = { |
d3810cd4 | 2059 | .name = "imx-uart", |
22698aa2 | 2060 | .of_match_table = imx_uart_dt_ids, |
3ae5eaec | 2061 | }, |
1da177e4 LT |
2062 | }; |
2063 | ||
2064 | static int __init imx_serial_init(void) | |
2065 | { | |
f0fd1b73 | 2066 | int ret = uart_register_driver(&imx_reg); |
1da177e4 | 2067 | |
1da177e4 LT |
2068 | if (ret) |
2069 | return ret; | |
2070 | ||
3ae5eaec | 2071 | ret = platform_driver_register(&serial_imx_driver); |
1da177e4 LT |
2072 | if (ret != 0) |
2073 | uart_unregister_driver(&imx_reg); | |
2074 | ||
f227824e | 2075 | return ret; |
1da177e4 LT |
2076 | } |
2077 | ||
2078 | static void __exit imx_serial_exit(void) | |
2079 | { | |
c889b896 | 2080 | platform_driver_unregister(&serial_imx_driver); |
4b300c36 | 2081 | uart_unregister_driver(&imx_reg); |
1da177e4 LT |
2082 | } |
2083 | ||
2084 | module_init(imx_serial_init); | |
2085 | module_exit(imx_serial_exit); | |
2086 | ||
2087 | MODULE_AUTHOR("Sascha Hauer"); | |
2088 | MODULE_DESCRIPTION("IMX generic serial port driver"); | |
2089 | MODULE_LICENSE("GPL"); | |
e169c139 | 2090 | MODULE_ALIAS("platform:imx-uart"); |