projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
serial: imx: Fix issue in software flow control
[deliverable/linux.git] / drivers / tty / serial / imx.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
b6e49138
FG		 9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
1da177e4
LT		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
1da177e4
LT		 29
30#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31#define SUPPORT_SYSRQ
32#endif
33
34#include <linux/module.h>
35#include <linux/ioport.h>
36#include <linux/init.h>
37#include <linux/console.h>
38#include <linux/sysrq.h>
d052d1be 39#include <linux/platform_device.h>
1da177e4
LT		 40#include <linux/tty.h>
41#include <linux/tty_flip.h>
42#include <linux/serial_core.h>
43#include <linux/serial.h>
38a41fdf 44#include <linux/clk.h>
b6e49138 45#include <linux/delay.h>
534fca06 46#include <linux/rational.h>
5a0e3ad6 47#include <linux/slab.h>
22698aa2
SG		 48#include <linux/of.h>
49#include <linux/of_device.h>
e32a9f8f 50#include <linux/io.h>
b4cdc8f6 51#include <linux/dma-mapping.h>
1da177e4 52
1da177e4 53#include <asm/irq.h>
82906b13 54#include <linux/platform_data/serial-imx.h>
b4cdc8f6 55#include <linux/platform_data/dma-imx.h>
1da177e4 56
ff4bfb21
SH		 57/* Register definitions */
58#define URXD0 0x0 /* Receiver Register */
59#define URTX0 0x40 /* Transmitter Register */
60#define UCR1 0x80 /* Control Register 1 */
61#define UCR2 0x84 /* Control Register 2 */
62#define UCR3 0x88 /* Control Register 3 */
63#define UCR4 0x8c /* Control Register 4 */
64#define UFCR 0x90 /* FIFO Control Register */
65#define USR1 0x94 /* Status Register 1 */
66#define USR2 0x98 /* Status Register 2 */
67#define UESC 0x9c /* Escape Character Register */
68#define UTIM 0xa0 /* Escape Timer Register */
69#define UBIR 0xa4 /* BRM Incremental Register */
70#define UBMR 0xa8 /* BRM Modulator Register */
71#define UBRC 0xac /* Baud Rate Count Register */
fe6b540a
SG		 72#define IMX21_ONEMS 0xb0 /* One Millisecond register */
73#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
74#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
ff4bfb21
SH		 75
76/* UART Control Register Bit Fields.*/
55d8693a 77#define URXD_DUMMY_READ (1<<16)
82313e66
SK		 78#define URXD_CHARRDY (1<<15)
79#define URXD_ERR (1<<14)
80#define URXD_OVRRUN (1<<13)
81#define URXD_FRMERR (1<<12)
82#define URXD_BRK (1<<11)
83#define URXD_PRERR (1<<10)
26c47412 84#define URXD_RX_DATA (0xFF<<0)
82313e66
SK		 85#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
86#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
87#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
88#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
b4cdc8f6 89#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
82313e66
SK		 90#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
91#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
92#define UCR1_IREN (1<<7) /* Infrared interface enable */
93#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
94#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
95#define UCR1_SNDBRK (1<<4) /* Send break */
96#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
97#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
b4cdc8f6 98#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
82313e66
SK		 99#define UCR1_DOZE (1<<1) /* Doze */
100#define UCR1_UARTEN (1<<0) /* UART enabled */
101#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
102#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
103#define UCR2_CTSC (1<<13) /* CTS pin control */
104#define UCR2_CTS (1<<12) /* Clear to send */
105#define UCR2_ESCEN (1<<11) /* Escape enable */
106#define UCR2_PREN (1<<8) /* Parity enable */
107#define UCR2_PROE (1<<7) /* Parity odd/even */
108#define UCR2_STPB (1<<6) /* Stop */
109#define UCR2_WS (1<<5) /* Word size */
110#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
111#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
112#define UCR2_TXEN (1<<2) /* Transmitter enabled */
113#define UCR2_RXEN (1<<1) /* Receiver enabled */
114#define UCR2_SRST (1<<0) /* SW reset */
115#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
116#define UCR3_PARERREN (1<<12) /* Parity enable */
117#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
118#define UCR3_DSR (1<<10) /* Data set ready */
119#define UCR3_DCD (1<<9) /* Data carrier detect */
120#define UCR3_RI (1<<8) /* Ring indicator */
b38cb7d2 121#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
82313e66
SK		 122#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
123#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
124#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
125#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
126#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
127#define UCR3_BPEN (1<<0) /* Preset registers enable */
128#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
129#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
130#define UCR4_INVR (1<<9) /* Inverted infrared reception */
131#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
132#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
133#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
b4cdc8f6 134#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
82313e66
SK		 135#define UCR4_IRSC (1<<5) /* IR special case */
136#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
137#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
138#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
139#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
140#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
141#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
142#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
143#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
144#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
145#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
146#define USR1_RTSS (1<<14) /* RTS pin status */
147#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
148#define USR1_RTSD (1<<12) /* RTS delta */
149#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
150#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
151#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
152#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
153#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
154#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
155#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
156#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
157#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
158#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
159#define USR2_IDLE (1<<12) /* Idle condition */
160#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
161#define USR2_WAKE (1<<7) /* Wake */
162#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
163#define USR2_TXDC (1<<3) /* Transmitter complete */
164#define USR2_BRCD (1<<2) /* Break condition */
165#define USR2_ORE (1<<1) /* Overrun error */
166#define USR2_RDR (1<<0) /* Recv data ready */
167#define UTS_FRCPERR (1<<13) /* Force parity error */
168#define UTS_LOOP (1<<12) /* Loop tx and rx */
169#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
170#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
171#define UTS_TXFULL (1<<4) /* TxFIFO full */
172#define UTS_RXFULL (1<<3) /* RxFIFO full */
173#define UTS_SOFTRST (1<<0) /* Software reset */
ff4bfb21 174
1da177e4 175/* We've been assigned a range on the "Low-density serial ports" major */
82313e66
SK		 176#define SERIAL_IMX_MAJOR 207
177#define MINOR_START 16
e3d13ff4 178#define DEV_NAME "ttymxc"
1da177e4 179
1da177e4
LT		 180/*
181 * This determines how often we check the modem status signals
182 * for any change. They generally aren't connected to an IRQ
183 * so we have to poll them. We also check immediately before
184 * filling the TX fifo incase CTS has been dropped.
185 */
186#define MCTRL_TIMEOUT (250*HZ/1000)
187
188#define DRIVER_NAME "IMX-uart"
189
dbff4e9e
SH		 190#define UART_NR 8
191
fe6b540a
SG		 192/* i.mx21 type uart runs on all i.mx except i.mx1 */
193enum imx_uart_type {
194 IMX1_UART,
195 IMX21_UART,
a496e628 196 IMX6Q_UART,
fe6b540a
SG		 197};
198
199/* device type dependent stuff */
200struct imx_uart_data {
201 unsigned uts_reg;
202 enum imx_uart_type devtype;
203};
204
1da177e4
LT		 205struct imx_port {
206 struct uart_port port;
207 struct timer_list timer;
208 unsigned int old_status;
82313e66 209 int txirq, rxirq, rtsirq;
26bbb3ff 210 unsigned int have_rtscts:1;
20ff2fe6 211 unsigned int dte_mode:1;
b6e49138
FG		 212 unsigned int use_irda:1;
213 unsigned int irda_inv_rx:1;
214 unsigned int irda_inv_tx:1;
215 unsigned short trcv_delay; /* transceiver delay */
3a9465fa
SH		 216 struct clk *clk_ipg;
217 struct clk *clk_per;
7d0b066f 218 const struct imx_uart_data *devdata;
b4cdc8f6
HS		 219
220 /* DMA fields */
221 unsigned int dma_is_inited:1;
222 unsigned int dma_is_enabled:1;
223 unsigned int dma_is_rxing:1;
224 unsigned int dma_is_txing:1;
225 struct dma_chan *dma_chan_rx, *dma_chan_tx;
226 struct scatterlist rx_sgl, tx_sgl[2];
227 void *rx_buf;
7cb92fd2 228 unsigned int tx_bytes;
b4cdc8f6 229 unsigned int dma_tx_nents;
9ce4f8f3 230 wait_queue_head_t dma_wait;
1da177e4
LT		 231};
232
0ad5a814
DB		 233struct imx_port_ucrs {
234 unsigned int ucr1;
235 unsigned int ucr2;
236 unsigned int ucr3;
237};
238
b6e49138
FG		 239#ifdef CONFIG_IRDA
240#define USE_IRDA(sport) ((sport)->use_irda)
241#else
242#define USE_IRDA(sport) (0)
243#endif
244
fe6b540a
SG		 245static struct imx_uart_data imx_uart_devdata[] = {
246 [IMX1_UART] = {
247 .uts_reg = IMX1_UTS,
248 .devtype = IMX1_UART,
249 },
250 [IMX21_UART] = {
251 .uts_reg = IMX21_UTS,
252 .devtype = IMX21_UART,
253 },
a496e628
HS		 254 [IMX6Q_UART] = {
255 .uts_reg = IMX21_UTS,
256 .devtype = IMX6Q_UART,
257 },
fe6b540a
SG		 258};
259
260static struct platform_device_id imx_uart_devtype[] = {
261 {
262 .name = "imx1-uart",
263 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
264 }, {
265 .name = "imx21-uart",
266 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
a496e628
HS		 267 }, {
268 .name = "imx6q-uart",
269 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
fe6b540a
SG		 270 }, {
271 /* sentinel */
272 }
273};
274MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
275
22698aa2 276static struct of_device_id imx_uart_dt_ids[] = {
a496e628 277 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
22698aa2
SG		 278 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
279 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
280 { /* sentinel */ }
281};
282MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
283
fe6b540a
SG		 284static inline unsigned uts_reg(struct imx_port *sport)
285{
286 return sport->devdata->uts_reg;
287}
288
289static inline int is_imx1_uart(struct imx_port *sport)
290{
291 return sport->devdata->devtype == IMX1_UART;
292}
293
294static inline int is_imx21_uart(struct imx_port *sport)
295{
296 return sport->devdata->devtype == IMX21_UART;
297}
298
a496e628
HS		 299static inline int is_imx6q_uart(struct imx_port *sport)
300{
301 return sport->devdata->devtype == IMX6Q_UART;
302}
44a75411 303/*
304 * Save and restore functions for UCR1, UCR2 and UCR3 registers
305 */
93d94b37 306#if defined(CONFIG_SERIAL_IMX_CONSOLE)
44a75411 307static void imx_port_ucrs_save(struct uart_port *port,
308 struct imx_port_ucrs *ucr)
309{
310 /* save control registers */
311 ucr->ucr1 = readl(port->membase + UCR1);
312 ucr->ucr2 = readl(port->membase + UCR2);
313 ucr->ucr3 = readl(port->membase + UCR3);
314}
315
316static void imx_port_ucrs_restore(struct uart_port *port,
317 struct imx_port_ucrs *ucr)
318{
319 /* restore control registers */
320 writel(ucr->ucr1, port->membase + UCR1);
321 writel(ucr->ucr2, port->membase + UCR2);
322 writel(ucr->ucr3, port->membase + UCR3);
323}
e8bfa760 324#endif
44a75411 325
1da177e4
LT		 326/*
327 * Handle any change of modem status signal since we were last called.
328 */
329static void imx_mctrl_check(struct imx_port *sport)
330{
331 unsigned int status, changed;
332
333 status = sport->port.ops->get_mctrl(&sport->port);
334 changed = status ^ sport->old_status;
335
336 if (changed == 0)
337 return;
338
339 sport->old_status = status;
340
341 if (changed & TIOCM_RI)
342 sport->port.icount.rng++;
343 if (changed & TIOCM_DSR)
344 sport->port.icount.dsr++;
345 if (changed & TIOCM_CAR)
346 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
347 if (changed & TIOCM_CTS)
348 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
349
bdc04e31 350 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
1da177e4
LT		 351}
352
353/*
354 * This is our per-port timeout handler, for checking the
355 * modem status signals.
356 */
357static void imx_timeout(unsigned long data)
358{
359 struct imx_port *sport = (struct imx_port *)data;
360 unsigned long flags;
361
ebd2c8f6 362 if (sport->port.state) {
1da177e4
LT		 363 spin_lock_irqsave(&sport->port.lock, flags);
364 imx_mctrl_check(sport);
365 spin_unlock_irqrestore(&sport->port.lock, flags);
366
367 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
368 }
369}
370
371/*
372 * interrupts disabled on entry
373 */
b129a8cc 374static void imx_stop_tx(struct uart_port *port)
1da177e4
LT		 375{
376 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 377 unsigned long temp;
378
b6e49138
FG		 379 if (USE_IRDA(sport)) {
380 /* half duplex - wait for end of transmission */
381 int n = 256;
382 while ((--n > 0) &&
383 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
384 udelay(5);
385 barrier();
386 }
387 /*
388 * irda transceiver - wait a bit more to avoid
389 * cutoff, hardware dependent
390 */
391 udelay(sport->trcv_delay);
392
393 /*
394 * half duplex - reactivate receive mode,
395 * flush receive pipe echo crap
396 */
397 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
398 temp = readl(sport->port.membase + UCR1);
399 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
400 writel(temp, sport->port.membase + UCR1);
401
402 temp = readl(sport->port.membase + UCR4);
403 temp &= ~(UCR4_TCEN);
404 writel(temp, sport->port.membase + UCR4);
405
406 while (readl(sport->port.membase + URXD0) &
407 URXD_CHARRDY)
408 barrier();
409
410 temp = readl(sport->port.membase + UCR1);
411 temp |= UCR1_RRDYEN;
412 writel(temp, sport->port.membase + UCR1);
413
414 temp = readl(sport->port.membase + UCR4);
415 temp |= UCR4_DREN;
416 writel(temp, sport->port.membase + UCR4);
417 }
418 return;
419 }
420
9ce4f8f3
GKH		 421 /*
422 * We are maybe in the SMP context, so if the DMA TX thread is running
423 * on other cpu, we have to wait for it to finish.
424 */
425 if (sport->dma_is_enabled && sport->dma_is_txing)
426 return;
b4cdc8f6 427
ff4bfb21
SH		 428 temp = readl(sport->port.membase + UCR1);
429 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
1da177e4
LT		 430}
431
432/*
433 * interrupts disabled on entry
434 */
435static void imx_stop_rx(struct uart_port *port)
436{
437 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 438 unsigned long temp;
439
45564a66
HS		 440 if (sport->dma_is_enabled && sport->dma_is_rxing) {
441 if (sport->port.suspended) {
442 dmaengine_terminate_all(sport->dma_chan_rx);
443 sport->dma_is_rxing = 0;
444 } else {
445 return;
446 }
447 }
b4cdc8f6 448
ff4bfb21 449 temp = readl(sport->port.membase + UCR2);
82313e66 450 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
85878399
HS		 451
452 /* disable the `Receiver Ready Interrrupt` */
453 temp = readl(sport->port.membase + UCR1);
454 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
1da177e4
LT		 455}
456
457/*
458 * Set the modem control timer to fire immediately.
459 */
460static void imx_enable_ms(struct uart_port *port)
461{
462 struct imx_port *sport = (struct imx_port *)port;
463
464 mod_timer(&sport->timer, jiffies);
465}
466
467static inline void imx_transmit_buffer(struct imx_port *sport)
468{
ebd2c8f6 469 struct circ_buf *xmit = &sport->port.state->xmit;
1da177e4 470
5e42e9a3
PH		 471 if (sport->port.x_char) {
472 /* Send next char */
473 writel(sport->port.x_char, sport->port.membase + URTX0);
7e2fb5aa
JW		 474 sport->port.icount.tx++;
475 sport->port.x_char = 0;
5e42e9a3
PH		 476 return;
477 }
478
479 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
480 imx_stop_tx(&sport->port);
481 return;
482 }
483
4e4e6602 484 while (!uart_circ_empty(xmit) &&
5e42e9a3 485 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
1da177e4
LT		 486 /* send xmit->buf[xmit->tail]
487 * out the port here */
ff4bfb21 488 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
d3810cd4 489 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1da177e4 490 sport->port.icount.tx++;
8c0b254b 491 }
1da177e4 492
97775731
FG		 493 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
494 uart_write_wakeup(&sport->port);
495
1da177e4 496 if (uart_circ_empty(xmit))
b129a8cc 497 imx_stop_tx(&sport->port);
1da177e4
LT		 498}
499
0bbc9b81 500static void imx_dma_tx(struct imx_port *sport);
b4cdc8f6
HS		 501static void dma_tx_callback(void *data)
502{
503 struct imx_port *sport = data;
504 struct scatterlist *sgl = &sport->tx_sgl[0];
505 struct circ_buf *xmit = &sport->port.state->xmit;
506 unsigned long flags;
a2c718ce 507 unsigned long temp;
b4cdc8f6 508
42f752b3 509 spin_lock_irqsave(&sport->port.lock, flags);
b4cdc8f6 510
42f752b3 511 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
b4cdc8f6 512
a2c718ce
DB		 513 temp = readl(sport->port.membase + UCR1);
514 temp &= ~UCR1_TDMAEN;
515 writel(temp, sport->port.membase + UCR1);
516
b4cdc8f6 517 /* update the stat */
b4cdc8f6
HS		 518 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
519 sport->port.icount.tx += sport->tx_bytes;
b4cdc8f6
HS		 520
521 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
522
42f752b3
DB		 523 sport->dma_is_txing = 0;
524
525 spin_unlock_irqrestore(&sport->port.lock, flags);
526
d64b8607
JW		 527 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
528 uart_write_wakeup(&sport->port);
9ce4f8f3
GKH		 529
530 if (waitqueue_active(&sport->dma_wait)) {
531 wake_up(&sport->dma_wait);
532 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
533 return;
534 }
0bbc9b81
JW		 535
536 spin_lock_irqsave(&sport->port.lock, flags);
537 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
538 imx_dma_tx(sport);
539 spin_unlock_irqrestore(&sport->port.lock, flags);
b4cdc8f6
HS		 540}
541
7cb92fd2 542static void imx_dma_tx(struct imx_port *sport)
b4cdc8f6 543{
b4cdc8f6
HS		 544 struct circ_buf *xmit = &sport->port.state->xmit;
545 struct scatterlist *sgl = sport->tx_sgl;
546 struct dma_async_tx_descriptor *desc;
547 struct dma_chan *chan = sport->dma_chan_tx;
548 struct device *dev = sport->port.dev;
a2c718ce 549 unsigned long temp;
b4cdc8f6
HS		 550 int ret;
551
42f752b3 552 if (sport->dma_is_txing)
b4cdc8f6
HS		 553 return;
554
b4cdc8f6 555 sport->tx_bytes = uart_circ_chars_pending(xmit);
b4cdc8f6 556
7942f857
DB		 557 if (xmit->tail < xmit->head) {
558 sport->dma_tx_nents = 1;
559 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
560 } else {
b4cdc8f6
HS		 561 sport->dma_tx_nents = 2;
562 sg_init_table(sgl, 2);
563 sg_set_buf(sgl, xmit->buf + xmit->tail,
564 UART_XMIT_SIZE - xmit->tail);
565 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
b4cdc8f6 566 }
b4cdc8f6
HS		 567
568 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
569 if (ret == 0) {
570 dev_err(dev, "DMA mapping error for TX.\n");
571 return;
572 }
573 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
574 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
575 if (!desc) {
24649821
DB		 576 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
577 DMA_TO_DEVICE);
b4cdc8f6
HS		 578 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
579 return;
580 }
581 desc->callback = dma_tx_callback;
582 desc->callback_param = sport;
583
584 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
585 uart_circ_chars_pending(xmit));
a2c718ce
DB		 586
587 temp = readl(sport->port.membase + UCR1);
588 temp |= UCR1_TDMAEN;
589 writel(temp, sport->port.membase + UCR1);
590
b4cdc8f6
HS		 591 /* fire it */
592 sport->dma_is_txing = 1;
593 dmaengine_submit(desc);
594 dma_async_issue_pending(chan);
595 return;
596}
597
1da177e4
LT		 598/*
599 * interrupts disabled on entry
600 */
b129a8cc 601static void imx_start_tx(struct uart_port *port)
1da177e4
LT		 602{
603 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 604 unsigned long temp;
1da177e4 605
b6e49138
FG		 606 if (USE_IRDA(sport)) {
607 /* half duplex in IrDA mode; have to disable receive mode */
608 temp = readl(sport->port.membase + UCR4);
609 temp &= ~(UCR4_DREN);
610 writel(temp, sport->port.membase + UCR4);
611
612 temp = readl(sport->port.membase + UCR1);
613 temp &= ~(UCR1_RRDYEN);
614 writel(temp, sport->port.membase + UCR1);
615 }
616
b4cdc8f6
HS		 617 if (!sport->dma_is_enabled) {
618 temp = readl(sport->port.membase + UCR1);
619 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
620 }
1da177e4 621
b6e49138
FG		 622 if (USE_IRDA(sport)) {
623 temp = readl(sport->port.membase + UCR1);
624 temp |= UCR1_TRDYEN;
625 writel(temp, sport->port.membase + UCR1);
626
627 temp = readl(sport->port.membase + UCR4);
628 temp |= UCR4_TCEN;
629 writel(temp, sport->port.membase + UCR4);
630 }
631
b4cdc8f6 632 if (sport->dma_is_enabled) {
5e42e9a3
PH		 633 /* FIXME: port->x_char must be transmitted if != 0 */
634 if (!uart_circ_empty(&port->state->xmit) &&
635 !uart_tx_stopped(port))
636 imx_dma_tx(sport);
b4cdc8f6
HS		 637 return;
638 }
1da177e4
LT		 639}
640
7d12e780 641static irqreturn_t imx_rtsint(int irq, void *dev_id)
ceca629e 642{
15aafa2f 643 struct imx_port *sport = dev_id;
5680e941 644 unsigned int val;
ceca629e
SH		 645 unsigned long flags;
646
647 spin_lock_irqsave(&sport->port.lock, flags);
648
ff4bfb21 649 writel(USR1_RTSD, sport->port.membase + USR1);
5680e941 650 val = readl(sport->port.membase + USR1) & USR1_RTSS;
ceca629e 651 uart_handle_cts_change(&sport->port, !!val);
bdc04e31 652 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
ceca629e
SH		 653
654 spin_unlock_irqrestore(&sport->port.lock, flags);
655 return IRQ_HANDLED;
656}
657
7d12e780 658static irqreturn_t imx_txint(int irq, void *dev_id)
1da177e4 659{
15aafa2f 660 struct imx_port *sport = dev_id;
1da177e4
LT		 661 unsigned long flags;
662
82313e66 663 spin_lock_irqsave(&sport->port.lock, flags);
1da177e4 664 imx_transmit_buffer(sport);
82313e66 665 spin_unlock_irqrestore(&sport->port.lock, flags);
1da177e4
LT		 666 return IRQ_HANDLED;
667}
668
7d12e780 669static irqreturn_t imx_rxint(int irq, void *dev_id)
1da177e4
LT		 670{
671 struct imx_port *sport = dev_id;
82313e66 672 unsigned int rx, flg, ignored = 0;
92a19f9c 673 struct tty_port *port = &sport->port.state->port;
ff4bfb21 674 unsigned long flags, temp;
1da177e4 675
82313e66 676 spin_lock_irqsave(&sport->port.lock, flags);
1da177e4 677
0d3c3938 678 while (readl(sport->port.membase + USR2) & USR2_RDR) {
1da177e4
LT		 679 flg = TTY_NORMAL;
680 sport->port.icount.rx++;
681
0d3c3938
SH		 682 rx = readl(sport->port.membase + URXD0);
683
ff4bfb21 684 temp = readl(sport->port.membase + USR2);
864eeed0 685 if (temp & USR2_BRCD) {
94d32f99 686 writel(USR2_BRCD, sport->port.membase + USR2);
864eeed0
SH		 687 if (uart_handle_break(&sport->port))
688 continue;
1da177e4
LT		 689 }
690
d3810cd4 691 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
864eeed0
SH		 692 continue;
693
019dc9ea
HW		 694 if (unlikely(rx & URXD_ERR)) {
695 if (rx & URXD_BRK)
696 sport->port.icount.brk++;
697 else if (rx & URXD_PRERR)
864eeed0
SH		 698 sport->port.icount.parity++;
699 else if (rx & URXD_FRMERR)
700 sport->port.icount.frame++;
701 if (rx & URXD_OVRRUN)
702 sport->port.icount.overrun++;
703
704 if (rx & sport->port.ignore_status_mask) {
705 if (++ignored > 100)
706 goto out;
707 continue;
708 }
709
710 rx &= sport->port.read_status_mask;
711
019dc9ea
HW		 712 if (rx & URXD_BRK)
713 flg = TTY_BREAK;
714 else if (rx & URXD_PRERR)
864eeed0
SH		 715 flg = TTY_PARITY;
716 else if (rx & URXD_FRMERR)
717 flg = TTY_FRAME;
718 if (rx & URXD_OVRRUN)
719 flg = TTY_OVERRUN;
1da177e4 720
864eeed0
SH		 721#ifdef SUPPORT_SYSRQ
722 sport->port.sysrq = 0;
723#endif
724 }
1da177e4 725
55d8693a
JW		 726 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
727 goto out;
728
92a19f9c 729 tty_insert_flip_char(port, rx, flg);
864eeed0 730 }
1da177e4
LT		 731
732out:
82313e66 733 spin_unlock_irqrestore(&sport->port.lock, flags);
2e124b4a 734 tty_flip_buffer_push(port);
1da177e4 735 return IRQ_HANDLED;
1da177e4
LT		 736}
737
7cb92fd2 738static int start_rx_dma(struct imx_port *sport);
b4cdc8f6
HS		 739/*
740 * If the RXFIFO is filled with some data, and then we
741 * arise a DMA operation to receive them.
742 */
743static void imx_dma_rxint(struct imx_port *sport)
744{
745 unsigned long temp;
73631813
JW		 746 unsigned long flags;
747
748 spin_lock_irqsave(&sport->port.lock, flags);
b4cdc8f6
HS		 749
750 temp = readl(sport->port.membase + USR2);
751 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
752 sport->dma_is_rxing = 1;
753
754 /* disable the `Recerver Ready Interrrupt` */
755 temp = readl(sport->port.membase + UCR1);
756 temp &= ~(UCR1_RRDYEN);
757 writel(temp, sport->port.membase + UCR1);
758
759 /* tell the DMA to receive the data. */
7cb92fd2 760 start_rx_dma(sport);
b4cdc8f6 761 }
73631813
JW		 762
763 spin_unlock_irqrestore(&sport->port.lock, flags);
b4cdc8f6
HS		 764}
765
e3d13ff4
SH		 766static irqreturn_t imx_int(int irq, void *dev_id)
767{
768 struct imx_port *sport = dev_id;
769 unsigned int sts;
f1f836e4 770 unsigned int sts2;
e3d13ff4
SH		 771
772 sts = readl(sport->port.membase + USR1);
773
b4cdc8f6
HS		 774 if (sts & USR1_RRDY) {
775 if (sport->dma_is_enabled)
776 imx_dma_rxint(sport);
777 else
778 imx_rxint(irq, dev_id);
779 }
e3d13ff4
SH		 780
781 if (sts & USR1_TRDY &&
782 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
783 imx_txint(irq, dev_id);
784
9fbe6044 785 if (sts & USR1_RTSD)
e3d13ff4
SH		 786 imx_rtsint(irq, dev_id);
787
db1a9b55
FE		 788 if (sts & USR1_AWAKE)
789 writel(USR1_AWAKE, sport->port.membase + USR1);
790
f1f836e4
AS		 791 sts2 = readl(sport->port.membase + USR2);
792 if (sts2 & USR2_ORE) {
793 dev_err(sport->port.dev, "Rx FIFO overrun\n");
794 sport->port.icount.overrun++;
795 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
796 }
797
e3d13ff4
SH		 798 return IRQ_HANDLED;
799}
800
1da177e4
LT		 801/*
802 * Return TIOCSER_TEMT when transmitter is not busy.
803 */
804static unsigned int imx_tx_empty(struct uart_port *port)
805{
806 struct imx_port *sport = (struct imx_port *)port;
1ce43e58 807 unsigned int ret;
1da177e4 808
1ce43e58 809 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1da177e4 810
1ce43e58
HS		 811 /* If the TX DMA is working, return 0. */
812 if (sport->dma_is_enabled && sport->dma_is_txing)
813 ret = 0;
814
815 return ret;
1da177e4
LT		 816}
817
0f302dc3
SH		 818/*
819 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
820 */
1da177e4
LT		 821static unsigned int imx_get_mctrl(struct uart_port *port)
822{
d3810cd4
OS		 823 struct imx_port *sport = (struct imx_port *)port;
824 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
0f302dc3 825
d3810cd4
OS		 826 if (readl(sport->port.membase + USR1) & USR1_RTSS)
827 tmp |= TIOCM_CTS;
0f302dc3 828
d3810cd4
OS		 829 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
830 tmp |= TIOCM_RTS;
0f302dc3 831
6b471a98
HS		 832 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
833 tmp |= TIOCM_LOOP;
834
d3810cd4 835 return tmp;
1da177e4
LT		 836}
837
838static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
839{
d3810cd4 840 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 841 unsigned long temp;
842
bb2f861a 843 temp = readl(sport->port.membase + UCR2) & ~(UCR2_CTS | UCR2_CTSC);
d3810cd4 844 if (mctrl & TIOCM_RTS)
bb2f861a 845 temp |= UCR2_CTS | UCR2_CTSC;
ff4bfb21
SH		 846
847 writel(temp, sport->port.membase + UCR2);
6b471a98
HS		 848
849 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
850 if (mctrl & TIOCM_LOOP)
851 temp |= UTS_LOOP;
852 writel(temp, sport->port.membase + uts_reg(sport));
1da177e4
LT		 853}
854
855/*
856 * Interrupts always disabled.
857 */
858static void imx_break_ctl(struct uart_port *port, int break_state)
859{
860 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 861 unsigned long flags, temp;
1da177e4
LT		 862
863 spin_lock_irqsave(&sport->port.lock, flags);
864
ff4bfb21
SH		 865 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
866
82313e66 867 if (break_state != 0)
ff4bfb21
SH		 868 temp |= UCR1_SNDBRK;
869
870 writel(temp, sport->port.membase + UCR1);
1da177e4
LT		 871
872 spin_unlock_irqrestore(&sport->port.lock, flags);
873}
874
875#define TXTL 2 /* reset default */
876#define RXTL 1 /* reset default */
877
587897f5
SH		 878static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
879{
880 unsigned int val;
587897f5 881
7be0670f
DB		 882 /* set receiver / transmitter trigger level */
883 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
884 val |= TXTL << UFCR_TXTL_SHF | RXTL;
ff4bfb21 885 writel(val, sport->port.membase + UFCR);
587897f5
SH		 886 return 0;
887}
888
b4cdc8f6 889#define RX_BUF_SIZE (PAGE_SIZE)
b4cdc8f6
HS		 890static void imx_rx_dma_done(struct imx_port *sport)
891{
892 unsigned long temp;
73631813
JW		 893 unsigned long flags;
894
895 spin_lock_irqsave(&sport->port.lock, flags);
b4cdc8f6
HS		 896
897 /* Enable this interrupt when the RXFIFO is empty. */
898 temp = readl(sport->port.membase + UCR1);
899 temp |= UCR1_RRDYEN;
900 writel(temp, sport->port.membase + UCR1);
901
902 sport->dma_is_rxing = 0;
9ce4f8f3
GKH		 903
904 /* Is the shutdown waiting for us? */
905 if (waitqueue_active(&sport->dma_wait))
906 wake_up(&sport->dma_wait);
73631813
JW		 907
908 spin_unlock_irqrestore(&sport->port.lock, flags);
b4cdc8f6
HS		 909}
910
911/*
912 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
913 * [1] the RX DMA buffer is full.
914 * [2] the Aging timer expires(wait for 8 bytes long)
915 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
916 *
917 * The [2] is trigger when a character was been sitting in the FIFO
918 * meanwhile [3] can wait for 32 bytes long when the RX line is
919 * on IDLE state and RxFIFO is empty.
920 */
921static void dma_rx_callback(void *data)
922{
923 struct imx_port *sport = data;
924 struct dma_chan *chan = sport->dma_chan_rx;
925 struct scatterlist *sgl = &sport->rx_sgl;
7cb92fd2 926 struct tty_port *port = &sport->port.state->port;
b4cdc8f6
HS		 927 struct dma_tx_state state;
928 enum dma_status status;
929 unsigned int count;
930
931 /* unmap it first */
932 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
933
f0ef8834 934 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
b4cdc8f6
HS		 935 count = RX_BUF_SIZE - state.residue;
936 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
937
938 if (count) {
55d8693a
JW		 939 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ))
940 tty_insert_flip_string(port, sport->rx_buf, count);
7cb92fd2
HS		 941 tty_flip_buffer_push(port);
942
943 start_rx_dma(sport);
ee5e7c10
RG		 944 } else if (readl(sport->port.membase + USR2) & USR2_RDR) {
945 /*
946 * start rx_dma directly once data in RXFIFO, more efficient
947 * than before:
948 * 1. call imx_rx_dma_done to stop dma if no data received
949 * 2. wait next RDR interrupt to start dma transfer.
950 */
951 start_rx_dma(sport);
952 } else {
953 /*
954 * stop dma to prevent too many IDLE event trigged if no data
955 * in RXFIFO
956 */
b4cdc8f6 957 imx_rx_dma_done(sport);
ee5e7c10 958 }
b4cdc8f6
HS		 959}
960
961static int start_rx_dma(struct imx_port *sport)
962{
963 struct scatterlist *sgl = &sport->rx_sgl;
964 struct dma_chan *chan = sport->dma_chan_rx;
965 struct device *dev = sport->port.dev;
966 struct dma_async_tx_descriptor *desc;
967 int ret;
968
969 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
970 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
971 if (ret == 0) {
972 dev_err(dev, "DMA mapping error for RX.\n");
973 return -EINVAL;
974 }
975 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
976 DMA_PREP_INTERRUPT);
977 if (!desc) {
24649821 978 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
b4cdc8f6
HS		 979 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
980 return -EINVAL;
981 }
982 desc->callback = dma_rx_callback;
983 desc->callback_param = sport;
984
985 dev_dbg(dev, "RX: prepare for the DMA.\n");
986 dmaengine_submit(desc);
987 dma_async_issue_pending(chan);
988 return 0;
989}
990
991static void imx_uart_dma_exit(struct imx_port *sport)
992{
993 if (sport->dma_chan_rx) {
994 dma_release_channel(sport->dma_chan_rx);
995 sport->dma_chan_rx = NULL;
996
997 kfree(sport->rx_buf);
998 sport->rx_buf = NULL;
999 }
1000
1001 if (sport->dma_chan_tx) {
1002 dma_release_channel(sport->dma_chan_tx);
1003 sport->dma_chan_tx = NULL;
1004 }
1005
1006 sport->dma_is_inited = 0;
1007}
1008
1009static int imx_uart_dma_init(struct imx_port *sport)
1010{
b09c74ae 1011 struct dma_slave_config slave_config = {};
b4cdc8f6
HS		 1012 struct device *dev = sport->port.dev;
1013 int ret;
1014
1015 /* Prepare for RX : */
1016 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1017 if (!sport->dma_chan_rx) {
1018 dev_dbg(dev, "cannot get the DMA channel.\n");
1019 ret = -EINVAL;
1020 goto err;
1021 }
1022
1023 slave_config.direction = DMA_DEV_TO_MEM;
1024 slave_config.src_addr = sport->port.mapbase + URXD0;
1025 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1026 slave_config.src_maxburst = RXTL;
1027 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1028 if (ret) {
1029 dev_err(dev, "error in RX dma configuration.\n");
1030 goto err;
1031 }
1032
1033 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1034 if (!sport->rx_buf) {
b4cdc8f6
HS		 1035 ret = -ENOMEM;
1036 goto err;
1037 }
b4cdc8f6
HS		 1038
1039 /* Prepare for TX : */
1040 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1041 if (!sport->dma_chan_tx) {
1042 dev_err(dev, "cannot get the TX DMA channel!\n");
1043 ret = -EINVAL;
1044 goto err;
1045 }
1046
1047 slave_config.direction = DMA_MEM_TO_DEV;
1048 slave_config.dst_addr = sport->port.mapbase + URTX0;
1049 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1050 slave_config.dst_maxburst = TXTL;
1051 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1052 if (ret) {
1053 dev_err(dev, "error in TX dma configuration.");
1054 goto err;
1055 }
1056
1057 sport->dma_is_inited = 1;
1058
1059 return 0;
1060err:
1061 imx_uart_dma_exit(sport);
1062 return ret;
1063}
1064
1065static void imx_enable_dma(struct imx_port *sport)
1066{
1067 unsigned long temp;
b4cdc8f6 1068
9ce4f8f3
GKH		 1069 init_waitqueue_head(&sport->dma_wait);
1070
b4cdc8f6
HS		 1071 /* set UCR1 */
1072 temp = readl(sport->port.membase + UCR1);
1073 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1074 /* wait for 32 idle frames for IDDMA interrupt */
1075 UCR1_ICD_REG(3);
1076 writel(temp, sport->port.membase + UCR1);
1077
1078 /* set UCR4 */
1079 temp = readl(sport->port.membase + UCR4);
1080 temp |= UCR4_IDDMAEN;
1081 writel(temp, sport->port.membase + UCR4);
1082
1083 sport->dma_is_enabled = 1;
1084}
1085
1086static void imx_disable_dma(struct imx_port *sport)
1087{
1088 unsigned long temp;
b4cdc8f6
HS		 1089
1090 /* clear UCR1 */
1091 temp = readl(sport->port.membase + UCR1);
1092 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1093 writel(temp, sport->port.membase + UCR1);
1094
1095 /* clear UCR2 */
1096 temp = readl(sport->port.membase + UCR2);
1097 temp &= ~(UCR2_CTSC | UCR2_CTS);
1098 writel(temp, sport->port.membase + UCR2);
1099
1100 /* clear UCR4 */
1101 temp = readl(sport->port.membase + UCR4);
1102 temp &= ~UCR4_IDDMAEN;
1103 writel(temp, sport->port.membase + UCR4);
1104
1105 sport->dma_is_enabled = 0;
b4cdc8f6
HS		 1106}
1107
1c5250d6
VL		 1108/* half the RX buffer size */
1109#define CTSTL 16
1110
1da177e4
LT		 1111static int imx_startup(struct uart_port *port)
1112{
1113 struct imx_port *sport = (struct imx_port *)port;
772f8991 1114 int retval, i;
ff4bfb21 1115 unsigned long flags, temp;
1da177e4 1116
1cf93e0d
HS		 1117 retval = clk_prepare_enable(sport->clk_per);
1118 if (retval)
cb0f0a5f 1119 return retval;
1cf93e0d
HS		 1120 retval = clk_prepare_enable(sport->clk_ipg);
1121 if (retval) {
1122 clk_disable_unprepare(sport->clk_per);
cb0f0a5f 1123 return retval;
0c375501 1124 }
28eb4274 1125
587897f5 1126 imx_setup_ufcr(sport, 0);
1da177e4
LT		 1127
1128 /* disable the DREN bit (Data Ready interrupt enable) before
1129 * requesting IRQs
1130 */
ff4bfb21 1131 temp = readl(sport->port.membase + UCR4);
b6e49138
FG		 1132
1133 if (USE_IRDA(sport))
1134 temp |= UCR4_IRSC;
1135
1c5250d6 1136 /* set the trigger level for CTS */
82313e66
SK		 1137 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1138 temp |= CTSTL << UCR4_CTSTL_SHF;
1c5250d6 1139
ff4bfb21 1140 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1da177e4 1141
772f8991
HS		 1142 /* Reset fifo's and state machines */
1143 i = 100;
1144
1145 temp = readl(sport->port.membase + UCR2);
1146 temp &= ~UCR2_SRST;
1147 writel(temp, sport->port.membase + UCR2);
1148
1149 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1150 udelay(1);
b6e49138 1151
068500e0
AB		 1152 /* Can we enable the DMA support? */
1153 if (is_imx6q_uart(sport) && !uart_console(port) &&
1154 !sport->dma_is_inited)
1155 imx_uart_dma_init(sport);
1156
9ec1882d 1157 spin_lock_irqsave(&sport->port.lock, flags);
1da177e4
LT		 1158 /*
1159 * Finally, clear and enable interrupts
1160 */
ff4bfb21
SH		 1161 writel(USR1_RTSD, sport->port.membase + USR1);
1162
068500e0
AB		 1163 if (sport->dma_is_inited && !sport->dma_is_enabled)
1164 imx_enable_dma(sport);
1165
ff4bfb21 1166 temp = readl(sport->port.membase + UCR1);
789d5258 1167 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
b6e49138
FG		 1168
1169 if (USE_IRDA(sport)) {
1170 temp |= UCR1_IREN;
1171 temp &= ~(UCR1_RTSDEN);
1172 }
1173
ff4bfb21 1174 writel(temp, sport->port.membase + UCR1);
1da177e4 1175
6f026d6b
JW		 1176 /* Clear any pending ORE flag before enabling interrupt */
1177 temp = readl(sport->port.membase + USR2);
1178 writel(temp | USR2_ORE, sport->port.membase + USR2);
1179
1180 temp = readl(sport->port.membase + UCR4);
1181 temp |= UCR4_OREN;
1182 writel(temp, sport->port.membase + UCR4);
1183
ff4bfb21
SH		 1184 temp = readl(sport->port.membase + UCR2);
1185 temp |= (UCR2_RXEN | UCR2_TXEN);
bff09b09
LS		 1186 if (!sport->have_rtscts)
1187 temp |= UCR2_IRTS;
ff4bfb21 1188 writel(temp, sport->port.membase + UCR2);
1da177e4 1189
a496e628 1190 if (!is_imx1_uart(sport)) {
37d6fb62 1191 temp = readl(sport->port.membase + UCR3);
b38cb7d2 1192 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
37d6fb62
SH		 1193 writel(temp, sport->port.membase + UCR3);
1194 }
4411805b 1195
b6e49138
FG		 1196 if (USE_IRDA(sport)) {
1197 temp = readl(sport->port.membase + UCR4);
1198 if (sport->irda_inv_rx)
1199 temp |= UCR4_INVR;
1200 else
1201 temp &= ~(UCR4_INVR);
1202 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
1203
1204 temp = readl(sport->port.membase + UCR3);
1205 if (sport->irda_inv_tx)
1206 temp |= UCR3_INVT;
1207 else
1208 temp &= ~(UCR3_INVT);
1209 writel(temp, sport->port.membase + UCR3);
1210 }
1211
1da177e4
LT		 1212 /*
1213 * Enable modem status interrupts
1214 */
1da177e4 1215 imx_enable_ms(&sport->port);
82313e66 1216 spin_unlock_irqrestore(&sport->port.lock, flags);
1da177e4 1217
b6e49138
FG		 1218 if (USE_IRDA(sport)) {
1219 struct imxuart_platform_data *pdata;
574de559 1220 pdata = dev_get_platdata(sport->port.dev);
b6e49138
FG		 1221 sport->irda_inv_rx = pdata->irda_inv_rx;
1222 sport->irda_inv_tx = pdata->irda_inv_tx;
1223 sport->trcv_delay = pdata->transceiver_delay;
1224 if (pdata->irda_enable)
1225 pdata->irda_enable(1);
1226 }
1227
1da177e4 1228 return 0;
1da177e4
LT		 1229}
1230
1231static void imx_shutdown(struct uart_port *port)
1232{
1233 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 1234 unsigned long temp;
9ec1882d 1235 unsigned long flags;
1da177e4 1236
b4cdc8f6 1237 if (sport->dma_is_enabled) {
a4688bcd
HS		 1238 int ret;
1239
9ce4f8f3 1240 /* We have to wait for the DMA to finish. */
a4688bcd 1241 ret = wait_event_interruptible(sport->dma_wait,
9ce4f8f3 1242 !sport->dma_is_rxing && !sport->dma_is_txing);
a4688bcd
HS		 1243 if (ret != 0) {
1244 sport->dma_is_rxing = 0;
1245 sport->dma_is_txing = 0;
1246 dmaengine_terminate_all(sport->dma_chan_tx);
1247 dmaengine_terminate_all(sport->dma_chan_rx);
1248 }
73631813 1249 spin_lock_irqsave(&sport->port.lock, flags);
a4688bcd 1250 imx_stop_tx(port);
b4cdc8f6
HS		 1251 imx_stop_rx(port);
1252 imx_disable_dma(sport);
73631813 1253 spin_unlock_irqrestore(&sport->port.lock, flags);
b4cdc8f6
HS		 1254 imx_uart_dma_exit(sport);
1255 }
1256
9ec1882d 1257 spin_lock_irqsave(&sport->port.lock, flags);
2e146392
FG		 1258 temp = readl(sport->port.membase + UCR2);
1259 temp &= ~(UCR2_TXEN);
1260 writel(temp, sport->port.membase + UCR2);
9ec1882d 1261 spin_unlock_irqrestore(&sport->port.lock, flags);
2e146392 1262
b6e49138
FG		 1263 if (USE_IRDA(sport)) {
1264 struct imxuart_platform_data *pdata;
574de559 1265 pdata = dev_get_platdata(sport->port.dev);
b6e49138
FG		 1266 if (pdata->irda_enable)
1267 pdata->irda_enable(0);
1268 }
1269
1da177e4
LT		 1270 /*
1271 * Stop our timer.
1272 */
1273 del_timer_sync(&sport->timer);
1274
1da177e4
LT		 1275 /*
1276 * Disable all interrupts, port and break condition.
1277 */
1278
9ec1882d 1279 spin_lock_irqsave(&sport->port.lock, flags);
ff4bfb21
SH		 1280 temp = readl(sport->port.membase + UCR1);
1281 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
b6e49138
FG		 1282 if (USE_IRDA(sport))
1283 temp &= ~(UCR1_IREN);
1284
ff4bfb21 1285 writel(temp, sport->port.membase + UCR1);
9ec1882d 1286 spin_unlock_irqrestore(&sport->port.lock, flags);
28eb4274 1287
1cf93e0d
HS		 1288 clk_disable_unprepare(sport->clk_per);
1289 clk_disable_unprepare(sport->clk_ipg);
1da177e4
LT		 1290}
1291
eb56b7ed
HS		 1292static void imx_flush_buffer(struct uart_port *port)
1293{
1294 struct imx_port *sport = (struct imx_port *)port;
82e86ae9 1295 struct scatterlist *sgl = &sport->tx_sgl[0];
a2c718ce 1296 unsigned long temp;
eb56b7ed 1297
82e86ae9
DB		 1298 if (!sport->dma_chan_tx)
1299 return;
1300
1301 sport->tx_bytes = 0;
1302 dmaengine_terminate_all(sport->dma_chan_tx);
1303 if (sport->dma_is_txing) {
1304 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1305 DMA_TO_DEVICE);
a2c718ce
DB		 1306 temp = readl(sport->port.membase + UCR1);
1307 temp &= ~UCR1_TDMAEN;
1308 writel(temp, sport->port.membase + UCR1);
82e86ae9 1309 sport->dma_is_txing = false;
eb56b7ed
HS		 1310 }
1311}
1312
1da177e4 1313static void
606d099c
AC		 1314imx_set_termios(struct uart_port *port, struct ktermios *termios,
1315 struct ktermios *old)
1da177e4
LT		 1316{
1317 struct imx_port *sport = (struct imx_port *)port;
1318 unsigned long flags;
1319 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1320 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
534fca06
OS		 1321 unsigned int div, ufcr;
1322 unsigned long num, denom;
d7f8d437 1323 uint64_t tdiv64;
1da177e4
LT		 1324
1325 /*
1326 * If we don't support modem control lines, don't allow
1327 * these to be set.
1328 */
1329 if (0) {
1330 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
1331 termios->c_cflag |= CLOCAL;
1332 }
1333
1334 /*
1335 * We only support CS7 and CS8.
1336 */
1337 while ((termios->c_cflag & CSIZE) != CS7 &&
1338 (termios->c_cflag & CSIZE) != CS8) {
1339 termios->c_cflag &= ~CSIZE;
1340 termios->c_cflag |= old_csize;
1341 old_csize = CS8;
1342 }
1343
1344 if ((termios->c_cflag & CSIZE) == CS8)
1345 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1346 else
1347 ucr2 = UCR2_SRST | UCR2_IRTS;
1348
1349 if (termios->c_cflag & CRTSCTS) {
82313e66 1350 if (sport->have_rtscts) {
5b802344
SH		 1351 ucr2 &= ~UCR2_IRTS;
1352 ucr2 |= UCR2_CTSC;
1353 } else {
1354 termios->c_cflag &= ~CRTSCTS;
1355 }
1da177e4
LT		 1356 }
1357
1358 if (termios->c_cflag & CSTOPB)
1359 ucr2 |= UCR2_STPB;
1360 if (termios->c_cflag & PARENB) {
1361 ucr2 |= UCR2_PREN;
3261e362 1362 if (termios->c_cflag & PARODD)
1da177e4
LT		 1363 ucr2 |= UCR2_PROE;
1364 }
1365
995234da
EM		 1366 del_timer_sync(&sport->timer);
1367
1da177e4
LT		 1368 /*
1369 * Ask the core to calculate the divisor for us.
1370 */
036bb15e 1371 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1da177e4
LT		 1372 quot = uart_get_divisor(port, baud);
1373
1374 spin_lock_irqsave(&sport->port.lock, flags);
1375
1376 sport->port.read_status_mask = 0;
1377 if (termios->c_iflag & INPCK)
1378 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1379 if (termios->c_iflag & (BRKINT | PARMRK))
1380 sport->port.read_status_mask |= URXD_BRK;
1381
1382 /*
1383 * Characters to ignore
1384 */
1385 sport->port.ignore_status_mask = 0;
1386 if (termios->c_iflag & IGNPAR)
1387 sport->port.ignore_status_mask |= URXD_PRERR;
1388 if (termios->c_iflag & IGNBRK) {
1389 sport->port.ignore_status_mask |= URXD_BRK;
1390 /*
1391 * If we're ignoring parity and break indicators,
1392 * ignore overruns too (for real raw support).
1393 */
1394 if (termios->c_iflag & IGNPAR)
1395 sport->port.ignore_status_mask |= URXD_OVRRUN;
1396 }
1397
55d8693a
JW		 1398 if ((termios->c_cflag & CREAD) == 0)
1399 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1400
1da177e4
LT		 1401 /*
1402 * Update the per-port timeout.
1403 */
1404 uart_update_timeout(port, termios->c_cflag, baud);
1405
1406 /*
1407 * disable interrupts and drain transmitter
1408 */
ff4bfb21
SH		 1409 old_ucr1 = readl(sport->port.membase + UCR1);
1410 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1411 sport->port.membase + UCR1);
1da177e4 1412
82313e66 1413 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1da177e4
LT		 1414 barrier();
1415
1416 /* then, disable everything */
ff4bfb21 1417 old_txrxen = readl(sport->port.membase + UCR2);
82313e66 1418 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
ff4bfb21
SH		 1419 sport->port.membase + UCR2);
1420 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1da177e4 1421
b6e49138
FG		 1422 if (USE_IRDA(sport)) {
1423 /*
1424 * use maximum available submodule frequency to
1425 * avoid missing short pulses due to low sampling rate
1426 */
036bb15e 1427 div = 1;
b6e49138 1428 } else {
09bd00f6
HF		 1429 /* custom-baudrate handling */
1430 div = sport->port.uartclk / (baud * 16);
1431 if (baud == 38400 && quot != div)
1432 baud = sport->port.uartclk / (quot * 16);
1433
b6e49138
FG		 1434 div = sport->port.uartclk / (baud * 16);
1435 if (div > 7)
1436 div = 7;
1437 if (!div)
1438 div = 1;
1439 }
036bb15e 1440
534fca06
OS		 1441 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1442 1 << 16, 1 << 16, &num, &denom);
036bb15e 1443
eab4f5af
AC		 1444 tdiv64 = sport->port.uartclk;
1445 tdiv64 *= num;
1446 do_div(tdiv64, denom * 16 * div);
1447 tty_termios_encode_baud_rate(termios,
1a2c4b31 1448 (speed_t)tdiv64, (speed_t)tdiv64);
d7f8d437 1449
534fca06
OS		 1450 num -= 1;
1451 denom -= 1;
036bb15e
SH		 1452
1453 ufcr = readl(sport->port.membase + UFCR);
b6e49138 1454 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
20ff2fe6
HS		 1455 if (sport->dte_mode)
1456 ufcr |= UFCR_DCEDTE;
036bb15e
SH		 1457 writel(ufcr, sport->port.membase + UFCR);
1458
534fca06
OS		 1459 writel(num, sport->port.membase + UBIR);
1460 writel(denom, sport->port.membase + UBMR);
1461
a496e628 1462 if (!is_imx1_uart(sport))
37d6fb62 1463 writel(sport->port.uartclk / div / 1000,
fe6b540a 1464 sport->port.membase + IMX21_ONEMS);
ff4bfb21
SH		 1465
1466 writel(old_ucr1, sport->port.membase + UCR1);
1da177e4 1467
ff4bfb21
SH		 1468 /* set the parity, stop bits and data size */
1469 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1da177e4
LT		 1470
1471 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1472 imx_enable_ms(&sport->port);
1473
1474 spin_unlock_irqrestore(&sport->port.lock, flags);
1475}
1476
1477static const char *imx_type(struct uart_port *port)
1478{
1479 struct imx_port *sport = (struct imx_port *)port;
1480
1481 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1482}
1483
1da177e4
LT		 1484/*
1485 * Configure/autoconfigure the port.
1486 */
1487static void imx_config_port(struct uart_port *port, int flags)
1488{
1489 struct imx_port *sport = (struct imx_port *)port;
1490
da82f997 1491 if (flags & UART_CONFIG_TYPE)
1da177e4
LT		 1492 sport->port.type = PORT_IMX;
1493}
1494
1495/*
1496 * Verify the new serial_struct (for TIOCSSERIAL).
1497 * The only change we allow are to the flags and type, and
1498 * even then only between PORT_IMX and PORT_UNKNOWN
1499 */
1500static int
1501imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1502{
1503 struct imx_port *sport = (struct imx_port *)port;
1504 int ret = 0;
1505
1506 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1507 ret = -EINVAL;
1508 if (sport->port.irq != ser->irq)
1509 ret = -EINVAL;
1510 if (ser->io_type != UPIO_MEM)
1511 ret = -EINVAL;
1512 if (sport->port.uartclk / 16 != ser->baud_base)
1513 ret = -EINVAL;
a50c44ce 1514 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1da177e4
LT		 1515 ret = -EINVAL;
1516 if (sport->port.iobase != ser->port)
1517 ret = -EINVAL;
1518 if (ser->hub6 != 0)
1519 ret = -EINVAL;
1520 return ret;
1521}
1522
01f56abd 1523#if defined(CONFIG_CONSOLE_POLL)
6b8bdad9
DT		 1524
1525static int imx_poll_init(struct uart_port *port)
1526{
1527 struct imx_port *sport = (struct imx_port *)port;
1528 unsigned long flags;
1529 unsigned long temp;
1530 int retval;
1531
1532 retval = clk_prepare_enable(sport->clk_ipg);
1533 if (retval)
1534 return retval;
1535 retval = clk_prepare_enable(sport->clk_per);
1536 if (retval)
1537 clk_disable_unprepare(sport->clk_ipg);
1538
1539 imx_setup_ufcr(sport, 0);
1540
1541 spin_lock_irqsave(&sport->port.lock, flags);
1542
1543 temp = readl(sport->port.membase + UCR1);
1544 if (is_imx1_uart(sport))
1545 temp |= IMX1_UCR1_UARTCLKEN;
1546 temp |= UCR1_UARTEN | UCR1_RRDYEN;
1547 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1548 writel(temp, sport->port.membase + UCR1);
1549
1550 temp = readl(sport->port.membase + UCR2);
1551 temp |= UCR2_RXEN;
1552 writel(temp, sport->port.membase + UCR2);
1553
1554 spin_unlock_irqrestore(&sport->port.lock, flags);
1555
1556 return 0;
1557}
1558
01f56abd
SA		 1559static int imx_poll_get_char(struct uart_port *port)
1560{
f968ef34 1561 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
26c47412 1562 return NO_POLL_CHAR;
01f56abd 1563
f968ef34 1564 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
01f56abd
SA		 1565}
1566
1567static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1568{
01f56abd
SA		 1569 unsigned int status;
1570
01f56abd
SA		 1571 /* drain */
1572 do {
f968ef34 1573 status = readl_relaxed(port->membase + USR1);
01f56abd
SA		 1574 } while (~status & USR1_TRDY);
1575
1576 /* write */
f968ef34 1577 writel_relaxed(c, port->membase + URTX0);
01f56abd
SA		 1578
1579 /* flush */
1580 do {
f968ef34 1581 status = readl_relaxed(port->membase + USR2);
01f56abd 1582 } while (~status & USR2_TXDC);
01f56abd
SA		 1583}
1584#endif
1585
1da177e4
LT		 1586static struct uart_ops imx_pops = {
1587 .tx_empty = imx_tx_empty,
1588 .set_mctrl = imx_set_mctrl,
1589 .get_mctrl = imx_get_mctrl,
1590 .stop_tx = imx_stop_tx,
1591 .start_tx = imx_start_tx,
1592 .stop_rx = imx_stop_rx,
1593 .enable_ms = imx_enable_ms,
1594 .break_ctl = imx_break_ctl,
1595 .startup = imx_startup,
1596 .shutdown = imx_shutdown,
eb56b7ed 1597 .flush_buffer = imx_flush_buffer,
1da177e4
LT		 1598 .set_termios = imx_set_termios,
1599 .type = imx_type,
1da177e4
LT		 1600 .config_port = imx_config_port,
1601 .verify_port = imx_verify_port,
01f56abd 1602#if defined(CONFIG_CONSOLE_POLL)
6b8bdad9 1603 .poll_init = imx_poll_init,
01f56abd
SA		 1604 .poll_get_char = imx_poll_get_char,
1605 .poll_put_char = imx_poll_put_char,
1606#endif
1da177e4
LT		 1607};
1608
dbff4e9e 1609static struct imx_port *imx_ports[UART_NR];
1da177e4
LT		 1610
1611#ifdef CONFIG_SERIAL_IMX_CONSOLE
d358788f
RK		 1612static void imx_console_putchar(struct uart_port *port, int ch)
1613{
1614 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 1615
fe6b540a 1616 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
d358788f 1617 barrier();
ff4bfb21
SH		 1618
1619 writel(ch, sport->port.membase + URTX0);
d358788f 1620}
1da177e4
LT		 1621
1622/*
1623 * Interrupts are disabled on entering
1624 */
1625static void
1626imx_console_write(struct console *co, const char *s, unsigned int count)
1627{
dbff4e9e 1628 struct imx_port *sport = imx_ports[co->index];
0ad5a814
DB		 1629 struct imx_port_ucrs old_ucr;
1630 unsigned int ucr1;
f30e8260 1631 unsigned long flags = 0;
677fe555 1632 int locked = 1;
1cf93e0d
HS		 1633 int retval;
1634
1635 retval = clk_enable(sport->clk_per);
1636 if (retval)
1637 return;
1638 retval = clk_enable(sport->clk_ipg);
1639 if (retval) {
1640 clk_disable(sport->clk_per);
1641 return;
1642 }
9ec1882d 1643
677fe555
TG		 1644 if (sport->port.sysrq)
1645 locked = 0;
1646 else if (oops_in_progress)
1647 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1648 else
1649 spin_lock_irqsave(&sport->port.lock, flags);
1da177e4
LT		 1650
1651 /*
0ad5a814 1652 * First, save UCR1/2/3 and then disable interrupts
1da177e4 1653 */
0ad5a814
DB		 1654 imx_port_ucrs_save(&sport->port, &old_ucr);
1655 ucr1 = old_ucr.ucr1;
1da177e4 1656
fe6b540a
SG		 1657 if (is_imx1_uart(sport))
1658 ucr1 |= IMX1_UCR1_UARTCLKEN;
37d6fb62
SH		 1659 ucr1 |= UCR1_UARTEN;
1660 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1661
1662 writel(ucr1, sport->port.membase + UCR1);
ff4bfb21 1663
0ad5a814 1664 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1da177e4 1665
d358788f 1666 uart_console_write(&sport->port, s, count, imx_console_putchar);
1da177e4
LT		 1667
1668 /*
1669 * Finally, wait for transmitter to become empty
0ad5a814 1670 * and restore UCR1/2/3
1da177e4 1671 */
ff4bfb21 1672 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1da177e4 1673
0ad5a814 1674 imx_port_ucrs_restore(&sport->port, &old_ucr);
9ec1882d 1675
677fe555
TG		 1676 if (locked)
1677 spin_unlock_irqrestore(&sport->port.lock, flags);
1cf93e0d
HS		 1678
1679 clk_disable(sport->clk_ipg);
1680 clk_disable(sport->clk_per);
1da177e4
LT		 1681}
1682
1683/*
1684 * If the port was already initialised (eg, by a boot loader),
1685 * try to determine the current setup.
1686 */
1687static void __init
1688imx_console_get_options(struct imx_port *sport, int *baud,
1689 int *parity, int *bits)
1690{
587897f5 1691
2e2eb509 1692 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1da177e4 1693 /* ok, the port was enabled */
82313e66 1694 unsigned int ucr2, ubir, ubmr, uartclk;
587897f5
SH		 1695 unsigned int baud_raw;
1696 unsigned int ucfr_rfdiv;
1da177e4 1697
ff4bfb21 1698 ucr2 = readl(sport->port.membase + UCR2);
1da177e4
LT		 1699
1700 *parity = 'n';
1701 if (ucr2 & UCR2_PREN) {
1702 if (ucr2 & UCR2_PROE)
1703 *parity = 'o';
1704 else
1705 *parity = 'e';
1706 }
1707
1708 if (ucr2 & UCR2_WS)
1709 *bits = 8;
1710 else
1711 *bits = 7;
1712
ff4bfb21
SH		 1713 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1714 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
587897f5 1715
ff4bfb21 1716 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
587897f5
SH		 1717 if (ucfr_rfdiv == 6)
1718 ucfr_rfdiv = 7;
1719 else
1720 ucfr_rfdiv = 6 - ucfr_rfdiv;
1721
3a9465fa 1722 uartclk = clk_get_rate(sport->clk_per);
587897f5
SH		 1723 uartclk /= ucfr_rfdiv;
1724
1725 { /*
1726 * The next code provides exact computation of
1727 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1728 * without need of float support or long long division,
1729 * which would be required to prevent 32bit arithmetic overflow
1730 */
1731 unsigned int mul = ubir + 1;
1732 unsigned int div = 16 * (ubmr + 1);
1733 unsigned int rem = uartclk % div;
1734
1735 baud_raw = (uartclk / div) * mul;
1736 baud_raw += (rem * mul + div / 2) / div;
1737 *baud = (baud_raw + 50) / 100 * 100;
1738 }
1739
82313e66 1740 if (*baud != baud_raw)
50bbdba3 1741 pr_info("Console IMX rounded baud rate from %d to %d\n",
587897f5 1742 baud_raw, *baud);
1da177e4
LT		 1743 }
1744}
1745
1746static int __init
1747imx_console_setup(struct console *co, char *options)
1748{
1749 struct imx_port *sport;
1750 int baud = 9600;
1751 int bits = 8;
1752 int parity = 'n';
1753 int flow = 'n';
1cf93e0d 1754 int retval;
1da177e4
LT		 1755
1756 /*
1757 * Check whether an invalid uart number has been specified, and
1758 * if so, search for the first available port that does have
1759 * console support.
1760 */
1761 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1762 co->index = 0;
dbff4e9e 1763 sport = imx_ports[co->index];
82313e66 1764 if (sport == NULL)
e76afc4e 1765 return -ENODEV;
1da177e4 1766
1cf93e0d
HS		 1767 /* For setting the registers, we only need to enable the ipg clock. */
1768 retval = clk_prepare_enable(sport->clk_ipg);
1769 if (retval)
1770 goto error_console;
1771
1da177e4
LT		 1772 if (options)
1773 uart_parse_options(options, &baud, &parity, &bits, &flow);
1774 else
1775 imx_console_get_options(sport, &baud, &parity, &bits);
1776
587897f5
SH		 1777 imx_setup_ufcr(sport, 0);
1778
1cf93e0d
HS		 1779 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1780
1781 clk_disable(sport->clk_ipg);
1782 if (retval) {
1783 clk_unprepare(sport->clk_ipg);
1784 goto error_console;
1785 }
1786
1787 retval = clk_prepare(sport->clk_per);
1788 if (retval)
1789 clk_disable_unprepare(sport->clk_ipg);
1790
1791error_console:
1792 return retval;
1da177e4
LT		 1793}
1794
9f4426dd 1795static struct uart_driver imx_reg;
1da177e4 1796static struct console imx_console = {
e3d13ff4 1797 .name = DEV_NAME,
1da177e4
LT		 1798 .write = imx_console_write,
1799 .device = uart_console_device,
1800 .setup = imx_console_setup,
1801 .flags = CON_PRINTBUFFER,
1802 .index = -1,
1803 .data = &imx_reg,
1804};
1805
1da177e4
LT		 1806#define IMX_CONSOLE &imx_console
1807#else
1808#define IMX_CONSOLE NULL
1809#endif
1810
1811static struct uart_driver imx_reg = {
1812 .owner = THIS_MODULE,
1813 .driver_name = DRIVER_NAME,
e3d13ff4 1814 .dev_name = DEV_NAME,
1da177e4
LT		 1815 .major = SERIAL_IMX_MAJOR,
1816 .minor = MINOR_START,
1817 .nr = ARRAY_SIZE(imx_ports),
1818 .cons = IMX_CONSOLE,
1819};
1820
3ae5eaec 1821static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1822{
d3810cd4 1823 struct imx_port *sport = platform_get_drvdata(dev);
db1a9b55
FE		 1824 unsigned int val;
1825
1826 /* enable wakeup from i.MX UART */
1827 val = readl(sport->port.membase + UCR3);
1828 val |= UCR3_AWAKEN;
1829 writel(val, sport->port.membase + UCR3);
1da177e4 1830
034dc4db 1831 uart_suspend_port(&imx_reg, &sport->port);
1da177e4 1832
d3810cd4 1833 return 0;
1da177e4
LT		 1834}
1835
3ae5eaec 1836static int serial_imx_resume(struct platform_device *dev)
1da177e4 1837{
d3810cd4 1838 struct imx_port *sport = platform_get_drvdata(dev);
db1a9b55
FE		 1839 unsigned int val;
1840
1841 /* disable wakeup from i.MX UART */
1842 val = readl(sport->port.membase + UCR3);
1843 val &= ~UCR3_AWAKEN;
1844 writel(val, sport->port.membase + UCR3);
1da177e4 1845
034dc4db 1846 uart_resume_port(&imx_reg, &sport->port);
1da177e4 1847
d3810cd4 1848 return 0;
1da177e4
LT		 1849}
1850
22698aa2 1851#ifdef CONFIG_OF
20bb8095
UKK		 1852/*
1853 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1854 * could successfully get all information from dt or a negative errno.
1855 */
22698aa2
SG		 1856static int serial_imx_probe_dt(struct imx_port *sport,
1857 struct platform_device *pdev)
1858{
1859 struct device_node *np = pdev->dev.of_node;
1860 const struct of_device_id *of_id =
1861 of_match_device(imx_uart_dt_ids, &pdev->dev);
ff05967a 1862 int ret;
22698aa2
SG		 1863
1864 if (!np)
20bb8095
UKK		 1865 /* no device tree device */
1866 return 1;
22698aa2 1867
ff05967a
SG		 1868 ret = of_alias_get_id(np, "serial");
1869 if (ret < 0) {
1870 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
a197a191 1871 return ret;
ff05967a
SG		 1872 }
1873 sport->port.line = ret;
22698aa2
SG		 1874
1875 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1876 sport->have_rtscts = 1;
1877
1878 if (of_get_property(np, "fsl,irda-mode", NULL))
1879 sport->use_irda = 1;
1880
20ff2fe6
HS		 1881 if (of_get_property(np, "fsl,dte-mode", NULL))
1882 sport->dte_mode = 1;
1883
22698aa2
SG		 1884 sport->devdata = of_id->data;
1885
1886 return 0;
1887}
1888#else
1889static inline int serial_imx_probe_dt(struct imx_port *sport,
1890 struct platform_device *pdev)
1891{
20bb8095 1892 return 1;
22698aa2
SG		 1893}
1894#endif
1895
1896static void serial_imx_probe_pdata(struct imx_port *sport,
1897 struct platform_device *pdev)
1898{
574de559 1899 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
22698aa2
SG		 1900
1901 sport->port.line = pdev->id;
1902 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1903
1904 if (!pdata)
1905 return;
1906
1907 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1908 sport->have_rtscts = 1;
1909
1910 if (pdata->flags & IMXUART_IRDA)
1911 sport->use_irda = 1;
1912}
1913
2582d8c1 1914static int serial_imx_probe(struct platform_device *pdev)
1da177e4 1915{
dbff4e9e 1916 struct imx_port *sport;
dbff4e9e
SH		 1917 void __iomem *base;
1918 int ret = 0;
1919 struct resource *res;
1920
42d34191 1921 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
dbff4e9e
SH		 1922 if (!sport)
1923 return -ENOMEM;
5b802344 1924
22698aa2 1925 ret = serial_imx_probe_dt(sport, pdev);
20bb8095 1926 if (ret > 0)
22698aa2 1927 serial_imx_probe_pdata(sport, pdev);
20bb8095 1928 else if (ret < 0)
42d34191 1929 return ret;
22698aa2 1930
dbff4e9e 1931 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
da82f997
AS		 1932 base = devm_ioremap_resource(&pdev->dev, res);
1933 if (IS_ERR(base))
1934 return PTR_ERR(base);
dbff4e9e
SH		 1935
1936 sport->port.dev = &pdev->dev;
1937 sport->port.mapbase = res->start;
1938 sport->port.membase = base;
1939 sport->port.type = PORT_IMX,
1940 sport->port.iotype = UPIO_MEM;
1941 sport->port.irq = platform_get_irq(pdev, 0);
1942 sport->rxirq = platform_get_irq(pdev, 0);
1943 sport->txirq = platform_get_irq(pdev, 1);
1944 sport->rtsirq = platform_get_irq(pdev, 2);
1945 sport->port.fifosize = 32;
1946 sport->port.ops = &imx_pops;
1947 sport->port.flags = UPF_BOOT_AUTOCONF;
dbff4e9e
SH		 1948 init_timer(&sport->timer);
1949 sport->timer.function = imx_timeout;
1950 sport->timer.data = (unsigned long)sport;
38a41fdf 1951
3a9465fa
SH		 1952 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1953 if (IS_ERR(sport->clk_ipg)) {
1954 ret = PTR_ERR(sport->clk_ipg);
833462e9 1955 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
42d34191 1956 return ret;
38a41fdf 1957 }
38a41fdf 1958
3a9465fa
SH		 1959 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1960 if (IS_ERR(sport->clk_per)) {
1961 ret = PTR_ERR(sport->clk_per);
833462e9 1962 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
42d34191 1963 return ret;
3a9465fa
SH		 1964 }
1965
3a9465fa 1966 sport->port.uartclk = clk_get_rate(sport->clk_per);
dbff4e9e 1967
c0d1c6b0
FE		 1968 /*
1969 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1970 * chips only have one interrupt.
1971 */
1972 if (sport->txirq > 0) {
1973 ret = devm_request_irq(&pdev->dev, sport->rxirq, imx_rxint, 0,
1974 dev_name(&pdev->dev), sport);
1975 if (ret)
1976 return ret;
1977
1978 ret = devm_request_irq(&pdev->dev, sport->txirq, imx_txint, 0,
1979 dev_name(&pdev->dev), sport);
1980 if (ret)
1981 return ret;
1982
1983 /* do not use RTS IRQ on IrDA */
1984 if (!USE_IRDA(sport)) {
1985 ret = devm_request_irq(&pdev->dev, sport->rtsirq,
1986 imx_rtsint, 0,
1987 dev_name(&pdev->dev), sport);
1988 if (ret)
1989 return ret;
1990 }
1991 } else {
1992 ret = devm_request_irq(&pdev->dev, sport->port.irq, imx_int, 0,
1993 dev_name(&pdev->dev), sport);
1994 if (ret)
1995 return ret;
1996 }
1997
22698aa2 1998 imx_ports[sport->port.line] = sport;
5b802344 1999
0a86a86b 2000 platform_set_drvdata(pdev, sport);
5b802344 2001
45af780a 2002 return uart_add_one_port(&imx_reg, &sport->port);
1da177e4
LT		 2003}
2004
2582d8c1 2005static int serial_imx_remove(struct platform_device *pdev)
1da177e4 2006{
2582d8c1 2007 struct imx_port *sport = platform_get_drvdata(pdev);
1da177e4 2008
45af780a 2009 return uart_remove_one_port(&imx_reg, &sport->port);
1da177e4
LT		 2010}
2011
3ae5eaec 2012static struct platform_driver serial_imx_driver = {
d3810cd4
OS		 2013 .probe = serial_imx_probe,
2014 .remove = serial_imx_remove,
1da177e4
LT		 2015
2016 .suspend = serial_imx_suspend,
2017 .resume = serial_imx_resume,
fe6b540a 2018 .id_table = imx_uart_devtype,
3ae5eaec 2019 .driver = {
d3810cd4 2020 .name = "imx-uart",
22698aa2 2021 .of_match_table = imx_uart_dt_ids,
3ae5eaec 2022 },
1da177e4
LT		 2023};
2024
2025static int __init imx_serial_init(void)
2026{
f0fd1b73 2027 int ret = uart_register_driver(&imx_reg);
1da177e4 2028
1da177e4
LT		 2029 if (ret)
2030 return ret;
2031
3ae5eaec 2032 ret = platform_driver_register(&serial_imx_driver);
1da177e4
LT		 2033 if (ret != 0)
2034 uart_unregister_driver(&imx_reg);
2035
f227824e 2036 return ret;
1da177e4
LT		 2037}
2038
2039static void __exit imx_serial_exit(void)
2040{
c889b896 2041 platform_driver_unregister(&serial_imx_driver);
4b300c36 2042 uart_unregister_driver(&imx_reg);
1da177e4
LT		 2043}
2044
2045module_init(imx_serial_init);
2046module_exit(imx_serial_exit);
2047
2048MODULE_AUTHOR("Sascha Hauer");
2049MODULE_DESCRIPTION("IMX generic serial port driver");
2050MODULE_LICENSE("GPL");
e169c139 2051MODULE_ALIAS("platform:imx-uart");
Linux kernel - Deliverables
This page took 1.086989 seconds and 5 git commands to generate.