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serial: imx: always restart DMA if more data is available
[deliverable/linux.git] / drivers / tty / serial / imx.c
CommitLineData
1da177e4 1/*
f890cef2 2 * Driver for Motorola/Freescale IMX serial ports
1da177e4 3 *
f890cef2 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
1da177e4 5 *
f890cef2
UKK		 6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
1da177e4
LT		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
1da177e4 18 */
1da177e4
LT		 19
20#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
23
24#include <linux/module.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
d052d1be 29#include <linux/platform_device.h>
1da177e4
LT		 30#include <linux/tty.h>
31#include <linux/tty_flip.h>
32#include <linux/serial_core.h>
33#include <linux/serial.h>
38a41fdf 34#include <linux/clk.h>
b6e49138 35#include <linux/delay.h>
534fca06 36#include <linux/rational.h>
5a0e3ad6 37#include <linux/slab.h>
22698aa2
SG		 38#include <linux/of.h>
39#include <linux/of_device.h>
e32a9f8f 40#include <linux/io.h>
b4cdc8f6 41#include <linux/dma-mapping.h>
1da177e4 42
1da177e4 43#include <asm/irq.h>
82906b13 44#include <linux/platform_data/serial-imx.h>
b4cdc8f6 45#include <linux/platform_data/dma-imx.h>
1da177e4 46
ff4bfb21
SH		 47/* Register definitions */
48#define URXD0 0x0 /* Receiver Register */
49#define URTX0 0x40 /* Transmitter Register */
50#define UCR1 0x80 /* Control Register 1 */
51#define UCR2 0x84 /* Control Register 2 */
52#define UCR3 0x88 /* Control Register 3 */
53#define UCR4 0x8c /* Control Register 4 */
54#define UFCR 0x90 /* FIFO Control Register */
55#define USR1 0x94 /* Status Register 1 */
56#define USR2 0x98 /* Status Register 2 */
57#define UESC 0x9c /* Escape Character Register */
58#define UTIM 0xa0 /* Escape Timer Register */
59#define UBIR 0xa4 /* BRM Incremental Register */
60#define UBMR 0xa8 /* BRM Modulator Register */
61#define UBRC 0xac /* Baud Rate Count Register */
fe6b540a
SG		 62#define IMX21_ONEMS 0xb0 /* One Millisecond register */
63#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
64#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
ff4bfb21
SH		 65
66/* UART Control Register Bit Fields.*/
55d8693a 67#define URXD_DUMMY_READ (1<<16)
82313e66
SK		 68#define URXD_CHARRDY (1<<15)
69#define URXD_ERR (1<<14)
70#define URXD_OVRRUN (1<<13)
71#define URXD_FRMERR (1<<12)
72#define URXD_BRK (1<<11)
73#define URXD_PRERR (1<<10)
26c47412 74#define URXD_RX_DATA (0xFF<<0)
82313e66
SK		 75#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
76#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
77#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
78#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
b4cdc8f6 79#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
82313e66
SK		 80#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
81#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
82#define UCR1_IREN (1<<7) /* Infrared interface enable */
83#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
84#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
85#define UCR1_SNDBRK (1<<4) /* Send break */
86#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
87#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
b4cdc8f6 88#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
82313e66
SK		 89#define UCR1_DOZE (1<<1) /* Doze */
90#define UCR1_UARTEN (1<<0) /* UART enabled */
91#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
92#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
93#define UCR2_CTSC (1<<13) /* CTS pin control */
94#define UCR2_CTS (1<<12) /* Clear to send */
95#define UCR2_ESCEN (1<<11) /* Escape enable */
96#define UCR2_PREN (1<<8) /* Parity enable */
97#define UCR2_PROE (1<<7) /* Parity odd/even */
98#define UCR2_STPB (1<<6) /* Stop */
99#define UCR2_WS (1<<5) /* Word size */
100#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
101#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
102#define UCR2_TXEN (1<<2) /* Transmitter enabled */
103#define UCR2_RXEN (1<<1) /* Receiver enabled */
104#define UCR2_SRST (1<<0) /* SW reset */
105#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
106#define UCR3_PARERREN (1<<12) /* Parity enable */
107#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
108#define UCR3_DSR (1<<10) /* Data set ready */
109#define UCR3_DCD (1<<9) /* Data carrier detect */
110#define UCR3_RI (1<<8) /* Ring indicator */
b38cb7d2 111#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
82313e66
SK		 112#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
113#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
114#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
115#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
116#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
117#define UCR3_BPEN (1<<0) /* Preset registers enable */
118#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
119#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
120#define UCR4_INVR (1<<9) /* Inverted infrared reception */
121#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
122#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
123#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
b4cdc8f6 124#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
82313e66
SK		 125#define UCR4_IRSC (1<<5) /* IR special case */
126#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
127#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
128#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
129#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
130#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
131#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
132#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
133#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
134#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
135#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
136#define USR1_RTSS (1<<14) /* RTS pin status */
137#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
138#define USR1_RTSD (1<<12) /* RTS delta */
139#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
140#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
141#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
86a04ba6 142#define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
82313e66
SK		 143#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
144#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
145#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
146#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
147#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
148#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
149#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
150#define USR2_IDLE (1<<12) /* Idle condition */
151#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
152#define USR2_WAKE (1<<7) /* Wake */
153#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
154#define USR2_TXDC (1<<3) /* Transmitter complete */
155#define USR2_BRCD (1<<2) /* Break condition */
156#define USR2_ORE (1<<1) /* Overrun error */
157#define USR2_RDR (1<<0) /* Recv data ready */
158#define UTS_FRCPERR (1<<13) /* Force parity error */
159#define UTS_LOOP (1<<12) /* Loop tx and rx */
160#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
161#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
162#define UTS_TXFULL (1<<4) /* TxFIFO full */
163#define UTS_RXFULL (1<<3) /* RxFIFO full */
164#define UTS_SOFTRST (1<<0) /* Software reset */
ff4bfb21 165
1da177e4 166/* We've been assigned a range on the "Low-density serial ports" major */
82313e66
SK		 167#define SERIAL_IMX_MAJOR 207
168#define MINOR_START 16
e3d13ff4 169#define DEV_NAME "ttymxc"
1da177e4 170
1da177e4
LT		 171/*
172 * This determines how often we check the modem status signals
173 * for any change. They generally aren't connected to an IRQ
174 * so we have to poll them. We also check immediately before
175 * filling the TX fifo incase CTS has been dropped.
176 */
177#define MCTRL_TIMEOUT (250*HZ/1000)
178
179#define DRIVER_NAME "IMX-uart"
180
dbff4e9e
SH		 181#define UART_NR 8
182
f95661b2 183/* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
fe6b540a
SG		 184enum imx_uart_type {
185 IMX1_UART,
186 IMX21_UART,
a496e628 187 IMX6Q_UART,
fe6b540a
SG		 188};
189
190/* device type dependent stuff */
191struct imx_uart_data {
192 unsigned uts_reg;
193 enum imx_uart_type devtype;
194};
195
1da177e4
LT		 196struct imx_port {
197 struct uart_port port;
198 struct timer_list timer;
199 unsigned int old_status;
26bbb3ff 200 unsigned int have_rtscts:1;
20ff2fe6 201 unsigned int dte_mode:1;
b6e49138
FG		 202 unsigned int irda_inv_rx:1;
203 unsigned int irda_inv_tx:1;
204 unsigned short trcv_delay; /* transceiver delay */
3a9465fa
SH		 205 struct clk *clk_ipg;
206 struct clk *clk_per;
7d0b066f 207 const struct imx_uart_data *devdata;
b4cdc8f6
HS		 208
209 /* DMA fields */
210 unsigned int dma_is_inited:1;
211 unsigned int dma_is_enabled:1;
212 unsigned int dma_is_rxing:1;
213 unsigned int dma_is_txing:1;
214 struct dma_chan *dma_chan_rx, *dma_chan_tx;
215 struct scatterlist rx_sgl, tx_sgl[2];
216 void *rx_buf;
7cb92fd2 217 unsigned int tx_bytes;
b4cdc8f6 218 unsigned int dma_tx_nents;
9ce4f8f3 219 wait_queue_head_t dma_wait;
90bb6bd3 220 unsigned int saved_reg[10];
c868cbb7 221 bool context_saved;
1da177e4
LT		 222};
223
0ad5a814
DB		 224struct imx_port_ucrs {
225 unsigned int ucr1;
226 unsigned int ucr2;
227 unsigned int ucr3;
228};
229
fe6b540a
SG		 230static struct imx_uart_data imx_uart_devdata[] = {
231 [IMX1_UART] = {
232 .uts_reg = IMX1_UTS,
233 .devtype = IMX1_UART,
234 },
235 [IMX21_UART] = {
236 .uts_reg = IMX21_UTS,
237 .devtype = IMX21_UART,
238 },
a496e628
HS		 239 [IMX6Q_UART] = {
240 .uts_reg = IMX21_UTS,
241 .devtype = IMX6Q_UART,
242 },
fe6b540a
SG		 243};
244
31ada047 245static const struct platform_device_id imx_uart_devtype[] = {
fe6b540a
SG		 246 {
247 .name = "imx1-uart",
248 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
249 }, {
250 .name = "imx21-uart",
251 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
a496e628
HS		 252 }, {
253 .name = "imx6q-uart",
254 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
fe6b540a
SG		 255 }, {
256 /* sentinel */
257 }
258};
259MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
260
ad3d4fdc 261static const struct of_device_id imx_uart_dt_ids[] = {
a496e628 262 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
22698aa2
SG		 263 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
264 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
265 { /* sentinel */ }
266};
267MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
268
fe6b540a
SG		 269static inline unsigned uts_reg(struct imx_port *sport)
270{
271 return sport->devdata->uts_reg;
272}
273
274static inline int is_imx1_uart(struct imx_port *sport)
275{
276 return sport->devdata->devtype == IMX1_UART;
277}
278
279static inline int is_imx21_uart(struct imx_port *sport)
280{
281 return sport->devdata->devtype == IMX21_UART;
282}
283
a496e628
HS		 284static inline int is_imx6q_uart(struct imx_port *sport)
285{
286 return sport->devdata->devtype == IMX6Q_UART;
287}
44a75411 288/*
289 * Save and restore functions for UCR1, UCR2 and UCR3 registers
290 */
93d94b37 291#if defined(CONFIG_SERIAL_IMX_CONSOLE)
44a75411 292static void imx_port_ucrs_save(struct uart_port *port,
293 struct imx_port_ucrs *ucr)
294{
295 /* save control registers */
296 ucr->ucr1 = readl(port->membase + UCR1);
297 ucr->ucr2 = readl(port->membase + UCR2);
298 ucr->ucr3 = readl(port->membase + UCR3);
299}
300
301static void imx_port_ucrs_restore(struct uart_port *port,
302 struct imx_port_ucrs *ucr)
303{
304 /* restore control registers */
305 writel(ucr->ucr1, port->membase + UCR1);
306 writel(ucr->ucr2, port->membase + UCR2);
307 writel(ucr->ucr3, port->membase + UCR3);
308}
e8bfa760 309#endif
44a75411 310
1da177e4
LT		 311/*
312 * Handle any change of modem status signal since we were last called.
313 */
314static void imx_mctrl_check(struct imx_port *sport)
315{
316 unsigned int status, changed;
317
318 status = sport->port.ops->get_mctrl(&sport->port);
319 changed = status ^ sport->old_status;
320
321 if (changed == 0)
322 return;
323
324 sport->old_status = status;
325
326 if (changed & TIOCM_RI)
327 sport->port.icount.rng++;
328 if (changed & TIOCM_DSR)
329 sport->port.icount.dsr++;
330 if (changed & TIOCM_CAR)
331 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
332 if (changed & TIOCM_CTS)
333 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
334
bdc04e31 335 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
1da177e4
LT		 336}
337
338/*
339 * This is our per-port timeout handler, for checking the
340 * modem status signals.
341 */
342static void imx_timeout(unsigned long data)
343{
344 struct imx_port *sport = (struct imx_port *)data;
345 unsigned long flags;
346
ebd2c8f6 347 if (sport->port.state) {
1da177e4
LT		 348 spin_lock_irqsave(&sport->port.lock, flags);
349 imx_mctrl_check(sport);
350 spin_unlock_irqrestore(&sport->port.lock, flags);
351
352 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
353 }
354}
355
356/*
357 * interrupts disabled on entry
358 */
b129a8cc 359static void imx_stop_tx(struct uart_port *port)
1da177e4
LT		 360{
361 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 362 unsigned long temp;
363
9ce4f8f3
GKH		 364 /*
365 * We are maybe in the SMP context, so if the DMA TX thread is running
366 * on other cpu, we have to wait for it to finish.
367 */
368 if (sport->dma_is_enabled && sport->dma_is_txing)
369 return;
b4cdc8f6 370
17b8f2a3
UKK		 371 temp = readl(port->membase + UCR1);
372 writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
373
374 /* in rs485 mode disable transmitter if shifter is empty */
375 if (port->rs485.flags & SER_RS485_ENABLED &&
376 readl(port->membase + USR2) & USR2_TXDC) {
377 temp = readl(port->membase + UCR2);
378 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
379 temp &= ~UCR2_CTS;
380 else
381 temp |= UCR2_CTS;
382 writel(temp, port->membase + UCR2);
383
384 temp = readl(port->membase + UCR4);
385 temp &= ~UCR4_TCEN;
386 writel(temp, port->membase + UCR4);
387 }
1da177e4
LT		 388}
389
390/*
391 * interrupts disabled on entry
392 */
393static void imx_stop_rx(struct uart_port *port)
394{
395 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 396 unsigned long temp;
397
45564a66
HS		 398 if (sport->dma_is_enabled && sport->dma_is_rxing) {
399 if (sport->port.suspended) {
400 dmaengine_terminate_all(sport->dma_chan_rx);
401 sport->dma_is_rxing = 0;
402 } else {
403 return;
404 }
405 }
b4cdc8f6 406
ff4bfb21 407 temp = readl(sport->port.membase + UCR2);
82313e66 408 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
85878399
HS		 409
410 /* disable the `Receiver Ready Interrrupt` */
411 temp = readl(sport->port.membase + UCR1);
412 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
1da177e4
LT		 413}
414
415/*
416 * Set the modem control timer to fire immediately.
417 */
418static void imx_enable_ms(struct uart_port *port)
419{
420 struct imx_port *sport = (struct imx_port *)port;
421
422 mod_timer(&sport->timer, jiffies);
423}
424
91a1a909 425static void imx_dma_tx(struct imx_port *sport);
1da177e4
LT		 426static inline void imx_transmit_buffer(struct imx_port *sport)
427{
ebd2c8f6 428 struct circ_buf *xmit = &sport->port.state->xmit;
91a1a909 429 unsigned long temp;
1da177e4 430
5e42e9a3
PH		 431 if (sport->port.x_char) {
432 /* Send next char */
433 writel(sport->port.x_char, sport->port.membase + URTX0);
7e2fb5aa
JW		 434 sport->port.icount.tx++;
435 sport->port.x_char = 0;
5e42e9a3
PH		 436 return;
437 }
438
439 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
440 imx_stop_tx(&sport->port);
441 return;
442 }
443
91a1a909
JW		 444 if (sport->dma_is_enabled) {
445 /*
446 * We've just sent a X-char Ensure the TX DMA is enabled
447 * and the TX IRQ is disabled.
448 **/
449 temp = readl(sport->port.membase + UCR1);
450 temp &= ~UCR1_TXMPTYEN;
451 if (sport->dma_is_txing) {
452 temp |= UCR1_TDMAEN;
453 writel(temp, sport->port.membase + UCR1);
454 } else {
455 writel(temp, sport->port.membase + UCR1);
456 imx_dma_tx(sport);
457 }
458 }
459
4e4e6602 460 while (!uart_circ_empty(xmit) &&
5e42e9a3 461 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
1da177e4
LT		 462 /* send xmit->buf[xmit->tail]
463 * out the port here */
ff4bfb21 464 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
d3810cd4 465 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1da177e4 466 sport->port.icount.tx++;
8c0b254b 467 }
1da177e4 468
97775731
FG		 469 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
470 uart_write_wakeup(&sport->port);
471
1da177e4 472 if (uart_circ_empty(xmit))
b129a8cc 473 imx_stop_tx(&sport->port);
1da177e4
LT		 474}
475
b4cdc8f6
HS		 476static void dma_tx_callback(void *data)
477{
478 struct imx_port *sport = data;
479 struct scatterlist *sgl = &sport->tx_sgl[0];
480 struct circ_buf *xmit = &sport->port.state->xmit;
481 unsigned long flags;
a2c718ce 482 unsigned long temp;
b4cdc8f6 483
42f752b3 484 spin_lock_irqsave(&sport->port.lock, flags);
b4cdc8f6 485
42f752b3 486 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
b4cdc8f6 487
a2c718ce
DB		 488 temp = readl(sport->port.membase + UCR1);
489 temp &= ~UCR1_TDMAEN;
490 writel(temp, sport->port.membase + UCR1);
491
b4cdc8f6 492 /* update the stat */
b4cdc8f6
HS		 493 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
494 sport->port.icount.tx += sport->tx_bytes;
b4cdc8f6
HS		 495
496 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
497
42f752b3
DB		 498 sport->dma_is_txing = 0;
499
500 spin_unlock_irqrestore(&sport->port.lock, flags);
501
d64b8607
JW		 502 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
503 uart_write_wakeup(&sport->port);
9ce4f8f3
GKH		 504
505 if (waitqueue_active(&sport->dma_wait)) {
506 wake_up(&sport->dma_wait);
507 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
508 return;
509 }
0bbc9b81
JW		 510
511 spin_lock_irqsave(&sport->port.lock, flags);
512 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
513 imx_dma_tx(sport);
514 spin_unlock_irqrestore(&sport->port.lock, flags);
b4cdc8f6
HS		 515}
516
7cb92fd2 517static void imx_dma_tx(struct imx_port *sport)
b4cdc8f6 518{
b4cdc8f6
HS		 519 struct circ_buf *xmit = &sport->port.state->xmit;
520 struct scatterlist *sgl = sport->tx_sgl;
521 struct dma_async_tx_descriptor *desc;
522 struct dma_chan *chan = sport->dma_chan_tx;
523 struct device *dev = sport->port.dev;
a2c718ce 524 unsigned long temp;
b4cdc8f6
HS		 525 int ret;
526
42f752b3 527 if (sport->dma_is_txing)
b4cdc8f6
HS		 528 return;
529
b4cdc8f6 530 sport->tx_bytes = uart_circ_chars_pending(xmit);
b4cdc8f6 531
7942f857
DB		 532 if (xmit->tail < xmit->head) {
533 sport->dma_tx_nents = 1;
534 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
535 } else {
b4cdc8f6
HS		 536 sport->dma_tx_nents = 2;
537 sg_init_table(sgl, 2);
538 sg_set_buf(sgl, xmit->buf + xmit->tail,
539 UART_XMIT_SIZE - xmit->tail);
540 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
b4cdc8f6 541 }
b4cdc8f6
HS		 542
543 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
544 if (ret == 0) {
545 dev_err(dev, "DMA mapping error for TX.\n");
546 return;
547 }
548 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
549 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
550 if (!desc) {
24649821
DB		 551 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
552 DMA_TO_DEVICE);
b4cdc8f6
HS		 553 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
554 return;
555 }
556 desc->callback = dma_tx_callback;
557 desc->callback_param = sport;
558
559 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
560 uart_circ_chars_pending(xmit));
a2c718ce
DB		 561
562 temp = readl(sport->port.membase + UCR1);
563 temp |= UCR1_TDMAEN;
564 writel(temp, sport->port.membase + UCR1);
565
b4cdc8f6
HS		 566 /* fire it */
567 sport->dma_is_txing = 1;
568 dmaengine_submit(desc);
569 dma_async_issue_pending(chan);
570 return;
571}
572
1da177e4
LT		 573/*
574 * interrupts disabled on entry
575 */
b129a8cc 576static void imx_start_tx(struct uart_port *port)
1da177e4
LT		 577{
578 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 579 unsigned long temp;
1da177e4 580
17b8f2a3
UKK		 581 if (port->rs485.flags & SER_RS485_ENABLED) {
582 /* enable transmitter and shifter empty irq */
583 temp = readl(port->membase + UCR2);
584 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
585 temp &= ~UCR2_CTS;
586 else
587 temp |= UCR2_CTS;
588 writel(temp, port->membase + UCR2);
589
590 temp = readl(port->membase + UCR4);
591 temp |= UCR4_TCEN;
592 writel(temp, port->membase + UCR4);
593 }
594
b4cdc8f6
HS		 595 if (!sport->dma_is_enabled) {
596 temp = readl(sport->port.membase + UCR1);
597 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
598 }
1da177e4 599
b4cdc8f6 600 if (sport->dma_is_enabled) {
91a1a909
JW		 601 if (sport->port.x_char) {
602 /* We have X-char to send, so enable TX IRQ and
603 * disable TX DMA to let TX interrupt to send X-char */
604 temp = readl(sport->port.membase + UCR1);
605 temp &= ~UCR1_TDMAEN;
606 temp |= UCR1_TXMPTYEN;
607 writel(temp, sport->port.membase + UCR1);
608 return;
609 }
610
5e42e9a3
PH		 611 if (!uart_circ_empty(&port->state->xmit) &&
612 !uart_tx_stopped(port))
613 imx_dma_tx(sport);
b4cdc8f6
HS		 614 return;
615 }
1da177e4
LT		 616}
617
7d12e780 618static irqreturn_t imx_rtsint(int irq, void *dev_id)
ceca629e 619{
15aafa2f 620 struct imx_port *sport = dev_id;
5680e941 621 unsigned int val;
ceca629e
SH		 622 unsigned long flags;
623
624 spin_lock_irqsave(&sport->port.lock, flags);
625
ff4bfb21 626 writel(USR1_RTSD, sport->port.membase + USR1);
5680e941 627 val = readl(sport->port.membase + USR1) & USR1_RTSS;
ceca629e 628 uart_handle_cts_change(&sport->port, !!val);
bdc04e31 629 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
ceca629e
SH		 630
631 spin_unlock_irqrestore(&sport->port.lock, flags);
632 return IRQ_HANDLED;
633}
634
7d12e780 635static irqreturn_t imx_txint(int irq, void *dev_id)
1da177e4 636{
15aafa2f 637 struct imx_port *sport = dev_id;
1da177e4
LT		 638 unsigned long flags;
639
82313e66 640 spin_lock_irqsave(&sport->port.lock, flags);
1da177e4 641 imx_transmit_buffer(sport);
82313e66 642 spin_unlock_irqrestore(&sport->port.lock, flags);
1da177e4
LT		 643 return IRQ_HANDLED;
644}
645
7d12e780 646static irqreturn_t imx_rxint(int irq, void *dev_id)
1da177e4
LT		 647{
648 struct imx_port *sport = dev_id;
82313e66 649 unsigned int rx, flg, ignored = 0;
92a19f9c 650 struct tty_port *port = &sport->port.state->port;
ff4bfb21 651 unsigned long flags, temp;
1da177e4 652
82313e66 653 spin_lock_irqsave(&sport->port.lock, flags);
1da177e4 654
0d3c3938 655 while (readl(sport->port.membase + USR2) & USR2_RDR) {
1da177e4
LT		 656 flg = TTY_NORMAL;
657 sport->port.icount.rx++;
658
0d3c3938
SH		 659 rx = readl(sport->port.membase + URXD0);
660
ff4bfb21 661 temp = readl(sport->port.membase + USR2);
864eeed0 662 if (temp & USR2_BRCD) {
94d32f99 663 writel(USR2_BRCD, sport->port.membase + USR2);
864eeed0
SH		 664 if (uart_handle_break(&sport->port))
665 continue;
1da177e4
LT		 666 }
667
d3810cd4 668 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
864eeed0
SH		 669 continue;
670
019dc9ea
HW		 671 if (unlikely(rx & URXD_ERR)) {
672 if (rx & URXD_BRK)
673 sport->port.icount.brk++;
674 else if (rx & URXD_PRERR)
864eeed0
SH		 675 sport->port.icount.parity++;
676 else if (rx & URXD_FRMERR)
677 sport->port.icount.frame++;
678 if (rx & URXD_OVRRUN)
679 sport->port.icount.overrun++;
680
681 if (rx & sport->port.ignore_status_mask) {
682 if (++ignored > 100)
683 goto out;
684 continue;
685 }
686
8d267fd9 687 rx &= (sport->port.read_status_mask | 0xFF);
864eeed0 688
019dc9ea
HW		 689 if (rx & URXD_BRK)
690 flg = TTY_BREAK;
691 else if (rx & URXD_PRERR)
864eeed0
SH		 692 flg = TTY_PARITY;
693 else if (rx & URXD_FRMERR)
694 flg = TTY_FRAME;
695 if (rx & URXD_OVRRUN)
696 flg = TTY_OVERRUN;
1da177e4 697
864eeed0
SH		 698#ifdef SUPPORT_SYSRQ
699 sport->port.sysrq = 0;
700#endif
701 }
1da177e4 702
55d8693a
JW		 703 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
704 goto out;
705
9b289932
MS		 706 if (tty_insert_flip_char(port, rx, flg) == 0)
707 sport->port.icount.buf_overrun++;
864eeed0 708 }
1da177e4
LT		 709
710out:
82313e66 711 spin_unlock_irqrestore(&sport->port.lock, flags);
2e124b4a 712 tty_flip_buffer_push(port);
1da177e4 713 return IRQ_HANDLED;
1da177e4
LT		 714}
715
7cb92fd2 716static int start_rx_dma(struct imx_port *sport);
b4cdc8f6
HS		 717/*
718 * If the RXFIFO is filled with some data, and then we
719 * arise a DMA operation to receive them.
720 */
721static void imx_dma_rxint(struct imx_port *sport)
722{
723 unsigned long temp;
73631813
JW		 724 unsigned long flags;
725
726 spin_lock_irqsave(&sport->port.lock, flags);
b4cdc8f6
HS		 727
728 temp = readl(sport->port.membase + USR2);
729 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
730 sport->dma_is_rxing = 1;
731
86a04ba6 732 /* disable the receiver ready and aging timer interrupts */
b4cdc8f6
HS		 733 temp = readl(sport->port.membase + UCR1);
734 temp &= ~(UCR1_RRDYEN);
735 writel(temp, sport->port.membase + UCR1);
736
86a04ba6
LS		 737 temp = readl(sport->port.membase + UCR2);
738 temp &= ~(UCR2_ATEN);
739 writel(temp, sport->port.membase + UCR2);
740
b4cdc8f6 741 /* tell the DMA to receive the data. */
7cb92fd2 742 start_rx_dma(sport);
b4cdc8f6 743 }
73631813
JW		 744
745 spin_unlock_irqrestore(&sport->port.lock, flags);
b4cdc8f6
HS		 746}
747
e3d13ff4
SH		 748static irqreturn_t imx_int(int irq, void *dev_id)
749{
750 struct imx_port *sport = dev_id;
751 unsigned int sts;
f1f836e4 752 unsigned int sts2;
e3d13ff4
SH		 753
754 sts = readl(sport->port.membase + USR1);
17b8f2a3 755 sts2 = readl(sport->port.membase + USR2);
e3d13ff4 756
86a04ba6 757 if (sts & (USR1_RRDY | USR1_AGTIM)) {
b4cdc8f6
HS		 758 if (sport->dma_is_enabled)
759 imx_dma_rxint(sport);
760 else
761 imx_rxint(irq, dev_id);
762 }
e3d13ff4 763
17b8f2a3
UKK		 764 if ((sts & USR1_TRDY &&
765 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
766 (sts2 & USR2_TXDC &&
767 readl(sport->port.membase + UCR4) & UCR4_TCEN))
e3d13ff4
SH		 768 imx_txint(irq, dev_id);
769
9fbe6044 770 if (sts & USR1_RTSD)
e3d13ff4
SH		 771 imx_rtsint(irq, dev_id);
772
db1a9b55
FE		 773 if (sts & USR1_AWAKE)
774 writel(USR1_AWAKE, sport->port.membase + USR1);
775
f1f836e4 776 if (sts2 & USR2_ORE) {
f1f836e4 777 sport->port.icount.overrun++;
91555ce9 778 writel(USR2_ORE, sport->port.membase + USR2);
f1f836e4
AS		 779 }
780
e3d13ff4
SH		 781 return IRQ_HANDLED;
782}
783
1da177e4
LT		 784/*
785 * Return TIOCSER_TEMT when transmitter is not busy.
786 */
787static unsigned int imx_tx_empty(struct uart_port *port)
788{
789 struct imx_port *sport = (struct imx_port *)port;
1ce43e58 790 unsigned int ret;
1da177e4 791
1ce43e58 792 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1da177e4 793
1ce43e58
HS		 794 /* If the TX DMA is working, return 0. */
795 if (sport->dma_is_enabled && sport->dma_is_txing)
796 ret = 0;
797
798 return ret;
1da177e4
LT		 799}
800
0f302dc3
SH		 801/*
802 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
803 */
1da177e4
LT		 804static unsigned int imx_get_mctrl(struct uart_port *port)
805{
d3810cd4
OS		 806 struct imx_port *sport = (struct imx_port *)port;
807 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
0f302dc3 808
d3810cd4
OS		 809 if (readl(sport->port.membase + USR1) & USR1_RTSS)
810 tmp |= TIOCM_CTS;
0f302dc3 811
d3810cd4
OS		 812 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
813 tmp |= TIOCM_RTS;
0f302dc3 814
6b471a98
HS		 815 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
816 tmp |= TIOCM_LOOP;
817
d3810cd4 818 return tmp;
1da177e4
LT		 819}
820
821static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
822{
d3810cd4 823 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 824 unsigned long temp;
825
17b8f2a3
UKK		 826 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
827 temp = readl(sport->port.membase + UCR2);
828 temp &= ~(UCR2_CTS | UCR2_CTSC);
829 if (mctrl & TIOCM_RTS)
830 temp |= UCR2_CTS | UCR2_CTSC;
831 writel(temp, sport->port.membase + UCR2);
832 }
6b471a98
HS		 833
834 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
835 if (mctrl & TIOCM_LOOP)
836 temp |= UTS_LOOP;
837 writel(temp, sport->port.membase + uts_reg(sport));
1da177e4
LT		 838}
839
840/*
841 * Interrupts always disabled.
842 */
843static void imx_break_ctl(struct uart_port *port, int break_state)
844{
845 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 846 unsigned long flags, temp;
1da177e4
LT		 847
848 spin_lock_irqsave(&sport->port.lock, flags);
849
ff4bfb21
SH		 850 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
851
82313e66 852 if (break_state != 0)
ff4bfb21
SH		 853 temp |= UCR1_SNDBRK;
854
855 writel(temp, sport->port.membase + UCR1);
1da177e4
LT		 856
857 spin_unlock_irqrestore(&sport->port.lock, flags);
858}
859
b4cdc8f6 860#define RX_BUF_SIZE (PAGE_SIZE)
b4cdc8f6
HS		 861static void imx_rx_dma_done(struct imx_port *sport)
862{
863 unsigned long temp;
73631813
JW		 864 unsigned long flags;
865
866 spin_lock_irqsave(&sport->port.lock, flags);
b4cdc8f6 867
86a04ba6 868 /* re-enable interrupts to get notified when new symbols are incoming */
b4cdc8f6
HS		 869 temp = readl(sport->port.membase + UCR1);
870 temp |= UCR1_RRDYEN;
871 writel(temp, sport->port.membase + UCR1);
872
86a04ba6
LS		 873 temp = readl(sport->port.membase + UCR2);
874 temp |= UCR2_ATEN;
875 writel(temp, sport->port.membase + UCR2);
876
b4cdc8f6 877 sport->dma_is_rxing = 0;
9ce4f8f3
GKH		 878
879 /* Is the shutdown waiting for us? */
880 if (waitqueue_active(&sport->dma_wait))
881 wake_up(&sport->dma_wait);
73631813
JW		 882
883 spin_unlock_irqrestore(&sport->port.lock, flags);
b4cdc8f6
HS		 884}
885
886/*
887 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
888 * [1] the RX DMA buffer is full.
889 * [2] the Aging timer expires(wait for 8 bytes long)
890 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
891 *
892 * The [2] is trigger when a character was been sitting in the FIFO
893 * meanwhile [3] can wait for 32 bytes long when the RX line is
894 * on IDLE state and RxFIFO is empty.
895 */
896static void dma_rx_callback(void *data)
897{
898 struct imx_port *sport = data;
899 struct dma_chan *chan = sport->dma_chan_rx;
900 struct scatterlist *sgl = &sport->rx_sgl;
7cb92fd2 901 struct tty_port *port = &sport->port.state->port;
b4cdc8f6
HS		 902 struct dma_tx_state state;
903 enum dma_status status;
904 unsigned int count;
905
906 /* unmap it first */
907 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
908
f0ef8834 909 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
b4cdc8f6 910 count = RX_BUF_SIZE - state.residue;
392bceed
PZ		 911
912 if (readl(sport->port.membase + USR2) & USR2_IDLE) {
913 /* In condition [3] the SDMA counted up too early */
914 count--;
915
916 writel(USR2_IDLE, sport->port.membase + USR2);
917 }
918
b4cdc8f6
HS		 919 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
920
921 if (count) {
9b289932
MS		 922 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
923 int bytes = tty_insert_flip_string(port, sport->rx_buf,
924 count);
925
926 if (bytes != count)
927 sport->port.icount.buf_overrun++;
928 }
7cb92fd2 929 tty_flip_buffer_push(port);
976b39cd 930 }
7cb92fd2 931
976b39cd
LS		 932 /*
933 * Restart RX DMA directly if more data is available in order to skip
934 * the roundtrip through the IRQ handler. If there is some data already
935 * in the FIFO, DMA needs to be restarted soon anyways.
936 *
937 * Otherwise stop the DMA and reactivate FIFO IRQs to restart DMA once
938 * data starts to arrive again.
939 */
940 if (readl(sport->port.membase + USR2) & USR2_RDR)
7cb92fd2 941 start_rx_dma(sport);
976b39cd 942 else
b4cdc8f6
HS		 943 imx_rx_dma_done(sport);
944}
945
946static int start_rx_dma(struct imx_port *sport)
947{
948 struct scatterlist *sgl = &sport->rx_sgl;
949 struct dma_chan *chan = sport->dma_chan_rx;
950 struct device *dev = sport->port.dev;
951 struct dma_async_tx_descriptor *desc;
952 int ret;
953
954 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
955 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
956 if (ret == 0) {
957 dev_err(dev, "DMA mapping error for RX.\n");
958 return -EINVAL;
959 }
960 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
961 DMA_PREP_INTERRUPT);
962 if (!desc) {
24649821 963 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
b4cdc8f6
HS		 964 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
965 return -EINVAL;
966 }
967 desc->callback = dma_rx_callback;
968 desc->callback_param = sport;
969
970 dev_dbg(dev, "RX: prepare for the DMA.\n");
971 dmaengine_submit(desc);
972 dma_async_issue_pending(chan);
973 return 0;
974}
975
cc32382d
LS		 976#define TXTL_DEFAULT 2 /* reset default */
977#define RXTL_DEFAULT 1 /* reset default */
978
979static void imx_setup_ufcr(struct imx_port *sport,
980 unsigned char txwl, unsigned char rxwl)
981{
982 unsigned int val;
983
984 /* set receiver / transmitter trigger level */
985 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
986 val |= txwl << UFCR_TXTL_SHF | rxwl;
987 writel(val, sport->port.membase + UFCR);
988}
989
b4cdc8f6
HS		 990static void imx_uart_dma_exit(struct imx_port *sport)
991{
992 if (sport->dma_chan_rx) {
993 dma_release_channel(sport->dma_chan_rx);
994 sport->dma_chan_rx = NULL;
995
996 kfree(sport->rx_buf);
997 sport->rx_buf = NULL;
998 }
999
1000 if (sport->dma_chan_tx) {
1001 dma_release_channel(sport->dma_chan_tx);
1002 sport->dma_chan_tx = NULL;
1003 }
1004
1005 sport->dma_is_inited = 0;
1006}
1007
1008static int imx_uart_dma_init(struct imx_port *sport)
1009{
b09c74ae 1010 struct dma_slave_config slave_config = {};
b4cdc8f6
HS		 1011 struct device *dev = sport->port.dev;
1012 int ret;
1013
1014 /* Prepare for RX : */
1015 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1016 if (!sport->dma_chan_rx) {
1017 dev_dbg(dev, "cannot get the DMA channel.\n");
1018 ret = -EINVAL;
1019 goto err;
1020 }
1021
1022 slave_config.direction = DMA_DEV_TO_MEM;
1023 slave_config.src_addr = sport->port.mapbase + URXD0;
1024 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
cc32382d 1025 slave_config.src_maxburst = RXTL_DEFAULT;
b4cdc8f6
HS		 1026 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1027 if (ret) {
1028 dev_err(dev, "error in RX dma configuration.\n");
1029 goto err;
1030 }
1031
1032 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1033 if (!sport->rx_buf) {
b4cdc8f6
HS		 1034 ret = -ENOMEM;
1035 goto err;
1036 }
b4cdc8f6
HS		 1037
1038 /* Prepare for TX : */
1039 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1040 if (!sport->dma_chan_tx) {
1041 dev_err(dev, "cannot get the TX DMA channel!\n");
1042 ret = -EINVAL;
1043 goto err;
1044 }
1045
1046 slave_config.direction = DMA_MEM_TO_DEV;
1047 slave_config.dst_addr = sport->port.mapbase + URTX0;
1048 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
cc32382d 1049 slave_config.dst_maxburst = TXTL_DEFAULT;
b4cdc8f6
HS		 1050 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1051 if (ret) {
1052 dev_err(dev, "error in TX dma configuration.");
1053 goto err;
1054 }
1055
1056 sport->dma_is_inited = 1;
1057
1058 return 0;
1059err:
1060 imx_uart_dma_exit(sport);
1061 return ret;
1062}
1063
1064static void imx_enable_dma(struct imx_port *sport)
1065{
1066 unsigned long temp;
b4cdc8f6 1067
9ce4f8f3
GKH		 1068 init_waitqueue_head(&sport->dma_wait);
1069
b4cdc8f6
HS		 1070 /* set UCR1 */
1071 temp = readl(sport->port.membase + UCR1);
1072 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1073 /* wait for 32 idle frames for IDDMA interrupt */
1074 UCR1_ICD_REG(3);
1075 writel(temp, sport->port.membase + UCR1);
1076
86a04ba6
LS		 1077 temp = readl(sport->port.membase + UCR2);
1078 temp |= UCR2_ATEN;
1079 writel(temp, sport->port.membase + UCR2);
1080
b4cdc8f6
HS		 1081 /* set UCR4 */
1082 temp = readl(sport->port.membase + UCR4);
1083 temp |= UCR4_IDDMAEN;
1084 writel(temp, sport->port.membase + UCR4);
1085
1086 sport->dma_is_enabled = 1;
1087}
1088
1089static void imx_disable_dma(struct imx_port *sport)
1090{
1091 unsigned long temp;
b4cdc8f6
HS		 1092
1093 /* clear UCR1 */
1094 temp = readl(sport->port.membase + UCR1);
1095 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1096 writel(temp, sport->port.membase + UCR1);
1097
1098 /* clear UCR2 */
1099 temp = readl(sport->port.membase + UCR2);
86a04ba6 1100 temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN);
b4cdc8f6
HS		 1101 writel(temp, sport->port.membase + UCR2);
1102
1103 /* clear UCR4 */
1104 temp = readl(sport->port.membase + UCR4);
1105 temp &= ~UCR4_IDDMAEN;
1106 writel(temp, sport->port.membase + UCR4);
1107
1108 sport->dma_is_enabled = 0;
b4cdc8f6
HS		 1109}
1110
1c5250d6
VL		 1111/* half the RX buffer size */
1112#define CTSTL 16
1113
1da177e4
LT		 1114static int imx_startup(struct uart_port *port)
1115{
1116 struct imx_port *sport = (struct imx_port *)port;
458e2c82 1117 int retval, i;
ff4bfb21 1118 unsigned long flags, temp;
1da177e4 1119
1cf93e0d
HS		 1120 retval = clk_prepare_enable(sport->clk_per);
1121 if (retval)
cb0f0a5f 1122 return retval;
1cf93e0d
HS		 1123 retval = clk_prepare_enable(sport->clk_ipg);
1124 if (retval) {
1125 clk_disable_unprepare(sport->clk_per);
cb0f0a5f 1126 return retval;
0c375501 1127 }
28eb4274 1128
cc32382d 1129 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1da177e4
LT		 1130
1131 /* disable the DREN bit (Data Ready interrupt enable) before
1132 * requesting IRQs
1133 */
ff4bfb21 1134 temp = readl(sport->port.membase + UCR4);
b6e49138 1135
1c5250d6 1136 /* set the trigger level for CTS */
82313e66
SK		 1137 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1138 temp |= CTSTL << UCR4_CTSTL_SHF;
1c5250d6 1139
ff4bfb21 1140 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1da177e4 1141
53794183 1142 spin_lock_irqsave(&sport->port.lock, flags);
772f8991 1143 /* Reset fifo's and state machines */
458e2c82
FE		 1144 i = 100;
1145
1146 temp = readl(sport->port.membase + UCR2);
1147 temp &= ~UCR2_SRST;
1148 writel(temp, sport->port.membase + UCR2);
1149
1150 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1151 udelay(1);
b6e49138 1152
1da177e4
LT		 1153 /*
1154 * Finally, clear and enable interrupts
1155 */
ff4bfb21 1156 writel(USR1_RTSD, sport->port.membase + USR1);
91555ce9 1157 writel(USR2_ORE, sport->port.membase + USR2);
ff4bfb21
SH		 1158
1159 temp = readl(sport->port.membase + UCR1);
789d5258 1160 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
b6e49138 1161
ff4bfb21 1162 writel(temp, sport->port.membase + UCR1);
1da177e4 1163
6f026d6b
JW		 1164 temp = readl(sport->port.membase + UCR4);
1165 temp |= UCR4_OREN;
1166 writel(temp, sport->port.membase + UCR4);
1167
ff4bfb21
SH		 1168 temp = readl(sport->port.membase + UCR2);
1169 temp |= (UCR2_RXEN | UCR2_TXEN);
bff09b09
LS		 1170 if (!sport->have_rtscts)
1171 temp |= UCR2_IRTS;
ff4bfb21 1172 writel(temp, sport->port.membase + UCR2);
1da177e4 1173
a496e628 1174 if (!is_imx1_uart(sport)) {
37d6fb62 1175 temp = readl(sport->port.membase + UCR3);
b38cb7d2 1176 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
37d6fb62
SH		 1177 writel(temp, sport->port.membase + UCR3);
1178 }
4411805b 1179
1da177e4
LT		 1180 /*
1181 * Enable modem status interrupts
1182 */
1da177e4 1183 imx_enable_ms(&sport->port);
82313e66 1184 spin_unlock_irqrestore(&sport->port.lock, flags);
1da177e4
LT		 1185
1186 return 0;
1da177e4
LT		 1187}
1188
1189static void imx_shutdown(struct uart_port *port)
1190{
1191 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 1192 unsigned long temp;
9ec1882d 1193 unsigned long flags;
1da177e4 1194
b4cdc8f6 1195 if (sport->dma_is_enabled) {
a4688bcd
HS		 1196 int ret;
1197
9ce4f8f3 1198 /* We have to wait for the DMA to finish. */
a4688bcd 1199 ret = wait_event_interruptible(sport->dma_wait,
9ce4f8f3 1200 !sport->dma_is_rxing && !sport->dma_is_txing);
a4688bcd
HS		 1201 if (ret != 0) {
1202 sport->dma_is_rxing = 0;
1203 sport->dma_is_txing = 0;
1204 dmaengine_terminate_all(sport->dma_chan_tx);
1205 dmaengine_terminate_all(sport->dma_chan_rx);
1206 }
73631813 1207 spin_lock_irqsave(&sport->port.lock, flags);
a4688bcd 1208 imx_stop_tx(port);
b4cdc8f6
HS		 1209 imx_stop_rx(port);
1210 imx_disable_dma(sport);
73631813 1211 spin_unlock_irqrestore(&sport->port.lock, flags);
b4cdc8f6
HS		 1212 imx_uart_dma_exit(sport);
1213 }
1214
9ec1882d 1215 spin_lock_irqsave(&sport->port.lock, flags);
2e146392
FG		 1216 temp = readl(sport->port.membase + UCR2);
1217 temp &= ~(UCR2_TXEN);
1218 writel(temp, sport->port.membase + UCR2);
9ec1882d 1219 spin_unlock_irqrestore(&sport->port.lock, flags);
2e146392 1220
1da177e4
LT		 1221 /*
1222 * Stop our timer.
1223 */
1224 del_timer_sync(&sport->timer);
1225
1da177e4
LT		 1226 /*
1227 * Disable all interrupts, port and break condition.
1228 */
1229
9ec1882d 1230 spin_lock_irqsave(&sport->port.lock, flags);
ff4bfb21
SH		 1231 temp = readl(sport->port.membase + UCR1);
1232 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
b6e49138 1233
ff4bfb21 1234 writel(temp, sport->port.membase + UCR1);
9ec1882d 1235 spin_unlock_irqrestore(&sport->port.lock, flags);
28eb4274 1236
1cf93e0d
HS		 1237 clk_disable_unprepare(sport->clk_per);
1238 clk_disable_unprepare(sport->clk_ipg);
1da177e4
LT		 1239}
1240
eb56b7ed
HS		 1241static void imx_flush_buffer(struct uart_port *port)
1242{
1243 struct imx_port *sport = (struct imx_port *)port;
82e86ae9 1244 struct scatterlist *sgl = &sport->tx_sgl[0];
a2c718ce 1245 unsigned long temp;
4f86a95d 1246 int i = 100, ubir, ubmr, uts;
eb56b7ed 1247
82e86ae9
DB		 1248 if (!sport->dma_chan_tx)
1249 return;
1250
1251 sport->tx_bytes = 0;
1252 dmaengine_terminate_all(sport->dma_chan_tx);
1253 if (sport->dma_is_txing) {
1254 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1255 DMA_TO_DEVICE);
a2c718ce
DB		 1256 temp = readl(sport->port.membase + UCR1);
1257 temp &= ~UCR1_TDMAEN;
1258 writel(temp, sport->port.membase + UCR1);
82e86ae9 1259 sport->dma_is_txing = false;
eb56b7ed 1260 }
934084a9
FE		 1261
1262 /*
1263 * According to the Reference Manual description of the UART SRST bit:
1264 * "Reset the transmit and receive state machines,
1265 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1266 * and UTS[6-3]". As we don't need to restore the old values from
1267 * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1268 */
1269 ubir = readl(sport->port.membase + UBIR);
1270 ubmr = readl(sport->port.membase + UBMR);
934084a9
FE		 1271 uts = readl(sport->port.membase + IMX21_UTS);
1272
1273 temp = readl(sport->port.membase + UCR2);
1274 temp &= ~UCR2_SRST;
1275 writel(temp, sport->port.membase + UCR2);
1276
1277 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1278 udelay(1);
1279
1280 /* Restore the registers */
1281 writel(ubir, sport->port.membase + UBIR);
1282 writel(ubmr, sport->port.membase + UBMR);
934084a9 1283 writel(uts, sport->port.membase + IMX21_UTS);
eb56b7ed
HS		 1284}
1285
1da177e4 1286static void
606d099c
AC		 1287imx_set_termios(struct uart_port *port, struct ktermios *termios,
1288 struct ktermios *old)
1da177e4
LT		 1289{
1290 struct imx_port *sport = (struct imx_port *)port;
1291 unsigned long flags;
86a04ba6 1292 unsigned int ucr2, old_ucr1, old_ucr2, baud, quot;
1da177e4 1293 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
534fca06
OS		 1294 unsigned int div, ufcr;
1295 unsigned long num, denom;
d7f8d437 1296 uint64_t tdiv64;
1da177e4 1297
1da177e4
LT		 1298 /*
1299 * We only support CS7 and CS8.
1300 */
1301 while ((termios->c_cflag & CSIZE) != CS7 &&
1302 (termios->c_cflag & CSIZE) != CS8) {
1303 termios->c_cflag &= ~CSIZE;
1304 termios->c_cflag |= old_csize;
1305 old_csize = CS8;
1306 }
1307
1308 if ((termios->c_cflag & CSIZE) == CS8)
1309 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1310 else
1311 ucr2 = UCR2_SRST | UCR2_IRTS;
1312
1313 if (termios->c_cflag & CRTSCTS) {
82313e66 1314 if (sport->have_rtscts) {
5b802344 1315 ucr2 &= ~UCR2_IRTS;
17b8f2a3 1316
12fe59f9 1317 if (port->rs485.flags & SER_RS485_ENABLED) {
17b8f2a3
UKK		 1318 /*
1319 * RTS is mandatory for rs485 operation, so keep
1320 * it under manual control and keep transmitter
1321 * disabled.
1322 */
1323 if (!(port->rs485.flags &
1324 SER_RS485_RTS_AFTER_SEND))
1325 ucr2 |= UCR2_CTS;
12fe59f9 1326 } else {
17b8f2a3 1327 ucr2 |= UCR2_CTSC;
12fe59f9 1328 }
907eda32
DJ		 1329
1330 /* Can we enable the DMA support? */
1331 if (is_imx6q_uart(sport) && !uart_console(port)
1332 && !sport->dma_is_inited)
1333 imx_uart_dma_init(sport);
5b802344
SH		 1334 } else {
1335 termios->c_cflag &= ~CRTSCTS;
1336 }
17b8f2a3
UKK		 1337 } else if (port->rs485.flags & SER_RS485_ENABLED)
1338 /* disable transmitter */
1339 if (!(port->rs485.flags & SER_RS485_RTS_AFTER_SEND))
1340 ucr2 |= UCR2_CTS;
1da177e4
LT		 1341
1342 if (termios->c_cflag & CSTOPB)
1343 ucr2 |= UCR2_STPB;
1344 if (termios->c_cflag & PARENB) {
1345 ucr2 |= UCR2_PREN;
3261e362 1346 if (termios->c_cflag & PARODD)
1da177e4
LT		 1347 ucr2 |= UCR2_PROE;
1348 }
1349
995234da
EM		 1350 del_timer_sync(&sport->timer);
1351
1da177e4
LT		 1352 /*
1353 * Ask the core to calculate the divisor for us.
1354 */
036bb15e 1355 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1da177e4
LT		 1356 quot = uart_get_divisor(port, baud);
1357
1358 spin_lock_irqsave(&sport->port.lock, flags);
1359
1360 sport->port.read_status_mask = 0;
1361 if (termios->c_iflag & INPCK)
1362 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1363 if (termios->c_iflag & (BRKINT | PARMRK))
1364 sport->port.read_status_mask |= URXD_BRK;
1365
1366 /*
1367 * Characters to ignore
1368 */
1369 sport->port.ignore_status_mask = 0;
1370 if (termios->c_iflag & IGNPAR)
865cea85 1371 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1da177e4
LT		 1372 if (termios->c_iflag & IGNBRK) {
1373 sport->port.ignore_status_mask |= URXD_BRK;
1374 /*
1375 * If we're ignoring parity and break indicators,
1376 * ignore overruns too (for real raw support).
1377 */
1378 if (termios->c_iflag & IGNPAR)
1379 sport->port.ignore_status_mask |= URXD_OVRRUN;
1380 }
1381
55d8693a
JW		 1382 if ((termios->c_cflag & CREAD) == 0)
1383 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1384
1da177e4
LT		 1385 /*
1386 * Update the per-port timeout.
1387 */
1388 uart_update_timeout(port, termios->c_cflag, baud);
1389
1390 /*
1391 * disable interrupts and drain transmitter
1392 */
ff4bfb21
SH		 1393 old_ucr1 = readl(sport->port.membase + UCR1);
1394 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1395 sport->port.membase + UCR1);
1da177e4 1396
82313e66 1397 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1da177e4
LT		 1398 barrier();
1399
1400 /* then, disable everything */
86a04ba6
LS		 1401 old_ucr2 = readl(sport->port.membase + UCR2);
1402 writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN),
ff4bfb21 1403 sport->port.membase + UCR2);
86a04ba6 1404 old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
1da177e4 1405
afe9cbb1
UKK		 1406 /* custom-baudrate handling */
1407 div = sport->port.uartclk / (baud * 16);
1408 if (baud == 38400 && quot != div)
1409 baud = sport->port.uartclk / (quot * 16);
1410
1411 div = sport->port.uartclk / (baud * 16);
1412 if (div > 7)
1413 div = 7;
1414 if (!div)
036bb15e
SH		 1415 div = 1;
1416
534fca06
OS		 1417 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1418 1 << 16, 1 << 16, &num, &denom);
036bb15e 1419
eab4f5af
AC		 1420 tdiv64 = sport->port.uartclk;
1421 tdiv64 *= num;
1422 do_div(tdiv64, denom * 16 * div);
1423 tty_termios_encode_baud_rate(termios,
1a2c4b31 1424 (speed_t)tdiv64, (speed_t)tdiv64);
d7f8d437 1425
534fca06
OS		 1426 num -= 1;
1427 denom -= 1;
036bb15e
SH		 1428
1429 ufcr = readl(sport->port.membase + UFCR);
b6e49138 1430 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
20ff2fe6
HS		 1431 if (sport->dte_mode)
1432 ufcr |= UFCR_DCEDTE;
036bb15e
SH		 1433 writel(ufcr, sport->port.membase + UFCR);
1434
534fca06
OS		 1435 writel(num, sport->port.membase + UBIR);
1436 writel(denom, sport->port.membase + UBMR);
1437
a496e628 1438 if (!is_imx1_uart(sport))
37d6fb62 1439 writel(sport->port.uartclk / div / 1000,
fe6b540a 1440 sport->port.membase + IMX21_ONEMS);
ff4bfb21
SH		 1441
1442 writel(old_ucr1, sport->port.membase + UCR1);
1da177e4 1443
ff4bfb21 1444 /* set the parity, stop bits and data size */
86a04ba6 1445 writel(ucr2 | old_ucr2, sport->port.membase + UCR2);
1da177e4
LT		 1446
1447 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1448 imx_enable_ms(&sport->port);
1449
907eda32
DJ		 1450 if (sport->dma_is_inited && !sport->dma_is_enabled)
1451 imx_enable_dma(sport);
1da177e4
LT		 1452 spin_unlock_irqrestore(&sport->port.lock, flags);
1453}
1454
1455static const char *imx_type(struct uart_port *port)
1456{
1457 struct imx_port *sport = (struct imx_port *)port;
1458
1459 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1460}
1461
1da177e4
LT		 1462/*
1463 * Configure/autoconfigure the port.
1464 */
1465static void imx_config_port(struct uart_port *port, int flags)
1466{
1467 struct imx_port *sport = (struct imx_port *)port;
1468
da82f997 1469 if (flags & UART_CONFIG_TYPE)
1da177e4
LT		 1470 sport->port.type = PORT_IMX;
1471}
1472
1473/*
1474 * Verify the new serial_struct (for TIOCSSERIAL).
1475 * The only change we allow are to the flags and type, and
1476 * even then only between PORT_IMX and PORT_UNKNOWN
1477 */
1478static int
1479imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1480{
1481 struct imx_port *sport = (struct imx_port *)port;
1482 int ret = 0;
1483
1484 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1485 ret = -EINVAL;
1486 if (sport->port.irq != ser->irq)
1487 ret = -EINVAL;
1488 if (ser->io_type != UPIO_MEM)
1489 ret = -EINVAL;
1490 if (sport->port.uartclk / 16 != ser->baud_base)
1491 ret = -EINVAL;
a50c44ce 1492 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1da177e4
LT		 1493 ret = -EINVAL;
1494 if (sport->port.iobase != ser->port)
1495 ret = -EINVAL;
1496 if (ser->hub6 != 0)
1497 ret = -EINVAL;
1498 return ret;
1499}
1500
01f56abd 1501#if defined(CONFIG_CONSOLE_POLL)
6b8bdad9
DT		 1502
1503static int imx_poll_init(struct uart_port *port)
1504{
1505 struct imx_port *sport = (struct imx_port *)port;
1506 unsigned long flags;
1507 unsigned long temp;
1508 int retval;
1509
1510 retval = clk_prepare_enable(sport->clk_ipg);
1511 if (retval)
1512 return retval;
1513 retval = clk_prepare_enable(sport->clk_per);
1514 if (retval)
1515 clk_disable_unprepare(sport->clk_ipg);
1516
cc32382d 1517 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
6b8bdad9
DT		 1518
1519 spin_lock_irqsave(&sport->port.lock, flags);
1520
1521 temp = readl(sport->port.membase + UCR1);
1522 if (is_imx1_uart(sport))
1523 temp |= IMX1_UCR1_UARTCLKEN;
1524 temp |= UCR1_UARTEN | UCR1_RRDYEN;
1525 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1526 writel(temp, sport->port.membase + UCR1);
1527
1528 temp = readl(sport->port.membase + UCR2);
1529 temp |= UCR2_RXEN;
1530 writel(temp, sport->port.membase + UCR2);
1531
1532 spin_unlock_irqrestore(&sport->port.lock, flags);
1533
1534 return 0;
1535}
1536
01f56abd
SA		 1537static int imx_poll_get_char(struct uart_port *port)
1538{
f968ef34 1539 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
26c47412 1540 return NO_POLL_CHAR;
01f56abd 1541
f968ef34 1542 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
01f56abd
SA		 1543}
1544
1545static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1546{
01f56abd
SA		 1547 unsigned int status;
1548
01f56abd
SA		 1549 /* drain */
1550 do {
f968ef34 1551 status = readl_relaxed(port->membase + USR1);
01f56abd
SA		 1552 } while (~status & USR1_TRDY);
1553
1554 /* write */
f968ef34 1555 writel_relaxed(c, port->membase + URTX0);
01f56abd
SA		 1556
1557 /* flush */
1558 do {
f968ef34 1559 status = readl_relaxed(port->membase + USR2);
01f56abd 1560 } while (~status & USR2_TXDC);
01f56abd
SA		 1561}
1562#endif
1563
17b8f2a3
UKK		 1564static int imx_rs485_config(struct uart_port *port,
1565 struct serial_rs485 *rs485conf)
1566{
1567 struct imx_port *sport = (struct imx_port *)port;
1568
1569 /* unimplemented */
1570 rs485conf->delay_rts_before_send = 0;
1571 rs485conf->delay_rts_after_send = 0;
1572 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1573
1574 /* RTS is required to control the transmitter */
1575 if (!sport->have_rtscts)
1576 rs485conf->flags &= ~SER_RS485_ENABLED;
1577
1578 if (rs485conf->flags & SER_RS485_ENABLED) {
1579 unsigned long temp;
1580
1581 /* disable transmitter */
1582 temp = readl(sport->port.membase + UCR2);
1583 temp &= ~UCR2_CTSC;
1584 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1585 temp &= ~UCR2_CTS;
1586 else
1587 temp |= UCR2_CTS;
1588 writel(temp, sport->port.membase + UCR2);
1589 }
1590
1591 port->rs485 = *rs485conf;
1592
1593 return 0;
1594}
1595
1da177e4
LT		 1596static struct uart_ops imx_pops = {
1597 .tx_empty = imx_tx_empty,
1598 .set_mctrl = imx_set_mctrl,
1599 .get_mctrl = imx_get_mctrl,
1600 .stop_tx = imx_stop_tx,
1601 .start_tx = imx_start_tx,
1602 .stop_rx = imx_stop_rx,
1603 .enable_ms = imx_enable_ms,
1604 .break_ctl = imx_break_ctl,
1605 .startup = imx_startup,
1606 .shutdown = imx_shutdown,
eb56b7ed 1607 .flush_buffer = imx_flush_buffer,
1da177e4
LT		 1608 .set_termios = imx_set_termios,
1609 .type = imx_type,
1da177e4
LT		 1610 .config_port = imx_config_port,
1611 .verify_port = imx_verify_port,
01f56abd 1612#if defined(CONFIG_CONSOLE_POLL)
6b8bdad9 1613 .poll_init = imx_poll_init,
01f56abd
SA		 1614 .poll_get_char = imx_poll_get_char,
1615 .poll_put_char = imx_poll_put_char,
1616#endif
1da177e4
LT		 1617};
1618
dbff4e9e 1619static struct imx_port *imx_ports[UART_NR];
1da177e4
LT		 1620
1621#ifdef CONFIG_SERIAL_IMX_CONSOLE
d358788f
RK		 1622static void imx_console_putchar(struct uart_port *port, int ch)
1623{
1624 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 1625
fe6b540a 1626 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
d358788f 1627 barrier();
ff4bfb21
SH		 1628
1629 writel(ch, sport->port.membase + URTX0);
d358788f 1630}
1da177e4
LT		 1631
1632/*
1633 * Interrupts are disabled on entering
1634 */
1635static void
1636imx_console_write(struct console *co, const char *s, unsigned int count)
1637{
dbff4e9e 1638 struct imx_port *sport = imx_ports[co->index];
0ad5a814
DB		 1639 struct imx_port_ucrs old_ucr;
1640 unsigned int ucr1;
f30e8260 1641 unsigned long flags = 0;
677fe555 1642 int locked = 1;
1cf93e0d
HS		 1643 int retval;
1644
9e7b399d 1645 retval = clk_prepare_enable(sport->clk_per);
1cf93e0d
HS		 1646 if (retval)
1647 return;
9e7b399d 1648 retval = clk_prepare_enable(sport->clk_ipg);
1cf93e0d 1649 if (retval) {
9e7b399d 1650 clk_disable_unprepare(sport->clk_per);
1cf93e0d
HS		 1651 return;
1652 }
9ec1882d 1653
677fe555
TG		 1654 if (sport->port.sysrq)
1655 locked = 0;
1656 else if (oops_in_progress)
1657 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1658 else
1659 spin_lock_irqsave(&sport->port.lock, flags);
1da177e4
LT		 1660
1661 /*
0ad5a814 1662 * First, save UCR1/2/3 and then disable interrupts
1da177e4 1663 */
0ad5a814
DB		 1664 imx_port_ucrs_save(&sport->port, &old_ucr);
1665 ucr1 = old_ucr.ucr1;
1da177e4 1666
fe6b540a
SG		 1667 if (is_imx1_uart(sport))
1668 ucr1 |= IMX1_UCR1_UARTCLKEN;
37d6fb62
SH		 1669 ucr1 |= UCR1_UARTEN;
1670 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1671
1672 writel(ucr1, sport->port.membase + UCR1);
ff4bfb21 1673
0ad5a814 1674 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1da177e4 1675
d358788f 1676 uart_console_write(&sport->port, s, count, imx_console_putchar);
1da177e4
LT		 1677
1678 /*
1679 * Finally, wait for transmitter to become empty
0ad5a814 1680 * and restore UCR1/2/3
1da177e4 1681 */
ff4bfb21 1682 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1da177e4 1683
0ad5a814 1684 imx_port_ucrs_restore(&sport->port, &old_ucr);
9ec1882d 1685
677fe555
TG		 1686 if (locked)
1687 spin_unlock_irqrestore(&sport->port.lock, flags);
1cf93e0d 1688
9e7b399d
EV		 1689 clk_disable_unprepare(sport->clk_ipg);
1690 clk_disable_unprepare(sport->clk_per);
1da177e4
LT		 1691}
1692
1693/*
1694 * If the port was already initialised (eg, by a boot loader),
1695 * try to determine the current setup.
1696 */
1697static void __init
1698imx_console_get_options(struct imx_port *sport, int *baud,
1699 int *parity, int *bits)
1700{
587897f5 1701
2e2eb509 1702 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1da177e4 1703 /* ok, the port was enabled */
82313e66 1704 unsigned int ucr2, ubir, ubmr, uartclk;
587897f5
SH		 1705 unsigned int baud_raw;
1706 unsigned int ucfr_rfdiv;
1da177e4 1707
ff4bfb21 1708 ucr2 = readl(sport->port.membase + UCR2);
1da177e4
LT		 1709
1710 *parity = 'n';
1711 if (ucr2 & UCR2_PREN) {
1712 if (ucr2 & UCR2_PROE)
1713 *parity = 'o';
1714 else
1715 *parity = 'e';
1716 }
1717
1718 if (ucr2 & UCR2_WS)
1719 *bits = 8;
1720 else
1721 *bits = 7;
1722
ff4bfb21
SH		 1723 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1724 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
587897f5 1725
ff4bfb21 1726 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
587897f5
SH		 1727 if (ucfr_rfdiv == 6)
1728 ucfr_rfdiv = 7;
1729 else
1730 ucfr_rfdiv = 6 - ucfr_rfdiv;
1731
3a9465fa 1732 uartclk = clk_get_rate(sport->clk_per);
587897f5
SH		 1733 uartclk /= ucfr_rfdiv;
1734
1735 { /*
1736 * The next code provides exact computation of
1737 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1738 * without need of float support or long long division,
1739 * which would be required to prevent 32bit arithmetic overflow
1740 */
1741 unsigned int mul = ubir + 1;
1742 unsigned int div = 16 * (ubmr + 1);
1743 unsigned int rem = uartclk % div;
1744
1745 baud_raw = (uartclk / div) * mul;
1746 baud_raw += (rem * mul + div / 2) / div;
1747 *baud = (baud_raw + 50) / 100 * 100;
1748 }
1749
82313e66 1750 if (*baud != baud_raw)
50bbdba3 1751 pr_info("Console IMX rounded baud rate from %d to %d\n",
587897f5 1752 baud_raw, *baud);
1da177e4
LT		 1753 }
1754}
1755
1756static int __init
1757imx_console_setup(struct console *co, char *options)
1758{
1759 struct imx_port *sport;
1760 int baud = 9600;
1761 int bits = 8;
1762 int parity = 'n';
1763 int flow = 'n';
1cf93e0d 1764 int retval;
1da177e4
LT		 1765
1766 /*
1767 * Check whether an invalid uart number has been specified, and
1768 * if so, search for the first available port that does have
1769 * console support.
1770 */
1771 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1772 co->index = 0;
dbff4e9e 1773 sport = imx_ports[co->index];
82313e66 1774 if (sport == NULL)
e76afc4e 1775 return -ENODEV;
1da177e4 1776
1cf93e0d
HS		 1777 /* For setting the registers, we only need to enable the ipg clock. */
1778 retval = clk_prepare_enable(sport->clk_ipg);
1779 if (retval)
1780 goto error_console;
1781
1da177e4
LT		 1782 if (options)
1783 uart_parse_options(options, &baud, &parity, &bits, &flow);
1784 else
1785 imx_console_get_options(sport, &baud, &parity, &bits);
1786
cc32382d 1787 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
587897f5 1788
1cf93e0d
HS		 1789 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1790
9e7b399d 1791 clk_disable_unprepare(sport->clk_ipg);
1cf93e0d
HS		 1792
1793error_console:
1794 return retval;
1da177e4
LT		 1795}
1796
9f4426dd 1797static struct uart_driver imx_reg;
1da177e4 1798static struct console imx_console = {
e3d13ff4 1799 .name = DEV_NAME,
1da177e4
LT		 1800 .write = imx_console_write,
1801 .device = uart_console_device,
1802 .setup = imx_console_setup,
1803 .flags = CON_PRINTBUFFER,
1804 .index = -1,
1805 .data = &imx_reg,
1806};
1807
1da177e4 1808#define IMX_CONSOLE &imx_console
913c6c0e
LS		 1809
1810#ifdef CONFIG_OF
1811static void imx_console_early_putchar(struct uart_port *port, int ch)
1812{
1813 while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL)
1814 cpu_relax();
1815
1816 writel_relaxed(ch, port->membase + URTX0);
1817}
1818
1819static void imx_console_early_write(struct console *con, const char *s,
1820 unsigned count)
1821{
1822 struct earlycon_device *dev = con->data;
1823
1824 uart_console_write(&dev->port, s, count, imx_console_early_putchar);
1825}
1826
1827static int __init
1828imx_console_early_setup(struct earlycon_device *dev, const char *opt)
1829{
1830 if (!dev->port.membase)
1831 return -ENODEV;
1832
1833 dev->con->write = imx_console_early_write;
1834
1835 return 0;
1836}
1837OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
1838OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
1839#endif
1840
1da177e4
LT		 1841#else
1842#define IMX_CONSOLE NULL
1843#endif
1844
1845static struct uart_driver imx_reg = {
1846 .owner = THIS_MODULE,
1847 .driver_name = DRIVER_NAME,
e3d13ff4 1848 .dev_name = DEV_NAME,
1da177e4
LT		 1849 .major = SERIAL_IMX_MAJOR,
1850 .minor = MINOR_START,
1851 .nr = ARRAY_SIZE(imx_ports),
1852 .cons = IMX_CONSOLE,
1853};
1854
22698aa2 1855#ifdef CONFIG_OF
20bb8095
UKK		 1856/*
1857 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1858 * could successfully get all information from dt or a negative errno.
1859 */
22698aa2
SG		 1860static int serial_imx_probe_dt(struct imx_port *sport,
1861 struct platform_device *pdev)
1862{
1863 struct device_node *np = pdev->dev.of_node;
1864 const struct of_device_id *of_id =
1865 of_match_device(imx_uart_dt_ids, &pdev->dev);
ff05967a 1866 int ret;
22698aa2
SG		 1867
1868 if (!np)
20bb8095
UKK		 1869 /* no device tree device */
1870 return 1;
22698aa2 1871
ff05967a
SG		 1872 ret = of_alias_get_id(np, "serial");
1873 if (ret < 0) {
1874 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
a197a191 1875 return ret;
ff05967a
SG		 1876 }
1877 sport->port.line = ret;
22698aa2
SG		 1878
1879 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1880 sport->have_rtscts = 1;
1881
20ff2fe6
HS		 1882 if (of_get_property(np, "fsl,dte-mode", NULL))
1883 sport->dte_mode = 1;
1884
22698aa2
SG		 1885 sport->devdata = of_id->data;
1886
1887 return 0;
1888}
1889#else
1890static inline int serial_imx_probe_dt(struct imx_port *sport,
1891 struct platform_device *pdev)
1892{
20bb8095 1893 return 1;
22698aa2
SG		 1894}
1895#endif
1896
1897static void serial_imx_probe_pdata(struct imx_port *sport,
1898 struct platform_device *pdev)
1899{
574de559 1900 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
22698aa2
SG		 1901
1902 sport->port.line = pdev->id;
1903 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1904
1905 if (!pdata)
1906 return;
1907
1908 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1909 sport->have_rtscts = 1;
22698aa2
SG		 1910}
1911
2582d8c1 1912static int serial_imx_probe(struct platform_device *pdev)
1da177e4 1913{
dbff4e9e 1914 struct imx_port *sport;
dbff4e9e 1915 void __iomem *base;
8a61f0c7 1916 int ret = 0, reg;
dbff4e9e 1917 struct resource *res;
842633bd 1918 int txirq, rxirq, rtsirq;
dbff4e9e 1919
42d34191 1920 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
dbff4e9e
SH		 1921 if (!sport)
1922 return -ENOMEM;
5b802344 1923
22698aa2 1924 ret = serial_imx_probe_dt(sport, pdev);
20bb8095 1925 if (ret > 0)
22698aa2 1926 serial_imx_probe_pdata(sport, pdev);
20bb8095 1927 else if (ret < 0)
42d34191 1928 return ret;
22698aa2 1929
dbff4e9e 1930 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
da82f997
AS		 1931 base = devm_ioremap_resource(&pdev->dev, res);
1932 if (IS_ERR(base))
1933 return PTR_ERR(base);
dbff4e9e 1934
842633bd
UKK		 1935 rxirq = platform_get_irq(pdev, 0);
1936 txirq = platform_get_irq(pdev, 1);
1937 rtsirq = platform_get_irq(pdev, 2);
1938
dbff4e9e
SH		 1939 sport->port.dev = &pdev->dev;
1940 sport->port.mapbase = res->start;
1941 sport->port.membase = base;
1942 sport->port.type = PORT_IMX,
1943 sport->port.iotype = UPIO_MEM;
842633bd 1944 sport->port.irq = rxirq;
dbff4e9e
SH		 1945 sport->port.fifosize = 32;
1946 sport->port.ops = &imx_pops;
17b8f2a3
UKK		 1947 sport->port.rs485_config = imx_rs485_config;
1948 sport->port.rs485.flags =
1949 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX;
dbff4e9e 1950 sport->port.flags = UPF_BOOT_AUTOCONF;
dbff4e9e
SH		 1951 init_timer(&sport->timer);
1952 sport->timer.function = imx_timeout;
1953 sport->timer.data = (unsigned long)sport;
38a41fdf 1954
3a9465fa
SH		 1955 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1956 if (IS_ERR(sport->clk_ipg)) {
1957 ret = PTR_ERR(sport->clk_ipg);
833462e9 1958 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
42d34191 1959 return ret;
38a41fdf 1960 }
38a41fdf 1961
3a9465fa
SH		 1962 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1963 if (IS_ERR(sport->clk_per)) {
1964 ret = PTR_ERR(sport->clk_per);
833462e9 1965 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
42d34191 1966 return ret;
3a9465fa
SH		 1967 }
1968
3a9465fa 1969 sport->port.uartclk = clk_get_rate(sport->clk_per);
dbff4e9e 1970
8a61f0c7
FE		 1971 /* For register access, we only need to enable the ipg clock. */
1972 ret = clk_prepare_enable(sport->clk_ipg);
1973 if (ret)
1974 return ret;
1975
1976 /* Disable interrupts before requesting them */
1977 reg = readl_relaxed(sport->port.membase + UCR1);
1978 reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
1979 UCR1_TXMPTYEN | UCR1_RTSDEN);
1980 writel_relaxed(reg, sport->port.membase + UCR1);
1981
1982 clk_disable_unprepare(sport->clk_ipg);
1983
c0d1c6b0
FE		 1984 /*
1985 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1986 * chips only have one interrupt.
1987 */
842633bd
UKK		 1988 if (txirq > 0) {
1989 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
c0d1c6b0
FE		 1990 dev_name(&pdev->dev), sport);
1991 if (ret)
1992 return ret;
1993
842633bd 1994 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
c0d1c6b0
FE		 1995 dev_name(&pdev->dev), sport);
1996 if (ret)
1997 return ret;
c0d1c6b0 1998 } else {
842633bd 1999 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
c0d1c6b0
FE		 2000 dev_name(&pdev->dev), sport);
2001 if (ret)
2002 return ret;
2003 }
2004
22698aa2 2005 imx_ports[sport->port.line] = sport;
5b802344 2006
0a86a86b 2007 platform_set_drvdata(pdev, sport);
5b802344 2008
45af780a 2009 return uart_add_one_port(&imx_reg, &sport->port);
1da177e4
LT		 2010}
2011
2582d8c1 2012static int serial_imx_remove(struct platform_device *pdev)
1da177e4 2013{
2582d8c1 2014 struct imx_port *sport = platform_get_drvdata(pdev);
1da177e4 2015
45af780a 2016 return uart_remove_one_port(&imx_reg, &sport->port);
1da177e4
LT		 2017}
2018
c868cbb7
EV		 2019static void serial_imx_restore_context(struct imx_port *sport)
2020{
2021 if (!sport->context_saved)
2022 return;
2023
2024 writel(sport->saved_reg[4], sport->port.membase + UFCR);
2025 writel(sport->saved_reg[5], sport->port.membase + UESC);
2026 writel(sport->saved_reg[6], sport->port.membase + UTIM);
2027 writel(sport->saved_reg[7], sport->port.membase + UBIR);
2028 writel(sport->saved_reg[8], sport->port.membase + UBMR);
2029 writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS);
2030 writel(sport->saved_reg[0], sport->port.membase + UCR1);
2031 writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2);
2032 writel(sport->saved_reg[2], sport->port.membase + UCR3);
2033 writel(sport->saved_reg[3], sport->port.membase + UCR4);
2034 sport->context_saved = false;
2035}
2036
2037static void serial_imx_save_context(struct imx_port *sport)
2038{
2039 /* Save necessary regs */
2040 sport->saved_reg[0] = readl(sport->port.membase + UCR1);
2041 sport->saved_reg[1] = readl(sport->port.membase + UCR2);
2042 sport->saved_reg[2] = readl(sport->port.membase + UCR3);
2043 sport->saved_reg[3] = readl(sport->port.membase + UCR4);
2044 sport->saved_reg[4] = readl(sport->port.membase + UFCR);
2045 sport->saved_reg[5] = readl(sport->port.membase + UESC);
2046 sport->saved_reg[6] = readl(sport->port.membase + UTIM);
2047 sport->saved_reg[7] = readl(sport->port.membase + UBIR);
2048 sport->saved_reg[8] = readl(sport->port.membase + UBMR);
2049 sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS);
2050 sport->context_saved = true;
2051}
2052
189550b8
EV		 2053static void serial_imx_enable_wakeup(struct imx_port *sport, bool on)
2054{
2055 unsigned int val;
2056
2057 val = readl(sport->port.membase + UCR3);
2058 if (on)
2059 val |= UCR3_AWAKEN;
2060 else
2061 val &= ~UCR3_AWAKEN;
2062 writel(val, sport->port.membase + UCR3);
bc85734b
EV		 2063
2064 val = readl(sport->port.membase + UCR1);
2065 if (on)
2066 val |= UCR1_RTSDEN;
2067 else
2068 val &= ~UCR1_RTSDEN;
2069 writel(val, sport->port.membase + UCR1);
189550b8
EV		 2070}
2071
90bb6bd3
SW		 2072static int imx_serial_port_suspend_noirq(struct device *dev)
2073{
2074 struct platform_device *pdev = to_platform_device(dev);
2075 struct imx_port *sport = platform_get_drvdata(pdev);
2076 int ret;
2077
2078 ret = clk_enable(sport->clk_ipg);
2079 if (ret)
2080 return ret;
2081
c868cbb7 2082 serial_imx_save_context(sport);
90bb6bd3
SW		 2083
2084 clk_disable(sport->clk_ipg);
2085
2086 return 0;
2087}
2088
2089static int imx_serial_port_resume_noirq(struct device *dev)
2090{
2091 struct platform_device *pdev = to_platform_device(dev);
2092 struct imx_port *sport = platform_get_drvdata(pdev);
2093 int ret;
2094
2095 ret = clk_enable(sport->clk_ipg);
2096 if (ret)
2097 return ret;
2098
c868cbb7 2099 serial_imx_restore_context(sport);
90bb6bd3
SW		 2100
2101 clk_disable(sport->clk_ipg);
2102
2103 return 0;
2104}
2105
2106static int imx_serial_port_suspend(struct device *dev)
2107{
2108 struct platform_device *pdev = to_platform_device(dev);
2109 struct imx_port *sport = platform_get_drvdata(pdev);
90bb6bd3
SW		 2110
2111 /* enable wakeup from i.MX UART */
189550b8 2112 serial_imx_enable_wakeup(sport, true);
90bb6bd3
SW		 2113
2114 uart_suspend_port(&imx_reg, &sport->port);
2115
2116 return 0;
2117}
2118
2119static int imx_serial_port_resume(struct device *dev)
2120{
2121 struct platform_device *pdev = to_platform_device(dev);
2122 struct imx_port *sport = platform_get_drvdata(pdev);
90bb6bd3
SW		 2123
2124 /* disable wakeup from i.MX UART */
189550b8 2125 serial_imx_enable_wakeup(sport, false);
90bb6bd3
SW		 2126
2127 uart_resume_port(&imx_reg, &sport->port);
2128
2129 return 0;
2130}
2131
2132static const struct dev_pm_ops imx_serial_port_pm_ops = {
2133 .suspend_noirq = imx_serial_port_suspend_noirq,
2134 .resume_noirq = imx_serial_port_resume_noirq,
2135 .suspend = imx_serial_port_suspend,
2136 .resume = imx_serial_port_resume,
2137};
2138
3ae5eaec 2139static struct platform_driver serial_imx_driver = {
d3810cd4
OS		 2140 .probe = serial_imx_probe,
2141 .remove = serial_imx_remove,
1da177e4 2142
fe6b540a 2143 .id_table = imx_uart_devtype,
3ae5eaec 2144 .driver = {
d3810cd4 2145 .name = "imx-uart",
22698aa2 2146 .of_match_table = imx_uart_dt_ids,
90bb6bd3 2147 .pm = &imx_serial_port_pm_ops,
3ae5eaec 2148 },
1da177e4
LT		 2149};
2150
2151static int __init imx_serial_init(void)
2152{
f0fd1b73 2153 int ret = uart_register_driver(&imx_reg);
1da177e4 2154
1da177e4
LT		 2155 if (ret)
2156 return ret;
2157
3ae5eaec 2158 ret = platform_driver_register(&serial_imx_driver);
1da177e4
LT		 2159 if (ret != 0)
2160 uart_unregister_driver(&imx_reg);
2161
f227824e 2162 return ret;
1da177e4
LT		 2163}
2164
2165static void __exit imx_serial_exit(void)
2166{
c889b896 2167 platform_driver_unregister(&serial_imx_driver);
4b300c36 2168 uart_unregister_driver(&imx_reg);
1da177e4
LT		 2169}
2170
2171module_init(imx_serial_init);
2172module_exit(imx_serial_exit);
2173
2174MODULE_AUTHOR("Sascha Hauer");
2175MODULE_DESCRIPTION("IMX generic serial port driver");
2176MODULE_LICENSE("GPL");
e169c139 2177MODULE_ALIAS("platform:imx-uart");
Linux kernel - Deliverables
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