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serial: Style fix
[deliverable/linux.git] / drivers / tty / serial / imx.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
b6e49138
FG		 9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
1da177e4
LT		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
1da177e4
LT		 29
30#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31#define SUPPORT_SYSRQ
32#endif
33
34#include <linux/module.h>
35#include <linux/ioport.h>
36#include <linux/init.h>
37#include <linux/console.h>
38#include <linux/sysrq.h>
d052d1be 39#include <linux/platform_device.h>
1da177e4
LT		 40#include <linux/tty.h>
41#include <linux/tty_flip.h>
42#include <linux/serial_core.h>
43#include <linux/serial.h>
38a41fdf 44#include <linux/clk.h>
b6e49138 45#include <linux/delay.h>
534fca06 46#include <linux/rational.h>
5a0e3ad6 47#include <linux/slab.h>
22698aa2
SG		 48#include <linux/of.h>
49#include <linux/of_device.h>
e32a9f8f 50#include <linux/io.h>
b4cdc8f6 51#include <linux/dma-mapping.h>
1da177e4 52
1da177e4 53#include <asm/irq.h>
82906b13 54#include <linux/platform_data/serial-imx.h>
b4cdc8f6 55#include <linux/platform_data/dma-imx.h>
1da177e4 56
ff4bfb21
SH		 57/* Register definitions */
58#define URXD0 0x0 /* Receiver Register */
59#define URTX0 0x40 /* Transmitter Register */
60#define UCR1 0x80 /* Control Register 1 */
61#define UCR2 0x84 /* Control Register 2 */
62#define UCR3 0x88 /* Control Register 3 */
63#define UCR4 0x8c /* Control Register 4 */
64#define UFCR 0x90 /* FIFO Control Register */
65#define USR1 0x94 /* Status Register 1 */
66#define USR2 0x98 /* Status Register 2 */
67#define UESC 0x9c /* Escape Character Register */
68#define UTIM 0xa0 /* Escape Timer Register */
69#define UBIR 0xa4 /* BRM Incremental Register */
70#define UBMR 0xa8 /* BRM Modulator Register */
71#define UBRC 0xac /* Baud Rate Count Register */
fe6b540a
SG		 72#define IMX21_ONEMS 0xb0 /* One Millisecond register */
73#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
74#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
ff4bfb21
SH		 75
76/* UART Control Register Bit Fields.*/
82313e66
SK		 77#define URXD_CHARRDY (1<<15)
78#define URXD_ERR (1<<14)
79#define URXD_OVRRUN (1<<13)
80#define URXD_FRMERR (1<<12)
81#define URXD_BRK (1<<11)
82#define URXD_PRERR (1<<10)
83#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
84#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
85#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
86#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
b4cdc8f6 87#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
82313e66
SK		 88#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
89#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
90#define UCR1_IREN (1<<7) /* Infrared interface enable */
91#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
92#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
93#define UCR1_SNDBRK (1<<4) /* Send break */
94#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
95#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
b4cdc8f6 96#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
82313e66
SK		 97#define UCR1_DOZE (1<<1) /* Doze */
98#define UCR1_UARTEN (1<<0) /* UART enabled */
99#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
100#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
101#define UCR2_CTSC (1<<13) /* CTS pin control */
102#define UCR2_CTS (1<<12) /* Clear to send */
103#define UCR2_ESCEN (1<<11) /* Escape enable */
104#define UCR2_PREN (1<<8) /* Parity enable */
105#define UCR2_PROE (1<<7) /* Parity odd/even */
106#define UCR2_STPB (1<<6) /* Stop */
107#define UCR2_WS (1<<5) /* Word size */
108#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
109#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
110#define UCR2_TXEN (1<<2) /* Transmitter enabled */
111#define UCR2_RXEN (1<<1) /* Receiver enabled */
112#define UCR2_SRST (1<<0) /* SW reset */
113#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
114#define UCR3_PARERREN (1<<12) /* Parity enable */
115#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
116#define UCR3_DSR (1<<10) /* Data set ready */
117#define UCR3_DCD (1<<9) /* Data carrier detect */
118#define UCR3_RI (1<<8) /* Ring indicator */
b38cb7d2 119#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
82313e66
SK		 120#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
121#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
122#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
123#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
124#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
125#define UCR3_BPEN (1<<0) /* Preset registers enable */
126#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
127#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
128#define UCR4_INVR (1<<9) /* Inverted infrared reception */
129#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
130#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
131#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
b4cdc8f6 132#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
82313e66
SK		 133#define UCR4_IRSC (1<<5) /* IR special case */
134#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
135#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
136#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
137#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
138#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
139#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
140#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
141#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
142#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
143#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
144#define USR1_RTSS (1<<14) /* RTS pin status */
145#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
146#define USR1_RTSD (1<<12) /* RTS delta */
147#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
148#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
149#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
150#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
151#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
152#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
153#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
154#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
155#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
156#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
157#define USR2_IDLE (1<<12) /* Idle condition */
158#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
159#define USR2_WAKE (1<<7) /* Wake */
160#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
161#define USR2_TXDC (1<<3) /* Transmitter complete */
162#define USR2_BRCD (1<<2) /* Break condition */
163#define USR2_ORE (1<<1) /* Overrun error */
164#define USR2_RDR (1<<0) /* Recv data ready */
165#define UTS_FRCPERR (1<<13) /* Force parity error */
166#define UTS_LOOP (1<<12) /* Loop tx and rx */
167#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
168#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
169#define UTS_TXFULL (1<<4) /* TxFIFO full */
170#define UTS_RXFULL (1<<3) /* RxFIFO full */
171#define UTS_SOFTRST (1<<0) /* Software reset */
ff4bfb21 172
1da177e4 173/* We've been assigned a range on the "Low-density serial ports" major */
82313e66
SK		 174#define SERIAL_IMX_MAJOR 207
175#define MINOR_START 16
e3d13ff4 176#define DEV_NAME "ttymxc"
1da177e4 177
1da177e4
LT		 178/*
179 * This determines how often we check the modem status signals
180 * for any change. They generally aren't connected to an IRQ
181 * so we have to poll them. We also check immediately before
182 * filling the TX fifo incase CTS has been dropped.
183 */
184#define MCTRL_TIMEOUT (250*HZ/1000)
185
186#define DRIVER_NAME "IMX-uart"
187
dbff4e9e
SH		 188#define UART_NR 8
189
fe6b540a
SG		 190/* i.mx21 type uart runs on all i.mx except i.mx1 */
191enum imx_uart_type {
192 IMX1_UART,
193 IMX21_UART,
a496e628 194 IMX6Q_UART,
fe6b540a
SG		 195};
196
197/* device type dependent stuff */
198struct imx_uart_data {
199 unsigned uts_reg;
200 enum imx_uart_type devtype;
201};
202
1da177e4
LT		 203struct imx_port {
204 struct uart_port port;
205 struct timer_list timer;
206 unsigned int old_status;
82313e66 207 int txirq, rxirq, rtsirq;
26bbb3ff 208 unsigned int have_rtscts:1;
20ff2fe6 209 unsigned int dte_mode:1;
b6e49138
FG		 210 unsigned int use_irda:1;
211 unsigned int irda_inv_rx:1;
212 unsigned int irda_inv_tx:1;
213 unsigned short trcv_delay; /* transceiver delay */
3a9465fa
SH		 214 struct clk *clk_ipg;
215 struct clk *clk_per;
7d0b066f 216 const struct imx_uart_data *devdata;
b4cdc8f6
HS		 217
218 /* DMA fields */
219 unsigned int dma_is_inited:1;
220 unsigned int dma_is_enabled:1;
221 unsigned int dma_is_rxing:1;
222 unsigned int dma_is_txing:1;
223 struct dma_chan *dma_chan_rx, *dma_chan_tx;
224 struct scatterlist rx_sgl, tx_sgl[2];
225 void *rx_buf;
7cb92fd2 226 unsigned int tx_bytes;
b4cdc8f6 227 unsigned int dma_tx_nents;
9ce4f8f3 228 wait_queue_head_t dma_wait;
1da177e4
LT		 229};
230
0ad5a814
DB		 231struct imx_port_ucrs {
232 unsigned int ucr1;
233 unsigned int ucr2;
234 unsigned int ucr3;
235};
236
b6e49138
FG		 237#ifdef CONFIG_IRDA
238#define USE_IRDA(sport) ((sport)->use_irda)
239#else
240#define USE_IRDA(sport) (0)
241#endif
242
fe6b540a
SG		 243static struct imx_uart_data imx_uart_devdata[] = {
244 [IMX1_UART] = {
245 .uts_reg = IMX1_UTS,
246 .devtype = IMX1_UART,
247 },
248 [IMX21_UART] = {
249 .uts_reg = IMX21_UTS,
250 .devtype = IMX21_UART,
251 },
a496e628
HS		 252 [IMX6Q_UART] = {
253 .uts_reg = IMX21_UTS,
254 .devtype = IMX6Q_UART,
255 },
fe6b540a
SG		 256};
257
258static struct platform_device_id imx_uart_devtype[] = {
259 {
260 .name = "imx1-uart",
261 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
262 }, {
263 .name = "imx21-uart",
264 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
a496e628
HS		 265 }, {
266 .name = "imx6q-uart",
267 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
fe6b540a
SG		 268 }, {
269 /* sentinel */
270 }
271};
272MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
273
22698aa2 274static struct of_device_id imx_uart_dt_ids[] = {
a496e628 275 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
22698aa2
SG		 276 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
277 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
278 { /* sentinel */ }
279};
280MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
281
fe6b540a
SG		 282static inline unsigned uts_reg(struct imx_port *sport)
283{
284 return sport->devdata->uts_reg;
285}
286
287static inline int is_imx1_uart(struct imx_port *sport)
288{
289 return sport->devdata->devtype == IMX1_UART;
290}
291
292static inline int is_imx21_uart(struct imx_port *sport)
293{
294 return sport->devdata->devtype == IMX21_UART;
295}
296
a496e628
HS		 297static inline int is_imx6q_uart(struct imx_port *sport)
298{
299 return sport->devdata->devtype == IMX6Q_UART;
300}
44a75411 301/*
302 * Save and restore functions for UCR1, UCR2 and UCR3 registers
303 */
e8bfa760 304#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_IMX_CONSOLE)
44a75411 305static void imx_port_ucrs_save(struct uart_port *port,
306 struct imx_port_ucrs *ucr)
307{
308 /* save control registers */
309 ucr->ucr1 = readl(port->membase + UCR1);
310 ucr->ucr2 = readl(port->membase + UCR2);
311 ucr->ucr3 = readl(port->membase + UCR3);
312}
313
314static void imx_port_ucrs_restore(struct uart_port *port,
315 struct imx_port_ucrs *ucr)
316{
317 /* restore control registers */
318 writel(ucr->ucr1, port->membase + UCR1);
319 writel(ucr->ucr2, port->membase + UCR2);
320 writel(ucr->ucr3, port->membase + UCR3);
321}
e8bfa760 322#endif
44a75411 323
1da177e4
LT		 324/*
325 * Handle any change of modem status signal since we were last called.
326 */
327static void imx_mctrl_check(struct imx_port *sport)
328{
329 unsigned int status, changed;
330
331 status = sport->port.ops->get_mctrl(&sport->port);
332 changed = status ^ sport->old_status;
333
334 if (changed == 0)
335 return;
336
337 sport->old_status = status;
338
339 if (changed & TIOCM_RI)
340 sport->port.icount.rng++;
341 if (changed & TIOCM_DSR)
342 sport->port.icount.dsr++;
343 if (changed & TIOCM_CAR)
344 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
345 if (changed & TIOCM_CTS)
346 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
347
bdc04e31 348 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
1da177e4
LT		 349}
350
351/*
352 * This is our per-port timeout handler, for checking the
353 * modem status signals.
354 */
355static void imx_timeout(unsigned long data)
356{
357 struct imx_port *sport = (struct imx_port *)data;
358 unsigned long flags;
359
ebd2c8f6 360 if (sport->port.state) {
1da177e4
LT		 361 spin_lock_irqsave(&sport->port.lock, flags);
362 imx_mctrl_check(sport);
363 spin_unlock_irqrestore(&sport->port.lock, flags);
364
365 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
366 }
367}
368
369/*
370 * interrupts disabled on entry
371 */
b129a8cc 372static void imx_stop_tx(struct uart_port *port)
1da177e4
LT		 373{
374 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 375 unsigned long temp;
376
b6e49138
FG		 377 if (USE_IRDA(sport)) {
378 /* half duplex - wait for end of transmission */
379 int n = 256;
380 while ((--n > 0) &&
381 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
382 udelay(5);
383 barrier();
384 }
385 /*
386 * irda transceiver - wait a bit more to avoid
387 * cutoff, hardware dependent
388 */
389 udelay(sport->trcv_delay);
390
391 /*
392 * half duplex - reactivate receive mode,
393 * flush receive pipe echo crap
394 */
395 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
396 temp = readl(sport->port.membase + UCR1);
397 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
398 writel(temp, sport->port.membase + UCR1);
399
400 temp = readl(sport->port.membase + UCR4);
401 temp &= ~(UCR4_TCEN);
402 writel(temp, sport->port.membase + UCR4);
403
404 while (readl(sport->port.membase + URXD0) &
405 URXD_CHARRDY)
406 barrier();
407
408 temp = readl(sport->port.membase + UCR1);
409 temp |= UCR1_RRDYEN;
410 writel(temp, sport->port.membase + UCR1);
411
412 temp = readl(sport->port.membase + UCR4);
413 temp |= UCR4_DREN;
414 writel(temp, sport->port.membase + UCR4);
415 }
416 return;
417 }
418
9ce4f8f3
GKH		 419 /*
420 * We are maybe in the SMP context, so if the DMA TX thread is running
421 * on other cpu, we have to wait for it to finish.
422 */
423 if (sport->dma_is_enabled && sport->dma_is_txing)
424 return;
b4cdc8f6 425
ff4bfb21
SH		 426 temp = readl(sport->port.membase + UCR1);
427 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
1da177e4
LT		 428}
429
430/*
431 * interrupts disabled on entry
432 */
433static void imx_stop_rx(struct uart_port *port)
434{
435 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 436 unsigned long temp;
437
9ce4f8f3
GKH		 438 /*
439 * We are maybe in the SMP context, so if the DMA TX thread is running
440 * on other cpu, we have to wait for it to finish.
441 */
442 if (sport->dma_is_enabled && sport->dma_is_rxing)
443 return;
b4cdc8f6 444
ff4bfb21 445 temp = readl(sport->port.membase + UCR2);
82313e66 446 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
85878399
HS		 447
448 /* disable the `Receiver Ready Interrrupt` */
449 temp = readl(sport->port.membase + UCR1);
450 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
1da177e4
LT		 451}
452
453/*
454 * Set the modem control timer to fire immediately.
455 */
456static void imx_enable_ms(struct uart_port *port)
457{
458 struct imx_port *sport = (struct imx_port *)port;
459
460 mod_timer(&sport->timer, jiffies);
461}
462
463static inline void imx_transmit_buffer(struct imx_port *sport)
464{
ebd2c8f6 465 struct circ_buf *xmit = &sport->port.state->xmit;
1da177e4 466
4e4e6602 467 while (!uart_circ_empty(xmit) &&
fe6b540a
SG		 468 !(readl(sport->port.membase + uts_reg(sport))
469 & UTS_TXFULL)) {
1da177e4
LT		 470 /* send xmit->buf[xmit->tail]
471 * out the port here */
ff4bfb21 472 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
d3810cd4 473 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1da177e4 474 sport->port.icount.tx++;
8c0b254b 475 }
1da177e4 476
97775731
FG		 477 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
478 uart_write_wakeup(&sport->port);
479
1da177e4 480 if (uart_circ_empty(xmit))
b129a8cc 481 imx_stop_tx(&sport->port);
1da177e4
LT		 482}
483
b4cdc8f6
HS		 484static void dma_tx_callback(void *data)
485{
486 struct imx_port *sport = data;
487 struct scatterlist *sgl = &sport->tx_sgl[0];
488 struct circ_buf *xmit = &sport->port.state->xmit;
489 unsigned long flags;
490
491 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
492
493 sport->dma_is_txing = 0;
494
495 /* update the stat */
496 spin_lock_irqsave(&sport->port.lock, flags);
497 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
498 sport->port.icount.tx += sport->tx_bytes;
499 spin_unlock_irqrestore(&sport->port.lock, flags);
500
501 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
502
2ad28e3e 503 uart_write_wakeup(&sport->port);
9ce4f8f3
GKH		 504
505 if (waitqueue_active(&sport->dma_wait)) {
506 wake_up(&sport->dma_wait);
507 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
508 return;
509 }
b4cdc8f6
HS		 510}
511
7cb92fd2 512static void imx_dma_tx(struct imx_port *sport)
b4cdc8f6 513{
b4cdc8f6
HS		 514 struct circ_buf *xmit = &sport->port.state->xmit;
515 struct scatterlist *sgl = sport->tx_sgl;
516 struct dma_async_tx_descriptor *desc;
517 struct dma_chan *chan = sport->dma_chan_tx;
518 struct device *dev = sport->port.dev;
519 enum dma_status status;
b4cdc8f6
HS		 520 int ret;
521
f0ef8834 522 status = dmaengine_tx_status(chan, (dma_cookie_t)0, NULL);
b4cdc8f6
HS		 523 if (DMA_IN_PROGRESS == status)
524 return;
525
b4cdc8f6 526 sport->tx_bytes = uart_circ_chars_pending(xmit);
b4cdc8f6 527
947c74eb 528 if (xmit->tail > xmit->head && xmit->head > 0) {
b4cdc8f6
HS		 529 sport->dma_tx_nents = 2;
530 sg_init_table(sgl, 2);
531 sg_set_buf(sgl, xmit->buf + xmit->tail,
532 UART_XMIT_SIZE - xmit->tail);
533 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
534 } else {
535 sport->dma_tx_nents = 1;
536 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
537 }
b4cdc8f6
HS		 538
539 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
540 if (ret == 0) {
541 dev_err(dev, "DMA mapping error for TX.\n");
542 return;
543 }
544 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
545 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
546 if (!desc) {
547 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
548 return;
549 }
550 desc->callback = dma_tx_callback;
551 desc->callback_param = sport;
552
553 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
554 uart_circ_chars_pending(xmit));
555 /* fire it */
556 sport->dma_is_txing = 1;
557 dmaengine_submit(desc);
558 dma_async_issue_pending(chan);
559 return;
560}
561
1da177e4
LT		 562/*
563 * interrupts disabled on entry
564 */
b129a8cc 565static void imx_start_tx(struct uart_port *port)
1da177e4
LT		 566{
567 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 568 unsigned long temp;
1da177e4 569
8bec751b 570 if (uart_circ_empty(&port->state->xmit))
c557d392
PH		 571 return;
572
b6e49138
FG		 573 if (USE_IRDA(sport)) {
574 /* half duplex in IrDA mode; have to disable receive mode */
575 temp = readl(sport->port.membase + UCR4);
576 temp &= ~(UCR4_DREN);
577 writel(temp, sport->port.membase + UCR4);
578
579 temp = readl(sport->port.membase + UCR1);
580 temp &= ~(UCR1_RRDYEN);
581 writel(temp, sport->port.membase + UCR1);
582 }
f1f836e4
AS		 583 /* Clear any pending ORE flag before enabling interrupt */
584 temp = readl(sport->port.membase + USR2);
585 writel(temp | USR2_ORE, sport->port.membase + USR2);
586
587 temp = readl(sport->port.membase + UCR4);
588 temp |= UCR4_OREN;
589 writel(temp, sport->port.membase + UCR4);
b6e49138 590
b4cdc8f6
HS		 591 if (!sport->dma_is_enabled) {
592 temp = readl(sport->port.membase + UCR1);
593 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
594 }
1da177e4 595
b6e49138
FG		 596 if (USE_IRDA(sport)) {
597 temp = readl(sport->port.membase + UCR1);
598 temp |= UCR1_TRDYEN;
599 writel(temp, sport->port.membase + UCR1);
600
601 temp = readl(sport->port.membase + UCR4);
602 temp |= UCR4_TCEN;
603 writel(temp, sport->port.membase + UCR4);
604 }
605
b4cdc8f6 606 if (sport->dma_is_enabled) {
7cb92fd2 607 imx_dma_tx(sport);
b4cdc8f6
HS		 608 return;
609 }
610
fe6b540a 611 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
ff4bfb21 612 imx_transmit_buffer(sport);
1da177e4
LT		 613}
614
7d12e780 615static irqreturn_t imx_rtsint(int irq, void *dev_id)
ceca629e 616{
15aafa2f 617 struct imx_port *sport = dev_id;
5680e941 618 unsigned int val;
ceca629e
SH		 619 unsigned long flags;
620
621 spin_lock_irqsave(&sport->port.lock, flags);
622
ff4bfb21 623 writel(USR1_RTSD, sport->port.membase + USR1);
5680e941 624 val = readl(sport->port.membase + USR1) & USR1_RTSS;
ceca629e 625 uart_handle_cts_change(&sport->port, !!val);
bdc04e31 626 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
ceca629e
SH		 627
628 spin_unlock_irqrestore(&sport->port.lock, flags);
629 return IRQ_HANDLED;
630}
631
7d12e780 632static irqreturn_t imx_txint(int irq, void *dev_id)
1da177e4 633{
15aafa2f 634 struct imx_port *sport = dev_id;
ebd2c8f6 635 struct circ_buf *xmit = &sport->port.state->xmit;
1da177e4
LT		 636 unsigned long flags;
637
82313e66 638 spin_lock_irqsave(&sport->port.lock, flags);
699cbd67 639 if (sport->port.x_char) {
1da177e4 640 /* Send next char */
ff4bfb21 641 writel(sport->port.x_char, sport->port.membase + URTX0);
1da177e4
LT		 642 goto out;
643 }
644
645 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
b129a8cc 646 imx_stop_tx(&sport->port);
1da177e4
LT		 647 goto out;
648 }
649
650 imx_transmit_buffer(sport);
651
652 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
653 uart_write_wakeup(&sport->port);
654
655out:
82313e66 656 spin_unlock_irqrestore(&sport->port.lock, flags);
1da177e4
LT		 657 return IRQ_HANDLED;
658}
659
7d12e780 660static irqreturn_t imx_rxint(int irq, void *dev_id)
1da177e4
LT		 661{
662 struct imx_port *sport = dev_id;
82313e66 663 unsigned int rx, flg, ignored = 0;
92a19f9c 664 struct tty_port *port = &sport->port.state->port;
ff4bfb21 665 unsigned long flags, temp;
1da177e4 666
82313e66 667 spin_lock_irqsave(&sport->port.lock, flags);
1da177e4 668
0d3c3938 669 while (readl(sport->port.membase + USR2) & USR2_RDR) {
1da177e4
LT		 670 flg = TTY_NORMAL;
671 sport->port.icount.rx++;
672
0d3c3938
SH		 673 rx = readl(sport->port.membase + URXD0);
674
ff4bfb21 675 temp = readl(sport->port.membase + USR2);
864eeed0 676 if (temp & USR2_BRCD) {
94d32f99 677 writel(USR2_BRCD, sport->port.membase + USR2);
864eeed0
SH		 678 if (uart_handle_break(&sport->port))
679 continue;
1da177e4
LT		 680 }
681
d3810cd4 682 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
864eeed0
SH		 683 continue;
684
019dc9ea
HW		 685 if (unlikely(rx & URXD_ERR)) {
686 if (rx & URXD_BRK)
687 sport->port.icount.brk++;
688 else if (rx & URXD_PRERR)
864eeed0
SH		 689 sport->port.icount.parity++;
690 else if (rx & URXD_FRMERR)
691 sport->port.icount.frame++;
692 if (rx & URXD_OVRRUN)
693 sport->port.icount.overrun++;
694
695 if (rx & sport->port.ignore_status_mask) {
696 if (++ignored > 100)
697 goto out;
698 continue;
699 }
700
701 rx &= sport->port.read_status_mask;
702
019dc9ea
HW		 703 if (rx & URXD_BRK)
704 flg = TTY_BREAK;
705 else if (rx & URXD_PRERR)
864eeed0
SH		 706 flg = TTY_PARITY;
707 else if (rx & URXD_FRMERR)
708 flg = TTY_FRAME;
709 if (rx & URXD_OVRRUN)
710 flg = TTY_OVERRUN;
1da177e4 711
864eeed0
SH		 712#ifdef SUPPORT_SYSRQ
713 sport->port.sysrq = 0;
714#endif
715 }
1da177e4 716
92a19f9c 717 tty_insert_flip_char(port, rx, flg);
864eeed0 718 }
1da177e4
LT		 719
720out:
82313e66 721 spin_unlock_irqrestore(&sport->port.lock, flags);
2e124b4a 722 tty_flip_buffer_push(port);
1da177e4 723 return IRQ_HANDLED;
1da177e4
LT		 724}
725
7cb92fd2 726static int start_rx_dma(struct imx_port *sport);
b4cdc8f6
HS		 727/*
728 * If the RXFIFO is filled with some data, and then we
729 * arise a DMA operation to receive them.
730 */
731static void imx_dma_rxint(struct imx_port *sport)
732{
733 unsigned long temp;
734
735 temp = readl(sport->port.membase + USR2);
736 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
737 sport->dma_is_rxing = 1;
738
739 /* disable the `Recerver Ready Interrrupt` */
740 temp = readl(sport->port.membase + UCR1);
741 temp &= ~(UCR1_RRDYEN);
742 writel(temp, sport->port.membase + UCR1);
743
744 /* tell the DMA to receive the data. */
7cb92fd2 745 start_rx_dma(sport);
b4cdc8f6
HS		 746 }
747}
748
e3d13ff4
SH		 749static irqreturn_t imx_int(int irq, void *dev_id)
750{
751 struct imx_port *sport = dev_id;
752 unsigned int sts;
f1f836e4 753 unsigned int sts2;
e3d13ff4
SH		 754
755 sts = readl(sport->port.membase + USR1);
756
b4cdc8f6
HS		 757 if (sts & USR1_RRDY) {
758 if (sport->dma_is_enabled)
759 imx_dma_rxint(sport);
760 else
761 imx_rxint(irq, dev_id);
762 }
e3d13ff4
SH		 763
764 if (sts & USR1_TRDY &&
765 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
766 imx_txint(irq, dev_id);
767
9fbe6044 768 if (sts & USR1_RTSD)
e3d13ff4
SH		 769 imx_rtsint(irq, dev_id);
770
db1a9b55
FE		 771 if (sts & USR1_AWAKE)
772 writel(USR1_AWAKE, sport->port.membase + USR1);
773
f1f836e4
AS		 774 sts2 = readl(sport->port.membase + USR2);
775 if (sts2 & USR2_ORE) {
776 dev_err(sport->port.dev, "Rx FIFO overrun\n");
777 sport->port.icount.overrun++;
778 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
779 }
780
e3d13ff4
SH		 781 return IRQ_HANDLED;
782}
783
1da177e4
LT		 784/*
785 * Return TIOCSER_TEMT when transmitter is not busy.
786 */
787static unsigned int imx_tx_empty(struct uart_port *port)
788{
789 struct imx_port *sport = (struct imx_port *)port;
1ce43e58 790 unsigned int ret;
1da177e4 791
1ce43e58 792 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1da177e4 793
1ce43e58
HS		 794 /* If the TX DMA is working, return 0. */
795 if (sport->dma_is_enabled && sport->dma_is_txing)
796 ret = 0;
797
798 return ret;
1da177e4
LT		 799}
800
0f302dc3
SH		 801/*
802 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
803 */
1da177e4
LT		 804static unsigned int imx_get_mctrl(struct uart_port *port)
805{
d3810cd4
OS		 806 struct imx_port *sport = (struct imx_port *)port;
807 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
0f302dc3 808
d3810cd4
OS		 809 if (readl(sport->port.membase + USR1) & USR1_RTSS)
810 tmp |= TIOCM_CTS;
0f302dc3 811
d3810cd4
OS		 812 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
813 tmp |= TIOCM_RTS;
0f302dc3 814
6b471a98
HS		 815 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
816 tmp |= TIOCM_LOOP;
817
d3810cd4 818 return tmp;
1da177e4
LT		 819}
820
821static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
822{
d3810cd4 823 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 824 unsigned long temp;
825
826 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
0f302dc3 827
d3810cd4 828 if (mctrl & TIOCM_RTS)
b4cdc8f6
HS		 829 if (!sport->dma_is_enabled)
830 temp |= UCR2_CTS;
ff4bfb21
SH		 831
832 writel(temp, sport->port.membase + UCR2);
6b471a98
HS		 833
834 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
835 if (mctrl & TIOCM_LOOP)
836 temp |= UTS_LOOP;
837 writel(temp, sport->port.membase + uts_reg(sport));
1da177e4
LT		 838}
839
840/*
841 * Interrupts always disabled.
842 */
843static void imx_break_ctl(struct uart_port *port, int break_state)
844{
845 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 846 unsigned long flags, temp;
1da177e4
LT		 847
848 spin_lock_irqsave(&sport->port.lock, flags);
849
ff4bfb21
SH		 850 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
851
82313e66 852 if (break_state != 0)
ff4bfb21
SH		 853 temp |= UCR1_SNDBRK;
854
855 writel(temp, sport->port.membase + UCR1);
1da177e4
LT		 856
857 spin_unlock_irqrestore(&sport->port.lock, flags);
858}
859
860#define TXTL 2 /* reset default */
861#define RXTL 1 /* reset default */
862
587897f5
SH		 863static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
864{
865 unsigned int val;
587897f5 866
7be0670f
DB		 867 /* set receiver / transmitter trigger level */
868 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
869 val |= TXTL << UFCR_TXTL_SHF | RXTL;
ff4bfb21 870 writel(val, sport->port.membase + UFCR);
587897f5
SH		 871 return 0;
872}
873
b4cdc8f6 874#define RX_BUF_SIZE (PAGE_SIZE)
b4cdc8f6
HS		 875static void imx_rx_dma_done(struct imx_port *sport)
876{
877 unsigned long temp;
878
879 /* Enable this interrupt when the RXFIFO is empty. */
880 temp = readl(sport->port.membase + UCR1);
881 temp |= UCR1_RRDYEN;
882 writel(temp, sport->port.membase + UCR1);
883
884 sport->dma_is_rxing = 0;
9ce4f8f3
GKH		 885
886 /* Is the shutdown waiting for us? */
887 if (waitqueue_active(&sport->dma_wait))
888 wake_up(&sport->dma_wait);
b4cdc8f6
HS		 889}
890
891/*
892 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
893 * [1] the RX DMA buffer is full.
894 * [2] the Aging timer expires(wait for 8 bytes long)
895 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
896 *
897 * The [2] is trigger when a character was been sitting in the FIFO
898 * meanwhile [3] can wait for 32 bytes long when the RX line is
899 * on IDLE state and RxFIFO is empty.
900 */
901static void dma_rx_callback(void *data)
902{
903 struct imx_port *sport = data;
904 struct dma_chan *chan = sport->dma_chan_rx;
905 struct scatterlist *sgl = &sport->rx_sgl;
7cb92fd2 906 struct tty_port *port = &sport->port.state->port;
b4cdc8f6
HS		 907 struct dma_tx_state state;
908 enum dma_status status;
909 unsigned int count;
910
911 /* unmap it first */
912 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
913
f0ef8834 914 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
b4cdc8f6
HS		 915 count = RX_BUF_SIZE - state.residue;
916 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
917
918 if (count) {
7cb92fd2
HS		 919 tty_insert_flip_string(port, sport->rx_buf, count);
920 tty_flip_buffer_push(port);
921
922 start_rx_dma(sport);
b4cdc8f6
HS		 923 } else
924 imx_rx_dma_done(sport);
925}
926
927static int start_rx_dma(struct imx_port *sport)
928{
929 struct scatterlist *sgl = &sport->rx_sgl;
930 struct dma_chan *chan = sport->dma_chan_rx;
931 struct device *dev = sport->port.dev;
932 struct dma_async_tx_descriptor *desc;
933 int ret;
934
935 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
936 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
937 if (ret == 0) {
938 dev_err(dev, "DMA mapping error for RX.\n");
939 return -EINVAL;
940 }
941 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
942 DMA_PREP_INTERRUPT);
943 if (!desc) {
944 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
945 return -EINVAL;
946 }
947 desc->callback = dma_rx_callback;
948 desc->callback_param = sport;
949
950 dev_dbg(dev, "RX: prepare for the DMA.\n");
951 dmaengine_submit(desc);
952 dma_async_issue_pending(chan);
953 return 0;
954}
955
956static void imx_uart_dma_exit(struct imx_port *sport)
957{
958 if (sport->dma_chan_rx) {
959 dma_release_channel(sport->dma_chan_rx);
960 sport->dma_chan_rx = NULL;
961
962 kfree(sport->rx_buf);
963 sport->rx_buf = NULL;
964 }
965
966 if (sport->dma_chan_tx) {
967 dma_release_channel(sport->dma_chan_tx);
968 sport->dma_chan_tx = NULL;
969 }
970
971 sport->dma_is_inited = 0;
972}
973
974static int imx_uart_dma_init(struct imx_port *sport)
975{
b09c74ae 976 struct dma_slave_config slave_config = {};
b4cdc8f6
HS		 977 struct device *dev = sport->port.dev;
978 int ret;
979
980 /* Prepare for RX : */
981 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
982 if (!sport->dma_chan_rx) {
983 dev_dbg(dev, "cannot get the DMA channel.\n");
984 ret = -EINVAL;
985 goto err;
986 }
987
988 slave_config.direction = DMA_DEV_TO_MEM;
989 slave_config.src_addr = sport->port.mapbase + URXD0;
990 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
991 slave_config.src_maxburst = RXTL;
992 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
993 if (ret) {
994 dev_err(dev, "error in RX dma configuration.\n");
995 goto err;
996 }
997
998 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
999 if (!sport->rx_buf) {
1000 dev_err(dev, "cannot alloc DMA buffer.\n");
1001 ret = -ENOMEM;
1002 goto err;
1003 }
b4cdc8f6
HS		 1004
1005 /* Prepare for TX : */
1006 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1007 if (!sport->dma_chan_tx) {
1008 dev_err(dev, "cannot get the TX DMA channel!\n");
1009 ret = -EINVAL;
1010 goto err;
1011 }
1012
1013 slave_config.direction = DMA_MEM_TO_DEV;
1014 slave_config.dst_addr = sport->port.mapbase + URTX0;
1015 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1016 slave_config.dst_maxburst = TXTL;
1017 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1018 if (ret) {
1019 dev_err(dev, "error in TX dma configuration.");
1020 goto err;
1021 }
1022
1023 sport->dma_is_inited = 1;
1024
1025 return 0;
1026err:
1027 imx_uart_dma_exit(sport);
1028 return ret;
1029}
1030
1031static void imx_enable_dma(struct imx_port *sport)
1032{
1033 unsigned long temp;
b4cdc8f6 1034
9ce4f8f3
GKH		 1035 init_waitqueue_head(&sport->dma_wait);
1036
b4cdc8f6
HS		 1037 /* set UCR1 */
1038 temp = readl(sport->port.membase + UCR1);
1039 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1040 /* wait for 32 idle frames for IDDMA interrupt */
1041 UCR1_ICD_REG(3);
1042 writel(temp, sport->port.membase + UCR1);
1043
1044 /* set UCR4 */
1045 temp = readl(sport->port.membase + UCR4);
1046 temp |= UCR4_IDDMAEN;
1047 writel(temp, sport->port.membase + UCR4);
1048
1049 sport->dma_is_enabled = 1;
1050}
1051
1052static void imx_disable_dma(struct imx_port *sport)
1053{
1054 unsigned long temp;
b4cdc8f6
HS		 1055
1056 /* clear UCR1 */
1057 temp = readl(sport->port.membase + UCR1);
1058 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1059 writel(temp, sport->port.membase + UCR1);
1060
1061 /* clear UCR2 */
1062 temp = readl(sport->port.membase + UCR2);
1063 temp &= ~(UCR2_CTSC | UCR2_CTS);
1064 writel(temp, sport->port.membase + UCR2);
1065
1066 /* clear UCR4 */
1067 temp = readl(sport->port.membase + UCR4);
1068 temp &= ~UCR4_IDDMAEN;
1069 writel(temp, sport->port.membase + UCR4);
1070
1071 sport->dma_is_enabled = 0;
b4cdc8f6
HS		 1072}
1073
1c5250d6
VL		 1074/* half the RX buffer size */
1075#define CTSTL 16
1076
1da177e4
LT		 1077static int imx_startup(struct uart_port *port)
1078{
1079 struct imx_port *sport = (struct imx_port *)port;
772f8991 1080 int retval, i;
ff4bfb21 1081 unsigned long flags, temp;
1da177e4 1082
1cf93e0d
HS		 1083 retval = clk_prepare_enable(sport->clk_per);
1084 if (retval)
1085 goto error_out1;
1086 retval = clk_prepare_enable(sport->clk_ipg);
1087 if (retval) {
1088 clk_disable_unprepare(sport->clk_per);
1089 goto error_out1;
0c375501 1090 }
28eb4274 1091
587897f5 1092 imx_setup_ufcr(sport, 0);
1da177e4
LT		 1093
1094 /* disable the DREN bit (Data Ready interrupt enable) before
1095 * requesting IRQs
1096 */
ff4bfb21 1097 temp = readl(sport->port.membase + UCR4);
b6e49138
FG		 1098
1099 if (USE_IRDA(sport))
1100 temp |= UCR4_IRSC;
1101
1c5250d6 1102 /* set the trigger level for CTS */
82313e66
SK		 1103 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1104 temp |= CTSTL << UCR4_CTSTL_SHF;
1c5250d6 1105
ff4bfb21 1106 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1da177e4 1107
772f8991
HS		 1108 /* Reset fifo's and state machines */
1109 i = 100;
1110
1111 temp = readl(sport->port.membase + UCR2);
1112 temp &= ~UCR2_SRST;
1113 writel(temp, sport->port.membase + UCR2);
1114
1115 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1116 udelay(1);
b6e49138 1117
1da177e4 1118 /*
e3d13ff4
SH		 1119 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1120 * chips only have one interrupt.
1da177e4 1121 */
e3d13ff4
SH		 1122 if (sport->txirq > 0) {
1123 retval = request_irq(sport->rxirq, imx_rxint, 0,
436e4ab5 1124 dev_name(port->dev), sport);
e3d13ff4
SH		 1125 if (retval)
1126 goto error_out1;
1127
1128 retval = request_irq(sport->txirq, imx_txint, 0,
436e4ab5 1129 dev_name(port->dev), sport);
e3d13ff4
SH		 1130 if (retval)
1131 goto error_out2;
1132
b6e49138
FG		 1133 /* do not use RTS IRQ on IrDA */
1134 if (!USE_IRDA(sport)) {
1ee8f65b 1135 retval = request_irq(sport->rtsirq, imx_rtsint, 0,
436e4ab5 1136 dev_name(port->dev), sport);
b6e49138
FG		 1137 if (retval)
1138 goto error_out3;
1139 }
e3d13ff4
SH		 1140 } else {
1141 retval = request_irq(sport->port.irq, imx_int, 0,
436e4ab5 1142 dev_name(port->dev), sport);
e3d13ff4
SH		 1143 if (retval) {
1144 free_irq(sport->port.irq, sport);
1145 goto error_out1;
1146 }
1147 }
ceca629e 1148
9ec1882d 1149 spin_lock_irqsave(&sport->port.lock, flags);
1da177e4
LT		 1150 /*
1151 * Finally, clear and enable interrupts
1152 */
ff4bfb21
SH		 1153 writel(USR1_RTSD, sport->port.membase + USR1);
1154
1155 temp = readl(sport->port.membase + UCR1);
789d5258 1156 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
b6e49138
FG		 1157
1158 if (USE_IRDA(sport)) {
1159 temp |= UCR1_IREN;
1160 temp &= ~(UCR1_RTSDEN);
1161 }
1162
ff4bfb21 1163 writel(temp, sport->port.membase + UCR1);
1da177e4 1164
ff4bfb21
SH		 1165 temp = readl(sport->port.membase + UCR2);
1166 temp |= (UCR2_RXEN | UCR2_TXEN);
bff09b09
LS		 1167 if (!sport->have_rtscts)
1168 temp |= UCR2_IRTS;
ff4bfb21 1169 writel(temp, sport->port.membase + UCR2);
1da177e4 1170
a496e628 1171 if (!is_imx1_uart(sport)) {
37d6fb62 1172 temp = readl(sport->port.membase + UCR3);
b38cb7d2 1173 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
37d6fb62
SH		 1174 writel(temp, sport->port.membase + UCR3);
1175 }
4411805b 1176
b6e49138
FG		 1177 if (USE_IRDA(sport)) {
1178 temp = readl(sport->port.membase + UCR4);
1179 if (sport->irda_inv_rx)
1180 temp |= UCR4_INVR;
1181 else
1182 temp &= ~(UCR4_INVR);
1183 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
1184
1185 temp = readl(sport->port.membase + UCR3);
1186 if (sport->irda_inv_tx)
1187 temp |= UCR3_INVT;
1188 else
1189 temp &= ~(UCR3_INVT);
1190 writel(temp, sport->port.membase + UCR3);
1191 }
1192
1da177e4
LT		 1193 /*
1194 * Enable modem status interrupts
1195 */
1da177e4 1196 imx_enable_ms(&sport->port);
82313e66 1197 spin_unlock_irqrestore(&sport->port.lock, flags);
1da177e4 1198
b6e49138
FG		 1199 if (USE_IRDA(sport)) {
1200 struct imxuart_platform_data *pdata;
574de559 1201 pdata = dev_get_platdata(sport->port.dev);
b6e49138
FG		 1202 sport->irda_inv_rx = pdata->irda_inv_rx;
1203 sport->irda_inv_tx = pdata->irda_inv_tx;
1204 sport->trcv_delay = pdata->transceiver_delay;
1205 if (pdata->irda_enable)
1206 pdata->irda_enable(1);
1207 }
1208
1da177e4
LT		 1209 return 0;
1210
ceca629e 1211error_out3:
e3d13ff4
SH		 1212 if (sport->txirq)
1213 free_irq(sport->txirq, sport);
1da177e4 1214error_out2:
e3d13ff4
SH		 1215 if (sport->rxirq)
1216 free_irq(sport->rxirq, sport);
86371d07 1217error_out1:
1da177e4
LT		 1218 return retval;
1219}
1220
1221static void imx_shutdown(struct uart_port *port)
1222{
1223 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 1224 unsigned long temp;
9ec1882d 1225 unsigned long flags;
1da177e4 1226
b4cdc8f6 1227 if (sport->dma_is_enabled) {
9ce4f8f3
GKH		 1228 /* We have to wait for the DMA to finish. */
1229 wait_event(sport->dma_wait,
1230 !sport->dma_is_rxing && !sport->dma_is_txing);
b4cdc8f6
HS		 1231 imx_stop_rx(port);
1232 imx_disable_dma(sport);
1233 imx_uart_dma_exit(sport);
1234 }
1235
9ec1882d 1236 spin_lock_irqsave(&sport->port.lock, flags);
2e146392
FG		 1237 temp = readl(sport->port.membase + UCR2);
1238 temp &= ~(UCR2_TXEN);
1239 writel(temp, sport->port.membase + UCR2);
9ec1882d 1240 spin_unlock_irqrestore(&sport->port.lock, flags);
2e146392 1241
b6e49138
FG		 1242 if (USE_IRDA(sport)) {
1243 struct imxuart_platform_data *pdata;
574de559 1244 pdata = dev_get_platdata(sport->port.dev);
b6e49138
FG		 1245 if (pdata->irda_enable)
1246 pdata->irda_enable(0);
1247 }
1248
1da177e4
LT		 1249 /*
1250 * Stop our timer.
1251 */
1252 del_timer_sync(&sport->timer);
1253
1254 /*
1255 * Free the interrupts
1256 */
e3d13ff4 1257 if (sport->txirq > 0) {
b6e49138
FG		 1258 if (!USE_IRDA(sport))
1259 free_irq(sport->rtsirq, sport);
e3d13ff4
SH		 1260 free_irq(sport->txirq, sport);
1261 free_irq(sport->rxirq, sport);
1262 } else
1263 free_irq(sport->port.irq, sport);
1da177e4
LT		 1264
1265 /*
1266 * Disable all interrupts, port and break condition.
1267 */
1268
9ec1882d 1269 spin_lock_irqsave(&sport->port.lock, flags);
ff4bfb21
SH		 1270 temp = readl(sport->port.membase + UCR1);
1271 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
b6e49138
FG		 1272 if (USE_IRDA(sport))
1273 temp &= ~(UCR1_IREN);
1274
ff4bfb21 1275 writel(temp, sport->port.membase + UCR1);
9ec1882d 1276 spin_unlock_irqrestore(&sport->port.lock, flags);
28eb4274 1277
1cf93e0d
HS		 1278 clk_disable_unprepare(sport->clk_per);
1279 clk_disable_unprepare(sport->clk_ipg);
1da177e4
LT		 1280}
1281
eb56b7ed
HS		 1282static void imx_flush_buffer(struct uart_port *port)
1283{
1284 struct imx_port *sport = (struct imx_port *)port;
1285
1286 if (sport->dma_is_enabled) {
1287 sport->tx_bytes = 0;
1288 dmaengine_terminate_all(sport->dma_chan_tx);
1289 }
1290}
1291
1da177e4 1292static void
606d099c
AC		 1293imx_set_termios(struct uart_port *port, struct ktermios *termios,
1294 struct ktermios *old)
1da177e4
LT		 1295{
1296 struct imx_port *sport = (struct imx_port *)port;
1297 unsigned long flags;
1298 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1299 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
534fca06
OS		 1300 unsigned int div, ufcr;
1301 unsigned long num, denom;
d7f8d437 1302 uint64_t tdiv64;
1da177e4
LT		 1303
1304 /*
1305 * If we don't support modem control lines, don't allow
1306 * these to be set.
1307 */
1308 if (0) {
1309 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
1310 termios->c_cflag |= CLOCAL;
1311 }
1312
1313 /*
1314 * We only support CS7 and CS8.
1315 */
1316 while ((termios->c_cflag & CSIZE) != CS7 &&
1317 (termios->c_cflag & CSIZE) != CS8) {
1318 termios->c_cflag &= ~CSIZE;
1319 termios->c_cflag |= old_csize;
1320 old_csize = CS8;
1321 }
1322
1323 if ((termios->c_cflag & CSIZE) == CS8)
1324 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1325 else
1326 ucr2 = UCR2_SRST | UCR2_IRTS;
1327
1328 if (termios->c_cflag & CRTSCTS) {
82313e66 1329 if (sport->have_rtscts) {
5b802344
SH		 1330 ucr2 &= ~UCR2_IRTS;
1331 ucr2 |= UCR2_CTSC;
b4cdc8f6
HS		 1332
1333 /* Can we enable the DMA support? */
1334 if (is_imx6q_uart(sport) && !uart_console(port)
1335 && !sport->dma_is_inited)
1336 imx_uart_dma_init(sport);
5b802344
SH		 1337 } else {
1338 termios->c_cflag &= ~CRTSCTS;
1339 }
1da177e4
LT		 1340 }
1341
1342 if (termios->c_cflag & CSTOPB)
1343 ucr2 |= UCR2_STPB;
1344 if (termios->c_cflag & PARENB) {
1345 ucr2 |= UCR2_PREN;
3261e362 1346 if (termios->c_cflag & PARODD)
1da177e4
LT		 1347 ucr2 |= UCR2_PROE;
1348 }
1349
995234da
EM		 1350 del_timer_sync(&sport->timer);
1351
1da177e4
LT		 1352 /*
1353 * Ask the core to calculate the divisor for us.
1354 */
036bb15e 1355 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1da177e4
LT		 1356 quot = uart_get_divisor(port, baud);
1357
1358 spin_lock_irqsave(&sport->port.lock, flags);
1359
1360 sport->port.read_status_mask = 0;
1361 if (termios->c_iflag & INPCK)
1362 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1363 if (termios->c_iflag & (BRKINT | PARMRK))
1364 sport->port.read_status_mask |= URXD_BRK;
1365
1366 /*
1367 * Characters to ignore
1368 */
1369 sport->port.ignore_status_mask = 0;
1370 if (termios->c_iflag & IGNPAR)
1371 sport->port.ignore_status_mask |= URXD_PRERR;
1372 if (termios->c_iflag & IGNBRK) {
1373 sport->port.ignore_status_mask |= URXD_BRK;
1374 /*
1375 * If we're ignoring parity and break indicators,
1376 * ignore overruns too (for real raw support).
1377 */
1378 if (termios->c_iflag & IGNPAR)
1379 sport->port.ignore_status_mask |= URXD_OVRRUN;
1380 }
1381
1da177e4
LT		 1382 /*
1383 * Update the per-port timeout.
1384 */
1385 uart_update_timeout(port, termios->c_cflag, baud);
1386
1387 /*
1388 * disable interrupts and drain transmitter
1389 */
ff4bfb21
SH		 1390 old_ucr1 = readl(sport->port.membase + UCR1);
1391 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1392 sport->port.membase + UCR1);
1da177e4 1393
82313e66 1394 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1da177e4
LT		 1395 barrier();
1396
1397 /* then, disable everything */
ff4bfb21 1398 old_txrxen = readl(sport->port.membase + UCR2);
82313e66 1399 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
ff4bfb21
SH		 1400 sport->port.membase + UCR2);
1401 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1da177e4 1402
b6e49138
FG		 1403 if (USE_IRDA(sport)) {
1404 /*
1405 * use maximum available submodule frequency to
1406 * avoid missing short pulses due to low sampling rate
1407 */
036bb15e 1408 div = 1;
b6e49138 1409 } else {
09bd00f6
HF		 1410 /* custom-baudrate handling */
1411 div = sport->port.uartclk / (baud * 16);
1412 if (baud == 38400 && quot != div)
1413 baud = sport->port.uartclk / (quot * 16);
1414
b6e49138
FG		 1415 div = sport->port.uartclk / (baud * 16);
1416 if (div > 7)
1417 div = 7;
1418 if (!div)
1419 div = 1;
1420 }
036bb15e 1421
534fca06
OS		 1422 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1423 1 << 16, 1 << 16, &num, &denom);
036bb15e 1424
eab4f5af
AC		 1425 tdiv64 = sport->port.uartclk;
1426 tdiv64 *= num;
1427 do_div(tdiv64, denom * 16 * div);
1428 tty_termios_encode_baud_rate(termios,
1a2c4b31 1429 (speed_t)tdiv64, (speed_t)tdiv64);
d7f8d437 1430
534fca06
OS		 1431 num -= 1;
1432 denom -= 1;
036bb15e
SH		 1433
1434 ufcr = readl(sport->port.membase + UFCR);
b6e49138 1435 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
20ff2fe6
HS		 1436 if (sport->dte_mode)
1437 ufcr |= UFCR_DCEDTE;
036bb15e
SH		 1438 writel(ufcr, sport->port.membase + UFCR);
1439
534fca06
OS		 1440 writel(num, sport->port.membase + UBIR);
1441 writel(denom, sport->port.membase + UBMR);
1442
a496e628 1443 if (!is_imx1_uart(sport))
37d6fb62 1444 writel(sport->port.uartclk / div / 1000,
fe6b540a 1445 sport->port.membase + IMX21_ONEMS);
ff4bfb21
SH		 1446
1447 writel(old_ucr1, sport->port.membase + UCR1);
1da177e4 1448
ff4bfb21
SH		 1449 /* set the parity, stop bits and data size */
1450 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1da177e4
LT		 1451
1452 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1453 imx_enable_ms(&sport->port);
1454
b4cdc8f6
HS		 1455 if (sport->dma_is_inited && !sport->dma_is_enabled)
1456 imx_enable_dma(sport);
1da177e4
LT		 1457 spin_unlock_irqrestore(&sport->port.lock, flags);
1458}
1459
1460static const char *imx_type(struct uart_port *port)
1461{
1462 struct imx_port *sport = (struct imx_port *)port;
1463
1464 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1465}
1466
1da177e4
LT		 1467/*
1468 * Configure/autoconfigure the port.
1469 */
1470static void imx_config_port(struct uart_port *port, int flags)
1471{
1472 struct imx_port *sport = (struct imx_port *)port;
1473
da82f997 1474 if (flags & UART_CONFIG_TYPE)
1da177e4
LT		 1475 sport->port.type = PORT_IMX;
1476}
1477
1478/*
1479 * Verify the new serial_struct (for TIOCSSERIAL).
1480 * The only change we allow are to the flags and type, and
1481 * even then only between PORT_IMX and PORT_UNKNOWN
1482 */
1483static int
1484imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1485{
1486 struct imx_port *sport = (struct imx_port *)port;
1487 int ret = 0;
1488
1489 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1490 ret = -EINVAL;
1491 if (sport->port.irq != ser->irq)
1492 ret = -EINVAL;
1493 if (ser->io_type != UPIO_MEM)
1494 ret = -EINVAL;
1495 if (sport->port.uartclk / 16 != ser->baud_base)
1496 ret = -EINVAL;
a50c44ce 1497 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1da177e4
LT		 1498 ret = -EINVAL;
1499 if (sport->port.iobase != ser->port)
1500 ret = -EINVAL;
1501 if (ser->hub6 != 0)
1502 ret = -EINVAL;
1503 return ret;
1504}
1505
01f56abd
SA		 1506#if defined(CONFIG_CONSOLE_POLL)
1507static int imx_poll_get_char(struct uart_port *port)
1508{
1509 struct imx_port_ucrs old_ucr;
1510 unsigned int status;
1511 unsigned char c;
1512
1513 /* save control registers */
1514 imx_port_ucrs_save(port, &old_ucr);
1515
1516 /* disable interrupts */
1517 writel(UCR1_UARTEN, port->membase + UCR1);
1518 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1519 port->membase + UCR2);
1520 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1521 port->membase + UCR3);
1522
1523 /* poll */
1524 do {
1525 status = readl(port->membase + USR2);
1526 } while (~status & USR2_RDR);
1527
1528 /* read */
1529 c = readl(port->membase + URXD0);
1530
1531 /* restore control registers */
1532 imx_port_ucrs_restore(port, &old_ucr);
1533
1534 return c;
1535}
1536
1537static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1538{
1539 struct imx_port_ucrs old_ucr;
1540 unsigned int status;
1541
1542 /* save control registers */
1543 imx_port_ucrs_save(port, &old_ucr);
1544
1545 /* disable interrupts */
1546 writel(UCR1_UARTEN, port->membase + UCR1);
1547 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1548 port->membase + UCR2);
1549 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1550 port->membase + UCR3);
1551
1552 /* drain */
1553 do {
1554 status = readl(port->membase + USR1);
1555 } while (~status & USR1_TRDY);
1556
1557 /* write */
1558 writel(c, port->membase + URTX0);
1559
1560 /* flush */
1561 do {
1562 status = readl(port->membase + USR2);
1563 } while (~status & USR2_TXDC);
1564
1565 /* restore control registers */
1566 imx_port_ucrs_restore(port, &old_ucr);
1567}
1568#endif
1569
1da177e4
LT		 1570static struct uart_ops imx_pops = {
1571 .tx_empty = imx_tx_empty,
1572 .set_mctrl = imx_set_mctrl,
1573 .get_mctrl = imx_get_mctrl,
1574 .stop_tx = imx_stop_tx,
1575 .start_tx = imx_start_tx,
1576 .stop_rx = imx_stop_rx,
1577 .enable_ms = imx_enable_ms,
1578 .break_ctl = imx_break_ctl,
1579 .startup = imx_startup,
1580 .shutdown = imx_shutdown,
eb56b7ed 1581 .flush_buffer = imx_flush_buffer,
1da177e4
LT		 1582 .set_termios = imx_set_termios,
1583 .type = imx_type,
1da177e4
LT		 1584 .config_port = imx_config_port,
1585 .verify_port = imx_verify_port,
01f56abd
SA		 1586#if defined(CONFIG_CONSOLE_POLL)
1587 .poll_get_char = imx_poll_get_char,
1588 .poll_put_char = imx_poll_put_char,
1589#endif
1da177e4
LT		 1590};
1591
dbff4e9e 1592static struct imx_port *imx_ports[UART_NR];
1da177e4
LT		 1593
1594#ifdef CONFIG_SERIAL_IMX_CONSOLE
d358788f
RK		 1595static void imx_console_putchar(struct uart_port *port, int ch)
1596{
1597 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 1598
fe6b540a 1599 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
d358788f 1600 barrier();
ff4bfb21
SH		 1601
1602 writel(ch, sport->port.membase + URTX0);
d358788f 1603}
1da177e4
LT		 1604
1605/*
1606 * Interrupts are disabled on entering
1607 */
1608static void
1609imx_console_write(struct console *co, const char *s, unsigned int count)
1610{
dbff4e9e 1611 struct imx_port *sport = imx_ports[co->index];
0ad5a814
DB		 1612 struct imx_port_ucrs old_ucr;
1613 unsigned int ucr1;
f30e8260 1614 unsigned long flags = 0;
677fe555 1615 int locked = 1;
1cf93e0d
HS		 1616 int retval;
1617
1618 retval = clk_enable(sport->clk_per);
1619 if (retval)
1620 return;
1621 retval = clk_enable(sport->clk_ipg);
1622 if (retval) {
1623 clk_disable(sport->clk_per);
1624 return;
1625 }
9ec1882d 1626
677fe555
TG		 1627 if (sport->port.sysrq)
1628 locked = 0;
1629 else if (oops_in_progress)
1630 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1631 else
1632 spin_lock_irqsave(&sport->port.lock, flags);
1da177e4
LT		 1633
1634 /*
0ad5a814 1635 * First, save UCR1/2/3 and then disable interrupts
1da177e4 1636 */
0ad5a814
DB		 1637 imx_port_ucrs_save(&sport->port, &old_ucr);
1638 ucr1 = old_ucr.ucr1;
1da177e4 1639
fe6b540a
SG		 1640 if (is_imx1_uart(sport))
1641 ucr1 |= IMX1_UCR1_UARTCLKEN;
37d6fb62
SH		 1642 ucr1 |= UCR1_UARTEN;
1643 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1644
1645 writel(ucr1, sport->port.membase + UCR1);
ff4bfb21 1646
0ad5a814 1647 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1da177e4 1648
d358788f 1649 uart_console_write(&sport->port, s, count, imx_console_putchar);
1da177e4
LT		 1650
1651 /*
1652 * Finally, wait for transmitter to become empty
0ad5a814 1653 * and restore UCR1/2/3
1da177e4 1654 */
ff4bfb21 1655 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1da177e4 1656
0ad5a814 1657 imx_port_ucrs_restore(&sport->port, &old_ucr);
9ec1882d 1658
677fe555
TG		 1659 if (locked)
1660 spin_unlock_irqrestore(&sport->port.lock, flags);
1cf93e0d
HS		 1661
1662 clk_disable(sport->clk_ipg);
1663 clk_disable(sport->clk_per);
1da177e4
LT		 1664}
1665
1666/*
1667 * If the port was already initialised (eg, by a boot loader),
1668 * try to determine the current setup.
1669 */
1670static void __init
1671imx_console_get_options(struct imx_port *sport, int *baud,
1672 int *parity, int *bits)
1673{
587897f5 1674
2e2eb509 1675 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1da177e4 1676 /* ok, the port was enabled */
82313e66 1677 unsigned int ucr2, ubir, ubmr, uartclk;
587897f5
SH		 1678 unsigned int baud_raw;
1679 unsigned int ucfr_rfdiv;
1da177e4 1680
ff4bfb21 1681 ucr2 = readl(sport->port.membase + UCR2);
1da177e4
LT		 1682
1683 *parity = 'n';
1684 if (ucr2 & UCR2_PREN) {
1685 if (ucr2 & UCR2_PROE)
1686 *parity = 'o';
1687 else
1688 *parity = 'e';
1689 }
1690
1691 if (ucr2 & UCR2_WS)
1692 *bits = 8;
1693 else
1694 *bits = 7;
1695
ff4bfb21
SH		 1696 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1697 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
587897f5 1698
ff4bfb21 1699 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
587897f5
SH		 1700 if (ucfr_rfdiv == 6)
1701 ucfr_rfdiv = 7;
1702 else
1703 ucfr_rfdiv = 6 - ucfr_rfdiv;
1704
3a9465fa 1705 uartclk = clk_get_rate(sport->clk_per);
587897f5
SH		 1706 uartclk /= ucfr_rfdiv;
1707
1708 { /*
1709 * The next code provides exact computation of
1710 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1711 * without need of float support or long long division,
1712 * which would be required to prevent 32bit arithmetic overflow
1713 */
1714 unsigned int mul = ubir + 1;
1715 unsigned int div = 16 * (ubmr + 1);
1716 unsigned int rem = uartclk % div;
1717
1718 baud_raw = (uartclk / div) * mul;
1719 baud_raw += (rem * mul + div / 2) / div;
1720 *baud = (baud_raw + 50) / 100 * 100;
1721 }
1722
82313e66 1723 if (*baud != baud_raw)
50bbdba3 1724 pr_info("Console IMX rounded baud rate from %d to %d\n",
587897f5 1725 baud_raw, *baud);
1da177e4
LT		 1726 }
1727}
1728
1729static int __init
1730imx_console_setup(struct console *co, char *options)
1731{
1732 struct imx_port *sport;
1733 int baud = 9600;
1734 int bits = 8;
1735 int parity = 'n';
1736 int flow = 'n';
1cf93e0d 1737 int retval;
1da177e4
LT		 1738
1739 /*
1740 * Check whether an invalid uart number has been specified, and
1741 * if so, search for the first available port that does have
1742 * console support.
1743 */
1744 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1745 co->index = 0;
dbff4e9e 1746 sport = imx_ports[co->index];
82313e66 1747 if (sport == NULL)
e76afc4e 1748 return -ENODEV;
1da177e4 1749
1cf93e0d
HS		 1750 /* For setting the registers, we only need to enable the ipg clock. */
1751 retval = clk_prepare_enable(sport->clk_ipg);
1752 if (retval)
1753 goto error_console;
1754
1da177e4
LT		 1755 if (options)
1756 uart_parse_options(options, &baud, &parity, &bits, &flow);
1757 else
1758 imx_console_get_options(sport, &baud, &parity, &bits);
1759
587897f5
SH		 1760 imx_setup_ufcr(sport, 0);
1761
1cf93e0d
HS		 1762 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1763
1764 clk_disable(sport->clk_ipg);
1765 if (retval) {
1766 clk_unprepare(sport->clk_ipg);
1767 goto error_console;
1768 }
1769
1770 retval = clk_prepare(sport->clk_per);
1771 if (retval)
1772 clk_disable_unprepare(sport->clk_ipg);
1773
1774error_console:
1775 return retval;
1da177e4
LT		 1776}
1777
9f4426dd 1778static struct uart_driver imx_reg;
1da177e4 1779static struct console imx_console = {
e3d13ff4 1780 .name = DEV_NAME,
1da177e4
LT		 1781 .write = imx_console_write,
1782 .device = uart_console_device,
1783 .setup = imx_console_setup,
1784 .flags = CON_PRINTBUFFER,
1785 .index = -1,
1786 .data = &imx_reg,
1787};
1788
1da177e4
LT		 1789#define IMX_CONSOLE &imx_console
1790#else
1791#define IMX_CONSOLE NULL
1792#endif
1793
1794static struct uart_driver imx_reg = {
1795 .owner = THIS_MODULE,
1796 .driver_name = DRIVER_NAME,
e3d13ff4 1797 .dev_name = DEV_NAME,
1da177e4
LT		 1798 .major = SERIAL_IMX_MAJOR,
1799 .minor = MINOR_START,
1800 .nr = ARRAY_SIZE(imx_ports),
1801 .cons = IMX_CONSOLE,
1802};
1803
3ae5eaec 1804static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1805{
d3810cd4 1806 struct imx_port *sport = platform_get_drvdata(dev);
db1a9b55
FE		 1807 unsigned int val;
1808
1809 /* enable wakeup from i.MX UART */
1810 val = readl(sport->port.membase + UCR3);
1811 val |= UCR3_AWAKEN;
1812 writel(val, sport->port.membase + UCR3);
1da177e4 1813
034dc4db 1814 uart_suspend_port(&imx_reg, &sport->port);
1da177e4 1815
d3810cd4 1816 return 0;
1da177e4
LT		 1817}
1818
3ae5eaec 1819static int serial_imx_resume(struct platform_device *dev)
1da177e4 1820{
d3810cd4 1821 struct imx_port *sport = platform_get_drvdata(dev);
db1a9b55
FE		 1822 unsigned int val;
1823
1824 /* disable wakeup from i.MX UART */
1825 val = readl(sport->port.membase + UCR3);
1826 val &= ~UCR3_AWAKEN;
1827 writel(val, sport->port.membase + UCR3);
1da177e4 1828
034dc4db 1829 uart_resume_port(&imx_reg, &sport->port);
1da177e4 1830
d3810cd4 1831 return 0;
1da177e4
LT		 1832}
1833
22698aa2 1834#ifdef CONFIG_OF
20bb8095
UKK		 1835/*
1836 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1837 * could successfully get all information from dt or a negative errno.
1838 */
22698aa2
SG		 1839static int serial_imx_probe_dt(struct imx_port *sport,
1840 struct platform_device *pdev)
1841{
1842 struct device_node *np = pdev->dev.of_node;
1843 const struct of_device_id *of_id =
1844 of_match_device(imx_uart_dt_ids, &pdev->dev);
ff05967a 1845 int ret;
22698aa2
SG		 1846
1847 if (!np)
20bb8095
UKK		 1848 /* no device tree device */
1849 return 1;
22698aa2 1850
ff05967a
SG		 1851 ret = of_alias_get_id(np, "serial");
1852 if (ret < 0) {
1853 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
a197a191 1854 return ret;
ff05967a
SG		 1855 }
1856 sport->port.line = ret;
22698aa2
SG		 1857
1858 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1859 sport->have_rtscts = 1;
1860
1861 if (of_get_property(np, "fsl,irda-mode", NULL))
1862 sport->use_irda = 1;
1863
20ff2fe6
HS		 1864 if (of_get_property(np, "fsl,dte-mode", NULL))
1865 sport->dte_mode = 1;
1866
22698aa2
SG		 1867 sport->devdata = of_id->data;
1868
1869 return 0;
1870}
1871#else
1872static inline int serial_imx_probe_dt(struct imx_port *sport,
1873 struct platform_device *pdev)
1874{
20bb8095 1875 return 1;
22698aa2
SG		 1876}
1877#endif
1878
1879static void serial_imx_probe_pdata(struct imx_port *sport,
1880 struct platform_device *pdev)
1881{
574de559 1882 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
22698aa2
SG		 1883
1884 sport->port.line = pdev->id;
1885 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1886
1887 if (!pdata)
1888 return;
1889
1890 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1891 sport->have_rtscts = 1;
1892
1893 if (pdata->flags & IMXUART_IRDA)
1894 sport->use_irda = 1;
1895}
1896
2582d8c1 1897static int serial_imx_probe(struct platform_device *pdev)
1da177e4 1898{
dbff4e9e 1899 struct imx_port *sport;
dbff4e9e
SH		 1900 void __iomem *base;
1901 int ret = 0;
1902 struct resource *res;
1903
42d34191 1904 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
dbff4e9e
SH		 1905 if (!sport)
1906 return -ENOMEM;
5b802344 1907
22698aa2 1908 ret = serial_imx_probe_dt(sport, pdev);
20bb8095 1909 if (ret > 0)
22698aa2 1910 serial_imx_probe_pdata(sport, pdev);
20bb8095 1911 else if (ret < 0)
42d34191 1912 return ret;
22698aa2 1913
dbff4e9e 1914 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
da82f997
AS		 1915 base = devm_ioremap_resource(&pdev->dev, res);
1916 if (IS_ERR(base))
1917 return PTR_ERR(base);
dbff4e9e
SH		 1918
1919 sport->port.dev = &pdev->dev;
1920 sport->port.mapbase = res->start;
1921 sport->port.membase = base;
1922 sport->port.type = PORT_IMX,
1923 sport->port.iotype = UPIO_MEM;
1924 sport->port.irq = platform_get_irq(pdev, 0);
1925 sport->rxirq = platform_get_irq(pdev, 0);
1926 sport->txirq = platform_get_irq(pdev, 1);
1927 sport->rtsirq = platform_get_irq(pdev, 2);
1928 sport->port.fifosize = 32;
1929 sport->port.ops = &imx_pops;
1930 sport->port.flags = UPF_BOOT_AUTOCONF;
dbff4e9e
SH		 1931 init_timer(&sport->timer);
1932 sport->timer.function = imx_timeout;
1933 sport->timer.data = (unsigned long)sport;
38a41fdf 1934
3a9465fa
SH		 1935 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1936 if (IS_ERR(sport->clk_ipg)) {
1937 ret = PTR_ERR(sport->clk_ipg);
833462e9 1938 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
42d34191 1939 return ret;
38a41fdf 1940 }
38a41fdf 1941
3a9465fa
SH		 1942 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1943 if (IS_ERR(sport->clk_per)) {
1944 ret = PTR_ERR(sport->clk_per);
833462e9 1945 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
42d34191 1946 return ret;
3a9465fa
SH		 1947 }
1948
3a9465fa 1949 sport->port.uartclk = clk_get_rate(sport->clk_per);
dbff4e9e 1950
22698aa2 1951 imx_ports[sport->port.line] = sport;
5b802344 1952
0a86a86b 1953 platform_set_drvdata(pdev, sport);
5b802344 1954
45af780a 1955 return uart_add_one_port(&imx_reg, &sport->port);
1da177e4
LT		 1956}
1957
2582d8c1 1958static int serial_imx_remove(struct platform_device *pdev)
1da177e4 1959{
2582d8c1 1960 struct imx_port *sport = platform_get_drvdata(pdev);
1da177e4 1961
45af780a 1962 return uart_remove_one_port(&imx_reg, &sport->port);
1da177e4
LT		 1963}
1964
3ae5eaec 1965static struct platform_driver serial_imx_driver = {
d3810cd4
OS		 1966 .probe = serial_imx_probe,
1967 .remove = serial_imx_remove,
1da177e4
LT		 1968
1969 .suspend = serial_imx_suspend,
1970 .resume = serial_imx_resume,
fe6b540a 1971 .id_table = imx_uart_devtype,
3ae5eaec 1972 .driver = {
d3810cd4 1973 .name = "imx-uart",
e169c139 1974 .owner = THIS_MODULE,
22698aa2 1975 .of_match_table = imx_uart_dt_ids,
3ae5eaec 1976 },
1da177e4
LT		 1977};
1978
1979static int __init imx_serial_init(void)
1980{
1981 int ret;
1982
50bbdba3 1983 pr_info("Serial: IMX driver\n");
1da177e4 1984
1da177e4
LT		 1985 ret = uart_register_driver(&imx_reg);
1986 if (ret)
1987 return ret;
1988
3ae5eaec 1989 ret = platform_driver_register(&serial_imx_driver);
1da177e4
LT		 1990 if (ret != 0)
1991 uart_unregister_driver(&imx_reg);
1992
f227824e 1993 return ret;
1da177e4
LT		 1994}
1995
1996static void __exit imx_serial_exit(void)
1997{
c889b896 1998 platform_driver_unregister(&serial_imx_driver);
4b300c36 1999 uart_unregister_driver(&imx_reg);
1da177e4
LT		 2000}
2001
2002module_init(imx_serial_init);
2003module_exit(imx_serial_exit);
2004
2005MODULE_AUTHOR("Sascha Hauer");
2006MODULE_DESCRIPTION("IMX generic serial port driver");
2007MODULE_LICENSE("GPL");
e169c139 2008MODULE_ALIAS("platform:imx-uart");
Linux kernel - Deliverables
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