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tty: Fix low_latency BUG
[deliverable/linux.git] / drivers / tty / serial / imx.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
b6e49138
FG		 9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
1da177e4
LT		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
1da177e4
LT		 29
30#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31#define SUPPORT_SYSRQ
32#endif
33
34#include <linux/module.h>
35#include <linux/ioport.h>
36#include <linux/init.h>
37#include <linux/console.h>
38#include <linux/sysrq.h>
d052d1be 39#include <linux/platform_device.h>
1da177e4
LT		 40#include <linux/tty.h>
41#include <linux/tty_flip.h>
42#include <linux/serial_core.h>
43#include <linux/serial.h>
38a41fdf 44#include <linux/clk.h>
b6e49138 45#include <linux/delay.h>
534fca06 46#include <linux/rational.h>
5a0e3ad6 47#include <linux/slab.h>
22698aa2
SG		 48#include <linux/of.h>
49#include <linux/of_device.h>
e32a9f8f 50#include <linux/io.h>
b4cdc8f6 51#include <linux/dma-mapping.h>
1da177e4 52
1da177e4 53#include <asm/irq.h>
82906b13 54#include <linux/platform_data/serial-imx.h>
b4cdc8f6 55#include <linux/platform_data/dma-imx.h>
1da177e4 56
ff4bfb21
SH		 57/* Register definitions */
58#define URXD0 0x0 /* Receiver Register */
59#define URTX0 0x40 /* Transmitter Register */
60#define UCR1 0x80 /* Control Register 1 */
61#define UCR2 0x84 /* Control Register 2 */
62#define UCR3 0x88 /* Control Register 3 */
63#define UCR4 0x8c /* Control Register 4 */
64#define UFCR 0x90 /* FIFO Control Register */
65#define USR1 0x94 /* Status Register 1 */
66#define USR2 0x98 /* Status Register 2 */
67#define UESC 0x9c /* Escape Character Register */
68#define UTIM 0xa0 /* Escape Timer Register */
69#define UBIR 0xa4 /* BRM Incremental Register */
70#define UBMR 0xa8 /* BRM Modulator Register */
71#define UBRC 0xac /* Baud Rate Count Register */
fe6b540a
SG		 72#define IMX21_ONEMS 0xb0 /* One Millisecond register */
73#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
74#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
ff4bfb21
SH		 75
76/* UART Control Register Bit Fields.*/
82313e66
SK		 77#define URXD_CHARRDY (1<<15)
78#define URXD_ERR (1<<14)
79#define URXD_OVRRUN (1<<13)
80#define URXD_FRMERR (1<<12)
81#define URXD_BRK (1<<11)
82#define URXD_PRERR (1<<10)
83#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
84#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
85#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
86#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
b4cdc8f6 87#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
82313e66
SK		 88#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
89#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
90#define UCR1_IREN (1<<7) /* Infrared interface enable */
91#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
92#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
93#define UCR1_SNDBRK (1<<4) /* Send break */
94#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
95#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
b4cdc8f6 96#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
82313e66
SK		 97#define UCR1_DOZE (1<<1) /* Doze */
98#define UCR1_UARTEN (1<<0) /* UART enabled */
99#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
100#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
101#define UCR2_CTSC (1<<13) /* CTS pin control */
102#define UCR2_CTS (1<<12) /* Clear to send */
103#define UCR2_ESCEN (1<<11) /* Escape enable */
104#define UCR2_PREN (1<<8) /* Parity enable */
105#define UCR2_PROE (1<<7) /* Parity odd/even */
106#define UCR2_STPB (1<<6) /* Stop */
107#define UCR2_WS (1<<5) /* Word size */
108#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
109#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
110#define UCR2_TXEN (1<<2) /* Transmitter enabled */
111#define UCR2_RXEN (1<<1) /* Receiver enabled */
112#define UCR2_SRST (1<<0) /* SW reset */
113#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
114#define UCR3_PARERREN (1<<12) /* Parity enable */
115#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
116#define UCR3_DSR (1<<10) /* Data set ready */
117#define UCR3_DCD (1<<9) /* Data carrier detect */
118#define UCR3_RI (1<<8) /* Ring indicator */
119#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
120#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
121#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
122#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
123#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
124#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
125#define UCR3_BPEN (1<<0) /* Preset registers enable */
126#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
127#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
128#define UCR4_INVR (1<<9) /* Inverted infrared reception */
129#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
130#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
131#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
b4cdc8f6 132#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
82313e66
SK		 133#define UCR4_IRSC (1<<5) /* IR special case */
134#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
135#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
136#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
137#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
138#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
139#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
140#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
141#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
142#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
143#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
144#define USR1_RTSS (1<<14) /* RTS pin status */
145#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
146#define USR1_RTSD (1<<12) /* RTS delta */
147#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
148#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
149#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
150#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
151#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
152#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
153#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
154#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
155#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
156#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
157#define USR2_IDLE (1<<12) /* Idle condition */
158#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
159#define USR2_WAKE (1<<7) /* Wake */
160#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
161#define USR2_TXDC (1<<3) /* Transmitter complete */
162#define USR2_BRCD (1<<2) /* Break condition */
163#define USR2_ORE (1<<1) /* Overrun error */
164#define USR2_RDR (1<<0) /* Recv data ready */
165#define UTS_FRCPERR (1<<13) /* Force parity error */
166#define UTS_LOOP (1<<12) /* Loop tx and rx */
167#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
168#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
169#define UTS_TXFULL (1<<4) /* TxFIFO full */
170#define UTS_RXFULL (1<<3) /* RxFIFO full */
171#define UTS_SOFTRST (1<<0) /* Software reset */
ff4bfb21 172
1da177e4 173/* We've been assigned a range on the "Low-density serial ports" major */
82313e66
SK		 174#define SERIAL_IMX_MAJOR 207
175#define MINOR_START 16
e3d13ff4 176#define DEV_NAME "ttymxc"
1da177e4 177
1da177e4
LT		 178/*
179 * This determines how often we check the modem status signals
180 * for any change. They generally aren't connected to an IRQ
181 * so we have to poll them. We also check immediately before
182 * filling the TX fifo incase CTS has been dropped.
183 */
184#define MCTRL_TIMEOUT (250*HZ/1000)
185
186#define DRIVER_NAME "IMX-uart"
187
dbff4e9e
SH		 188#define UART_NR 8
189
fe6b540a
SG		 190/* i.mx21 type uart runs on all i.mx except i.mx1 */
191enum imx_uart_type {
192 IMX1_UART,
193 IMX21_UART,
a496e628 194 IMX6Q_UART,
fe6b540a
SG		 195};
196
197/* device type dependent stuff */
198struct imx_uart_data {
199 unsigned uts_reg;
200 enum imx_uart_type devtype;
201};
202
1da177e4
LT		 203struct imx_port {
204 struct uart_port port;
205 struct timer_list timer;
206 unsigned int old_status;
82313e66 207 int txirq, rxirq, rtsirq;
26bbb3ff 208 unsigned int have_rtscts:1;
20ff2fe6 209 unsigned int dte_mode:1;
b6e49138
FG		 210 unsigned int use_irda:1;
211 unsigned int irda_inv_rx:1;
212 unsigned int irda_inv_tx:1;
213 unsigned short trcv_delay; /* transceiver delay */
3a9465fa
SH		 214 struct clk *clk_ipg;
215 struct clk *clk_per;
7d0b066f 216 const struct imx_uart_data *devdata;
b4cdc8f6
HS		 217
218 /* DMA fields */
219 unsigned int dma_is_inited:1;
220 unsigned int dma_is_enabled:1;
221 unsigned int dma_is_rxing:1;
222 unsigned int dma_is_txing:1;
223 struct dma_chan *dma_chan_rx, *dma_chan_tx;
224 struct scatterlist rx_sgl, tx_sgl[2];
225 void *rx_buf;
7cb92fd2 226 unsigned int tx_bytes;
b4cdc8f6
HS		 227 unsigned int dma_tx_nents;
228 wait_queue_head_t dma_wait;
1da177e4
LT		 229};
230
0ad5a814
DB		 231struct imx_port_ucrs {
232 unsigned int ucr1;
233 unsigned int ucr2;
234 unsigned int ucr3;
235};
236
b6e49138
FG		 237#ifdef CONFIG_IRDA
238#define USE_IRDA(sport) ((sport)->use_irda)
239#else
240#define USE_IRDA(sport) (0)
241#endif
242
fe6b540a
SG		 243static struct imx_uart_data imx_uart_devdata[] = {
244 [IMX1_UART] = {
245 .uts_reg = IMX1_UTS,
246 .devtype = IMX1_UART,
247 },
248 [IMX21_UART] = {
249 .uts_reg = IMX21_UTS,
250 .devtype = IMX21_UART,
251 },
a496e628
HS		 252 [IMX6Q_UART] = {
253 .uts_reg = IMX21_UTS,
254 .devtype = IMX6Q_UART,
255 },
fe6b540a
SG		 256};
257
258static struct platform_device_id imx_uart_devtype[] = {
259 {
260 .name = "imx1-uart",
261 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
262 }, {
263 .name = "imx21-uart",
264 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
a496e628
HS		 265 }, {
266 .name = "imx6q-uart",
267 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
fe6b540a
SG		 268 }, {
269 /* sentinel */
270 }
271};
272MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
273
22698aa2 274static struct of_device_id imx_uart_dt_ids[] = {
a496e628 275 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
22698aa2
SG		 276 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
277 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
278 { /* sentinel */ }
279};
280MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
281
fe6b540a
SG		 282static inline unsigned uts_reg(struct imx_port *sport)
283{
284 return sport->devdata->uts_reg;
285}
286
287static inline int is_imx1_uart(struct imx_port *sport)
288{
289 return sport->devdata->devtype == IMX1_UART;
290}
291
292static inline int is_imx21_uart(struct imx_port *sport)
293{
294 return sport->devdata->devtype == IMX21_UART;
295}
296
a496e628
HS		 297static inline int is_imx6q_uart(struct imx_port *sport)
298{
299 return sport->devdata->devtype == IMX6Q_UART;
300}
44a75411 301/*
302 * Save and restore functions for UCR1, UCR2 and UCR3 registers
303 */
e8bfa760 304#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_IMX_CONSOLE)
44a75411 305static void imx_port_ucrs_save(struct uart_port *port,
306 struct imx_port_ucrs *ucr)
307{
308 /* save control registers */
309 ucr->ucr1 = readl(port->membase + UCR1);
310 ucr->ucr2 = readl(port->membase + UCR2);
311 ucr->ucr3 = readl(port->membase + UCR3);
312}
313
314static void imx_port_ucrs_restore(struct uart_port *port,
315 struct imx_port_ucrs *ucr)
316{
317 /* restore control registers */
318 writel(ucr->ucr1, port->membase + UCR1);
319 writel(ucr->ucr2, port->membase + UCR2);
320 writel(ucr->ucr3, port->membase + UCR3);
321}
e8bfa760 322#endif
44a75411 323
1da177e4
LT		 324/*
325 * Handle any change of modem status signal since we were last called.
326 */
327static void imx_mctrl_check(struct imx_port *sport)
328{
329 unsigned int status, changed;
330
331 status = sport->port.ops->get_mctrl(&sport->port);
332 changed = status ^ sport->old_status;
333
334 if (changed == 0)
335 return;
336
337 sport->old_status = status;
338
339 if (changed & TIOCM_RI)
340 sport->port.icount.rng++;
341 if (changed & TIOCM_DSR)
342 sport->port.icount.dsr++;
343 if (changed & TIOCM_CAR)
344 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
345 if (changed & TIOCM_CTS)
346 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
347
bdc04e31 348 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
1da177e4
LT		 349}
350
351/*
352 * This is our per-port timeout handler, for checking the
353 * modem status signals.
354 */
355static void imx_timeout(unsigned long data)
356{
357 struct imx_port *sport = (struct imx_port *)data;
358 unsigned long flags;
359
ebd2c8f6 360 if (sport->port.state) {
1da177e4
LT		 361 spin_lock_irqsave(&sport->port.lock, flags);
362 imx_mctrl_check(sport);
363 spin_unlock_irqrestore(&sport->port.lock, flags);
364
365 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
366 }
367}
368
369/*
370 * interrupts disabled on entry
371 */
b129a8cc 372static void imx_stop_tx(struct uart_port *port)
1da177e4
LT		 373{
374 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 375 unsigned long temp;
376
b6e49138
FG		 377 if (USE_IRDA(sport)) {
378 /* half duplex - wait for end of transmission */
379 int n = 256;
380 while ((--n > 0) &&
381 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
382 udelay(5);
383 barrier();
384 }
385 /*
386 * irda transceiver - wait a bit more to avoid
387 * cutoff, hardware dependent
388 */
389 udelay(sport->trcv_delay);
390
391 /*
392 * half duplex - reactivate receive mode,
393 * flush receive pipe echo crap
394 */
395 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
396 temp = readl(sport->port.membase + UCR1);
397 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
398 writel(temp, sport->port.membase + UCR1);
399
400 temp = readl(sport->port.membase + UCR4);
401 temp &= ~(UCR4_TCEN);
402 writel(temp, sport->port.membase + UCR4);
403
404 while (readl(sport->port.membase + URXD0) &
405 URXD_CHARRDY)
406 barrier();
407
408 temp = readl(sport->port.membase + UCR1);
409 temp |= UCR1_RRDYEN;
410 writel(temp, sport->port.membase + UCR1);
411
412 temp = readl(sport->port.membase + UCR4);
413 temp |= UCR4_DREN;
414 writel(temp, sport->port.membase + UCR4);
415 }
416 return;
417 }
418
b4cdc8f6
HS		 419 /*
420 * We are maybe in the SMP context, so if the DMA TX thread is running
421 * on other cpu, we have to wait for it to finish.
422 */
423 if (sport->dma_is_enabled && sport->dma_is_txing)
424 return;
425
ff4bfb21
SH		 426 temp = readl(sport->port.membase + UCR1);
427 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
1da177e4
LT		 428}
429
430/*
431 * interrupts disabled on entry
432 */
433static void imx_stop_rx(struct uart_port *port)
434{
435 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 436 unsigned long temp;
437
b4cdc8f6
HS		 438 /*
439 * We are maybe in the SMP context, so if the DMA TX thread is running
440 * on other cpu, we have to wait for it to finish.
441 */
442 if (sport->dma_is_enabled && sport->dma_is_rxing)
443 return;
444
ff4bfb21 445 temp = readl(sport->port.membase + UCR2);
82313e66 446 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
1da177e4
LT		 447}
448
449/*
450 * Set the modem control timer to fire immediately.
451 */
452static void imx_enable_ms(struct uart_port *port)
453{
454 struct imx_port *sport = (struct imx_port *)port;
455
456 mod_timer(&sport->timer, jiffies);
457}
458
459static inline void imx_transmit_buffer(struct imx_port *sport)
460{
ebd2c8f6 461 struct circ_buf *xmit = &sport->port.state->xmit;
1da177e4 462
4e4e6602 463 while (!uart_circ_empty(xmit) &&
fe6b540a
SG		 464 !(readl(sport->port.membase + uts_reg(sport))
465 & UTS_TXFULL)) {
1da177e4
LT		 466 /* send xmit->buf[xmit->tail]
467 * out the port here */
ff4bfb21 468 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
d3810cd4 469 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1da177e4 470 sport->port.icount.tx++;
8c0b254b 471 }
1da177e4 472
97775731
FG		 473 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
474 uart_write_wakeup(&sport->port);
475
1da177e4 476 if (uart_circ_empty(xmit))
b129a8cc 477 imx_stop_tx(&sport->port);
1da177e4
LT		 478}
479
b4cdc8f6
HS		 480static void dma_tx_callback(void *data)
481{
482 struct imx_port *sport = data;
483 struct scatterlist *sgl = &sport->tx_sgl[0];
484 struct circ_buf *xmit = &sport->port.state->xmit;
485 unsigned long flags;
486
487 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
488
489 sport->dma_is_txing = 0;
490
491 /* update the stat */
492 spin_lock_irqsave(&sport->port.lock, flags);
493 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
494 sport->port.icount.tx += sport->tx_bytes;
495 spin_unlock_irqrestore(&sport->port.lock, flags);
496
497 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
498
2ad28e3e 499 uart_write_wakeup(&sport->port);
b4cdc8f6
HS		 500
501 if (waitqueue_active(&sport->dma_wait)) {
502 wake_up(&sport->dma_wait);
503 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
504 return;
505 }
b4cdc8f6
HS		 506}
507
7cb92fd2 508static void imx_dma_tx(struct imx_port *sport)
b4cdc8f6 509{
b4cdc8f6
HS		 510 struct circ_buf *xmit = &sport->port.state->xmit;
511 struct scatterlist *sgl = sport->tx_sgl;
512 struct dma_async_tx_descriptor *desc;
513 struct dma_chan *chan = sport->dma_chan_tx;
514 struct device *dev = sport->port.dev;
515 enum dma_status status;
b4cdc8f6
HS		 516 int ret;
517
f0ef8834 518 status = dmaengine_tx_status(chan, (dma_cookie_t)0, NULL);
b4cdc8f6
HS		 519 if (DMA_IN_PROGRESS == status)
520 return;
521
b4cdc8f6 522 sport->tx_bytes = uart_circ_chars_pending(xmit);
b4cdc8f6 523
947c74eb 524 if (xmit->tail > xmit->head && xmit->head > 0) {
b4cdc8f6
HS		 525 sport->dma_tx_nents = 2;
526 sg_init_table(sgl, 2);
527 sg_set_buf(sgl, xmit->buf + xmit->tail,
528 UART_XMIT_SIZE - xmit->tail);
529 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
530 } else {
531 sport->dma_tx_nents = 1;
532 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
533 }
b4cdc8f6
HS		 534
535 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
536 if (ret == 0) {
537 dev_err(dev, "DMA mapping error for TX.\n");
538 return;
539 }
540 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
541 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
542 if (!desc) {
543 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
544 return;
545 }
546 desc->callback = dma_tx_callback;
547 desc->callback_param = sport;
548
549 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
550 uart_circ_chars_pending(xmit));
551 /* fire it */
552 sport->dma_is_txing = 1;
553 dmaengine_submit(desc);
554 dma_async_issue_pending(chan);
555 return;
556}
557
1da177e4
LT		 558/*
559 * interrupts disabled on entry
560 */
b129a8cc 561static void imx_start_tx(struct uart_port *port)
1da177e4
LT		 562{
563 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 564 unsigned long temp;
1da177e4 565
b6e49138
FG		 566 if (USE_IRDA(sport)) {
567 /* half duplex in IrDA mode; have to disable receive mode */
568 temp = readl(sport->port.membase + UCR4);
569 temp &= ~(UCR4_DREN);
570 writel(temp, sport->port.membase + UCR4);
571
572 temp = readl(sport->port.membase + UCR1);
573 temp &= ~(UCR1_RRDYEN);
574 writel(temp, sport->port.membase + UCR1);
575 }
f1f836e4
AS		 576 /* Clear any pending ORE flag before enabling interrupt */
577 temp = readl(sport->port.membase + USR2);
578 writel(temp | USR2_ORE, sport->port.membase + USR2);
579
580 temp = readl(sport->port.membase + UCR4);
581 temp |= UCR4_OREN;
582 writel(temp, sport->port.membase + UCR4);
b6e49138 583
b4cdc8f6
HS		 584 if (!sport->dma_is_enabled) {
585 temp = readl(sport->port.membase + UCR1);
586 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
587 }
1da177e4 588
b6e49138
FG		 589 if (USE_IRDA(sport)) {
590 temp = readl(sport->port.membase + UCR1);
591 temp |= UCR1_TRDYEN;
592 writel(temp, sport->port.membase + UCR1);
593
594 temp = readl(sport->port.membase + UCR4);
595 temp |= UCR4_TCEN;
596 writel(temp, sport->port.membase + UCR4);
597 }
598
b4cdc8f6 599 if (sport->dma_is_enabled) {
7cb92fd2 600 imx_dma_tx(sport);
b4cdc8f6
HS		 601 return;
602 }
603
fe6b540a 604 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
ff4bfb21 605 imx_transmit_buffer(sport);
1da177e4
LT		 606}
607
7d12e780 608static irqreturn_t imx_rtsint(int irq, void *dev_id)
ceca629e 609{
15aafa2f 610 struct imx_port *sport = dev_id;
5680e941 611 unsigned int val;
ceca629e
SH		 612 unsigned long flags;
613
614 spin_lock_irqsave(&sport->port.lock, flags);
615
ff4bfb21 616 writel(USR1_RTSD, sport->port.membase + USR1);
5680e941 617 val = readl(sport->port.membase + USR1) & USR1_RTSS;
ceca629e 618 uart_handle_cts_change(&sport->port, !!val);
bdc04e31 619 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
ceca629e
SH		 620
621 spin_unlock_irqrestore(&sport->port.lock, flags);
622 return IRQ_HANDLED;
623}
624
7d12e780 625static irqreturn_t imx_txint(int irq, void *dev_id)
1da177e4 626{
15aafa2f 627 struct imx_port *sport = dev_id;
ebd2c8f6 628 struct circ_buf *xmit = &sport->port.state->xmit;
1da177e4
LT		 629 unsigned long flags;
630
82313e66 631 spin_lock_irqsave(&sport->port.lock, flags);
699cbd67 632 if (sport->port.x_char) {
1da177e4 633 /* Send next char */
ff4bfb21 634 writel(sport->port.x_char, sport->port.membase + URTX0);
1da177e4
LT		 635 goto out;
636 }
637
638 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
b129a8cc 639 imx_stop_tx(&sport->port);
1da177e4
LT		 640 goto out;
641 }
642
643 imx_transmit_buffer(sport);
644
645 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
646 uart_write_wakeup(&sport->port);
647
648out:
82313e66 649 spin_unlock_irqrestore(&sport->port.lock, flags);
1da177e4
LT		 650 return IRQ_HANDLED;
651}
652
7d12e780 653static irqreturn_t imx_rxint(int irq, void *dev_id)
1da177e4
LT		 654{
655 struct imx_port *sport = dev_id;
82313e66 656 unsigned int rx, flg, ignored = 0;
92a19f9c 657 struct tty_port *port = &sport->port.state->port;
ff4bfb21 658 unsigned long flags, temp;
1da177e4 659
82313e66 660 spin_lock_irqsave(&sport->port.lock, flags);
1da177e4 661
0d3c3938 662 while (readl(sport->port.membase + USR2) & USR2_RDR) {
1da177e4
LT		 663 flg = TTY_NORMAL;
664 sport->port.icount.rx++;
665
0d3c3938
SH		 666 rx = readl(sport->port.membase + URXD0);
667
ff4bfb21 668 temp = readl(sport->port.membase + USR2);
864eeed0 669 if (temp & USR2_BRCD) {
94d32f99 670 writel(USR2_BRCD, sport->port.membase + USR2);
864eeed0
SH		 671 if (uart_handle_break(&sport->port))
672 continue;
1da177e4
LT		 673 }
674
d3810cd4 675 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
864eeed0
SH		 676 continue;
677
019dc9ea
HW		 678 if (unlikely(rx & URXD_ERR)) {
679 if (rx & URXD_BRK)
680 sport->port.icount.brk++;
681 else if (rx & URXD_PRERR)
864eeed0
SH		 682 sport->port.icount.parity++;
683 else if (rx & URXD_FRMERR)
684 sport->port.icount.frame++;
685 if (rx & URXD_OVRRUN)
686 sport->port.icount.overrun++;
687
688 if (rx & sport->port.ignore_status_mask) {
689 if (++ignored > 100)
690 goto out;
691 continue;
692 }
693
694 rx &= sport->port.read_status_mask;
695
019dc9ea
HW		 696 if (rx & URXD_BRK)
697 flg = TTY_BREAK;
698 else if (rx & URXD_PRERR)
864eeed0
SH		 699 flg = TTY_PARITY;
700 else if (rx & URXD_FRMERR)
701 flg = TTY_FRAME;
702 if (rx & URXD_OVRRUN)
703 flg = TTY_OVERRUN;
1da177e4 704
864eeed0
SH		 705#ifdef SUPPORT_SYSRQ
706 sport->port.sysrq = 0;
707#endif
708 }
1da177e4 709
92a19f9c 710 tty_insert_flip_char(port, rx, flg);
864eeed0 711 }
1da177e4
LT		 712
713out:
82313e66 714 spin_unlock_irqrestore(&sport->port.lock, flags);
2e124b4a 715 tty_flip_buffer_push(port);
1da177e4 716 return IRQ_HANDLED;
1da177e4
LT		 717}
718
7cb92fd2 719static int start_rx_dma(struct imx_port *sport);
b4cdc8f6
HS		 720/*
721 * If the RXFIFO is filled with some data, and then we
722 * arise a DMA operation to receive them.
723 */
724static void imx_dma_rxint(struct imx_port *sport)
725{
726 unsigned long temp;
727
728 temp = readl(sport->port.membase + USR2);
729 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
730 sport->dma_is_rxing = 1;
731
732 /* disable the `Recerver Ready Interrrupt` */
733 temp = readl(sport->port.membase + UCR1);
734 temp &= ~(UCR1_RRDYEN);
735 writel(temp, sport->port.membase + UCR1);
736
737 /* tell the DMA to receive the data. */
7cb92fd2 738 start_rx_dma(sport);
b4cdc8f6
HS		 739 }
740}
741
e3d13ff4
SH		 742static irqreturn_t imx_int(int irq, void *dev_id)
743{
744 struct imx_port *sport = dev_id;
745 unsigned int sts;
f1f836e4 746 unsigned int sts2;
e3d13ff4
SH		 747
748 sts = readl(sport->port.membase + USR1);
749
b4cdc8f6
HS		 750 if (sts & USR1_RRDY) {
751 if (sport->dma_is_enabled)
752 imx_dma_rxint(sport);
753 else
754 imx_rxint(irq, dev_id);
755 }
e3d13ff4
SH		 756
757 if (sts & USR1_TRDY &&
758 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
759 imx_txint(irq, dev_id);
760
9fbe6044 761 if (sts & USR1_RTSD)
e3d13ff4
SH		 762 imx_rtsint(irq, dev_id);
763
db1a9b55
FE		 764 if (sts & USR1_AWAKE)
765 writel(USR1_AWAKE, sport->port.membase + USR1);
766
f1f836e4
AS		 767 sts2 = readl(sport->port.membase + USR2);
768 if (sts2 & USR2_ORE) {
769 dev_err(sport->port.dev, "Rx FIFO overrun\n");
770 sport->port.icount.overrun++;
771 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
772 }
773
e3d13ff4
SH		 774 return IRQ_HANDLED;
775}
776
1da177e4
LT		 777/*
778 * Return TIOCSER_TEMT when transmitter is not busy.
779 */
780static unsigned int imx_tx_empty(struct uart_port *port)
781{
782 struct imx_port *sport = (struct imx_port *)port;
1ce43e58 783 unsigned int ret;
1da177e4 784
1ce43e58 785 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1da177e4 786
1ce43e58
HS		 787 /* If the TX DMA is working, return 0. */
788 if (sport->dma_is_enabled && sport->dma_is_txing)
789 ret = 0;
790
791 return ret;
1da177e4
LT		 792}
793
0f302dc3
SH		 794/*
795 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
796 */
1da177e4
LT		 797static unsigned int imx_get_mctrl(struct uart_port *port)
798{
d3810cd4
OS		 799 struct imx_port *sport = (struct imx_port *)port;
800 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
0f302dc3 801
d3810cd4
OS		 802 if (readl(sport->port.membase + USR1) & USR1_RTSS)
803 tmp |= TIOCM_CTS;
0f302dc3 804
d3810cd4
OS		 805 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
806 tmp |= TIOCM_RTS;
0f302dc3 807
6b471a98
HS		 808 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
809 tmp |= TIOCM_LOOP;
810
d3810cd4 811 return tmp;
1da177e4
LT		 812}
813
814static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
815{
d3810cd4 816 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21
SH		 817 unsigned long temp;
818
819 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
0f302dc3 820
d3810cd4 821 if (mctrl & TIOCM_RTS)
b4cdc8f6
HS		 822 if (!sport->dma_is_enabled)
823 temp |= UCR2_CTS;
ff4bfb21
SH		 824
825 writel(temp, sport->port.membase + UCR2);
6b471a98
HS		 826
827 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
828 if (mctrl & TIOCM_LOOP)
829 temp |= UTS_LOOP;
830 writel(temp, sport->port.membase + uts_reg(sport));
1da177e4
LT		 831}
832
833/*
834 * Interrupts always disabled.
835 */
836static void imx_break_ctl(struct uart_port *port, int break_state)
837{
838 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 839 unsigned long flags, temp;
1da177e4
LT		 840
841 spin_lock_irqsave(&sport->port.lock, flags);
842
ff4bfb21
SH		 843 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
844
82313e66 845 if (break_state != 0)
ff4bfb21
SH		 846 temp |= UCR1_SNDBRK;
847
848 writel(temp, sport->port.membase + UCR1);
1da177e4
LT		 849
850 spin_unlock_irqrestore(&sport->port.lock, flags);
851}
852
853#define TXTL 2 /* reset default */
854#define RXTL 1 /* reset default */
855
587897f5
SH		 856static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
857{
858 unsigned int val;
587897f5 859
7be0670f
DB		 860 /* set receiver / transmitter trigger level */
861 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
862 val |= TXTL << UFCR_TXTL_SHF | RXTL;
ff4bfb21 863 writel(val, sport->port.membase + UFCR);
587897f5
SH		 864 return 0;
865}
866
b4cdc8f6 867#define RX_BUF_SIZE (PAGE_SIZE)
b4cdc8f6
HS		 868static void imx_rx_dma_done(struct imx_port *sport)
869{
870 unsigned long temp;
871
872 /* Enable this interrupt when the RXFIFO is empty. */
873 temp = readl(sport->port.membase + UCR1);
874 temp |= UCR1_RRDYEN;
875 writel(temp, sport->port.membase + UCR1);
876
877 sport->dma_is_rxing = 0;
878
879 /* Is the shutdown waiting for us? */
880 if (waitqueue_active(&sport->dma_wait))
881 wake_up(&sport->dma_wait);
882}
883
884/*
885 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
886 * [1] the RX DMA buffer is full.
887 * [2] the Aging timer expires(wait for 8 bytes long)
888 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
889 *
890 * The [2] is trigger when a character was been sitting in the FIFO
891 * meanwhile [3] can wait for 32 bytes long when the RX line is
892 * on IDLE state and RxFIFO is empty.
893 */
894static void dma_rx_callback(void *data)
895{
896 struct imx_port *sport = data;
897 struct dma_chan *chan = sport->dma_chan_rx;
898 struct scatterlist *sgl = &sport->rx_sgl;
7cb92fd2 899 struct tty_port *port = &sport->port.state->port;
b4cdc8f6
HS		 900 struct dma_tx_state state;
901 enum dma_status status;
902 unsigned int count;
903
904 /* unmap it first */
905 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
906
f0ef8834 907 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
b4cdc8f6
HS		 908 count = RX_BUF_SIZE - state.residue;
909 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
910
911 if (count) {
7cb92fd2
HS		 912 tty_insert_flip_string(port, sport->rx_buf, count);
913 tty_flip_buffer_push(port);
914
915 start_rx_dma(sport);
b4cdc8f6
HS		 916 } else
917 imx_rx_dma_done(sport);
918}
919
920static int start_rx_dma(struct imx_port *sport)
921{
922 struct scatterlist *sgl = &sport->rx_sgl;
923 struct dma_chan *chan = sport->dma_chan_rx;
924 struct device *dev = sport->port.dev;
925 struct dma_async_tx_descriptor *desc;
926 int ret;
927
928 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
929 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
930 if (ret == 0) {
931 dev_err(dev, "DMA mapping error for RX.\n");
932 return -EINVAL;
933 }
934 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
935 DMA_PREP_INTERRUPT);
936 if (!desc) {
937 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
938 return -EINVAL;
939 }
940 desc->callback = dma_rx_callback;
941 desc->callback_param = sport;
942
943 dev_dbg(dev, "RX: prepare for the DMA.\n");
944 dmaengine_submit(desc);
945 dma_async_issue_pending(chan);
946 return 0;
947}
948
949static void imx_uart_dma_exit(struct imx_port *sport)
950{
951 if (sport->dma_chan_rx) {
952 dma_release_channel(sport->dma_chan_rx);
953 sport->dma_chan_rx = NULL;
954
955 kfree(sport->rx_buf);
956 sport->rx_buf = NULL;
957 }
958
959 if (sport->dma_chan_tx) {
960 dma_release_channel(sport->dma_chan_tx);
961 sport->dma_chan_tx = NULL;
962 }
963
964 sport->dma_is_inited = 0;
965}
966
967static int imx_uart_dma_init(struct imx_port *sport)
968{
b09c74ae 969 struct dma_slave_config slave_config = {};
b4cdc8f6
HS		 970 struct device *dev = sport->port.dev;
971 int ret;
972
973 /* Prepare for RX : */
974 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
975 if (!sport->dma_chan_rx) {
976 dev_dbg(dev, "cannot get the DMA channel.\n");
977 ret = -EINVAL;
978 goto err;
979 }
980
981 slave_config.direction = DMA_DEV_TO_MEM;
982 slave_config.src_addr = sport->port.mapbase + URXD0;
983 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
984 slave_config.src_maxburst = RXTL;
985 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
986 if (ret) {
987 dev_err(dev, "error in RX dma configuration.\n");
988 goto err;
989 }
990
991 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
992 if (!sport->rx_buf) {
993 dev_err(dev, "cannot alloc DMA buffer.\n");
994 ret = -ENOMEM;
995 goto err;
996 }
b4cdc8f6
HS		 997
998 /* Prepare for TX : */
999 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1000 if (!sport->dma_chan_tx) {
1001 dev_err(dev, "cannot get the TX DMA channel!\n");
1002 ret = -EINVAL;
1003 goto err;
1004 }
1005
1006 slave_config.direction = DMA_MEM_TO_DEV;
1007 slave_config.dst_addr = sport->port.mapbase + URTX0;
1008 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1009 slave_config.dst_maxburst = TXTL;
1010 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1011 if (ret) {
1012 dev_err(dev, "error in TX dma configuration.");
1013 goto err;
1014 }
1015
1016 sport->dma_is_inited = 1;
1017
1018 return 0;
1019err:
1020 imx_uart_dma_exit(sport);
1021 return ret;
1022}
1023
1024static void imx_enable_dma(struct imx_port *sport)
1025{
1026 unsigned long temp;
b4cdc8f6 1027
b4cdc8f6
HS		 1028 init_waitqueue_head(&sport->dma_wait);
1029
1030 /* set UCR1 */
1031 temp = readl(sport->port.membase + UCR1);
1032 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1033 /* wait for 32 idle frames for IDDMA interrupt */
1034 UCR1_ICD_REG(3);
1035 writel(temp, sport->port.membase + UCR1);
1036
1037 /* set UCR4 */
1038 temp = readl(sport->port.membase + UCR4);
1039 temp |= UCR4_IDDMAEN;
1040 writel(temp, sport->port.membase + UCR4);
1041
1042 sport->dma_is_enabled = 1;
1043}
1044
1045static void imx_disable_dma(struct imx_port *sport)
1046{
1047 unsigned long temp;
b4cdc8f6
HS		 1048
1049 /* clear UCR1 */
1050 temp = readl(sport->port.membase + UCR1);
1051 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1052 writel(temp, sport->port.membase + UCR1);
1053
1054 /* clear UCR2 */
1055 temp = readl(sport->port.membase + UCR2);
1056 temp &= ~(UCR2_CTSC | UCR2_CTS);
1057 writel(temp, sport->port.membase + UCR2);
1058
1059 /* clear UCR4 */
1060 temp = readl(sport->port.membase + UCR4);
1061 temp &= ~UCR4_IDDMAEN;
1062 writel(temp, sport->port.membase + UCR4);
1063
1064 sport->dma_is_enabled = 0;
b4cdc8f6
HS		 1065}
1066
1c5250d6
VL		 1067/* half the RX buffer size */
1068#define CTSTL 16
1069
1da177e4
LT		 1070static int imx_startup(struct uart_port *port)
1071{
1072 struct imx_port *sport = (struct imx_port *)port;
1073 int retval;
ff4bfb21 1074 unsigned long flags, temp;
1da177e4 1075
1cf93e0d
HS		 1076 retval = clk_prepare_enable(sport->clk_per);
1077 if (retval)
1078 goto error_out1;
1079 retval = clk_prepare_enable(sport->clk_ipg);
1080 if (retval) {
1081 clk_disable_unprepare(sport->clk_per);
1082 goto error_out1;
0c375501 1083 }
28eb4274 1084
587897f5 1085 imx_setup_ufcr(sport, 0);
1da177e4
LT		 1086
1087 /* disable the DREN bit (Data Ready interrupt enable) before
1088 * requesting IRQs
1089 */
ff4bfb21 1090 temp = readl(sport->port.membase + UCR4);
b6e49138
FG		 1091
1092 if (USE_IRDA(sport))
1093 temp |= UCR4_IRSC;
1094
1c5250d6 1095 /* set the trigger level for CTS */
82313e66
SK		 1096 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1097 temp |= CTSTL << UCR4_CTSTL_SHF;
1c5250d6 1098
ff4bfb21 1099 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1da177e4 1100
b6e49138
FG		 1101 if (USE_IRDA(sport)) {
1102 /* reset fifo's and state machines */
1103 int i = 100;
1104 temp = readl(sport->port.membase + UCR2);
1105 temp &= ~UCR2_SRST;
1106 writel(temp, sport->port.membase + UCR2);
1107 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
1108 (--i > 0)) {
1109 udelay(1);
1110 }
1111 }
1112
1da177e4 1113 /*
e3d13ff4
SH		 1114 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1115 * chips only have one interrupt.
1da177e4 1116 */
e3d13ff4
SH		 1117 if (sport->txirq > 0) {
1118 retval = request_irq(sport->rxirq, imx_rxint, 0,
1119 DRIVER_NAME, sport);
1120 if (retval)
1121 goto error_out1;
1122
1123 retval = request_irq(sport->txirq, imx_txint, 0,
1124 DRIVER_NAME, sport);
1125 if (retval)
1126 goto error_out2;
1127
b6e49138
FG		 1128 /* do not use RTS IRQ on IrDA */
1129 if (!USE_IRDA(sport)) {
1ee8f65b 1130 retval = request_irq(sport->rtsirq, imx_rtsint, 0,
b6e49138
FG		 1131 DRIVER_NAME, sport);
1132 if (retval)
1133 goto error_out3;
1134 }
e3d13ff4
SH		 1135 } else {
1136 retval = request_irq(sport->port.irq, imx_int, 0,
1137 DRIVER_NAME, sport);
1138 if (retval) {
1139 free_irq(sport->port.irq, sport);
1140 goto error_out1;
1141 }
1142 }
ceca629e 1143
9ec1882d 1144 spin_lock_irqsave(&sport->port.lock, flags);
1da177e4
LT		 1145 /*
1146 * Finally, clear and enable interrupts
1147 */
ff4bfb21
SH		 1148 writel(USR1_RTSD, sport->port.membase + USR1);
1149
1150 temp = readl(sport->port.membase + UCR1);
789d5258 1151 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
b6e49138
FG		 1152
1153 if (USE_IRDA(sport)) {
1154 temp |= UCR1_IREN;
1155 temp &= ~(UCR1_RTSDEN);
1156 }
1157
ff4bfb21 1158 writel(temp, sport->port.membase + UCR1);
1da177e4 1159
ff4bfb21
SH		 1160 temp = readl(sport->port.membase + UCR2);
1161 temp |= (UCR2_RXEN | UCR2_TXEN);
bff09b09
LS		 1162 if (!sport->have_rtscts)
1163 temp |= UCR2_IRTS;
ff4bfb21 1164 writel(temp, sport->port.membase + UCR2);
1da177e4 1165
b6e49138
FG		 1166 if (USE_IRDA(sport)) {
1167 /* clear RX-FIFO */
1168 int i = 64;
1169 while ((--i > 0) &&
1170 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
1171 barrier();
1172 }
1173 }
1174
a496e628 1175 if (!is_imx1_uart(sport)) {
37d6fb62 1176 temp = readl(sport->port.membase + UCR3);
fe6b540a 1177 temp |= IMX21_UCR3_RXDMUXSEL;
37d6fb62
SH		 1178 writel(temp, sport->port.membase + UCR3);
1179 }
4411805b 1180
b6e49138
FG		 1181 if (USE_IRDA(sport)) {
1182 temp = readl(sport->port.membase + UCR4);
1183 if (sport->irda_inv_rx)
1184 temp |= UCR4_INVR;
1185 else
1186 temp &= ~(UCR4_INVR);
1187 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
1188
1189 temp = readl(sport->port.membase + UCR3);
1190 if (sport->irda_inv_tx)
1191 temp |= UCR3_INVT;
1192 else
1193 temp &= ~(UCR3_INVT);
1194 writel(temp, sport->port.membase + UCR3);
1195 }
1196
1da177e4
LT		 1197 /*
1198 * Enable modem status interrupts
1199 */
1da177e4 1200 imx_enable_ms(&sport->port);
82313e66 1201 spin_unlock_irqrestore(&sport->port.lock, flags);
1da177e4 1202
b6e49138
FG		 1203 if (USE_IRDA(sport)) {
1204 struct imxuart_platform_data *pdata;
574de559 1205 pdata = dev_get_platdata(sport->port.dev);
b6e49138
FG		 1206 sport->irda_inv_rx = pdata->irda_inv_rx;
1207 sport->irda_inv_tx = pdata->irda_inv_tx;
1208 sport->trcv_delay = pdata->transceiver_delay;
1209 if (pdata->irda_enable)
1210 pdata->irda_enable(1);
1211 }
1212
1da177e4
LT		 1213 return 0;
1214
ceca629e 1215error_out3:
e3d13ff4
SH		 1216 if (sport->txirq)
1217 free_irq(sport->txirq, sport);
1da177e4 1218error_out2:
e3d13ff4
SH		 1219 if (sport->rxirq)
1220 free_irq(sport->rxirq, sport);
86371d07 1221error_out1:
1da177e4
LT		 1222 return retval;
1223}
1224
1225static void imx_shutdown(struct uart_port *port)
1226{
1227 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 1228 unsigned long temp;
9ec1882d 1229 unsigned long flags;
1da177e4 1230
b4cdc8f6
HS		 1231 if (sport->dma_is_enabled) {
1232 /* We have to wait for the DMA to finish. */
1233 wait_event(sport->dma_wait,
1234 !sport->dma_is_rxing && !sport->dma_is_txing);
1235 imx_stop_rx(port);
1236 imx_disable_dma(sport);
1237 imx_uart_dma_exit(sport);
1238 }
1239
9ec1882d 1240 spin_lock_irqsave(&sport->port.lock, flags);
2e146392
FG		 1241 temp = readl(sport->port.membase + UCR2);
1242 temp &= ~(UCR2_TXEN);
1243 writel(temp, sport->port.membase + UCR2);
9ec1882d 1244 spin_unlock_irqrestore(&sport->port.lock, flags);
2e146392 1245
b6e49138
FG		 1246 if (USE_IRDA(sport)) {
1247 struct imxuart_platform_data *pdata;
574de559 1248 pdata = dev_get_platdata(sport->port.dev);
b6e49138
FG		 1249 if (pdata->irda_enable)
1250 pdata->irda_enable(0);
1251 }
1252
1da177e4
LT		 1253 /*
1254 * Stop our timer.
1255 */
1256 del_timer_sync(&sport->timer);
1257
1258 /*
1259 * Free the interrupts
1260 */
e3d13ff4 1261 if (sport->txirq > 0) {
b6e49138
FG		 1262 if (!USE_IRDA(sport))
1263 free_irq(sport->rtsirq, sport);
e3d13ff4
SH		 1264 free_irq(sport->txirq, sport);
1265 free_irq(sport->rxirq, sport);
1266 } else
1267 free_irq(sport->port.irq, sport);
1da177e4
LT		 1268
1269 /*
1270 * Disable all interrupts, port and break condition.
1271 */
1272
9ec1882d 1273 spin_lock_irqsave(&sport->port.lock, flags);
ff4bfb21
SH		 1274 temp = readl(sport->port.membase + UCR1);
1275 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
b6e49138
FG		 1276 if (USE_IRDA(sport))
1277 temp &= ~(UCR1_IREN);
1278
ff4bfb21 1279 writel(temp, sport->port.membase + UCR1);
9ec1882d 1280 spin_unlock_irqrestore(&sport->port.lock, flags);
28eb4274 1281
1cf93e0d
HS		 1282 clk_disable_unprepare(sport->clk_per);
1283 clk_disable_unprepare(sport->clk_ipg);
1da177e4
LT		 1284}
1285
eb56b7ed
HS		 1286static void imx_flush_buffer(struct uart_port *port)
1287{
1288 struct imx_port *sport = (struct imx_port *)port;
1289
1290 if (sport->dma_is_enabled) {
1291 sport->tx_bytes = 0;
1292 dmaengine_terminate_all(sport->dma_chan_tx);
1293 }
1294}
1295
1da177e4 1296static void
606d099c
AC		 1297imx_set_termios(struct uart_port *port, struct ktermios *termios,
1298 struct ktermios *old)
1da177e4
LT		 1299{
1300 struct imx_port *sport = (struct imx_port *)port;
1301 unsigned long flags;
1302 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1303 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
534fca06
OS		 1304 unsigned int div, ufcr;
1305 unsigned long num, denom;
d7f8d437 1306 uint64_t tdiv64;
1da177e4
LT		 1307
1308 /*
1309 * If we don't support modem control lines, don't allow
1310 * these to be set.
1311 */
1312 if (0) {
1313 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
1314 termios->c_cflag |= CLOCAL;
1315 }
1316
1317 /*
1318 * We only support CS7 and CS8.
1319 */
1320 while ((termios->c_cflag & CSIZE) != CS7 &&
1321 (termios->c_cflag & CSIZE) != CS8) {
1322 termios->c_cflag &= ~CSIZE;
1323 termios->c_cflag |= old_csize;
1324 old_csize = CS8;
1325 }
1326
1327 if ((termios->c_cflag & CSIZE) == CS8)
1328 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1329 else
1330 ucr2 = UCR2_SRST | UCR2_IRTS;
1331
1332 if (termios->c_cflag & CRTSCTS) {
82313e66 1333 if (sport->have_rtscts) {
5b802344
SH		 1334 ucr2 &= ~UCR2_IRTS;
1335 ucr2 |= UCR2_CTSC;
b4cdc8f6
HS		 1336
1337 /* Can we enable the DMA support? */
1338 if (is_imx6q_uart(sport) && !uart_console(port)
1339 && !sport->dma_is_inited)
1340 imx_uart_dma_init(sport);
5b802344
SH		 1341 } else {
1342 termios->c_cflag &= ~CRTSCTS;
1343 }
1da177e4
LT		 1344 }
1345
1346 if (termios->c_cflag & CSTOPB)
1347 ucr2 |= UCR2_STPB;
1348 if (termios->c_cflag & PARENB) {
1349 ucr2 |= UCR2_PREN;
3261e362 1350 if (termios->c_cflag & PARODD)
1da177e4
LT		 1351 ucr2 |= UCR2_PROE;
1352 }
1353
995234da
EM		 1354 del_timer_sync(&sport->timer);
1355
1da177e4
LT		 1356 /*
1357 * Ask the core to calculate the divisor for us.
1358 */
036bb15e 1359 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1da177e4
LT		 1360 quot = uart_get_divisor(port, baud);
1361
1362 spin_lock_irqsave(&sport->port.lock, flags);
1363
1364 sport->port.read_status_mask = 0;
1365 if (termios->c_iflag & INPCK)
1366 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1367 if (termios->c_iflag & (BRKINT | PARMRK))
1368 sport->port.read_status_mask |= URXD_BRK;
1369
1370 /*
1371 * Characters to ignore
1372 */
1373 sport->port.ignore_status_mask = 0;
1374 if (termios->c_iflag & IGNPAR)
1375 sport->port.ignore_status_mask |= URXD_PRERR;
1376 if (termios->c_iflag & IGNBRK) {
1377 sport->port.ignore_status_mask |= URXD_BRK;
1378 /*
1379 * If we're ignoring parity and break indicators,
1380 * ignore overruns too (for real raw support).
1381 */
1382 if (termios->c_iflag & IGNPAR)
1383 sport->port.ignore_status_mask |= URXD_OVRRUN;
1384 }
1385
1da177e4
LT		 1386 /*
1387 * Update the per-port timeout.
1388 */
1389 uart_update_timeout(port, termios->c_cflag, baud);
1390
1391 /*
1392 * disable interrupts and drain transmitter
1393 */
ff4bfb21
SH		 1394 old_ucr1 = readl(sport->port.membase + UCR1);
1395 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1396 sport->port.membase + UCR1);
1da177e4 1397
82313e66 1398 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1da177e4
LT		 1399 barrier();
1400
1401 /* then, disable everything */
ff4bfb21 1402 old_txrxen = readl(sport->port.membase + UCR2);
82313e66 1403 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
ff4bfb21
SH		 1404 sport->port.membase + UCR2);
1405 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1da177e4 1406
b6e49138
FG		 1407 if (USE_IRDA(sport)) {
1408 /*
1409 * use maximum available submodule frequency to
1410 * avoid missing short pulses due to low sampling rate
1411 */
036bb15e 1412 div = 1;
b6e49138 1413 } else {
09bd00f6
HF		 1414 /* custom-baudrate handling */
1415 div = sport->port.uartclk / (baud * 16);
1416 if (baud == 38400 && quot != div)
1417 baud = sport->port.uartclk / (quot * 16);
1418
b6e49138
FG		 1419 div = sport->port.uartclk / (baud * 16);
1420 if (div > 7)
1421 div = 7;
1422 if (!div)
1423 div = 1;
1424 }
036bb15e 1425
534fca06
OS		 1426 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1427 1 << 16, 1 << 16, &num, &denom);
036bb15e 1428
eab4f5af
AC		 1429 tdiv64 = sport->port.uartclk;
1430 tdiv64 *= num;
1431 do_div(tdiv64, denom * 16 * div);
1432 tty_termios_encode_baud_rate(termios,
1a2c4b31 1433 (speed_t)tdiv64, (speed_t)tdiv64);
d7f8d437 1434
534fca06
OS		 1435 num -= 1;
1436 denom -= 1;
036bb15e
SH		 1437
1438 ufcr = readl(sport->port.membase + UFCR);
b6e49138 1439 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
20ff2fe6
HS		 1440 if (sport->dte_mode)
1441 ufcr |= UFCR_DCEDTE;
036bb15e
SH		 1442 writel(ufcr, sport->port.membase + UFCR);
1443
534fca06
OS		 1444 writel(num, sport->port.membase + UBIR);
1445 writel(denom, sport->port.membase + UBMR);
1446
a496e628 1447 if (!is_imx1_uart(sport))
37d6fb62 1448 writel(sport->port.uartclk / div / 1000,
fe6b540a 1449 sport->port.membase + IMX21_ONEMS);
ff4bfb21
SH		 1450
1451 writel(old_ucr1, sport->port.membase + UCR1);
1da177e4 1452
ff4bfb21
SH		 1453 /* set the parity, stop bits and data size */
1454 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1da177e4
LT		 1455
1456 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1457 imx_enable_ms(&sport->port);
1458
b4cdc8f6
HS		 1459 if (sport->dma_is_inited && !sport->dma_is_enabled)
1460 imx_enable_dma(sport);
1da177e4
LT		 1461 spin_unlock_irqrestore(&sport->port.lock, flags);
1462}
1463
1464static const char *imx_type(struct uart_port *port)
1465{
1466 struct imx_port *sport = (struct imx_port *)port;
1467
1468 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1469}
1470
1471/*
1472 * Release the memory region(s) being used by 'port'.
1473 */
1474static void imx_release_port(struct uart_port *port)
1475{
3d454446
SH		 1476 struct platform_device *pdev = to_platform_device(port->dev);
1477 struct resource *mmres;
1da177e4 1478
3d454446 1479 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
28f65c11 1480 release_mem_region(mmres->start, resource_size(mmres));
1da177e4
LT		 1481}
1482
1483/*
1484 * Request the memory region(s) being used by 'port'.
1485 */
1486static int imx_request_port(struct uart_port *port)
1487{
3d454446
SH		 1488 struct platform_device *pdev = to_platform_device(port->dev);
1489 struct resource *mmres;
1490 void *ret;
1491
1492 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1493 if (!mmres)
1494 return -ENODEV;
1495
28f65c11 1496 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart");
1da177e4 1497
3d454446 1498 return ret ? 0 : -EBUSY;
1da177e4
LT		 1499}
1500
1501/*
1502 * Configure/autoconfigure the port.
1503 */
1504static void imx_config_port(struct uart_port *port, int flags)
1505{
1506 struct imx_port *sport = (struct imx_port *)port;
1507
1508 if (flags & UART_CONFIG_TYPE &&
1509 imx_request_port(&sport->port) == 0)
1510 sport->port.type = PORT_IMX;
1511}
1512
1513/*
1514 * Verify the new serial_struct (for TIOCSSERIAL).
1515 * The only change we allow are to the flags and type, and
1516 * even then only between PORT_IMX and PORT_UNKNOWN
1517 */
1518static int
1519imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1520{
1521 struct imx_port *sport = (struct imx_port *)port;
1522 int ret = 0;
1523
1524 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1525 ret = -EINVAL;
1526 if (sport->port.irq != ser->irq)
1527 ret = -EINVAL;
1528 if (ser->io_type != UPIO_MEM)
1529 ret = -EINVAL;
1530 if (sport->port.uartclk / 16 != ser->baud_base)
1531 ret = -EINVAL;
a50c44ce 1532 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1da177e4
LT		 1533 ret = -EINVAL;
1534 if (sport->port.iobase != ser->port)
1535 ret = -EINVAL;
1536 if (ser->hub6 != 0)
1537 ret = -EINVAL;
1538 return ret;
1539}
1540
01f56abd
SA		 1541#if defined(CONFIG_CONSOLE_POLL)
1542static int imx_poll_get_char(struct uart_port *port)
1543{
1544 struct imx_port_ucrs old_ucr;
1545 unsigned int status;
1546 unsigned char c;
1547
1548 /* save control registers */
1549 imx_port_ucrs_save(port, &old_ucr);
1550
1551 /* disable interrupts */
1552 writel(UCR1_UARTEN, port->membase + UCR1);
1553 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1554 port->membase + UCR2);
1555 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1556 port->membase + UCR3);
1557
1558 /* poll */
1559 do {
1560 status = readl(port->membase + USR2);
1561 } while (~status & USR2_RDR);
1562
1563 /* read */
1564 c = readl(port->membase + URXD0);
1565
1566 /* restore control registers */
1567 imx_port_ucrs_restore(port, &old_ucr);
1568
1569 return c;
1570}
1571
1572static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1573{
1574 struct imx_port_ucrs old_ucr;
1575 unsigned int status;
1576
1577 /* save control registers */
1578 imx_port_ucrs_save(port, &old_ucr);
1579
1580 /* disable interrupts */
1581 writel(UCR1_UARTEN, port->membase + UCR1);
1582 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1583 port->membase + UCR2);
1584 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1585 port->membase + UCR3);
1586
1587 /* drain */
1588 do {
1589 status = readl(port->membase + USR1);
1590 } while (~status & USR1_TRDY);
1591
1592 /* write */
1593 writel(c, port->membase + URTX0);
1594
1595 /* flush */
1596 do {
1597 status = readl(port->membase + USR2);
1598 } while (~status & USR2_TXDC);
1599
1600 /* restore control registers */
1601 imx_port_ucrs_restore(port, &old_ucr);
1602}
1603#endif
1604
1da177e4
LT		 1605static struct uart_ops imx_pops = {
1606 .tx_empty = imx_tx_empty,
1607 .set_mctrl = imx_set_mctrl,
1608 .get_mctrl = imx_get_mctrl,
1609 .stop_tx = imx_stop_tx,
1610 .start_tx = imx_start_tx,
1611 .stop_rx = imx_stop_rx,
1612 .enable_ms = imx_enable_ms,
1613 .break_ctl = imx_break_ctl,
1614 .startup = imx_startup,
1615 .shutdown = imx_shutdown,
eb56b7ed 1616 .flush_buffer = imx_flush_buffer,
1da177e4
LT		 1617 .set_termios = imx_set_termios,
1618 .type = imx_type,
1619 .release_port = imx_release_port,
1620 .request_port = imx_request_port,
1621 .config_port = imx_config_port,
1622 .verify_port = imx_verify_port,
01f56abd
SA		 1623#if defined(CONFIG_CONSOLE_POLL)
1624 .poll_get_char = imx_poll_get_char,
1625 .poll_put_char = imx_poll_put_char,
1626#endif
1da177e4
LT		 1627};
1628
dbff4e9e 1629static struct imx_port *imx_ports[UART_NR];
1da177e4
LT		 1630
1631#ifdef CONFIG_SERIAL_IMX_CONSOLE
d358788f
RK		 1632static void imx_console_putchar(struct uart_port *port, int ch)
1633{
1634 struct imx_port *sport = (struct imx_port *)port;
ff4bfb21 1635
fe6b540a 1636 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
d358788f 1637 barrier();
ff4bfb21
SH		 1638
1639 writel(ch, sport->port.membase + URTX0);
d358788f 1640}
1da177e4
LT		 1641
1642/*
1643 * Interrupts are disabled on entering
1644 */
1645static void
1646imx_console_write(struct console *co, const char *s, unsigned int count)
1647{
dbff4e9e 1648 struct imx_port *sport = imx_ports[co->index];
0ad5a814
DB		 1649 struct imx_port_ucrs old_ucr;
1650 unsigned int ucr1;
f30e8260 1651 unsigned long flags = 0;
677fe555 1652 int locked = 1;
1cf93e0d
HS		 1653 int retval;
1654
1655 retval = clk_enable(sport->clk_per);
1656 if (retval)
1657 return;
1658 retval = clk_enable(sport->clk_ipg);
1659 if (retval) {
1660 clk_disable(sport->clk_per);
1661 return;
1662 }
9ec1882d 1663
677fe555
TG		 1664 if (sport->port.sysrq)
1665 locked = 0;
1666 else if (oops_in_progress)
1667 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1668 else
1669 spin_lock_irqsave(&sport->port.lock, flags);
1da177e4
LT		 1670
1671 /*
0ad5a814 1672 * First, save UCR1/2/3 and then disable interrupts
1da177e4 1673 */
0ad5a814
DB		 1674 imx_port_ucrs_save(&sport->port, &old_ucr);
1675 ucr1 = old_ucr.ucr1;
1da177e4 1676
fe6b540a
SG		 1677 if (is_imx1_uart(sport))
1678 ucr1 |= IMX1_UCR1_UARTCLKEN;
37d6fb62
SH		 1679 ucr1 |= UCR1_UARTEN;
1680 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1681
1682 writel(ucr1, sport->port.membase + UCR1);
ff4bfb21 1683
0ad5a814 1684 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1da177e4 1685
d358788f 1686 uart_console_write(&sport->port, s, count, imx_console_putchar);
1da177e4
LT		 1687
1688 /*
1689 * Finally, wait for transmitter to become empty
0ad5a814 1690 * and restore UCR1/2/3
1da177e4 1691 */
ff4bfb21 1692 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1da177e4 1693
0ad5a814 1694 imx_port_ucrs_restore(&sport->port, &old_ucr);
9ec1882d 1695
677fe555
TG		 1696 if (locked)
1697 spin_unlock_irqrestore(&sport->port.lock, flags);
1cf93e0d
HS		 1698
1699 clk_disable(sport->clk_ipg);
1700 clk_disable(sport->clk_per);
1da177e4
LT		 1701}
1702
1703/*
1704 * If the port was already initialised (eg, by a boot loader),
1705 * try to determine the current setup.
1706 */
1707static void __init
1708imx_console_get_options(struct imx_port *sport, int *baud,
1709 int *parity, int *bits)
1710{
587897f5 1711
2e2eb509 1712 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1da177e4 1713 /* ok, the port was enabled */
82313e66 1714 unsigned int ucr2, ubir, ubmr, uartclk;
587897f5
SH		 1715 unsigned int baud_raw;
1716 unsigned int ucfr_rfdiv;
1da177e4 1717
ff4bfb21 1718 ucr2 = readl(sport->port.membase + UCR2);
1da177e4
LT		 1719
1720 *parity = 'n';
1721 if (ucr2 & UCR2_PREN) {
1722 if (ucr2 & UCR2_PROE)
1723 *parity = 'o';
1724 else
1725 *parity = 'e';
1726 }
1727
1728 if (ucr2 & UCR2_WS)
1729 *bits = 8;
1730 else
1731 *bits = 7;
1732
ff4bfb21
SH		 1733 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1734 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
587897f5 1735
ff4bfb21 1736 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
587897f5
SH		 1737 if (ucfr_rfdiv == 6)
1738 ucfr_rfdiv = 7;
1739 else
1740 ucfr_rfdiv = 6 - ucfr_rfdiv;
1741
3a9465fa 1742 uartclk = clk_get_rate(sport->clk_per);
587897f5
SH		 1743 uartclk /= ucfr_rfdiv;
1744
1745 { /*
1746 * The next code provides exact computation of
1747 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1748 * without need of float support or long long division,
1749 * which would be required to prevent 32bit arithmetic overflow
1750 */
1751 unsigned int mul = ubir + 1;
1752 unsigned int div = 16 * (ubmr + 1);
1753 unsigned int rem = uartclk % div;
1754
1755 baud_raw = (uartclk / div) * mul;
1756 baud_raw += (rem * mul + div / 2) / div;
1757 *baud = (baud_raw + 50) / 100 * 100;
1758 }
1759
82313e66 1760 if (*baud != baud_raw)
50bbdba3 1761 pr_info("Console IMX rounded baud rate from %d to %d\n",
587897f5 1762 baud_raw, *baud);
1da177e4
LT		 1763 }
1764}
1765
1766static int __init
1767imx_console_setup(struct console *co, char *options)
1768{
1769 struct imx_port *sport;
1770 int baud = 9600;
1771 int bits = 8;
1772 int parity = 'n';
1773 int flow = 'n';
1cf93e0d 1774 int retval;
1da177e4
LT		 1775
1776 /*
1777 * Check whether an invalid uart number has been specified, and
1778 * if so, search for the first available port that does have
1779 * console support.
1780 */
1781 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1782 co->index = 0;
dbff4e9e 1783 sport = imx_ports[co->index];
82313e66 1784 if (sport == NULL)
e76afc4e 1785 return -ENODEV;
1da177e4 1786
1cf93e0d
HS		 1787 /* For setting the registers, we only need to enable the ipg clock. */
1788 retval = clk_prepare_enable(sport->clk_ipg);
1789 if (retval)
1790 goto error_console;
1791
1da177e4
LT		 1792 if (options)
1793 uart_parse_options(options, &baud, &parity, &bits, &flow);
1794 else
1795 imx_console_get_options(sport, &baud, &parity, &bits);
1796
587897f5
SH		 1797 imx_setup_ufcr(sport, 0);
1798
1cf93e0d
HS		 1799 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1800
1801 clk_disable(sport->clk_ipg);
1802 if (retval) {
1803 clk_unprepare(sport->clk_ipg);
1804 goto error_console;
1805 }
1806
1807 retval = clk_prepare(sport->clk_per);
1808 if (retval)
1809 clk_disable_unprepare(sport->clk_ipg);
1810
1811error_console:
1812 return retval;
1da177e4
LT		 1813}
1814
9f4426dd 1815static struct uart_driver imx_reg;
1da177e4 1816static struct console imx_console = {
e3d13ff4 1817 .name = DEV_NAME,
1da177e4
LT		 1818 .write = imx_console_write,
1819 .device = uart_console_device,
1820 .setup = imx_console_setup,
1821 .flags = CON_PRINTBUFFER,
1822 .index = -1,
1823 .data = &imx_reg,
1824};
1825
1da177e4
LT		 1826#define IMX_CONSOLE &imx_console
1827#else
1828#define IMX_CONSOLE NULL
1829#endif
1830
1831static struct uart_driver imx_reg = {
1832 .owner = THIS_MODULE,
1833 .driver_name = DRIVER_NAME,
e3d13ff4 1834 .dev_name = DEV_NAME,
1da177e4
LT		 1835 .major = SERIAL_IMX_MAJOR,
1836 .minor = MINOR_START,
1837 .nr = ARRAY_SIZE(imx_ports),
1838 .cons = IMX_CONSOLE,
1839};
1840
3ae5eaec 1841static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1da177e4 1842{
d3810cd4 1843 struct imx_port *sport = platform_get_drvdata(dev);
db1a9b55
FE		 1844 unsigned int val;
1845
1846 /* enable wakeup from i.MX UART */
1847 val = readl(sport->port.membase + UCR3);
1848 val |= UCR3_AWAKEN;
1849 writel(val, sport->port.membase + UCR3);
1da177e4 1850
034dc4db 1851 uart_suspend_port(&imx_reg, &sport->port);
1da177e4 1852
d3810cd4 1853 return 0;
1da177e4
LT		 1854}
1855
3ae5eaec 1856static int serial_imx_resume(struct platform_device *dev)
1da177e4 1857{
d3810cd4 1858 struct imx_port *sport = platform_get_drvdata(dev);
db1a9b55
FE		 1859 unsigned int val;
1860
1861 /* disable wakeup from i.MX UART */
1862 val = readl(sport->port.membase + UCR3);
1863 val &= ~UCR3_AWAKEN;
1864 writel(val, sport->port.membase + UCR3);
1da177e4 1865
034dc4db 1866 uart_resume_port(&imx_reg, &sport->port);
1da177e4 1867
d3810cd4 1868 return 0;
1da177e4
LT		 1869}
1870
22698aa2 1871#ifdef CONFIG_OF
20bb8095
UKK		 1872/*
1873 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1874 * could successfully get all information from dt or a negative errno.
1875 */
22698aa2
SG		 1876static int serial_imx_probe_dt(struct imx_port *sport,
1877 struct platform_device *pdev)
1878{
1879 struct device_node *np = pdev->dev.of_node;
1880 const struct of_device_id *of_id =
1881 of_match_device(imx_uart_dt_ids, &pdev->dev);
ff05967a 1882 int ret;
22698aa2
SG		 1883
1884 if (!np)
20bb8095
UKK		 1885 /* no device tree device */
1886 return 1;
22698aa2 1887
ff05967a
SG		 1888 ret = of_alias_get_id(np, "serial");
1889 if (ret < 0) {
1890 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
a197a191 1891 return ret;
ff05967a
SG		 1892 }
1893 sport->port.line = ret;
22698aa2
SG		 1894
1895 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1896 sport->have_rtscts = 1;
1897
1898 if (of_get_property(np, "fsl,irda-mode", NULL))
1899 sport->use_irda = 1;
1900
20ff2fe6
HS		 1901 if (of_get_property(np, "fsl,dte-mode", NULL))
1902 sport->dte_mode = 1;
1903
22698aa2
SG		 1904 sport->devdata = of_id->data;
1905
1906 return 0;
1907}
1908#else
1909static inline int serial_imx_probe_dt(struct imx_port *sport,
1910 struct platform_device *pdev)
1911{
20bb8095 1912 return 1;
22698aa2
SG		 1913}
1914#endif
1915
1916static void serial_imx_probe_pdata(struct imx_port *sport,
1917 struct platform_device *pdev)
1918{
574de559 1919 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
22698aa2
SG		 1920
1921 sport->port.line = pdev->id;
1922 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1923
1924 if (!pdata)
1925 return;
1926
1927 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1928 sport->have_rtscts = 1;
1929
1930 if (pdata->flags & IMXUART_IRDA)
1931 sport->use_irda = 1;
1932}
1933
2582d8c1 1934static int serial_imx_probe(struct platform_device *pdev)
1da177e4 1935{
dbff4e9e 1936 struct imx_port *sport;
5b802344 1937 struct imxuart_platform_data *pdata;
dbff4e9e
SH		 1938 void __iomem *base;
1939 int ret = 0;
1940 struct resource *res;
1941
42d34191 1942 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
dbff4e9e
SH		 1943 if (!sport)
1944 return -ENOMEM;
5b802344 1945
22698aa2 1946 ret = serial_imx_probe_dt(sport, pdev);
20bb8095 1947 if (ret > 0)
22698aa2 1948 serial_imx_probe_pdata(sport, pdev);
20bb8095 1949 else if (ret < 0)
42d34191 1950 return ret;
22698aa2 1951
dbff4e9e 1952 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
42d34191
SK		 1953 if (!res)
1954 return -ENODEV;
dbff4e9e 1955
42d34191
SK		 1956 base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE);
1957 if (!base)
1958 return -ENOMEM;
dbff4e9e
SH		 1959
1960 sport->port.dev = &pdev->dev;
1961 sport->port.mapbase = res->start;
1962 sport->port.membase = base;
1963 sport->port.type = PORT_IMX,
1964 sport->port.iotype = UPIO_MEM;
1965 sport->port.irq = platform_get_irq(pdev, 0);
1966 sport->rxirq = platform_get_irq(pdev, 0);
1967 sport->txirq = platform_get_irq(pdev, 1);
1968 sport->rtsirq = platform_get_irq(pdev, 2);
1969 sport->port.fifosize = 32;
1970 sport->port.ops = &imx_pops;
1971 sport->port.flags = UPF_BOOT_AUTOCONF;
dbff4e9e
SH		 1972 init_timer(&sport->timer);
1973 sport->timer.function = imx_timeout;
1974 sport->timer.data = (unsigned long)sport;
38a41fdf 1975
3a9465fa
SH		 1976 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1977 if (IS_ERR(sport->clk_ipg)) {
1978 ret = PTR_ERR(sport->clk_ipg);
833462e9 1979 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
42d34191 1980 return ret;
38a41fdf 1981 }
38a41fdf 1982
3a9465fa
SH		 1983 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1984 if (IS_ERR(sport->clk_per)) {
1985 ret = PTR_ERR(sport->clk_per);
833462e9 1986 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
42d34191 1987 return ret;
3a9465fa
SH		 1988 }
1989
3a9465fa 1990 sport->port.uartclk = clk_get_rate(sport->clk_per);
dbff4e9e 1991
22698aa2 1992 imx_ports[sport->port.line] = sport;
5b802344 1993
574de559 1994 pdata = dev_get_platdata(&pdev->dev);
bbcd18d1 1995 if (pdata && pdata->init) {
c45e7d7b
DA		 1996 ret = pdata->init(pdev);
1997 if (ret)
1cf93e0d 1998 return ret;
c45e7d7b 1999 }
2582d8c1 2000
9f322ad0
DG		 2001 ret = uart_add_one_port(&imx_reg, &sport->port);
2002 if (ret)
2003 goto deinit;
0a86a86b 2004 platform_set_drvdata(pdev, sport);
5b802344 2005
1da177e4 2006 return 0;
9f322ad0 2007deinit:
bbcd18d1 2008 if (pdata && pdata->exit)
9f322ad0 2009 pdata->exit(pdev);
dbff4e9e 2010 return ret;
1da177e4
LT		 2011}
2012
2582d8c1 2013static int serial_imx_remove(struct platform_device *pdev)
1da177e4 2014{
2582d8c1
SH		 2015 struct imxuart_platform_data *pdata;
2016 struct imx_port *sport = platform_get_drvdata(pdev);
1da177e4 2017
574de559 2018 pdata = dev_get_platdata(&pdev->dev);
2582d8c1 2019
3a9465fa
SH		 2020 uart_remove_one_port(&imx_reg, &sport->port);
2021
bbcd18d1 2022 if (pdata && pdata->exit)
2582d8c1
SH		 2023 pdata->exit(pdev);
2024
1da177e4
LT		 2025 return 0;
2026}
2027
3ae5eaec 2028static struct platform_driver serial_imx_driver = {
d3810cd4
OS		 2029 .probe = serial_imx_probe,
2030 .remove = serial_imx_remove,
1da177e4
LT		 2031
2032 .suspend = serial_imx_suspend,
2033 .resume = serial_imx_resume,
fe6b540a 2034 .id_table = imx_uart_devtype,
3ae5eaec 2035 .driver = {
d3810cd4 2036 .name = "imx-uart",
e169c139 2037 .owner = THIS_MODULE,
22698aa2 2038 .of_match_table = imx_uart_dt_ids,
3ae5eaec 2039 },
1da177e4
LT		 2040};
2041
2042static int __init imx_serial_init(void)
2043{
2044 int ret;
2045
50bbdba3 2046 pr_info("Serial: IMX driver\n");
1da177e4 2047
1da177e4
LT		 2048 ret = uart_register_driver(&imx_reg);
2049 if (ret)
2050 return ret;
2051
3ae5eaec 2052 ret = platform_driver_register(&serial_imx_driver);
1da177e4
LT		 2053 if (ret != 0)
2054 uart_unregister_driver(&imx_reg);
2055
f227824e 2056 return ret;
1da177e4
LT		 2057}
2058
2059static void __exit imx_serial_exit(void)
2060{
c889b896 2061 platform_driver_unregister(&serial_imx_driver);
4b300c36 2062 uart_unregister_driver(&imx_reg);
1da177e4
LT		 2063}
2064
2065module_init(imx_serial_init);
2066module_exit(imx_serial_exit);
2067
2068MODULE_AUTHOR("Sascha Hauer");
2069MODULE_DESCRIPTION("IMX generic serial port driver");
2070MODULE_LICENSE("GPL");
e169c139 2071MODULE_ALIAS("platform:imx-uart");
Linux kernel - Deliverables
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