Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * m32r_sio.c | |
3 | * | |
4 | * Driver for M32R serial ports | |
5 | * | |
6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
7 | * Based on drivers/serial/8250.c. | |
8 | * | |
9 | * Copyright (C) 2001 Russell King. | |
10 | * Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | */ | |
17 | ||
18 | /* | |
19 | * A note about mapbase / membase | |
20 | * | |
21 | * mapbase is the physical address of the IO port. Currently, we don't | |
22 | * support this very well, and it may well be dropped from this driver | |
23 | * in future. As such, mapbase should be NULL. | |
24 | * | |
25 | * membase is an 'ioremapped' cookie. This is compatible with the old | |
26 | * serial.c driver, and is currently the preferred form. | |
27 | */ | |
1da177e4 LT |
28 | |
29 | #if defined(CONFIG_SERIAL_M32R_SIO_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
30 | #define SUPPORT_SYSRQ | |
31 | #endif | |
32 | ||
33 | #include <linux/module.h> | |
34 | #include <linux/tty.h> | |
ee160a38 | 35 | #include <linux/tty_flip.h> |
1da177e4 LT |
36 | #include <linux/ioport.h> |
37 | #include <linux/init.h> | |
38 | #include <linux/console.h> | |
39 | #include <linux/sysrq.h> | |
40 | #include <linux/serial.h> | |
1da177e4 LT |
41 | #include <linux/delay.h> |
42 | ||
43 | #include <asm/m32r.h> | |
44 | #include <asm/io.h> | |
45 | #include <asm/irq.h> | |
46 | ||
1da177e4 LT |
47 | #define BAUD_RATE 115200 |
48 | ||
49 | #include <linux/serial_core.h> | |
50 | #include "m32r_sio.h" | |
51 | #include "m32r_sio_reg.h" | |
52 | ||
53 | /* | |
54 | * Debugging. | |
55 | */ | |
56 | #if 0 | |
57 | #define DEBUG_AUTOCONF(fmt...) printk(fmt) | |
58 | #else | |
59 | #define DEBUG_AUTOCONF(fmt...) do { } while (0) | |
60 | #endif | |
61 | ||
62 | #if 0 | |
63 | #define DEBUG_INTR(fmt...) printk(fmt) | |
64 | #else | |
65 | #define DEBUG_INTR(fmt...) do { } while (0) | |
66 | #endif | |
67 | ||
68 | #define PASS_LIMIT 256 | |
69 | ||
de6cc84f | 70 | #define BASE_BAUD 115200 |
1da177e4 LT |
71 | |
72 | /* Standard COM flags */ | |
59a675b2 | 73 | #define STD_COM_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST) |
1da177e4 LT |
74 | |
75 | /* | |
76 | * SERIAL_PORT_DFNS tells us about built-in ports that have no | |
77 | * standard enumeration mechanism. Platforms that can find all | |
78 | * serial ports via mechanisms like ACPI or PCI need not supply it. | |
79 | */ | |
1da177e4 LT |
80 | #if defined(CONFIG_PLAT_USRV) |
81 | ||
82 | #define SERIAL_PORT_DFNS \ | |
83 | /* UART CLK PORT IRQ FLAGS */ \ | |
84 | { 0, BASE_BAUD, 0x3F8, PLD_IRQ_UART0, STD_COM_FLAGS }, /* ttyS0 */ \ | |
85 | { 0, BASE_BAUD, 0x2F8, PLD_IRQ_UART1, STD_COM_FLAGS }, /* ttyS1 */ | |
86 | ||
87 | #else /* !CONFIG_PLAT_USRV */ | |
88 | ||
89 | #if defined(CONFIG_SERIAL_M32R_PLDSIO) | |
90 | #define SERIAL_PORT_DFNS \ | |
91 | { 0, BASE_BAUD, ((unsigned long)PLD_ESIO0CR), PLD_IRQ_SIO0_RCV, \ | |
92 | STD_COM_FLAGS }, /* ttyS0 */ | |
93 | #else | |
94 | #define SERIAL_PORT_DFNS \ | |
95 | { 0, BASE_BAUD, M32R_SIO_OFFSET, M32R_IRQ_SIO0_R, \ | |
96 | STD_COM_FLAGS }, /* ttyS0 */ | |
97 | #endif | |
98 | ||
99 | #endif /* !CONFIG_PLAT_USRV */ | |
100 | ||
101 | static struct old_serial_port old_serial_port[] = { | |
de6cc84f | 102 | SERIAL_PORT_DFNS |
1da177e4 LT |
103 | }; |
104 | ||
105 | #define UART_NR ARRAY_SIZE(old_serial_port) | |
106 | ||
107 | struct uart_sio_port { | |
108 | struct uart_port port; | |
109 | struct timer_list timer; /* "no irq" timer */ | |
110 | struct list_head list; /* ports on this IRQ */ | |
111 | unsigned short rev; | |
112 | unsigned char acr; | |
113 | unsigned char ier; | |
114 | unsigned char lcr; | |
115 | unsigned char mcr_mask; /* mask of user bits */ | |
116 | unsigned char mcr_force; /* mask of forced bits */ | |
117 | unsigned char lsr_break_flag; | |
118 | ||
119 | /* | |
120 | * We provide a per-port pm hook. | |
121 | */ | |
122 | void (*pm)(struct uart_port *port, | |
123 | unsigned int state, unsigned int old); | |
124 | }; | |
125 | ||
126 | struct irq_info { | |
127 | spinlock_t lock; | |
128 | struct list_head *head; | |
129 | }; | |
130 | ||
131 | static struct irq_info irq_lists[NR_IRQS]; | |
132 | ||
1da177e4 LT |
133 | #ifdef CONFIG_SERIAL_M32R_PLDSIO |
134 | ||
135 | #define __sio_in(x) inw((unsigned long)(x)) | |
136 | #define __sio_out(v,x) outw((v),(unsigned long)(x)) | |
137 | ||
138 | static inline void sio_set_baud_rate(unsigned long baud) | |
139 | { | |
140 | unsigned short sbaud; | |
141 | sbaud = (boot_cpu_data.bus_clock / (baud * 4))-1; | |
142 | __sio_out(sbaud, PLD_ESIO0BAUR); | |
143 | } | |
144 | ||
145 | static void sio_reset(void) | |
146 | { | |
147 | unsigned short tmp; | |
148 | ||
149 | tmp = __sio_in(PLD_ESIO0RXB); | |
150 | tmp = __sio_in(PLD_ESIO0RXB); | |
151 | tmp = __sio_in(PLD_ESIO0CR); | |
152 | sio_set_baud_rate(BAUD_RATE); | |
153 | __sio_out(0x0300, PLD_ESIO0CR); | |
154 | __sio_out(0x0003, PLD_ESIO0CR); | |
155 | } | |
156 | ||
157 | static void sio_init(void) | |
158 | { | |
159 | unsigned short tmp; | |
160 | ||
161 | tmp = __sio_in(PLD_ESIO0RXB); | |
162 | tmp = __sio_in(PLD_ESIO0RXB); | |
163 | tmp = __sio_in(PLD_ESIO0CR); | |
164 | __sio_out(0x0300, PLD_ESIO0CR); | |
165 | __sio_out(0x0003, PLD_ESIO0CR); | |
166 | } | |
167 | ||
168 | static void sio_error(int *status) | |
169 | { | |
170 | printk("SIO0 error[%04x]\n", *status); | |
171 | do { | |
172 | sio_init(); | |
173 | } while ((*status = __sio_in(PLD_ESIO0CR)) != 3); | |
174 | } | |
175 | ||
176 | #else /* not CONFIG_SERIAL_M32R_PLDSIO */ | |
177 | ||
178 | #define __sio_in(x) inl(x) | |
179 | #define __sio_out(v,x) outl((v),(x)) | |
180 | ||
181 | static inline void sio_set_baud_rate(unsigned long baud) | |
182 | { | |
183 | unsigned long i, j; | |
184 | ||
185 | i = boot_cpu_data.bus_clock / (baud * 16); | |
186 | j = (boot_cpu_data.bus_clock - (i * baud * 16)) / baud; | |
187 | i -= 1; | |
188 | j = (j + 1) >> 1; | |
189 | ||
190 | __sio_out(i, M32R_SIO0_BAUR_PORTL); | |
191 | __sio_out(j, M32R_SIO0_RBAUR_PORTL); | |
192 | } | |
193 | ||
194 | static void sio_reset(void) | |
195 | { | |
196 | __sio_out(0x00000300, M32R_SIO0_CR_PORTL); /* init status */ | |
197 | __sio_out(0x00000800, M32R_SIO0_MOD1_PORTL); /* 8bit */ | |
198 | __sio_out(0x00000080, M32R_SIO0_MOD0_PORTL); /* 1stop non */ | |
199 | sio_set_baud_rate(BAUD_RATE); | |
200 | __sio_out(0x00000000, M32R_SIO0_TRCR_PORTL); | |
201 | __sio_out(0x00000003, M32R_SIO0_CR_PORTL); /* RXCEN */ | |
202 | } | |
203 | ||
204 | static void sio_init(void) | |
205 | { | |
206 | unsigned int tmp; | |
207 | ||
208 | tmp = __sio_in(M32R_SIO0_RXB_PORTL); | |
209 | tmp = __sio_in(M32R_SIO0_RXB_PORTL); | |
210 | tmp = __sio_in(M32R_SIO0_STS_PORTL); | |
211 | __sio_out(0x00000003, M32R_SIO0_CR_PORTL); | |
212 | } | |
213 | ||
214 | static void sio_error(int *status) | |
215 | { | |
216 | printk("SIO0 error[%04x]\n", *status); | |
217 | do { | |
218 | sio_init(); | |
219 | } while ((*status = __sio_in(M32R_SIO0_CR_PORTL)) != 3); | |
220 | } | |
221 | ||
222 | #endif /* CONFIG_SERIAL_M32R_PLDSIO */ | |
223 | ||
41c28ff1 | 224 | static unsigned int sio_in(struct uart_sio_port *up, int offset) |
1da177e4 LT |
225 | { |
226 | return __sio_in(up->port.iobase + offset); | |
227 | } | |
228 | ||
41c28ff1 | 229 | static void sio_out(struct uart_sio_port *up, int offset, int value) |
1da177e4 LT |
230 | { |
231 | __sio_out(value, up->port.iobase + offset); | |
232 | } | |
233 | ||
41c28ff1 | 234 | static unsigned int serial_in(struct uart_sio_port *up, int offset) |
1da177e4 LT |
235 | { |
236 | if (!offset) | |
237 | return 0; | |
238 | ||
239 | return __sio_in(offset); | |
240 | } | |
241 | ||
41c28ff1 | 242 | static void serial_out(struct uart_sio_port *up, int offset, int value) |
1da177e4 LT |
243 | { |
244 | if (!offset) | |
245 | return; | |
246 | ||
247 | __sio_out(value, offset); | |
248 | } | |
249 | ||
b129a8cc | 250 | static void m32r_sio_stop_tx(struct uart_port *port) |
1da177e4 | 251 | { |
b6b30d67 FF |
252 | struct uart_sio_port *up = |
253 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
254 | |
255 | if (up->ier & UART_IER_THRI) { | |
256 | up->ier &= ~UART_IER_THRI; | |
257 | serial_out(up, UART_IER, up->ier); | |
258 | } | |
259 | } | |
260 | ||
b129a8cc | 261 | static void m32r_sio_start_tx(struct uart_port *port) |
1da177e4 LT |
262 | { |
263 | #ifdef CONFIG_SERIAL_M32R_PLDSIO | |
b6b30d67 FF |
264 | struct uart_sio_port *up = |
265 | container_of(port, struct uart_sio_port, port); | |
ebd2c8f6 | 266 | struct circ_buf *xmit = &up->port.state->xmit; |
1da177e4 LT |
267 | |
268 | if (!(up->ier & UART_IER_THRI)) { | |
269 | up->ier |= UART_IER_THRI; | |
270 | serial_out(up, UART_IER, up->ier); | |
c557d392 PH |
271 | if (!uart_circ_empty(xmit)) { |
272 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
273 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
274 | up->port.icount.tx++; | |
275 | } | |
1da177e4 LT |
276 | } |
277 | while((serial_in(up, UART_LSR) & UART_EMPTY) != UART_EMPTY); | |
278 | #else | |
b6b30d67 FF |
279 | struct uart_sio_port *up = |
280 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
281 | |
282 | if (!(up->ier & UART_IER_THRI)) { | |
283 | up->ier |= UART_IER_THRI; | |
284 | serial_out(up, UART_IER, up->ier); | |
285 | } | |
286 | #endif | |
287 | } | |
288 | ||
289 | static void m32r_sio_stop_rx(struct uart_port *port) | |
290 | { | |
b6b30d67 FF |
291 | struct uart_sio_port *up = |
292 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
293 | |
294 | up->ier &= ~UART_IER_RLSI; | |
295 | up->port.read_status_mask &= ~UART_LSR_DR; | |
296 | serial_out(up, UART_IER, up->ier); | |
297 | } | |
298 | ||
299 | static void m32r_sio_enable_ms(struct uart_port *port) | |
300 | { | |
b6b30d67 FF |
301 | struct uart_sio_port *up = |
302 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
303 | |
304 | up->ier |= UART_IER_MSI; | |
305 | serial_out(up, UART_IER, up->ier); | |
306 | } | |
307 | ||
7d12e780 | 308 | static void receive_chars(struct uart_sio_port *up, int *status) |
1da177e4 | 309 | { |
92a19f9c | 310 | struct tty_port *port = &up->port.state->port; |
1da177e4 | 311 | unsigned char ch; |
33f0f88f | 312 | unsigned char flag; |
1da177e4 LT |
313 | int max_count = 256; |
314 | ||
315 | do { | |
1da177e4 | 316 | ch = sio_in(up, SIORXB); |
33f0f88f | 317 | flag = TTY_NORMAL; |
1da177e4 LT |
318 | up->port.icount.rx++; |
319 | ||
320 | if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | | |
321 | UART_LSR_FE | UART_LSR_OE))) { | |
322 | /* | |
323 | * For statistics only | |
324 | */ | |
325 | if (*status & UART_LSR_BI) { | |
326 | *status &= ~(UART_LSR_FE | UART_LSR_PE); | |
327 | up->port.icount.brk++; | |
328 | /* | |
329 | * We do the SysRQ and SAK checking | |
330 | * here because otherwise the break | |
331 | * may get masked by ignore_status_mask | |
332 | * or read_status_mask. | |
333 | */ | |
334 | if (uart_handle_break(&up->port)) | |
335 | goto ignore_char; | |
336 | } else if (*status & UART_LSR_PE) | |
337 | up->port.icount.parity++; | |
338 | else if (*status & UART_LSR_FE) | |
339 | up->port.icount.frame++; | |
340 | if (*status & UART_LSR_OE) | |
341 | up->port.icount.overrun++; | |
342 | ||
343 | /* | |
344 | * Mask off conditions which should be ingored. | |
345 | */ | |
346 | *status &= up->port.read_status_mask; | |
347 | ||
348 | if (up->port.line == up->port.cons->index) { | |
349 | /* Recover the break flag from console xmit */ | |
350 | *status |= up->lsr_break_flag; | |
351 | up->lsr_break_flag = 0; | |
352 | } | |
353 | ||
354 | if (*status & UART_LSR_BI) { | |
355 | DEBUG_INTR("handling break...."); | |
33f0f88f | 356 | flag = TTY_BREAK; |
1da177e4 | 357 | } else if (*status & UART_LSR_PE) |
33f0f88f | 358 | flag = TTY_PARITY; |
1da177e4 | 359 | else if (*status & UART_LSR_FE) |
33f0f88f | 360 | flag = TTY_FRAME; |
1da177e4 | 361 | } |
7d12e780 | 362 | if (uart_handle_sysrq_char(&up->port, ch)) |
1da177e4 | 363 | goto ignore_char; |
33f0f88f | 364 | if ((*status & up->port.ignore_status_mask) == 0) |
92a19f9c | 365 | tty_insert_flip_char(port, ch, flag); |
33f0f88f AC |
366 | |
367 | if (*status & UART_LSR_OE) { | |
1da177e4 LT |
368 | /* |
369 | * Overrun is special, since it's reported | |
370 | * immediately, and doesn't affect the current | |
371 | * character. | |
372 | */ | |
92a19f9c | 373 | tty_insert_flip_char(port, 0, TTY_OVERRUN); |
1da177e4 LT |
374 | } |
375 | ignore_char: | |
376 | *status = serial_in(up, UART_LSR); | |
377 | } while ((*status & UART_LSR_DR) && (max_count-- > 0)); | |
af89f837 VK |
378 | |
379 | spin_unlock(&up->port.lock); | |
2e124b4a | 380 | tty_flip_buffer_push(port); |
af89f837 | 381 | spin_lock(&up->port.lock); |
1da177e4 LT |
382 | } |
383 | ||
41c28ff1 | 384 | static void transmit_chars(struct uart_sio_port *up) |
1da177e4 | 385 | { |
ebd2c8f6 | 386 | struct circ_buf *xmit = &up->port.state->xmit; |
1da177e4 LT |
387 | int count; |
388 | ||
389 | if (up->port.x_char) { | |
390 | #ifndef CONFIG_SERIAL_M32R_PLDSIO /* XXX */ | |
391 | serial_out(up, UART_TX, up->port.x_char); | |
392 | #endif | |
393 | up->port.icount.tx++; | |
394 | up->port.x_char = 0; | |
395 | return; | |
396 | } | |
397 | if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { | |
b129a8cc | 398 | m32r_sio_stop_tx(&up->port); |
1da177e4 LT |
399 | return; |
400 | } | |
401 | ||
402 | count = up->port.fifosize; | |
403 | do { | |
404 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
405 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
406 | up->port.icount.tx++; | |
407 | if (uart_circ_empty(xmit)) | |
408 | break; | |
022d917d | 409 | while (!(serial_in(up, UART_LSR) & UART_LSR_THRE)); |
1da177e4 LT |
410 | |
411 | } while (--count > 0); | |
412 | ||
413 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
414 | uart_write_wakeup(&up->port); | |
415 | ||
416 | DEBUG_INTR("THRE..."); | |
417 | ||
418 | if (uart_circ_empty(xmit)) | |
b129a8cc | 419 | m32r_sio_stop_tx(&up->port); |
1da177e4 LT |
420 | } |
421 | ||
422 | /* | |
423 | * This handles the interrupt from one port. | |
424 | */ | |
425 | static inline void m32r_sio_handle_port(struct uart_sio_port *up, | |
7d12e780 | 426 | unsigned int status) |
1da177e4 LT |
427 | { |
428 | DEBUG_INTR("status = %x...", status); | |
429 | ||
430 | if (status & 0x04) | |
7d12e780 | 431 | receive_chars(up, &status); |
1da177e4 LT |
432 | if (status & 0x01) |
433 | transmit_chars(up); | |
434 | } | |
435 | ||
436 | /* | |
437 | * This is the serial driver's interrupt routine. | |
438 | * | |
439 | * Arjan thinks the old way was overly complex, so it got simplified. | |
440 | * Alan disagrees, saying that need the complexity to handle the weird | |
441 | * nature of ISA shared interrupts. (This is a special exception.) | |
442 | * | |
443 | * In order to handle ISA shared interrupts properly, we need to check | |
444 | * that all ports have been serviced, and therefore the ISA interrupt | |
445 | * line has been de-asserted. | |
446 | * | |
447 | * This means we need to loop through all ports. checking that they | |
448 | * don't have an interrupt pending. | |
449 | */ | |
7d12e780 | 450 | static irqreturn_t m32r_sio_interrupt(int irq, void *dev_id) |
1da177e4 LT |
451 | { |
452 | struct irq_info *i = dev_id; | |
453 | struct list_head *l, *end = NULL; | |
454 | int pass_counter = 0; | |
455 | ||
456 | DEBUG_INTR("m32r_sio_interrupt(%d)...", irq); | |
457 | ||
458 | #ifdef CONFIG_SERIAL_M32R_PLDSIO | |
459 | // if (irq == PLD_IRQ_SIO0_SND) | |
460 | // irq = PLD_IRQ_SIO0_RCV; | |
461 | #else | |
462 | if (irq == M32R_IRQ_SIO0_S) | |
463 | irq = M32R_IRQ_SIO0_R; | |
464 | #endif | |
465 | ||
466 | spin_lock(&i->lock); | |
467 | ||
468 | l = i->head; | |
469 | do { | |
470 | struct uart_sio_port *up; | |
471 | unsigned int sts; | |
472 | ||
473 | up = list_entry(l, struct uart_sio_port, list); | |
474 | ||
475 | sts = sio_in(up, SIOSTS); | |
476 | if (sts & 0x5) { | |
477 | spin_lock(&up->port.lock); | |
7d12e780 | 478 | m32r_sio_handle_port(up, sts); |
1da177e4 LT |
479 | spin_unlock(&up->port.lock); |
480 | ||
481 | end = NULL; | |
482 | } else if (end == NULL) | |
483 | end = l; | |
484 | ||
485 | l = l->next; | |
486 | ||
487 | if (l == i->head && pass_counter++ > PASS_LIMIT) { | |
488 | if (sts & 0xe0) | |
489 | sio_error(&sts); | |
490 | break; | |
491 | } | |
492 | } while (l != end); | |
493 | ||
494 | spin_unlock(&i->lock); | |
495 | ||
496 | DEBUG_INTR("end.\n"); | |
497 | ||
498 | return IRQ_HANDLED; | |
499 | } | |
500 | ||
501 | /* | |
502 | * To support ISA shared interrupts, we need to have one interrupt | |
503 | * handler that ensures that the IRQ line has been deasserted | |
504 | * before returning. Failing to do this will result in the IRQ | |
505 | * line being stuck active, and, since ISA irqs are edge triggered, | |
506 | * no more IRQs will be seen. | |
507 | */ | |
508 | static void serial_do_unlink(struct irq_info *i, struct uart_sio_port *up) | |
509 | { | |
510 | spin_lock_irq(&i->lock); | |
511 | ||
512 | if (!list_empty(i->head)) { | |
513 | if (i->head == &up->list) | |
514 | i->head = i->head->next; | |
515 | list_del(&up->list); | |
516 | } else { | |
517 | BUG_ON(i->head != &up->list); | |
518 | i->head = NULL; | |
519 | } | |
520 | ||
521 | spin_unlock_irq(&i->lock); | |
522 | } | |
523 | ||
524 | static int serial_link_irq_chain(struct uart_sio_port *up) | |
525 | { | |
526 | struct irq_info *i = irq_lists + up->port.irq; | |
dab8f496 | 527 | int ret, irq_flags = 0; |
1da177e4 LT |
528 | |
529 | spin_lock_irq(&i->lock); | |
530 | ||
531 | if (i->head) { | |
532 | list_add(&up->list, i->head); | |
533 | spin_unlock_irq(&i->lock); | |
534 | ||
535 | ret = 0; | |
536 | } else { | |
537 | INIT_LIST_HEAD(&up->list); | |
538 | i->head = &up->list; | |
539 | spin_unlock_irq(&i->lock); | |
540 | ||
541 | ret = request_irq(up->port.irq, m32r_sio_interrupt, | |
542 | irq_flags, "SIO0-RX", i); | |
543 | ret |= request_irq(up->port.irq + 1, m32r_sio_interrupt, | |
544 | irq_flags, "SIO0-TX", i); | |
545 | if (ret < 0) | |
546 | serial_do_unlink(i, up); | |
547 | } | |
548 | ||
549 | return ret; | |
550 | } | |
551 | ||
552 | static void serial_unlink_irq_chain(struct uart_sio_port *up) | |
553 | { | |
554 | struct irq_info *i = irq_lists + up->port.irq; | |
555 | ||
556 | BUG_ON(i->head == NULL); | |
557 | ||
558 | if (list_empty(i->head)) { | |
559 | free_irq(up->port.irq, i); | |
560 | free_irq(up->port.irq + 1, i); | |
561 | } | |
562 | ||
563 | serial_do_unlink(i, up); | |
564 | } | |
565 | ||
566 | /* | |
567 | * This function is used to handle ports that do not have an interrupt. | |
568 | */ | |
569 | static void m32r_sio_timeout(unsigned long data) | |
570 | { | |
571 | struct uart_sio_port *up = (struct uart_sio_port *)data; | |
572 | unsigned int timeout; | |
573 | unsigned int sts; | |
574 | ||
575 | sts = sio_in(up, SIOSTS); | |
576 | if (sts & 0x5) { | |
577 | spin_lock(&up->port.lock); | |
9c8e7f5c | 578 | m32r_sio_handle_port(up, sts); |
1da177e4 LT |
579 | spin_unlock(&up->port.lock); |
580 | } | |
581 | ||
582 | timeout = up->port.timeout; | |
583 | timeout = timeout > 6 ? (timeout / 2 - 2) : 1; | |
584 | mod_timer(&up->timer, jiffies + timeout); | |
585 | } | |
586 | ||
587 | static unsigned int m32r_sio_tx_empty(struct uart_port *port) | |
588 | { | |
b6b30d67 FF |
589 | struct uart_sio_port *up = |
590 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
591 | unsigned long flags; |
592 | unsigned int ret; | |
593 | ||
594 | spin_lock_irqsave(&up->port.lock, flags); | |
595 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; | |
596 | spin_unlock_irqrestore(&up->port.lock, flags); | |
597 | ||
598 | return ret; | |
599 | } | |
600 | ||
601 | static unsigned int m32r_sio_get_mctrl(struct uart_port *port) | |
602 | { | |
603 | return 0; | |
604 | } | |
605 | ||
606 | static void m32r_sio_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
607 | { | |
608 | ||
609 | } | |
610 | ||
611 | static void m32r_sio_break_ctl(struct uart_port *port, int break_state) | |
612 | { | |
613 | ||
614 | } | |
615 | ||
616 | static int m32r_sio_startup(struct uart_port *port) | |
617 | { | |
b6b30d67 FF |
618 | struct uart_sio_port *up = |
619 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
620 | int retval; |
621 | ||
622 | sio_init(); | |
623 | ||
624 | /* | |
625 | * If the "interrupt" for this port doesn't correspond with any | |
626 | * hardware interrupt, we use a timer-based system. The original | |
627 | * driver used to do this with IRQ0. | |
628 | */ | |
d4e33fac | 629 | if (!up->port.irq) { |
1da177e4 LT |
630 | unsigned int timeout = up->port.timeout; |
631 | ||
632 | timeout = timeout > 6 ? (timeout / 2 - 2) : 1; | |
633 | ||
634 | up->timer.data = (unsigned long)up; | |
635 | mod_timer(&up->timer, jiffies + timeout); | |
636 | } else { | |
637 | retval = serial_link_irq_chain(up); | |
638 | if (retval) | |
639 | return retval; | |
640 | } | |
641 | ||
642 | /* | |
643 | * Finally, enable interrupts. Note: Modem status interrupts | |
644 | * are set via set_termios(), which will be occurring imminently | |
645 | * anyway, so we don't enable them here. | |
646 | * - M32R_SIO: 0x0c | |
647 | * - M32R_PLDSIO: 0x04 | |
648 | */ | |
649 | up->ier = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; | |
650 | sio_out(up, SIOTRCR, up->ier); | |
651 | ||
652 | /* | |
653 | * And clear the interrupt registers again for luck. | |
654 | */ | |
655 | sio_reset(); | |
656 | ||
657 | return 0; | |
658 | } | |
659 | ||
660 | static void m32r_sio_shutdown(struct uart_port *port) | |
661 | { | |
b6b30d67 FF |
662 | struct uart_sio_port *up = |
663 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
664 | |
665 | /* | |
666 | * Disable interrupts from this port | |
667 | */ | |
668 | up->ier = 0; | |
669 | sio_out(up, SIOTRCR, 0); | |
670 | ||
671 | /* | |
672 | * Disable break condition and FIFOs | |
673 | */ | |
674 | ||
675 | sio_init(); | |
676 | ||
d4e33fac | 677 | if (!up->port.irq) |
1da177e4 LT |
678 | del_timer_sync(&up->timer); |
679 | else | |
680 | serial_unlink_irq_chain(up); | |
681 | } | |
682 | ||
683 | static unsigned int m32r_sio_get_divisor(struct uart_port *port, | |
684 | unsigned int baud) | |
685 | { | |
686 | return uart_get_divisor(port, baud); | |
687 | } | |
688 | ||
689 | static void m32r_sio_set_termios(struct uart_port *port, | |
606d099c | 690 | struct ktermios *termios, struct ktermios *old) |
1da177e4 | 691 | { |
b6b30d67 FF |
692 | struct uart_sio_port *up = |
693 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
694 | unsigned char cval = 0; |
695 | unsigned long flags; | |
696 | unsigned int baud, quot; | |
697 | ||
698 | switch (termios->c_cflag & CSIZE) { | |
699 | case CS5: | |
0a8b80c5 | 700 | cval = UART_LCR_WLEN5; |
1da177e4 LT |
701 | break; |
702 | case CS6: | |
0a8b80c5 | 703 | cval = UART_LCR_WLEN6; |
1da177e4 LT |
704 | break; |
705 | case CS7: | |
0a8b80c5 | 706 | cval = UART_LCR_WLEN7; |
1da177e4 LT |
707 | break; |
708 | default: | |
709 | case CS8: | |
0a8b80c5 | 710 | cval = UART_LCR_WLEN8; |
1da177e4 LT |
711 | break; |
712 | } | |
713 | ||
714 | if (termios->c_cflag & CSTOPB) | |
0a8b80c5 | 715 | cval |= UART_LCR_STOP; |
1da177e4 LT |
716 | if (termios->c_cflag & PARENB) |
717 | cval |= UART_LCR_PARITY; | |
718 | if (!(termios->c_cflag & PARODD)) | |
719 | cval |= UART_LCR_EPAR; | |
720 | #ifdef CMSPAR | |
721 | if (termios->c_cflag & CMSPAR) | |
722 | cval |= UART_LCR_SPAR; | |
723 | #endif | |
724 | ||
725 | /* | |
726 | * Ask the core to calculate the divisor for us. | |
727 | */ | |
728 | #ifdef CONFIG_SERIAL_M32R_PLDSIO | |
729 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/4); | |
730 | #else | |
731 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
732 | #endif | |
733 | quot = m32r_sio_get_divisor(port, baud); | |
734 | ||
735 | /* | |
736 | * Ok, we're now changing the port state. Do it with | |
737 | * interrupts disabled. | |
738 | */ | |
739 | spin_lock_irqsave(&up->port.lock, flags); | |
740 | ||
741 | sio_set_baud_rate(baud); | |
742 | ||
743 | /* | |
744 | * Update the per-port timeout. | |
745 | */ | |
746 | uart_update_timeout(port, termios->c_cflag, baud); | |
747 | ||
748 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
749 | if (termios->c_iflag & INPCK) | |
750 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
ef8b9ddc | 751 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
1da177e4 LT |
752 | up->port.read_status_mask |= UART_LSR_BI; |
753 | ||
754 | /* | |
755 | * Characteres to ignore | |
756 | */ | |
757 | up->port.ignore_status_mask = 0; | |
758 | if (termios->c_iflag & IGNPAR) | |
759 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
760 | if (termios->c_iflag & IGNBRK) { | |
761 | up->port.ignore_status_mask |= UART_LSR_BI; | |
762 | /* | |
763 | * If we're ignoring parity and break indicators, | |
764 | * ignore overruns too (for real raw support). | |
765 | */ | |
766 | if (termios->c_iflag & IGNPAR) | |
767 | up->port.ignore_status_mask |= UART_LSR_OE; | |
768 | } | |
769 | ||
770 | /* | |
771 | * ignore all characters if CREAD is not set | |
772 | */ | |
773 | if ((termios->c_cflag & CREAD) == 0) | |
774 | up->port.ignore_status_mask |= UART_LSR_DR; | |
775 | ||
776 | /* | |
777 | * CTS flow control flag and modem status interrupts | |
778 | */ | |
779 | up->ier &= ~UART_IER_MSI; | |
780 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
781 | up->ier |= UART_IER_MSI; | |
782 | ||
783 | serial_out(up, UART_IER, up->ier); | |
784 | ||
785 | up->lcr = cval; /* Save LCR */ | |
786 | spin_unlock_irqrestore(&up->port.lock, flags); | |
787 | } | |
788 | ||
789 | static void m32r_sio_pm(struct uart_port *port, unsigned int state, | |
790 | unsigned int oldstate) | |
791 | { | |
b6b30d67 FF |
792 | struct uart_sio_port *up = |
793 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
794 | |
795 | if (up->pm) | |
796 | up->pm(port, state, oldstate); | |
797 | } | |
798 | ||
799 | /* | |
800 | * Resource handling. This is complicated by the fact that resources | |
801 | * depend on the port type. Maybe we should be claiming the standard | |
802 | * 8250 ports, and then trying to get other resources as necessary? | |
803 | */ | |
804 | static int | |
805 | m32r_sio_request_std_resource(struct uart_sio_port *up, struct resource **res) | |
806 | { | |
807 | unsigned int size = 8 << up->port.regshift; | |
808 | #ifndef CONFIG_SERIAL_M32R_PLDSIO | |
809 | unsigned long start; | |
810 | #endif | |
811 | int ret = 0; | |
812 | ||
813 | switch (up->port.iotype) { | |
814 | case UPIO_MEM: | |
815 | if (up->port.mapbase) { | |
816 | #ifdef CONFIG_SERIAL_M32R_PLDSIO | |
817 | *res = request_mem_region(up->port.mapbase, size, "serial"); | |
818 | #else | |
819 | start = up->port.mapbase; | |
820 | *res = request_mem_region(start, size, "serial"); | |
821 | #endif | |
822 | if (!*res) | |
823 | ret = -EBUSY; | |
824 | } | |
825 | break; | |
826 | ||
827 | case UPIO_PORT: | |
828 | *res = request_region(up->port.iobase, size, "serial"); | |
829 | if (!*res) | |
830 | ret = -EBUSY; | |
831 | break; | |
832 | } | |
833 | return ret; | |
834 | } | |
835 | ||
836 | static void m32r_sio_release_port(struct uart_port *port) | |
837 | { | |
b6b30d67 FF |
838 | struct uart_sio_port *up = |
839 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
840 | unsigned long start, offset = 0, size = 0; |
841 | ||
842 | size <<= up->port.regshift; | |
843 | ||
844 | switch (up->port.iotype) { | |
845 | case UPIO_MEM: | |
846 | if (up->port.mapbase) { | |
847 | /* | |
848 | * Unmap the area. | |
849 | */ | |
850 | iounmap(up->port.membase); | |
851 | up->port.membase = NULL; | |
852 | ||
853 | start = up->port.mapbase; | |
854 | ||
855 | if (size) | |
856 | release_mem_region(start + offset, size); | |
857 | release_mem_region(start, 8 << up->port.regshift); | |
858 | } | |
859 | break; | |
860 | ||
861 | case UPIO_PORT: | |
862 | start = up->port.iobase; | |
863 | ||
864 | if (size) | |
865 | release_region(start + offset, size); | |
866 | release_region(start + offset, 8 << up->port.regshift); | |
867 | break; | |
868 | ||
869 | default: | |
870 | break; | |
871 | } | |
872 | } | |
873 | ||
874 | static int m32r_sio_request_port(struct uart_port *port) | |
875 | { | |
b6b30d67 FF |
876 | struct uart_sio_port *up = |
877 | container_of(port, struct uart_sio_port, port); | |
1da177e4 LT |
878 | struct resource *res = NULL; |
879 | int ret = 0; | |
880 | ||
881 | ret = m32r_sio_request_std_resource(up, &res); | |
882 | ||
883 | /* | |
884 | * If we have a mapbase, then request that as well. | |
885 | */ | |
886 | if (ret == 0 && up->port.flags & UPF_IOREMAP) { | |
28f65c11 | 887 | int size = resource_size(res); |
1da177e4 LT |
888 | |
889 | up->port.membase = ioremap(up->port.mapbase, size); | |
890 | if (!up->port.membase) | |
891 | ret = -ENOMEM; | |
892 | } | |
893 | ||
894 | if (ret < 0) { | |
895 | if (res) | |
896 | release_resource(res); | |
897 | } | |
898 | ||
899 | return ret; | |
900 | } | |
901 | ||
1e806c50 | 902 | static void m32r_sio_config_port(struct uart_port *port, int unused) |
1da177e4 | 903 | { |
b6b30d67 FF |
904 | struct uart_sio_port *up = |
905 | container_of(port, struct uart_sio_port, port); | |
1e806c50 | 906 | unsigned long flags; |
1da177e4 LT |
907 | |
908 | spin_lock_irqsave(&up->port.lock, flags); | |
909 | ||
b8ede90c | 910 | up->port.fifosize = 1; |
1da177e4 LT |
911 | |
912 | spin_unlock_irqrestore(&up->port.lock, flags); | |
913 | } | |
914 | ||
915 | static int | |
916 | m32r_sio_verify_port(struct uart_port *port, struct serial_struct *ser) | |
917 | { | |
b8ede90c | 918 | if (ser->irq >= nr_irqs || ser->irq < 0 || ser->baud_base < 9600) |
1da177e4 LT |
919 | return -EINVAL; |
920 | return 0; | |
921 | } | |
922 | ||
1da177e4 LT |
923 | static struct uart_ops m32r_sio_pops = { |
924 | .tx_empty = m32r_sio_tx_empty, | |
925 | .set_mctrl = m32r_sio_set_mctrl, | |
926 | .get_mctrl = m32r_sio_get_mctrl, | |
927 | .stop_tx = m32r_sio_stop_tx, | |
928 | .start_tx = m32r_sio_start_tx, | |
929 | .stop_rx = m32r_sio_stop_rx, | |
930 | .enable_ms = m32r_sio_enable_ms, | |
931 | .break_ctl = m32r_sio_break_ctl, | |
932 | .startup = m32r_sio_startup, | |
933 | .shutdown = m32r_sio_shutdown, | |
934 | .set_termios = m32r_sio_set_termios, | |
935 | .pm = m32r_sio_pm, | |
1da177e4 LT |
936 | .release_port = m32r_sio_release_port, |
937 | .request_port = m32r_sio_request_port, | |
938 | .config_port = m32r_sio_config_port, | |
939 | .verify_port = m32r_sio_verify_port, | |
940 | }; | |
941 | ||
942 | static struct uart_sio_port m32r_sio_ports[UART_NR]; | |
943 | ||
944 | static void __init m32r_sio_init_ports(void) | |
945 | { | |
946 | struct uart_sio_port *up; | |
947 | static int first = 1; | |
948 | int i; | |
949 | ||
950 | if (!first) | |
951 | return; | |
952 | first = 0; | |
953 | ||
954 | for (i = 0, up = m32r_sio_ports; i < ARRAY_SIZE(old_serial_port); | |
955 | i++, up++) { | |
956 | up->port.iobase = old_serial_port[i].port; | |
957 | up->port.irq = irq_canonicalize(old_serial_port[i].irq); | |
958 | up->port.uartclk = old_serial_port[i].baud_base * 16; | |
959 | up->port.flags = old_serial_port[i].flags; | |
960 | up->port.membase = old_serial_port[i].iomem_base; | |
961 | up->port.iotype = old_serial_port[i].io_type; | |
962 | up->port.regshift = old_serial_port[i].iomem_reg_shift; | |
963 | up->port.ops = &m32r_sio_pops; | |
964 | } | |
965 | } | |
966 | ||
967 | static void __init m32r_sio_register_ports(struct uart_driver *drv) | |
968 | { | |
969 | int i; | |
970 | ||
971 | m32r_sio_init_ports(); | |
972 | ||
973 | for (i = 0; i < UART_NR; i++) { | |
974 | struct uart_sio_port *up = &m32r_sio_ports[i]; | |
975 | ||
976 | up->port.line = i; | |
977 | up->port.ops = &m32r_sio_pops; | |
978 | init_timer(&up->timer); | |
979 | up->timer.function = m32r_sio_timeout; | |
980 | ||
59087384 PG |
981 | up->mcr_mask = ~0; |
982 | up->mcr_force = 0; | |
1da177e4 LT |
983 | |
984 | uart_add_one_port(drv, &up->port); | |
985 | } | |
986 | } | |
987 | ||
988 | #ifdef CONFIG_SERIAL_M32R_SIO_CONSOLE | |
989 | ||
990 | /* | |
991 | * Wait for transmitter & holding register to empty | |
992 | */ | |
9cdb9332 | 993 | static void wait_for_xmitr(struct uart_sio_port *up) |
1da177e4 LT |
994 | { |
995 | unsigned int status, tmout = 10000; | |
996 | ||
997 | /* Wait up to 10ms for the character(s) to be sent. */ | |
998 | do { | |
999 | status = sio_in(up, SIOSTS); | |
1000 | ||
1001 | if (--tmout == 0) | |
1002 | break; | |
1003 | udelay(1); | |
1004 | } while ((status & UART_EMPTY) != UART_EMPTY); | |
1005 | ||
1006 | /* Wait up to 1s for flow control if necessary */ | |
1007 | if (up->port.flags & UPF_CONS_FLOW) { | |
1008 | tmout = 1000000; | |
1009 | while (--tmout) | |
1010 | udelay(1); | |
1011 | } | |
1012 | } | |
1013 | ||
d358788f RK |
1014 | static void m32r_sio_console_putchar(struct uart_port *port, int ch) |
1015 | { | |
b6b30d67 FF |
1016 | struct uart_sio_port *up = |
1017 | container_of(port, struct uart_sio_port, port); | |
d358788f RK |
1018 | |
1019 | wait_for_xmitr(up); | |
1020 | sio_out(up, SIOTXB, ch); | |
1021 | } | |
1022 | ||
1da177e4 LT |
1023 | /* |
1024 | * Print a string to the serial port trying not to disturb | |
1025 | * any possible real use of the port... | |
1026 | * | |
1027 | * The console_lock must be held when we get here. | |
1028 | */ | |
1029 | static void m32r_sio_console_write(struct console *co, const char *s, | |
1030 | unsigned int count) | |
1031 | { | |
1032 | struct uart_sio_port *up = &m32r_sio_ports[co->index]; | |
1033 | unsigned int ier; | |
1da177e4 LT |
1034 | |
1035 | /* | |
1036 | * First save the UER then disable the interrupts | |
1037 | */ | |
1038 | ier = sio_in(up, SIOTRCR); | |
1039 | sio_out(up, SIOTRCR, 0); | |
1040 | ||
d358788f | 1041 | uart_console_write(&up->port, s, count, m32r_sio_console_putchar); |
1da177e4 LT |
1042 | |
1043 | /* | |
1044 | * Finally, wait for transmitter to become empty | |
1045 | * and restore the IER | |
1046 | */ | |
1047 | wait_for_xmitr(up); | |
1048 | sio_out(up, SIOTRCR, ier); | |
1049 | } | |
1050 | ||
1051 | static int __init m32r_sio_console_setup(struct console *co, char *options) | |
1052 | { | |
1053 | struct uart_port *port; | |
1054 | int baud = 9600; | |
1055 | int bits = 8; | |
1056 | int parity = 'n'; | |
1057 | int flow = 'n'; | |
1058 | ||
1059 | /* | |
1060 | * Check whether an invalid uart number has been specified, and | |
1061 | * if so, search for the first available port that does have | |
1062 | * console support. | |
1063 | */ | |
1064 | if (co->index >= UART_NR) | |
1065 | co->index = 0; | |
1066 | port = &m32r_sio_ports[co->index].port; | |
1067 | ||
1068 | /* | |
1069 | * Temporary fix. | |
1070 | */ | |
1071 | spin_lock_init(&port->lock); | |
1072 | ||
1073 | if (options) | |
1074 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1075 | ||
1076 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1077 | } | |
1078 | ||
a828b8e4 | 1079 | static struct uart_driver m32r_sio_reg; |
1da177e4 LT |
1080 | static struct console m32r_sio_console = { |
1081 | .name = "ttyS", | |
1082 | .write = m32r_sio_console_write, | |
1083 | .device = uart_console_device, | |
1084 | .setup = m32r_sio_console_setup, | |
1085 | .flags = CON_PRINTBUFFER, | |
1086 | .index = -1, | |
1087 | .data = &m32r_sio_reg, | |
1088 | }; | |
1089 | ||
1090 | static int __init m32r_sio_console_init(void) | |
1091 | { | |
1092 | sio_reset(); | |
1093 | sio_init(); | |
1094 | m32r_sio_init_ports(); | |
1095 | register_console(&m32r_sio_console); | |
1096 | return 0; | |
1097 | } | |
1098 | console_initcall(m32r_sio_console_init); | |
1099 | ||
1100 | #define M32R_SIO_CONSOLE &m32r_sio_console | |
1101 | #else | |
1102 | #define M32R_SIO_CONSOLE NULL | |
1103 | #endif | |
1104 | ||
1105 | static struct uart_driver m32r_sio_reg = { | |
1106 | .owner = THIS_MODULE, | |
1107 | .driver_name = "sio", | |
1da177e4 LT |
1108 | .dev_name = "ttyS", |
1109 | .major = TTY_MAJOR, | |
1110 | .minor = 64, | |
1111 | .nr = UART_NR, | |
1112 | .cons = M32R_SIO_CONSOLE, | |
1113 | }; | |
1114 | ||
1115 | /** | |
1116 | * m32r_sio_suspend_port - suspend one serial port | |
1117 | * @line: serial line number | |
1118 | * | |
1119 | * Suspend one serial port. | |
1120 | */ | |
1121 | void m32r_sio_suspend_port(int line) | |
1122 | { | |
1123 | uart_suspend_port(&m32r_sio_reg, &m32r_sio_ports[line].port); | |
1124 | } | |
1125 | ||
1126 | /** | |
1127 | * m32r_sio_resume_port - resume one serial port | |
1128 | * @line: serial line number | |
1129 | * | |
1130 | * Resume one serial port. | |
1131 | */ | |
1132 | void m32r_sio_resume_port(int line) | |
1133 | { | |
1134 | uart_resume_port(&m32r_sio_reg, &m32r_sio_ports[line].port); | |
1135 | } | |
1136 | ||
1137 | static int __init m32r_sio_init(void) | |
1138 | { | |
1139 | int ret, i; | |
1140 | ||
d87a6d95 | 1141 | printk(KERN_INFO "Serial: M32R SIO driver\n"); |
1da177e4 | 1142 | |
a62c4133 | 1143 | for (i = 0; i < nr_irqs; i++) |
1da177e4 LT |
1144 | spin_lock_init(&irq_lists[i].lock); |
1145 | ||
1146 | ret = uart_register_driver(&m32r_sio_reg); | |
1147 | if (ret >= 0) | |
1148 | m32r_sio_register_ports(&m32r_sio_reg); | |
1149 | ||
1150 | return ret; | |
1151 | } | |
1152 | ||
1153 | static void __exit m32r_sio_exit(void) | |
1154 | { | |
1155 | int i; | |
1156 | ||
1157 | for (i = 0; i < UART_NR; i++) | |
1158 | uart_remove_one_port(&m32r_sio_reg, &m32r_sio_ports[i].port); | |
1159 | ||
1160 | uart_unregister_driver(&m32r_sio_reg); | |
1161 | } | |
1162 | ||
1163 | module_init(m32r_sio_init); | |
1164 | module_exit(m32r_sio_exit); | |
1165 | ||
1166 | EXPORT_SYMBOL(m32r_sio_suspend_port); | |
1167 | EXPORT_SYMBOL(m32r_sio_resume_port); | |
1168 | ||
1169 | MODULE_LICENSE("GPL"); | |
d87a6d95 | 1170 | MODULE_DESCRIPTION("Generic M32R SIO serial driver"); |