Commit | Line | Data |
---|---|---|
f6544418 | 1 | /* |
003236d9 | 2 | * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver |
f6544418 | 3 | * |
e97e1556 | 4 | * Copyright (C) 2012-2014 Alexander Shiyan <shc_work@mail.ru> |
f6544418 AS |
5 | * |
6 | * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> | |
7 | * Based on max3110.c, by Feng Tang <feng.tang@intel.com> | |
8 | * Based on max3107.c, by Aavamobile | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License, or | |
13 | * (at your option) any later version. | |
14 | */ | |
15 | ||
f6544418 | 16 | #include <linux/module.h> |
10d8b34a | 17 | #include <linux/delay.h> |
f6544418 | 18 | #include <linux/device.h> |
10d8b34a | 19 | #include <linux/bitops.h> |
d3a8a252 | 20 | #include <linux/clk.h> |
f6544418 AS |
21 | #include <linux/serial_core.h> |
22 | #include <linux/serial.h> | |
23 | #include <linux/tty.h> | |
24 | #include <linux/tty_flip.h> | |
25 | #include <linux/regmap.h> | |
26 | #include <linux/gpio.h> | |
27 | #include <linux/spi/spi.h> | |
10d8b34a | 28 | |
f6544418 AS |
29 | #include <linux/platform_data/max310x.h> |
30 | ||
10d8b34a | 31 | #define MAX310X_NAME "max310x" |
f6544418 AS |
32 | #define MAX310X_MAJOR 204 |
33 | #define MAX310X_MINOR 209 | |
34 | ||
35 | /* MAX310X register definitions */ | |
36 | #define MAX310X_RHR_REG (0x00) /* RX FIFO */ | |
37 | #define MAX310X_THR_REG (0x00) /* TX FIFO */ | |
38 | #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */ | |
39 | #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ | |
40 | #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ | |
41 | #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ | |
10d8b34a AS |
42 | #define MAX310X_REG_05 (0x05) |
43 | #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */ | |
f6544418 AS |
44 | #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ |
45 | #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ | |
46 | #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ | |
47 | #define MAX310X_MODE1_REG (0x09) /* MODE1 */ | |
48 | #define MAX310X_MODE2_REG (0x0a) /* MODE2 */ | |
49 | #define MAX310X_LCR_REG (0x0b) /* LCR */ | |
50 | #define MAX310X_RXTO_REG (0x0c) /* RX timeout */ | |
51 | #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ | |
52 | #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */ | |
53 | #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ | |
54 | #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ | |
55 | #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ | |
56 | #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ | |
57 | #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ | |
58 | #define MAX310X_XON1_REG (0x14) /* XON1 character */ | |
59 | #define MAX310X_XON2_REG (0x15) /* XON2 character */ | |
60 | #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ | |
61 | #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ | |
62 | #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ | |
63 | #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */ | |
64 | #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */ | |
65 | #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ | |
66 | #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ | |
67 | #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ | |
68 | #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ | |
10d8b34a AS |
69 | #define MAX310X_REG_1F (0x1f) |
70 | ||
71 | #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */ | |
72 | ||
73 | #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */ | |
74 | #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */ | |
75 | ||
76 | /* Extended registers */ | |
77 | #define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */ | |
f6544418 AS |
78 | |
79 | /* IRQ register bits */ | |
80 | #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ | |
81 | #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ | |
82 | #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ | |
83 | #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ | |
84 | #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ | |
85 | #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ | |
86 | #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ | |
87 | #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ | |
88 | ||
89 | /* LSR register bits */ | |
90 | #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ | |
91 | #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ | |
92 | #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ | |
93 | #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ | |
94 | #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ | |
95 | #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ | |
96 | #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ | |
97 | ||
98 | /* Special character register bits */ | |
99 | #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ | |
100 | #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ | |
101 | #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ | |
102 | #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ | |
103 | #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ | |
104 | #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ | |
105 | ||
106 | /* Status register bits */ | |
107 | #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ | |
108 | #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ | |
109 | #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ | |
110 | #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ | |
111 | #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ | |
112 | #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ | |
113 | ||
114 | /* MODE1 register bits */ | |
115 | #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ | |
116 | #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ | |
117 | #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ | |
118 | #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ | |
119 | #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ | |
120 | #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ | |
121 | #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ | |
122 | #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ | |
123 | ||
124 | /* MODE2 register bits */ | |
125 | #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ | |
126 | #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ | |
127 | #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ | |
128 | #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ | |
129 | #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ | |
130 | #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ | |
131 | #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ | |
132 | #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ | |
133 | ||
134 | /* LCR register bits */ | |
135 | #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ | |
136 | #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 | |
137 | * | |
138 | * Word length bits table: | |
139 | * 00 -> 5 bit words | |
140 | * 01 -> 6 bit words | |
141 | * 10 -> 7 bit words | |
142 | * 11 -> 8 bit words | |
143 | */ | |
144 | #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit | |
145 | * | |
146 | * STOP length bit table: | |
147 | * 0 -> 1 stop bit | |
148 | * 1 -> 1-1.5 stop bits if | |
149 | * word length is 5, | |
150 | * 2 stop bits otherwise | |
151 | */ | |
152 | #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ | |
153 | #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ | |
154 | #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ | |
155 | #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ | |
156 | #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ | |
157 | #define MAX310X_LCR_WORD_LEN_5 (0x00) | |
158 | #define MAX310X_LCR_WORD_LEN_6 (0x01) | |
159 | #define MAX310X_LCR_WORD_LEN_7 (0x02) | |
160 | #define MAX310X_LCR_WORD_LEN_8 (0x03) | |
161 | ||
162 | /* IRDA register bits */ | |
163 | #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ | |
164 | #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ | |
165 | #define MAX310X_IRDA_SHORTIR_BIT (1 << 2) /* Short SIR mode enable */ | |
166 | #define MAX310X_IRDA_MIR_BIT (1 << 3) /* MIR mode enable */ | |
167 | #define MAX310X_IRDA_RXINV_BIT (1 << 4) /* RX logic inversion enable */ | |
168 | #define MAX310X_IRDA_TXINV_BIT (1 << 5) /* TX logic inversion enable */ | |
169 | ||
170 | /* Flow control trigger level register masks */ | |
171 | #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */ | |
172 | #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */ | |
173 | #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) | |
174 | #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) | |
175 | ||
176 | /* FIFO interrupt trigger level register masks */ | |
177 | #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */ | |
178 | #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */ | |
179 | #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) | |
180 | #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) | |
181 | ||
182 | /* Flow control register bits */ | |
183 | #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ | |
184 | #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ | |
185 | #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs | |
186 | * are used in conjunction with | |
187 | * XOFF2 for definition of | |
188 | * special character */ | |
189 | #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ | |
190 | #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ | |
191 | #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 | |
192 | * | |
193 | * SWFLOW bits 1 & 0 table: | |
194 | * 00 -> no transmitter flow | |
195 | * control | |
196 | * 01 -> receiver compares | |
197 | * XON2 and XOFF2 | |
198 | * and controls | |
199 | * transmitter | |
200 | * 10 -> receiver compares | |
201 | * XON1 and XOFF1 | |
202 | * and controls | |
203 | * transmitter | |
204 | * 11 -> receiver compares | |
205 | * XON1, XON2, XOFF1 and | |
206 | * XOFF2 and controls | |
207 | * transmitter | |
208 | */ | |
209 | #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ | |
210 | #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 | |
211 | * | |
212 | * SWFLOW bits 3 & 2 table: | |
213 | * 00 -> no received flow | |
214 | * control | |
215 | * 01 -> transmitter generates | |
216 | * XON2 and XOFF2 | |
217 | * 10 -> transmitter generates | |
218 | * XON1 and XOFF1 | |
219 | * 11 -> transmitter generates | |
220 | * XON1, XON2, XOFF1 and | |
221 | * XOFF2 | |
222 | */ | |
223 | ||
224 | /* GPIO configuration register bits */ | |
225 | #define MAX310X_GPIOCFG_GP0OUT_BIT (1 << 0) /* GPIO 0 output enable */ | |
226 | #define MAX310X_GPIOCFG_GP1OUT_BIT (1 << 1) /* GPIO 1 output enable */ | |
227 | #define MAX310X_GPIOCFG_GP2OUT_BIT (1 << 2) /* GPIO 2 output enable */ | |
228 | #define MAX310X_GPIOCFG_GP3OUT_BIT (1 << 3) /* GPIO 3 output enable */ | |
229 | #define MAX310X_GPIOCFG_GP0OD_BIT (1 << 4) /* GPIO 0 open-drain enable */ | |
230 | #define MAX310X_GPIOCFG_GP1OD_BIT (1 << 5) /* GPIO 1 open-drain enable */ | |
231 | #define MAX310X_GPIOCFG_GP2OD_BIT (1 << 6) /* GPIO 2 open-drain enable */ | |
232 | #define MAX310X_GPIOCFG_GP3OD_BIT (1 << 7) /* GPIO 3 open-drain enable */ | |
233 | ||
234 | /* GPIO DATA register bits */ | |
235 | #define MAX310X_GPIODATA_GP0OUT_BIT (1 << 0) /* GPIO 0 output value */ | |
236 | #define MAX310X_GPIODATA_GP1OUT_BIT (1 << 1) /* GPIO 1 output value */ | |
237 | #define MAX310X_GPIODATA_GP2OUT_BIT (1 << 2) /* GPIO 2 output value */ | |
238 | #define MAX310X_GPIODATA_GP3OUT_BIT (1 << 3) /* GPIO 3 output value */ | |
239 | #define MAX310X_GPIODATA_GP0IN_BIT (1 << 4) /* GPIO 0 input value */ | |
240 | #define MAX310X_GPIODATA_GP1IN_BIT (1 << 5) /* GPIO 1 input value */ | |
241 | #define MAX310X_GPIODATA_GP2IN_BIT (1 << 6) /* GPIO 2 input value */ | |
242 | #define MAX310X_GPIODATA_GP3IN_BIT (1 << 7) /* GPIO 3 input value */ | |
243 | ||
244 | /* PLL configuration register masks */ | |
245 | #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */ | |
246 | #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */ | |
247 | ||
248 | /* Baud rate generator configuration register bits */ | |
249 | #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ | |
250 | #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ | |
251 | ||
252 | /* Clock source register bits */ | |
253 | #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ | |
254 | #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ | |
255 | #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ | |
256 | #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ | |
257 | #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ | |
258 | ||
10d8b34a AS |
259 | /* Global commands */ |
260 | #define MAX310X_EXTREG_ENBL (0xce) | |
261 | #define MAX310X_EXTREG_DSBL (0xcd) | |
262 | ||
f6544418 AS |
263 | /* Misc definitions */ |
264 | #define MAX310X_FIFO_SIZE (128) | |
10d8b34a | 265 | #define MAX310x_REV_MASK (0xfc) |
f6544418 AS |
266 | |
267 | /* MAX3107 specific */ | |
268 | #define MAX3107_REV_ID (0xa0) | |
10d8b34a | 269 | |
21fc509f AS |
270 | /* MAX3109 specific */ |
271 | #define MAX3109_REV_ID (0xc0) | |
272 | ||
003236d9 AS |
273 | /* MAX14830 specific */ |
274 | #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */ | |
275 | #define MAX14830_REV_ID (0xb0) | |
276 | ||
10d8b34a AS |
277 | struct max310x_devtype { |
278 | char name[9]; | |
279 | int nr; | |
280 | int (*detect)(struct device *); | |
281 | void (*power)(struct uart_port *, int); | |
f6544418 AS |
282 | }; |
283 | ||
10d8b34a | 284 | struct max310x_one { |
f6544418 | 285 | struct uart_port port; |
10d8b34a | 286 | struct work_struct tx_work; |
e7b8a3ce | 287 | struct work_struct md_work; |
10d8b34a | 288 | }; |
f6544418 | 289 | |
10d8b34a AS |
290 | struct max310x_port { |
291 | struct uart_driver uart; | |
292 | struct max310x_devtype *devtype; | |
293 | struct regmap *regmap; | |
10d8b34a | 294 | struct mutex mutex; |
d3a8a252 | 295 | struct clk *clk; |
10d8b34a | 296 | struct max310x_pdata *pdata; |
f6544418 AS |
297 | #ifdef CONFIG_GPIOLIB |
298 | struct gpio_chip gpio; | |
299 | #endif | |
10d8b34a AS |
300 | struct max310x_one p[0]; |
301 | }; | |
f6544418 | 302 | |
10d8b34a AS |
303 | static u8 max310x_port_read(struct uart_port *port, u8 reg) |
304 | { | |
305 | struct max310x_port *s = dev_get_drvdata(port->dev); | |
306 | unsigned int val = 0; | |
f6544418 | 307 | |
10d8b34a | 308 | regmap_read(s->regmap, port->iobase + reg, &val); |
f6544418 | 309 | |
10d8b34a AS |
310 | return val; |
311 | } | |
f6544418 | 312 | |
10d8b34a AS |
313 | static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) |
314 | { | |
315 | struct max310x_port *s = dev_get_drvdata(port->dev); | |
316 | ||
317 | regmap_write(s->regmap, port->iobase + reg, val); | |
318 | } | |
319 | ||
320 | static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) | |
321 | { | |
322 | struct max310x_port *s = dev_get_drvdata(port->dev); | |
323 | ||
324 | regmap_update_bits(s->regmap, port->iobase + reg, mask, val); | |
325 | } | |
326 | ||
327 | static int max3107_detect(struct device *dev) | |
328 | { | |
329 | struct max310x_port *s = dev_get_drvdata(dev); | |
330 | unsigned int val = 0; | |
331 | int ret; | |
332 | ||
333 | ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); | |
334 | if (ret) | |
335 | return ret; | |
336 | ||
337 | if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) { | |
338 | dev_err(dev, | |
339 | "%s ID 0x%02x does not match\n", s->devtype->name, val); | |
340 | return -ENODEV; | |
341 | } | |
342 | ||
343 | return 0; | |
344 | } | |
345 | ||
346 | static int max3108_detect(struct device *dev) | |
347 | { | |
348 | struct max310x_port *s = dev_get_drvdata(dev); | |
349 | unsigned int val = 0; | |
350 | int ret; | |
351 | ||
352 | /* MAX3108 have not REV ID register, we just check default value | |
353 | * from clocksource register to make sure everything works. | |
354 | */ | |
355 | ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); | |
356 | if (ret) | |
357 | return ret; | |
358 | ||
359 | if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) { | |
360 | dev_err(dev, "%s not present\n", s->devtype->name); | |
361 | return -ENODEV; | |
362 | } | |
363 | ||
364 | return 0; | |
365 | } | |
366 | ||
21fc509f AS |
367 | static int max3109_detect(struct device *dev) |
368 | { | |
369 | struct max310x_port *s = dev_get_drvdata(dev); | |
370 | unsigned int val = 0; | |
371 | int ret; | |
372 | ||
373 | ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); | |
374 | if (ret) | |
375 | return ret; | |
376 | ||
377 | if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) { | |
378 | dev_err(dev, | |
379 | "%s ID 0x%02x does not match\n", s->devtype->name, val); | |
380 | return -ENODEV; | |
381 | } | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
10d8b34a AS |
386 | static void max310x_power(struct uart_port *port, int on) |
387 | { | |
388 | max310x_port_update(port, MAX310X_MODE1_REG, | |
389 | MAX310X_MODE1_FORCESLEEP_BIT, | |
390 | on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT); | |
391 | if (on) | |
392 | msleep(50); | |
393 | } | |
394 | ||
003236d9 AS |
395 | static int max14830_detect(struct device *dev) |
396 | { | |
397 | struct max310x_port *s = dev_get_drvdata(dev); | |
398 | unsigned int val = 0; | |
399 | int ret; | |
400 | ||
401 | ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, | |
402 | MAX310X_EXTREG_ENBL); | |
403 | if (ret) | |
404 | return ret; | |
405 | ||
406 | regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val); | |
407 | regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL); | |
408 | if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) { | |
409 | dev_err(dev, | |
410 | "%s ID 0x%02x does not match\n", s->devtype->name, val); | |
411 | return -ENODEV; | |
412 | } | |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
417 | static void max14830_power(struct uart_port *port, int on) | |
418 | { | |
419 | max310x_port_update(port, MAX310X_BRGCFG_REG, | |
420 | MAX14830_BRGCFG_CLKDIS_BIT, | |
421 | on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT); | |
422 | if (on) | |
423 | msleep(50); | |
424 | } | |
425 | ||
10d8b34a AS |
426 | static const struct max310x_devtype max3107_devtype = { |
427 | .name = "MAX3107", | |
428 | .nr = 1, | |
429 | .detect = max3107_detect, | |
430 | .power = max310x_power, | |
f6544418 AS |
431 | }; |
432 | ||
10d8b34a AS |
433 | static const struct max310x_devtype max3108_devtype = { |
434 | .name = "MAX3108", | |
435 | .nr = 1, | |
436 | .detect = max3108_detect, | |
437 | .power = max310x_power, | |
438 | }; | |
439 | ||
21fc509f AS |
440 | static const struct max310x_devtype max3109_devtype = { |
441 | .name = "MAX3109", | |
442 | .nr = 2, | |
443 | .detect = max3109_detect, | |
444 | .power = max310x_power, | |
445 | }; | |
446 | ||
003236d9 AS |
447 | static const struct max310x_devtype max14830_devtype = { |
448 | .name = "MAX14830", | |
449 | .nr = 4, | |
450 | .detect = max14830_detect, | |
451 | .power = max14830_power, | |
452 | }; | |
453 | ||
10d8b34a | 454 | static bool max310x_reg_writeable(struct device *dev, unsigned int reg) |
f6544418 | 455 | { |
10d8b34a | 456 | switch (reg & 0x1f) { |
f6544418 AS |
457 | case MAX310X_IRQSTS_REG: |
458 | case MAX310X_LSR_IRQSTS_REG: | |
459 | case MAX310X_SPCHR_IRQSTS_REG: | |
460 | case MAX310X_STS_IRQSTS_REG: | |
461 | case MAX310X_TXFIFOLVL_REG: | |
462 | case MAX310X_RXFIFOLVL_REG: | |
f6544418 AS |
463 | return false; |
464 | default: | |
465 | break; | |
466 | } | |
467 | ||
468 | return true; | |
469 | } | |
470 | ||
471 | static bool max310x_reg_volatile(struct device *dev, unsigned int reg) | |
472 | { | |
10d8b34a | 473 | switch (reg & 0x1f) { |
f6544418 AS |
474 | case MAX310X_RHR_REG: |
475 | case MAX310X_IRQSTS_REG: | |
476 | case MAX310X_LSR_IRQSTS_REG: | |
477 | case MAX310X_SPCHR_IRQSTS_REG: | |
478 | case MAX310X_STS_IRQSTS_REG: | |
479 | case MAX310X_TXFIFOLVL_REG: | |
480 | case MAX310X_RXFIFOLVL_REG: | |
481 | case MAX310X_GPIODATA_REG: | |
10d8b34a AS |
482 | case MAX310X_BRGDIVLSB_REG: |
483 | case MAX310X_REG_05: | |
484 | case MAX310X_REG_1F: | |
f6544418 AS |
485 | return true; |
486 | default: | |
487 | break; | |
488 | } | |
489 | ||
490 | return false; | |
491 | } | |
492 | ||
493 | static bool max310x_reg_precious(struct device *dev, unsigned int reg) | |
494 | { | |
10d8b34a | 495 | switch (reg & 0x1f) { |
f6544418 AS |
496 | case MAX310X_RHR_REG: |
497 | case MAX310X_IRQSTS_REG: | |
498 | case MAX310X_SPCHR_IRQSTS_REG: | |
499 | case MAX310X_STS_IRQSTS_REG: | |
500 | return true; | |
501 | default: | |
502 | break; | |
503 | } | |
504 | ||
505 | return false; | |
506 | } | |
507 | ||
e97e1556 | 508 | static int max310x_set_baud(struct uart_port *port, int baud) |
f6544418 | 509 | { |
e97e1556 | 510 | unsigned int mode = 0, clk = port->uartclk, div = clk / baud; |
f6544418 | 511 | |
e97e1556 AS |
512 | /* Check for minimal value for divider */ |
513 | if (div < 16) | |
514 | div = 16; | |
515 | ||
516 | if (clk % baud && (div / 16) < 0x8000) { | |
f6544418 AS |
517 | /* Mode x2 */ |
518 | mode = MAX310X_BRGCFG_2XMODE_BIT; | |
e97e1556 AS |
519 | clk = port->uartclk * 2; |
520 | div = clk / baud; | |
521 | ||
522 | if (clk % baud && (div / 16) < 0x8000) { | |
523 | /* Mode x4 */ | |
524 | mode = MAX310X_BRGCFG_4XMODE_BIT; | |
525 | clk = port->uartclk * 4; | |
526 | div = clk / baud; | |
527 | } | |
f6544418 AS |
528 | } |
529 | ||
10d8b34a AS |
530 | max310x_port_write(port, MAX310X_BRGDIVMSB_REG, (div / 16) >> 8); |
531 | max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div / 16); | |
532 | max310x_port_write(port, MAX310X_BRGCFG_REG, (div % 16) | mode); | |
e97e1556 AS |
533 | |
534 | return DIV_ROUND_CLOSEST(clk, div); | |
f6544418 AS |
535 | } |
536 | ||
9671f099 | 537 | static int max310x_update_best_err(unsigned long f, long *besterr) |
f6544418 AS |
538 | { |
539 | /* Use baudrate 115200 for calculate error */ | |
540 | long err = f % (115200 * 16); | |
541 | ||
542 | if ((*besterr < 0) || (*besterr > err)) { | |
543 | *besterr = err; | |
544 | return 0; | |
545 | } | |
546 | ||
547 | return 1; | |
548 | } | |
549 | ||
d3a8a252 AS |
550 | static int max310x_set_ref_clk(struct max310x_port *s, unsigned long freq, |
551 | bool xtal) | |
f6544418 AS |
552 | { |
553 | unsigned int div, clksrc, pllcfg = 0; | |
554 | long besterr = -1; | |
d3a8a252 | 555 | unsigned long fdiv, fmul, bestfreq = freq; |
f6544418 AS |
556 | |
557 | /* First, update error without PLL */ | |
d3a8a252 | 558 | max310x_update_best_err(freq, &besterr); |
f6544418 AS |
559 | |
560 | /* Try all possible PLL dividers */ | |
561 | for (div = 1; (div <= 63) && besterr; div++) { | |
d3a8a252 | 562 | fdiv = DIV_ROUND_CLOSEST(freq, div); |
f6544418 AS |
563 | |
564 | /* Try multiplier 6 */ | |
565 | fmul = fdiv * 6; | |
566 | if ((fdiv >= 500000) && (fdiv <= 800000)) | |
567 | if (!max310x_update_best_err(fmul, &besterr)) { | |
568 | pllcfg = (0 << 6) | div; | |
569 | bestfreq = fmul; | |
570 | } | |
571 | /* Try multiplier 48 */ | |
572 | fmul = fdiv * 48; | |
573 | if ((fdiv >= 850000) && (fdiv <= 1200000)) | |
574 | if (!max310x_update_best_err(fmul, &besterr)) { | |
575 | pllcfg = (1 << 6) | div; | |
576 | bestfreq = fmul; | |
577 | } | |
578 | /* Try multiplier 96 */ | |
579 | fmul = fdiv * 96; | |
580 | if ((fdiv >= 425000) && (fdiv <= 1000000)) | |
581 | if (!max310x_update_best_err(fmul, &besterr)) { | |
582 | pllcfg = (2 << 6) | div; | |
583 | bestfreq = fmul; | |
584 | } | |
585 | /* Try multiplier 144 */ | |
586 | fmul = fdiv * 144; | |
587 | if ((fdiv >= 390000) && (fdiv <= 667000)) | |
588 | if (!max310x_update_best_err(fmul, &besterr)) { | |
589 | pllcfg = (3 << 6) | div; | |
590 | bestfreq = fmul; | |
591 | } | |
592 | } | |
593 | ||
594 | /* Configure clock source */ | |
d3a8a252 | 595 | clksrc = xtal ? MAX310X_CLKSRC_CRYST_BIT : MAX310X_CLKSRC_EXTCLK_BIT; |
f6544418 AS |
596 | |
597 | /* Configure PLL */ | |
598 | if (pllcfg) { | |
599 | clksrc |= MAX310X_CLKSRC_PLL_BIT; | |
600 | regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); | |
601 | } else | |
602 | clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; | |
603 | ||
604 | regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); | |
605 | ||
10d8b34a | 606 | /* Wait for crystal */ |
d3a8a252 | 607 | if (pllcfg && xtal) |
10d8b34a | 608 | msleep(10); |
f6544418 AS |
609 | |
610 | return (int)bestfreq; | |
611 | } | |
612 | ||
10d8b34a | 613 | static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) |
f6544418 | 614 | { |
10d8b34a | 615 | unsigned int sts, ch, flag; |
f6544418 | 616 | |
10d8b34a AS |
617 | if (unlikely(rxlen >= port->fifosize)) { |
618 | dev_warn_ratelimited(port->dev, | |
619 | "Port %i: Possible RX FIFO overrun\n", | |
620 | port->line); | |
621 | port->icount.buf_overrun++; | |
f6544418 | 622 | /* Ensure sanity of RX level */ |
10d8b34a | 623 | rxlen = port->fifosize; |
f6544418 AS |
624 | } |
625 | ||
f6544418 | 626 | while (rxlen--) { |
10d8b34a AS |
627 | ch = max310x_port_read(port, MAX310X_RHR_REG); |
628 | sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); | |
f6544418 AS |
629 | |
630 | sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | | |
631 | MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; | |
632 | ||
10d8b34a | 633 | port->icount.rx++; |
f6544418 AS |
634 | flag = TTY_NORMAL; |
635 | ||
636 | if (unlikely(sts)) { | |
637 | if (sts & MAX310X_LSR_RXBRK_BIT) { | |
10d8b34a AS |
638 | port->icount.brk++; |
639 | if (uart_handle_break(port)) | |
f6544418 AS |
640 | continue; |
641 | } else if (sts & MAX310X_LSR_RXPAR_BIT) | |
10d8b34a | 642 | port->icount.parity++; |
f6544418 | 643 | else if (sts & MAX310X_LSR_FRERR_BIT) |
10d8b34a | 644 | port->icount.frame++; |
f6544418 | 645 | else if (sts & MAX310X_LSR_RXOVR_BIT) |
10d8b34a | 646 | port->icount.overrun++; |
f6544418 | 647 | |
10d8b34a | 648 | sts &= port->read_status_mask; |
f6544418 AS |
649 | if (sts & MAX310X_LSR_RXBRK_BIT) |
650 | flag = TTY_BREAK; | |
651 | else if (sts & MAX310X_LSR_RXPAR_BIT) | |
652 | flag = TTY_PARITY; | |
653 | else if (sts & MAX310X_LSR_FRERR_BIT) | |
654 | flag = TTY_FRAME; | |
655 | else if (sts & MAX310X_LSR_RXOVR_BIT) | |
656 | flag = TTY_OVERRUN; | |
657 | } | |
658 | ||
10d8b34a | 659 | if (uart_handle_sysrq_char(port, ch)) |
f6544418 AS |
660 | continue; |
661 | ||
10d8b34a | 662 | if (sts & port->ignore_status_mask) |
f6544418 AS |
663 | continue; |
664 | ||
10d8b34a | 665 | uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); |
f6544418 AS |
666 | } |
667 | ||
10d8b34a | 668 | tty_flip_buffer_push(&port->state->port); |
f6544418 AS |
669 | } |
670 | ||
10d8b34a | 671 | static void max310x_handle_tx(struct uart_port *port) |
f6544418 | 672 | { |
10d8b34a AS |
673 | struct circ_buf *xmit = &port->state->xmit; |
674 | unsigned int txlen, to_send; | |
f6544418 | 675 | |
10d8b34a AS |
676 | if (unlikely(port->x_char)) { |
677 | max310x_port_write(port, MAX310X_THR_REG, port->x_char); | |
678 | port->icount.tx++; | |
679 | port->x_char = 0; | |
f6544418 AS |
680 | return; |
681 | } | |
682 | ||
10d8b34a | 683 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) |
f6544418 AS |
684 | return; |
685 | ||
686 | /* Get length of data pending in circular buffer */ | |
687 | to_send = uart_circ_chars_pending(xmit); | |
688 | if (likely(to_send)) { | |
689 | /* Limit to size of TX FIFO */ | |
10d8b34a AS |
690 | txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); |
691 | txlen = port->fifosize - txlen; | |
f6544418 AS |
692 | to_send = (to_send > txlen) ? txlen : to_send; |
693 | ||
f6544418 | 694 | /* Add data to send */ |
10d8b34a | 695 | port->icount.tx += to_send; |
f6544418 | 696 | while (to_send--) { |
10d8b34a AS |
697 | max310x_port_write(port, MAX310X_THR_REG, |
698 | xmit->buf[xmit->tail]); | |
f6544418 | 699 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
fc811472 | 700 | } |
f6544418 AS |
701 | } |
702 | ||
703 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
10d8b34a | 704 | uart_write_wakeup(port); |
f6544418 AS |
705 | } |
706 | ||
10d8b34a | 707 | static void max310x_port_irq(struct max310x_port *s, int portno) |
f6544418 | 708 | { |
10d8b34a | 709 | struct uart_port *port = &s->p[portno].port; |
f6544418 | 710 | |
10d8b34a AS |
711 | do { |
712 | unsigned int ists, lsr, rxlen; | |
f6544418 | 713 | |
f6544418 | 714 | /* Read IRQ status & RX FIFO level */ |
10d8b34a AS |
715 | ists = max310x_port_read(port, MAX310X_IRQSTS_REG); |
716 | rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); | |
717 | if (!ists && !rxlen) | |
f6544418 AS |
718 | break; |
719 | ||
10d8b34a AS |
720 | if (ists & MAX310X_IRQ_CTS_BIT) { |
721 | lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); | |
722 | uart_handle_cts_change(port, | |
f6544418 | 723 | !!(lsr & MAX310X_LSR_CTS_BIT)); |
10d8b34a AS |
724 | } |
725 | if (rxlen) | |
726 | max310x_handle_rx(port, rxlen); | |
727 | if (ists & MAX310X_IRQ_TXEMPTY_BIT) { | |
728 | mutex_lock(&s->mutex); | |
729 | max310x_handle_tx(port); | |
730 | mutex_unlock(&s->mutex); | |
731 | } | |
732 | } while (1); | |
733 | } | |
f6544418 | 734 | |
10d8b34a AS |
735 | static irqreturn_t max310x_ist(int irq, void *dev_id) |
736 | { | |
737 | struct max310x_port *s = (struct max310x_port *)dev_id; | |
738 | ||
739 | if (s->uart.nr > 1) { | |
740 | do { | |
741 | unsigned int val = ~0; | |
742 | ||
743 | WARN_ON_ONCE(regmap_read(s->regmap, | |
744 | MAX310X_GLOBALIRQ_REG, &val)); | |
745 | val = ((1 << s->uart.nr) - 1) & ~val; | |
746 | if (!val) | |
747 | break; | |
748 | max310x_port_irq(s, fls(val) - 1); | |
749 | } while (1); | |
750 | } else | |
751 | max310x_port_irq(s, 0); | |
f6544418 AS |
752 | |
753 | return IRQ_HANDLED; | |
754 | } | |
755 | ||
756 | static void max310x_wq_proc(struct work_struct *ws) | |
757 | { | |
10d8b34a AS |
758 | struct max310x_one *one = container_of(ws, struct max310x_one, tx_work); |
759 | struct max310x_port *s = dev_get_drvdata(one->port.dev); | |
f6544418 | 760 | |
10d8b34a AS |
761 | mutex_lock(&s->mutex); |
762 | max310x_handle_tx(&one->port); | |
763 | mutex_unlock(&s->mutex); | |
f6544418 AS |
764 | } |
765 | ||
766 | static void max310x_start_tx(struct uart_port *port) | |
767 | { | |
10d8b34a | 768 | struct max310x_one *one = container_of(port, struct max310x_one, port); |
f6544418 | 769 | |
10d8b34a AS |
770 | if (!work_pending(&one->tx_work)) |
771 | schedule_work(&one->tx_work); | |
f6544418 AS |
772 | } |
773 | ||
774 | static unsigned int max310x_tx_empty(struct uart_port *port) | |
775 | { | |
10d8b34a | 776 | unsigned int lvl, sts; |
f6544418 | 777 | |
10d8b34a AS |
778 | lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); |
779 | sts = max310x_port_read(port, MAX310X_IRQSTS_REG); | |
f6544418 | 780 | |
10d8b34a | 781 | return ((sts & MAX310X_IRQ_TXEMPTY_BIT) && !lvl) ? TIOCSER_TEMT : 0; |
f6544418 AS |
782 | } |
783 | ||
784 | static unsigned int max310x_get_mctrl(struct uart_port *port) | |
785 | { | |
786 | /* DCD and DSR are not wired and CTS/RTS is handled automatically | |
787 | * so just indicate DSR and CAR asserted | |
788 | */ | |
789 | return TIOCM_DSR | TIOCM_CAR; | |
790 | } | |
791 | ||
e7b8a3ce AS |
792 | static void max310x_md_proc(struct work_struct *ws) |
793 | { | |
794 | struct max310x_one *one = container_of(ws, struct max310x_one, md_work); | |
795 | ||
796 | max310x_port_update(&one->port, MAX310X_MODE2_REG, | |
797 | MAX310X_MODE2_LOOPBACK_BIT, | |
798 | (one->port.mctrl & TIOCM_LOOP) ? | |
799 | MAX310X_MODE2_LOOPBACK_BIT : 0); | |
800 | } | |
801 | ||
f6544418 AS |
802 | static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) |
803 | { | |
e7b8a3ce AS |
804 | struct max310x_one *one = container_of(port, struct max310x_one, port); |
805 | ||
806 | schedule_work(&one->md_work); | |
f6544418 AS |
807 | } |
808 | ||
809 | static void max310x_break_ctl(struct uart_port *port, int break_state) | |
810 | { | |
10d8b34a AS |
811 | max310x_port_update(port, MAX310X_LCR_REG, |
812 | MAX310X_LCR_TXBREAK_BIT, | |
813 | break_state ? MAX310X_LCR_TXBREAK_BIT : 0); | |
f6544418 AS |
814 | } |
815 | ||
816 | static void max310x_set_termios(struct uart_port *port, | |
817 | struct ktermios *termios, | |
818 | struct ktermios *old) | |
819 | { | |
f6544418 AS |
820 | unsigned int lcr, flow = 0; |
821 | int baud; | |
822 | ||
f6544418 AS |
823 | /* Mask termios capabilities we don't support */ |
824 | termios->c_cflag &= ~CMSPAR; | |
f6544418 AS |
825 | |
826 | /* Word size */ | |
827 | switch (termios->c_cflag & CSIZE) { | |
828 | case CS5: | |
829 | lcr = MAX310X_LCR_WORD_LEN_5; | |
830 | break; | |
831 | case CS6: | |
832 | lcr = MAX310X_LCR_WORD_LEN_6; | |
833 | break; | |
834 | case CS7: | |
835 | lcr = MAX310X_LCR_WORD_LEN_7; | |
836 | break; | |
837 | case CS8: | |
838 | default: | |
839 | lcr = MAX310X_LCR_WORD_LEN_8; | |
840 | break; | |
841 | } | |
842 | ||
843 | /* Parity */ | |
844 | if (termios->c_cflag & PARENB) { | |
845 | lcr |= MAX310X_LCR_PARITY_BIT; | |
846 | if (!(termios->c_cflag & PARODD)) | |
847 | lcr |= MAX310X_LCR_EVENPARITY_BIT; | |
848 | } | |
849 | ||
850 | /* Stop bits */ | |
851 | if (termios->c_cflag & CSTOPB) | |
852 | lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ | |
853 | ||
854 | /* Update LCR register */ | |
10d8b34a | 855 | max310x_port_write(port, MAX310X_LCR_REG, lcr); |
f6544418 AS |
856 | |
857 | /* Set read status mask */ | |
858 | port->read_status_mask = MAX310X_LSR_RXOVR_BIT; | |
859 | if (termios->c_iflag & INPCK) | |
860 | port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | | |
861 | MAX310X_LSR_FRERR_BIT; | |
862 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
863 | port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; | |
864 | ||
865 | /* Set status ignore mask */ | |
866 | port->ignore_status_mask = 0; | |
867 | if (termios->c_iflag & IGNBRK) | |
868 | port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; | |
869 | if (!(termios->c_cflag & CREAD)) | |
870 | port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | | |
871 | MAX310X_LSR_RXOVR_BIT | | |
872 | MAX310X_LSR_FRERR_BIT | | |
873 | MAX310X_LSR_RXBRK_BIT; | |
874 | ||
875 | /* Configure flow control */ | |
10d8b34a AS |
876 | max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); |
877 | max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); | |
f6544418 AS |
878 | if (termios->c_cflag & CRTSCTS) |
879 | flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | | |
880 | MAX310X_FLOWCTRL_AUTORTS_BIT; | |
881 | if (termios->c_iflag & IXON) | |
882 | flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT | | |
883 | MAX310X_FLOWCTRL_SWFLOWEN_BIT; | |
884 | if (termios->c_iflag & IXOFF) | |
885 | flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | | |
886 | MAX310X_FLOWCTRL_SWFLOWEN_BIT; | |
10d8b34a | 887 | max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); |
f6544418 AS |
888 | |
889 | /* Get baud rate generator configuration */ | |
890 | baud = uart_get_baud_rate(port, termios, old, | |
891 | port->uartclk / 16 / 0xffff, | |
892 | port->uartclk / 4); | |
893 | ||
894 | /* Setup baudrate generator */ | |
e97e1556 | 895 | baud = max310x_set_baud(port, baud); |
f6544418 AS |
896 | |
897 | /* Update timeout according to new baud rate */ | |
898 | uart_update_timeout(port, termios->c_cflag, baud); | |
f6544418 AS |
899 | } |
900 | ||
901 | static int max310x_startup(struct uart_port *port) | |
902 | { | |
903 | unsigned int val, line = port->line; | |
10d8b34a | 904 | struct max310x_port *s = dev_get_drvdata(port->dev); |
f6544418 | 905 | |
10d8b34a | 906 | s->devtype->power(port, 1); |
f6544418 | 907 | |
f6544418 | 908 | /* Configure MODE1 register */ |
10d8b34a AS |
909 | max310x_port_update(port, MAX310X_MODE1_REG, |
910 | MAX310X_MODE1_TRNSCVCTRL_BIT, | |
911 | (s->pdata->uart_flags[line] & MAX310X_AUTO_DIR_CTRL) | |
912 | ? MAX310X_MODE1_TRNSCVCTRL_BIT : 0); | |
f6544418 AS |
913 | |
914 | /* Configure MODE2 register */ | |
915 | val = MAX310X_MODE2_RXEMPTINV_BIT; | |
f6544418 AS |
916 | if (s->pdata->uart_flags[line] & MAX310X_ECHO_SUPRESS) |
917 | val |= MAX310X_MODE2_ECHOSUPR_BIT; | |
918 | ||
919 | /* Reset FIFOs */ | |
920 | val |= MAX310X_MODE2_FIFORST_BIT; | |
10d8b34a AS |
921 | max310x_port_write(port, MAX310X_MODE2_REG, val); |
922 | max310x_port_update(port, MAX310X_MODE2_REG, | |
923 | MAX310X_MODE2_FIFORST_BIT, 0); | |
f6544418 AS |
924 | |
925 | /* Configure flow control levels */ | |
926 | /* Flow control halt level 96, resume level 48 */ | |
10d8b34a AS |
927 | max310x_port_write(port, MAX310X_FLOWLVL_REG, |
928 | MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96)); | |
f6544418 | 929 | |
10d8b34a AS |
930 | /* Clear IRQ status register */ |
931 | max310x_port_read(port, MAX310X_IRQSTS_REG); | |
f6544418 | 932 | |
10d8b34a AS |
933 | /* Enable RX, TX, CTS change interrupts */ |
934 | val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; | |
935 | max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); | |
f6544418 AS |
936 | |
937 | return 0; | |
938 | } | |
939 | ||
940 | static void max310x_shutdown(struct uart_port *port) | |
941 | { | |
10d8b34a | 942 | struct max310x_port *s = dev_get_drvdata(port->dev); |
f6544418 AS |
943 | |
944 | /* Disable all interrupts */ | |
10d8b34a | 945 | max310x_port_write(port, MAX310X_IRQEN_REG, 0); |
f6544418 | 946 | |
10d8b34a | 947 | s->devtype->power(port, 0); |
f6544418 AS |
948 | } |
949 | ||
950 | static const char *max310x_type(struct uart_port *port) | |
951 | { | |
10d8b34a | 952 | struct max310x_port *s = dev_get_drvdata(port->dev); |
f6544418 | 953 | |
10d8b34a | 954 | return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; |
f6544418 AS |
955 | } |
956 | ||
957 | static int max310x_request_port(struct uart_port *port) | |
958 | { | |
959 | /* Do nothing */ | |
960 | return 0; | |
961 | } | |
962 | ||
f6544418 AS |
963 | static void max310x_config_port(struct uart_port *port, int flags) |
964 | { | |
965 | if (flags & UART_CONFIG_TYPE) | |
966 | port->type = PORT_MAX310X; | |
967 | } | |
968 | ||
10d8b34a | 969 | static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) |
f6544418 | 970 | { |
10d8b34a AS |
971 | if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) |
972 | return -EINVAL; | |
973 | if (s->irq != port->irq) | |
974 | return -EINVAL; | |
f6544418 | 975 | |
10d8b34a | 976 | return 0; |
f6544418 AS |
977 | } |
978 | ||
10d8b34a AS |
979 | static void max310x_null_void(struct uart_port *port) |
980 | { | |
981 | /* Do nothing */ | |
982 | } | |
983 | ||
984 | static const struct uart_ops max310x_ops = { | |
f6544418 AS |
985 | .tx_empty = max310x_tx_empty, |
986 | .set_mctrl = max310x_set_mctrl, | |
987 | .get_mctrl = max310x_get_mctrl, | |
10d8b34a | 988 | .stop_tx = max310x_null_void, |
f6544418 | 989 | .start_tx = max310x_start_tx, |
10d8b34a AS |
990 | .stop_rx = max310x_null_void, |
991 | .enable_ms = max310x_null_void, | |
f6544418 AS |
992 | .break_ctl = max310x_break_ctl, |
993 | .startup = max310x_startup, | |
994 | .shutdown = max310x_shutdown, | |
995 | .set_termios = max310x_set_termios, | |
996 | .type = max310x_type, | |
997 | .request_port = max310x_request_port, | |
10d8b34a | 998 | .release_port = max310x_null_void, |
f6544418 AS |
999 | .config_port = max310x_config_port, |
1000 | .verify_port = max310x_verify_port, | |
1001 | }; | |
1002 | ||
c2978296 | 1003 | static int __maybe_unused max310x_suspend(struct device *dev) |
f6544418 | 1004 | { |
c2978296 | 1005 | struct max310x_port *s = dev_get_drvdata(dev); |
10d8b34a | 1006 | int i; |
f6544418 | 1007 | |
10d8b34a AS |
1008 | for (i = 0; i < s->uart.nr; i++) { |
1009 | uart_suspend_port(&s->uart, &s->p[i].port); | |
1010 | s->devtype->power(&s->p[i].port, 0); | |
1011 | } | |
f6544418 | 1012 | |
10d8b34a | 1013 | return 0; |
f6544418 AS |
1014 | } |
1015 | ||
c2978296 | 1016 | static int __maybe_unused max310x_resume(struct device *dev) |
f6544418 | 1017 | { |
c2978296 | 1018 | struct max310x_port *s = dev_get_drvdata(dev); |
10d8b34a | 1019 | int i; |
f6544418 | 1020 | |
10d8b34a AS |
1021 | for (i = 0; i < s->uart.nr; i++) { |
1022 | s->devtype->power(&s->p[i].port, 1); | |
1023 | uart_resume_port(&s->uart, &s->p[i].port); | |
1024 | } | |
f6544418 | 1025 | |
10d8b34a | 1026 | return 0; |
f6544418 AS |
1027 | } |
1028 | ||
27027a70 AS |
1029 | static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); |
1030 | ||
f6544418 AS |
1031 | #ifdef CONFIG_GPIOLIB |
1032 | static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset) | |
1033 | { | |
10d8b34a | 1034 | unsigned int val; |
f6544418 | 1035 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); |
10d8b34a | 1036 | struct uart_port *port = &s->p[offset / 4].port; |
f6544418 | 1037 | |
10d8b34a | 1038 | val = max310x_port_read(port, MAX310X_GPIODATA_REG); |
f6544418 | 1039 | |
10d8b34a | 1040 | return !!((val >> 4) & (1 << (offset % 4))); |
f6544418 AS |
1041 | } |
1042 | ||
1043 | static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
1044 | { | |
1045 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); | |
10d8b34a | 1046 | struct uart_port *port = &s->p[offset / 4].port; |
f6544418 | 1047 | |
10d8b34a AS |
1048 | max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), |
1049 | value ? 1 << (offset % 4) : 0); | |
f6544418 AS |
1050 | } |
1051 | ||
1052 | static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
1053 | { | |
1054 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); | |
10d8b34a | 1055 | struct uart_port *port = &s->p[offset / 4].port; |
f6544418 | 1056 | |
10d8b34a | 1057 | max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); |
f6544418 AS |
1058 | |
1059 | return 0; | |
1060 | } | |
1061 | ||
1062 | static int max310x_gpio_direction_output(struct gpio_chip *chip, | |
1063 | unsigned offset, int value) | |
1064 | { | |
1065 | struct max310x_port *s = container_of(chip, struct max310x_port, gpio); | |
10d8b34a | 1066 | struct uart_port *port = &s->p[offset / 4].port; |
f6544418 | 1067 | |
10d8b34a AS |
1068 | max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), |
1069 | value ? 1 << (offset % 4) : 0); | |
1070 | max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), | |
1071 | 1 << (offset % 4)); | |
f6544418 AS |
1072 | |
1073 | return 0; | |
1074 | } | |
1075 | #endif | |
1076 | ||
27027a70 AS |
1077 | static int max310x_probe(struct device *dev, struct max310x_devtype *devtype, |
1078 | struct regmap *regmap, int irq) | |
f6544418 | 1079 | { |
10d8b34a | 1080 | struct max310x_pdata *pdata = dev_get_platdata(dev); |
d3a8a252 AS |
1081 | int i, ret, fmin, fmax, freq, uartclk; |
1082 | struct clk *clk_osc, *clk_xtal; | |
1083 | struct max310x_port *s; | |
1084 | bool xtal = false; | |
f6544418 | 1085 | |
27027a70 AS |
1086 | if (IS_ERR(regmap)) |
1087 | return PTR_ERR(regmap); | |
1088 | ||
10d8b34a AS |
1089 | if (!pdata) { |
1090 | dev_err(dev, "No platform data supplied\n"); | |
1091 | return -EINVAL; | |
1092 | } | |
1093 | ||
f6544418 | 1094 | /* Alloc port structure */ |
10d8b34a AS |
1095 | s = devm_kzalloc(dev, sizeof(*s) + |
1096 | sizeof(struct max310x_one) * devtype->nr, GFP_KERNEL); | |
f6544418 AS |
1097 | if (!s) { |
1098 | dev_err(dev, "Error allocating port structure\n"); | |
1099 | return -ENOMEM; | |
1100 | } | |
f6544418 | 1101 | |
d3a8a252 AS |
1102 | clk_osc = devm_clk_get(dev, "osc"); |
1103 | clk_xtal = devm_clk_get(dev, "xtal"); | |
1104 | if (!IS_ERR(clk_osc)) { | |
1105 | s->clk = clk_osc; | |
1106 | fmin = 500000; | |
1107 | fmax = 35000000; | |
1108 | } else if (!IS_ERR(clk_xtal)) { | |
1109 | s->clk = clk_xtal; | |
1110 | fmin = 1000000; | |
1111 | fmax = 4000000; | |
1112 | xtal = true; | |
1113 | } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER || | |
1114 | PTR_ERR(clk_xtal) == -EPROBE_DEFER) { | |
1115 | return -EPROBE_DEFER; | |
1116 | } else { | |
1117 | dev_err(dev, "Cannot get clock\n"); | |
1118 | return -EINVAL; | |
1119 | } | |
1120 | ||
1121 | ret = clk_prepare_enable(s->clk); | |
1122 | if (ret) | |
1123 | return ret; | |
1124 | ||
1125 | freq = clk_get_rate(s->clk); | |
1126 | /* Check frequency limits */ | |
1127 | if (freq < fmin || freq > fmax) { | |
1128 | ret = -ERANGE; | |
1129 | goto out_clk; | |
1130 | } | |
f6544418 | 1131 | |
10d8b34a | 1132 | s->pdata = pdata; |
27027a70 | 1133 | s->regmap = regmap; |
10d8b34a AS |
1134 | s->devtype = devtype; |
1135 | dev_set_drvdata(dev, s); | |
f6544418 | 1136 | |
10d8b34a AS |
1137 | /* Check device to ensure we are talking to what we expect */ |
1138 | ret = devtype->detect(dev); | |
1139 | if (ret) | |
d3a8a252 | 1140 | goto out_clk; |
10d8b34a AS |
1141 | |
1142 | for (i = 0; i < devtype->nr; i++) { | |
1143 | unsigned int offs = i << 5; | |
1144 | ||
1145 | /* Reset port */ | |
1146 | regmap_write(s->regmap, MAX310X_MODE2_REG + offs, | |
1147 | MAX310X_MODE2_RST_BIT); | |
1148 | /* Clear port reset */ | |
1149 | regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0); | |
1150 | ||
1151 | /* Wait for port startup */ | |
1152 | do { | |
1153 | regmap_read(s->regmap, | |
1154 | MAX310X_BRGDIVLSB_REG + offs, &ret); | |
1155 | } while (ret != 0x01); | |
1156 | ||
1157 | regmap_update_bits(s->regmap, MAX310X_MODE1_REG + offs, | |
1158 | MAX310X_MODE1_AUTOSLEEP_BIT, | |
1159 | MAX310X_MODE1_AUTOSLEEP_BIT); | |
f6544418 AS |
1160 | } |
1161 | ||
d3a8a252 | 1162 | uartclk = max310x_set_ref_clk(s, freq, xtal); |
10d8b34a AS |
1163 | dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); |
1164 | ||
f6544418 AS |
1165 | /* Register UART driver */ |
1166 | s->uart.owner = THIS_MODULE; | |
f6544418 AS |
1167 | s->uart.dev_name = "ttyMAX"; |
1168 | s->uart.major = MAX310X_MAJOR; | |
1169 | s->uart.minor = MAX310X_MINOR; | |
10d8b34a | 1170 | s->uart.nr = devtype->nr; |
f6544418 AS |
1171 | ret = uart_register_driver(&s->uart); |
1172 | if (ret) { | |
1173 | dev_err(dev, "Registering UART driver failed\n"); | |
d3a8a252 | 1174 | goto out_clk; |
f6544418 AS |
1175 | } |
1176 | ||
dba29a28 AS |
1177 | #ifdef CONFIG_GPIOLIB |
1178 | /* Setup GPIO cotroller */ | |
1179 | s->gpio.owner = THIS_MODULE; | |
1180 | s->gpio.dev = dev; | |
1181 | s->gpio.label = dev_name(dev); | |
1182 | s->gpio.direction_input = max310x_gpio_direction_input; | |
1183 | s->gpio.get = max310x_gpio_get; | |
1184 | s->gpio.direction_output= max310x_gpio_direction_output; | |
1185 | s->gpio.set = max310x_gpio_set; | |
1186 | s->gpio.base = -1; | |
1187 | s->gpio.ngpio = devtype->nr * 4; | |
1188 | s->gpio.can_sleep = 1; | |
1189 | ret = gpiochip_add(&s->gpio); | |
1190 | if (ret) | |
1191 | goto out_uart; | |
1192 | #endif | |
1193 | ||
0fbae887 AS |
1194 | mutex_init(&s->mutex); |
1195 | ||
10d8b34a AS |
1196 | for (i = 0; i < devtype->nr; i++) { |
1197 | /* Initialize port data */ | |
1198 | s->p[i].port.line = i; | |
1199 | s->p[i].port.dev = dev; | |
1200 | s->p[i].port.irq = irq; | |
1201 | s->p[i].port.type = PORT_MAX310X; | |
1202 | s->p[i].port.fifosize = MAX310X_FIFO_SIZE; | |
e7b8a3ce | 1203 | s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; |
10d8b34a AS |
1204 | s->p[i].port.iotype = UPIO_PORT; |
1205 | s->p[i].port.iobase = i * 0x20; | |
1206 | s->p[i].port.membase = (void __iomem *)~0; | |
1207 | s->p[i].port.uartclk = uartclk; | |
1208 | s->p[i].port.ops = &max310x_ops; | |
1209 | /* Disable all interrupts */ | |
1210 | max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); | |
1211 | /* Clear IRQ status register */ | |
1212 | max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); | |
1213 | /* Enable IRQ pin */ | |
1214 | max310x_port_update(&s->p[i].port, MAX310X_MODE1_REG, | |
1215 | MAX310X_MODE1_IRQSEL_BIT, | |
1216 | MAX310X_MODE1_IRQSEL_BIT); | |
1217 | /* Initialize queue for start TX */ | |
1218 | INIT_WORK(&s->p[i].tx_work, max310x_wq_proc); | |
e7b8a3ce AS |
1219 | /* Initialize queue for changing mode */ |
1220 | INIT_WORK(&s->p[i].md_work, max310x_md_proc); | |
10d8b34a AS |
1221 | /* Register port */ |
1222 | uart_add_one_port(&s->uart, &s->p[i].port); | |
1223 | /* Go to suspend mode */ | |
1224 | devtype->power(&s->p[i].port, 0); | |
1225 | } | |
f6544418 | 1226 | |
10d8b34a AS |
1227 | /* Setup interrupt */ |
1228 | ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist, | |
1229 | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, | |
1230 | dev_name(dev), s); | |
d3a8a252 AS |
1231 | if (!ret) |
1232 | return 0; | |
1233 | ||
1234 | dev_err(dev, "Unable to reguest IRQ %i\n", irq); | |
dba29a28 | 1235 | |
0fbae887 AS |
1236 | mutex_destroy(&s->mutex); |
1237 | ||
10d8b34a | 1238 | #ifdef CONFIG_GPIOLIB |
dba29a28 | 1239 | WARN_ON(gpiochip_remove(&s->gpio)); |
10d8b34a | 1240 | #endif |
f6544418 | 1241 | |
dba29a28 AS |
1242 | out_uart: |
1243 | uart_unregister_driver(&s->uart); | |
1244 | ||
d3a8a252 AS |
1245 | out_clk: |
1246 | clk_disable_unprepare(s->clk); | |
f6544418 | 1247 | |
d3a8a252 | 1248 | return ret; |
f6544418 AS |
1249 | } |
1250 | ||
10d8b34a | 1251 | static int max310x_remove(struct device *dev) |
f6544418 | 1252 | { |
f6544418 | 1253 | struct max310x_port *s = dev_get_drvdata(dev); |
10d8b34a | 1254 | int i, ret = 0; |
f6544418 | 1255 | |
dba29a28 AS |
1256 | #ifdef CONFIG_GPIOLIB |
1257 | ret = gpiochip_remove(&s->gpio); | |
1258 | if (ret) | |
1259 | return ret; | |
1260 | #endif | |
1261 | ||
10d8b34a AS |
1262 | for (i = 0; i < s->uart.nr; i++) { |
1263 | cancel_work_sync(&s->p[i].tx_work); | |
e7b8a3ce | 1264 | cancel_work_sync(&s->p[i].md_work); |
10d8b34a AS |
1265 | uart_remove_one_port(&s->uart, &s->p[i].port); |
1266 | s->devtype->power(&s->p[i].port, 0); | |
1267 | } | |
f6544418 | 1268 | |
0fbae887 | 1269 | mutex_destroy(&s->mutex); |
f6544418 | 1270 | uart_unregister_driver(&s->uart); |
d3a8a252 | 1271 | clk_disable_unprepare(s->clk); |
f6544418 | 1272 | |
23e7c6a7 | 1273 | return ret; |
f6544418 AS |
1274 | } |
1275 | ||
27027a70 AS |
1276 | static struct regmap_config regcfg = { |
1277 | .reg_bits = 8, | |
1278 | .val_bits = 8, | |
1279 | .write_flag_mask = 0x80, | |
1280 | .cache_type = REGCACHE_RBTREE, | |
1281 | .writeable_reg = max310x_reg_writeable, | |
1282 | .volatile_reg = max310x_reg_volatile, | |
1283 | .precious_reg = max310x_reg_precious, | |
1284 | }; | |
1285 | ||
10d8b34a AS |
1286 | #ifdef CONFIG_SPI_MASTER |
1287 | static int max310x_spi_probe(struct spi_device *spi) | |
1288 | { | |
1289 | struct max310x_devtype *devtype = | |
1290 | (struct max310x_devtype *)spi_get_device_id(spi)->driver_data; | |
27027a70 | 1291 | struct regmap *regmap; |
10d8b34a AS |
1292 | int ret; |
1293 | ||
1294 | /* Setup SPI bus */ | |
1295 | spi->bits_per_word = 8; | |
1296 | spi->mode = spi->mode ? : SPI_MODE_0; | |
1297 | spi->max_speed_hz = spi->max_speed_hz ? : 26000000; | |
1298 | ret = spi_setup(spi); | |
27027a70 | 1299 | if (ret) |
10d8b34a | 1300 | return ret; |
10d8b34a | 1301 | |
27027a70 AS |
1302 | regcfg.max_register = devtype->nr * 0x20 - 1; |
1303 | regmap = devm_regmap_init_spi(spi, ®cfg); | |
1304 | ||
1305 | return max310x_probe(&spi->dev, devtype, regmap, spi->irq); | |
10d8b34a AS |
1306 | } |
1307 | ||
1308 | static int max310x_spi_remove(struct spi_device *spi) | |
1309 | { | |
1310 | return max310x_remove(&spi->dev); | |
1311 | } | |
1312 | ||
f6544418 | 1313 | static const struct spi_device_id max310x_id_table[] = { |
10d8b34a AS |
1314 | { "max3107", (kernel_ulong_t)&max3107_devtype, }, |
1315 | { "max3108", (kernel_ulong_t)&max3108_devtype, }, | |
21fc509f | 1316 | { "max3109", (kernel_ulong_t)&max3109_devtype, }, |
003236d9 | 1317 | { "max14830", (kernel_ulong_t)&max14830_devtype, }, |
1838b8c4 | 1318 | { } |
f6544418 AS |
1319 | }; |
1320 | MODULE_DEVICE_TABLE(spi, max310x_id_table); | |
1321 | ||
10d8b34a | 1322 | static struct spi_driver max310x_uart_driver = { |
f6544418 | 1323 | .driver = { |
10d8b34a | 1324 | .name = MAX310X_NAME, |
f6544418 | 1325 | .owner = THIS_MODULE, |
10d8b34a | 1326 | .pm = &max310x_pm_ops, |
f6544418 | 1327 | }, |
10d8b34a AS |
1328 | .probe = max310x_spi_probe, |
1329 | .remove = max310x_spi_remove, | |
f6544418 AS |
1330 | .id_table = max310x_id_table, |
1331 | }; | |
10d8b34a AS |
1332 | module_spi_driver(max310x_uart_driver); |
1333 | #endif | |
f6544418 | 1334 | |
10d8b34a | 1335 | MODULE_LICENSE("GPL"); |
f6544418 AS |
1336 | MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); |
1337 | MODULE_DESCRIPTION("MAX310X serial driver"); |