Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * Driver for the PSC of the Freescale MPC52xx PSCs configured as UARTs. |
3 | * | |
4 | * FIXME According to the usermanual the status bits in the status register | |
5 | * are only updated when the peripherals access the FIFO and not when the | |
6 | * CPU access them. So since we use this bits to know when we stop writing | |
7 | * and reading, they may not be updated in-time and a race condition may | |
8 | * exists. But I haven't be able to prove this and I don't care. But if | |
9 | * any problem arises, it might worth checking. The TX/RX FIFO Stats | |
10 | * registers should be used in addition. | |
11 | * Update: Actually, they seem updated ... At least the bits we use. | |
12 | * | |
13 | * | |
14 | * Maintainer : Sylvain Munaut <tnt@246tNt.com> | |
9b9129e7 | 15 | * |
1da177e4 LT |
16 | * Some of the code has been inspired/copied from the 2.4 code written |
17 | * by Dale Farnsworth <dfarnsworth@mvista.com>. | |
9b9129e7 | 18 | * |
25ae3a07 JR |
19 | * Copyright (C) 2008 Freescale Semiconductor Inc. |
20 | * John Rigby <jrigby@gmail.com> | |
21 | * Added support for MPC5121 | |
b9272dfd GL |
22 | * Copyright (C) 2006 Secret Lab Technologies Ltd. |
23 | * Grant Likely <grant.likely@secretlab.ca> | |
24 | * Copyright (C) 2004-2006 Sylvain Munaut <tnt@246tNt.com> | |
1da177e4 | 25 | * Copyright (C) 2003 MontaVista, Software, Inc. |
9b9129e7 | 26 | * |
1da177e4 LT |
27 | * This file is licensed under the terms of the GNU General Public License |
28 | * version 2. This program is licensed "as is" without any warranty of any | |
29 | * kind, whether express or implied. | |
30 | */ | |
9b9129e7 | 31 | |
b9272dfd GL |
32 | #undef DEBUG |
33 | ||
34 | #include <linux/device.h> | |
1da177e4 LT |
35 | #include <linux/module.h> |
36 | #include <linux/tty.h> | |
ee160a38 | 37 | #include <linux/tty_flip.h> |
1da177e4 LT |
38 | #include <linux/serial.h> |
39 | #include <linux/sysrq.h> | |
40 | #include <linux/console.h> | |
406b7d4f JR |
41 | #include <linux/delay.h> |
42 | #include <linux/io.h> | |
283029d1 GL |
43 | #include <linux/of.h> |
44 | #include <linux/of_platform.h> | |
6acc6833 | 45 | #include <linux/clk.h> |
b9272dfd | 46 | |
1da177e4 LT |
47 | #include <asm/mpc52xx.h> |
48 | #include <asm/mpc52xx_psc.h> | |
49 | ||
50 | #if defined(CONFIG_SERIAL_MPC52xx_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
51 | #define SUPPORT_SYSRQ | |
52 | #endif | |
53 | ||
54 | #include <linux/serial_core.h> | |
55 | ||
56 | ||
d62de3aa SM |
57 | /* We've been assigned a range on the "Low-density serial ports" major */ |
58 | #define SERIAL_PSC_MAJOR 204 | |
59 | #define SERIAL_PSC_MINOR 148 | |
60 | ||
1da177e4 LT |
61 | |
62 | #define ISR_PASS_LIMIT 256 /* Max number of iteration in the interrupt */ | |
63 | ||
64 | ||
65 | static struct uart_port mpc52xx_uart_ports[MPC52xx_PSC_MAXNUM]; | |
66 | /* Rem: - We use the read_status_mask as a shadow of | |
67 | * psc->mpc52xx_psc_imr | |
68 | * - It's important that is array is all zero on start as we | |
69 | * use it to know if it's initialized or not ! If it's not sure | |
70 | * it's cleared, then a memset(...,0,...) should be added to | |
71 | * the console_init | |
72 | */ | |
8d1fb8cb | 73 | |
b9272dfd GL |
74 | /* lookup table for matching device nodes to index numbers */ |
75 | static struct device_node *mpc52xx_uart_nodes[MPC52xx_PSC_MAXNUM]; | |
76 | ||
77 | static void mpc52xx_uart_of_enumerate(void); | |
1da177e4 | 78 | |
599f030c | 79 | |
1da177e4 LT |
80 | #define PSC(port) ((struct mpc52xx_psc __iomem *)((port)->membase)) |
81 | ||
82 | ||
83 | /* Forward declaration of the interruption handling routine */ | |
406b7d4f | 84 | static irqreturn_t mpc52xx_uart_int(int irq, void *dev_id); |
6acc6833 | 85 | static irqreturn_t mpc5xxx_uart_process_int(struct uart_port *port); |
1da177e4 | 86 | |
599f030c JR |
87 | /* ======================================================================== */ |
88 | /* PSC fifo operations for isolating differences between 52xx and 512x */ | |
89 | /* ======================================================================== */ | |
90 | ||
91 | struct psc_ops { | |
92 | void (*fifo_init)(struct uart_port *port); | |
93 | int (*raw_rx_rdy)(struct uart_port *port); | |
94 | int (*raw_tx_rdy)(struct uart_port *port); | |
95 | int (*rx_rdy)(struct uart_port *port); | |
96 | int (*tx_rdy)(struct uart_port *port); | |
97 | int (*tx_empty)(struct uart_port *port); | |
98 | void (*stop_rx)(struct uart_port *port); | |
99 | void (*start_tx)(struct uart_port *port); | |
100 | void (*stop_tx)(struct uart_port *port); | |
101 | void (*rx_clr_irq)(struct uart_port *port); | |
102 | void (*tx_clr_irq)(struct uart_port *port); | |
103 | void (*write_char)(struct uart_port *port, unsigned char c); | |
104 | unsigned char (*read_char)(struct uart_port *port); | |
105 | void (*cw_disable_ints)(struct uart_port *port); | |
106 | void (*cw_restore_ints)(struct uart_port *port); | |
0d1f22e4 AD |
107 | unsigned int (*set_baudrate)(struct uart_port *port, |
108 | struct ktermios *new, | |
109 | struct ktermios *old); | |
6acc6833 AG |
110 | int (*clock)(struct uart_port *port, int enable); |
111 | int (*fifoc_init)(void); | |
112 | void (*fifoc_uninit)(void); | |
113 | void (*get_irq)(struct uart_port *, struct device_node *); | |
114 | irqreturn_t (*handle_irq)(struct uart_port *port); | |
599f030c JR |
115 | }; |
116 | ||
0d1f22e4 AD |
117 | /* setting the prescaler and divisor reg is common for all chips */ |
118 | static inline void mpc52xx_set_divisor(struct mpc52xx_psc __iomem *psc, | |
119 | u16 prescaler, unsigned int divisor) | |
120 | { | |
121 | /* select prescaler */ | |
122 | out_be16(&psc->mpc52xx_psc_clock_select, prescaler); | |
123 | out_8(&psc->ctur, divisor >> 8); | |
124 | out_8(&psc->ctlr, divisor & 0xff); | |
125 | } | |
126 | ||
25ae3a07 | 127 | #ifdef CONFIG_PPC_MPC52xx |
599f030c JR |
128 | #define FIFO_52xx(port) ((struct mpc52xx_psc_fifo __iomem *)(PSC(port)+1)) |
129 | static void mpc52xx_psc_fifo_init(struct uart_port *port) | |
130 | { | |
131 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
132 | struct mpc52xx_psc_fifo __iomem *fifo = FIFO_52xx(port); | |
133 | ||
599f030c JR |
134 | out_8(&fifo->rfcntl, 0x00); |
135 | out_be16(&fifo->rfalarm, 0x1ff); | |
136 | out_8(&fifo->tfcntl, 0x07); | |
137 | out_be16(&fifo->tfalarm, 0x80); | |
138 | ||
139 | port->read_status_mask |= MPC52xx_PSC_IMR_RXRDY | MPC52xx_PSC_IMR_TXRDY; | |
140 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); | |
141 | } | |
142 | ||
143 | static int mpc52xx_psc_raw_rx_rdy(struct uart_port *port) | |
144 | { | |
145 | return in_be16(&PSC(port)->mpc52xx_psc_status) | |
146 | & MPC52xx_PSC_SR_RXRDY; | |
147 | } | |
148 | ||
149 | static int mpc52xx_psc_raw_tx_rdy(struct uart_port *port) | |
150 | { | |
151 | return in_be16(&PSC(port)->mpc52xx_psc_status) | |
152 | & MPC52xx_PSC_SR_TXRDY; | |
153 | } | |
154 | ||
155 | ||
156 | static int mpc52xx_psc_rx_rdy(struct uart_port *port) | |
157 | { | |
158 | return in_be16(&PSC(port)->mpc52xx_psc_isr) | |
159 | & port->read_status_mask | |
160 | & MPC52xx_PSC_IMR_RXRDY; | |
161 | } | |
162 | ||
163 | static int mpc52xx_psc_tx_rdy(struct uart_port *port) | |
164 | { | |
165 | return in_be16(&PSC(port)->mpc52xx_psc_isr) | |
166 | & port->read_status_mask | |
167 | & MPC52xx_PSC_IMR_TXRDY; | |
168 | } | |
169 | ||
170 | static int mpc52xx_psc_tx_empty(struct uart_port *port) | |
171 | { | |
172 | return in_be16(&PSC(port)->mpc52xx_psc_status) | |
173 | & MPC52xx_PSC_SR_TXEMP; | |
174 | } | |
175 | ||
176 | static void mpc52xx_psc_start_tx(struct uart_port *port) | |
177 | { | |
178 | port->read_status_mask |= MPC52xx_PSC_IMR_TXRDY; | |
179 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
180 | } | |
181 | ||
182 | static void mpc52xx_psc_stop_tx(struct uart_port *port) | |
183 | { | |
184 | port->read_status_mask &= ~MPC52xx_PSC_IMR_TXRDY; | |
185 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
186 | } | |
187 | ||
188 | static void mpc52xx_psc_stop_rx(struct uart_port *port) | |
189 | { | |
190 | port->read_status_mask &= ~MPC52xx_PSC_IMR_RXRDY; | |
191 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
192 | } | |
193 | ||
194 | static void mpc52xx_psc_rx_clr_irq(struct uart_port *port) | |
195 | { | |
196 | } | |
197 | ||
198 | static void mpc52xx_psc_tx_clr_irq(struct uart_port *port) | |
199 | { | |
200 | } | |
201 | ||
202 | static void mpc52xx_psc_write_char(struct uart_port *port, unsigned char c) | |
203 | { | |
204 | out_8(&PSC(port)->mpc52xx_psc_buffer_8, c); | |
205 | } | |
206 | ||
207 | static unsigned char mpc52xx_psc_read_char(struct uart_port *port) | |
208 | { | |
209 | return in_8(&PSC(port)->mpc52xx_psc_buffer_8); | |
210 | } | |
211 | ||
212 | static void mpc52xx_psc_cw_disable_ints(struct uart_port *port) | |
213 | { | |
214 | out_be16(&PSC(port)->mpc52xx_psc_imr, 0); | |
215 | } | |
216 | ||
217 | static void mpc52xx_psc_cw_restore_ints(struct uart_port *port) | |
218 | { | |
219 | out_be16(&PSC(port)->mpc52xx_psc_imr, port->read_status_mask); | |
220 | } | |
221 | ||
0d1f22e4 AD |
222 | static unsigned int mpc5200_psc_set_baudrate(struct uart_port *port, |
223 | struct ktermios *new, | |
224 | struct ktermios *old) | |
599f030c | 225 | { |
0d1f22e4 AD |
226 | unsigned int baud; |
227 | unsigned int divisor; | |
228 | ||
229 | /* The 5200 has a fixed /32 prescaler, uartclk contains the ipb freq */ | |
230 | baud = uart_get_baud_rate(port, new, old, | |
231 | port->uartclk / (32 * 0xffff) + 1, | |
232 | port->uartclk / 32); | |
233 | divisor = (port->uartclk + 16 * baud) / (32 * baud); | |
234 | ||
235 | /* enable the /32 prescaler and set the divisor */ | |
236 | mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); | |
237 | return baud; | |
238 | } | |
239 | ||
240 | static unsigned int mpc5200b_psc_set_baudrate(struct uart_port *port, | |
241 | struct ktermios *new, | |
242 | struct ktermios *old) | |
243 | { | |
244 | unsigned int baud; | |
245 | unsigned int divisor; | |
246 | u16 prescaler; | |
247 | ||
248 | /* The 5200B has a selectable /4 or /32 prescaler, uartclk contains the | |
249 | * ipb freq */ | |
250 | baud = uart_get_baud_rate(port, new, old, | |
251 | port->uartclk / (32 * 0xffff) + 1, | |
252 | port->uartclk / 4); | |
253 | divisor = (port->uartclk + 2 * baud) / (4 * baud); | |
254 | ||
e0955ace FB |
255 | /* select the proper prescaler and set the divisor |
256 | * prefer high prescaler for more tolerance on low baudrates */ | |
257 | if (divisor > 0xffff || baud <= 115200) { | |
0d1f22e4 AD |
258 | divisor = (divisor + 4) / 8; |
259 | prescaler = 0xdd00; /* /32 */ | |
260 | } else | |
261 | prescaler = 0xff00; /* /4 */ | |
262 | mpc52xx_set_divisor(PSC(port), prescaler, divisor); | |
263 | return baud; | |
599f030c JR |
264 | } |
265 | ||
6acc6833 AG |
266 | static void mpc52xx_psc_get_irq(struct uart_port *port, struct device_node *np) |
267 | { | |
9cfb5c05 | 268 | port->irqflags = 0; |
6acc6833 AG |
269 | port->irq = irq_of_parse_and_map(np, 0); |
270 | } | |
271 | ||
272 | /* 52xx specific interrupt handler. The caller holds the port lock */ | |
273 | static irqreturn_t mpc52xx_psc_handle_irq(struct uart_port *port) | |
274 | { | |
275 | return mpc5xxx_uart_process_int(port); | |
276 | } | |
277 | ||
599f030c JR |
278 | static struct psc_ops mpc52xx_psc_ops = { |
279 | .fifo_init = mpc52xx_psc_fifo_init, | |
280 | .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, | |
281 | .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, | |
282 | .rx_rdy = mpc52xx_psc_rx_rdy, | |
283 | .tx_rdy = mpc52xx_psc_tx_rdy, | |
284 | .tx_empty = mpc52xx_psc_tx_empty, | |
285 | .stop_rx = mpc52xx_psc_stop_rx, | |
286 | .start_tx = mpc52xx_psc_start_tx, | |
287 | .stop_tx = mpc52xx_psc_stop_tx, | |
288 | .rx_clr_irq = mpc52xx_psc_rx_clr_irq, | |
289 | .tx_clr_irq = mpc52xx_psc_tx_clr_irq, | |
290 | .write_char = mpc52xx_psc_write_char, | |
291 | .read_char = mpc52xx_psc_read_char, | |
292 | .cw_disable_ints = mpc52xx_psc_cw_disable_ints, | |
293 | .cw_restore_ints = mpc52xx_psc_cw_restore_ints, | |
0d1f22e4 AD |
294 | .set_baudrate = mpc5200_psc_set_baudrate, |
295 | .get_irq = mpc52xx_psc_get_irq, | |
296 | .handle_irq = mpc52xx_psc_handle_irq, | |
297 | }; | |
298 | ||
299 | static struct psc_ops mpc5200b_psc_ops = { | |
300 | .fifo_init = mpc52xx_psc_fifo_init, | |
301 | .raw_rx_rdy = mpc52xx_psc_raw_rx_rdy, | |
302 | .raw_tx_rdy = mpc52xx_psc_raw_tx_rdy, | |
303 | .rx_rdy = mpc52xx_psc_rx_rdy, | |
304 | .tx_rdy = mpc52xx_psc_tx_rdy, | |
305 | .tx_empty = mpc52xx_psc_tx_empty, | |
306 | .stop_rx = mpc52xx_psc_stop_rx, | |
307 | .start_tx = mpc52xx_psc_start_tx, | |
308 | .stop_tx = mpc52xx_psc_stop_tx, | |
309 | .rx_clr_irq = mpc52xx_psc_rx_clr_irq, | |
310 | .tx_clr_irq = mpc52xx_psc_tx_clr_irq, | |
311 | .write_char = mpc52xx_psc_write_char, | |
312 | .read_char = mpc52xx_psc_read_char, | |
313 | .cw_disable_ints = mpc52xx_psc_cw_disable_ints, | |
314 | .cw_restore_ints = mpc52xx_psc_cw_restore_ints, | |
315 | .set_baudrate = mpc5200b_psc_set_baudrate, | |
6acc6833 AG |
316 | .get_irq = mpc52xx_psc_get_irq, |
317 | .handle_irq = mpc52xx_psc_handle_irq, | |
599f030c JR |
318 | }; |
319 | ||
25ae3a07 JR |
320 | #endif /* CONFIG_MPC52xx */ |
321 | ||
322 | #ifdef CONFIG_PPC_MPC512x | |
323 | #define FIFO_512x(port) ((struct mpc512x_psc_fifo __iomem *)(PSC(port)+1)) | |
6acc6833 AG |
324 | |
325 | /* PSC FIFO Controller for mpc512x */ | |
326 | struct psc_fifoc { | |
327 | u32 fifoc_cmd; | |
328 | u32 fifoc_int; | |
329 | u32 fifoc_dma; | |
330 | u32 fifoc_axe; | |
331 | u32 fifoc_debug; | |
332 | }; | |
333 | ||
334 | static struct psc_fifoc __iomem *psc_fifoc; | |
335 | static unsigned int psc_fifoc_irq; | |
336 | ||
25ae3a07 JR |
337 | static void mpc512x_psc_fifo_init(struct uart_port *port) |
338 | { | |
6acc6833 AG |
339 | /* /32 prescaler */ |
340 | out_be16(&PSC(port)->mpc52xx_psc_clock_select, 0xdd00); | |
341 | ||
25ae3a07 JR |
342 | out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_RESET_SLICE); |
343 | out_be32(&FIFO_512x(port)->txcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); | |
344 | out_be32(&FIFO_512x(port)->txalarm, 1); | |
345 | out_be32(&FIFO_512x(port)->tximr, 0); | |
346 | ||
347 | out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_RESET_SLICE); | |
348 | out_be32(&FIFO_512x(port)->rxcmd, MPC512x_PSC_FIFO_ENABLE_SLICE); | |
349 | out_be32(&FIFO_512x(port)->rxalarm, 1); | |
350 | out_be32(&FIFO_512x(port)->rximr, 0); | |
351 | ||
352 | out_be32(&FIFO_512x(port)->tximr, MPC512x_PSC_FIFO_ALARM); | |
353 | out_be32(&FIFO_512x(port)->rximr, MPC512x_PSC_FIFO_ALARM); | |
354 | } | |
355 | ||
356 | static int mpc512x_psc_raw_rx_rdy(struct uart_port *port) | |
357 | { | |
358 | return !(in_be32(&FIFO_512x(port)->rxsr) & MPC512x_PSC_FIFO_EMPTY); | |
359 | } | |
360 | ||
361 | static int mpc512x_psc_raw_tx_rdy(struct uart_port *port) | |
362 | { | |
363 | return !(in_be32(&FIFO_512x(port)->txsr) & MPC512x_PSC_FIFO_FULL); | |
364 | } | |
365 | ||
366 | static int mpc512x_psc_rx_rdy(struct uart_port *port) | |
367 | { | |
368 | return in_be32(&FIFO_512x(port)->rxsr) | |
369 | & in_be32(&FIFO_512x(port)->rximr) | |
370 | & MPC512x_PSC_FIFO_ALARM; | |
371 | } | |
372 | ||
373 | static int mpc512x_psc_tx_rdy(struct uart_port *port) | |
374 | { | |
375 | return in_be32(&FIFO_512x(port)->txsr) | |
376 | & in_be32(&FIFO_512x(port)->tximr) | |
377 | & MPC512x_PSC_FIFO_ALARM; | |
378 | } | |
379 | ||
380 | static int mpc512x_psc_tx_empty(struct uart_port *port) | |
381 | { | |
382 | return in_be32(&FIFO_512x(port)->txsr) | |
383 | & MPC512x_PSC_FIFO_EMPTY; | |
384 | } | |
385 | ||
386 | static void mpc512x_psc_stop_rx(struct uart_port *port) | |
387 | { | |
388 | unsigned long rx_fifo_imr; | |
389 | ||
390 | rx_fifo_imr = in_be32(&FIFO_512x(port)->rximr); | |
391 | rx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; | |
392 | out_be32(&FIFO_512x(port)->rximr, rx_fifo_imr); | |
393 | } | |
394 | ||
395 | static void mpc512x_psc_start_tx(struct uart_port *port) | |
396 | { | |
397 | unsigned long tx_fifo_imr; | |
398 | ||
399 | tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); | |
400 | tx_fifo_imr |= MPC512x_PSC_FIFO_ALARM; | |
401 | out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); | |
402 | } | |
403 | ||
404 | static void mpc512x_psc_stop_tx(struct uart_port *port) | |
405 | { | |
406 | unsigned long tx_fifo_imr; | |
407 | ||
408 | tx_fifo_imr = in_be32(&FIFO_512x(port)->tximr); | |
409 | tx_fifo_imr &= ~MPC512x_PSC_FIFO_ALARM; | |
410 | out_be32(&FIFO_512x(port)->tximr, tx_fifo_imr); | |
411 | } | |
412 | ||
413 | static void mpc512x_psc_rx_clr_irq(struct uart_port *port) | |
414 | { | |
415 | out_be32(&FIFO_512x(port)->rxisr, in_be32(&FIFO_512x(port)->rxisr)); | |
416 | } | |
417 | ||
418 | static void mpc512x_psc_tx_clr_irq(struct uart_port *port) | |
419 | { | |
420 | out_be32(&FIFO_512x(port)->txisr, in_be32(&FIFO_512x(port)->txisr)); | |
421 | } | |
422 | ||
423 | static void mpc512x_psc_write_char(struct uart_port *port, unsigned char c) | |
424 | { | |
425 | out_8(&FIFO_512x(port)->txdata_8, c); | |
426 | } | |
427 | ||
428 | static unsigned char mpc512x_psc_read_char(struct uart_port *port) | |
429 | { | |
430 | return in_8(&FIFO_512x(port)->rxdata_8); | |
431 | } | |
432 | ||
433 | static void mpc512x_psc_cw_disable_ints(struct uart_port *port) | |
434 | { | |
435 | port->read_status_mask = | |
436 | in_be32(&FIFO_512x(port)->tximr) << 16 | | |
437 | in_be32(&FIFO_512x(port)->rximr); | |
438 | out_be32(&FIFO_512x(port)->tximr, 0); | |
439 | out_be32(&FIFO_512x(port)->rximr, 0); | |
440 | } | |
441 | ||
442 | static void mpc512x_psc_cw_restore_ints(struct uart_port *port) | |
443 | { | |
444 | out_be32(&FIFO_512x(port)->tximr, | |
445 | (port->read_status_mask >> 16) & 0x7f); | |
446 | out_be32(&FIFO_512x(port)->rximr, port->read_status_mask & 0x7f); | |
447 | } | |
448 | ||
0d1f22e4 AD |
449 | static unsigned int mpc512x_psc_set_baudrate(struct uart_port *port, |
450 | struct ktermios *new, | |
451 | struct ktermios *old) | |
25ae3a07 | 452 | { |
0d1f22e4 AD |
453 | unsigned int baud; |
454 | unsigned int divisor; | |
455 | ||
456 | /* | |
457 | * The "MPC5121e Microcontroller Reference Manual, Rev. 3" says on | |
458 | * pg. 30-10 that the chip supports a /32 and a /10 prescaler. | |
459 | * Furthermore, it states that "After reset, the prescaler by 10 | |
460 | * for the UART mode is selected", but the reset register value is | |
461 | * 0x0000 which means a /32 prescaler. This is wrong. | |
462 | * | |
463 | * In reality using /32 prescaler doesn't work, as it is not supported! | |
464 | * Use /16 or /10 prescaler, see "MPC5121e Hardware Design Guide", | |
465 | * Chapter 4.1 PSC in UART Mode. | |
466 | * Calculate with a /16 prescaler here. | |
467 | */ | |
468 | ||
469 | /* uartclk contains the ips freq */ | |
470 | baud = uart_get_baud_rate(port, new, old, | |
471 | port->uartclk / (16 * 0xffff) + 1, | |
472 | port->uartclk / 16); | |
473 | divisor = (port->uartclk + 8 * baud) / (16 * baud); | |
474 | ||
475 | /* enable the /16 prescaler and set the divisor */ | |
476 | mpc52xx_set_divisor(PSC(port), 0xdd00, divisor); | |
477 | return baud; | |
25ae3a07 JR |
478 | } |
479 | ||
6acc6833 AG |
480 | /* Init PSC FIFO Controller */ |
481 | static int __init mpc512x_psc_fifoc_init(void) | |
482 | { | |
483 | struct device_node *np; | |
6acc6833 AG |
484 | |
485 | np = of_find_compatible_node(NULL, NULL, | |
486 | "fsl,mpc5121-psc-fifo"); | |
487 | if (!np) { | |
488 | pr_err("%s: Can't find FIFOC node\n", __func__); | |
489 | return -ENODEV; | |
490 | } | |
491 | ||
492 | psc_fifoc = of_iomap(np, 0); | |
493 | if (!psc_fifoc) { | |
494 | pr_err("%s: Can't map FIFOC\n", __func__); | |
05f25abc | 495 | of_node_put(np); |
6acc6833 AG |
496 | return -ENODEV; |
497 | } | |
498 | ||
499 | psc_fifoc_irq = irq_of_parse_and_map(np, 0); | |
500 | of_node_put(np); | |
d4e33fac | 501 | if (psc_fifoc_irq == 0) { |
6acc6833 AG |
502 | pr_err("%s: Can't get FIFOC irq\n", __func__); |
503 | iounmap(psc_fifoc); | |
504 | return -ENODEV; | |
505 | } | |
506 | ||
6acc6833 AG |
507 | return 0; |
508 | } | |
509 | ||
510 | static void __exit mpc512x_psc_fifoc_uninit(void) | |
511 | { | |
512 | iounmap(psc_fifoc); | |
513 | } | |
514 | ||
515 | /* 512x specific interrupt handler. The caller holds the port lock */ | |
516 | static irqreturn_t mpc512x_psc_handle_irq(struct uart_port *port) | |
517 | { | |
518 | unsigned long fifoc_int; | |
519 | int psc_num; | |
520 | ||
521 | /* Read pending PSC FIFOC interrupts */ | |
522 | fifoc_int = in_be32(&psc_fifoc->fifoc_int); | |
523 | ||
524 | /* Check if it is an interrupt for this port */ | |
525 | psc_num = (port->mapbase & 0xf00) >> 8; | |
526 | if (test_bit(psc_num, &fifoc_int) || | |
527 | test_bit(psc_num + 16, &fifoc_int)) | |
528 | return mpc5xxx_uart_process_int(port); | |
529 | ||
530 | return IRQ_NONE; | |
531 | } | |
532 | ||
533 | static int mpc512x_psc_clock(struct uart_port *port, int enable) | |
534 | { | |
535 | struct clk *psc_clk; | |
536 | int psc_num; | |
537 | char clk_name[10]; | |
538 | ||
539 | if (uart_console(port)) | |
540 | return 0; | |
541 | ||
542 | psc_num = (port->mapbase & 0xf00) >> 8; | |
09081e5b | 543 | snprintf(clk_name, sizeof(clk_name), "psc%d_mclk", psc_num); |
6acc6833 AG |
544 | psc_clk = clk_get(port->dev, clk_name); |
545 | if (IS_ERR(psc_clk)) { | |
546 | dev_err(port->dev, "Failed to get PSC clock entry!\n"); | |
547 | return -ENODEV; | |
548 | } | |
549 | ||
550 | dev_dbg(port->dev, "%s %sable\n", clk_name, enable ? "en" : "dis"); | |
551 | ||
552 | if (enable) | |
553 | clk_enable(psc_clk); | |
554 | else | |
555 | clk_disable(psc_clk); | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
560 | static void mpc512x_psc_get_irq(struct uart_port *port, struct device_node *np) | |
561 | { | |
562 | port->irqflags = IRQF_SHARED; | |
563 | port->irq = psc_fifoc_irq; | |
564 | } | |
565 | ||
25ae3a07 JR |
566 | static struct psc_ops mpc512x_psc_ops = { |
567 | .fifo_init = mpc512x_psc_fifo_init, | |
568 | .raw_rx_rdy = mpc512x_psc_raw_rx_rdy, | |
569 | .raw_tx_rdy = mpc512x_psc_raw_tx_rdy, | |
570 | .rx_rdy = mpc512x_psc_rx_rdy, | |
571 | .tx_rdy = mpc512x_psc_tx_rdy, | |
572 | .tx_empty = mpc512x_psc_tx_empty, | |
573 | .stop_rx = mpc512x_psc_stop_rx, | |
574 | .start_tx = mpc512x_psc_start_tx, | |
575 | .stop_tx = mpc512x_psc_stop_tx, | |
576 | .rx_clr_irq = mpc512x_psc_rx_clr_irq, | |
577 | .tx_clr_irq = mpc512x_psc_tx_clr_irq, | |
578 | .write_char = mpc512x_psc_write_char, | |
579 | .read_char = mpc512x_psc_read_char, | |
580 | .cw_disable_ints = mpc512x_psc_cw_disable_ints, | |
581 | .cw_restore_ints = mpc512x_psc_cw_restore_ints, | |
0d1f22e4 | 582 | .set_baudrate = mpc512x_psc_set_baudrate, |
6acc6833 AG |
583 | .clock = mpc512x_psc_clock, |
584 | .fifoc_init = mpc512x_psc_fifoc_init, | |
585 | .fifoc_uninit = mpc512x_psc_fifoc_uninit, | |
586 | .get_irq = mpc512x_psc_get_irq, | |
587 | .handle_irq = mpc512x_psc_handle_irq, | |
25ae3a07 JR |
588 | }; |
589 | #endif | |
590 | ||
76d28e44 | 591 | static const struct psc_ops *psc_ops; |
1da177e4 LT |
592 | |
593 | /* ======================================================================== */ | |
594 | /* UART operations */ | |
595 | /* ======================================================================== */ | |
596 | ||
9b9129e7 | 597 | static unsigned int |
1da177e4 LT |
598 | mpc52xx_uart_tx_empty(struct uart_port *port) |
599 | { | |
599f030c | 600 | return psc_ops->tx_empty(port) ? TIOCSER_TEMT : 0; |
1da177e4 LT |
601 | } |
602 | ||
9b9129e7 | 603 | static void |
1da177e4 LT |
604 | mpc52xx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
605 | { | |
aec739e0 WS |
606 | if (mctrl & TIOCM_RTS) |
607 | out_8(&PSC(port)->op1, MPC52xx_PSC_OP_RTS); | |
608 | else | |
609 | out_8(&PSC(port)->op0, MPC52xx_PSC_OP_RTS); | |
1da177e4 LT |
610 | } |
611 | ||
9b9129e7 | 612 | static unsigned int |
1da177e4 LT |
613 | mpc52xx_uart_get_mctrl(struct uart_port *port) |
614 | { | |
aec739e0 WS |
615 | unsigned int ret = TIOCM_DSR; |
616 | u8 status = in_8(&PSC(port)->mpc52xx_psc_ipcr); | |
617 | ||
618 | if (!(status & MPC52xx_PSC_CTS)) | |
619 | ret |= TIOCM_CTS; | |
620 | if (!(status & MPC52xx_PSC_DCD)) | |
621 | ret |= TIOCM_CAR; | |
622 | ||
623 | return ret; | |
1da177e4 LT |
624 | } |
625 | ||
9b9129e7 | 626 | static void |
b129a8cc | 627 | mpc52xx_uart_stop_tx(struct uart_port *port) |
1da177e4 LT |
628 | { |
629 | /* port->lock taken by caller */ | |
599f030c | 630 | psc_ops->stop_tx(port); |
1da177e4 LT |
631 | } |
632 | ||
9b9129e7 | 633 | static void |
b129a8cc | 634 | mpc52xx_uart_start_tx(struct uart_port *port) |
1da177e4 LT |
635 | { |
636 | /* port->lock taken by caller */ | |
599f030c | 637 | psc_ops->start_tx(port); |
1da177e4 LT |
638 | } |
639 | ||
9b9129e7 | 640 | static void |
1da177e4 LT |
641 | mpc52xx_uart_send_xchar(struct uart_port *port, char ch) |
642 | { | |
643 | unsigned long flags; | |
644 | spin_lock_irqsave(&port->lock, flags); | |
9b9129e7 | 645 | |
1da177e4 LT |
646 | port->x_char = ch; |
647 | if (ch) { | |
648 | /* Make sure tx interrupts are on */ | |
649 | /* Truly necessary ??? They should be anyway */ | |
599f030c | 650 | psc_ops->start_tx(port); |
1da177e4 | 651 | } |
9b9129e7 | 652 | |
1da177e4 LT |
653 | spin_unlock_irqrestore(&port->lock, flags); |
654 | } | |
655 | ||
656 | static void | |
657 | mpc52xx_uart_stop_rx(struct uart_port *port) | |
658 | { | |
659 | /* port->lock taken by caller */ | |
599f030c | 660 | psc_ops->stop_rx(port); |
1da177e4 LT |
661 | } |
662 | ||
663 | static void | |
664 | mpc52xx_uart_enable_ms(struct uart_port *port) | |
665 | { | |
aec739e0 WS |
666 | struct mpc52xx_psc __iomem *psc = PSC(port); |
667 | ||
668 | /* clear D_*-bits by reading them */ | |
669 | in_8(&psc->mpc52xx_psc_ipcr); | |
670 | /* enable CTS and DCD as IPC interrupts */ | |
671 | out_8(&psc->mpc52xx_psc_acr, MPC52xx_PSC_IEC_CTS | MPC52xx_PSC_IEC_DCD); | |
672 | ||
673 | port->read_status_mask |= MPC52xx_PSC_IMR_IPC; | |
674 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); | |
1da177e4 LT |
675 | } |
676 | ||
677 | static void | |
678 | mpc52xx_uart_break_ctl(struct uart_port *port, int ctl) | |
679 | { | |
680 | unsigned long flags; | |
681 | spin_lock_irqsave(&port->lock, flags); | |
682 | ||
406b7d4f JR |
683 | if (ctl == -1) |
684 | out_8(&PSC(port)->command, MPC52xx_PSC_START_BRK); | |
1da177e4 | 685 | else |
406b7d4f | 686 | out_8(&PSC(port)->command, MPC52xx_PSC_STOP_BRK); |
9b9129e7 | 687 | |
1da177e4 LT |
688 | spin_unlock_irqrestore(&port->lock, flags); |
689 | } | |
690 | ||
691 | static int | |
692 | mpc52xx_uart_startup(struct uart_port *port) | |
693 | { | |
694 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
695 | int ret; | |
696 | ||
6acc6833 AG |
697 | if (psc_ops->clock) { |
698 | ret = psc_ops->clock(port, 1); | |
699 | if (ret) | |
700 | return ret; | |
701 | } | |
702 | ||
1da177e4 LT |
703 | /* Request IRQ */ |
704 | ret = request_irq(port->irq, mpc52xx_uart_int, | |
6acc6833 | 705 | port->irqflags, "mpc52xx_psc_uart", port); |
1da177e4 LT |
706 | if (ret) |
707 | return ret; | |
708 | ||
709 | /* Reset/activate the port, clear and enable interrupts */ | |
406b7d4f JR |
710 | out_8(&psc->command, MPC52xx_PSC_RST_RX); |
711 | out_8(&psc->command, MPC52xx_PSC_RST_TX); | |
9b9129e7 | 712 | |
406b7d4f | 713 | out_be32(&psc->sicr, 0); /* UART mode DCD ignored */ |
1da177e4 | 714 | |
599f030c | 715 | psc_ops->fifo_init(port); |
9b9129e7 | 716 | |
406b7d4f JR |
717 | out_8(&psc->command, MPC52xx_PSC_TX_ENABLE); |
718 | out_8(&psc->command, MPC52xx_PSC_RX_ENABLE); | |
9b9129e7 | 719 | |
1da177e4 LT |
720 | return 0; |
721 | } | |
722 | ||
723 | static void | |
724 | mpc52xx_uart_shutdown(struct uart_port *port) | |
725 | { | |
726 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
9b9129e7 | 727 | |
a3481197 | 728 | /* Shut down the port. Leave TX active if on a console port */ |
406b7d4f | 729 | out_8(&psc->command, MPC52xx_PSC_RST_RX); |
a3481197 | 730 | if (!uart_console(port)) |
406b7d4f | 731 | out_8(&psc->command, MPC52xx_PSC_RST_TX); |
9b9129e7 GL |
732 | |
733 | port->read_status_mask = 0; | |
406b7d4f | 734 | out_be16(&psc->mpc52xx_psc_imr, port->read_status_mask); |
1da177e4 | 735 | |
6acc6833 AG |
736 | if (psc_ops->clock) |
737 | psc_ops->clock(port, 0); | |
738 | ||
1da177e4 LT |
739 | /* Release interrupt */ |
740 | free_irq(port->irq, port); | |
741 | } | |
742 | ||
9b9129e7 | 743 | static void |
606d099c | 744 | mpc52xx_uart_set_termios(struct uart_port *port, struct ktermios *new, |
406b7d4f | 745 | struct ktermios *old) |
1da177e4 LT |
746 | { |
747 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
748 | unsigned long flags; | |
749 | unsigned char mr1, mr2; | |
0d1f22e4 AD |
750 | unsigned int j; |
751 | unsigned int baud; | |
9b9129e7 | 752 | |
1da177e4 LT |
753 | /* Prepare what we're gonna write */ |
754 | mr1 = 0; | |
9b9129e7 | 755 | |
1da177e4 | 756 | switch (new->c_cflag & CSIZE) { |
406b7d4f JR |
757 | case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS; |
758 | break; | |
759 | case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS; | |
760 | break; | |
761 | case CS7: mr1 |= MPC52xx_PSC_MODE_7_BITS; | |
762 | break; | |
763 | case CS8: | |
764 | default: mr1 |= MPC52xx_PSC_MODE_8_BITS; | |
1da177e4 LT |
765 | } |
766 | ||
767 | if (new->c_cflag & PARENB) { | |
d3dec96e WS |
768 | if (new->c_cflag & CMSPAR) |
769 | mr1 |= MPC52xx_PSC_MODE_PARFORCE; | |
770 | ||
771 | /* With CMSPAR, PARODD also means high parity (same as termios) */ | |
1da177e4 LT |
772 | mr1 |= (new->c_cflag & PARODD) ? |
773 | MPC52xx_PSC_MODE_PARODD : MPC52xx_PSC_MODE_PAREVEN; | |
d3dec96e | 774 | } else { |
1da177e4 | 775 | mr1 |= MPC52xx_PSC_MODE_PARNONE; |
d3dec96e | 776 | } |
9b9129e7 | 777 | |
1da177e4 LT |
778 | mr2 = 0; |
779 | ||
780 | if (new->c_cflag & CSTOPB) | |
781 | mr2 |= MPC52xx_PSC_MODE_TWO_STOP; | |
782 | else | |
783 | mr2 |= ((new->c_cflag & CSIZE) == CS5) ? | |
784 | MPC52xx_PSC_MODE_ONE_STOP_5_BITS : | |
785 | MPC52xx_PSC_MODE_ONE_STOP; | |
786 | ||
aec739e0 WS |
787 | if (new->c_cflag & CRTSCTS) { |
788 | mr1 |= MPC52xx_PSC_MODE_RXRTS; | |
789 | mr2 |= MPC52xx_PSC_MODE_TXCTS; | |
790 | } | |
1da177e4 | 791 | |
1da177e4 LT |
792 | /* Get the lock */ |
793 | spin_lock_irqsave(&port->lock, flags); | |
794 | ||
c4f01240 NA |
795 | /* Do our best to flush TX & RX, so we don't lose anything */ |
796 | /* But we don't wait indefinitely ! */ | |
1da177e4 LT |
797 | j = 5000000; /* Maximum wait */ |
798 | /* FIXME Can't receive chars since set_termios might be called at early | |
799 | * boot for the console, all stuff is not yet ready to receive at that | |
800 | * time and that just makes the kernel oops */ | |
801 | /* while (j-- && mpc52xx_uart_int_rx_chars(port)); */ | |
599f030c | 802 | while (!mpc52xx_uart_tx_empty(port) && --j) |
1da177e4 LT |
803 | udelay(1); |
804 | ||
805 | if (!j) | |
406b7d4f | 806 | printk(KERN_ERR "mpc52xx_uart.c: " |
1da177e4 | 807 | "Unable to flush RX & TX fifos in-time in set_termios." |
406b7d4f | 808 | "Some chars may have been lost.\n"); |
1da177e4 LT |
809 | |
810 | /* Reset the TX & RX */ | |
406b7d4f JR |
811 | out_8(&psc->command, MPC52xx_PSC_RST_RX); |
812 | out_8(&psc->command, MPC52xx_PSC_RST_TX); | |
1da177e4 LT |
813 | |
814 | /* Send new mode settings */ | |
406b7d4f JR |
815 | out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); |
816 | out_8(&psc->mode, mr1); | |
817 | out_8(&psc->mode, mr2); | |
0d1f22e4 AD |
818 | baud = psc_ops->set_baudrate(port, new, old); |
819 | ||
820 | /* Update the per-port timeout */ | |
821 | uart_update_timeout(port, new->c_cflag, baud); | |
9b9129e7 | 822 | |
aec739e0 WS |
823 | if (UART_ENABLE_MS(port, new->c_cflag)) |
824 | mpc52xx_uart_enable_ms(port); | |
825 | ||
1da177e4 | 826 | /* Reenable TX & RX */ |
406b7d4f JR |
827 | out_8(&psc->command, MPC52xx_PSC_TX_ENABLE); |
828 | out_8(&psc->command, MPC52xx_PSC_RX_ENABLE); | |
1da177e4 LT |
829 | |
830 | /* We're all set, release the lock */ | |
831 | spin_unlock_irqrestore(&port->lock, flags); | |
832 | } | |
833 | ||
834 | static const char * | |
835 | mpc52xx_uart_type(struct uart_port *port) | |
836 | { | |
e44dcb6c WS |
837 | /* |
838 | * We keep using PORT_MPC52xx for historic reasons although it applies | |
839 | * for MPC512x, too, but print "MPC5xxx" to not irritate users | |
840 | */ | |
841 | return port->type == PORT_MPC52xx ? "MPC5xxx PSC" : NULL; | |
1da177e4 LT |
842 | } |
843 | ||
844 | static void | |
845 | mpc52xx_uart_release_port(struct uart_port *port) | |
846 | { | |
406b7d4f JR |
847 | /* remapped by us ? */ |
848 | if (port->flags & UPF_IOREMAP) { | |
1da177e4 LT |
849 | iounmap(port->membase); |
850 | port->membase = NULL; | |
851 | } | |
852 | ||
b9272dfd | 853 | release_mem_region(port->mapbase, sizeof(struct mpc52xx_psc)); |
1da177e4 LT |
854 | } |
855 | ||
856 | static int | |
857 | mpc52xx_uart_request_port(struct uart_port *port) | |
858 | { | |
be618f55 AL |
859 | int err; |
860 | ||
1da177e4 | 861 | if (port->flags & UPF_IOREMAP) /* Need to remap ? */ |
b9272dfd | 862 | port->membase = ioremap(port->mapbase, |
406b7d4f | 863 | sizeof(struct mpc52xx_psc)); |
1da177e4 LT |
864 | |
865 | if (!port->membase) | |
866 | return -EINVAL; | |
867 | ||
b9272dfd | 868 | err = request_mem_region(port->mapbase, sizeof(struct mpc52xx_psc), |
1da177e4 | 869 | "mpc52xx_psc_uart") != NULL ? 0 : -EBUSY; |
be618f55 AL |
870 | |
871 | if (err && (port->flags & UPF_IOREMAP)) { | |
872 | iounmap(port->membase); | |
873 | port->membase = NULL; | |
874 | } | |
875 | ||
876 | return err; | |
1da177e4 LT |
877 | } |
878 | ||
879 | static void | |
880 | mpc52xx_uart_config_port(struct uart_port *port, int flags) | |
881 | { | |
406b7d4f JR |
882 | if ((flags & UART_CONFIG_TYPE) |
883 | && (mpc52xx_uart_request_port(port) == 0)) | |
884 | port->type = PORT_MPC52xx; | |
1da177e4 LT |
885 | } |
886 | ||
887 | static int | |
888 | mpc52xx_uart_verify_port(struct uart_port *port, struct serial_struct *ser) | |
889 | { | |
406b7d4f | 890 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPC52xx) |
1da177e4 LT |
891 | return -EINVAL; |
892 | ||
406b7d4f | 893 | if ((ser->irq != port->irq) || |
b7a8212c | 894 | (ser->io_type != UPIO_MEM) || |
406b7d4f JR |
895 | (ser->baud_base != port->uartclk) || |
896 | (ser->iomem_base != (void *)port->mapbase) || | |
897 | (ser->hub6 != 0)) | |
1da177e4 LT |
898 | return -EINVAL; |
899 | ||
900 | return 0; | |
901 | } | |
902 | ||
903 | ||
904 | static struct uart_ops mpc52xx_uart_ops = { | |
905 | .tx_empty = mpc52xx_uart_tx_empty, | |
906 | .set_mctrl = mpc52xx_uart_set_mctrl, | |
907 | .get_mctrl = mpc52xx_uart_get_mctrl, | |
908 | .stop_tx = mpc52xx_uart_stop_tx, | |
909 | .start_tx = mpc52xx_uart_start_tx, | |
910 | .send_xchar = mpc52xx_uart_send_xchar, | |
911 | .stop_rx = mpc52xx_uart_stop_rx, | |
912 | .enable_ms = mpc52xx_uart_enable_ms, | |
913 | .break_ctl = mpc52xx_uart_break_ctl, | |
914 | .startup = mpc52xx_uart_startup, | |
915 | .shutdown = mpc52xx_uart_shutdown, | |
916 | .set_termios = mpc52xx_uart_set_termios, | |
917 | /* .pm = mpc52xx_uart_pm, Not supported yet */ | |
918 | /* .set_wake = mpc52xx_uart_set_wake, Not supported yet */ | |
919 | .type = mpc52xx_uart_type, | |
920 | .release_port = mpc52xx_uart_release_port, | |
921 | .request_port = mpc52xx_uart_request_port, | |
922 | .config_port = mpc52xx_uart_config_port, | |
923 | .verify_port = mpc52xx_uart_verify_port | |
924 | }; | |
925 | ||
9b9129e7 | 926 | |
1da177e4 LT |
927 | /* ======================================================================== */ |
928 | /* Interrupt handling */ | |
929 | /* ======================================================================== */ | |
9b9129e7 | 930 | |
1da177e4 | 931 | static inline int |
7d12e780 | 932 | mpc52xx_uart_int_rx_chars(struct uart_port *port) |
1da177e4 | 933 | { |
92a19f9c | 934 | struct tty_port *tport = &port->state->port; |
33f0f88f | 935 | unsigned char ch, flag; |
1da177e4 LT |
936 | unsigned short status; |
937 | ||
938 | /* While we can read, do so ! */ | |
599f030c | 939 | while (psc_ops->raw_rx_rdy(port)) { |
1da177e4 | 940 | /* Get the char */ |
599f030c | 941 | ch = psc_ops->read_char(port); |
1da177e4 LT |
942 | |
943 | /* Handle sysreq char */ | |
944 | #ifdef SUPPORT_SYSRQ | |
7d12e780 | 945 | if (uart_handle_sysrq_char(port, ch)) { |
1da177e4 LT |
946 | port->sysrq = 0; |
947 | continue; | |
948 | } | |
949 | #endif | |
950 | ||
951 | /* Store it */ | |
33f0f88f AC |
952 | |
953 | flag = TTY_NORMAL; | |
1da177e4 | 954 | port->icount.rx++; |
9b9129e7 | 955 | |
599f030c JR |
956 | status = in_be16(&PSC(port)->mpc52xx_psc_status); |
957 | ||
406b7d4f JR |
958 | if (status & (MPC52xx_PSC_SR_PE | |
959 | MPC52xx_PSC_SR_FE | | |
960 | MPC52xx_PSC_SR_RB)) { | |
9b9129e7 | 961 | |
1da177e4 | 962 | if (status & MPC52xx_PSC_SR_RB) { |
33f0f88f | 963 | flag = TTY_BREAK; |
1da177e4 | 964 | uart_handle_break(port); |
b6514988 RB |
965 | port->icount.brk++; |
966 | } else if (status & MPC52xx_PSC_SR_PE) { | |
33f0f88f | 967 | flag = TTY_PARITY; |
b6514988 RB |
968 | port->icount.parity++; |
969 | } | |
970 | else if (status & MPC52xx_PSC_SR_FE) { | |
33f0f88f | 971 | flag = TTY_FRAME; |
b6514988 RB |
972 | port->icount.frame++; |
973 | } | |
1da177e4 LT |
974 | |
975 | /* Clear error condition */ | |
406b7d4f | 976 | out_8(&PSC(port)->command, MPC52xx_PSC_RST_ERR_STAT); |
1da177e4 LT |
977 | |
978 | } | |
92a19f9c | 979 | tty_insert_flip_char(tport, ch, flag); |
33f0f88f AC |
980 | if (status & MPC52xx_PSC_SR_OE) { |
981 | /* | |
982 | * Overrun is special, since it's | |
983 | * reported immediately, and doesn't | |
984 | * affect the current character | |
985 | */ | |
92a19f9c | 986 | tty_insert_flip_char(tport, 0, TTY_OVERRUN); |
b6514988 | 987 | port->icount.overrun++; |
33f0f88f | 988 | } |
1da177e4 LT |
989 | } |
990 | ||
fbe543b4 | 991 | spin_unlock(&port->lock); |
2e124b4a | 992 | tty_flip_buffer_push(tport); |
fbe543b4 | 993 | spin_lock(&port->lock); |
9b9129e7 | 994 | |
599f030c | 995 | return psc_ops->raw_rx_rdy(port); |
1da177e4 LT |
996 | } |
997 | ||
998 | static inline int | |
999 | mpc52xx_uart_int_tx_chars(struct uart_port *port) | |
1000 | { | |
ebd2c8f6 | 1001 | struct circ_buf *xmit = &port->state->xmit; |
1da177e4 LT |
1002 | |
1003 | /* Process out of band chars */ | |
1004 | if (port->x_char) { | |
599f030c | 1005 | psc_ops->write_char(port, port->x_char); |
1da177e4 LT |
1006 | port->icount.tx++; |
1007 | port->x_char = 0; | |
1008 | return 1; | |
1009 | } | |
1010 | ||
1011 | /* Nothing to do ? */ | |
1012 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
b129a8cc | 1013 | mpc52xx_uart_stop_tx(port); |
1da177e4 LT |
1014 | return 0; |
1015 | } | |
1016 | ||
1017 | /* Send chars */ | |
599f030c JR |
1018 | while (psc_ops->raw_tx_rdy(port)) { |
1019 | psc_ops->write_char(port, xmit->buf[xmit->tail]); | |
1da177e4 LT |
1020 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
1021 | port->icount.tx++; | |
1022 | if (uart_circ_empty(xmit)) | |
1023 | break; | |
1024 | } | |
1025 | ||
1026 | /* Wake up */ | |
1027 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1028 | uart_write_wakeup(port); | |
1029 | ||
1030 | /* Maybe we're done after all */ | |
1031 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 1032 | mpc52xx_uart_stop_tx(port); |
1da177e4 LT |
1033 | return 0; |
1034 | } | |
1035 | ||
1036 | return 1; | |
1037 | } | |
1038 | ||
9b9129e7 | 1039 | static irqreturn_t |
6acc6833 | 1040 | mpc5xxx_uart_process_int(struct uart_port *port) |
1da177e4 | 1041 | { |
1da177e4 LT |
1042 | unsigned long pass = ISR_PASS_LIMIT; |
1043 | unsigned int keepgoing; | |
aec739e0 | 1044 | u8 status; |
9b9129e7 | 1045 | |
1da177e4 LT |
1046 | /* While we have stuff to do, we continue */ |
1047 | do { | |
1048 | /* If we don't find anything to do, we stop */ | |
9b9129e7 GL |
1049 | keepgoing = 0; |
1050 | ||
599f030c JR |
1051 | psc_ops->rx_clr_irq(port); |
1052 | if (psc_ops->rx_rdy(port)) | |
7d12e780 | 1053 | keepgoing |= mpc52xx_uart_int_rx_chars(port); |
1da177e4 | 1054 | |
599f030c JR |
1055 | psc_ops->tx_clr_irq(port); |
1056 | if (psc_ops->tx_rdy(port)) | |
1da177e4 | 1057 | keepgoing |= mpc52xx_uart_int_tx_chars(port); |
9b9129e7 | 1058 | |
aec739e0 WS |
1059 | status = in_8(&PSC(port)->mpc52xx_psc_ipcr); |
1060 | if (status & MPC52xx_PSC_D_DCD) | |
1061 | uart_handle_dcd_change(port, !(status & MPC52xx_PSC_DCD)); | |
1062 | ||
1063 | if (status & MPC52xx_PSC_D_CTS) | |
1064 | uart_handle_cts_change(port, !(status & MPC52xx_PSC_CTS)); | |
1065 | ||
1da177e4 | 1066 | /* Limit number of iteration */ |
406b7d4f | 1067 | if (!(--pass)) |
1da177e4 LT |
1068 | keepgoing = 0; |
1069 | ||
1070 | } while (keepgoing); | |
9b9129e7 | 1071 | |
1da177e4 LT |
1072 | return IRQ_HANDLED; |
1073 | } | |
1074 | ||
6acc6833 AG |
1075 | static irqreturn_t |
1076 | mpc52xx_uart_int(int irq, void *dev_id) | |
1077 | { | |
1078 | struct uart_port *port = dev_id; | |
1079 | irqreturn_t ret; | |
1080 | ||
1081 | spin_lock(&port->lock); | |
1082 | ||
1083 | ret = psc_ops->handle_irq(port); | |
1084 | ||
1085 | spin_unlock(&port->lock); | |
1086 | ||
1087 | return ret; | |
1088 | } | |
1da177e4 LT |
1089 | |
1090 | /* ======================================================================== */ | |
1091 | /* Console ( if applicable ) */ | |
1092 | /* ======================================================================== */ | |
1093 | ||
1094 | #ifdef CONFIG_SERIAL_MPC52xx_CONSOLE | |
1095 | ||
1096 | static void __init | |
1097 | mpc52xx_console_get_options(struct uart_port *port, | |
406b7d4f | 1098 | int *baud, int *parity, int *bits, int *flow) |
1da177e4 LT |
1099 | { |
1100 | struct mpc52xx_psc __iomem *psc = PSC(port); | |
1101 | unsigned char mr1; | |
1102 | ||
b9272dfd GL |
1103 | pr_debug("mpc52xx_console_get_options(port=%p)\n", port); |
1104 | ||
1da177e4 | 1105 | /* Read the mode registers */ |
406b7d4f | 1106 | out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1); |
1da177e4 | 1107 | mr1 = in_8(&psc->mode); |
9b9129e7 | 1108 | |
1da177e4 | 1109 | /* CT{U,L}R are write-only ! */ |
b9272dfd | 1110 | *baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; |
1da177e4 LT |
1111 | |
1112 | /* Parse them */ | |
1113 | switch (mr1 & MPC52xx_PSC_MODE_BITS_MASK) { | |
406b7d4f JR |
1114 | case MPC52xx_PSC_MODE_5_BITS: |
1115 | *bits = 5; | |
1116 | break; | |
1117 | case MPC52xx_PSC_MODE_6_BITS: | |
1118 | *bits = 6; | |
1119 | break; | |
1120 | case MPC52xx_PSC_MODE_7_BITS: | |
1121 | *bits = 7; | |
1122 | break; | |
1123 | case MPC52xx_PSC_MODE_8_BITS: | |
1124 | default: | |
1125 | *bits = 8; | |
1da177e4 | 1126 | } |
9b9129e7 | 1127 | |
1da177e4 LT |
1128 | if (mr1 & MPC52xx_PSC_MODE_PARNONE) |
1129 | *parity = 'n'; | |
1130 | else | |
1131 | *parity = mr1 & MPC52xx_PSC_MODE_PARODD ? 'o' : 'e'; | |
1132 | } | |
1133 | ||
9b9129e7 | 1134 | static void |
1da177e4 LT |
1135 | mpc52xx_console_write(struct console *co, const char *s, unsigned int count) |
1136 | { | |
1137 | struct uart_port *port = &mpc52xx_uart_ports[co->index]; | |
1da177e4 | 1138 | unsigned int i, j; |
9b9129e7 | 1139 | |
1da177e4 | 1140 | /* Disable interrupts */ |
599f030c | 1141 | psc_ops->cw_disable_ints(port); |
1da177e4 LT |
1142 | |
1143 | /* Wait the TX buffer to be empty */ | |
9b9129e7 | 1144 | j = 5000000; /* Maximum wait */ |
599f030c | 1145 | while (!mpc52xx_uart_tx_empty(port) && --j) |
1da177e4 LT |
1146 | udelay(1); |
1147 | ||
1148 | /* Write all the chars */ | |
d358788f | 1149 | for (i = 0; i < count; i++, s++) { |
1da177e4 | 1150 | /* Line return handling */ |
d358788f | 1151 | if (*s == '\n') |
599f030c | 1152 | psc_ops->write_char(port, '\r'); |
9b9129e7 | 1153 | |
d358788f | 1154 | /* Send the char */ |
599f030c | 1155 | psc_ops->write_char(port, *s); |
d358788f | 1156 | |
1da177e4 | 1157 | /* Wait the TX buffer to be empty */ |
9b9129e7 | 1158 | j = 20000; /* Maximum wait */ |
599f030c | 1159 | while (!mpc52xx_uart_tx_empty(port) && --j) |
1da177e4 LT |
1160 | udelay(1); |
1161 | } | |
1162 | ||
1163 | /* Restore interrupt state */ | |
599f030c | 1164 | psc_ops->cw_restore_ints(port); |
1da177e4 LT |
1165 | } |
1166 | ||
b9272dfd GL |
1167 | |
1168 | static int __init | |
1169 | mpc52xx_console_setup(struct console *co, char *options) | |
1170 | { | |
1171 | struct uart_port *port = &mpc52xx_uart_ports[co->index]; | |
1172 | struct device_node *np = mpc52xx_uart_nodes[co->index]; | |
599f030c | 1173 | unsigned int uartclk; |
b9272dfd GL |
1174 | struct resource res; |
1175 | int ret; | |
1176 | ||
1177 | int baud = CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD; | |
1178 | int bits = 8; | |
1179 | int parity = 'n'; | |
1180 | int flow = 'n'; | |
1181 | ||
1182 | pr_debug("mpc52xx_console_setup co=%p, co->index=%i, options=%s\n", | |
1183 | co, co->index, options); | |
1184 | ||
b898f4f8 | 1185 | if ((co->index < 0) || (co->index >= MPC52xx_PSC_MAXNUM)) { |
b9272dfd GL |
1186 | pr_debug("PSC%x out of range\n", co->index); |
1187 | return -EINVAL; | |
1188 | } | |
1189 | ||
1190 | if (!np) { | |
1191 | pr_debug("PSC%x not found in device tree\n", co->index); | |
1192 | return -EINVAL; | |
1193 | } | |
1194 | ||
1195 | pr_debug("Console on ttyPSC%x is %s\n", | |
406b7d4f | 1196 | co->index, mpc52xx_uart_nodes[co->index]->full_name); |
b9272dfd GL |
1197 | |
1198 | /* Fetch register locations */ | |
406b7d4f JR |
1199 | ret = of_address_to_resource(np, 0, &res); |
1200 | if (ret) { | |
b9272dfd GL |
1201 | pr_debug("Could not get resources for PSC%x\n", co->index); |
1202 | return ret; | |
1203 | } | |
1204 | ||
0d1f22e4 | 1205 | uartclk = mpc5xxx_get_bus_frequency(np); |
599f030c JR |
1206 | if (uartclk == 0) { |
1207 | pr_debug("Could not find uart clock frequency!\n"); | |
b9272dfd GL |
1208 | return -EINVAL; |
1209 | } | |
1210 | ||
1211 | /* Basic port init. Needed since we use some uart_??? func before | |
1212 | * real init for early access */ | |
1213 | spin_lock_init(&port->lock); | |
599f030c | 1214 | port->uartclk = uartclk; |
b9272dfd GL |
1215 | port->ops = &mpc52xx_uart_ops; |
1216 | port->mapbase = res.start; | |
1217 | port->membase = ioremap(res.start, sizeof(struct mpc52xx_psc)); | |
1218 | port->irq = irq_of_parse_and_map(np, 0); | |
1219 | ||
1220 | if (port->membase == NULL) | |
1221 | return -EINVAL; | |
1222 | ||
5dd80d5d | 1223 | pr_debug("mpc52xx-psc uart at %p, mapped to %p, irq=%x, freq=%i\n", |
406b7d4f JR |
1224 | (void *)port->mapbase, port->membase, |
1225 | port->irq, port->uartclk); | |
b9272dfd GL |
1226 | |
1227 | /* Setup the port parameters accoding to options */ | |
1228 | if (options) | |
1229 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1230 | else | |
1231 | mpc52xx_console_get_options(port, &baud, &parity, &bits, &flow); | |
1232 | ||
1233 | pr_debug("Setting console parameters: %i %i%c1 flow=%c\n", | |
406b7d4f | 1234 | baud, bits, parity, flow); |
b9272dfd GL |
1235 | |
1236 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1237 | } | |
b9272dfd | 1238 | |
1da177e4 | 1239 | |
2d8179c0 | 1240 | static struct uart_driver mpc52xx_uart_driver; |
1da177e4 LT |
1241 | |
1242 | static struct console mpc52xx_console = { | |
d62de3aa | 1243 | .name = "ttyPSC", |
1da177e4 LT |
1244 | .write = mpc52xx_console_write, |
1245 | .device = uart_console_device, | |
1246 | .setup = mpc52xx_console_setup, | |
1247 | .flags = CON_PRINTBUFFER, | |
406b7d4f | 1248 | .index = -1, /* Specified on the cmdline (e.g. console=ttyPSC0) */ |
1da177e4 LT |
1249 | .data = &mpc52xx_uart_driver, |
1250 | }; | |
1251 | ||
9b9129e7 GL |
1252 | |
1253 | static int __init | |
1da177e4 LT |
1254 | mpc52xx_console_init(void) |
1255 | { | |
b9272dfd | 1256 | mpc52xx_uart_of_enumerate(); |
1da177e4 LT |
1257 | register_console(&mpc52xx_console); |
1258 | return 0; | |
1259 | } | |
1260 | ||
1261 | console_initcall(mpc52xx_console_init); | |
1262 | ||
1263 | #define MPC52xx_PSC_CONSOLE &mpc52xx_console | |
1264 | #else | |
1265 | #define MPC52xx_PSC_CONSOLE NULL | |
1266 | #endif | |
1267 | ||
1268 | ||
1269 | /* ======================================================================== */ | |
1270 | /* UART Driver */ | |
1271 | /* ======================================================================== */ | |
1272 | ||
1273 | static struct uart_driver mpc52xx_uart_driver = { | |
1da177e4 | 1274 | .driver_name = "mpc52xx_psc_uart", |
d62de3aa | 1275 | .dev_name = "ttyPSC", |
d62de3aa SM |
1276 | .major = SERIAL_PSC_MAJOR, |
1277 | .minor = SERIAL_PSC_MINOR, | |
1da177e4 LT |
1278 | .nr = MPC52xx_PSC_MAXNUM, |
1279 | .cons = MPC52xx_PSC_CONSOLE, | |
1280 | }; | |
1281 | ||
b9272dfd GL |
1282 | /* ======================================================================== */ |
1283 | /* OF Platform Driver */ | |
1284 | /* ======================================================================== */ | |
1285 | ||
52b80482 GL |
1286 | static struct of_device_id mpc52xx_uart_of_match[] = { |
1287 | #ifdef CONFIG_PPC_MPC52xx | |
0d1f22e4 | 1288 | { .compatible = "fsl,mpc5200b-psc-uart", .data = &mpc5200b_psc_ops, }, |
52b80482 GL |
1289 | { .compatible = "fsl,mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, |
1290 | /* binding used by old lite5200 device trees: */ | |
1291 | { .compatible = "mpc5200-psc-uart", .data = &mpc52xx_psc_ops, }, | |
1292 | /* binding used by efika: */ | |
1293 | { .compatible = "mpc5200-serial", .data = &mpc52xx_psc_ops, }, | |
1294 | #endif | |
1295 | #ifdef CONFIG_PPC_MPC512x | |
1296 | { .compatible = "fsl,mpc5121-psc-uart", .data = &mpc512x_psc_ops, }, | |
52b80482 | 1297 | #endif |
bc775eac | 1298 | {}, |
52b80482 GL |
1299 | }; |
1300 | ||
9671f099 | 1301 | static int mpc52xx_uart_of_probe(struct platform_device *op) |
b9272dfd GL |
1302 | { |
1303 | int idx = -1; | |
599f030c | 1304 | unsigned int uartclk; |
b9272dfd GL |
1305 | struct uart_port *port = NULL; |
1306 | struct resource res; | |
1307 | int ret; | |
1308 | ||
b9272dfd GL |
1309 | /* Check validity & presence */ |
1310 | for (idx = 0; idx < MPC52xx_PSC_MAXNUM; idx++) | |
61c7a080 | 1311 | if (mpc52xx_uart_nodes[idx] == op->dev.of_node) |
b9272dfd GL |
1312 | break; |
1313 | if (idx >= MPC52xx_PSC_MAXNUM) | |
1314 | return -EINVAL; | |
1315 | pr_debug("Found %s assigned to ttyPSC%x\n", | |
406b7d4f | 1316 | mpc52xx_uart_nodes[idx]->full_name, idx); |
b9272dfd | 1317 | |
0d1f22e4 AD |
1318 | /* set the uart clock to the input clock of the psc, the different |
1319 | * prescalers are taken into account in the set_baudrate() methods | |
1320 | * of the respective chip */ | |
1321 | uartclk = mpc5xxx_get_bus_frequency(op->dev.of_node); | |
599f030c JR |
1322 | if (uartclk == 0) { |
1323 | dev_dbg(&op->dev, "Could not find uart clock frequency!\n"); | |
b9272dfd GL |
1324 | return -EINVAL; |
1325 | } | |
1326 | ||
1327 | /* Init the port structure */ | |
1328 | port = &mpc52xx_uart_ports[idx]; | |
1329 | ||
1330 | spin_lock_init(&port->lock); | |
599f030c | 1331 | port->uartclk = uartclk; |
b9272dfd GL |
1332 | port->fifosize = 512; |
1333 | port->iotype = UPIO_MEM; | |
1334 | port->flags = UPF_BOOT_AUTOCONF | | |
406b7d4f | 1335 | (uart_console(port) ? 0 : UPF_IOREMAP); |
b9272dfd GL |
1336 | port->line = idx; |
1337 | port->ops = &mpc52xx_uart_ops; | |
1338 | port->dev = &op->dev; | |
1339 | ||
1340 | /* Search for IRQ and mapbase */ | |
61c7a080 | 1341 | ret = of_address_to_resource(op->dev.of_node, 0, &res); |
406b7d4f | 1342 | if (ret) |
b9272dfd GL |
1343 | return ret; |
1344 | ||
1345 | port->mapbase = res.start; | |
418441d9 WS |
1346 | if (!port->mapbase) { |
1347 | dev_dbg(&op->dev, "Could not allocate resources for PSC\n"); | |
1348 | return -EINVAL; | |
1349 | } | |
1350 | ||
61c7a080 | 1351 | psc_ops->get_irq(port, op->dev.of_node); |
d4e33fac | 1352 | if (port->irq == 0) { |
418441d9 WS |
1353 | dev_dbg(&op->dev, "Could not get irq\n"); |
1354 | return -EINVAL; | |
1355 | } | |
b9272dfd | 1356 | |
5dd80d5d | 1357 | dev_dbg(&op->dev, "mpc52xx-psc uart at %p, irq=%x, freq=%i\n", |
406b7d4f | 1358 | (void *)port->mapbase, port->irq, port->uartclk); |
b9272dfd | 1359 | |
b9272dfd GL |
1360 | /* Add the port to the uart sub-system */ |
1361 | ret = uart_add_one_port(&mpc52xx_uart_driver, port); | |
6acc6833 | 1362 | if (ret) |
418441d9 | 1363 | return ret; |
b9272dfd | 1364 | |
696faedd | 1365 | platform_set_drvdata(op, (void *)port); |
418441d9 | 1366 | return 0; |
b9272dfd GL |
1367 | } |
1368 | ||
1369 | static int | |
2dc11581 | 1370 | mpc52xx_uart_of_remove(struct platform_device *op) |
b9272dfd | 1371 | { |
696faedd | 1372 | struct uart_port *port = platform_get_drvdata(op); |
b9272dfd | 1373 | |
6acc6833 | 1374 | if (port) |
b9272dfd GL |
1375 | uart_remove_one_port(&mpc52xx_uart_driver, port); |
1376 | ||
1377 | return 0; | |
1378 | } | |
1379 | ||
1380 | #ifdef CONFIG_PM | |
1381 | static int | |
2dc11581 | 1382 | mpc52xx_uart_of_suspend(struct platform_device *op, pm_message_t state) |
b9272dfd | 1383 | { |
696faedd | 1384 | struct uart_port *port = (struct uart_port *) platform_get_drvdata(op); |
b9272dfd GL |
1385 | |
1386 | if (port) | |
1387 | uart_suspend_port(&mpc52xx_uart_driver, port); | |
1388 | ||
1389 | return 0; | |
1390 | } | |
1391 | ||
1392 | static int | |
2dc11581 | 1393 | mpc52xx_uart_of_resume(struct platform_device *op) |
b9272dfd | 1394 | { |
696faedd | 1395 | struct uart_port *port = (struct uart_port *) platform_get_drvdata(op); |
b9272dfd GL |
1396 | |
1397 | if (port) | |
1398 | uart_resume_port(&mpc52xx_uart_driver, port); | |
1399 | ||
1400 | return 0; | |
1401 | } | |
1402 | #endif | |
1403 | ||
1404 | static void | |
3b5ebf8e | 1405 | mpc52xx_uart_of_assign(struct device_node *np) |
b9272dfd | 1406 | { |
b9272dfd GL |
1407 | int i; |
1408 | ||
3b5ebf8e | 1409 | /* Find the first free PSC number */ |
b9272dfd GL |
1410 | for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { |
1411 | if (mpc52xx_uart_nodes[i] == NULL) { | |
3b5ebf8e GL |
1412 | of_node_get(np); |
1413 | mpc52xx_uart_nodes[i] = np; | |
1414 | return; | |
b9272dfd GL |
1415 | } |
1416 | } | |
b9272dfd GL |
1417 | } |
1418 | ||
1419 | static void | |
1420 | mpc52xx_uart_of_enumerate(void) | |
1421 | { | |
406b7d4f | 1422 | static int enum_done; |
b9272dfd | 1423 | struct device_node *np; |
25ae3a07 | 1424 | const struct of_device_id *match; |
b9272dfd GL |
1425 | int i; |
1426 | ||
1427 | if (enum_done) | |
1428 | return; | |
1429 | ||
3b5ebf8e GL |
1430 | /* Assign index to each PSC in device tree */ |
1431 | for_each_matching_node(np, mpc52xx_uart_of_match) { | |
25ae3a07 | 1432 | match = of_match_node(mpc52xx_uart_of_match, np); |
25ae3a07 | 1433 | psc_ops = match->data; |
3b5ebf8e | 1434 | mpc52xx_uart_of_assign(np); |
b9272dfd GL |
1435 | } |
1436 | ||
1437 | enum_done = 1; | |
1438 | ||
1439 | for (i = 0; i < MPC52xx_PSC_MAXNUM; i++) { | |
1440 | if (mpc52xx_uart_nodes[i]) | |
1441 | pr_debug("%s assigned to ttyPSC%x\n", | |
406b7d4f | 1442 | mpc52xx_uart_nodes[i]->full_name, i); |
b9272dfd GL |
1443 | } |
1444 | } | |
1445 | ||
1446 | MODULE_DEVICE_TABLE(of, mpc52xx_uart_of_match); | |
1447 | ||
793218df | 1448 | static struct platform_driver mpc52xx_uart_of_driver = { |
b9272dfd GL |
1449 | .probe = mpc52xx_uart_of_probe, |
1450 | .remove = mpc52xx_uart_of_remove, | |
1451 | #ifdef CONFIG_PM | |
1452 | .suspend = mpc52xx_uart_of_suspend, | |
1453 | .resume = mpc52xx_uart_of_resume, | |
1454 | #endif | |
4018294b GL |
1455 | .driver = { |
1456 | .name = "mpc52xx-psc-uart", | |
1457 | .owner = THIS_MODULE, | |
1458 | .of_match_table = mpc52xx_uart_of_match, | |
b9272dfd GL |
1459 | }, |
1460 | }; | |
1da177e4 LT |
1461 | |
1462 | ||
1463 | /* ======================================================================== */ | |
1464 | /* Module */ | |
1465 | /* ======================================================================== */ | |
1466 | ||
1467 | static int __init | |
1468 | mpc52xx_uart_init(void) | |
1469 | { | |
1470 | int ret; | |
1471 | ||
b9272dfd | 1472 | printk(KERN_INFO "Serial: MPC52xx PSC UART driver\n"); |
1da177e4 | 1473 | |
406b7d4f JR |
1474 | ret = uart_register_driver(&mpc52xx_uart_driver); |
1475 | if (ret) { | |
b9272dfd GL |
1476 | printk(KERN_ERR "%s: uart_register_driver failed (%i)\n", |
1477 | __FILE__, ret); | |
1478 | return ret; | |
1da177e4 LT |
1479 | } |
1480 | ||
b9272dfd GL |
1481 | mpc52xx_uart_of_enumerate(); |
1482 | ||
6acc6833 AG |
1483 | /* |
1484 | * Map the PSC FIFO Controller and init if on MPC512x. | |
1485 | */ | |
e6114fa1 | 1486 | if (psc_ops && psc_ops->fifoc_init) { |
6acc6833 AG |
1487 | ret = psc_ops->fifoc_init(); |
1488 | if (ret) | |
9bcc3278 | 1489 | goto err_init; |
6acc6833 AG |
1490 | } |
1491 | ||
793218df | 1492 | ret = platform_driver_register(&mpc52xx_uart_of_driver); |
b9272dfd | 1493 | if (ret) { |
793218df | 1494 | printk(KERN_ERR "%s: platform_driver_register failed (%i)\n", |
b9272dfd | 1495 | __FILE__, ret); |
9bcc3278 | 1496 | goto err_reg; |
b9272dfd | 1497 | } |
b9272dfd GL |
1498 | |
1499 | return 0; | |
9bcc3278 WY |
1500 | err_reg: |
1501 | if (psc_ops && psc_ops->fifoc_uninit) | |
1502 | psc_ops->fifoc_uninit(); | |
1503 | err_init: | |
1504 | uart_unregister_driver(&mpc52xx_uart_driver); | |
1505 | return ret; | |
1da177e4 LT |
1506 | } |
1507 | ||
1508 | static void __exit | |
1509 | mpc52xx_uart_exit(void) | |
1510 | { | |
6acc6833 AG |
1511 | if (psc_ops->fifoc_uninit) |
1512 | psc_ops->fifoc_uninit(); | |
1513 | ||
793218df | 1514 | platform_driver_unregister(&mpc52xx_uart_of_driver); |
1da177e4 LT |
1515 | uart_unregister_driver(&mpc52xx_uart_driver); |
1516 | } | |
1517 | ||
1518 | ||
1519 | module_init(mpc52xx_uart_init); | |
1520 | module_exit(mpc52xx_uart_exit); | |
1521 | ||
1522 | MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>"); | |
1523 | MODULE_DESCRIPTION("Freescale MPC52xx PSC UART"); | |
1524 | MODULE_LICENSE("GPL"); |