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tty: mpsc.c: move assignment out of if () block
[deliverable/linux.git] / drivers / tty / serial / mpsc.c
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1da177e4 1/*
1da177e4
LT		 2 * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240,
3 * GT64260, MV64340, MV64360, GT96100, ... ).
4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * Based on an old MPSC driver that was in the linuxppc tree. It appears to
8 * have been created by Chris Zankel (formerly of MontaVista) but there
9 * is no proper Copyright so I'm not sure. Apparently, parts were also
10 * taken from PPCBoot (now U-Boot). Also based on drivers/serial/8250.c
11 * by Russell King.
12 *
13 * 2004 (c) MontaVista, Software, Inc. This file is licensed under
14 * the terms of the GNU General Public License version 2. This program
15 * is licensed "as is" without any warranty of any kind, whether express
16 * or implied.
17 */
18/*
19 * The MPSC interface is much like a typical network controller's interface.
20 * That is, you set up separate rings of descriptors for transmitting and
21 * receiving data. There is also a pool of buffers with (one buffer per
22 * descriptor) that incoming data are dma'd into or outgoing data are dma'd
23 * out of.
24 *
25 * The MPSC requires two other controllers to be able to work. The Baud Rate
26 * Generator (BRG) provides a clock at programmable frequencies which determines
27 * the baud rate. The Serial DMA Controller (SDMA) takes incoming data from the
28 * MPSC and DMA's it into memory or DMA's outgoing data and passes it to the
29 * MPSC. It is actually the SDMA interrupt that the driver uses to keep the
30 * transmit and receive "engines" going (i.e., indicate data has been
31 * transmitted or received).
32 *
33 * NOTES:
34 *
35 * 1) Some chips have an erratum where several regs cannot be
36 * read. To work around that, we keep a local copy of those regs in
37 * 'mpsc_port_info'.
38 *
39 * 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr
40 * accesses system mem with coherency enabled. For that reason, the driver
41 * assumes that coherency for that ctlr has been disabled. This means
42 * that when in a cache coherent system, the driver has to manually manage
43 * the data cache on the areas that it touches because the dma_* macro are
44 * basically no-ops.
45 *
46 * 3) There is an erratum (on PPC) where you can't use the instruction to do
47 * a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places
48 * where a DMA_TO_DEVICE/clean would have [otherwise] sufficed.
49 *
50 * 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
51 */
52
e4294b3e
MG		 53
54#if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
55#define SUPPORT_SYSRQ
56#endif
57
58#include <linux/module.h>
59#include <linux/moduleparam.h>
60#include <linux/tty.h>
61#include <linux/tty_flip.h>
62#include <linux/ioport.h>
63#include <linux/init.h>
64#include <linux/console.h>
65#include <linux/sysrq.h>
66#include <linux/serial.h>
67#include <linux/serial_core.h>
68#include <linux/delay.h>
69#include <linux/device.h>
70#include <linux/dma-mapping.h>
71#include <linux/mv643xx.h>
d052d1be 72#include <linux/platform_device.h>
5a0e3ad6 73#include <linux/gfp.h>
d052d1be 74
e4294b3e
MG		 75#include <asm/io.h>
76#include <asm/irq.h>
77
e4294b3e
MG		 78#define MPSC_NUM_CTLRS 2
79
80/*
81 * Descriptors and buffers must be cache line aligned.
82 * Buffers lengths must be multiple of cache line size.
83 * Number of Tx & Rx descriptors must be powers of 2.
84 */
85#define MPSC_RXR_ENTRIES 32
86#define MPSC_RXRE_SIZE dma_get_cache_alignment()
87#define MPSC_RXR_SIZE (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE)
88#define MPSC_RXBE_SIZE dma_get_cache_alignment()
89#define MPSC_RXB_SIZE (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE)
90
91#define MPSC_TXR_ENTRIES 32
92#define MPSC_TXRE_SIZE dma_get_cache_alignment()
93#define MPSC_TXR_SIZE (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE)
94#define MPSC_TXBE_SIZE dma_get_cache_alignment()
95#define MPSC_TXB_SIZE (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
96
2e89db75
MG		 97#define MPSC_DMA_ALLOC_SIZE (MPSC_RXR_SIZE + MPSC_RXB_SIZE + MPSC_TXR_SIZE \
98 + MPSC_TXB_SIZE + dma_get_cache_alignment() /* for alignment */)
e4294b3e
MG		 99
100/* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
101struct mpsc_rx_desc {
102 u16 bufsize;
103 u16 bytecnt;
104 u32 cmdstat;
105 u32 link;
106 u32 buf_ptr;
107} __attribute((packed));
108
109struct mpsc_tx_desc {
110 u16 bytecnt;
111 u16 shadow;
112 u32 cmdstat;
113 u32 link;
114 u32 buf_ptr;
115} __attribute((packed));
116
117/*
118 * Some regs that have the erratum that you can't read them are are shared
119 * between the two MPSC controllers. This struct contains those shared regs.
120 */
121struct mpsc_shared_regs {
122 phys_addr_t mpsc_routing_base_p;
123 phys_addr_t sdma_intr_base_p;
124
125 void __iomem *mpsc_routing_base;
126 void __iomem *sdma_intr_base;
127
128 u32 MPSC_MRR_m;
129 u32 MPSC_RCRR_m;
130 u32 MPSC_TCRR_m;
131 u32 SDMA_INTR_CAUSE_m;
132 u32 SDMA_INTR_MASK_m;
133};
134
135/* The main driver data structure */
136struct mpsc_port_info {
137 struct uart_port port; /* Overlay uart_port structure */
138
139 /* Internal driver state for this ctlr */
140 u8 ready;
141 u8 rcv_data;
142 tcflag_t c_iflag; /* save termios->c_iflag */
143 tcflag_t c_cflag; /* save termios->c_cflag */
144
145 /* Info passed in from platform */
146 u8 mirror_regs; /* Need to mirror regs? */
147 u8 cache_mgmt; /* Need manual cache mgmt? */
148 u8 brg_can_tune; /* BRG has baud tuning? */
149 u32 brg_clk_src;
150 u16 mpsc_max_idle;
151 int default_baud;
152 int default_bits;
153 int default_parity;
154 int default_flow;
155
156 /* Physical addresses of various blocks of registers (from platform) */
157 phys_addr_t mpsc_base_p;
158 phys_addr_t sdma_base_p;
159 phys_addr_t brg_base_p;
160
161 /* Virtual addresses of various blocks of registers (from platform) */
162 void __iomem *mpsc_base;
163 void __iomem *sdma_base;
164 void __iomem *brg_base;
165
166 /* Descriptor ring and buffer allocations */
167 void *dma_region;
168 dma_addr_t dma_region_p;
169
170 dma_addr_t rxr; /* Rx descriptor ring */
171 dma_addr_t rxr_p; /* Phys addr of rxr */
172 u8 *rxb; /* Rx Ring I/O buf */
173 u8 *rxb_p; /* Phys addr of rxb */
174 u32 rxr_posn; /* First desc w/ Rx data */
175
176 dma_addr_t txr; /* Tx descriptor ring */
177 dma_addr_t txr_p; /* Phys addr of txr */
178 u8 *txb; /* Tx Ring I/O buf */
179 u8 *txb_p; /* Phys addr of txb */
180 int txr_head; /* Where new data goes */
181 int txr_tail; /* Where sent data comes off */
1733310b 182 spinlock_t tx_lock; /* transmit lock */
e4294b3e
MG		 183
184 /* Mirrored values of regs we can't read (if 'mirror_regs' set) */
185 u32 MPSC_MPCR_m;
186 u32 MPSC_CHR_1_m;
187 u32 MPSC_CHR_2_m;
188 u32 MPSC_CHR_10_m;
189 u32 BRG_BCR_m;
190 struct mpsc_shared_regs *shared_regs;
191};
192
193/* Hooks to platform-specific code */
194int mpsc_platform_register_driver(void);
195void mpsc_platform_unregister_driver(void);
196
197/* Hooks back in to mpsc common to be called by platform-specific code */
198struct mpsc_port_info *mpsc_device_probe(int index);
199struct mpsc_port_info *mpsc_device_remove(int index);
200
201/* Main MPSC Configuration Register Offsets */
202#define MPSC_MMCRL 0x0000
203#define MPSC_MMCRH 0x0004
204#define MPSC_MPCR 0x0008
205#define MPSC_CHR_1 0x000c
206#define MPSC_CHR_2 0x0010
207#define MPSC_CHR_3 0x0014
208#define MPSC_CHR_4 0x0018
209#define MPSC_CHR_5 0x001c
210#define MPSC_CHR_6 0x0020
211#define MPSC_CHR_7 0x0024
212#define MPSC_CHR_8 0x0028
213#define MPSC_CHR_9 0x002c
214#define MPSC_CHR_10 0x0030
215#define MPSC_CHR_11 0x0034
216
217#define MPSC_MPCR_FRZ (1 << 9)
218#define MPSC_MPCR_CL_5 0
219#define MPSC_MPCR_CL_6 1
220#define MPSC_MPCR_CL_7 2
221#define MPSC_MPCR_CL_8 3
222#define MPSC_MPCR_SBL_1 0
223#define MPSC_MPCR_SBL_2 1
224
225#define MPSC_CHR_2_TEV (1<<1)
226#define MPSC_CHR_2_TA (1<<7)
227#define MPSC_CHR_2_TTCS (1<<9)
228#define MPSC_CHR_2_REV (1<<17)
229#define MPSC_CHR_2_RA (1<<23)
230#define MPSC_CHR_2_CRD (1<<25)
231#define MPSC_CHR_2_EH (1<<31)
232#define MPSC_CHR_2_PAR_ODD 0
233#define MPSC_CHR_2_PAR_SPACE 1
234#define MPSC_CHR_2_PAR_EVEN 2
235#define MPSC_CHR_2_PAR_MARK 3
236
237/* MPSC Signal Routing */
238#define MPSC_MRR 0x0000
239#define MPSC_RCRR 0x0004
240#define MPSC_TCRR 0x0008
241
242/* Serial DMA Controller Interface Registers */
243#define SDMA_SDC 0x0000
244#define SDMA_SDCM 0x0008
245#define SDMA_RX_DESC 0x0800
246#define SDMA_RX_BUF_PTR 0x0808
247#define SDMA_SCRDP 0x0810
248#define SDMA_TX_DESC 0x0c00
249#define SDMA_SCTDP 0x0c10
250#define SDMA_SFTDP 0x0c14
251
252#define SDMA_DESC_CMDSTAT_PE (1<<0)
253#define SDMA_DESC_CMDSTAT_CDL (1<<1)
254#define SDMA_DESC_CMDSTAT_FR (1<<3)
255#define SDMA_DESC_CMDSTAT_OR (1<<6)
256#define SDMA_DESC_CMDSTAT_BR (1<<9)
257#define SDMA_DESC_CMDSTAT_MI (1<<10)
258#define SDMA_DESC_CMDSTAT_A (1<<11)
259#define SDMA_DESC_CMDSTAT_AM (1<<12)
260#define SDMA_DESC_CMDSTAT_CT (1<<13)
261#define SDMA_DESC_CMDSTAT_C (1<<14)
262#define SDMA_DESC_CMDSTAT_ES (1<<15)
263#define SDMA_DESC_CMDSTAT_L (1<<16)
264#define SDMA_DESC_CMDSTAT_F (1<<17)
265#define SDMA_DESC_CMDSTAT_P (1<<18)
266#define SDMA_DESC_CMDSTAT_EI (1<<23)
267#define SDMA_DESC_CMDSTAT_O (1<<31)
268
2e89db75
MG		 269#define SDMA_DESC_DFLT (SDMA_DESC_CMDSTAT_O \
270 | SDMA_DESC_CMDSTAT_EI)
e4294b3e
MG		 271
272#define SDMA_SDC_RFT (1<<0)
273#define SDMA_SDC_SFM (1<<1)
274#define SDMA_SDC_BLMR (1<<6)
275#define SDMA_SDC_BLMT (1<<7)
276#define SDMA_SDC_POVR (1<<8)
277#define SDMA_SDC_RIFB (1<<9)
278
279#define SDMA_SDCM_ERD (1<<7)
280#define SDMA_SDCM_AR (1<<15)
281#define SDMA_SDCM_STD (1<<16)
282#define SDMA_SDCM_TXD (1<<23)
283#define SDMA_SDCM_AT (1<<31)
284
285#define SDMA_0_CAUSE_RXBUF (1<<0)
286#define SDMA_0_CAUSE_RXERR (1<<1)
287#define SDMA_0_CAUSE_TXBUF (1<<2)
288#define SDMA_0_CAUSE_TXEND (1<<3)
289#define SDMA_1_CAUSE_RXBUF (1<<8)
290#define SDMA_1_CAUSE_RXERR (1<<9)
291#define SDMA_1_CAUSE_TXBUF (1<<10)
292#define SDMA_1_CAUSE_TXEND (1<<11)
293
2e89db75
MG		 294#define SDMA_CAUSE_RX_MASK (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR \
295 | SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
296#define SDMA_CAUSE_TX_MASK (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND \
297 | SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
e4294b3e
MG		 298
299/* SDMA Interrupt registers */
300#define SDMA_INTR_CAUSE 0x0000
301#define SDMA_INTR_MASK 0x0080
302
303/* Baud Rate Generator Interface Registers */
304#define BRG_BCR 0x0000
305#define BRG_BTR 0x0004
1da177e4
LT		 306
307/*
308 * Define how this driver is known to the outside (we've been assigned a
309 * range on the "Low-density serial ports" major).
310 */
2e89db75
MG		 311#define MPSC_MAJOR 204
312#define MPSC_MINOR_START 44
313#define MPSC_DRIVER_NAME "MPSC"
314#define MPSC_DEV_NAME "ttyMM"
315#define MPSC_VERSION "1.00"
1da177e4
LT		 316
317static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS];
318static struct mpsc_shared_regs mpsc_shared_regs;
4d0145a7 319static struct uart_driver mpsc_reg;
1da177e4 320
4d0145a7
LN		 321static void mpsc_start_rx(struct mpsc_port_info *pi);
322static void mpsc_free_ring_mem(struct mpsc_port_info *pi);
323static void mpsc_release_port(struct uart_port *port);
1da177e4
LT		 324/*
325 ******************************************************************************
326 *
327 * Baud Rate Generator Routines (BRG)
328 *
329 ******************************************************************************
330 */
2e89db75 331static void mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src)
1da177e4
LT		 332{
333 u32 v;
334
335 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
336 v = (v & ~(0xf << 18)) | ((clk_src & 0xf) << 18);
337
338 if (pi->brg_can_tune)
339 v &= ~(1 << 25);
340
341 if (pi->mirror_regs)
342 pi->BRG_BCR_m = v;
343 writel(v, pi->brg_base + BRG_BCR);
344
345 writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000,
346 pi->brg_base + BRG_BTR);
1da177e4
LT		 347}
348
2e89db75 349static void mpsc_brg_enable(struct mpsc_port_info *pi)
1da177e4
LT		 350{
351 u32 v;
352
353 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
354 v |= (1 << 16);
355
356 if (pi->mirror_regs)
357 pi->BRG_BCR_m = v;
358 writel(v, pi->brg_base + BRG_BCR);
1da177e4
LT		 359}
360
2e89db75 361static void mpsc_brg_disable(struct mpsc_port_info *pi)
1da177e4
LT		 362{
363 u32 v;
364
365 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
366 v &= ~(1 << 16);
367
368 if (pi->mirror_regs)
369 pi->BRG_BCR_m = v;
370 writel(v, pi->brg_base + BRG_BCR);
1da177e4
LT		 371}
372
2e89db75
MG		 373/*
374 * To set the baud, we adjust the CDV field in the BRG_BCR reg.
375 * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1.
376 * However, the input clock is divided by 16 in the MPSC b/c of how
377 * 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our
378 * calculation by 16 to account for that. So the real calculation
379 * that accounts for the way the mpsc is set up is:
380 * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1.
381 */
382static void mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud)
1da177e4 383{
1da177e4
LT		 384 u32 cdv = (pi->port.uartclk / (baud << 5)) - 1;
385 u32 v;
386
387 mpsc_brg_disable(pi);
388 v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR);
389 v = (v & 0xffff0000) | (cdv & 0xffff);
390
391 if (pi->mirror_regs)
392 pi->BRG_BCR_m = v;
393 writel(v, pi->brg_base + BRG_BCR);
394 mpsc_brg_enable(pi);
1da177e4
LT		 395}
396
397/*
398 ******************************************************************************
399 *
400 * Serial DMA Routines (SDMA)
401 *
402 ******************************************************************************
403 */
404
2e89db75 405static void mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size)
1da177e4
LT		 406{
407 u32 v;
408
409 pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n",
2e89db75 410 pi->port.line, burst_size);
1da177e4
LT		 411
412 burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */
413
414 if (burst_size < 2)
415 v = 0x0; /* 1 64-bit word */
416 else if (burst_size < 4)
417 v = 0x1; /* 2 64-bit words */
418 else if (burst_size < 8)
419 v = 0x2; /* 4 64-bit words */
420 else
421 v = 0x3; /* 8 64-bit words */
422
423 writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12),
424 pi->sdma_base + SDMA_SDC);
1da177e4
LT		 425}
426
2e89db75 427static void mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size)
1da177e4
LT		 428{
429 pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line,
430 burst_size);
431
432 writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f,
433 pi->sdma_base + SDMA_SDC);
434 mpsc_sdma_burstsize(pi, burst_size);
1da177e4
LT		 435}
436
2e89db75 437static u32 mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask)
1da177e4
LT		 438{
439 u32 old, v;
440
441 pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask);
442
443 old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m :
444 readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
445
446 mask &= 0xf;
447 if (pi->port.line)
448 mask <<= 8;
449 v &= ~mask;
450
451 if (pi->mirror_regs)
452 pi->shared_regs->SDMA_INTR_MASK_m = v;
453 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
454
455 if (pi->port.line)
456 old >>= 8;
457 return old & 0xf;
458}
459
2e89db75 460static void mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask)
1da177e4
LT		 461{
462 u32 v;
463
464 pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask);
465
2e89db75
MG		 466 v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m
467 : readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
1da177e4
LT		 468
469 mask &= 0xf;
470 if (pi->port.line)
471 mask <<= 8;
472 v |= mask;
473
474 if (pi->mirror_regs)
475 pi->shared_regs->SDMA_INTR_MASK_m = v;
476 writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK);
1da177e4
LT		 477}
478
2e89db75 479static void mpsc_sdma_intr_ack(struct mpsc_port_info *pi)
1da177e4
LT		 480{
481 pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line);
482
483 if (pi->mirror_regs)
484 pi->shared_regs->SDMA_INTR_CAUSE_m = 0;
2e89db75
MG		 485 writeb(0x00, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE
486 + pi->port.line);
1da177e4
LT		 487}
488
2e89db75
MG		 489static void mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi,
490 struct mpsc_rx_desc *rxre_p)
1da177e4
LT		 491{
492 pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n",
2e89db75 493 pi->port.line, (u32)rxre_p);
1da177e4
LT		 494
495 writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP);
1da177e4
LT		 496}
497
2e89db75
MG		 498static void mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi,
499 struct mpsc_tx_desc *txre_p)
1da177e4
LT		 500{
501 writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP);
502 writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP);
1da177e4
LT		 503}
504
2e89db75 505static void mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val)
1da177e4
LT		 506{
507 u32 v;
508
509 v = readl(pi->sdma_base + SDMA_SDCM);
510 if (val)
511 v |= val;
512 else
513 v = 0;
514 wmb();
515 writel(v, pi->sdma_base + SDMA_SDCM);
516 wmb();
1da177e4
LT		 517}
518
2e89db75 519static uint mpsc_sdma_tx_active(struct mpsc_port_info *pi)
1da177e4
LT		 520{
521 return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD;
522}
523
2e89db75 524static void mpsc_sdma_start_tx(struct mpsc_port_info *pi)
1da177e4
LT		 525{
526 struct mpsc_tx_desc *txre, *txre_p;
527
528 /* If tx isn't running & there's a desc ready to go, start it */
529 if (!mpsc_sdma_tx_active(pi)) {
2e89db75
MG		 530 txre = (struct mpsc_tx_desc *)(pi->txr
531 + (pi->txr_tail * MPSC_TXRE_SIZE));
532 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
533 DMA_FROM_DEVICE);
1da177e4
LT		 534#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
535 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
536 invalidate_dcache_range((ulong)txre,
2e89db75 537 (ulong)txre + MPSC_TXRE_SIZE);
1da177e4
LT		 538#endif
539
540 if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) {
2e89db75
MG		 541 txre_p = (struct mpsc_tx_desc *)
542 (pi->txr_p + (pi->txr_tail * MPSC_TXRE_SIZE));
1da177e4
LT		 543
544 mpsc_sdma_set_tx_ring(pi, txre_p);
545 mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD);
546 }
547 }
1da177e4
LT		 548}
549
2e89db75 550static void mpsc_sdma_stop(struct mpsc_port_info *pi)
1da177e4
LT		 551{
552 pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line);
553
554 /* Abort any SDMA transfers */
555 mpsc_sdma_cmd(pi, 0);
556 mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT);
557
558 /* Clear the SDMA current and first TX and RX pointers */
2c6e7599
AV		 559 mpsc_sdma_set_tx_ring(pi, NULL);
560 mpsc_sdma_set_rx_ring(pi, NULL);
1da177e4
LT		 561
562 /* Disable interrupts */
563 mpsc_sdma_intr_mask(pi, 0xf);
564 mpsc_sdma_intr_ack(pi);
1da177e4
LT		 565}
566
567/*
568 ******************************************************************************
569 *
570 * Multi-Protocol Serial Controller Routines (MPSC)
571 *
572 ******************************************************************************
573 */
574
2e89db75 575static void mpsc_hw_init(struct mpsc_port_info *pi)
1da177e4
LT		 576{
577 u32 v;
578
579 pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line);
580
581 /* Set up clock routing */
582 if (pi->mirror_regs) {
583 v = pi->shared_regs->MPSC_MRR_m;
584 v &= ~0x1c7;
585 pi->shared_regs->MPSC_MRR_m = v;
586 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
587
588 v = pi->shared_regs->MPSC_RCRR_m;
589 v = (v & ~0xf0f) | 0x100;
590 pi->shared_regs->MPSC_RCRR_m = v;
591 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
592
593 v = pi->shared_regs->MPSC_TCRR_m;
594 v = (v & ~0xf0f) | 0x100;
595 pi->shared_regs->MPSC_TCRR_m = v;
596 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
2e89db75 597 } else {
1da177e4
LT		 598 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR);
599 v &= ~0x1c7;
600 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR);
601
602 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
603 v = (v & ~0xf0f) | 0x100;
604 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR);
605
606 v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
607 v = (v & ~0xf0f) | 0x100;
608 writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR);
609 }
610
611 /* Put MPSC in UART mode & enabel Tx/Rx egines */
612 writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL);
613
2e89db75 614 /* No preamble, 16x divider, low-latency, */
1da177e4 615 writel(0x04400400, pi->mpsc_base + MPSC_MMCRH);
7bbdc3d5 616 mpsc_set_baudrate(pi, pi->default_baud);
1da177e4
LT		 617
618 if (pi->mirror_regs) {
619 pi->MPSC_CHR_1_m = 0;
620 pi->MPSC_CHR_2_m = 0;
621 }
622 writel(0, pi->mpsc_base + MPSC_CHR_1);
623 writel(0, pi->mpsc_base + MPSC_CHR_2);
624 writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3);
625 writel(0, pi->mpsc_base + MPSC_CHR_4);
626 writel(0, pi->mpsc_base + MPSC_CHR_5);
627 writel(0, pi->mpsc_base + MPSC_CHR_6);
628 writel(0, pi->mpsc_base + MPSC_CHR_7);
629 writel(0, pi->mpsc_base + MPSC_CHR_8);
630 writel(0, pi->mpsc_base + MPSC_CHR_9);
631 writel(0, pi->mpsc_base + MPSC_CHR_10);
1da177e4
LT		 632}
633
2e89db75 634static void mpsc_enter_hunt(struct mpsc_port_info *pi)
1da177e4
LT		 635{
636 pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line);
637
638 if (pi->mirror_regs) {
639 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH,
640 pi->mpsc_base + MPSC_CHR_2);
641 /* Erratum prevents reading CHR_2 so just delay for a while */
642 udelay(100);
2e89db75 643 } else {
1da177e4 644 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH,
2e89db75 645 pi->mpsc_base + MPSC_CHR_2);
1da177e4
LT		 646
647 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH)
648 udelay(10);
649 }
1da177e4
LT		 650}
651
2e89db75 652static void mpsc_freeze(struct mpsc_port_info *pi)
1da177e4
LT		 653{
654 u32 v;
655
656 pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line);
657
658 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
659 readl(pi->mpsc_base + MPSC_MPCR);
660 v |= MPSC_MPCR_FRZ;
661
662 if (pi->mirror_regs)
663 pi->MPSC_MPCR_m = v;
664 writel(v, pi->mpsc_base + MPSC_MPCR);
1da177e4
LT		 665}
666
2e89db75 667static void mpsc_unfreeze(struct mpsc_port_info *pi)
1da177e4
LT		 668{
669 u32 v;
670
671 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
672 readl(pi->mpsc_base + MPSC_MPCR);
673 v &= ~MPSC_MPCR_FRZ;
674
675 if (pi->mirror_regs)
676 pi->MPSC_MPCR_m = v;
677 writel(v, pi->mpsc_base + MPSC_MPCR);
678
679 pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line);
1da177e4
LT		 680}
681
2e89db75 682static void mpsc_set_char_length(struct mpsc_port_info *pi, u32 len)
1da177e4
LT		 683{
684 u32 v;
685
686 pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len);
687
688 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
689 readl(pi->mpsc_base + MPSC_MPCR);
690 v = (v & ~(0x3 << 12)) | ((len & 0x3) << 12);
691
692 if (pi->mirror_regs)
693 pi->MPSC_MPCR_m = v;
694 writel(v, pi->mpsc_base + MPSC_MPCR);
1da177e4
LT		 695}
696
2e89db75 697static void mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len)
1da177e4
LT		 698{
699 u32 v;
700
701 pr_debug("mpsc_set_stop_bit_length[%d]: stop bits: %d\n",
702 pi->port.line, len);
703
704 v = (pi->mirror_regs) ? pi->MPSC_MPCR_m :
705 readl(pi->mpsc_base + MPSC_MPCR);
706
707 v = (v & ~(1 << 14)) | ((len & 0x1) << 14);
708
709 if (pi->mirror_regs)
710 pi->MPSC_MPCR_m = v;
711 writel(v, pi->mpsc_base + MPSC_MPCR);
1da177e4
LT		 712}
713
2e89db75 714static void mpsc_set_parity(struct mpsc_port_info *pi, u32 p)
1da177e4
LT		 715{
716 u32 v;
717
718 pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p);
719
720 v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m :
721 readl(pi->mpsc_base + MPSC_CHR_2);
722
723 p &= 0x3;
724 v = (v & ~0xc000c) | (p << 18) | (p << 2);
725
726 if (pi->mirror_regs)
727 pi->MPSC_CHR_2_m = v;
728 writel(v, pi->mpsc_base + MPSC_CHR_2);
1da177e4
LT		 729}
730
731/*
732 ******************************************************************************
733 *
734 * Driver Init Routines
735 *
736 ******************************************************************************
737 */
738
2e89db75 739static void mpsc_init_hw(struct mpsc_port_info *pi)
1da177e4
LT		 740{
741 pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line);
742
743 mpsc_brg_init(pi, pi->brg_clk_src);
744 mpsc_brg_enable(pi);
745 mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */
746 mpsc_sdma_stop(pi);
747 mpsc_hw_init(pi);
1da177e4
LT		 748}
749
2e89db75 750static int mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
1da177e4
LT		 751{
752 int rc = 0;
1da177e4
LT		 753
754 pr_debug("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n",
755 pi->port.line);
756
757 if (!pi->dma_region) {
758 if (!dma_supported(pi->port.dev, 0xffffffff)) {
759 printk(KERN_ERR "MPSC: Inadequate DMA support\n");
760 rc = -ENXIO;
2e89db75
MG		 761 } else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev,
762 MPSC_DMA_ALLOC_SIZE,
763 &pi->dma_region_p, GFP_KERNEL))
764 == NULL) {
1da177e4
LT		 765 printk(KERN_ERR "MPSC: Can't alloc Desc region\n");
766 rc = -ENOMEM;
767 }
768 }
769
770 return rc;
771}
772
2e89db75 773static void mpsc_free_ring_mem(struct mpsc_port_info *pi)
1da177e4
LT		 774{
775 pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line);
776
777 if (pi->dma_region) {
778 dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE,
2e89db75 779 pi->dma_region, pi->dma_region_p);
1da177e4 780 pi->dma_region = NULL;
2e89db75 781 pi->dma_region_p = (dma_addr_t)NULL;
1da177e4 782 }
1da177e4
LT		 783}
784
2e89db75 785static void mpsc_init_rings(struct mpsc_port_info *pi)
1da177e4
LT		 786{
787 struct mpsc_rx_desc *rxre;
788 struct mpsc_tx_desc *txre;
789 dma_addr_t dp, dp_p;
790 u8 *bp, *bp_p;
791 int i;
792
793 pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line);
794
795 BUG_ON(pi->dma_region == NULL);
796
797 memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE);
798
799 /*
800 * Descriptors & buffers are multiples of cacheline size and must be
801 * cacheline aligned.
802 */
2e89db75
MG		 803 dp = ALIGN((u32)pi->dma_region, dma_get_cache_alignment());
804 dp_p = ALIGN((u32)pi->dma_region_p, dma_get_cache_alignment());
1da177e4
LT		 805
806 /*
807 * Partition dma region into rx ring descriptor, rx buffers,
808 * tx ring descriptors, and tx buffers.
809 */
810 pi->rxr = dp;
811 pi->rxr_p = dp_p;
812 dp += MPSC_RXR_SIZE;
813 dp_p += MPSC_RXR_SIZE;
814
2e89db75
MG		 815 pi->rxb = (u8 *)dp;
816 pi->rxb_p = (u8 *)dp_p;
1da177e4
LT		 817 dp += MPSC_RXB_SIZE;
818 dp_p += MPSC_RXB_SIZE;
819
820 pi->rxr_posn = 0;
821
822 pi->txr = dp;
823 pi->txr_p = dp_p;
824 dp += MPSC_TXR_SIZE;
825 dp_p += MPSC_TXR_SIZE;
826
2e89db75
MG		 827 pi->txb = (u8 *)dp;
828 pi->txb_p = (u8 *)dp_p;
1da177e4
LT		 829
830 pi->txr_head = 0;
831 pi->txr_tail = 0;
832
833 /* Init rx ring descriptors */
834 dp = pi->rxr;
835 dp_p = pi->rxr_p;
836 bp = pi->rxb;
837 bp_p = pi->rxb_p;
838
839 for (i = 0; i < MPSC_RXR_ENTRIES; i++) {
840 rxre = (struct mpsc_rx_desc *)dp;
841
842 rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE);
843 rxre->bytecnt = cpu_to_be16(0);
2e89db75
MG		 844 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
845 | SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F
846 | SDMA_DESC_CMDSTAT_L);
1da177e4
LT		 847 rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE);
848 rxre->buf_ptr = cpu_to_be32(bp_p);
849
850 dp += MPSC_RXRE_SIZE;
851 dp_p += MPSC_RXRE_SIZE;
852 bp += MPSC_RXBE_SIZE;
853 bp_p += MPSC_RXBE_SIZE;
854 }
855 rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */
856
857 /* Init tx ring descriptors */
858 dp = pi->txr;
859 dp_p = pi->txr_p;
860 bp = pi->txb;
861 bp_p = pi->txb_p;
862
863 for (i = 0; i < MPSC_TXR_ENTRIES; i++) {
864 txre = (struct mpsc_tx_desc *)dp;
865
866 txre->link = cpu_to_be32(dp_p + MPSC_TXRE_SIZE);
867 txre->buf_ptr = cpu_to_be32(bp_p);
868
869 dp += MPSC_TXRE_SIZE;
870 dp_p += MPSC_TXRE_SIZE;
871 bp += MPSC_TXBE_SIZE;
872 bp_p += MPSC_TXBE_SIZE;
873 }
874 txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */
875
2e89db75
MG		 876 dma_cache_sync(pi->port.dev, (void *)pi->dma_region,
877 MPSC_DMA_ALLOC_SIZE, DMA_BIDIRECTIONAL);
1da177e4
LT		 878#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
879 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
880 flush_dcache_range((ulong)pi->dma_region,
2e89db75
MG		 881 (ulong)pi->dma_region
882 + MPSC_DMA_ALLOC_SIZE);
1da177e4
LT		 883#endif
884
885 return;
886}
887
2e89db75 888static void mpsc_uninit_rings(struct mpsc_port_info *pi)
1da177e4
LT		 889{
890 pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line);
891
892 BUG_ON(pi->dma_region == NULL);
893
894 pi->rxr = 0;
895 pi->rxr_p = 0;
896 pi->rxb = NULL;
897 pi->rxb_p = NULL;
898 pi->rxr_posn = 0;
899
900 pi->txr = 0;
901 pi->txr_p = 0;
902 pi->txb = NULL;
903 pi->txb_p = NULL;
904 pi->txr_head = 0;
905 pi->txr_tail = 0;
1da177e4
LT		 906}
907
2e89db75 908static int mpsc_make_ready(struct mpsc_port_info *pi)
1da177e4
LT		 909{
910 int rc;
911
912 pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line);
913
914 if (!pi->ready) {
915 mpsc_init_hw(pi);
f2908f70
GKH		 916 rc = mpsc_alloc_ring_mem(pi);
917 if (rc)
1da177e4
LT		 918 return rc;
919 mpsc_init_rings(pi);
920 pi->ready = 1;
921 }
922
923 return 0;
924}
925
3b216c9e
JW		 926#ifdef CONFIG_CONSOLE_POLL
927static int serial_polled;
928#endif
929
1da177e4
LT		 930/*
931 ******************************************************************************
932 *
933 * Interrupt Handling Routines
934 *
935 ******************************************************************************
936 */
937
bf7f5ee3 938static int mpsc_rx_intr(struct mpsc_port_info *pi, unsigned long *flags)
1da177e4
LT		 939{
940 struct mpsc_rx_desc *rxre;
227434f8 941 struct tty_port *port = &pi->port.state->port;
1da177e4
LT		 942 u32 cmdstat, bytes_in, i;
943 int rc = 0;
944 u8 *bp;
945 char flag = TTY_NORMAL;
1da177e4
LT		 946
947 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
948
949 rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE));
950
2e89db75
MG		 951 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
952 DMA_FROM_DEVICE);
1da177e4
LT		 953#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
954 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
955 invalidate_dcache_range((ulong)rxre,
2e89db75 956 (ulong)rxre + MPSC_RXRE_SIZE);
1da177e4
LT		 957#endif
958
959 /*
960 * Loop through Rx descriptors handling ones that have been completed.
961 */
2e89db75
MG		 962 while (!((cmdstat = be32_to_cpu(rxre->cmdstat))
963 & SDMA_DESC_CMDSTAT_O)) {
1da177e4 964 bytes_in = be16_to_cpu(rxre->bytecnt);
3b216c9e
JW		 965#ifdef CONFIG_CONSOLE_POLL
966 if (unlikely(serial_polled)) {
967 serial_polled = 0;
968 return 0;
969 }
970#endif
1da177e4 971 /* Following use of tty struct directly is deprecated */
227434f8 972 if (tty_buffer_request_room(port, bytes_in) < bytes_in) {
bf7f5ee3
VK		 973 if (port->low_latency) {
974 spin_unlock_irqrestore(&pi->port.lock, *flags);
2e124b4a 975 tty_flip_buffer_push(port);
bf7f5ee3
VK		 976 spin_lock_irqsave(&pi->port.lock, *flags);
977 }
1da177e4 978 /*
33f0f88f
AC		 979 * If this failed then we will throw away the bytes
980 * but must do so to clear interrupts.
1da177e4
LT		 981 */
982 }
983
984 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
2e89db75
MG		 985 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_RXBE_SIZE,
986 DMA_FROM_DEVICE);
1da177e4
LT		 987#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
988 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
989 invalidate_dcache_range((ulong)bp,
2e89db75 990 (ulong)bp + MPSC_RXBE_SIZE);
1da177e4
LT		 991#endif
992
993 /*
994 * Other than for parity error, the manual provides little
995 * info on what data will be in a frame flagged by any of
996 * these errors. For parity error, it is the last byte in
997 * the buffer that had the error. As for the rest, I guess
998 * we'll assume there is no data in the buffer.
999 * If there is...it gets lost.
1000 */
2e89db75
MG		 1001 if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
1002 | SDMA_DESC_CMDSTAT_FR
1003 | SDMA_DESC_CMDSTAT_OR))) {
1da177e4
LT		 1004
1005 pi->port.icount.rx++;
1006
1007 if (cmdstat & SDMA_DESC_CMDSTAT_BR) { /* Break */
1008 pi->port.icount.brk++;
1009
1010 if (uart_handle_break(&pi->port))
1011 goto next_frame;
2e89db75 1012 } else if (cmdstat & SDMA_DESC_CMDSTAT_FR) {
1da177e4 1013 pi->port.icount.frame++;
2e89db75 1014 } else if (cmdstat & SDMA_DESC_CMDSTAT_OR) {
1da177e4 1015 pi->port.icount.overrun++;
2e89db75 1016 }
1da177e4
LT		 1017
1018 cmdstat &= pi->port.read_status_mask;
1019
1020 if (cmdstat & SDMA_DESC_CMDSTAT_BR)
1021 flag = TTY_BREAK;
1022 else if (cmdstat & SDMA_DESC_CMDSTAT_FR)
1023 flag = TTY_FRAME;
1024 else if (cmdstat & SDMA_DESC_CMDSTAT_OR)
1025 flag = TTY_OVERRUN;
1026 else if (cmdstat & SDMA_DESC_CMDSTAT_PE)
1027 flag = TTY_PARITY;
1028 }
1029
7d12e780 1030 if (uart_handle_sysrq_char(&pi->port, *bp)) {
1da177e4
LT		 1031 bp++;
1032 bytes_in--;
3b216c9e
JW		 1033#ifdef CONFIG_CONSOLE_POLL
1034 if (unlikely(serial_polled)) {
1035 serial_polled = 0;
1036 return 0;
1037 }
1038#endif
1da177e4
LT		 1039 goto next_frame;
1040 }
1041
2e89db75
MG		 1042 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR
1043 | SDMA_DESC_CMDSTAT_FR
1044 | SDMA_DESC_CMDSTAT_OR)))
1045 && !(cmdstat & pi->port.ignore_status_mask)) {
92a19f9c 1046 tty_insert_flip_char(port, *bp, flag);
2e89db75 1047 } else {
1da177e4 1048 for (i=0; i<bytes_in; i++)
92a19f9c 1049 tty_insert_flip_char(port, *bp++, TTY_NORMAL);
1da177e4
LT		 1050
1051 pi->port.icount.rx += bytes_in;
1052 }
1053
1054next_frame:
1055 rxre->bytecnt = cpu_to_be16(0);
1056 wmb();
2e89db75
MG		 1057 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O
1058 | SDMA_DESC_CMDSTAT_EI | SDMA_DESC_CMDSTAT_F
1059 | SDMA_DESC_CMDSTAT_L);
1da177e4 1060 wmb();
2e89db75
MG		 1061 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
1062 DMA_BIDIRECTIONAL);
1da177e4
LT		 1063#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1064 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1065 flush_dcache_range((ulong)rxre,
2e89db75 1066 (ulong)rxre + MPSC_RXRE_SIZE);
1da177e4
LT		 1067#endif
1068
1069 /* Advance to next descriptor */
1070 pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1);
2e89db75
MG		 1071 rxre = (struct mpsc_rx_desc *)
1072 (pi->rxr + (pi->rxr_posn * MPSC_RXRE_SIZE));
1073 dma_cache_sync(pi->port.dev, (void *)rxre, MPSC_RXRE_SIZE,
1074 DMA_FROM_DEVICE);
1da177e4
LT		 1075#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1076 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1077 invalidate_dcache_range((ulong)rxre,
2e89db75 1078 (ulong)rxre + MPSC_RXRE_SIZE);
1da177e4 1079#endif
1da177e4
LT		 1080 rc = 1;
1081 }
1082
1083 /* Restart rx engine, if its stopped */
1084 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
1085 mpsc_start_rx(pi);
1086
bf7f5ee3 1087 spin_unlock_irqrestore(&pi->port.lock, *flags);
2e124b4a 1088 tty_flip_buffer_push(port);
bf7f5ee3 1089 spin_lock_irqsave(&pi->port.lock, *flags);
1da177e4
LT		 1090 return rc;
1091}
1092
2e89db75 1093static void mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr)
1da177e4
LT		 1094{
1095 struct mpsc_tx_desc *txre;
1096
2e89db75
MG		 1097 txre = (struct mpsc_tx_desc *)(pi->txr
1098 + (pi->txr_head * MPSC_TXRE_SIZE));
1da177e4
LT		 1099
1100 txre->bytecnt = cpu_to_be16(count);
1101 txre->shadow = txre->bytecnt;
1102 wmb(); /* ensure cmdstat is last field updated */
2e89db75
MG		 1103 txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F
1104 | SDMA_DESC_CMDSTAT_L
1105 | ((intr) ? SDMA_DESC_CMDSTAT_EI : 0));
1da177e4 1106 wmb();
2e89db75
MG		 1107 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
1108 DMA_BIDIRECTIONAL);
1da177e4
LT		 1109#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1110 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1111 flush_dcache_range((ulong)txre,
2e89db75 1112 (ulong)txre + MPSC_TXRE_SIZE);
1da177e4 1113#endif
1da177e4
LT		 1114}
1115
2e89db75 1116static void mpsc_copy_tx_data(struct mpsc_port_info *pi)
1da177e4 1117{
ebd2c8f6 1118 struct circ_buf *xmit = &pi->port.state->xmit;
1da177e4
LT		 1119 u8 *bp;
1120 u32 i;
1121
1122 /* Make sure the desc ring isn't full */
2e89db75
MG		 1123 while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES)
1124 < (MPSC_TXR_ENTRIES - 1)) {
1da177e4
LT		 1125 if (pi->port.x_char) {
1126 /*
1127 * Ideally, we should use the TCS field in
1128 * CHR_1 to put the x_char out immediately but
1129 * errata prevents us from being able to read
1130 * CHR_2 to know that its safe to write to
1131 * CHR_1. Instead, just put it in-band with
1132 * all the other Tx data.
1133 */
1134 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1135 *bp = pi->port.x_char;
1136 pi->port.x_char = 0;
1137 i = 1;
2e89db75
MG		 1138 } else if (!uart_circ_empty(xmit)
1139 && !uart_tx_stopped(&pi->port)) {
1140 i = min((u32)MPSC_TXBE_SIZE,
1141 (u32)uart_circ_chars_pending(xmit));
1142 i = min(i, (u32)CIRC_CNT_TO_END(xmit->head, xmit->tail,
1da177e4
LT		 1143 UART_XMIT_SIZE));
1144 bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1145 memcpy(bp, &xmit->buf[xmit->tail], i);
1146 xmit->tail = (xmit->tail + i) & (UART_XMIT_SIZE - 1);
1147
1148 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1149 uart_write_wakeup(&pi->port);
2e89db75 1150 } else { /* All tx data copied into ring bufs */
1da177e4 1151 return;
2e89db75 1152 }
1da177e4 1153
2e89db75
MG		 1154 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE,
1155 DMA_BIDIRECTIONAL);
1da177e4
LT		 1156#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1157 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1158 flush_dcache_range((ulong)bp,
2e89db75 1159 (ulong)bp + MPSC_TXBE_SIZE);
1da177e4
LT		 1160#endif
1161 mpsc_setup_tx_desc(pi, i, 1);
1162
1163 /* Advance to next descriptor */
1164 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1165 }
1da177e4
LT		 1166}
1167
2e89db75 1168static int mpsc_tx_intr(struct mpsc_port_info *pi)
1da177e4
LT		 1169{
1170 struct mpsc_tx_desc *txre;
1171 int rc = 0;
1733310b
DJ		 1172 unsigned long iflags;
1173
1174 spin_lock_irqsave(&pi->tx_lock, iflags);
1da177e4
LT		 1175
1176 if (!mpsc_sdma_tx_active(pi)) {
2e89db75
MG		 1177 txre = (struct mpsc_tx_desc *)(pi->txr
1178 + (pi->txr_tail * MPSC_TXRE_SIZE));
1da177e4 1179
2e89db75
MG		 1180 dma_cache_sync(pi->port.dev, (void *)txre, MPSC_TXRE_SIZE,
1181 DMA_FROM_DEVICE);
1da177e4
LT		 1182#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1183 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1184 invalidate_dcache_range((ulong)txre,
2e89db75 1185 (ulong)txre + MPSC_TXRE_SIZE);
1da177e4
LT		 1186#endif
1187
1188 while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) {
1189 rc = 1;
1190 pi->port.icount.tx += be16_to_cpu(txre->bytecnt);
1191 pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1);
1192
1193 /* If no more data to tx, fall out of loop */
1194 if (pi->txr_head == pi->txr_tail)
1195 break;
1196
2e89db75
MG		 1197 txre = (struct mpsc_tx_desc *)(pi->txr
1198 + (pi->txr_tail * MPSC_TXRE_SIZE));
1199 dma_cache_sync(pi->port.dev, (void *)txre,
1200 MPSC_TXRE_SIZE, DMA_FROM_DEVICE);
1da177e4
LT		 1201#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1202 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1203 invalidate_dcache_range((ulong)txre,
2e89db75 1204 (ulong)txre + MPSC_TXRE_SIZE);
1da177e4
LT		 1205#endif
1206 }
1207
1208 mpsc_copy_tx_data(pi);
1209 mpsc_sdma_start_tx(pi); /* start next desc if ready */
1210 }
1211
1733310b 1212 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1da177e4
LT		 1213 return rc;
1214}
1215
1216/*
1217 * This is the driver's interrupt handler. To avoid a race, we first clear
1218 * the interrupt, then handle any completed Rx/Tx descriptors. When done
1219 * handling those descriptors, we restart the Rx/Tx engines if they're stopped.
1220 */
2e89db75 1221static irqreturn_t mpsc_sdma_intr(int irq, void *dev_id)
1da177e4
LT		 1222{
1223 struct mpsc_port_info *pi = dev_id;
1224 ulong iflags;
1225 int rc = IRQ_NONE;
1226
1227 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line);
1228
1229 spin_lock_irqsave(&pi->port.lock, iflags);
1230 mpsc_sdma_intr_ack(pi);
bf7f5ee3 1231 if (mpsc_rx_intr(pi, &iflags))
1da177e4
LT		 1232 rc = IRQ_HANDLED;
1233 if (mpsc_tx_intr(pi))
1234 rc = IRQ_HANDLED;
1235 spin_unlock_irqrestore(&pi->port.lock, iflags);
1236
1237 pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line);
1238 return rc;
1239}
1240
1241/*
1242 ******************************************************************************
1243 *
1244 * serial_core.c Interface routines
1245 *
1246 ******************************************************************************
1247 */
2e89db75 1248static uint mpsc_tx_empty(struct uart_port *port)
1da177e4 1249{
22d4d44c
FF		 1250 struct mpsc_port_info *pi =
1251 container_of(port, struct mpsc_port_info, port);
1da177e4
LT		 1252 ulong iflags;
1253 uint rc;
1254
1255 spin_lock_irqsave(&pi->port.lock, iflags);
1256 rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT;
1257 spin_unlock_irqrestore(&pi->port.lock, iflags);
1258
1259 return rc;
1260}
1261
2e89db75 1262static void mpsc_set_mctrl(struct uart_port *port, uint mctrl)
1da177e4
LT		 1263{
1264 /* Have no way to set modem control lines AFAICT */
1da177e4
LT		 1265}
1266
2e89db75 1267static uint mpsc_get_mctrl(struct uart_port *port)
1da177e4 1268{
22d4d44c
FF		 1269 struct mpsc_port_info *pi =
1270 container_of(port, struct mpsc_port_info, port);
1da177e4 1271 u32 mflags, status;
1da177e4 1272
2e89db75
MG		 1273 status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m
1274 : readl(pi->mpsc_base + MPSC_CHR_10);
1da177e4
LT		 1275
1276 mflags = 0;
1277 if (status & 0x1)
1278 mflags |= TIOCM_CTS;
1279 if (status & 0x2)
1280 mflags |= TIOCM_CAR;
1281
1282 return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */
1283}
1284
2e89db75 1285static void mpsc_stop_tx(struct uart_port *port)
1da177e4 1286{
22d4d44c
FF		 1287 struct mpsc_port_info *pi =
1288 container_of(port, struct mpsc_port_info, port);
1da177e4 1289
b129a8cc 1290 pr_debug("mpsc_stop_tx[%d]\n", port->line);
1da177e4
LT		 1291
1292 mpsc_freeze(pi);
1da177e4
LT		 1293}
1294
2e89db75 1295static void mpsc_start_tx(struct uart_port *port)
1da177e4 1296{
22d4d44c
FF		 1297 struct mpsc_port_info *pi =
1298 container_of(port, struct mpsc_port_info, port);
1733310b
DJ		 1299 unsigned long iflags;
1300
1301 spin_lock_irqsave(&pi->tx_lock, iflags);
1da177e4
LT		 1302
1303 mpsc_unfreeze(pi);
1304 mpsc_copy_tx_data(pi);
1305 mpsc_sdma_start_tx(pi);
1306
1733310b
DJ		 1307 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1308
b129a8cc 1309 pr_debug("mpsc_start_tx[%d]\n", port->line);
1da177e4
LT		 1310}
1311
2e89db75 1312static void mpsc_start_rx(struct mpsc_port_info *pi)
1da177e4
LT		 1313{
1314 pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line);
1315
1316 if (pi->rcv_data) {
1317 mpsc_enter_hunt(pi);
1318 mpsc_sdma_cmd(pi, SDMA_SDCM_ERD);
1319 }
1da177e4
LT		 1320}
1321
2e89db75 1322static void mpsc_stop_rx(struct uart_port *port)
1da177e4 1323{
22d4d44c
FF		 1324 struct mpsc_port_info *pi =
1325 container_of(port, struct mpsc_port_info, port);
1da177e4
LT		 1326
1327 pr_debug("mpsc_stop_rx[%d]: Stopping...\n", port->line);
1328
6c1ead5e
CS		 1329 if (pi->mirror_regs) {
1330 writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_RA,
1331 pi->mpsc_base + MPSC_CHR_2);
1332 /* Erratum prevents reading CHR_2 so just delay for a while */
1333 udelay(100);
2e89db75 1334 } else {
6c1ead5e 1335 writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_RA,
2e89db75 1336 pi->mpsc_base + MPSC_CHR_2);
6c1ead5e
CS		 1337
1338 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_RA)
1339 udelay(10);
1340 }
1341
1da177e4 1342 mpsc_sdma_cmd(pi, SDMA_SDCM_AR);
1da177e4
LT		 1343}
1344
2e89db75 1345static void mpsc_break_ctl(struct uart_port *port, int ctl)
1da177e4 1346{
22d4d44c
FF		 1347 struct mpsc_port_info *pi =
1348 container_of(port, struct mpsc_port_info, port);
1da177e4
LT		 1349 ulong flags;
1350 u32 v;
1351
1352 v = ctl ? 0x00ff0000 : 0;
1353
1354 spin_lock_irqsave(&pi->port.lock, flags);
1355 if (pi->mirror_regs)
1356 pi->MPSC_CHR_1_m = v;
1357 writel(v, pi->mpsc_base + MPSC_CHR_1);
1358 spin_unlock_irqrestore(&pi->port.lock, flags);
1da177e4
LT		 1359}
1360
2e89db75 1361static int mpsc_startup(struct uart_port *port)
1da177e4 1362{
22d4d44c
FF		 1363 struct mpsc_port_info *pi =
1364 container_of(port, struct mpsc_port_info, port);
1da177e4
LT		 1365 u32 flag = 0;
1366 int rc;
1367
1368 pr_debug("mpsc_startup[%d]: Starting up MPSC, irq: %d\n",
1369 port->line, pi->port.irq);
1370
1371 if ((rc = mpsc_make_ready(pi)) == 0) {
1372 /* Setup IRQ handler */
1373 mpsc_sdma_intr_ack(pi);
1374
1375 /* If irq's are shared, need to set flag */
1376 if (mpsc_ports[0].port.irq == mpsc_ports[1].port.irq)
40663cc7 1377 flag = IRQF_SHARED;
1da177e4
LT		 1378
1379 if (request_irq(pi->port.irq, mpsc_sdma_intr, flag,
2e89db75 1380 "mpsc-sdma", pi))
1da177e4 1381 printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n",
2e89db75 1382 pi->port.irq);
1da177e4
LT		 1383
1384 mpsc_sdma_intr_unmask(pi, 0xf);
2e89db75
MG		 1385 mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p
1386 + (pi->rxr_posn * MPSC_RXRE_SIZE)));
1da177e4
LT		 1387 }
1388
1389 return rc;
1390}
1391
2e89db75 1392static void mpsc_shutdown(struct uart_port *port)
1da177e4 1393{
22d4d44c
FF		 1394 struct mpsc_port_info *pi =
1395 container_of(port, struct mpsc_port_info, port);
1da177e4
LT		 1396
1397 pr_debug("mpsc_shutdown[%d]: Shutting down MPSC\n", port->line);
1398
1399 mpsc_sdma_stop(pi);
1400 free_irq(pi->port.irq, pi);
1da177e4
LT		 1401}
1402
2e89db75 1403static void mpsc_set_termios(struct uart_port *port, struct ktermios *termios,
606d099c 1404 struct ktermios *old)
1da177e4 1405{
22d4d44c
FF		 1406 struct mpsc_port_info *pi =
1407 container_of(port, struct mpsc_port_info, port);
1da177e4
LT		 1408 u32 baud;
1409 ulong flags;
1410 u32 chr_bits, stop_bits, par;
1411
1412 pi->c_iflag = termios->c_iflag;
1413 pi->c_cflag = termios->c_cflag;
1414
1415 switch (termios->c_cflag & CSIZE) {
1416 case CS5:
1417 chr_bits = MPSC_MPCR_CL_5;
1418 break;
1419 case CS6:
1420 chr_bits = MPSC_MPCR_CL_6;
1421 break;
1422 case CS7:
1423 chr_bits = MPSC_MPCR_CL_7;
1424 break;
1425 case CS8:
1426 default:
1427 chr_bits = MPSC_MPCR_CL_8;
1428 break;
1429 }
1430
1431 if (termios->c_cflag & CSTOPB)
1432 stop_bits = MPSC_MPCR_SBL_2;
1433 else
1434 stop_bits = MPSC_MPCR_SBL_1;
1435
1436 par = MPSC_CHR_2_PAR_EVEN;
1437 if (termios->c_cflag & PARENB)
1438 if (termios->c_cflag & PARODD)
1439 par = MPSC_CHR_2_PAR_ODD;
1440#ifdef CMSPAR
1441 if (termios->c_cflag & CMSPAR) {
1442 if (termios->c_cflag & PARODD)
1443 par = MPSC_CHR_2_PAR_MARK;
1444 else
1445 par = MPSC_CHR_2_PAR_SPACE;
1446 }
1447#endif
1448
1449 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk);
1450
1451 spin_lock_irqsave(&pi->port.lock, flags);
1452
1453 uart_update_timeout(port, termios->c_cflag, baud);
1454
1455 mpsc_set_char_length(pi, chr_bits);
1456 mpsc_set_stop_bit_length(pi, stop_bits);
1457 mpsc_set_parity(pi, par);
1458 mpsc_set_baudrate(pi, baud);
1459
1460 /* Characters/events to read */
1da177e4
LT		 1461 pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR;
1462
1463 if (termios->c_iflag & INPCK)
2e89db75
MG		 1464 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE
1465 | SDMA_DESC_CMDSTAT_FR;
1da177e4 1466
ef8b9ddc 1467 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1da177e4
LT		 1468 pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR;
1469
1470 /* Characters/events to ignore */
1471 pi->port.ignore_status_mask = 0;
1472
1473 if (termios->c_iflag & IGNPAR)
2e89db75
MG		 1474 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE
1475 | SDMA_DESC_CMDSTAT_FR;
1da177e4
LT		 1476
1477 if (termios->c_iflag & IGNBRK) {
1478 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR;
1479
1480 if (termios->c_iflag & IGNPAR)
1481 pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR;
1482 }
1483
5797ae36
SC		 1484 if ((termios->c_cflag & CREAD)) {
1485 if (!pi->rcv_data) {
1486 pi->rcv_data = 1;
1487 mpsc_start_rx(pi);
1488 }
1489 } else if (pi->rcv_data) {
1490 mpsc_stop_rx(port);
1da177e4 1491 pi->rcv_data = 0;
5797ae36 1492 }
1da177e4
LT		 1493
1494 spin_unlock_irqrestore(&pi->port.lock, flags);
1da177e4
LT		 1495}
1496
2e89db75 1497static const char *mpsc_type(struct uart_port *port)
1da177e4
LT		 1498{
1499 pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME);
1500 return MPSC_DRIVER_NAME;
1501}
1502
2e89db75 1503static int mpsc_request_port(struct uart_port *port)
1da177e4
LT		 1504{
1505 /* Should make chip/platform specific call */
1506 return 0;
1507}
1508
2e89db75 1509static void mpsc_release_port(struct uart_port *port)
1da177e4 1510{
22d4d44c
FF		 1511 struct mpsc_port_info *pi =
1512 container_of(port, struct mpsc_port_info, port);
1da177e4
LT		 1513
1514 if (pi->ready) {
1515 mpsc_uninit_rings(pi);
1516 mpsc_free_ring_mem(pi);
1517 pi->ready = 0;
1518 }
1da177e4
LT		 1519}
1520
2e89db75 1521static void mpsc_config_port(struct uart_port *port, int flags)
1da177e4 1522{
1da177e4
LT		 1523}
1524
2e89db75 1525static int mpsc_verify_port(struct uart_port *port, struct serial_struct *ser)
1da177e4 1526{
22d4d44c
FF		 1527 struct mpsc_port_info *pi =
1528 container_of(port, struct mpsc_port_info, port);
1da177e4
LT		 1529 int rc = 0;
1530
1531 pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line);
1532
1533 if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPSC)
1534 rc = -EINVAL;
1535 else if (pi->port.irq != ser->irq)
1536 rc = -EINVAL;
1537 else if (ser->io_type != SERIAL_IO_MEM)
1538 rc = -EINVAL;
1539 else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */
1540 rc = -EINVAL;
1541 else if ((void *)pi->port.mapbase != ser->iomem_base)
1542 rc = -EINVAL;
1543 else if (pi->port.iobase != ser->port)
1544 rc = -EINVAL;
1545 else if (ser->hub6 != 0)
1546 rc = -EINVAL;
1547
1548 return rc;
1549}
3b216c9e
JW		 1550#ifdef CONFIG_CONSOLE_POLL
1551/* Serial polling routines for writing and reading from the uart while
1552 * in an interrupt or debug context.
1553 */
1554
1555static char poll_buf[2048];
1556static int poll_ptr;
1557static int poll_cnt;
1558static void mpsc_put_poll_char(struct uart_port *port,
1559 unsigned char c);
1560
1561static int mpsc_get_poll_char(struct uart_port *port)
1562{
22d4d44c
FF		 1563 struct mpsc_port_info *pi =
1564 container_of(port, struct mpsc_port_info, port);
3b216c9e
JW		 1565 struct mpsc_rx_desc *rxre;
1566 u32 cmdstat, bytes_in, i;
1567 u8 *bp;
1568
1569 if (!serial_polled)
1570 serial_polled = 1;
1571
1572 pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
1573
1574 if (poll_cnt) {
1575 poll_cnt--;
1576 return poll_buf[poll_ptr++];
1577 }
1578 poll_ptr = 0;
1579 poll_cnt = 0;
1580
1581 while (poll_cnt == 0) {
1582 rxre = (struct mpsc_rx_desc *)(pi->rxr +
1583 (pi->rxr_posn*MPSC_RXRE_SIZE));
1584 dma_cache_sync(pi->port.dev, (void *)rxre,
1585 MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1586#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1587 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1588 invalidate_dcache_range((ulong)rxre,
1589 (ulong)rxre + MPSC_RXRE_SIZE);
1590#endif
1591 /*
1592 * Loop through Rx descriptors handling ones that have
1593 * been completed.
1594 */
1595 while (poll_cnt == 0 &&
1596 !((cmdstat = be32_to_cpu(rxre->cmdstat)) &
1597 SDMA_DESC_CMDSTAT_O)){
1598 bytes_in = be16_to_cpu(rxre->bytecnt);
1599 bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE);
1600 dma_cache_sync(pi->port.dev, (void *) bp,
1601 MPSC_RXBE_SIZE, DMA_FROM_DEVICE);
1602#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1603 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1604 invalidate_dcache_range((ulong)bp,
1605 (ulong)bp + MPSC_RXBE_SIZE);
1606#endif
1607 if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR |
1608 SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) &&
1609 !(cmdstat & pi->port.ignore_status_mask)) {
1610 poll_buf[poll_cnt] = *bp;
1611 poll_cnt++;
1612 } else {
1613 for (i = 0; i < bytes_in; i++) {
1614 poll_buf[poll_cnt] = *bp++;
1615 poll_cnt++;
1616 }
1617 pi->port.icount.rx += bytes_in;
1618 }
1619 rxre->bytecnt = cpu_to_be16(0);
1620 wmb();
1621 rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O |
1622 SDMA_DESC_CMDSTAT_EI |
1623 SDMA_DESC_CMDSTAT_F |
1624 SDMA_DESC_CMDSTAT_L);
1625 wmb();
1626 dma_cache_sync(pi->port.dev, (void *)rxre,
1627 MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL);
1628#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1629 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1630 flush_dcache_range((ulong)rxre,
1631 (ulong)rxre + MPSC_RXRE_SIZE);
1632#endif
1633
1634 /* Advance to next descriptor */
1635 pi->rxr_posn = (pi->rxr_posn + 1) &
1636 (MPSC_RXR_ENTRIES - 1);
1637 rxre = (struct mpsc_rx_desc *)(pi->rxr +
1638 (pi->rxr_posn * MPSC_RXRE_SIZE));
1639 dma_cache_sync(pi->port.dev, (void *)rxre,
1640 MPSC_RXRE_SIZE, DMA_FROM_DEVICE);
1641#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1642 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1643 invalidate_dcache_range((ulong)rxre,
1644 (ulong)rxre + MPSC_RXRE_SIZE);
1645#endif
1646 }
1647
1648 /* Restart rx engine, if its stopped */
1649 if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0)
1650 mpsc_start_rx(pi);
1651 }
1652 if (poll_cnt) {
1653 poll_cnt--;
1654 return poll_buf[poll_ptr++];
1655 }
1656
1657 return 0;
1658}
1659
1660
1661static void mpsc_put_poll_char(struct uart_port *port,
1662 unsigned char c)
1663{
22d4d44c
FF		 1664 struct mpsc_port_info *pi =
1665 container_of(port, struct mpsc_port_info, port);
3b216c9e
JW		 1666 u32 data;
1667
1668 data = readl(pi->mpsc_base + MPSC_MPCR);
1669 writeb(c, pi->mpsc_base + MPSC_CHR_1);
1670 mb();
1671 data = readl(pi->mpsc_base + MPSC_CHR_2);
1672 data |= MPSC_CHR_2_TTCS;
1673 writel(data, pi->mpsc_base + MPSC_CHR_2);
1674 mb();
1675
1676 while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_TTCS);
1677}
1678#endif
1da177e4
LT		 1679
1680static struct uart_ops mpsc_pops = {
2e89db75
MG		 1681 .tx_empty = mpsc_tx_empty,
1682 .set_mctrl = mpsc_set_mctrl,
1683 .get_mctrl = mpsc_get_mctrl,
1684 .stop_tx = mpsc_stop_tx,
1685 .start_tx = mpsc_start_tx,
1686 .stop_rx = mpsc_stop_rx,
2e89db75
MG		 1687 .break_ctl = mpsc_break_ctl,
1688 .startup = mpsc_startup,
1689 .shutdown = mpsc_shutdown,
1690 .set_termios = mpsc_set_termios,
1691 .type = mpsc_type,
1692 .release_port = mpsc_release_port,
1693 .request_port = mpsc_request_port,
1694 .config_port = mpsc_config_port,
1695 .verify_port = mpsc_verify_port,
3b216c9e
JW		 1696#ifdef CONFIG_CONSOLE_POLL
1697 .poll_get_char = mpsc_get_poll_char,
1698 .poll_put_char = mpsc_put_poll_char,
1699#endif
1da177e4
LT		 1700};
1701
1702/*
1703 ******************************************************************************
1704 *
1705 * Console Interface Routines
1706 *
1707 ******************************************************************************
1708 */
1709
1710#ifdef CONFIG_SERIAL_MPSC_CONSOLE
2e89db75 1711static void mpsc_console_write(struct console *co, const char *s, uint count)
1da177e4
LT		 1712{
1713 struct mpsc_port_info *pi = &mpsc_ports[co->index];
1714 u8 *bp, *dp, add_cr = 0;
1715 int i;
1733310b
DJ		 1716 unsigned long iflags;
1717
1718 spin_lock_irqsave(&pi->tx_lock, iflags);
1719
1720 while (pi->txr_head != pi->txr_tail) {
1721 while (mpsc_sdma_tx_active(pi))
1722 udelay(100);
1723 mpsc_sdma_intr_ack(pi);
1724 mpsc_tx_intr(pi);
1725 }
1da177e4
LT		 1726
1727 while (mpsc_sdma_tx_active(pi))
1728 udelay(100);
1729
1730 while (count > 0) {
1731 bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE);
1732
1733 for (i = 0; i < MPSC_TXBE_SIZE; i++) {
1734 if (count == 0)
1735 break;
1736
1737 if (add_cr) {
1738 *(dp++) = '\r';
1739 add_cr = 0;
2e89db75 1740 } else {
1da177e4
LT		 1741 *(dp++) = *s;
1742
1743 if (*(s++) == '\n') { /* add '\r' after '\n' */
1744 add_cr = 1;
1745 count++;
1746 }
1747 }
1748
1749 count--;
1750 }
1751
2e89db75
MG		 1752 dma_cache_sync(pi->port.dev, (void *)bp, MPSC_TXBE_SIZE,
1753 DMA_BIDIRECTIONAL);
1da177e4
LT		 1754#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
1755 if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */
1756 flush_dcache_range((ulong)bp,
2e89db75 1757 (ulong)bp + MPSC_TXBE_SIZE);
1da177e4
LT		 1758#endif
1759 mpsc_setup_tx_desc(pi, i, 0);
1760 pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1);
1761 mpsc_sdma_start_tx(pi);
1762
1763 while (mpsc_sdma_tx_active(pi))
1764 udelay(100);
1765
1766 pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1);
1767 }
1768
1733310b 1769 spin_unlock_irqrestore(&pi->tx_lock, iflags);
1da177e4
LT		 1770}
1771
2e89db75 1772static int __init mpsc_console_setup(struct console *co, char *options)
1da177e4
LT		 1773{
1774 struct mpsc_port_info *pi;
1775 int baud, bits, parity, flow;
1776
1777 pr_debug("mpsc_console_setup[%d]: options: %s\n", co->index, options);
1778
1779 if (co->index >= MPSC_NUM_CTLRS)
1780 co->index = 0;
1781
1782 pi = &mpsc_ports[co->index];
1783
1784 baud = pi->default_baud;
1785 bits = pi->default_bits;
1786 parity = pi->default_parity;
1787 flow = pi->default_flow;
1788
1789 if (!pi->port.ops)
1790 return -ENODEV;
1791
1792 spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */
1793
1794 if (options)
1795 uart_parse_options(options, &baud, &parity, &bits, &flow);
1796
1797 return uart_set_options(&pi->port, co, baud, parity, bits, flow);
1798}
1799
1da177e4 1800static struct console mpsc_console = {
2e89db75
MG		 1801 .name = MPSC_DEV_NAME,
1802 .write = mpsc_console_write,
1803 .device = uart_console_device,
1804 .setup = mpsc_console_setup,
1805 .flags = CON_PRINTBUFFER,
1806 .index = -1,
1807 .data = &mpsc_reg,
1da177e4
LT		 1808};
1809
2e89db75 1810static int __init mpsc_late_console_init(void)
1da177e4
LT		 1811{
1812 pr_debug("mpsc_late_console_init: Enter\n");
1813
1814 if (!(mpsc_console.flags & CON_ENABLED))
1815 register_console(&mpsc_console);
1816 return 0;
1817}
1818
1819late_initcall(mpsc_late_console_init);
1820
1821#define MPSC_CONSOLE &mpsc_console
1822#else
1823#define MPSC_CONSOLE NULL
1824#endif
1825/*
1826 ******************************************************************************
1827 *
1828 * Dummy Platform Driver to extract & map shared register regions
1829 *
1830 ******************************************************************************
1831 */
2e89db75 1832static void mpsc_resource_err(char *s)
1da177e4
LT		 1833{
1834 printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s);
1da177e4
LT		 1835}
1836
2e89db75 1837static int mpsc_shared_map_regs(struct platform_device *pd)
1da177e4
LT		 1838{
1839 struct resource *r;
1840
1841 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
2e89db75
MG		 1842 MPSC_ROUTING_BASE_ORDER))
1843 && request_mem_region(r->start,
1844 MPSC_ROUTING_REG_BLOCK_SIZE,
1845 "mpsc_routing_regs")) {
1da177e4 1846 mpsc_shared_regs.mpsc_routing_base = ioremap(r->start,
2e89db75 1847 MPSC_ROUTING_REG_BLOCK_SIZE);
1da177e4 1848 mpsc_shared_regs.mpsc_routing_base_p = r->start;
2e89db75 1849 } else {
1da177e4
LT		 1850 mpsc_resource_err("MPSC routing base");
1851 return -ENOMEM;
1852 }
1853
1854 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
2e89db75
MG		 1855 MPSC_SDMA_INTR_BASE_ORDER))
1856 && request_mem_region(r->start,
1857 MPSC_SDMA_INTR_REG_BLOCK_SIZE,
1858 "sdma_intr_regs")) {
1da177e4
LT		 1859 mpsc_shared_regs.sdma_intr_base = ioremap(r->start,
1860 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1861 mpsc_shared_regs.sdma_intr_base_p = r->start;
2e89db75 1862 } else {
1da177e4
LT		 1863 iounmap(mpsc_shared_regs.mpsc_routing_base);
1864 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
2e89db75 1865 MPSC_ROUTING_REG_BLOCK_SIZE);
1da177e4
LT		 1866 mpsc_resource_err("SDMA intr base");
1867 return -ENOMEM;
1868 }
1869
1870 return 0;
1871}
1872
2e89db75 1873static void mpsc_shared_unmap_regs(void)
1da177e4
LT		 1874{
1875 if (!mpsc_shared_regs.mpsc_routing_base) {
1876 iounmap(mpsc_shared_regs.mpsc_routing_base);
1877 release_mem_region(mpsc_shared_regs.mpsc_routing_base_p,
2e89db75 1878 MPSC_ROUTING_REG_BLOCK_SIZE);
1da177e4
LT		 1879 }
1880 if (!mpsc_shared_regs.sdma_intr_base) {
1881 iounmap(mpsc_shared_regs.sdma_intr_base);
1882 release_mem_region(mpsc_shared_regs.sdma_intr_base_p,
2e89db75 1883 MPSC_SDMA_INTR_REG_BLOCK_SIZE);
1da177e4
LT		 1884 }
1885
2c6e7599
AV		 1886 mpsc_shared_regs.mpsc_routing_base = NULL;
1887 mpsc_shared_regs.sdma_intr_base = NULL;
1da177e4
LT		 1888
1889 mpsc_shared_regs.mpsc_routing_base_p = 0;
1890 mpsc_shared_regs.sdma_intr_base_p = 0;
1da177e4
LT		 1891}
1892
2e89db75 1893static int mpsc_shared_drv_probe(struct platform_device *dev)
1da177e4 1894{
1da177e4
LT		 1895 struct mpsc_shared_pdata *pdata;
1896 int rc = -ENODEV;
1897
3ae5eaec 1898 if (dev->id == 0) {
f2908f70
GKH		 1899 rc = mpsc_shared_map_regs(dev);
1900 if (!rc) {
2e89db75 1901 pdata = (struct mpsc_shared_pdata *)
574de559 1902 dev_get_platdata(&dev->dev);
1da177e4
LT		 1903
1904 mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val;
1905 mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val;
1906 mpsc_shared_regs.MPSC_TCRR_m= pdata->tcrr_val;
1907 mpsc_shared_regs.SDMA_INTR_CAUSE_m =
1908 pdata->intr_cause_val;
1909 mpsc_shared_regs.SDMA_INTR_MASK_m =
1910 pdata->intr_mask_val;
1911
1912 rc = 0;
1913 }
1914 }
1915
1916 return rc;
1917}
1918
2e89db75 1919static int mpsc_shared_drv_remove(struct platform_device *dev)
1da177e4 1920{
1da177e4
LT		 1921 int rc = -ENODEV;
1922
3ae5eaec 1923 if (dev->id == 0) {
1da177e4
LT		 1924 mpsc_shared_unmap_regs();
1925 mpsc_shared_regs.MPSC_MRR_m = 0;
1926 mpsc_shared_regs.MPSC_RCRR_m = 0;
1927 mpsc_shared_regs.MPSC_TCRR_m = 0;
1928 mpsc_shared_regs.SDMA_INTR_CAUSE_m = 0;
1929 mpsc_shared_regs.SDMA_INTR_MASK_m = 0;
1930 rc = 0;
1931 }
1932
1933 return rc;
1934}
1935
3ae5eaec 1936static struct platform_driver mpsc_shared_driver = {
1da177e4
LT		 1937 .probe = mpsc_shared_drv_probe,
1938 .remove = mpsc_shared_drv_remove,
3ae5eaec 1939 .driver = {
2e89db75 1940 .name = MPSC_SHARED_NAME,
3ae5eaec 1941 },
1da177e4
LT		 1942};
1943
1944/*
1945 ******************************************************************************
1946 *
1947 * Driver Interface Routines
1948 *
1949 ******************************************************************************
1950 */
1951static struct uart_driver mpsc_reg = {
2e89db75
MG		 1952 .owner = THIS_MODULE,
1953 .driver_name = MPSC_DRIVER_NAME,
1954 .dev_name = MPSC_DEV_NAME,
1955 .major = MPSC_MAJOR,
1956 .minor = MPSC_MINOR_START,
1957 .nr = MPSC_NUM_CTLRS,
1958 .cons = MPSC_CONSOLE,
1da177e4
LT		 1959};
1960
2e89db75
MG		 1961static int mpsc_drv_map_regs(struct mpsc_port_info *pi,
1962 struct platform_device *pd)
1da177e4
LT		 1963{
1964 struct resource *r;
1965
2e89db75
MG		 1966 if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER))
1967 && request_mem_region(r->start, MPSC_REG_BLOCK_SIZE,
1968 "mpsc_regs")) {
1da177e4
LT		 1969 pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE);
1970 pi->mpsc_base_p = r->start;
2e89db75 1971 } else {
1da177e4 1972 mpsc_resource_err("MPSC base");
2e89db75 1973 goto err;
1da177e4
LT		 1974 }
1975
1976 if ((r = platform_get_resource(pd, IORESOURCE_MEM,
2e89db75
MG		 1977 MPSC_SDMA_BASE_ORDER))
1978 && request_mem_region(r->start,
1979 MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) {
1da177e4
LT		 1980 pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE);
1981 pi->sdma_base_p = r->start;
2e89db75 1982 } else {
1da177e4 1983 mpsc_resource_err("SDMA base");
a141a043
AL		 1984 if (pi->mpsc_base) {
1985 iounmap(pi->mpsc_base);
1986 pi->mpsc_base = NULL;
1987 }
2e89db75 1988 goto err;
1da177e4
LT		 1989 }
1990
1991 if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER))
2e89db75
MG		 1992 && request_mem_region(r->start,
1993 MPSC_BRG_REG_BLOCK_SIZE, "brg_regs")) {
1da177e4
LT		 1994 pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE);
1995 pi->brg_base_p = r->start;
2e89db75 1996 } else {
1da177e4 1997 mpsc_resource_err("BRG base");
a141a043
AL		 1998 if (pi->mpsc_base) {
1999 iounmap(pi->mpsc_base);
2000 pi->mpsc_base = NULL;
2001 }
2002 if (pi->sdma_base) {
2003 iounmap(pi->sdma_base);
2004 pi->sdma_base = NULL;
2005 }
2e89db75 2006 goto err;
1da177e4 2007 }
1da177e4 2008 return 0;
2e89db75
MG		 2009
2010err:
2011 return -ENOMEM;
1da177e4
LT		 2012}
2013
2e89db75 2014static void mpsc_drv_unmap_regs(struct mpsc_port_info *pi)
1da177e4
LT		 2015{
2016 if (!pi->mpsc_base) {
2017 iounmap(pi->mpsc_base);
2018 release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE);
2019 }
2020 if (!pi->sdma_base) {
2021 iounmap(pi->sdma_base);
2022 release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE);
2023 }
2024 if (!pi->brg_base) {
2025 iounmap(pi->brg_base);
2026 release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE);
2027 }
2028
2c6e7599
AV		 2029 pi->mpsc_base = NULL;
2030 pi->sdma_base = NULL;
2031 pi->brg_base = NULL;
1da177e4
LT		 2032
2033 pi->mpsc_base_p = 0;
2034 pi->sdma_base_p = 0;
2035 pi->brg_base_p = 0;
1da177e4
LT		 2036}
2037
2e89db75
MG		 2038static void mpsc_drv_get_platform_data(struct mpsc_port_info *pi,
2039 struct platform_device *pd, int num)
1da177e4
LT		 2040{
2041 struct mpsc_pdata *pdata;
2042
5c02fab6 2043 pdata = dev_get_platdata(&pd->dev);
1da177e4
LT		 2044
2045 pi->port.uartclk = pdata->brg_clk_freq;
2046 pi->port.iotype = UPIO_MEM;
2047 pi->port.line = num;
2048 pi->port.type = PORT_MPSC;
2049 pi->port.fifosize = MPSC_TXBE_SIZE;
2050 pi->port.membase = pi->mpsc_base;
2051 pi->port.mapbase = (ulong)pi->mpsc_base;
2052 pi->port.ops = &mpsc_pops;
2053
2054 pi->mirror_regs = pdata->mirror_regs;
2055 pi->cache_mgmt = pdata->cache_mgmt;
2056 pi->brg_can_tune = pdata->brg_can_tune;
2057 pi->brg_clk_src = pdata->brg_clk_src;
2058 pi->mpsc_max_idle = pdata->max_idle;
2059 pi->default_baud = pdata->default_baud;
2060 pi->default_bits = pdata->default_bits;
2061 pi->default_parity = pdata->default_parity;
2062 pi->default_flow = pdata->default_flow;
2063
2064 /* Initial values of mirrored regs */
2065 pi->MPSC_CHR_1_m = pdata->chr_1_val;
2066 pi->MPSC_CHR_2_m = pdata->chr_2_val;
2067 pi->MPSC_CHR_10_m = pdata->chr_10_val;
2068 pi->MPSC_MPCR_m = pdata->mpcr_val;
2069 pi->BRG_BCR_m = pdata->bcr_val;
2070
2071 pi->shared_regs = &mpsc_shared_regs;
2072
2073 pi->port.irq = platform_get_irq(pd, 0);
1da177e4
LT		 2074}
2075
2e89db75 2076static int mpsc_drv_probe(struct platform_device *dev)
1da177e4 2077{
1da177e4
LT		 2078 struct mpsc_port_info *pi;
2079 int rc = -ENODEV;
2080
3ae5eaec 2081 pr_debug("mpsc_drv_probe: Adding MPSC %d\n", dev->id);
1da177e4 2082
3ae5eaec
RK		 2083 if (dev->id < MPSC_NUM_CTLRS) {
2084 pi = &mpsc_ports[dev->id];
1da177e4 2085
f2908f70
GKH		 2086 rc = mpsc_drv_map_regs(pi, dev);
2087 if (!rc) {
3ae5eaec 2088 mpsc_drv_get_platform_data(pi, dev, dev->id);
f467bc14 2089 pi->port.dev = &dev->dev;
1da177e4 2090
f2908f70
GKH		 2091 rc = mpsc_make_ready(pi);
2092 if (!rc) {
1733310b 2093 spin_lock_init(&pi->tx_lock);
f2908f70
GKH		 2094 rc = uart_add_one_port(&mpsc_reg, &pi->port);
2095 if (!rc) {
1da177e4 2096 rc = 0;
2e89db75
MG		 2097 } else {
2098 mpsc_release_port((struct uart_port *)
2099 pi);
1da177e4
LT		 2100 mpsc_drv_unmap_regs(pi);
2101 }
2e89db75 2102 } else {
1da177e4 2103 mpsc_drv_unmap_regs(pi);
2e89db75 2104 }
1da177e4
LT		 2105 }
2106 }
2107
2108 return rc;
2109}
2110
2e89db75 2111static int mpsc_drv_remove(struct platform_device *dev)
1da177e4 2112{
3ae5eaec 2113 pr_debug("mpsc_drv_exit: Removing MPSC %d\n", dev->id);
1da177e4 2114
3ae5eaec
RK		 2115 if (dev->id < MPSC_NUM_CTLRS) {
2116 uart_remove_one_port(&mpsc_reg, &mpsc_ports[dev->id].port);
2e89db75
MG		 2117 mpsc_release_port((struct uart_port *)
2118 &mpsc_ports[dev->id].port);
3ae5eaec 2119 mpsc_drv_unmap_regs(&mpsc_ports[dev->id]);
1da177e4 2120 return 0;
2e89db75 2121 } else {
1da177e4 2122 return -ENODEV;
2e89db75 2123 }
1da177e4
LT		 2124}
2125
3ae5eaec 2126static struct platform_driver mpsc_driver = {
1da177e4
LT		 2127 .probe = mpsc_drv_probe,
2128 .remove = mpsc_drv_remove,
3ae5eaec 2129 .driver = {
2e89db75 2130 .name = MPSC_CTLR_NAME,
3ae5eaec 2131 },
1da177e4
LT		 2132};
2133
2e89db75 2134static int __init mpsc_drv_init(void)
1da177e4
LT		 2135{
2136 int rc;
2137
d87a6d95 2138 printk(KERN_INFO "Serial: MPSC driver\n");
1da177e4
LT		 2139
2140 memset(mpsc_ports, 0, sizeof(mpsc_ports));
2141 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
2142
f2908f70
GKH		 2143 rc = uart_register_driver(&mpsc_reg);
2144 if (!rc) {
2145 rc = platform_driver_register(&mpsc_shared_driver);
2146 if (!rc) {
2147 rc = platform_driver_register(&mpsc_driver);
2148 if (rc) {
3ae5eaec 2149 platform_driver_unregister(&mpsc_shared_driver);
1da177e4
LT		 2150 uart_unregister_driver(&mpsc_reg);
2151 }
2e89db75 2152 } else {
1da177e4 2153 uart_unregister_driver(&mpsc_reg);
2e89db75 2154 }
1da177e4
LT		 2155 }
2156
2157 return rc;
1da177e4
LT		 2158}
2159
2e89db75 2160static void __exit mpsc_drv_exit(void)
1da177e4 2161{
3ae5eaec
RK		 2162 platform_driver_unregister(&mpsc_driver);
2163 platform_driver_unregister(&mpsc_shared_driver);
1da177e4
LT		 2164 uart_unregister_driver(&mpsc_reg);
2165 memset(mpsc_ports, 0, sizeof(mpsc_ports));
2166 memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs));
1da177e4
LT		 2167}
2168
2169module_init(mpsc_drv_init);
2170module_exit(mpsc_drv_exit);
2171
2172MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
d87a6d95 2173MODULE_DESCRIPTION("Generic Marvell MPSC serial/UART driver");
1da177e4
LT		 2174MODULE_VERSION(MPSC_VERSION);
2175MODULE_LICENSE("GPL");
2176MODULE_ALIAS_CHARDEV_MAJOR(MPSC_MAJOR);
e169c139 2177MODULE_ALIAS("platform:" MPSC_CTLR_NAME);
Linux kernel - Deliverables
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