projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
pci_ids.h: remove PCI_VENDOR_ID_ADDIDATA_OLD and PCI_DEVICE_ID_ADDIDATA_APCI7800
[deliverable/linux.git] / drivers / tty / serial / msm_serial.c
CommitLineData
04896a77 1/*
99edb3d1 2 * Driver for msm7k serial device and console
04896a77
RL		 3 *
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
ec8f29e7 6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
04896a77
RL		 7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19# define SUPPORT_SYSRQ
20#endif
21
cfdad2ab 22#include <linux/atomic.h>
04896a77
RL		 23#include <linux/hrtimer.h>
24#include <linux/module.h>
25#include <linux/io.h>
26#include <linux/ioport.h>
27#include <linux/irq.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/tty.h>
31#include <linux/tty_flip.h>
32#include <linux/serial_core.h>
33#include <linux/serial.h>
34#include <linux/clk.h>
35#include <linux/platform_device.h>
ec8f29e7 36#include <linux/delay.h>
cfdad2ab
DB		 37#include <linux/of.h>
38#include <linux/of_device.h>
04896a77
RL		 39
40#include "msm_serial.h"
41
42struct msm_port {
43 struct uart_port uart;
44 char name[16];
45 struct clk *clk;
ec8f29e7 46 struct clk *pclk;
04896a77 47 unsigned int imr;
ec8f29e7
SM		 48 unsigned int *gsbi_base;
49 int is_uartdm;
50 unsigned int old_snap_state;
04896a77
RL		 51};
52
ec8f29e7
SM		 53static inline void wait_for_xmitr(struct uart_port *port, int bits)
54{
55 if (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY))
56 while ((msm_read(port, UART_ISR) & bits) != bits)
57 cpu_relax();
58}
59
04896a77
RL		 60static void msm_stop_tx(struct uart_port *port)
61{
62 struct msm_port *msm_port = UART_TO_MSM(port);
63
64 msm_port->imr &= ~UART_IMR_TXLEV;
65 msm_write(port, msm_port->imr, UART_IMR);
66}
67
68static void msm_start_tx(struct uart_port *port)
69{
70 struct msm_port *msm_port = UART_TO_MSM(port);
71
72 msm_port->imr |= UART_IMR_TXLEV;
73 msm_write(port, msm_port->imr, UART_IMR);
74}
75
76static void msm_stop_rx(struct uart_port *port)
77{
78 struct msm_port *msm_port = UART_TO_MSM(port);
79
80 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
81 msm_write(port, msm_port->imr, UART_IMR);
82}
83
84static void msm_enable_ms(struct uart_port *port)
85{
86 struct msm_port *msm_port = UART_TO_MSM(port);
87
88 msm_port->imr |= UART_IMR_DELTA_CTS;
89 msm_write(port, msm_port->imr, UART_IMR);
90}
91
ec8f29e7
SM		 92static void handle_rx_dm(struct uart_port *port, unsigned int misr)
93{
92a19f9c 94 struct tty_port *tport = &port->state->port;
ec8f29e7
SM		 95 unsigned int sr;
96 int count = 0;
97 struct msm_port *msm_port = UART_TO_MSM(port);
98
99 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
100 port->icount.overrun++;
92a19f9c 101 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
ec8f29e7
SM		 102 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
103 }
104
105 if (misr & UART_IMR_RXSTALE) {
106 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
107 msm_port->old_snap_state;
108 msm_port->old_snap_state = 0;
109 } else {
110 count = 4 * (msm_read(port, UART_RFWR));
111 msm_port->old_snap_state += count;
112 }
113
114 /* TODO: Precise error reporting */
115
116 port->icount.rx += count;
117
118 while (count > 0) {
119 unsigned int c;
120
121 sr = msm_read(port, UART_SR);
122 if ((sr & UART_SR_RX_READY) == 0) {
123 msm_port->old_snap_state -= count;
124 break;
125 }
126 c = msm_read(port, UARTDM_RF);
127 if (sr & UART_SR_RX_BREAK) {
128 port->icount.brk++;
129 if (uart_handle_break(port))
130 continue;
131 } else if (sr & UART_SR_PAR_FRAME_ERR)
132 port->icount.frame++;
133
134 /* TODO: handle sysrq */
05c7cd39 135 tty_insert_flip_string(tport, (char *)&c,
ec8f29e7
SM		 136 (count > 4) ? 4 : count);
137 count -= 4;
138 }
139
2e124b4a 140 tty_flip_buffer_push(tport);
ec8f29e7
SM		 141 if (misr & (UART_IMR_RXSTALE))
142 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
143 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
144 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
145}
146
04896a77
RL		 147static void handle_rx(struct uart_port *port)
148{
92a19f9c 149 struct tty_port *tport = &port->state->port;
04896a77
RL		 150 unsigned int sr;
151
152 /*
153 * Handle overrun. My understanding of the hardware is that overrun
154 * is not tied to the RX buffer, so we handle the case out of band.
155 */
156 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
157 port->icount.overrun++;
92a19f9c 158 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
04896a77
RL		 159 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
160 }
161
162 /* and now the main RX loop */
163 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
164 unsigned int c;
165 char flag = TTY_NORMAL;
166
167 c = msm_read(port, UART_RF);
168
169 if (sr & UART_SR_RX_BREAK) {
170 port->icount.brk++;
171 if (uart_handle_break(port))
172 continue;
173 } else if (sr & UART_SR_PAR_FRAME_ERR) {
174 port->icount.frame++;
175 } else {
176 port->icount.rx++;
177 }
178
179 /* Mask conditions we're ignorning. */
180 sr &= port->read_status_mask;
181
182 if (sr & UART_SR_RX_BREAK) {
183 flag = TTY_BREAK;
184 } else if (sr & UART_SR_PAR_FRAME_ERR) {
185 flag = TTY_FRAME;
186 }
187
188 if (!uart_handle_sysrq_char(port, c))
92a19f9c 189 tty_insert_flip_char(tport, c, flag);
04896a77
RL		 190 }
191
2e124b4a 192 tty_flip_buffer_push(tport);
04896a77
RL		 193}
194
ec8f29e7
SM		 195static void reset_dm_count(struct uart_port *port)
196{
197 wait_for_xmitr(port, UART_ISR_TX_READY);
198 msm_write(port, 1, UARTDM_NCF_TX);
199}
200
04896a77
RL		 201static void handle_tx(struct uart_port *port)
202{
ebd2c8f6 203 struct circ_buf *xmit = &port->state->xmit;
04896a77
RL		 204 struct msm_port *msm_port = UART_TO_MSM(port);
205 int sent_tx;
206
207 if (port->x_char) {
ec8f29e7
SM		 208 if (msm_port->is_uartdm)
209 reset_dm_count(port);
210
211 msm_write(port, port->x_char,
212 msm_port->is_uartdm ? UARTDM_TF : UART_TF);
04896a77
RL		 213 port->icount.tx++;
214 port->x_char = 0;
215 }
216
ec8f29e7
SM		 217 if (msm_port->is_uartdm)
218 reset_dm_count(port);
219
04896a77
RL		 220 while (msm_read(port, UART_SR) & UART_SR_TX_READY) {
221 if (uart_circ_empty(xmit)) {
222 /* disable tx interrupts */
223 msm_port->imr &= ~UART_IMR_TXLEV;
224 msm_write(port, msm_port->imr, UART_IMR);
225 break;
226 }
ec8f29e7
SM		 227 msm_write(port, xmit->buf[xmit->tail],
228 msm_port->is_uartdm ? UARTDM_TF : UART_TF);
04896a77 229
ec8f29e7
SM		 230 if (msm_port->is_uartdm)
231 reset_dm_count(port);
04896a77
RL		 232
233 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
234 port->icount.tx++;
235 sent_tx = 1;
236 }
237
238 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
239 uart_write_wakeup(port);
240}
241
242static void handle_delta_cts(struct uart_port *port)
243{
244 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
245 port->icount.cts++;
bdc04e31 246 wake_up_interruptible(&port->state->port.delta_msr_wait);
04896a77
RL		 247}
248
249static irqreturn_t msm_irq(int irq, void *dev_id)
250{
251 struct uart_port *port = dev_id;
252 struct msm_port *msm_port = UART_TO_MSM(port);
253 unsigned int misr;
254
255 spin_lock(&port->lock);
256 misr = msm_read(port, UART_MISR);
257 msm_write(port, 0, UART_IMR); /* disable interrupt */
258
ec8f29e7
SM		 259 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
260 if (msm_port->is_uartdm)
261 handle_rx_dm(port, misr);
262 else
263 handle_rx(port);
264 }
04896a77
RL		 265 if (misr & UART_IMR_TXLEV)
266 handle_tx(port);
267 if (misr & UART_IMR_DELTA_CTS)
268 handle_delta_cts(port);
269
270 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
271 spin_unlock(&port->lock);
272
273 return IRQ_HANDLED;
274}
275
276static unsigned int msm_tx_empty(struct uart_port *port)
277{
278 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
279}
280
281static unsigned int msm_get_mctrl(struct uart_port *port)
282{
283 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
284}
285
ec8f29e7
SM		 286
287static void msm_reset(struct uart_port *port)
04896a77 288{
ec8f29e7
SM		 289 /* reset everything */
290 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
291 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
292 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
293 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
294 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
295 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
296}
04896a77 297
ec8f29e7
SM		 298void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
299{
300 unsigned int mr;
04896a77
RL		 301 mr = msm_read(port, UART_MR1);
302
303 if (!(mctrl & TIOCM_RTS)) {
304 mr &= ~UART_MR1_RX_RDY_CTL;
305 msm_write(port, mr, UART_MR1);
306 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
307 } else {
308 mr |= UART_MR1_RX_RDY_CTL;
309 msm_write(port, mr, UART_MR1);
310 }
311}
312
313static void msm_break_ctl(struct uart_port *port, int break_ctl)
314{
315 if (break_ctl)
316 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
317 else
318 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
319}
320
44da59e4 321static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
04896a77
RL		 322{
323 unsigned int baud_code, rxstale, watermark;
ec8f29e7 324 struct msm_port *msm_port = UART_TO_MSM(port);
04896a77
RL		 325
326 switch (baud) {
327 case 300:
328 baud_code = UART_CSR_300;
329 rxstale = 1;
330 break;
331 case 600:
332 baud_code = UART_CSR_600;
333 rxstale = 1;
334 break;
335 case 1200:
336 baud_code = UART_CSR_1200;
337 rxstale = 1;
338 break;
339 case 2400:
340 baud_code = UART_CSR_2400;
341 rxstale = 1;
342 break;
343 case 4800:
344 baud_code = UART_CSR_4800;
345 rxstale = 1;
346 break;
347 case 9600:
348 baud_code = UART_CSR_9600;
349 rxstale = 2;
350 break;
351 case 14400:
352 baud_code = UART_CSR_14400;
353 rxstale = 3;
354 break;
355 case 19200:
356 baud_code = UART_CSR_19200;
357 rxstale = 4;
358 break;
359 case 28800:
360 baud_code = UART_CSR_28800;
361 rxstale = 6;
362 break;
363 case 38400:
364 baud_code = UART_CSR_38400;
365 rxstale = 8;
366 break;
367 case 57600:
368 baud_code = UART_CSR_57600;
369 rxstale = 16;
370 break;
371 case 115200:
372 default:
373 baud_code = UART_CSR_115200;
44da59e4 374 baud = 115200;
04896a77
RL		 375 rxstale = 31;
376 break;
377 }
378
ec8f29e7
SM		 379 if (msm_port->is_uartdm)
380 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
381
04896a77
RL		 382 msm_write(port, baud_code, UART_CSR);
383
384 /* RX stale watermark */
385 watermark = UART_IPR_STALE_LSB & rxstale;
386 watermark |= UART_IPR_RXSTALE_LAST;
387 watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
388 msm_write(port, watermark, UART_IPR);
389
390 /* set RX watermark */
391 watermark = (port->fifosize * 3) / 4;
392 msm_write(port, watermark, UART_RFWR);
393
394 /* set TX watermark */
395 msm_write(port, 10, UART_TFWR);
44da59e4 396
ec8f29e7
SM		 397 if (msm_port->is_uartdm) {
398 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
399 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
400 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
401 }
402
44da59e4 403 return baud;
04896a77
RL		 404}
405
04896a77
RL		 406
407static void msm_init_clock(struct uart_port *port)
408{
409 struct msm_port *msm_port = UART_TO_MSM(port);
410
f98cf83d 411 clk_prepare_enable(msm_port->clk);
ec8f29e7 412 if (!IS_ERR(msm_port->pclk))
f98cf83d 413 clk_prepare_enable(msm_port->pclk);
18c79d76 414 msm_serial_set_mnd_regs(port);
04896a77
RL		 415}
416
417static int msm_startup(struct uart_port *port)
418{
419 struct msm_port *msm_port = UART_TO_MSM(port);
420 unsigned int data, rfr_level;
421 int ret;
422
423 snprintf(msm_port->name, sizeof(msm_port->name),
424 "msm_serial%d", port->line);
425
426 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
427 msm_port->name, port);
428 if (unlikely(ret))
429 return ret;
430
431 msm_init_clock(port);
432
433 if (likely(port->fifosize > 12))
434 rfr_level = port->fifosize - 12;
435 else
436 rfr_level = port->fifosize;
437
438 /* set automatic RFR level */
439 data = msm_read(port, UART_MR1);
440 data &= ~UART_MR1_AUTO_RFR_LEVEL1;
441 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
442 data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
443 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
444 msm_write(port, data, UART_MR1);
445
446 /* make sure that RXSTALE count is non-zero */
447 data = msm_read(port, UART_IPR);
448 if (unlikely(!data)) {
449 data |= UART_IPR_RXSTALE_LAST;
450 data |= UART_IPR_STALE_LSB;
451 msm_write(port, data, UART_IPR);
452 }
453
ec8f29e7
SM		 454 data = 0;
455 if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) {
456 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
457 msm_reset(port);
458 data = UART_CR_TX_ENABLE;
459 }
460
461 data |= UART_CR_RX_ENABLE;
462 msm_write(port, data, UART_CR); /* enable TX & RX */
04896a77 463
ec8f29e7
SM		 464 /* Make sure IPR is not 0 to start with*/
465 if (msm_port->is_uartdm)
466 msm_write(port, UART_IPR_STALE_LSB, UART_IPR);
04896a77
RL		 467
468 /* turn on RX and CTS interrupts */
469 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
470 UART_IMR_CURRENT_CTS;
04896a77 471
ec8f29e7
SM		 472 if (msm_port->is_uartdm) {
473 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
474 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
475 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
476 }
477
478 msm_write(port, msm_port->imr, UART_IMR);
04896a77
RL		 479 return 0;
480}
481
482static void msm_shutdown(struct uart_port *port)
483{
484 struct msm_port *msm_port = UART_TO_MSM(port);
485
486 msm_port->imr = 0;
487 msm_write(port, 0, UART_IMR); /* disable interrupts */
488
f98cf83d 489 clk_disable_unprepare(msm_port->clk);
04896a77
RL		 490
491 free_irq(port->irq, port);
492}
493
494static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
495 struct ktermios *old)
496{
497 unsigned long flags;
498 unsigned int baud, mr;
499
500 spin_lock_irqsave(&port->lock, flags);
501
502 /* calculate and set baud rate */
503 baud = uart_get_baud_rate(port, termios, old, 300, 115200);
44da59e4
AC		 504 baud = msm_set_baud_rate(port, baud);
505 if (tty_termios_baud_rate(termios))
506 tty_termios_encode_baud_rate(termios, baud, baud);
ec8f29e7 507
04896a77
RL		 508 /* calculate parity */
509 mr = msm_read(port, UART_MR2);
510 mr &= ~UART_MR2_PARITY_MODE;
511 if (termios->c_cflag & PARENB) {
512 if (termios->c_cflag & PARODD)
513 mr |= UART_MR2_PARITY_MODE_ODD;
514 else if (termios->c_cflag & CMSPAR)
515 mr |= UART_MR2_PARITY_MODE_SPACE;
516 else
517 mr |= UART_MR2_PARITY_MODE_EVEN;
518 }
519
520 /* calculate bits per char */
521 mr &= ~UART_MR2_BITS_PER_CHAR;
522 switch (termios->c_cflag & CSIZE) {
523 case CS5:
524 mr |= UART_MR2_BITS_PER_CHAR_5;
525 break;
526 case CS6:
527 mr |= UART_MR2_BITS_PER_CHAR_6;
528 break;
529 case CS7:
530 mr |= UART_MR2_BITS_PER_CHAR_7;
531 break;
532 case CS8:
533 default:
534 mr |= UART_MR2_BITS_PER_CHAR_8;
535 break;
536 }
537
538 /* calculate stop bits */
539 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
540 if (termios->c_cflag & CSTOPB)
541 mr |= UART_MR2_STOP_BIT_LEN_TWO;
542 else
543 mr |= UART_MR2_STOP_BIT_LEN_ONE;
544
545 /* set parity, bits per char, and stop bit */
546 msm_write(port, mr, UART_MR2);
547
548 /* calculate and set hardware flow control */
549 mr = msm_read(port, UART_MR1);
550 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
551 if (termios->c_cflag & CRTSCTS) {
552 mr |= UART_MR1_CTS_CTL;
553 mr |= UART_MR1_RX_RDY_CTL;
554 }
555 msm_write(port, mr, UART_MR1);
556
557 /* Configure status bits to ignore based on termio flags. */
558 port->read_status_mask = 0;
559 if (termios->c_iflag & INPCK)
560 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
561 if (termios->c_iflag & (BRKINT | PARMRK))
562 port->read_status_mask |= UART_SR_RX_BREAK;
563
564 uart_update_timeout(port, termios->c_cflag, baud);
565
566 spin_unlock_irqrestore(&port->lock, flags);
567}
568
569static const char *msm_type(struct uart_port *port)
570{
571 return "MSM";
572}
573
574static void msm_release_port(struct uart_port *port)
575{
576 struct platform_device *pdev = to_platform_device(port->dev);
ec8f29e7
SM		 577 struct msm_port *msm_port = UART_TO_MSM(port);
578 struct resource *uart_resource;
579 struct resource *gsbi_resource;
04896a77
RL		 580 resource_size_t size;
581
ec8f29e7
SM		 582 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
583 if (unlikely(!uart_resource))
04896a77 584 return;
ec8f29e7 585 size = resource_size(uart_resource);
04896a77
RL		 586
587 release_mem_region(port->mapbase, size);
588 iounmap(port->membase);
589 port->membase = NULL;
ec8f29e7
SM		 590
591 if (msm_port->gsbi_base) {
592 iowrite32(GSBI_PROTOCOL_IDLE, msm_port->gsbi_base +
593 GSBI_CONTROL);
594
886a451b
DB		 595 gsbi_resource = platform_get_resource(pdev,
596 IORESOURCE_MEM, 1);
ec8f29e7
SM		 597
598 if (unlikely(!gsbi_resource))
599 return;
600
601 size = resource_size(gsbi_resource);
602 release_mem_region(gsbi_resource->start, size);
603 iounmap(msm_port->gsbi_base);
604 msm_port->gsbi_base = NULL;
605 }
04896a77
RL		 606}
607
608static int msm_request_port(struct uart_port *port)
609{
ec8f29e7 610 struct msm_port *msm_port = UART_TO_MSM(port);
04896a77 611 struct platform_device *pdev = to_platform_device(port->dev);
ec8f29e7
SM		 612 struct resource *uart_resource;
613 struct resource *gsbi_resource;
04896a77 614 resource_size_t size;
ec8f29e7 615 int ret;
04896a77 616
886a451b 617 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ec8f29e7 618 if (unlikely(!uart_resource))
04896a77 619 return -ENXIO;
04896a77 620
ec8f29e7
SM		 621 size = resource_size(uart_resource);
622
623 if (!request_mem_region(port->mapbase, size, "msm_serial"))
04896a77
RL		 624 return -EBUSY;
625
626 port->membase = ioremap(port->mapbase, size);
627 if (!port->membase) {
ec8f29e7
SM		 628 ret = -EBUSY;
629 goto fail_release_port;
630 }
631
886a451b 632 gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
ec8f29e7
SM		 633 /* Is this a GSBI-based port? */
634 if (gsbi_resource) {
635 size = resource_size(gsbi_resource);
636
637 if (!request_mem_region(gsbi_resource->start, size,
638 "msm_serial")) {
639 ret = -EBUSY;
195be84a 640 goto fail_release_port_membase;
ec8f29e7
SM		 641 }
642
643 msm_port->gsbi_base = ioremap(gsbi_resource->start, size);
644 if (!msm_port->gsbi_base) {
645 ret = -EBUSY;
646 goto fail_release_gsbi;
647 }
04896a77
RL		 648 }
649
650 return 0;
ec8f29e7
SM		 651
652fail_release_gsbi:
653 release_mem_region(gsbi_resource->start, size);
195be84a
WY		 654fail_release_port_membase:
655 iounmap(port->membase);
ec8f29e7
SM		 656fail_release_port:
657 release_mem_region(port->mapbase, size);
658 return ret;
04896a77
RL		 659}
660
661static void msm_config_port(struct uart_port *port, int flags)
662{
ec8f29e7
SM		 663 struct msm_port *msm_port = UART_TO_MSM(port);
664 int ret;
04896a77
RL		 665 if (flags & UART_CONFIG_TYPE) {
666 port->type = PORT_MSM;
ec8f29e7
SM		 667 ret = msm_request_port(port);
668 if (ret)
669 return;
04896a77 670 }
ec8f29e7
SM		 671
672 if (msm_port->is_uartdm)
673 iowrite32(GSBI_PROTOCOL_UART, msm_port->gsbi_base +
674 GSBI_CONTROL);
04896a77
RL		 675}
676
677static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
678{
679 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
680 return -EINVAL;
681 if (unlikely(port->irq != ser->irq))
682 return -EINVAL;
683 return 0;
684}
685
686static void msm_power(struct uart_port *port, unsigned int state,
687 unsigned int oldstate)
688{
689 struct msm_port *msm_port = UART_TO_MSM(port);
690
691 switch (state) {
692 case 0:
f98cf83d 693 clk_prepare_enable(msm_port->clk);
ec8f29e7 694 if (!IS_ERR(msm_port->pclk))
f98cf83d 695 clk_prepare_enable(msm_port->pclk);
04896a77
RL		 696 break;
697 case 3:
f98cf83d 698 clk_disable_unprepare(msm_port->clk);
ec8f29e7 699 if (!IS_ERR(msm_port->pclk))
f98cf83d 700 clk_disable_unprepare(msm_port->pclk);
04896a77
RL		 701 break;
702 default:
703 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
704 }
705}
706
707static struct uart_ops msm_uart_pops = {
708 .tx_empty = msm_tx_empty,
709 .set_mctrl = msm_set_mctrl,
710 .get_mctrl = msm_get_mctrl,
711 .stop_tx = msm_stop_tx,
712 .start_tx = msm_start_tx,
713 .stop_rx = msm_stop_rx,
714 .enable_ms = msm_enable_ms,
715 .break_ctl = msm_break_ctl,
716 .startup = msm_startup,
717 .shutdown = msm_shutdown,
718 .set_termios = msm_set_termios,
719 .type = msm_type,
720 .release_port = msm_release_port,
721 .request_port = msm_request_port,
722 .config_port = msm_config_port,
723 .verify_port = msm_verify_port,
724 .pm = msm_power,
725};
726
727static struct msm_port msm_uart_ports[] = {
728 {
729 .uart = {
730 .iotype = UPIO_MEM,
731 .ops = &msm_uart_pops,
732 .flags = UPF_BOOT_AUTOCONF,
ec8f29e7 733 .fifosize = 64,
04896a77
RL		 734 .line = 0,
735 },
736 },
737 {
738 .uart = {
739 .iotype = UPIO_MEM,
740 .ops = &msm_uart_pops,
741 .flags = UPF_BOOT_AUTOCONF,
ec8f29e7 742 .fifosize = 64,
04896a77
RL		 743 .line = 1,
744 },
745 },
746 {
747 .uart = {
748 .iotype = UPIO_MEM,
749 .ops = &msm_uart_pops,
750 .flags = UPF_BOOT_AUTOCONF,
751 .fifosize = 64,
752 .line = 2,
753 },
754 },
755};
756
757#define UART_NR ARRAY_SIZE(msm_uart_ports)
758
759static inline struct uart_port *get_port_from_line(unsigned int line)
760{
761 return &msm_uart_ports[line].uart;
762}
763
764#ifdef CONFIG_SERIAL_MSM_CONSOLE
765
766static void msm_console_putchar(struct uart_port *port, int c)
767{
ec8f29e7
SM		 768 struct msm_port *msm_port = UART_TO_MSM(port);
769
770 if (msm_port->is_uartdm)
771 reset_dm_count(port);
772
04896a77
RL		 773 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
774 ;
ec8f29e7 775 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
04896a77
RL		 776}
777
778static void msm_console_write(struct console *co, const char *s,
779 unsigned int count)
780{
781 struct uart_port *port;
782 struct msm_port *msm_port;
783
784 BUG_ON(co->index < 0 || co->index >= UART_NR);
785
786 port = get_port_from_line(co->index);
787 msm_port = UART_TO_MSM(port);
788
789 spin_lock(&port->lock);
790 uart_console_write(port, s, count, msm_console_putchar);
791 spin_unlock(&port->lock);
792}
793
794static int __init msm_console_setup(struct console *co, char *options)
795{
796 struct uart_port *port;
ec8f29e7 797 struct msm_port *msm_port;
04896a77
RL		 798 int baud, flow, bits, parity;
799
800 if (unlikely(co->index >= UART_NR || co->index < 0))
801 return -ENXIO;
802
803 port = get_port_from_line(co->index);
ec8f29e7 804 msm_port = UART_TO_MSM(port);
04896a77
RL		 805
806 if (unlikely(!port->membase))
807 return -ENXIO;
808
04896a77
RL		 809 msm_init_clock(port);
810
811 if (options)
812 uart_parse_options(options, &baud, &parity, &bits, &flow);
813
814 bits = 8;
815 parity = 'n';
816 flow = 'n';
817 msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
818 UART_MR2); /* 8N1 */
819
820 if (baud < 300 || baud > 115200)
821 baud = 115200;
822 msm_set_baud_rate(port, baud);
823
824 msm_reset(port);
825
ec8f29e7
SM		 826 if (msm_port->is_uartdm) {
827 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
828 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
829 }
830
04896a77
RL		 831 printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
832
833 return uart_set_options(port, co, baud, parity, bits, flow);
834}
835
836static struct uart_driver msm_uart_driver;
837
838static struct console msm_console = {
839 .name = "ttyMSM",
840 .write = msm_console_write,
841 .device = uart_console_device,
842 .setup = msm_console_setup,
843 .flags = CON_PRINTBUFFER,
844 .index = -1,
845 .data = &msm_uart_driver,
846};
847
848#define MSM_CONSOLE (&msm_console)
849
850#else
851#define MSM_CONSOLE NULL
852#endif
853
854static struct uart_driver msm_uart_driver = {
855 .owner = THIS_MODULE,
856 .driver_name = "msm_serial",
857 .dev_name = "ttyMSM",
858 .nr = UART_NR,
859 .cons = MSM_CONSOLE,
860};
861
cfdad2ab
DB		 862static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
863
04896a77
RL		 864static int __init msm_serial_probe(struct platform_device *pdev)
865{
866 struct msm_port *msm_port;
867 struct resource *resource;
868 struct uart_port *port;
1e091751 869 int irq;
04896a77 870
cfdad2ab
DB		 871 if (pdev->id == -1)
872 pdev->id = atomic_inc_return(&msm_uart_next_id) - 1;
873
04896a77
RL		 874 if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
875 return -ENXIO;
876
877 printk(KERN_INFO "msm_serial: detected port #%d\n", pdev->id);
878
879 port = get_port_from_line(pdev->id);
880 port->dev = &pdev->dev;
881 msm_port = UART_TO_MSM(port);
882
886a451b 883 if (platform_get_resource(pdev, IORESOURCE_MEM, 1))
ec8f29e7
SM		 884 msm_port->is_uartdm = 1;
885 else
886 msm_port->is_uartdm = 0;
887
888 if (msm_port->is_uartdm) {
519b371d
SB		 889 msm_port->clk = devm_clk_get(&pdev->dev, "gsbi_uart_clk");
890 msm_port->pclk = devm_clk_get(&pdev->dev, "gsbi_pclk");
ec8f29e7 891 } else {
519b371d 892 msm_port->clk = devm_clk_get(&pdev->dev, "uart_clk");
ec8f29e7
SM		 893 msm_port->pclk = ERR_PTR(-ENOENT);
894 }
895
519b371d
SB		 896 if (IS_ERR(msm_port->clk))
897 return PTR_ERR(msm_port->clk);
898
899 if (msm_port->is_uartdm) {
900 if (IS_ERR(msm_port->pclk))
901 return PTR_ERR(msm_port->pclk);
ec8f29e7 902
7b6031a7 903 clk_set_rate(msm_port->clk, 1843200);
519b371d 904 }
ec8f29e7 905
04896a77 906 port->uartclk = clk_get_rate(msm_port->clk);
18c79d76
AD		 907 printk(KERN_INFO "uartclk = %d\n", port->uartclk);
908
04896a77 909
886a451b 910 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
04896a77
RL		 911 if (unlikely(!resource))
912 return -ENXIO;
913 port->mapbase = resource->start;
914
1e091751
RK		 915 irq = platform_get_irq(pdev, 0);
916 if (unlikely(irq < 0))
04896a77 917 return -ENXIO;
1e091751 918 port->irq = irq;
04896a77
RL		 919
920 platform_set_drvdata(pdev, port);
921
922 return uart_add_one_port(&msm_uart_driver, port);
923}
924
ae8d8a14 925static int msm_serial_remove(struct platform_device *pdev)
04896a77 926{
519b371d 927 struct uart_port *port = platform_get_drvdata(pdev);
04896a77 928
519b371d 929 uart_remove_one_port(&msm_uart_driver, port);
04896a77
RL		 930
931 return 0;
932}
933
cfdad2ab
DB		 934static struct of_device_id msm_match_table[] = {
935 { .compatible = "qcom,msm-uart" },
936 {}
937};
938
04896a77 939static struct platform_driver msm_platform_driver = {
04896a77
RL		 940 .remove = msm_serial_remove,
941 .driver = {
942 .name = "msm_serial",
943 .owner = THIS_MODULE,
cfdad2ab 944 .of_match_table = msm_match_table,
04896a77
RL		 945 },
946};
947
948static int __init msm_serial_init(void)
949{
950 int ret;
951
952 ret = uart_register_driver(&msm_uart_driver);
953 if (unlikely(ret))
954 return ret;
955
956 ret = platform_driver_probe(&msm_platform_driver, msm_serial_probe);
957 if (unlikely(ret))
958 uart_unregister_driver(&msm_uart_driver);
959
960 printk(KERN_INFO "msm_serial: driver initialized\n");
961
962 return ret;
963}
964
965static void __exit msm_serial_exit(void)
966{
967#ifdef CONFIG_SERIAL_MSM_CONSOLE
968 unregister_console(&msm_console);
969#endif
970 platform_driver_unregister(&msm_platform_driver);
971 uart_unregister_driver(&msm_uart_driver);
972}
973
974module_init(msm_serial_init);
975module_exit(msm_serial_exit);
976
977MODULE_AUTHOR("Robert Love <rlove@google.com>");
978MODULE_DESCRIPTION("Driver for msm7x serial device");
979MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.392803 seconds and 5 git commands to generate.