[deliverable/linux.git] / drivers / tty / serial / of_serial.c

/*
 *  Serial Port driver for Open Firmware platform devices
 *
 *    Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp.
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 *
 */
#include <linux/console.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/nwpserial.h>
#include <linux/clk.h>

#ifdef CONFIG_SERIAL_8250_MODULE
#define CONFIG_SERIAL_8250 CONFIG_SERIAL_8250_MODULE
#endif

#include "8250/8250.h"

struct of_serial_info {
	struct clk *clk;
	int type;
	int line;
};

#ifdef CONFIG_ARCH_TEGRA
void tegra_serial_handle_break(struct uart_port *p)
{
	unsigned int status, tmout = 10000;

	do {
		status = p->serial_in(p, UART_LSR);
		if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
			status = p->serial_in(p, UART_RX);
		else
			break;
		if (--tmout == 0)
			break;
		udelay(1);
	} while (1);
}
#else
static inline void tegra_serial_handle_break(struct uart_port *port)
{
}
#endif

/*
 * Fill a struct uart_port for a given device node
 */
static int of_platform_serial_setup(struct platform_device *ofdev,
			int type, struct uart_port *port,
			struct of_serial_info *info)
{
	struct resource resource;
	struct device_node *np = ofdev->dev.of_node;
	u32 clk, spd, prop;
	int ret;

	memset(port, 0, sizeof *port);
	if (of_property_read_u32(np, "clock-frequency", &clk)) {

		/* Get clk rate through clk driver if present */
		info->clk = devm_clk_get(&ofdev->dev, NULL);
		if (IS_ERR(info->clk)) {
			dev_warn(&ofdev->dev,
				"clk or clock-frequency not defined\n");
			return PTR_ERR(info->clk);
		}

		ret = clk_prepare_enable(info->clk);
		if (ret < 0)
			return ret;

		clk = clk_get_rate(info->clk);
	}
	/* If current-speed was set, then try not to change it. */
	if (of_property_read_u32(np, "current-speed", &spd) == 0)
		port->custom_divisor = clk / (16 * spd);

	ret = of_address_to_resource(np, 0, &resource);
	if (ret) {
		dev_warn(&ofdev->dev, "invalid address\n");
		goto out;
	}

	spin_lock_init(&port->lock);
	port->mapbase = resource.start;
	port->mapsize = resource_size(&resource);

	/* Check for shifted address mapping */
	if (of_property_read_u32(np, "reg-offset", &prop) == 0)
		port->mapbase += prop;

	/* Check for registers offset within the devices address range */
	if (of_property_read_u32(np, "reg-shift", &prop) == 0)
		port->regshift = prop;

	/* Check for fifo size */
	if (of_property_read_u32(np, "fifo-size", &prop) == 0)
		port->fifosize = prop;

	/* Check for a fixed line number */
	ret = of_alias_get_id(np, "serial");
	if (ret >= 0)
		port->line = ret;

	port->irq = irq_of_parse_and_map(np, 0);
	port->iotype = UPIO_MEM;
	if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
		switch (prop) {
		case 1:
			port->iotype = UPIO_MEM;
			break;
		case 4:
			port->iotype = of_device_is_big_endian(np) ?
				       UPIO_MEM32BE : UPIO_MEM32;
			break;
		default:
			dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n",
				 prop);
			ret = -EINVAL;
			goto out;
		}
	}

	port->type = type;
	port->uartclk = clk;
	port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP
		| UPF_FIXED_PORT | UPF_FIXED_TYPE;

	if (of_find_property(np, "no-loopback-test", NULL))
		port->flags |= UPF_SKIP_TEST;

	port->dev = &ofdev->dev;

	switch (type) {
	case PORT_TEGRA:
		port->handle_break = tegra_serial_handle_break;
		break;

	case PORT_RT2880:
		port->iotype = UPIO_AU;
		break;
	}

	if (IS_ENABLED(CONFIG_SERIAL_8250_FSL) &&
	    (of_device_is_compatible(np, "fsl,ns16550") ||
	     of_device_is_compatible(np, "fsl,16550-FIFO64")))
		port->handle_irq = fsl8250_handle_irq;

	return 0;
out:
	if (info->clk)
		clk_disable_unprepare(info->clk);
	return ret;
}

/*
 * Try to register a serial port
 */
static const struct of_device_id of_platform_serial_table[];
static int of_platform_serial_probe(struct platform_device *ofdev)
{
	const struct of_device_id *match;
	struct of_serial_info *info;
	struct uart_port port;
	int port_type;
	int ret;

	match = of_match_device(of_platform_serial_table, &ofdev->dev);
	if (!match)
		return -EINVAL;

	if (of_find_property(ofdev->dev.of_node, "used-by-rtas", NULL))
		return -EBUSY;

	info = kzalloc(sizeof(*info), GFP_KERNEL);
	if (info == NULL)
		return -ENOMEM;

	port_type = (unsigned long)match->data;
	ret = of_platform_serial_setup(ofdev, port_type, &port, info);
	if (ret)
		goto out;

	switch (port_type) {
#ifdef CONFIG_SERIAL_8250
	case PORT_8250 ... PORT_MAX_8250:
	{
		struct uart_8250_port port8250;
		memset(&port8250, 0, sizeof(port8250));
		port8250.port = port;

		if (port.fifosize)
			port8250.capabilities = UART_CAP_FIFO;

		if (of_property_read_bool(ofdev->dev.of_node,
					  "auto-flow-control"))
			port8250.capabilities |= UART_CAP_AFE;

		ret = serial8250_register_8250_port(&port8250);
		break;
	}
#endif
#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
	case PORT_NWPSERIAL:
		ret = nwpserial_register_port(&port);
		break;
#endif
	default:
		/* need to add code for these */
	case PORT_UNKNOWN:
		dev_info(&ofdev->dev, "Unknown serial port found, ignored\n");
		ret = -ENODEV;
		break;
	}
	if (ret < 0)
		goto out;

	info->type = port_type;
	info->line = ret;
	platform_set_drvdata(ofdev, info);
	return 0;
out:
	kfree(info);
	irq_dispose_mapping(port.irq);
	return ret;
}

/*
 * Release a line
 */
static int of_platform_serial_remove(struct platform_device *ofdev)
{
	struct of_serial_info *info = platform_get_drvdata(ofdev);
	switch (info->type) {
#ifdef CONFIG_SERIAL_8250
	case PORT_8250 ... PORT_MAX_8250:
		serial8250_unregister_port(info->line);
		break;
#endif
#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
	case PORT_NWPSERIAL:
		nwpserial_unregister_port(info->line);
		break;
#endif
	default:
		/* need to add code for these */
		break;
	}

	if (info->clk)
		clk_disable_unprepare(info->clk);
	kfree(info);
	return 0;
}

#ifdef CONFIG_PM_SLEEP
#ifdef CONFIG_SERIAL_8250
static void of_serial_suspend_8250(struct of_serial_info *info)
{
	struct uart_8250_port *port8250 = serial8250_get_port(info->line);
	struct uart_port *port = &port8250->port;

	serial8250_suspend_port(info->line);
	if (info->clk && (!uart_console(port) || console_suspend_enabled))
		clk_disable_unprepare(info->clk);
}

static void of_serial_resume_8250(struct of_serial_info *info)
{
	struct uart_8250_port *port8250 = serial8250_get_port(info->line);
	struct uart_port *port = &port8250->port;

	if (info->clk && (!uart_console(port) || console_suspend_enabled))
		clk_prepare_enable(info->clk);

	serial8250_resume_port(info->line);
}
#else
static inline void of_serial_suspend_8250(struct of_serial_info *info)
{
}

static inline void of_serial_resume_8250(struct of_serial_info *info)
{
}
#endif

static int of_serial_suspend(struct device *dev)
{
	struct of_serial_info *info = dev_get_drvdata(dev);

	switch (info->type) {
	case PORT_8250 ... PORT_MAX_8250:
		of_serial_suspend_8250(info);
		break;
	default:
		break;
	}

	return 0;
}

static int of_serial_resume(struct device *dev)
{
	struct of_serial_info *info = dev_get_drvdata(dev);

	switch (info->type) {
	case PORT_8250 ... PORT_MAX_8250:
		of_serial_resume_8250(info);
		break;
	default:
		break;
	}

	return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(of_serial_pm_ops, of_serial_suspend, of_serial_resume);

/*
 * A few common types, add more as needed.
 */
static const struct of_device_id of_platform_serial_table[] = {
	{ .compatible = "ns8250",   .data = (void *)PORT_8250, },
	{ .compatible = "ns16450",  .data = (void *)PORT_16450, },
	{ .compatible = "ns16550a", .data = (void *)PORT_16550A, },
	{ .compatible = "ns16550",  .data = (void *)PORT_16550, },
	{ .compatible = "ns16750",  .data = (void *)PORT_16750, },
	{ .compatible = "ns16850",  .data = (void *)PORT_16850, },
	{ .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },
	{ .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
	{ .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, },
	{ .compatible = "altr,16550-FIFO32",
		.data = (void *)PORT_ALTR_16550_F32, },
	{ .compatible = "altr,16550-FIFO64",
		.data = (void *)PORT_ALTR_16550_F64, },
	{ .compatible = "altr,16550-FIFO128",
		.data = (void *)PORT_ALTR_16550_F128, },
	{ .compatible = "mrvl,mmp-uart",
		.data = (void *)PORT_XSCALE, },
	{ .compatible = "mrvl,pxa-uart",
		.data = (void *)PORT_XSCALE, },
#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
	{ .compatible = "ibm,qpace-nwp-serial",
		.data = (void *)PORT_NWPSERIAL, },
#endif
	{ /* end of list */ },
};
MODULE_DEVICE_TABLE(of, of_platform_serial_table);

static struct platform_driver of_platform_serial_driver = {
	.driver = {
		.name = "of_serial",
		.of_match_table = of_platform_serial_table,
	},
	.probe = of_platform_serial_probe,
	.remove = of_platform_serial_remove,
};

module_platform_driver(of_platform_serial_driver);

MODULE_AUTHOR("Arnd Bergmann <arnd@arndb.de>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices");
Commit	Line	Data
8d38a5b2 AB	1	/*
	2	* Serial Port driver for Open Firmware platform devices
	3	*
	4	* Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*
	11	*/
8ad3b135	12	#include <linux/console.h>
8d38a5b2	13	#include <linux/module.h>
5a0e3ad6	14	#include <linux/slab.h>
bf03f65b	15	#include <linux/delay.h>
8d38a5b2	16	#include <linux/serial_core.h>
bf03f65b	17	#include <linux/serial_reg.h>
f1ca09b2	18	#include <linux/of_address.h>
73930a85	19	#include <linux/of_irq.h>
c401b044	20	#include <linux/of_platform.h>
5886188d	21	#include <linux/nwpserial.h>
0bbeb3c3	22	#include <linux/clk.h>
8d38a5b2	23
ed4492fa MS	24	#ifdef CONFIG_SERIAL_8250_MODULE
	25	#define CONFIG_SERIAL_8250 CONFIG_SERIAL_8250_MODULE
	26	#endif
	27
b0b8c84c HK	28	#include "8250/8250.h"
b0b8c84c HK	29
e34b9c94	30	struct of_serial_info {
0bbeb3c3	31	struct clk *clk;
e34b9c94 IK	32	int type;
	33	int line;
	34	};
	35
bf03f65b DW	36	#ifdef CONFIG_ARCH_TEGRA
	37	void tegra_serial_handle_break(struct uart_port *p)
	38	{
	39	unsigned int status, tmout = 10000;
	40
	41	do {
	42	status = p->serial_in(p, UART_LSR);
	43	if (status & (UART_LSR_FIFOE \| UART_LSR_BRK_ERROR_BITS))
	44	status = p->serial_in(p, UART_RX);
	45	else
	46	break;
	47	if (--tmout == 0)
	48	break;
	49	udelay(1);
	50	} while (1);
	51	}
f26402e8 SW	52	#else
	53	static inline void tegra_serial_handle_break(struct uart_port *port)
	54	{
	55	}
bf03f65b DW	56	#endif
bf03f65b DW	57
8d38a5b2 AB	58	/*
	59	* Fill a struct uart_port for a given device node
	60	*/
9671f099	61	static int of_platform_serial_setup(struct platform_device *ofdev,
0bbeb3c3 MK	62	int type, struct uart_port *port,
0bbeb3c3 MK	63	struct of_serial_info *info)
8d38a5b2 AB	64	{
8d38a5b2 AB	65	struct resource resource;
61c7a080	66	struct device_node *np = ofdev->dev.of_node;
b84e7731 GL	67	u32 clk, spd, prop;
b84e7731 GL	68	int ret;
8d38a5b2 AB	69
8d38a5b2 AB	70	memset(port, 0, sizeof *port);
b84e7731	71	if (of_property_read_u32(np, "clock-frequency", &clk)) {
0bbeb3c3 MK	72
0bbeb3c3 MK	73	/* Get clk rate through clk driver if present */
3a63d224	74	info->clk = devm_clk_get(&ofdev->dev, NULL);
76cc4386	75	if (IS_ERR(info->clk)) {
0bbeb3c3 MK	76	dev_warn(&ofdev->dev,
0bbeb3c3 MK	77	"clk or clock-frequency not defined\n");
76cc4386	78	return PTR_ERR(info->clk);
0bbeb3c3 MK	79	}
0bbeb3c3 MK	80
6f0c3091 MY	81	ret = clk_prepare_enable(info->clk);
	82	if (ret < 0)
	83	return ret;
	84
0bbeb3c3	85	clk = clk_get_rate(info->clk);
8d38a5b2	86	}
b84e7731 GL	87	/* If current-speed was set, then try not to change it. */
	88	if (of_property_read_u32(np, "current-speed", &spd) == 0)
	89	port->custom_divisor = clk / (16 * spd);
8d38a5b2 AB	90
	91	ret = of_address_to_resource(np, 0, &resource);
	92	if (ret) {
	93	dev_warn(&ofdev->dev, "invalid address\n");
0bbeb3c3	94	goto out;
8d38a5b2 AB	95	}
	96
	97	spin_lock_init(&port->lock);
	98	port->mapbase = resource.start;
07876912	99	port->mapsize = resource_size(&resource);
b912b5e2 JL	100
b912b5e2 JL	101	/* Check for shifted address mapping */
b84e7731 GL	102	if (of_property_read_u32(np, "reg-offset", &prop) == 0)
b84e7731 GL	103	port->mapbase += prop;
b912b5e2 JL	104
b912b5e2 JL	105	/* Check for registers offset within the devices address range */
b84e7731 GL	106	if (of_property_read_u32(np, "reg-shift", &prop) == 0)
b84e7731 GL	107	port->regshift = prop;
b912b5e2	108
9f1ca068 HK	109	/* Check for fifo size */
	110	if (of_property_read_u32(np, "fifo-size", &prop) == 0)
	111	port->fifosize = prop;
	112
3239fd31 LS	113	/* Check for a fixed line number */
	114	ret = of_alias_get_id(np, "serial");
	115	if (ret >= 0)
	116	port->line = ret;
	117
8d38a5b2 AB	118	port->irq = irq_of_parse_and_map(np, 0);
8d38a5b2 AB	119	port->iotype = UPIO_MEM;
b84e7731 GL	120	if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
b84e7731 GL	121	switch (prop) {
7423734e JI	122	case 1:
	123	port->iotype = UPIO_MEM;
	124	break;
	125	case 4:
ebc5e200 KC	126	port->iotype = of_device_is_big_endian(np) ?
ebc5e200 KC	127	UPIO_MEM32BE : UPIO_MEM32;
7423734e JI	128	break;
7423734e JI	129	default:
b84e7731 GL	130	dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n",
b84e7731 GL	131	prop);
0bbeb3c3 MK	132	ret = -EINVAL;
0bbeb3c3 MK	133	goto out;
7423734e JI	134	}
	135	}
	136
8d38a5b2	137	port->type = type;
b84e7731	138	port->uartclk = clk;
abb4a239	139	port->flags = UPF_SHARE_IRQ \| UPF_BOOT_AUTOCONF \| UPF_IOREMAP
eedacbf0	140	\| UPF_FIXED_PORT \| UPF_FIXED_TYPE;
fde8be29 GJ	141
	142	if (of_find_property(np, "no-loopback-test", NULL))
	143	port->flags \|= UPF_SKIP_TEST;
	144
8d38a5b2	145	port->dev = &ofdev->dev;
8d38a5b2	146
9b8777e3 JC	147	switch (type) {
9b8777e3 JC	148	case PORT_TEGRA:
bf03f65b	149	port->handle_break = tegra_serial_handle_break;
9b8777e3 JC	150	break;
	151
	152	case PORT_RT2880:
	153	port->iotype = UPIO_AU;
	154	break;
	155	}
bf03f65b	156
d43b54d2 SW	157	if (IS_ENABLED(CONFIG_SERIAL_8250_FSL) &&
	158	(of_device_is_compatible(np, "fsl,ns16550") \|\|
	159	of_device_is_compatible(np, "fsl,16550-FIFO64")))
	160	port->handle_irq = fsl8250_handle_irq;
	161
8d38a5b2	162	return 0;
0bbeb3c3 MK	163	out:
	164	if (info->clk)
	165	clk_disable_unprepare(info->clk);
	166	return ret;
8d38a5b2 AB	167	}
	168
	169	/*
	170	* Try to register a serial port
	171	*/
ed0bb232	172	static const struct of_device_id of_platform_serial_table[];
9671f099	173	static int of_platform_serial_probe(struct platform_device *ofdev)
8d38a5b2	174	{
b1608d69	175	const struct of_device_id *match;
e34b9c94	176	struct of_serial_info *info;
8d38a5b2 AB	177	struct uart_port port;
	178	int port_type;
	179	int ret;
	180
b1608d69 GL	181	match = of_match_device(of_platform_serial_table, &ofdev->dev);
b1608d69 GL	182	if (!match)
793218df GL	183	return -EINVAL;
793218df GL	184
61c7a080	185	if (of_find_property(ofdev->dev.of_node, "used-by-rtas", NULL))
8d38a5b2 AB	186	return -EBUSY;
8d38a5b2 AB	187
7e12e675	188	info = kzalloc(sizeof(*info), GFP_KERNEL);
e34b9c94 IK	189	if (info == NULL)
	190	return -ENOMEM;
	191
b1608d69	192	port_type = (unsigned long)match->data;
0bbeb3c3	193	ret = of_platform_serial_setup(ofdev, port_type, &port, info);
8d38a5b2 AB	194	if (ret)
	195	goto out;
	196
	197	switch (port_type) {
5886188d	198	#ifdef CONFIG_SERIAL_8250
8d38a5b2	199	case PORT_8250 ... PORT_MAX_8250:
ce7240e4	200	{
ce7240e4 AC	201	struct uart_8250_port port8250;
	202	memset(&port8250, 0, sizeof(port8250));
	203	port8250.port = port;
b0b8c84c HK	204
	205	if (port.fifosize)
	206	port8250.capabilities = UART_CAP_FIFO;
	207
	208	if (of_property_read_bool(ofdev->dev.of_node,
	209	"auto-flow-control"))
	210	port8250.capabilities \|= UART_CAP_AFE;
	211
ce7240e4	212	ret = serial8250_register_8250_port(&port8250);
8d38a5b2	213	break;
ce7240e4	214	}
5886188d BK	215	#endif
	216	#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
	217	case PORT_NWPSERIAL:
	218	ret = nwpserial_register_port(&port);
	219	break;
	220	#endif
8d38a5b2 AB	221	default:
8d38a5b2 AB	222	/* need to add code for these */
1558f9b4 IK	223	case PORT_UNKNOWN:
1558f9b4 IK	224	dev_info(&ofdev->dev, "Unknown serial port found, ignored\n");
8d38a5b2 AB	225	ret = -ENODEV;
	226	break;
	227	}
	228	if (ret < 0)
	229	goto out;
	230
e34b9c94 IK	231	info->type = port_type;
e34b9c94 IK	232	info->line = ret;
696faedd	233	platform_set_drvdata(ofdev, info);
8d38a5b2 AB	234	return 0;
8d38a5b2 AB	235	out:
e34b9c94	236	kfree(info);
8d38a5b2 AB	237	irq_dispose_mapping(port.irq);
	238	return ret;
	239	}
	240
	241	/*
	242	* Release a line
	243	*/
2dc11581	244	static int of_platform_serial_remove(struct platform_device *ofdev)
8d38a5b2	245	{
696faedd	246	struct of_serial_info *info = platform_get_drvdata(ofdev);
e34b9c94	247	switch (info->type) {
5886188d	248	#ifdef CONFIG_SERIAL_8250
e34b9c94 IK	249	case PORT_8250 ... PORT_MAX_8250:
	250	serial8250_unregister_port(info->line);
	251	break;
5886188d BK	252	#endif
	253	#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
	254	case PORT_NWPSERIAL:
	255	nwpserial_unregister_port(info->line);
	256	break;
	257	#endif
e34b9c94 IK	258	default:
	259	/* need to add code for these */
	260	break;
	261	}
0bbeb3c3 MK	262
	263	if (info->clk)
	264	clk_disable_unprepare(info->clk);
e34b9c94	265	kfree(info);
8d38a5b2 AB	266	return 0;
	267	}
	268
8ad3b135 JL	269	#ifdef CONFIG_PM_SLEEP
	270	#ifdef CONFIG_SERIAL_8250
	271	static void of_serial_suspend_8250(struct of_serial_info *info)
	272	{
	273	struct uart_8250_port *port8250 = serial8250_get_port(info->line);
	274	struct uart_port *port = &port8250->port;
	275
	276	serial8250_suspend_port(info->line);
	277	if (info->clk && (!uart_console(port) \|\| console_suspend_enabled))
	278	clk_disable_unprepare(info->clk);
	279	}
	280
	281	static void of_serial_resume_8250(struct of_serial_info *info)
	282	{
	283	struct uart_8250_port *port8250 = serial8250_get_port(info->line);
	284	struct uart_port *port = &port8250->port;
	285
	286	if (info->clk && (!uart_console(port) \|\| console_suspend_enabled))
	287	clk_prepare_enable(info->clk);
	288
	289	serial8250_resume_port(info->line);
	290	}
	291	#else
	292	static inline void of_serial_suspend_8250(struct of_serial_info *info)
	293	{
	294	}
	295
	296	static inline void of_serial_resume_8250(struct of_serial_info *info)
	297	{
	298	}
	299	#endif
	300
	301	static int of_serial_suspend(struct device *dev)
	302	{
	303	struct of_serial_info *info = dev_get_drvdata(dev);
	304
	305	switch (info->type) {
	306	case PORT_8250 ... PORT_MAX_8250:
	307	of_serial_suspend_8250(info);
	308	break;
	309	default:
	310	break;
	311	}
	312
	313	return 0;
	314	}
	315
	316	static int of_serial_resume(struct device *dev)
	317	{
	318	struct of_serial_info *info = dev_get_drvdata(dev);
	319
	320	switch (info->type) {
	321	case PORT_8250 ... PORT_MAX_8250:
	322	of_serial_resume_8250(info);
	323	break;
	324	default:
	325	break;
	326	}
	327
	328	return 0;
	329	}
	330	#endif
	331	static SIMPLE_DEV_PM_OPS(of_serial_pm_ops, of_serial_suspend, of_serial_resume);
	332
8d38a5b2 AB	333	/*
	334	* A few common types, add more as needed.
	335	*/
ed0bb232	336	static const struct of_device_id of_platform_serial_table[] = {
8c6e9112 GL	337	{ .compatible = "ns8250", .data = (void *)PORT_8250, },
	338	{ .compatible = "ns16450", .data = (void *)PORT_16450, },
	339	{ .compatible = "ns16550a", .data = (void *)PORT_16550A, },
	340	{ .compatible = "ns16550", .data = (void *)PORT_16550, },
	341	{ .compatible = "ns16750", .data = (void *)PORT_16750, },
	342	{ .compatible = "ns16850", .data = (void *)PORT_16850, },
2e39e5be	343	{ .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },
e4305f0c	344	{ .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
9b8777e3	345	{ .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, },
e06c93ca LFT	346	{ .compatible = "altr,16550-FIFO32",
	347	.data = (void *)PORT_ALTR_16550_F32, },
	348	{ .compatible = "altr,16550-FIFO64",
	349	.data = (void *)PORT_ALTR_16550_F64, },
	350	{ .compatible = "altr,16550-FIFO128",
	351	.data = (void *)PORT_ALTR_16550_F128, },
6ad991b6 RH	352	{ .compatible = "mrvl,mmp-uart",
	353	.data = (void *)PORT_XSCALE, },
	354	{ .compatible = "mrvl,pxa-uart",
	355	.data = (void *)PORT_XSCALE, },
5886188d	356	#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
8c6e9112 GL	357	{ .compatible = "ibm,qpace-nwp-serial",
8c6e9112 GL	358	.data = (void *)PORT_NWPSERIAL, },
5886188d	359	#endif
8d38a5b2 AB	360	{ /* end of list */ },
8d38a5b2 AB	361	};
8d58db1e	362	MODULE_DEVICE_TABLE(of, of_platform_serial_table);
8d38a5b2	363
793218df	364	static struct platform_driver of_platform_serial_driver = {
4018294b GL	365	.driver = {
4018294b GL	366	.name = "of_serial",
4018294b GL	367	.of_match_table = of_platform_serial_table,
4018294b GL	368	},
8d38a5b2 AB	369	.probe = of_platform_serial_probe,
8d38a5b2 AB	370	.remove = of_platform_serial_remove,
8d38a5b2 AB	371	};
8d38a5b2 AB	372
940ab889	373	module_platform_driver(of_platform_serial_driver);
8d38a5b2 AB	374
	375	MODULE_AUTHOR("Arnd Bergmann <arnd@arndb.de>");
	376	MODULE_LICENSE("GPL");
	377	MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices");