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serial: omap: fix DeviceTree boot
[deliverable/linux.git] / drivers / tty / serial / omap-serial.c
CommitLineData
b612633b
G		 1/*
2 * Driver for OMAP-UART controller.
3 * Based on drivers/serial/8250.c
4 *
5 * Copyright (C) 2010 Texas Instruments.
6 *
7 * Authors:
8 * Govindraj R <govindraj.raja@ti.com>
9 * Thara Gopinath <thara@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
25985edc 16 * Note: This driver is made separate from 8250 driver as we cannot
b612633b
G		 17 * over load 8250 driver with omap platform specific configuration for
18 * features like DMA, it makes easier to implement features like DMA and
19 * hardware flow control and software flow control configuration with
20 * this driver as required for the omap-platform.
21 */
22
364a6ece
TW		 23#if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24#define SUPPORT_SYSRQ
25#endif
26
b612633b
G		 27#include <linux/module.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/serial_reg.h>
31#include <linux/delay.h>
32#include <linux/slab.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
d21e4005 35#include <linux/platform_device.h>
b612633b 36#include <linux/io.h>
b612633b
G		 37#include <linux/clk.h>
38#include <linux/serial_core.h>
39#include <linux/irq.h>
fcdca757 40#include <linux/pm_runtime.h>
d92b0dfc 41#include <linux/of.h>
9574f36f 42#include <linux/gpio.h>
b612633b 43
b612633b
G		 44#include <plat/omap-serial.h>
45
7c77c8de
G		 46#define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
47
48#define OMAP_UART_REV_42 0x0402
49#define OMAP_UART_REV_46 0x0406
50#define OMAP_UART_REV_52 0x0502
51#define OMAP_UART_REV_63 0x0603
52
8fe789dc
RN		 53#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
54
0ba5f668
PW		 55/* SCR register bitmasks */
56#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
57
58/* FCR register bitmasks */
0ba5f668 59#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
6721ab7f 60#define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4)
0ba5f668 61
7c77c8de
G		 62/* MVR register bitmasks */
63#define OMAP_UART_MVR_SCHEME_SHIFT 30
64
65#define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
66#define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
67#define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
68
69#define OMAP_UART_MVR_MAJ_MASK 0x700
70#define OMAP_UART_MVR_MAJ_SHIFT 8
71#define OMAP_UART_MVR_MIN_MASK 0x3f
72
d37c6ceb
FB		 73struct uart_omap_port {
74 struct uart_port port;
75 struct uart_omap_dma uart_dma;
76 struct device *dev;
77
78 unsigned char ier;
79 unsigned char lcr;
80 unsigned char mcr;
81 unsigned char fcr;
82 unsigned char efr;
83 unsigned char dll;
84 unsigned char dlh;
85 unsigned char mdr1;
86 unsigned char scr;
87
88 int use_dma;
89 /*
90 * Some bits in registers are cleared on a read, so they must
91 * be saved whenever the register is read but the bits will not
92 * be immediately processed.
93 */
94 unsigned int lsr_break_flag;
95 unsigned char msr_saved_flags;
96 char name[20];
97 unsigned long port_activity;
98 u32 context_loss_cnt;
99 u32 errata;
100 u8 wakeups_enabled;
101 unsigned int irq_pending:1;
102
e36851d0
FB		 103 int DTR_gpio;
104 int DTR_inverted;
105 int DTR_active;
106
d37c6ceb
FB		 107 struct pm_qos_request pm_qos_request;
108 u32 latency;
109 u32 calc_latency;
110 struct work_struct qos_work;
111};
112
113#define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
114
b612633b
G		 115static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
116
117/* Forward declaration of functions */
94734749 118static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
b612633b 119
2fd14964 120static struct workqueue_struct *serial_omap_uart_wq;
b612633b
G		 121
122static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
123{
124 offset <<= up->port.regshift;
125 return readw(up->port.membase + offset);
126}
127
128static inline void serial_out(struct uart_omap_port *up, int offset, int value)
129{
130 offset <<= up->port.regshift;
131 writew(value, up->port.membase + offset);
132}
133
134static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
135{
136 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
137 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
138 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
139 serial_out(up, UART_FCR, 0);
140}
141
e5b57c03
FB		 142static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
143{
d8ee4ea6 144 struct omap_uart_port_info *pdata = up->dev->platform_data;
e5b57c03 145
ce2f08de 146 if (!pdata || !pdata->get_context_loss_count)
e5b57c03
FB		 147 return 0;
148
d8ee4ea6 149 return pdata->get_context_loss_count(up->dev);
e5b57c03
FB		 150}
151
152static void serial_omap_set_forceidle(struct uart_omap_port *up)
153{
d8ee4ea6 154 struct omap_uart_port_info *pdata = up->dev->platform_data;
e5b57c03 155
ce2f08de
FB		 156 if (!pdata || !pdata->set_forceidle)
157 return;
158
159 pdata->set_forceidle(up->dev);
e5b57c03
FB		 160}
161
162static void serial_omap_set_noidle(struct uart_omap_port *up)
163{
d8ee4ea6 164 struct omap_uart_port_info *pdata = up->dev->platform_data;
e5b57c03 165
ce2f08de
FB		 166 if (!pdata || !pdata->set_noidle)
167 return;
168
169 pdata->set_noidle(up->dev);
e5b57c03
FB		 170}
171
172static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
173{
d8ee4ea6 174 struct omap_uart_port_info *pdata = up->dev->platform_data;
e5b57c03 175
ce2f08de
FB		 176 if (!pdata || !pdata->enable_wakeup)
177 return;
178
179 pdata->enable_wakeup(up->dev, enable);
e5b57c03
FB		 180}
181
b612633b
G		 182/*
183 * serial_omap_get_divisor - calculate divisor value
184 * @port: uart port info
185 * @baud: baudrate for which divisor needs to be calculated.
186 *
187 * We have written our own function to get the divisor so as to support
188 * 13x mode. 3Mbps Baudrate as an different divisor.
189 * Reference OMAP TRM Chapter 17:
190 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
191 * referring to oversampling - divisor value
192 * baudrate 460,800 to 3,686,400 all have divisor 13
193 * except 3,000,000 which has divisor value 16
194 */
195static unsigned int
196serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
197{
198 unsigned int divisor;
199
200 if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
201 divisor = 13;
202 else
203 divisor = 16;
204 return port->uartclk/(baud * divisor);
205}
206
b612633b
G		 207static void serial_omap_enable_ms(struct uart_port *port)
208{
c990f351 209 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b 210
ba77433d 211 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
fcdca757 212
d8ee4ea6 213 pm_runtime_get_sync(up->dev);
b612633b
G		 214 up->ier |= UART_IER_MSI;
215 serial_out(up, UART_IER, up->ier);
660ac5f4
FB		 216 pm_runtime_mark_last_busy(up->dev);
217 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 218}
219
220static void serial_omap_stop_tx(struct uart_port *port)
221{
c990f351 222 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b 223
d8ee4ea6 224 pm_runtime_get_sync(up->dev);
b612633b
G		 225 if (up->ier & UART_IER_THRI) {
226 up->ier &= ~UART_IER_THRI;
227 serial_out(up, UART_IER, up->ier);
228 }
fcdca757 229
49457430 230 serial_omap_set_forceidle(up);
be4b0281 231
d8ee4ea6
FB		 232 pm_runtime_mark_last_busy(up->dev);
233 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 234}
235
236static void serial_omap_stop_rx(struct uart_port *port)
237{
c990f351 238 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b 239
d8ee4ea6 240 pm_runtime_get_sync(up->dev);
b612633b
G		 241 up->ier &= ~UART_IER_RLSI;
242 up->port.read_status_mask &= ~UART_LSR_DR;
243 serial_out(up, UART_IER, up->ier);
d8ee4ea6
FB		 244 pm_runtime_mark_last_busy(up->dev);
245 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 246}
247
bf63a086 248static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
b612633b
G		 249{
250 struct circ_buf *xmit = &up->port.state->xmit;
251 int count;
252
bf63a086
FB		 253 if (!(lsr & UART_LSR_THRE))
254 return;
255
b612633b
G		 256 if (up->port.x_char) {
257 serial_out(up, UART_TX, up->port.x_char);
258 up->port.icount.tx++;
259 up->port.x_char = 0;
260 return;
261 }
262 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
263 serial_omap_stop_tx(&up->port);
264 return;
265 }
af681cad 266 count = up->port.fifosize / 4;
b612633b
G		 267 do {
268 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
269 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
270 up->port.icount.tx++;
271 if (uart_circ_empty(xmit))
272 break;
273 } while (--count > 0);
274
0324a821
RK		 275 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
276 spin_unlock(&up->port.lock);
b612633b 277 uart_write_wakeup(&up->port);
0324a821
RK		 278 spin_lock(&up->port.lock);
279 }
b612633b
G		 280
281 if (uart_circ_empty(xmit))
282 serial_omap_stop_tx(&up->port);
283}
284
285static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
286{
287 if (!(up->ier & UART_IER_THRI)) {
288 up->ier |= UART_IER_THRI;
289 serial_out(up, UART_IER, up->ier);
290 }
291}
292
293static void serial_omap_start_tx(struct uart_port *port)
294{
c990f351 295 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b 296
49457430
FB		 297 pm_runtime_get_sync(up->dev);
298 serial_omap_enable_ier_thri(up);
299 serial_omap_set_noidle(up);
300 pm_runtime_mark_last_busy(up->dev);
301 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 302}
303
304static unsigned int check_modem_status(struct uart_omap_port *up)
305{
306 unsigned int status;
307
308 status = serial_in(up, UART_MSR);
309 status |= up->msr_saved_flags;
310 up->msr_saved_flags = 0;
311 if ((status & UART_MSR_ANY_DELTA) == 0)
312 return status;
313
314 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
315 up->port.state != NULL) {
316 if (status & UART_MSR_TERI)
317 up->port.icount.rng++;
318 if (status & UART_MSR_DDSR)
319 up->port.icount.dsr++;
320 if (status & UART_MSR_DDCD)
321 uart_handle_dcd_change
322 (&up->port, status & UART_MSR_DCD);
323 if (status & UART_MSR_DCTS)
324 uart_handle_cts_change
325 (&up->port, status & UART_MSR_CTS);
326 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
327 }
328
329 return status;
330}
331
72256cbd
FB		 332static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
333{
334 unsigned int flag;
335
336 up->port.icount.rx++;
337 flag = TTY_NORMAL;
338
339 if (lsr & UART_LSR_BI) {
340 flag = TTY_BREAK;
341 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
342 up->port.icount.brk++;
343 /*
344 * We do the SysRQ and SAK checking
345 * here because otherwise the break
346 * may get masked by ignore_status_mask
347 * or read_status_mask.
348 */
349 if (uart_handle_break(&up->port))
350 return;
351
352 }
353
354 if (lsr & UART_LSR_PE) {
355 flag = TTY_PARITY;
356 up->port.icount.parity++;
357 }
358
359 if (lsr & UART_LSR_FE) {
360 flag = TTY_FRAME;
361 up->port.icount.frame++;
362 }
363
364 if (lsr & UART_LSR_OE)
365 up->port.icount.overrun++;
366
367#ifdef CONFIG_SERIAL_OMAP_CONSOLE
368 if (up->port.line == up->port.cons->index) {
369 /* Recover the break flag from console xmit */
370 lsr |= up->lsr_break_flag;
371 }
372#endif
373 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
374}
375
376static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
377{
378 unsigned char ch = 0;
379 unsigned int flag;
380
381 if (!(lsr & UART_LSR_DR))
382 return;
383
384 ch = serial_in(up, UART_RX);
385 flag = TTY_NORMAL;
386 up->port.icount.rx++;
387
388 if (uart_handle_sysrq_char(&up->port, ch))
389 return;
390
391 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
392}
393
b612633b
G		 394/**
395 * serial_omap_irq() - This handles the interrupt from one port
396 * @irq: uart port irq number
397 * @dev_id: uart port info
398 */
52c5513d 399static irqreturn_t serial_omap_irq(int irq, void *dev_id)
b612633b
G		 400{
401 struct uart_omap_port *up = dev_id;
72256cbd 402 struct tty_struct *tty = up->port.state->port.tty;
b612633b 403 unsigned int iir, lsr;
81b75aef 404 unsigned int type;
81b75aef 405 irqreturn_t ret = IRQ_NONE;
72256cbd 406 int max_count = 256;
b612633b 407
6c3a30c7 408 spin_lock(&up->port.lock);
d8ee4ea6 409 pm_runtime_get_sync(up->dev);
72256cbd
FB		 410
411 do {
81b75aef 412 iir = serial_in(up, UART_IIR);
72256cbd
FB		 413 if (iir & UART_IIR_NO_INT)
414 break;
415
416 ret = IRQ_HANDLED;
417 lsr = serial_in(up, UART_LSR);
418
419 /* extract IRQ type from IIR register */
420 type = iir & 0x3e;
421
422 switch (type) {
423 case UART_IIR_MSI:
424 check_modem_status(up);
425 break;
426 case UART_IIR_THRI:
bf63a086 427 transmit_chars(up, lsr);
72256cbd
FB		 428 break;
429 case UART_IIR_RX_TIMEOUT:
430 /* FALLTHROUGH */
431 case UART_IIR_RDI:
432 serial_omap_rdi(up, lsr);
433 break;
434 case UART_IIR_RLSI:
435 serial_omap_rlsi(up, lsr);
436 break;
437 case UART_IIR_CTS_RTS_DSR:
438 /* simply try again */
439 break;
440 case UART_IIR_XOFF:
441 /* FALLTHROUGH */
442 default:
443 break;
444 }
445 } while (!(iir & UART_IIR_NO_INT) && max_count--);
b612633b 446
6c3a30c7 447 spin_unlock(&up->port.lock);
72256cbd
FB		 448
449 tty_flip_buffer_push(tty);
450
d8ee4ea6
FB		 451 pm_runtime_mark_last_busy(up->dev);
452 pm_runtime_put_autosuspend(up->dev);
b612633b 453 up->port_activity = jiffies;
81b75aef
FB		 454
455 return ret;
b612633b
G		 456}
457
458static unsigned int serial_omap_tx_empty(struct uart_port *port)
459{
c990f351 460 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 461 unsigned long flags = 0;
462 unsigned int ret = 0;
463
d8ee4ea6 464 pm_runtime_get_sync(up->dev);
ba77433d 465 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
b612633b
G		 466 spin_lock_irqsave(&up->port.lock, flags);
467 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
468 spin_unlock_irqrestore(&up->port.lock, flags);
660ac5f4
FB		 469 pm_runtime_mark_last_busy(up->dev);
470 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 471 return ret;
472}
473
474static unsigned int serial_omap_get_mctrl(struct uart_port *port)
475{
c990f351 476 struct uart_omap_port *up = to_uart_omap_port(port);
514f31d1 477 unsigned int status;
b612633b
G		 478 unsigned int ret = 0;
479
d8ee4ea6 480 pm_runtime_get_sync(up->dev);
b612633b 481 status = check_modem_status(up);
660ac5f4
FB		 482 pm_runtime_mark_last_busy(up->dev);
483 pm_runtime_put_autosuspend(up->dev);
fcdca757 484
ba77433d 485 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
b612633b
G		 486
487 if (status & UART_MSR_DCD)
488 ret |= TIOCM_CAR;
489 if (status & UART_MSR_RI)
490 ret |= TIOCM_RNG;
491 if (status & UART_MSR_DSR)
492 ret |= TIOCM_DSR;
493 if (status & UART_MSR_CTS)
494 ret |= TIOCM_CTS;
495 return ret;
496}
497
498static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
499{
c990f351 500 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 501 unsigned char mcr = 0;
502
ba77433d 503 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
b612633b
G		 504 if (mctrl & TIOCM_RTS)
505 mcr |= UART_MCR_RTS;
506 if (mctrl & TIOCM_DTR)
507 mcr |= UART_MCR_DTR;
508 if (mctrl & TIOCM_OUT1)
509 mcr |= UART_MCR_OUT1;
510 if (mctrl & TIOCM_OUT2)
511 mcr |= UART_MCR_OUT2;
512 if (mctrl & TIOCM_LOOP)
513 mcr |= UART_MCR_LOOP;
514
d8ee4ea6 515 pm_runtime_get_sync(up->dev);
c538d20c
G		 516 up->mcr = serial_in(up, UART_MCR);
517 up->mcr |= mcr;
518 serial_out(up, UART_MCR, up->mcr);
660ac5f4
FB		 519 pm_runtime_mark_last_busy(up->dev);
520 pm_runtime_put_autosuspend(up->dev);
9574f36f
N		 521
522 if (gpio_is_valid(up->DTR_gpio) &&
523 !!(mctrl & TIOCM_DTR) != up->DTR_active) {
524 up->DTR_active = !up->DTR_active;
525 if (gpio_cansleep(up->DTR_gpio))
526 schedule_work(&up->qos_work);
527 else
528 gpio_set_value(up->DTR_gpio,
529 up->DTR_active != up->DTR_inverted);
530 }
b612633b
G		 531}
532
533static void serial_omap_break_ctl(struct uart_port *port, int break_state)
534{
c990f351 535 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 536 unsigned long flags = 0;
537
ba77433d 538 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
d8ee4ea6 539 pm_runtime_get_sync(up->dev);
b612633b
G		 540 spin_lock_irqsave(&up->port.lock, flags);
541 if (break_state == -1)
542 up->lcr |= UART_LCR_SBC;
543 else
544 up->lcr &= ~UART_LCR_SBC;
545 serial_out(up, UART_LCR, up->lcr);
546 spin_unlock_irqrestore(&up->port.lock, flags);
660ac5f4
FB		 547 pm_runtime_mark_last_busy(up->dev);
548 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 549}
550
551static int serial_omap_startup(struct uart_port *port)
552{
c990f351 553 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 554 unsigned long flags = 0;
555 int retval;
556
557 /*
558 * Allocate the IRQ
559 */
560 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
561 up->name, up);
562 if (retval)
563 return retval;
564
ba77433d 565 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
b612633b 566
d8ee4ea6 567 pm_runtime_get_sync(up->dev);
b612633b
G		 568 /*
569 * Clear the FIFO buffers and disable them.
570 * (they will be reenabled in set_termios())
571 */
572 serial_omap_clear_fifos(up);
573 /* For Hardware flow control */
574 serial_out(up, UART_MCR, UART_MCR_RTS);
575
576 /*
577 * Clear the interrupt registers.
578 */
579 (void) serial_in(up, UART_LSR);
580 if (serial_in(up, UART_LSR) & UART_LSR_DR)
581 (void) serial_in(up, UART_RX);
582 (void) serial_in(up, UART_IIR);
583 (void) serial_in(up, UART_MSR);
584
585 /*
586 * Now, initialize the UART
587 */
588 serial_out(up, UART_LCR, UART_LCR_WLEN8);
589 spin_lock_irqsave(&up->port.lock, flags);
590 /*
591 * Most PC uarts need OUT2 raised to enable interrupts.
592 */
593 up->port.mctrl |= TIOCM_OUT2;
594 serial_omap_set_mctrl(&up->port, up->port.mctrl);
595 spin_unlock_irqrestore(&up->port.lock, flags);
596
597 up->msr_saved_flags = 0;
b612633b
G		 598 /*
599 * Finally, enable interrupts. Note: Modem status interrupts
600 * are set via set_termios(), which will be occurring imminently
601 * anyway, so we don't enable them here.
602 */
603 up->ier = UART_IER_RLSI | UART_IER_RDI;
604 serial_out(up, UART_IER, up->ier);
605
78841462
JN		 606 /* Enable module level wake up */
607 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
608
d8ee4ea6
FB		 609 pm_runtime_mark_last_busy(up->dev);
610 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 611 up->port_activity = jiffies;
612 return 0;
613}
614
615static void serial_omap_shutdown(struct uart_port *port)
616{
c990f351 617 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 618 unsigned long flags = 0;
619
ba77433d 620 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
fcdca757 621
d8ee4ea6 622 pm_runtime_get_sync(up->dev);
b612633b
G		 623 /*
624 * Disable interrupts from this port
625 */
626 up->ier = 0;
627 serial_out(up, UART_IER, 0);
628
629 spin_lock_irqsave(&up->port.lock, flags);
630 up->port.mctrl &= ~TIOCM_OUT2;
631 serial_omap_set_mctrl(&up->port, up->port.mctrl);
632 spin_unlock_irqrestore(&up->port.lock, flags);
633
634 /*
635 * Disable break condition and FIFOs
636 */
637 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
638 serial_omap_clear_fifos(up);
639
640 /*
641 * Read data port to reset things, and then free the irq
642 */
643 if (serial_in(up, UART_LSR) & UART_LSR_DR)
644 (void) serial_in(up, UART_RX);
fcdca757 645
660ac5f4
FB		 646 pm_runtime_mark_last_busy(up->dev);
647 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 648 free_irq(up->port.irq, up);
649}
650
651static inline void
652serial_omap_configure_xonxoff
653 (struct uart_omap_port *up, struct ktermios *termios)
654{
b612633b 655 up->lcr = serial_in(up, UART_LCR);
662b083a 656 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b
G		 657 up->efr = serial_in(up, UART_EFR);
658 serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
659
660 serial_out(up, UART_XON1, termios->c_cc[VSTART]);
661 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
662
663 /* clear SW control mode bits */
c538d20c 664 up->efr &= OMAP_UART_SW_CLR;
b612633b
G		 665
666 /*
667 * IXON Flag:
957ee727
VP		 668 * Flow control for OMAP.TX
669 * OMAP.RX should listen for XON/XOFF
b612633b
G		 670 */
671 if (termios->c_iflag & IXON)
957ee727 672 up->efr |= OMAP_UART_SW_RX;
b612633b
G		 673
674 /*
675 * IXOFF Flag:
957ee727
VP		 676 * Flow control for OMAP.RX
677 * OMAP.TX should send XON/XOFF
b612633b
G		 678 */
679 if (termios->c_iflag & IXOFF)
957ee727 680 up->efr |= OMAP_UART_SW_TX;
b612633b
G		 681
682 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
662b083a 683 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b612633b
G		 684
685 up->mcr = serial_in(up, UART_MCR);
686
687 /*
688 * IXANY Flag:
689 * Enable any character to restart output.
690 * Operation resumes after receiving any
691 * character after recognition of the XOFF character
692 */
693 if (termios->c_iflag & IXANY)
694 up->mcr |= UART_MCR_XONANY;
695
696 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
662b083a 697 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b
G		 698 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
699 /* Enable special char function UARTi.EFR_REG[5] and
700 * load the new software flow control mode IXON or IXOFF
701 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value.
702 */
c538d20c 703 serial_out(up, UART_EFR, up->efr | UART_EFR_SCD);
662b083a 704 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b612633b
G		 705
706 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
707 serial_out(up, UART_LCR, up->lcr);
708}
709
2fd14964
G		 710static void serial_omap_uart_qos_work(struct work_struct *work)
711{
712 struct uart_omap_port *up = container_of(work, struct uart_omap_port,
713 qos_work);
714
715 pm_qos_update_request(&up->pm_qos_request, up->latency);
9574f36f
N		 716 if (gpio_is_valid(up->DTR_gpio))
717 gpio_set_value_cansleep(up->DTR_gpio,
718 up->DTR_active != up->DTR_inverted);
2fd14964
G		 719}
720
b612633b
G		 721static void
722serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
723 struct ktermios *old)
724{
c990f351 725 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 726 unsigned char cval = 0;
727 unsigned char efr = 0;
728 unsigned long flags = 0;
729 unsigned int baud, quot;
730
731 switch (termios->c_cflag & CSIZE) {
732 case CS5:
733 cval = UART_LCR_WLEN5;
734 break;
735 case CS6:
736 cval = UART_LCR_WLEN6;
737 break;
738 case CS7:
739 cval = UART_LCR_WLEN7;
740 break;
741 default:
742 case CS8:
743 cval = UART_LCR_WLEN8;
744 break;
745 }
746
747 if (termios->c_cflag & CSTOPB)
748 cval |= UART_LCR_STOP;
749 if (termios->c_cflag & PARENB)
750 cval |= UART_LCR_PARITY;
751 if (!(termios->c_cflag & PARODD))
752 cval |= UART_LCR_EPAR;
753
754 /*
755 * Ask the core to calculate the divisor for us.
756 */
757
758 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
759 quot = serial_omap_get_divisor(port, baud);
760
2fd14964 761 /* calculate wakeup latency constraint */
19723452 762 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
2fd14964
G		 763 up->latency = up->calc_latency;
764 schedule_work(&up->qos_work);
765
c538d20c
G		 766 up->dll = quot & 0xff;
767 up->dlh = quot >> 8;
768 up->mdr1 = UART_OMAP_MDR1_DISABLE;
769
b612633b
G		 770 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
771 UART_FCR_ENABLE_FIFO;
b612633b
G		 772
773 /*
774 * Ok, we're now changing the port state. Do it with
775 * interrupts disabled.
776 */
d8ee4ea6 777 pm_runtime_get_sync(up->dev);
b612633b
G		 778 spin_lock_irqsave(&up->port.lock, flags);
779
780 /*
781 * Update the per-port timeout.
782 */
783 uart_update_timeout(port, termios->c_cflag, baud);
784
785 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
786 if (termios->c_iflag & INPCK)
787 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
788 if (termios->c_iflag & (BRKINT | PARMRK))
789 up->port.read_status_mask |= UART_LSR_BI;
790
791 /*
792 * Characters to ignore
793 */
794 up->port.ignore_status_mask = 0;
795 if (termios->c_iflag & IGNPAR)
796 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
797 if (termios->c_iflag & IGNBRK) {
798 up->port.ignore_status_mask |= UART_LSR_BI;
799 /*
800 * If we're ignoring parity and break indicators,
801 * ignore overruns too (for real raw support).
802 */
803 if (termios->c_iflag & IGNPAR)
804 up->port.ignore_status_mask |= UART_LSR_OE;
805 }
806
807 /*
808 * ignore all characters if CREAD is not set
809 */
810 if ((termios->c_cflag & CREAD) == 0)
811 up->port.ignore_status_mask |= UART_LSR_DR;
812
813 /*
814 * Modem status interrupts
815 */
816 up->ier &= ~UART_IER_MSI;
817 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
818 up->ier |= UART_IER_MSI;
819 serial_out(up, UART_IER, up->ier);
820 serial_out(up, UART_LCR, cval); /* reset DLAB */
c538d20c 821 up->lcr = cval;
32212897 822 up->scr = OMAP_UART_SCR_TX_EMPTY;
b612633b
G		 823
824 /* FIFOs and DMA Settings */
825
826 /* FCR can be changed only when the
827 * baud clock is not running
828 * DLL_REG and DLH_REG set to 0.
829 */
662b083a 830 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b612633b
G		 831 serial_out(up, UART_DLL, 0);
832 serial_out(up, UART_DLM, 0);
833 serial_out(up, UART_LCR, 0);
834
662b083a 835 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b
G		 836
837 up->efr = serial_in(up, UART_EFR);
838 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
839
662b083a 840 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b612633b
G		 841 up->mcr = serial_in(up, UART_MCR);
842 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
843 /* FIFO ENABLE, DMA MODE */
0ba5f668
PW		 844
845 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
b612633b 846
6721ab7f
FB		 847 /* Set receive FIFO threshold to 16 characters and
848 * transmit FIFO threshold to 16 spaces
849 */
49457430 850 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
6721ab7f
FB		 851 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
852 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
853 UART_FCR_ENABLE_FIFO;
b612633b 854
0ba5f668
PW		 855 serial_out(up, UART_FCR, up->fcr);
856 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
857
c538d20c
G		 858 serial_out(up, UART_OMAP_SCR, up->scr);
859
b612633b 860 serial_out(up, UART_EFR, up->efr);
662b083a 861 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b612633b
G		 862 serial_out(up, UART_MCR, up->mcr);
863
864 /* Protocol, Baud Rate, and Interrupt Settings */
865
94734749
G		 866 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
867 serial_omap_mdr1_errataset(up, up->mdr1);
868 else
869 serial_out(up, UART_OMAP_MDR1, up->mdr1);
870
662b083a 871 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b
G		 872
873 up->efr = serial_in(up, UART_EFR);
874 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
875
876 serial_out(up, UART_LCR, 0);
877 serial_out(up, UART_IER, 0);
662b083a 878 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b 879
c538d20c
G		 880 serial_out(up, UART_DLL, up->dll); /* LS of divisor */
881 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */
b612633b
G		 882
883 serial_out(up, UART_LCR, 0);
884 serial_out(up, UART_IER, up->ier);
662b083a 885 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b
G		 886
887 serial_out(up, UART_EFR, up->efr);
888 serial_out(up, UART_LCR, cval);
889
890 if (baud > 230400 && baud != 3000000)
c538d20c 891 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
b612633b 892 else
c538d20c
G		 893 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
894
94734749
G		 895 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
896 serial_omap_mdr1_errataset(up, up->mdr1);
897 else
898 serial_out(up, UART_OMAP_MDR1, up->mdr1);
b612633b
G		 899
900 /* Hardware Flow Control Configuration */
901
902 if (termios->c_cflag & CRTSCTS) {
903 efr |= (UART_EFR_CTS | UART_EFR_RTS);
662b083a 904 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b612633b
G		 905
906 up->mcr = serial_in(up, UART_MCR);
907 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
908
662b083a 909 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b
G		 910 up->efr = serial_in(up, UART_EFR);
911 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
912
913 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
914 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
662b083a 915 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
b612633b
G		 916 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
917 serial_out(up, UART_LCR, cval);
918 }
919
920 serial_omap_set_mctrl(&up->port, up->port.mctrl);
921 /* Software Flow Control Configuration */
b280a97d 922 serial_omap_configure_xonxoff(up, termios);
b612633b
G		 923
924 spin_unlock_irqrestore(&up->port.lock, flags);
660ac5f4
FB		 925 pm_runtime_mark_last_busy(up->dev);
926 pm_runtime_put_autosuspend(up->dev);
ba77433d 927 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
b612633b
G		 928}
929
9727faf4
FB		 930static int serial_omap_set_wake(struct uart_port *port, unsigned int state)
931{
932 struct uart_omap_port *up = to_uart_omap_port(port);
933
934 serial_omap_enable_wakeup(up, state);
935
936 return 0;
937}
938
b612633b
G		 939static void
940serial_omap_pm(struct uart_port *port, unsigned int state,
941 unsigned int oldstate)
942{
c990f351 943 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 944 unsigned char efr;
945
ba77433d 946 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
fcdca757 947
d8ee4ea6 948 pm_runtime_get_sync(up->dev);
662b083a 949 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b
G		 950 efr = serial_in(up, UART_EFR);
951 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
952 serial_out(up, UART_LCR, 0);
953
954 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
662b083a 955 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
b612633b
G		 956 serial_out(up, UART_EFR, efr);
957 serial_out(up, UART_LCR, 0);
fcdca757 958
d8ee4ea6 959 if (!device_may_wakeup(up->dev)) {
fcdca757 960 if (!state)
d8ee4ea6 961 pm_runtime_forbid(up->dev);
fcdca757 962 else
d8ee4ea6 963 pm_runtime_allow(up->dev);
fcdca757
G		 964 }
965
660ac5f4
FB		 966 pm_runtime_mark_last_busy(up->dev);
967 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 968}
969
970static void serial_omap_release_port(struct uart_port *port)
971{
972 dev_dbg(port->dev, "serial_omap_release_port+\n");
973}
974
975static int serial_omap_request_port(struct uart_port *port)
976{
977 dev_dbg(port->dev, "serial_omap_request_port+\n");
978 return 0;
979}
980
981static void serial_omap_config_port(struct uart_port *port, int flags)
982{
c990f351 983 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 984
985 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
ba77433d 986 up->port.line);
b612633b
G		 987 up->port.type = PORT_OMAP;
988}
989
990static int
991serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
992{
993 /* we don't want the core code to modify any port params */
994 dev_dbg(port->dev, "serial_omap_verify_port+\n");
995 return -EINVAL;
996}
997
998static const char *
999serial_omap_type(struct uart_port *port)
1000{
c990f351 1001 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b 1002
ba77433d 1003 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
b612633b
G		 1004 return up->name;
1005}
1006
b612633b
G		 1007#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1008
1009static inline void wait_for_xmitr(struct uart_omap_port *up)
1010{
1011 unsigned int status, tmout = 10000;
1012
1013 /* Wait up to 10ms for the character(s) to be sent. */
1014 do {
1015 status = serial_in(up, UART_LSR);
1016
1017 if (status & UART_LSR_BI)
1018 up->lsr_break_flag = UART_LSR_BI;
1019
1020 if (--tmout == 0)
1021 break;
1022 udelay(1);
1023 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1024
1025 /* Wait up to 1s for flow control if necessary */
1026 if (up->port.flags & UPF_CONS_FLOW) {
1027 tmout = 1000000;
1028 for (tmout = 1000000; tmout; tmout--) {
1029 unsigned int msr = serial_in(up, UART_MSR);
1030
1031 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1032 if (msr & UART_MSR_CTS)
1033 break;
1034
1035 udelay(1);
1036 }
1037 }
1038}
1039
1b41dbc1
CC		 1040#ifdef CONFIG_CONSOLE_POLL
1041
1042static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1043{
c990f351 1044 struct uart_omap_port *up = to_uart_omap_port(port);
fcdca757 1045
d8ee4ea6 1046 pm_runtime_get_sync(up->dev);
1b41dbc1
CC		 1047 wait_for_xmitr(up);
1048 serial_out(up, UART_TX, ch);
660ac5f4
FB		 1049 pm_runtime_mark_last_busy(up->dev);
1050 pm_runtime_put_autosuspend(up->dev);
1b41dbc1
CC		 1051}
1052
1053static int serial_omap_poll_get_char(struct uart_port *port)
1054{
c990f351 1055 struct uart_omap_port *up = to_uart_omap_port(port);
fcdca757 1056 unsigned int status;
1b41dbc1 1057
d8ee4ea6 1058 pm_runtime_get_sync(up->dev);
fcdca757 1059 status = serial_in(up, UART_LSR);
a6b19c33
FB		 1060 if (!(status & UART_LSR_DR)) {
1061 status = NO_POLL_CHAR;
1062 goto out;
1063 }
1b41dbc1 1064
fcdca757 1065 status = serial_in(up, UART_RX);
a6b19c33
FB		 1066
1067out:
660ac5f4
FB		 1068 pm_runtime_mark_last_busy(up->dev);
1069 pm_runtime_put_autosuspend(up->dev);
a6b19c33 1070
fcdca757 1071 return status;
1b41dbc1
CC		 1072}
1073
1074#endif /* CONFIG_CONSOLE_POLL */
1075
1076#ifdef CONFIG_SERIAL_OMAP_CONSOLE
1077
1078static struct uart_omap_port *serial_omap_console_ports[4];
1079
1080static struct uart_driver serial_omap_reg;
1081
b612633b
G		 1082static void serial_omap_console_putchar(struct uart_port *port, int ch)
1083{
c990f351 1084 struct uart_omap_port *up = to_uart_omap_port(port);
b612633b
G		 1085
1086 wait_for_xmitr(up);
1087 serial_out(up, UART_TX, ch);
1088}
1089
1090static void
1091serial_omap_console_write(struct console *co, const char *s,
1092 unsigned int count)
1093{
1094 struct uart_omap_port *up = serial_omap_console_ports[co->index];
1095 unsigned long flags;
1096 unsigned int ier;
1097 int locked = 1;
1098
d8ee4ea6 1099 pm_runtime_get_sync(up->dev);
fcdca757 1100
b612633b
G		 1101 local_irq_save(flags);
1102 if (up->port.sysrq)
1103 locked = 0;
1104 else if (oops_in_progress)
1105 locked = spin_trylock(&up->port.lock);
1106 else
1107 spin_lock(&up->port.lock);
1108
1109 /*
1110 * First save the IER then disable the interrupts
1111 */
1112 ier = serial_in(up, UART_IER);
1113 serial_out(up, UART_IER, 0);
1114
1115 uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1116
1117 /*
1118 * Finally, wait for transmitter to become empty
1119 * and restore the IER
1120 */
1121 wait_for_xmitr(up);
1122 serial_out(up, UART_IER, ier);
1123 /*
1124 * The receive handling will happen properly because the
1125 * receive ready bit will still be set; it is not cleared
1126 * on read. However, modem control will not, we must
1127 * call it if we have saved something in the saved flags
1128 * while processing with interrupts off.
1129 */
1130 if (up->msr_saved_flags)
1131 check_modem_status(up);
1132
d8ee4ea6
FB		 1133 pm_runtime_mark_last_busy(up->dev);
1134 pm_runtime_put_autosuspend(up->dev);
b612633b
G		 1135 if (locked)
1136 spin_unlock(&up->port.lock);
1137 local_irq_restore(flags);
1138}
1139
1140static int __init
1141serial_omap_console_setup(struct console *co, char *options)
1142{
1143 struct uart_omap_port *up;
1144 int baud = 115200;
1145 int bits = 8;
1146 int parity = 'n';
1147 int flow = 'n';
1148
1149 if (serial_omap_console_ports[co->index] == NULL)
1150 return -ENODEV;
1151 up = serial_omap_console_ports[co->index];
1152
1153 if (options)
1154 uart_parse_options(options, &baud, &parity, &bits, &flow);
1155
1156 return uart_set_options(&up->port, co, baud, parity, bits, flow);
1157}
1158
1159static struct console serial_omap_console = {
1160 .name = OMAP_SERIAL_NAME,
1161 .write = serial_omap_console_write,
1162 .device = uart_console_device,
1163 .setup = serial_omap_console_setup,
1164 .flags = CON_PRINTBUFFER,
1165 .index = -1,
1166 .data = &serial_omap_reg,
1167};
1168
1169static void serial_omap_add_console_port(struct uart_omap_port *up)
1170{
ba77433d 1171 serial_omap_console_ports[up->port.line] = up;
b612633b
G		 1172}
1173
1174#define OMAP_CONSOLE (&serial_omap_console)
1175
1176#else
1177
1178#define OMAP_CONSOLE NULL
1179
1180static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1181{}
1182
1183#endif
1184
1185static struct uart_ops serial_omap_pops = {
1186 .tx_empty = serial_omap_tx_empty,
1187 .set_mctrl = serial_omap_set_mctrl,
1188 .get_mctrl = serial_omap_get_mctrl,
1189 .stop_tx = serial_omap_stop_tx,
1190 .start_tx = serial_omap_start_tx,
1191 .stop_rx = serial_omap_stop_rx,
1192 .enable_ms = serial_omap_enable_ms,
1193 .break_ctl = serial_omap_break_ctl,
1194 .startup = serial_omap_startup,
1195 .shutdown = serial_omap_shutdown,
1196 .set_termios = serial_omap_set_termios,
1197 .pm = serial_omap_pm,
9727faf4 1198 .set_wake = serial_omap_set_wake,
b612633b
G		 1199 .type = serial_omap_type,
1200 .release_port = serial_omap_release_port,
1201 .request_port = serial_omap_request_port,
1202 .config_port = serial_omap_config_port,
1203 .verify_port = serial_omap_verify_port,
1b41dbc1
CC		 1204#ifdef CONFIG_CONSOLE_POLL
1205 .poll_put_char = serial_omap_poll_put_char,
1206 .poll_get_char = serial_omap_poll_get_char,
1207#endif
b612633b
G		 1208};
1209
1210static struct uart_driver serial_omap_reg = {
1211 .owner = THIS_MODULE,
1212 .driver_name = "OMAP-SERIAL",
1213 .dev_name = OMAP_SERIAL_NAME,
1214 .nr = OMAP_MAX_HSUART_PORTS,
1215 .cons = OMAP_CONSOLE,
1216};
1217
3bc4f0d8 1218#ifdef CONFIG_PM_SLEEP
fcdca757 1219static int serial_omap_suspend(struct device *dev)
b612633b 1220{
fcdca757 1221 struct uart_omap_port *up = dev_get_drvdata(dev);
b612633b 1222
2fd14964 1223 if (up) {
b612633b 1224 uart_suspend_port(&serial_omap_reg, &up->port);
2fd14964
G		 1225 flush_work_sync(&up->qos_work);
1226 }
1227
b612633b
G		 1228 return 0;
1229}
1230
fcdca757 1231static int serial_omap_resume(struct device *dev)
b612633b 1232{
fcdca757 1233 struct uart_omap_port *up = dev_get_drvdata(dev);
b612633b
G		 1234
1235 if (up)
1236 uart_resume_port(&serial_omap_reg, &up->port);
1237 return 0;
1238}
fcdca757 1239#endif
b612633b 1240
6d608ef3 1241static void __devinit omap_serial_fill_features_erratas(struct uart_omap_port *up)
7c77c8de
G		 1242{
1243 u32 mvr, scheme;
1244 u16 revision, major, minor;
1245
1246 mvr = serial_in(up, UART_OMAP_MVER);
1247
1248 /* Check revision register scheme */
1249 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1250
1251 switch (scheme) {
1252 case 0: /* Legacy Scheme: OMAP2/3 */
1253 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1254 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1255 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1256 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1257 break;
1258 case 1:
1259 /* New Scheme: OMAP4+ */
1260 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1261 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1262 OMAP_UART_MVR_MAJ_SHIFT;
1263 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1264 break;
1265 default:
d8ee4ea6 1266 dev_warn(up->dev,
7c77c8de
G		 1267 "Unknown %s revision, defaulting to highest\n",
1268 up->name);
1269 /* highest possible revision */
1270 major = 0xff;
1271 minor = 0xff;
1272 }
1273
1274 /* normalize revision for the driver */
1275 revision = UART_BUILD_REVISION(major, minor);
1276
1277 switch (revision) {
1278 case OMAP_UART_REV_46:
1279 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1280 UART_ERRATA_i291_DMA_FORCEIDLE);
1281 break;
1282 case OMAP_UART_REV_52:
1283 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1284 UART_ERRATA_i291_DMA_FORCEIDLE);
1285 break;
1286 case OMAP_UART_REV_63:
1287 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1288 break;
1289 default:
1290 break;
1291 }
1292}
1293
6d608ef3 1294static __devinit struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
d92b0dfc
RN		 1295{
1296 struct omap_uart_port_info *omap_up_info;
1297
1298 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1299 if (!omap_up_info)
1300 return NULL; /* out of memory */
1301
1302 of_property_read_u32(dev->of_node, "clock-frequency",
1303 &omap_up_info->uartclk);
1304 return omap_up_info;
1305}
1306
6d608ef3 1307static int __devinit serial_omap_probe(struct platform_device *pdev)
b612633b
G		 1308{
1309 struct uart_omap_port *up;
49457430 1310 struct resource *mem, *irq;
b612633b 1311 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
9574f36f 1312 int ret;
b612633b 1313
d92b0dfc
RN		 1314 if (pdev->dev.of_node)
1315 omap_up_info = of_get_uart_port_info(&pdev->dev);
1316
b612633b
G		 1317 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1318 if (!mem) {
1319 dev_err(&pdev->dev, "no mem resource?\n");
1320 return -ENODEV;
1321 }
1322
1323 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1324 if (!irq) {
1325 dev_err(&pdev->dev, "no irq resource?\n");
1326 return -ENODEV;
1327 }
1328
388bc262 1329 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
28f65c11 1330 pdev->dev.driver->name)) {
b612633b
G		 1331 dev_err(&pdev->dev, "memory region already claimed\n");
1332 return -EBUSY;
1333 }
1334
9574f36f
N		 1335 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1336 omap_up_info->DTR_present) {
1337 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1338 if (ret < 0)
1339 return ret;
1340 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1341 omap_up_info->DTR_inverted);
1342 if (ret < 0)
1343 return ret;
1344 }
1345
388bc262
S		 1346 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1347 if (!up)
1348 return -ENOMEM;
b612633b 1349
9574f36f
N		 1350 if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1351 omap_up_info->DTR_present) {
1352 up->DTR_gpio = omap_up_info->DTR_gpio;
1353 up->DTR_inverted = omap_up_info->DTR_inverted;
1354 } else
1355 up->DTR_gpio = -EINVAL;
1356 up->DTR_active = 0;
1357
d8ee4ea6 1358 up->dev = &pdev->dev;
b612633b
G		 1359 up->port.dev = &pdev->dev;
1360 up->port.type = PORT_OMAP;
1361 up->port.iotype = UPIO_MEM;
1362 up->port.irq = irq->start;
1363
1364 up->port.regshift = 2;
1365 up->port.fifosize = 64;
1366 up->port.ops = &serial_omap_pops;
b612633b 1367
d92b0dfc
RN		 1368 if (pdev->dev.of_node)
1369 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1370 else
1371 up->port.line = pdev->id;
1372
1373 if (up->port.line < 0) {
1374 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1375 up->port.line);
1376 ret = -ENODEV;
388bc262 1377 goto err_port_line;
d92b0dfc
RN		 1378 }
1379
1380 sprintf(up->name, "OMAP UART%d", up->port.line);
edd70ad7 1381 up->port.mapbase = mem->start;
388bc262
S		 1382 up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1383 resource_size(mem));
edd70ad7
G		 1384 if (!up->port.membase) {
1385 dev_err(&pdev->dev, "can't ioremap UART\n");
1386 ret = -ENOMEM;
388bc262 1387 goto err_ioremap;
edd70ad7
G		 1388 }
1389
b612633b 1390 up->port.flags = omap_up_info->flags;
b612633b 1391 up->port.uartclk = omap_up_info->uartclk;
8fe789dc
RN		 1392 if (!up->port.uartclk) {
1393 up->port.uartclk = DEFAULT_CLK_SPEED;
1394 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1395 "%d\n", DEFAULT_CLK_SPEED);
1396 }
b612633b 1397
2fd14964
G		 1398 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1399 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1400 pm_qos_add_request(&up->pm_qos_request,
1401 PM_QOS_CPU_DMA_LATENCY, up->latency);
1402 serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1403 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1404
93220dcc 1405 platform_set_drvdata(pdev, up);
856e35bf 1406 pm_runtime_enable(&pdev->dev);
fcdca757
G		 1407 pm_runtime_use_autosuspend(&pdev->dev);
1408 pm_runtime_set_autosuspend_delay(&pdev->dev,
c86845db 1409 omap_up_info->autosuspend_timeout);
fcdca757
G		 1410
1411 pm_runtime_irq_safe(&pdev->dev);
fcdca757
G		 1412 pm_runtime_get_sync(&pdev->dev);
1413
7c77c8de
G		 1414 omap_serial_fill_features_erratas(up);
1415
ba77433d 1416 ui[up->port.line] = up;
b612633b
G		 1417 serial_omap_add_console_port(up);
1418
1419 ret = uart_add_one_port(&serial_omap_reg, &up->port);
1420 if (ret != 0)
388bc262 1421 goto err_add_port;
b612633b 1422
660ac5f4
FB		 1423 pm_runtime_mark_last_busy(up->dev);
1424 pm_runtime_put_autosuspend(up->dev);
b612633b 1425 return 0;
388bc262
S		 1426
1427err_add_port:
1428 pm_runtime_put(&pdev->dev);
1429 pm_runtime_disable(&pdev->dev);
1430err_ioremap:
1431err_port_line:
b612633b
G		 1432 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1433 pdev->id, __func__, ret);
b612633b
G		 1434 return ret;
1435}
1436
6d608ef3 1437static int __devexit serial_omap_remove(struct platform_device *dev)
b612633b
G		 1438{
1439 struct uart_omap_port *up = platform_get_drvdata(dev);
1440
7e9c8e7d 1441 pm_runtime_put_sync(up->dev);
1b42c8b2
FB		 1442 pm_runtime_disable(up->dev);
1443 uart_remove_one_port(&serial_omap_reg, &up->port);
1444 pm_qos_remove_request(&up->pm_qos_request);
fcdca757 1445
fcdca757
G		 1446 return 0;
1447}
1448
94734749
G		 1449/*
1450 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1451 * The access to uart register after MDR1 Access
1452 * causes UART to corrupt data.
1453 *
1454 * Need a delay =
1455 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1456 * give 10 times as much
1457 */
1458static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1459{
1460 u8 timeout = 255;
1461
1462 serial_out(up, UART_OMAP_MDR1, mdr1);
1463 udelay(2);
1464 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1465 UART_FCR_CLEAR_RCVR);
1466 /*
1467 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1468 * TX_FIFO_E bit is 1.
1469 */
1470 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1471 (UART_LSR_THRE | UART_LSR_DR))) {
1472 timeout--;
1473 if (!timeout) {
1474 /* Should *never* happen. we warn and carry on */
d8ee4ea6 1475 dev_crit(up->dev, "Errata i202: timedout %x\n",
94734749
G		 1476 serial_in(up, UART_LSR));
1477 break;
1478 }
1479 udelay(1);
1480 }
1481}
1482
b5148856 1483#ifdef CONFIG_PM_RUNTIME
9f9ac1e8
G		 1484static void serial_omap_restore_context(struct uart_omap_port *up)
1485{
94734749
G		 1486 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1487 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1488 else
1489 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1490
9f9ac1e8
G		 1491 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1492 serial_out(up, UART_EFR, UART_EFR_ECB);
1493 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1494 serial_out(up, UART_IER, 0x0);
1495 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
c538d20c
G		 1496 serial_out(up, UART_DLL, up->dll);
1497 serial_out(up, UART_DLM, up->dlh);
9f9ac1e8
G		 1498 serial_out(up, UART_LCR, 0x0); /* Operational mode */
1499 serial_out(up, UART_IER, up->ier);
1500 serial_out(up, UART_FCR, up->fcr);
1501 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1502 serial_out(up, UART_MCR, up->mcr);
1503 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
c538d20c 1504 serial_out(up, UART_OMAP_SCR, up->scr);
9f9ac1e8
G		 1505 serial_out(up, UART_EFR, up->efr);
1506 serial_out(up, UART_LCR, up->lcr);
94734749
G		 1507 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1508 serial_omap_mdr1_errataset(up, up->mdr1);
1509 else
1510 serial_out(up, UART_OMAP_MDR1, up->mdr1);
9f9ac1e8
G		 1511}
1512
fcdca757
G		 1513static int serial_omap_runtime_suspend(struct device *dev)
1514{
ec3bebc6
G		 1515 struct uart_omap_port *up = dev_get_drvdata(dev);
1516 struct omap_uart_port_info *pdata = dev->platform_data;
1517
1518 if (!up)
1519 return -EINVAL;
1520
e5b57c03 1521 if (!pdata)
62f3ec5f
G		 1522 return 0;
1523
e5b57c03 1524 up->context_loss_cnt = serial_omap_get_context_loss_count(up);
ec3bebc6 1525
62f3ec5f
G		 1526 if (device_may_wakeup(dev)) {
1527 if (!up->wakeups_enabled) {
e5b57c03 1528 serial_omap_enable_wakeup(up, true);
62f3ec5f
G		 1529 up->wakeups_enabled = true;
1530 }
1531 } else {
1532 if (up->wakeups_enabled) {
e5b57c03 1533 serial_omap_enable_wakeup(up, false);
62f3ec5f
G		 1534 up->wakeups_enabled = false;
1535 }
1536 }
1537
2fd14964
G		 1538 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1539 schedule_work(&up->qos_work);
1540
b612633b
G		 1541 return 0;
1542}
1543
fcdca757
G		 1544static int serial_omap_runtime_resume(struct device *dev)
1545{
9f9ac1e8 1546 struct uart_omap_port *up = dev_get_drvdata(dev);
ec3bebc6 1547 struct omap_uart_port_info *pdata = dev->platform_data;
9f9ac1e8 1548
a5f43138 1549 if (up && pdata) {
e5b57c03 1550 u32 loss_cnt = serial_omap_get_context_loss_count(up);
ec3bebc6
G		 1551
1552 if (up->context_loss_cnt != loss_cnt)
1553 serial_omap_restore_context(up);
94734749 1554
2fd14964
G		 1555 up->latency = up->calc_latency;
1556 schedule_work(&up->qos_work);
ec3bebc6 1557 }
9f9ac1e8 1558
b612633b
G		 1559 return 0;
1560}
fcdca757
G		 1561#endif
1562
1563static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1564 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1565 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1566 serial_omap_runtime_resume, NULL)
1567};
1568
d92b0dfc
RN		 1569#if defined(CONFIG_OF)
1570static const struct of_device_id omap_serial_of_match[] = {
1571 { .compatible = "ti,omap2-uart" },
1572 { .compatible = "ti,omap3-uart" },
1573 { .compatible = "ti,omap4-uart" },
1574 {},
1575};
1576MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1577#endif
b612633b
G		 1578
1579static struct platform_driver serial_omap_driver = {
1580 .probe = serial_omap_probe,
6d608ef3 1581 .remove = __devexit_p(serial_omap_remove),
b612633b
G		 1582 .driver = {
1583 .name = DRIVER_NAME,
fcdca757 1584 .pm = &serial_omap_dev_pm_ops,
d92b0dfc 1585 .of_match_table = of_match_ptr(omap_serial_of_match),
b612633b
G		 1586 },
1587};
1588
1589static int __init serial_omap_init(void)
1590{
1591 int ret;
1592
1593 ret = uart_register_driver(&serial_omap_reg);
1594 if (ret != 0)
1595 return ret;
1596 ret = platform_driver_register(&serial_omap_driver);
1597 if (ret != 0)
1598 uart_unregister_driver(&serial_omap_reg);
1599 return ret;
1600}
1601
1602static void __exit serial_omap_exit(void)
1603{
1604 platform_driver_unregister(&serial_omap_driver);
1605 uart_unregister_driver(&serial_omap_reg);
1606}
1607
1608module_init(serial_omap_init);
1609module_exit(serial_omap_exit);
1610
1611MODULE_DESCRIPTION("OMAP High Speed UART driver");
1612MODULE_LICENSE("GPL");
1613MODULE_AUTHOR("Texas Instruments Inc");
Linux kernel - Deliverables
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