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serial: samsung: get fifosize via device tree
[deliverable/linux.git] / drivers / tty / serial / samsung.c
CommitLineData
99edb3d1 1/*
b497549a
BD		 2 * Driver core for Samsung SoC onboard UARTs.
3 *
ccae941e 4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
b497549a
BD		 5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25*/
26
27#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28#define SUPPORT_SYSRQ
29#endif
30
31#include <linux/module.h>
32#include <linux/ioport.h>
33#include <linux/io.h>
34#include <linux/platform_device.h>
35#include <linux/init.h>
36#include <linux/sysrq.h>
37#include <linux/console.h>
38#include <linux/tty.h>
39#include <linux/tty_flip.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
9ee51f01 42#include <linux/serial_s3c.h>
b497549a
BD		 43#include <linux/delay.h>
44#include <linux/clk.h>
30555476 45#include <linux/cpufreq.h>
26c919e1 46#include <linux/of.h>
b497549a
BD		 47
48#include <asm/irq.h>
49
9ee51f01 50#ifdef CONFIG_SAMSUNG_CLOCK
5f5a7a55 51#include <plat/clock.h>
9ee51f01 52#endif
b497549a
BD		 53
54#include "samsung.h"
55
e4ac92df
JP		 56#if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
57 defined(CONFIG_DEBUG_LL) && \
58 !defined(MODULE)
59
60extern void printascii(const char *);
61
62__printf(1, 2)
63static void dbg(const char *fmt, ...)
64{
65 va_list va;
66 char buff[256];
67
68 va_start(va, fmt);
a859c8b2 69 vscnprintf(buff, sizeof(buff), fmt, va);
e4ac92df
JP		 70 va_end(va);
71
72 printascii(buff);
73}
74
75#else
76#define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
77#endif
78
b497549a
BD		 79/* UART name and device definitions */
80
81#define S3C24XX_SERIAL_NAME "ttySAC"
82#define S3C24XX_SERIAL_MAJOR 204
83#define S3C24XX_SERIAL_MINOR 64
84
b497549a
BD		 85/* macros to change one thing to another */
86
87#define tx_enabled(port) ((port)->unused[0])
88#define rx_enabled(port) ((port)->unused[1])
89
25985edc 90/* flag to ignore all characters coming in */
b497549a
BD		 91#define RXSTAT_DUMMY_READ (0x10000000)
92
93static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
94{
95 return container_of(port, struct s3c24xx_uart_port, port);
96}
97
98/* translate a port to the device name */
99
100static inline const char *s3c24xx_serial_portname(struct uart_port *port)
101{
102 return to_platform_device(port->dev)->name;
103}
104
105static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
106{
9303ac15 107 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
b497549a
BD		 108}
109
88bb4ea1
TA		 110/*
111 * s3c64xx and later SoC's include the interrupt mask and status registers in
112 * the controller itself, unlike the s3c24xx SoC's which have these registers
113 * in the interrupt controller. Check if the port type is s3c64xx or higher.
114 */
115static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
116{
117 return to_ourport(port)->info->type == PORT_S3C6400;
118}
119
b497549a
BD		 120static void s3c24xx_serial_rx_enable(struct uart_port *port)
121{
122 unsigned long flags;
123 unsigned int ucon, ufcon;
124 int count = 10000;
125
126 spin_lock_irqsave(&port->lock, flags);
127
128 while (--count && !s3c24xx_serial_txempty_nofifo(port))
129 udelay(100);
130
131 ufcon = rd_regl(port, S3C2410_UFCON);
132 ufcon |= S3C2410_UFCON_RESETRX;
133 wr_regl(port, S3C2410_UFCON, ufcon);
134
135 ucon = rd_regl(port, S3C2410_UCON);
136 ucon |= S3C2410_UCON_RXIRQMODE;
137 wr_regl(port, S3C2410_UCON, ucon);
138
139 rx_enabled(port) = 1;
140 spin_unlock_irqrestore(&port->lock, flags);
141}
142
143static void s3c24xx_serial_rx_disable(struct uart_port *port)
144{
145 unsigned long flags;
146 unsigned int ucon;
147
148 spin_lock_irqsave(&port->lock, flags);
149
150 ucon = rd_regl(port, S3C2410_UCON);
151 ucon &= ~S3C2410_UCON_RXIRQMODE;
152 wr_regl(port, S3C2410_UCON, ucon);
153
154 rx_enabled(port) = 0;
155 spin_unlock_irqrestore(&port->lock, flags);
156}
157
158static void s3c24xx_serial_stop_tx(struct uart_port *port)
159{
b73c289c
BD		 160 struct s3c24xx_uart_port *ourport = to_ourport(port);
161
b497549a 162 if (tx_enabled(port)) {
88bb4ea1
TA		 163 if (s3c24xx_serial_has_interrupt_mask(port))
164 __set_bit(S3C64XX_UINTM_TXD,
165 portaddrl(port, S3C64XX_UINTM));
166 else
167 disable_irq_nosync(ourport->tx_irq);
b497549a
BD		 168 tx_enabled(port) = 0;
169 if (port->flags & UPF_CONS_FLOW)
170 s3c24xx_serial_rx_enable(port);
171 }
172}
173
174static void s3c24xx_serial_start_tx(struct uart_port *port)
175{
b73c289c
BD		 176 struct s3c24xx_uart_port *ourport = to_ourport(port);
177
b497549a
BD		 178 if (!tx_enabled(port)) {
179 if (port->flags & UPF_CONS_FLOW)
180 s3c24xx_serial_rx_disable(port);
181
88bb4ea1
TA		 182 if (s3c24xx_serial_has_interrupt_mask(port))
183 __clear_bit(S3C64XX_UINTM_TXD,
184 portaddrl(port, S3C64XX_UINTM));
185 else
186 enable_irq(ourport->tx_irq);
b497549a
BD		 187 tx_enabled(port) = 1;
188 }
189}
190
b497549a
BD		 191static void s3c24xx_serial_stop_rx(struct uart_port *port)
192{
b73c289c
BD		 193 struct s3c24xx_uart_port *ourport = to_ourport(port);
194
b497549a
BD		 195 if (rx_enabled(port)) {
196 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
88bb4ea1
TA		 197 if (s3c24xx_serial_has_interrupt_mask(port))
198 __set_bit(S3C64XX_UINTM_RXD,
199 portaddrl(port, S3C64XX_UINTM));
200 else
201 disable_irq_nosync(ourport->rx_irq);
b497549a
BD		 202 rx_enabled(port) = 0;
203 }
204}
205
b497549a
BD		 206static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
207{
208 return to_ourport(port)->info;
209}
210
211static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
212{
4d84e970
TA		 213 struct s3c24xx_uart_port *ourport;
214
b497549a
BD		 215 if (port->dev == NULL)
216 return NULL;
217
4d84e970
TA		 218 ourport = container_of(port, struct s3c24xx_uart_port, port);
219 return ourport->cfg;
b497549a
BD		 220}
221
222static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
223 unsigned long ufstat)
224{
225 struct s3c24xx_uart_info *info = ourport->info;
226
227 if (ufstat & info->rx_fifofull)
da121506 228 return ourport->port.fifosize;
b497549a
BD		 229
230 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
231}
232
233
234/* ? - where has parity gone?? */
235#define S3C2410_UERSTAT_PARITY (0x1000)
236
237static irqreturn_t
238s3c24xx_serial_rx_chars(int irq, void *dev_id)
239{
240 struct s3c24xx_uart_port *ourport = dev_id;
241 struct uart_port *port = &ourport->port;
b497549a 242 unsigned int ufcon, ch, flag, ufstat, uerstat;
c15c3747 243 unsigned long flags;
b497549a
BD		 244 int max_count = 64;
245
c15c3747
TA		 246 spin_lock_irqsave(&port->lock, flags);
247
b497549a
BD		 248 while (max_count-- > 0) {
249 ufcon = rd_regl(port, S3C2410_UFCON);
250 ufstat = rd_regl(port, S3C2410_UFSTAT);
251
252 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
253 break;
254
255 uerstat = rd_regl(port, S3C2410_UERSTAT);
256 ch = rd_regb(port, S3C2410_URXH);
257
258 if (port->flags & UPF_CONS_FLOW) {
259 int txe = s3c24xx_serial_txempty_nofifo(port);
260
261 if (rx_enabled(port)) {
262 if (!txe) {
263 rx_enabled(port) = 0;
264 continue;
265 }
266 } else {
267 if (txe) {
268 ufcon |= S3C2410_UFCON_RESETRX;
269 wr_regl(port, S3C2410_UFCON, ufcon);
270 rx_enabled(port) = 1;
f5693ea2
VK		 271 spin_unlock_irqrestore(&port->lock,
272 flags);
b497549a
BD		 273 goto out;
274 }
275 continue;
276 }
277 }
278
279 /* insert the character into the buffer */
280
281 flag = TTY_NORMAL;
282 port->icount.rx++;
283
284 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
285 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
286 ch, uerstat);
287
288 /* check for break */
289 if (uerstat & S3C2410_UERSTAT_BREAK) {
290 dbg("break!\n");
291 port->icount.brk++;
292 if (uart_handle_break(port))
9303ac15 293 goto ignore_char;
b497549a
BD		 294 }
295
296 if (uerstat & S3C2410_UERSTAT_FRAME)
297 port->icount.frame++;
298 if (uerstat & S3C2410_UERSTAT_OVERRUN)
299 port->icount.overrun++;
300
301 uerstat &= port->read_status_mask;
302
303 if (uerstat & S3C2410_UERSTAT_BREAK)
304 flag = TTY_BREAK;
305 else if (uerstat & S3C2410_UERSTAT_PARITY)
306 flag = TTY_PARITY;
307 else if (uerstat & (S3C2410_UERSTAT_FRAME |
308 S3C2410_UERSTAT_OVERRUN))
309 flag = TTY_FRAME;
310 }
311
312 if (uart_handle_sysrq_char(port, ch))
313 goto ignore_char;
314
315 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
316 ch, flag);
317
318 ignore_char:
319 continue;
320 }
f5693ea2
VK		 321
322 spin_unlock_irqrestore(&port->lock, flags);
2e124b4a 323 tty_flip_buffer_push(&port->state->port);
b497549a
BD		 324
325 out:
326 return IRQ_HANDLED;
327}
328
329static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
330{
331 struct s3c24xx_uart_port *ourport = id;
332 struct uart_port *port = &ourport->port;
ebd2c8f6 333 struct circ_buf *xmit = &port->state->xmit;
c15c3747 334 unsigned long flags;
b497549a
BD		 335 int count = 256;
336
c15c3747
TA		 337 spin_lock_irqsave(&port->lock, flags);
338
b497549a
BD		 339 if (port->x_char) {
340 wr_regb(port, S3C2410_UTXH, port->x_char);
341 port->icount.tx++;
342 port->x_char = 0;
343 goto out;
344 }
345
25985edc 346 /* if there isn't anything more to transmit, or the uart is now
b497549a
BD		 347 * stopped, disable the uart and exit
348 */
349
350 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
351 s3c24xx_serial_stop_tx(port);
352 goto out;
353 }
354
355 /* try and drain the buffer... */
356
357 while (!uart_circ_empty(xmit) && count-- > 0) {
358 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
359 break;
360
361 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
362 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
363 port->icount.tx++;
364 }
365
c15c3747
TA		 366 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
367 spin_unlock(&port->lock);
b497549a 368 uart_write_wakeup(port);
c15c3747
TA		 369 spin_lock(&port->lock);
370 }
b497549a
BD		 371
372 if (uart_circ_empty(xmit))
373 s3c24xx_serial_stop_tx(port);
374
375 out:
c15c3747 376 spin_unlock_irqrestore(&port->lock, flags);
b497549a
BD		 377 return IRQ_HANDLED;
378}
379
88bb4ea1
TA		 380/* interrupt handler for s3c64xx and later SoC's.*/
381static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
382{
383 struct s3c24xx_uart_port *ourport = id;
384 struct uart_port *port = &ourport->port;
385 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
88bb4ea1
TA		 386 irqreturn_t ret = IRQ_HANDLED;
387
88bb4ea1
TA		 388 if (pend & S3C64XX_UINTM_RXD_MSK) {
389 ret = s3c24xx_serial_rx_chars(irq, id);
390 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
391 }
392 if (pend & S3C64XX_UINTM_TXD_MSK) {
393 ret = s3c24xx_serial_tx_chars(irq, id);
394 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
395 }
88bb4ea1
TA		 396 return ret;
397}
398
b497549a
BD		 399static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
400{
401 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
402 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
403 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
404
405 if (ufcon & S3C2410_UFCON_FIFOMODE) {
406 if ((ufstat & info->tx_fifomask) != 0 ||
407 (ufstat & info->tx_fifofull))
408 return 0;
409
410 return 1;
411 }
412
413 return s3c24xx_serial_txempty_nofifo(port);
414}
415
416/* no modem control lines */
417static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
418{
419 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
420
421 if (umstat & S3C2410_UMSTAT_CTS)
422 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
423 else
424 return TIOCM_CAR | TIOCM_DSR;
425}
426
427static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
428{
2d1e5a48
JMG		 429 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
430
431 if (mctrl & TIOCM_RTS)
432 umcon |= S3C2410_UMCOM_RTS_LOW;
433 else
434 umcon &= ~S3C2410_UMCOM_RTS_LOW;
435
436 wr_regl(port, S3C2410_UMCON, umcon);
b497549a
BD		 437}
438
439static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
440{
441 unsigned long flags;
442 unsigned int ucon;
443
444 spin_lock_irqsave(&port->lock, flags);
445
446 ucon = rd_regl(port, S3C2410_UCON);
447
448 if (break_state)
449 ucon |= S3C2410_UCON_SBREAK;
450 else
451 ucon &= ~S3C2410_UCON_SBREAK;
452
453 wr_regl(port, S3C2410_UCON, ucon);
454
455 spin_unlock_irqrestore(&port->lock, flags);
456}
457
458static void s3c24xx_serial_shutdown(struct uart_port *port)
459{
460 struct s3c24xx_uart_port *ourport = to_ourport(port);
461
462 if (ourport->tx_claimed) {
88bb4ea1
TA		 463 if (!s3c24xx_serial_has_interrupt_mask(port))
464 free_irq(ourport->tx_irq, ourport);
b497549a
BD		 465 tx_enabled(port) = 0;
466 ourport->tx_claimed = 0;
467 }
468
469 if (ourport->rx_claimed) {
88bb4ea1
TA		 470 if (!s3c24xx_serial_has_interrupt_mask(port))
471 free_irq(ourport->rx_irq, ourport);
b497549a
BD		 472 ourport->rx_claimed = 0;
473 rx_enabled(port) = 0;
474 }
b497549a 475
88bb4ea1
TA		 476 /* Clear pending interrupts and mask all interrupts */
477 if (s3c24xx_serial_has_interrupt_mask(port)) {
b6ad2935
TF		 478 free_irq(port->irq, ourport);
479
88bb4ea1
TA		 480 wr_regl(port, S3C64XX_UINTP, 0xf);
481 wr_regl(port, S3C64XX_UINTM, 0xf);
482 }
483}
b497549a
BD		 484
485static int s3c24xx_serial_startup(struct uart_port *port)
486{
487 struct s3c24xx_uart_port *ourport = to_ourport(port);
488 int ret;
489
e4ac92df
JP		 490 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
491 port, (unsigned long long)port->mapbase, port->membase);
b497549a
BD		 492
493 rx_enabled(port) = 1;
494
b73c289c 495 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
b497549a
BD		 496 s3c24xx_serial_portname(port), ourport);
497
498 if (ret != 0) {
d20925e1 499 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
b497549a
BD		 500 return ret;
501 }
502
503 ourport->rx_claimed = 1;
504
505 dbg("requesting tx irq...\n");
506
507 tx_enabled(port) = 1;
508
b73c289c 509 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
b497549a
BD		 510 s3c24xx_serial_portname(port), ourport);
511
512 if (ret) {
d20925e1 513 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
b497549a
BD		 514 goto err;
515 }
516
517 ourport->tx_claimed = 1;
518
519 dbg("s3c24xx_serial_startup ok\n");
520
521 /* the port reset code should have done the correct
522 * register setup for the port controls */
523
524 return ret;
525
526 err:
527 s3c24xx_serial_shutdown(port);
528 return ret;
529}
530
88bb4ea1
TA		 531static int s3c64xx_serial_startup(struct uart_port *port)
532{
533 struct s3c24xx_uart_port *ourport = to_ourport(port);
534 int ret;
535
e4ac92df
JP		 536 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
537 port, (unsigned long long)port->mapbase, port->membase);
88bb4ea1 538
b6ad2935
TF		 539 wr_regl(port, S3C64XX_UINTM, 0xf);
540
88bb4ea1
TA		 541 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
542 s3c24xx_serial_portname(port), ourport);
543 if (ret) {
d20925e1 544 dev_err(port->dev, "cannot get irq %d\n", port->irq);
88bb4ea1
TA		 545 return ret;
546 }
547
548 /* For compatibility with s3c24xx Soc's */
549 rx_enabled(port) = 1;
550 ourport->rx_claimed = 1;
551 tx_enabled(port) = 0;
552 ourport->tx_claimed = 1;
553
554 /* Enable Rx Interrupt */
555 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
556 dbg("s3c64xx_serial_startup ok\n");
557 return ret;
558}
559
b497549a
BD		 560/* power power management control */
561
562static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
563 unsigned int old)
564{
565 struct s3c24xx_uart_port *ourport = to_ourport(port);
566
30555476
BD		 567 ourport->pm_level = level;
568
b497549a
BD		 569 switch (level) {
570 case 3:
7cd88831 571 if (!IS_ERR(ourport->baudclk))
9484b009 572 clk_disable_unprepare(ourport->baudclk);
b497549a 573
9484b009 574 clk_disable_unprepare(ourport->clk);
b497549a
BD		 575 break;
576
577 case 0:
9484b009 578 clk_prepare_enable(ourport->clk);
b497549a 579
7cd88831 580 if (!IS_ERR(ourport->baudclk))
9484b009 581 clk_prepare_enable(ourport->baudclk);
b497549a
BD		 582
583 break;
584 default:
d20925e1 585 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
b497549a
BD		 586 }
587}
588
589/* baud rate calculation
590 *
591 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
592 * of different sources, including the peripheral clock ("pclk") and an
593 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
594 * with a programmable extra divisor.
595 *
596 * The following code goes through the clock sources, and calculates the
597 * baud clocks (and the resultant actual baud rates) and then tries to
598 * pick the closest one and select that.
599 *
600*/
601
5f5a7a55 602#define MAX_CLK_NAME_LENGTH 15
b497549a 603
5f5a7a55 604static inline int s3c24xx_serial_getsource(struct uart_port *port)
b497549a
BD		 605{
606 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
5f5a7a55 607 unsigned int ucon;
b497549a 608
5f5a7a55
TA		 609 if (info->num_clks == 1)
610 return 0;
b497549a 611
5f5a7a55
TA		 612 ucon = rd_regl(port, S3C2410_UCON);
613 ucon &= info->clksel_mask;
614 return ucon >> info->clksel_shift;
b497549a
BD		 615}
616
5f5a7a55
TA		 617static void s3c24xx_serial_setsource(struct uart_port *port,
618 unsigned int clk_sel)
b497549a 619{
5f5a7a55
TA		 620 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
621 unsigned int ucon;
b497549a 622
5f5a7a55
TA		 623 if (info->num_clks == 1)
624 return;
090f848d 625
5f5a7a55
TA		 626 ucon = rd_regl(port, S3C2410_UCON);
627 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
628 return;
b497549a 629
5f5a7a55
TA		 630 ucon &= ~info->clksel_mask;
631 ucon |= clk_sel << info->clksel_shift;
632 wr_regl(port, S3C2410_UCON, ucon);
b497549a
BD		 633}
634
5f5a7a55
TA		 635static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
636 unsigned int req_baud, struct clk **best_clk,
637 unsigned int *clk_num)
b497549a 638{
5f5a7a55
TA		 639 struct s3c24xx_uart_info *info = ourport->info;
640 struct clk *clk;
641 unsigned long rate;
642 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
643 char clkname[MAX_CLK_NAME_LENGTH];
644 int calc_deviation, deviation = (1 << 30) - 1;
645
5f5a7a55
TA		 646 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
647 ourport->info->def_clk_sel;
648 for (cnt = 0; cnt < info->num_clks; cnt++) {
649 if (!(clk_sel & (1 << cnt)))
650 continue;
651
652 sprintf(clkname, "clk_uart_baud%d", cnt);
653 clk = clk_get(ourport->port.dev, clkname);
7cd88831 654 if (IS_ERR(clk))
5f5a7a55
TA		 655 continue;
656
657 rate = clk_get_rate(clk);
658 if (!rate)
659 continue;
660
661 if (ourport->info->has_divslot) {
662 unsigned long div = rate / req_baud;
663
664 /* The UDIVSLOT register on the newer UARTs allows us to
665 * get a divisor adjustment of 1/16th on the baud clock.
666 *
667 * We don't keep the UDIVSLOT value (the 16ths we
668 * calculated by not multiplying the baud by 16) as it
669 * is easy enough to recalculate.
670 */
671
672 quot = div / 16;
673 baud = rate / div;
674 } else {
675 quot = (rate + (8 * req_baud)) / (16 * req_baud);
676 baud = rate / (quot * 16);
b497549a 677 }
5f5a7a55 678 quot--;
b497549a 679
5f5a7a55
TA		 680 calc_deviation = req_baud - baud;
681 if (calc_deviation < 0)
682 calc_deviation = -calc_deviation;
b497549a 683
5f5a7a55
TA		 684 if (calc_deviation < deviation) {
685 *best_clk = clk;
686 best_quot = quot;
687 *clk_num = cnt;
688 deviation = calc_deviation;
b497549a
BD		 689 }
690 }
691
5f5a7a55 692 return best_quot;
b497549a
BD		 693}
694
090f848d
BD		 695/* udivslot_table[]
696 *
697 * This table takes the fractional value of the baud divisor and gives
698 * the recommended setting for the UDIVSLOT register.
699 */
700static u16 udivslot_table[16] = {
701 [0] = 0x0000,
702 [1] = 0x0080,
703 [2] = 0x0808,
704 [3] = 0x0888,
705 [4] = 0x2222,
706 [5] = 0x4924,
707 [6] = 0x4A52,
708 [7] = 0x54AA,
709 [8] = 0x5555,
710 [9] = 0xD555,
711 [10] = 0xD5D5,
712 [11] = 0xDDD5,
713 [12] = 0xDDDD,
714 [13] = 0xDFDD,
715 [14] = 0xDFDF,
716 [15] = 0xFFDF,
717};
718
b497549a
BD		 719static void s3c24xx_serial_set_termios(struct uart_port *port,
720 struct ktermios *termios,
721 struct ktermios *old)
722{
723 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
724 struct s3c24xx_uart_port *ourport = to_ourport(port);
7cd88831 725 struct clk *clk = ERR_PTR(-EINVAL);
b497549a 726 unsigned long flags;
5f5a7a55 727 unsigned int baud, quot, clk_sel = 0;
b497549a
BD		 728 unsigned int ulcon;
729 unsigned int umcon;
090f848d 730 unsigned int udivslot = 0;
b497549a
BD		 731
732 /*
733 * We don't support modem control lines.
734 */
735 termios->c_cflag &= ~(HUPCL | CMSPAR);
736 termios->c_cflag |= CLOCAL;
737
738 /*
739 * Ask the core to calculate the divisor for us.
740 */
741
742 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
5f5a7a55 743 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
b497549a
BD		 744 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
745 quot = port->custom_divisor;
7cd88831 746 if (IS_ERR(clk))
5f5a7a55 747 return;
b497549a
BD		 748
749 /* check to see if we need to change clock source */
750
5f5a7a55
TA		 751 if (ourport->baudclk != clk) {
752 s3c24xx_serial_setsource(port, clk_sel);
b497549a 753
7cd88831 754 if (!IS_ERR(ourport->baudclk)) {
9484b009 755 clk_disable_unprepare(ourport->baudclk);
7cd88831 756 ourport->baudclk = ERR_PTR(-EINVAL);
b497549a
BD		 757 }
758
9484b009 759 clk_prepare_enable(clk);
b497549a 760
b497549a 761 ourport->baudclk = clk;
30555476 762 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
b497549a
BD		 763 }
764
090f848d
BD		 765 if (ourport->info->has_divslot) {
766 unsigned int div = ourport->baudclk_rate / baud;
767
8b526ae4
JL		 768 if (cfg->has_fracval) {
769 udivslot = (div & 15);
770 dbg("fracval = %04x\n", udivslot);
771 } else {
772 udivslot = udivslot_table[div & 15];
773 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
774 }
090f848d
BD		 775 }
776
b497549a
BD		 777 switch (termios->c_cflag & CSIZE) {
778 case CS5:
779 dbg("config: 5bits/char\n");
780 ulcon = S3C2410_LCON_CS5;
781 break;
782 case CS6:
783 dbg("config: 6bits/char\n");
784 ulcon = S3C2410_LCON_CS6;
785 break;
786 case CS7:
787 dbg("config: 7bits/char\n");
788 ulcon = S3C2410_LCON_CS7;
789 break;
790 case CS8:
791 default:
792 dbg("config: 8bits/char\n");
793 ulcon = S3C2410_LCON_CS8;
794 break;
795 }
796
797 /* preserve original lcon IR settings */
798 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
799
800 if (termios->c_cflag & CSTOPB)
801 ulcon |= S3C2410_LCON_STOPB;
802
b497549a
BD		 803 if (termios->c_cflag & PARENB) {
804 if (termios->c_cflag & PARODD)
805 ulcon |= S3C2410_LCON_PODD;
806 else
807 ulcon |= S3C2410_LCON_PEVEN;
808 } else {
809 ulcon |= S3C2410_LCON_PNONE;
810 }
811
812 spin_lock_irqsave(&port->lock, flags);
813
090f848d
BD		 814 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
815 ulcon, quot, udivslot);
b497549a
BD		 816
817 wr_regl(port, S3C2410_ULCON, ulcon);
818 wr_regl(port, S3C2410_UBRDIV, quot);
2d1e5a48
JMG		 819
820 umcon = rd_regl(port, S3C2410_UMCON);
821 if (termios->c_cflag & CRTSCTS) {
822 umcon |= S3C2410_UMCOM_AFC;
823 /* Disable RTS when RX FIFO contains 63 bytes */
824 umcon &= ~S3C2412_UMCON_AFC_8;
825 } else {
826 umcon &= ~S3C2410_UMCOM_AFC;
827 }
b497549a
BD		 828 wr_regl(port, S3C2410_UMCON, umcon);
829
090f848d
BD		 830 if (ourport->info->has_divslot)
831 wr_regl(port, S3C2443_DIVSLOT, udivslot);
832
b497549a
BD		 833 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
834 rd_regl(port, S3C2410_ULCON),
835 rd_regl(port, S3C2410_UCON),
836 rd_regl(port, S3C2410_UFCON));
837
838 /*
839 * Update the per-port timeout.
840 */
841 uart_update_timeout(port, termios->c_cflag, baud);
842
843 /*
844 * Which character status flags are we interested in?
845 */
846 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
847 if (termios->c_iflag & INPCK)
848 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
849
850 /*
851 * Which character status flags should we ignore?
852 */
853 port->ignore_status_mask = 0;
854 if (termios->c_iflag & IGNPAR)
855 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
856 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
857 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
858
859 /*
860 * Ignore all characters if CREAD is not set.
861 */
862 if ((termios->c_cflag & CREAD) == 0)
863 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
864
865 spin_unlock_irqrestore(&port->lock, flags);
866}
867
868static const char *s3c24xx_serial_type(struct uart_port *port)
869{
870 switch (port->type) {
871 case PORT_S3C2410:
872 return "S3C2410";
873 case PORT_S3C2440:
874 return "S3C2440";
875 case PORT_S3C2412:
876 return "S3C2412";
b690ace5
BD		 877 case PORT_S3C6400:
878 return "S3C6400/10";
b497549a
BD		 879 default:
880 return NULL;
881 }
882}
883
884#define MAP_SIZE (0x100)
885
886static void s3c24xx_serial_release_port(struct uart_port *port)
887{
888 release_mem_region(port->mapbase, MAP_SIZE);
889}
890
891static int s3c24xx_serial_request_port(struct uart_port *port)
892{
893 const char *name = s3c24xx_serial_portname(port);
894 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
895}
896
897static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
898{
899 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
900
901 if (flags & UART_CONFIG_TYPE &&
902 s3c24xx_serial_request_port(port) == 0)
903 port->type = info->type;
904}
905
906/*
907 * verify the new serial_struct (for TIOCSSERIAL).
908 */
909static int
910s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
911{
912 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
913
914 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
915 return -EINVAL;
916
917 return 0;
918}
919
920
921#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
922
923static struct console s3c24xx_serial_console;
924
93b5c032
JP		 925static int __init s3c24xx_serial_console_init(void)
926{
927 register_console(&s3c24xx_serial_console);
928 return 0;
929}
930console_initcall(s3c24xx_serial_console_init);
931
b497549a
BD		 932#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
933#else
934#define S3C24XX_SERIAL_CONSOLE NULL
935#endif
936
84f57d9e 937#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 938static int s3c24xx_serial_get_poll_char(struct uart_port *port);
939static void s3c24xx_serial_put_poll_char(struct uart_port *port,
940 unsigned char c);
941#endif
942
b497549a
BD		 943static struct uart_ops s3c24xx_serial_ops = {
944 .pm = s3c24xx_serial_pm,
945 .tx_empty = s3c24xx_serial_tx_empty,
946 .get_mctrl = s3c24xx_serial_get_mctrl,
947 .set_mctrl = s3c24xx_serial_set_mctrl,
948 .stop_tx = s3c24xx_serial_stop_tx,
949 .start_tx = s3c24xx_serial_start_tx,
950 .stop_rx = s3c24xx_serial_stop_rx,
b497549a
BD		 951 .break_ctl = s3c24xx_serial_break_ctl,
952 .startup = s3c24xx_serial_startup,
953 .shutdown = s3c24xx_serial_shutdown,
954 .set_termios = s3c24xx_serial_set_termios,
955 .type = s3c24xx_serial_type,
956 .release_port = s3c24xx_serial_release_port,
957 .request_port = s3c24xx_serial_request_port,
958 .config_port = s3c24xx_serial_config_port,
959 .verify_port = s3c24xx_serial_verify_port,
84f57d9e 960#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 961 .poll_get_char = s3c24xx_serial_get_poll_char,
962 .poll_put_char = s3c24xx_serial_put_poll_char,
963#endif
b497549a
BD		 964};
965
b497549a
BD		 966static struct uart_driver s3c24xx_uart_drv = {
967 .owner = THIS_MODULE,
2cf0c58e 968 .driver_name = "s3c2410_serial",
bdd4915a 969 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
b497549a 970 .cons = S3C24XX_SERIAL_CONSOLE,
2cf0c58e 971 .dev_name = S3C24XX_SERIAL_NAME,
b497549a
BD		 972 .major = S3C24XX_SERIAL_MAJOR,
973 .minor = S3C24XX_SERIAL_MINOR,
974};
975
03d5e77b 976static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
b497549a
BD		 977 [0] = {
978 .port = {
979 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
980 .iotype = UPIO_MEM,
b497549a
BD		 981 .uartclk = 0,
982 .fifosize = 16,
983 .ops = &s3c24xx_serial_ops,
984 .flags = UPF_BOOT_AUTOCONF,
985 .line = 0,
986 }
987 },
988 [1] = {
989 .port = {
990 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
991 .iotype = UPIO_MEM,
b497549a
BD		 992 .uartclk = 0,
993 .fifosize = 16,
994 .ops = &s3c24xx_serial_ops,
995 .flags = UPF_BOOT_AUTOCONF,
996 .line = 1,
997 }
998 },
03d5e77b 999#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
b497549a
BD		 1000
1001 [2] = {
1002 .port = {
1003 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
1004 .iotype = UPIO_MEM,
b497549a
BD		 1005 .uartclk = 0,
1006 .fifosize = 16,
1007 .ops = &s3c24xx_serial_ops,
1008 .flags = UPF_BOOT_AUTOCONF,
1009 .line = 2,
1010 }
03d5e77b
BD		 1011 },
1012#endif
1013#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1014 [3] = {
1015 .port = {
1016 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
1017 .iotype = UPIO_MEM,
03d5e77b
BD		 1018 .uartclk = 0,
1019 .fifosize = 16,
1020 .ops = &s3c24xx_serial_ops,
1021 .flags = UPF_BOOT_AUTOCONF,
1022 .line = 3,
1023 }
b497549a
BD		 1024 }
1025#endif
1026};
1027
1028/* s3c24xx_serial_resetport
1029 *
0dfb3b41 1030 * reset the fifos and other the settings.
b497549a
BD		 1031*/
1032
0dfb3b41
TA		 1033static void s3c24xx_serial_resetport(struct uart_port *port,
1034 struct s3c2410_uartcfg *cfg)
b497549a
BD		 1035{
1036 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
0dfb3b41
TA		 1037 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1038 unsigned int ucon_mask;
b497549a 1039
0dfb3b41
TA		 1040 ucon_mask = info->clksel_mask;
1041 if (info->type == PORT_S3C2440)
1042 ucon_mask |= S3C2440_UCON0_DIVMASK;
1043
1044 ucon &= ucon_mask;
1045 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1046
1047 /* reset both fifos */
1048 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1049 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1050
1051 /* some delay is required after fifo reset */
1052 udelay(1);
b497549a
BD		 1053}
1054
30555476
BD		 1055
1056#ifdef CONFIG_CPU_FREQ
1057
1058static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1059 unsigned long val, void *data)
1060{
1061 struct s3c24xx_uart_port *port;
1062 struct uart_port *uport;
1063
1064 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1065 uport = &port->port;
1066
1067 /* check to see if port is enabled */
1068
1069 if (port->pm_level != 0)
1070 return 0;
1071
1072 /* try and work out if the baudrate is changing, we can detect
1073 * a change in rate, but we do not have support for detecting
1074 * a disturbance in the clock-rate over the change.
1075 */
1076
25f04ad4 1077 if (IS_ERR(port->baudclk))
30555476
BD		 1078 goto exit;
1079
25f04ad4 1080 if (port->baudclk_rate == clk_get_rate(port->baudclk))
30555476
BD		 1081 goto exit;
1082
1083 if (val == CPUFREQ_PRECHANGE) {
1084 /* we should really shut the port down whilst the
1085 * frequency change is in progress. */
1086
1087 } else if (val == CPUFREQ_POSTCHANGE) {
1088 struct ktermios *termios;
1089 struct tty_struct *tty;
1090
ebd2c8f6 1091 if (uport->state == NULL)
30555476 1092 goto exit;
30555476 1093
ebd2c8f6 1094 tty = uport->state->port.tty;
30555476 1095
7de40c21 1096 if (tty == NULL)
30555476 1097 goto exit;
30555476 1098
adc8d746 1099 termios = &tty->termios;
30555476
BD		 1100
1101 if (termios == NULL) {
d20925e1 1102 dev_warn(uport->dev, "%s: no termios?\n", __func__);
30555476
BD		 1103 goto exit;
1104 }
1105
1106 s3c24xx_serial_set_termios(uport, termios, NULL);
1107 }
1108
1109 exit:
1110 return 0;
1111}
1112
1113static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1114{
1115 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1116
1117 return cpufreq_register_notifier(&port->freq_transition,
1118 CPUFREQ_TRANSITION_NOTIFIER);
1119}
1120
1121static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1122{
1123 cpufreq_unregister_notifier(&port->freq_transition,
1124 CPUFREQ_TRANSITION_NOTIFIER);
1125}
1126
1127#else
1128static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1129{
1130 return 0;
1131}
1132
1133static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1134{
1135}
1136#endif
1137
b497549a
BD		 1138/* s3c24xx_serial_init_port
1139 *
1140 * initialise a single serial port from the platform device given
1141 */
1142
1143static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
b497549a
BD		 1144 struct platform_device *platdev)
1145{
1146 struct uart_port *port = &ourport->port;
da121506 1147 struct s3c2410_uartcfg *cfg = ourport->cfg;
b497549a
BD		 1148 struct resource *res;
1149 int ret;
1150
1151 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1152
1153 if (platdev == NULL)
1154 return -ENODEV;
1155
b497549a
BD		 1156 if (port->mapbase != 0)
1157 return 0;
1158
b497549a
BD		 1159 /* setup info for port */
1160 port->dev = &platdev->dev;
b497549a 1161
88bb4ea1
TA		 1162 /* Startup sequence is different for s3c64xx and higher SoC's */
1163 if (s3c24xx_serial_has_interrupt_mask(port))
1164 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1165
b497549a
BD		 1166 port->uartclk = 1;
1167
1168 if (cfg->uart_flags & UPF_CONS_FLOW) {
1169 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1170 port->flags |= UPF_CONS_FLOW;
1171 }
1172
1173 /* sort our the physical and virtual addresses for each UART */
1174
1175 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1176 if (res == NULL) {
d20925e1 1177 dev_err(port->dev, "failed to find memory resource for uart\n");
b497549a
BD		 1178 return -EINVAL;
1179 }
1180
e4ac92df 1181 dbg("resource %pR)\n", res);
b497549a 1182
41147bfd
TA		 1183 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1184 if (!port->membase) {
1185 dev_err(port->dev, "failed to remap controller address\n");
1186 return -EBUSY;
1187 }
1188
b690ace5 1189 port->mapbase = res->start;
b497549a
BD		 1190 ret = platform_get_irq(platdev, 0);
1191 if (ret < 0)
1192 port->irq = 0;
b73c289c 1193 else {
b497549a 1194 port->irq = ret;
b73c289c
BD		 1195 ourport->rx_irq = ret;
1196 ourport->tx_irq = ret + 1;
1197 }
9303ac15 1198
b73c289c
BD		 1199 ret = platform_get_irq(platdev, 1);
1200 if (ret > 0)
1201 ourport->tx_irq = ret;
b497549a
BD		 1202
1203 ourport->clk = clk_get(&platdev->dev, "uart");
60e93575
CK		 1204 if (IS_ERR(ourport->clk)) {
1205 pr_err("%s: Controller clock not found\n",
1206 dev_name(&platdev->dev));
1207 return PTR_ERR(ourport->clk);
1208 }
1209
1210 ret = clk_prepare_enable(ourport->clk);
1211 if (ret) {
1212 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1213 clk_put(ourport->clk);
1214 return ret;
1215 }
b497549a 1216
88bb4ea1
TA		 1217 /* Keep all interrupts masked and cleared */
1218 if (s3c24xx_serial_has_interrupt_mask(port)) {
1219 wr_regl(port, S3C64XX_UINTM, 0xf);
1220 wr_regl(port, S3C64XX_UINTP, 0xf);
1221 wr_regl(port, S3C64XX_UINTSP, 0xf);
1222 }
1223
1ff5b64d
FE		 1224 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1225 &port->mapbase, port->membase, port->irq,
b73c289c 1226 ourport->rx_irq, ourport->tx_irq, port->uartclk);
b497549a
BD		 1227
1228 /* reset the fifos (and setup the uart) */
1229 s3c24xx_serial_resetport(port, cfg);
1230 return 0;
1231}
1232
17efd2b7 1233#ifdef CONFIG_SAMSUNG_CLOCK
b497549a
BD		 1234static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1235 struct device_attribute *attr,
1236 char *buf)
1237{
1238 struct uart_port *port = s3c24xx_dev_to_port(dev);
1239 struct s3c24xx_uart_port *ourport = to_ourport(port);
1240
7cd88831
KK		 1241 if (IS_ERR(ourport->baudclk))
1242 return -EINVAL;
1243
7b15e1d9
KP		 1244 return snprintf(buf, PAGE_SIZE, "* %s\n",
1245 ourport->baudclk->name ?: "(null)");
b497549a
BD		 1246}
1247
1248static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
17efd2b7 1249#endif
26c919e1 1250
b497549a
BD		 1251/* Device driver serial port probe */
1252
26c919e1 1253static const struct of_device_id s3c24xx_uart_dt_match[];
b497549a
BD		 1254static int probe_index;
1255
26c919e1
TA		 1256static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1257 struct platform_device *pdev)
1258{
1259#ifdef CONFIG_OF
1260 if (pdev->dev.of_node) {
1261 const struct of_device_id *match;
1262 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1263 return (struct s3c24xx_serial_drv_data *)match->data;
1264 }
1265#endif
1266 return (struct s3c24xx_serial_drv_data *)
1267 platform_get_device_id(pdev)->driver_data;
1268}
1269
da121506 1270static int s3c24xx_serial_probe(struct platform_device *pdev)
b497549a
BD		 1271{
1272 struct s3c24xx_uart_port *ourport;
13a9f6c6 1273 int index = probe_index;
b497549a
BD		 1274 int ret;
1275
13a9f6c6
TF		 1276 if (pdev->dev.of_node) {
1277 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1278 if (ret >= 0)
1279 index = ret;
1280 }
1281
1282 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
b497549a 1283
13a9f6c6 1284 ourport = &s3c24xx_serial_ports[index];
da121506 1285
26c919e1
TA		 1286 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1287 if (!ourport->drv_data) {
1288 dev_err(&pdev->dev, "could not find driver data\n");
1289 return -ENODEV;
1290 }
da121506 1291
7cd88831 1292 ourport->baudclk = ERR_PTR(-EINVAL);
da121506 1293 ourport->info = ourport->drv_data->info;
574de559 1294 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
d4aab206 1295 dev_get_platdata(&pdev->dev) :
da121506
TA		 1296 ourport->drv_data->def_cfg;
1297
135f07c3
NKC		 1298 if (pdev->dev.of_node)
1299 of_property_read_u32(pdev->dev.of_node,
1300 "samsung,uart-fifosize", &ourport->port.fifosize);
1301
1302 if (!ourport->port.fifosize) {
1303 ourport->port.fifosize = (ourport->info->fifosize) ?
1304 ourport->info->fifosize :
1305 ourport->drv_data->fifosize[index];
1306 }
da121506 1307
b497549a
BD		 1308 probe_index++;
1309
1310 dbg("%s: initialising port %p...\n", __func__, ourport);
1311
da121506 1312 ret = s3c24xx_serial_init_port(ourport, pdev);
b497549a 1313 if (ret < 0)
8ad711a9 1314 return ret;
b497549a 1315
6f134c3c
TB		 1316 if (!s3c24xx_uart_drv.state) {
1317 ret = uart_register_driver(&s3c24xx_uart_drv);
1318 if (ret < 0) {
1319 pr_err("Failed to register Samsung UART driver\n");
1320 return ret;
1321 }
1322 }
1323
b497549a
BD		 1324 dbg("%s: adding port\n", __func__);
1325 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
da121506 1326 platform_set_drvdata(pdev, &ourport->port);
b497549a 1327
0da3336f
HS		 1328 /*
1329 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1330 * so that a potential re-enablement through the pm-callback overlaps
1331 * and keeps the clock enabled in this case.
1332 */
1333 clk_disable_unprepare(ourport->clk);
1334
17efd2b7 1335#ifdef CONFIG_SAMSUNG_CLOCK
da121506 1336 ret = device_create_file(&pdev->dev, &dev_attr_clock_source);
b497549a 1337 if (ret < 0)
da121506 1338 dev_err(&pdev->dev, "failed to add clock source attr.\n");
17efd2b7 1339#endif
b497549a 1340
30555476
BD		 1341 ret = s3c24xx_serial_cpufreq_register(ourport);
1342 if (ret < 0)
da121506 1343 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
30555476 1344
b497549a 1345 return 0;
b497549a
BD		 1346}
1347
ae8d8a14 1348static int s3c24xx_serial_remove(struct platform_device *dev)
b497549a
BD		 1349{
1350 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1351
1352 if (port) {
30555476 1353 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
17efd2b7 1354#ifdef CONFIG_SAMSUNG_CLOCK
b497549a 1355 device_remove_file(&dev->dev, &dev_attr_clock_source);
17efd2b7 1356#endif
b497549a
BD		 1357 uart_remove_one_port(&s3c24xx_uart_drv, port);
1358 }
1359
6f134c3c
TB		 1360 uart_unregister_driver(&s3c24xx_uart_drv);
1361
b497549a
BD		 1362 return 0;
1363}
1364
b497549a 1365/* UART power management code */
aef7fe52
MH		 1366#ifdef CONFIG_PM_SLEEP
1367static int s3c24xx_serial_suspend(struct device *dev)
b497549a 1368{
aef7fe52 1369 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1370
1371 if (port)
1372 uart_suspend_port(&s3c24xx_uart_drv, port);
1373
1374 return 0;
1375}
1376
aef7fe52 1377static int s3c24xx_serial_resume(struct device *dev)
b497549a 1378{
aef7fe52 1379 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1380 struct s3c24xx_uart_port *ourport = to_ourport(port);
1381
1382 if (port) {
9484b009 1383 clk_prepare_enable(ourport->clk);
b497549a 1384 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
9484b009 1385 clk_disable_unprepare(ourport->clk);
b497549a
BD		 1386
1387 uart_resume_port(&s3c24xx_uart_drv, port);
1388 }
1389
1390 return 0;
1391}
aef7fe52 1392
d09a7308
MS		 1393static int s3c24xx_serial_resume_noirq(struct device *dev)
1394{
1395 struct uart_port *port = s3c24xx_dev_to_port(dev);
1396
1397 if (port) {
1398 /* restore IRQ mask */
1399 if (s3c24xx_serial_has_interrupt_mask(port)) {
1400 unsigned int uintm = 0xf;
1401 if (tx_enabled(port))
1402 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1403 if (rx_enabled(port))
1404 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1405 wr_regl(port, S3C64XX_UINTM, uintm);
1406 }
1407 }
1408
1409 return 0;
1410}
1411
aef7fe52
MH		 1412static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1413 .suspend = s3c24xx_serial_suspend,
1414 .resume = s3c24xx_serial_resume,
d09a7308 1415 .resume_noirq = s3c24xx_serial_resume_noirq,
aef7fe52 1416};
b882fc1b
KK		 1417#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1418
aef7fe52 1419#else /* !CONFIG_PM_SLEEP */
b882fc1b
KK		 1420
1421#define SERIAL_SAMSUNG_PM_OPS NULL
aef7fe52 1422#endif /* CONFIG_PM_SLEEP */
b497549a 1423
b497549a
BD		 1424/* Console code */
1425
1426#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1427
1428static struct uart_port *cons_uart;
1429
1430static int
1431s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1432{
1433 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1434 unsigned long ufstat, utrstat;
1435
1436 if (ufcon & S3C2410_UFCON_FIFOMODE) {
9ddc5b6f 1437 /* fifo mode - check amount of data in fifo registers... */
b497549a
BD		 1438
1439 ufstat = rd_regl(port, S3C2410_UFSTAT);
1440 return (ufstat & info->tx_fifofull) ? 0 : 1;
1441 }
1442
1443 /* in non-fifo mode, we go and use the tx buffer empty */
1444
1445 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1446 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1447}
1448
38adbc54
MS		 1449static bool
1450s3c24xx_port_configured(unsigned int ucon)
1451{
1452 /* consider the serial port configured if the tx/rx mode set */
1453 return (ucon & 0xf) != 0;
1454}
1455
93b5c032
JP		 1456#ifdef CONFIG_CONSOLE_POLL
1457/*
1458 * Console polling routines for writing and reading from the uart while
1459 * in an interrupt or debug context.
1460 */
1461
1462static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1463{
1464 struct s3c24xx_uart_port *ourport = to_ourport(port);
1465 unsigned int ufstat;
1466
1467 ufstat = rd_regl(port, S3C2410_UFSTAT);
1468 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1469 return NO_POLL_CHAR;
1470
1471 return rd_regb(port, S3C2410_URXH);
1472}
1473
1474static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1475 unsigned char c)
1476{
bb7f09ba
DA		 1477 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
1478 unsigned int ucon = rd_regl(port, S3C2410_UCON);
38adbc54
MS		 1479
1480 /* not possible to xmit on unconfigured port */
1481 if (!s3c24xx_port_configured(ucon))
1482 return;
93b5c032
JP		 1483
1484 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1485 cpu_relax();
bb7f09ba 1486 wr_regb(port, S3C2410_UTXH, c);
93b5c032
JP		 1487}
1488
1489#endif /* CONFIG_CONSOLE_POLL */
1490
b497549a
BD		 1491static void
1492s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1493{
bb7f09ba 1494 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
38adbc54 1495
b497549a 1496 while (!s3c24xx_serial_console_txrdy(port, ufcon))
f94b0572 1497 cpu_relax();
bb7f09ba 1498 wr_regb(port, S3C2410_UTXH, ch);
b497549a
BD		 1499}
1500
1501static void
1502s3c24xx_serial_console_write(struct console *co, const char *s,
1503 unsigned int count)
1504{
ab88c8dc
DA		 1505 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1506
1507 /* not possible to xmit on unconfigured port */
1508 if (!s3c24xx_port_configured(ucon))
1509 return;
1510
b497549a
BD		 1511 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1512}
1513
1514static void __init
1515s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1516 int *parity, int *bits)
1517{
b497549a
BD		 1518 struct clk *clk;
1519 unsigned int ulcon;
1520 unsigned int ucon;
1521 unsigned int ubrdiv;
1522 unsigned long rate;
5f5a7a55
TA		 1523 unsigned int clk_sel;
1524 char clk_name[MAX_CLK_NAME_LENGTH];
b497549a
BD		 1525
1526 ulcon = rd_regl(port, S3C2410_ULCON);
1527 ucon = rd_regl(port, S3C2410_UCON);
1528 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1529
1530 dbg("s3c24xx_serial_get_options: port=%p\n"
1531 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1532 port, ulcon, ucon, ubrdiv);
1533
38adbc54 1534 if (s3c24xx_port_configured(ucon)) {
b497549a
BD		 1535 switch (ulcon & S3C2410_LCON_CSMASK) {
1536 case S3C2410_LCON_CS5:
1537 *bits = 5;
1538 break;
1539 case S3C2410_LCON_CS6:
1540 *bits = 6;
1541 break;
1542 case S3C2410_LCON_CS7:
1543 *bits = 7;
1544 break;
1545 default:
1546 case S3C2410_LCON_CS8:
1547 *bits = 8;
1548 break;
1549 }
1550
1551 switch (ulcon & S3C2410_LCON_PMASK) {
1552 case S3C2410_LCON_PEVEN:
1553 *parity = 'e';
1554 break;
1555
1556 case S3C2410_LCON_PODD:
1557 *parity = 'o';
1558 break;
1559
1560 case S3C2410_LCON_PNONE:
1561 default:
1562 *parity = 'n';
1563 }
1564
1565 /* now calculate the baud rate */
1566
5f5a7a55
TA		 1567 clk_sel = s3c24xx_serial_getsource(port);
1568 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
b497549a 1569
5f5a7a55 1570 clk = clk_get(port->dev, clk_name);
7cd88831 1571 if (!IS_ERR(clk))
5f5a7a55 1572 rate = clk_get_rate(clk);
b497549a
BD		 1573 else
1574 rate = 1;
1575
b497549a
BD		 1576 *baud = rate / (16 * (ubrdiv + 1));
1577 dbg("calculated baud %d\n", *baud);
1578 }
1579
1580}
1581
b497549a
BD		 1582static int __init
1583s3c24xx_serial_console_setup(struct console *co, char *options)
1584{
1585 struct uart_port *port;
1586 int baud = 9600;
1587 int bits = 8;
1588 int parity = 'n';
1589 int flow = 'n';
1590
1591 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1592 co, co->index, options);
1593
1594 /* is this a valid port */
1595
03d5e77b 1596 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
b497549a
BD		 1597 co->index = 0;
1598
1599 port = &s3c24xx_serial_ports[co->index].port;
1600
1601 /* is the port configured? */
1602
ee430f16
TA		 1603 if (port->mapbase == 0x0)
1604 return -ENODEV;
b497549a
BD		 1605
1606 cons_uart = port;
1607
1608 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1609
1610 /*
1611 * Check whether an invalid uart number has been specified, and
1612 * if so, search for the first available port that does have
1613 * console support.
1614 */
1615 if (options)
1616 uart_parse_options(options, &baud, &parity, &bits, &flow);
1617 else
1618 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1619
1620 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1621
1622 return uart_set_options(port, co, baud, parity, bits, flow);
1623}
1624
b497549a
BD		 1625static struct console s3c24xx_serial_console = {
1626 .name = S3C24XX_SERIAL_NAME,
1627 .device = uart_console_device,
1628 .flags = CON_PRINTBUFFER,
1629 .index = -1,
1630 .write = s3c24xx_serial_console_write,
5822a5df
TA		 1631 .setup = s3c24xx_serial_console_setup,
1632 .data = &s3c24xx_uart_drv,
b497549a 1633};
da121506
TA		 1634#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1635
1636#ifdef CONFIG_CPU_S3C2410
1637static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1638 .info = &(struct s3c24xx_uart_info) {
1639 .name = "Samsung S3C2410 UART",
1640 .type = PORT_S3C2410,
1641 .fifosize = 16,
1642 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1643 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1644 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1645 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1646 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1647 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1648 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1649 .num_clks = 2,
1650 .clksel_mask = S3C2410_UCON_CLKMASK,
1651 .clksel_shift = S3C2410_UCON_CLKSHIFT,
1652 },
1653 .def_cfg = &(struct s3c2410_uartcfg) {
1654 .ucon = S3C2410_UCON_DEFAULT,
1655 .ufcon = S3C2410_UFCON_DEFAULT,
1656 },
1657};
1658#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1659#else
1660#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1661#endif
b497549a 1662
da121506
TA		 1663#ifdef CONFIG_CPU_S3C2412
1664static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1665 .info = &(struct s3c24xx_uart_info) {
1666 .name = "Samsung S3C2412 UART",
1667 .type = PORT_S3C2412,
1668 .fifosize = 64,
1669 .has_divslot = 1,
1670 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1671 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1672 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1673 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1674 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1675 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1676 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1677 .num_clks = 4,
1678 .clksel_mask = S3C2412_UCON_CLKMASK,
1679 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1680 },
1681 .def_cfg = &(struct s3c2410_uartcfg) {
1682 .ucon = S3C2410_UCON_DEFAULT,
1683 .ufcon = S3C2410_UFCON_DEFAULT,
1684 },
1685};
1686#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1687#else
1688#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1689#endif
b497549a 1690
da121506 1691#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
b26469a8 1692 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
da121506
TA		 1693static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1694 .info = &(struct s3c24xx_uart_info) {
1695 .name = "Samsung S3C2440 UART",
1696 .type = PORT_S3C2440,
1697 .fifosize = 64,
1698 .has_divslot = 1,
1699 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1700 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1701 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1702 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1703 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1704 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1705 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1706 .num_clks = 4,
1707 .clksel_mask = S3C2412_UCON_CLKMASK,
1708 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1709 },
1710 .def_cfg = &(struct s3c2410_uartcfg) {
1711 .ucon = S3C2410_UCON_DEFAULT,
1712 .ufcon = S3C2410_UFCON_DEFAULT,
1713 },
1714};
1715#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1716#else
1717#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1718#endif
b497549a 1719
953b53a7 1720#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
da121506
TA		 1721static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1722 .info = &(struct s3c24xx_uart_info) {
1723 .name = "Samsung S3C6400 UART",
1724 .type = PORT_S3C6400,
1725 .fifosize = 64,
1726 .has_divslot = 1,
1727 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1728 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1729 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1730 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1731 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1732 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1733 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1734 .num_clks = 4,
1735 .clksel_mask = S3C6400_UCON_CLKMASK,
1736 .clksel_shift = S3C6400_UCON_CLKSHIFT,
1737 },
1738 .def_cfg = &(struct s3c2410_uartcfg) {
1739 .ucon = S3C2410_UCON_DEFAULT,
1740 .ufcon = S3C2410_UFCON_DEFAULT,
1741 },
1742};
1743#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1744#else
1745#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1746#endif
b497549a 1747
da121506
TA		 1748#ifdef CONFIG_CPU_S5PV210
1749static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1750 .info = &(struct s3c24xx_uart_info) {
1751 .name = "Samsung S5PV210 UART",
1752 .type = PORT_S3C6400,
1753 .has_divslot = 1,
1754 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1755 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1756 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1757 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1758 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1759 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1760 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1761 .num_clks = 2,
1762 .clksel_mask = S5PV210_UCON_CLKMASK,
1763 .clksel_shift = S5PV210_UCON_CLKSHIFT,
1764 },
1765 .def_cfg = &(struct s3c2410_uartcfg) {
1766 .ucon = S5PV210_UCON_DEFAULT,
1767 .ufcon = S5PV210_UFCON_DEFAULT,
1768 },
1769 .fifosize = { 256, 64, 16, 16 },
1770};
1771#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1772#else
1773#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1774#endif
b497549a 1775
33f88136 1776#if defined(CONFIG_ARCH_EXYNOS)
da121506
TA		 1777static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1778 .info = &(struct s3c24xx_uart_info) {
1779 .name = "Samsung Exynos4 UART",
1780 .type = PORT_S3C6400,
1781 .has_divslot = 1,
1782 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1783 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1784 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1785 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1786 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1787 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1788 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1789 .num_clks = 1,
1790 .clksel_mask = 0,
1791 .clksel_shift = 0,
1792 },
1793 .def_cfg = &(struct s3c2410_uartcfg) {
1794 .ucon = S5PV210_UCON_DEFAULT,
1795 .ufcon = S5PV210_UFCON_DEFAULT,
1796 .has_fracval = 1,
1797 },
1798 .fifosize = { 256, 64, 16, 16 },
1799};
1800#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1801#else
1802#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1803#endif
b497549a 1804
da121506
TA		 1805static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1806 {
1807 .name = "s3c2410-uart",
1808 .driver_data = S3C2410_SERIAL_DRV_DATA,
1809 }, {
1810 .name = "s3c2412-uart",
1811 .driver_data = S3C2412_SERIAL_DRV_DATA,
1812 }, {
1813 .name = "s3c2440-uart",
1814 .driver_data = S3C2440_SERIAL_DRV_DATA,
1815 }, {
1816 .name = "s3c6400-uart",
1817 .driver_data = S3C6400_SERIAL_DRV_DATA,
1818 }, {
1819 .name = "s5pv210-uart",
1820 .driver_data = S5PV210_SERIAL_DRV_DATA,
1821 }, {
1822 .name = "exynos4210-uart",
1823 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1824 },
1825 { },
1826};
1827MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1828
26c919e1
TA		 1829#ifdef CONFIG_OF
1830static const struct of_device_id s3c24xx_uart_dt_match[] = {
666ca0b9
HS		 1831 { .compatible = "samsung,s3c2410-uart",
1832 .data = (void *)S3C2410_SERIAL_DRV_DATA },
1833 { .compatible = "samsung,s3c2412-uart",
1834 .data = (void *)S3C2412_SERIAL_DRV_DATA },
1835 { .compatible = "samsung,s3c2440-uart",
1836 .data = (void *)S3C2440_SERIAL_DRV_DATA },
1837 { .compatible = "samsung,s3c6400-uart",
1838 .data = (void *)S3C6400_SERIAL_DRV_DATA },
1839 { .compatible = "samsung,s5pv210-uart",
1840 .data = (void *)S5PV210_SERIAL_DRV_DATA },
26c919e1 1841 { .compatible = "samsung,exynos4210-uart",
a169a888 1842 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
26c919e1
TA		 1843 {},
1844};
1845MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
26c919e1
TA		 1846#endif
1847
da121506
TA		 1848static struct platform_driver samsung_serial_driver = {
1849 .probe = s3c24xx_serial_probe,
2d47b716 1850 .remove = s3c24xx_serial_remove,
da121506
TA		 1851 .id_table = s3c24xx_serial_driver_ids,
1852 .driver = {
1853 .name = "samsung-uart",
1854 .owner = THIS_MODULE,
1855 .pm = SERIAL_SAMSUNG_PM_OPS,
905f4ba2 1856 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
da121506
TA		 1857 },
1858};
b497549a 1859
6f134c3c 1860module_platform_driver(samsung_serial_driver);
b497549a 1861
da121506 1862MODULE_ALIAS("platform:samsung-uart");
b497549a
BD		 1863MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1864MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1865MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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