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Merge tag 'for-4.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux...
[deliverable/linux.git] / drivers / tty / serial / samsung.c
CommitLineData
99edb3d1 1/*
b497549a
BD		 2 * Driver core for Samsung SoC onboard UARTs.
3 *
ccae941e 4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
b497549a
BD		 5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25*/
26
27#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28#define SUPPORT_SYSRQ
29#endif
30
62c37eed
RB		 31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/slab.h>
b497549a
BD		 34#include <linux/module.h>
35#include <linux/ioport.h>
36#include <linux/io.h>
37#include <linux/platform_device.h>
38#include <linux/init.h>
39#include <linux/sysrq.h>
40#include <linux/console.h>
41#include <linux/tty.h>
42#include <linux/tty_flip.h>
43#include <linux/serial_core.h>
44#include <linux/serial.h>
9ee51f01 45#include <linux/serial_s3c.h>
b497549a
BD		 46#include <linux/delay.h>
47#include <linux/clk.h>
30555476 48#include <linux/cpufreq.h>
26c919e1 49#include <linux/of.h>
b497549a
BD		 50
51#include <asm/irq.h>
52
b497549a
BD		 53#include "samsung.h"
54
e4ac92df
JP		 55#if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
56 defined(CONFIG_DEBUG_LL) && \
57 !defined(MODULE)
58
59extern void printascii(const char *);
60
61__printf(1, 2)
62static void dbg(const char *fmt, ...)
63{
64 va_list va;
65 char buff[256];
66
67 va_start(va, fmt);
a859c8b2 68 vscnprintf(buff, sizeof(buff), fmt, va);
e4ac92df
JP		 69 va_end(va);
70
71 printascii(buff);
72}
73
74#else
75#define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
76#endif
77
b497549a
BD		 78/* UART name and device definitions */
79
80#define S3C24XX_SERIAL_NAME "ttySAC"
81#define S3C24XX_SERIAL_MAJOR 204
82#define S3C24XX_SERIAL_MINOR 64
83
29bef799
RB		 84#define S3C24XX_TX_PIO 1
85#define S3C24XX_TX_DMA 2
b543c301
RB		 86#define S3C24XX_RX_PIO 1
87#define S3C24XX_RX_DMA 2
b497549a
BD		 88/* macros to change one thing to another */
89
90#define tx_enabled(port) ((port)->unused[0])
91#define rx_enabled(port) ((port)->unused[1])
92
25985edc 93/* flag to ignore all characters coming in */
b497549a
BD		 94#define RXSTAT_DUMMY_READ (0x10000000)
95
96static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
97{
98 return container_of(port, struct s3c24xx_uart_port, port);
99}
100
101/* translate a port to the device name */
102
103static inline const char *s3c24xx_serial_portname(struct uart_port *port)
104{
105 return to_platform_device(port->dev)->name;
106}
107
108static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
109{
9303ac15 110 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
b497549a
BD		 111}
112
88bb4ea1
TA		 113/*
114 * s3c64xx and later SoC's include the interrupt mask and status registers in
115 * the controller itself, unlike the s3c24xx SoC's which have these registers
116 * in the interrupt controller. Check if the port type is s3c64xx or higher.
117 */
118static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
119{
120 return to_ourport(port)->info->type == PORT_S3C6400;
121}
122
b497549a
BD		 123static void s3c24xx_serial_rx_enable(struct uart_port *port)
124{
125 unsigned long flags;
126 unsigned int ucon, ufcon;
127 int count = 10000;
128
129 spin_lock_irqsave(&port->lock, flags);
130
131 while (--count && !s3c24xx_serial_txempty_nofifo(port))
132 udelay(100);
133
134 ufcon = rd_regl(port, S3C2410_UFCON);
135 ufcon |= S3C2410_UFCON_RESETRX;
136 wr_regl(port, S3C2410_UFCON, ufcon);
137
138 ucon = rd_regl(port, S3C2410_UCON);
139 ucon |= S3C2410_UCON_RXIRQMODE;
140 wr_regl(port, S3C2410_UCON, ucon);
141
142 rx_enabled(port) = 1;
143 spin_unlock_irqrestore(&port->lock, flags);
144}
145
146static void s3c24xx_serial_rx_disable(struct uart_port *port)
147{
148 unsigned long flags;
149 unsigned int ucon;
150
151 spin_lock_irqsave(&port->lock, flags);
152
153 ucon = rd_regl(port, S3C2410_UCON);
154 ucon &= ~S3C2410_UCON_RXIRQMODE;
155 wr_regl(port, S3C2410_UCON, ucon);
156
157 rx_enabled(port) = 0;
158 spin_unlock_irqrestore(&port->lock, flags);
159}
160
161static void s3c24xx_serial_stop_tx(struct uart_port *port)
162{
b73c289c 163 struct s3c24xx_uart_port *ourport = to_ourport(port);
29bef799
RB		 164 struct s3c24xx_uart_dma *dma = ourport->dma;
165 struct circ_buf *xmit = &port->state->xmit;
166 struct dma_tx_state state;
167 int count;
b73c289c 168
29bef799
RB		 169 if (!tx_enabled(port))
170 return;
171
172 if (s3c24xx_serial_has_interrupt_mask(port))
173 __set_bit(S3C64XX_UINTM_TXD,
174 portaddrl(port, S3C64XX_UINTM));
175 else
176 disable_irq_nosync(ourport->tx_irq);
177
178 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
179 dmaengine_pause(dma->tx_chan);
180 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
181 dmaengine_terminate_all(dma->tx_chan);
182 dma_sync_single_for_cpu(ourport->port.dev,
183 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
184 async_tx_ack(dma->tx_desc);
185 count = dma->tx_bytes_requested - state.residue;
186 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
187 port->icount.tx += count;
b497549a 188 }
29bef799
RB		 189
190 tx_enabled(port) = 0;
191 ourport->tx_in_progress = 0;
192
193 if (port->flags & UPF_CONS_FLOW)
194 s3c24xx_serial_rx_enable(port);
195
196 ourport->tx_mode = 0;
197}
198
199static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
200
201static void s3c24xx_serial_tx_dma_complete(void *args)
202{
203 struct s3c24xx_uart_port *ourport = args;
204 struct uart_port *port = &ourport->port;
205 struct circ_buf *xmit = &port->state->xmit;
206 struct s3c24xx_uart_dma *dma = ourport->dma;
207 struct dma_tx_state state;
208 unsigned long flags;
209 int count;
210
211
212 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
213 count = dma->tx_bytes_requested - state.residue;
214 async_tx_ack(dma->tx_desc);
215
216 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
217 dma->tx_size, DMA_TO_DEVICE);
218
219 spin_lock_irqsave(&port->lock, flags);
220
221 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
222 port->icount.tx += count;
223 ourport->tx_in_progress = 0;
224
225 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
226 uart_write_wakeup(port);
227
228 s3c24xx_serial_start_next_tx(ourport);
229 spin_unlock_irqrestore(&port->lock, flags);
230}
231
232static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
233{
234 struct uart_port *port = &ourport->port;
235 u32 ucon;
236
237 /* Mask Tx interrupt */
238 if (s3c24xx_serial_has_interrupt_mask(port))
239 __set_bit(S3C64XX_UINTM_TXD,
240 portaddrl(port, S3C64XX_UINTM));
241 else
242 disable_irq_nosync(ourport->tx_irq);
243
244 /* Enable tx dma mode */
245 ucon = rd_regl(port, S3C2410_UCON);
246 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
247 ucon |= (dma_get_cache_alignment() >= 16) ?
248 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
249 ucon |= S3C64XX_UCON_TXMODE_DMA;
250 wr_regl(port, S3C2410_UCON, ucon);
251
252 ourport->tx_mode = S3C24XX_TX_DMA;
253}
254
255static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
256{
257 struct uart_port *port = &ourport->port;
258 u32 ucon, ufcon;
259
260 /* Set ufcon txtrig */
261 ourport->tx_in_progress = S3C24XX_TX_PIO;
262 ufcon = rd_regl(port, S3C2410_UFCON);
263 wr_regl(port, S3C2410_UFCON, ufcon);
264
265 /* Enable tx pio mode */
266 ucon = rd_regl(port, S3C2410_UCON);
267 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
268 ucon |= S3C64XX_UCON_TXMODE_CPU;
269 wr_regl(port, S3C2410_UCON, ucon);
270
271 /* Unmask Tx interrupt */
272 if (s3c24xx_serial_has_interrupt_mask(port))
273 __clear_bit(S3C64XX_UINTM_TXD,
274 portaddrl(port, S3C64XX_UINTM));
275 else
276 enable_irq(ourport->tx_irq);
277
278 ourport->tx_mode = S3C24XX_TX_PIO;
279}
280
281static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
282{
283 if (ourport->tx_mode != S3C24XX_TX_PIO)
284 enable_tx_pio(ourport);
b497549a
BD		 285}
286
29bef799
RB		 287static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
288 unsigned int count)
289{
290 struct uart_port *port = &ourport->port;
291 struct circ_buf *xmit = &port->state->xmit;
292 struct s3c24xx_uart_dma *dma = ourport->dma;
293
294
295 if (ourport->tx_mode != S3C24XX_TX_DMA)
296 enable_tx_dma(ourport);
297
298 while (xmit->tail & (dma_get_cache_alignment() - 1)) {
299 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
300 return 0;
301 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
302 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
303 port->icount.tx++;
304 count--;
305 }
306
307 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
308 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
309
310 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
311 dma->tx_size, DMA_TO_DEVICE);
312
313 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
314 dma->tx_transfer_addr, dma->tx_size,
315 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
316 if (!dma->tx_desc) {
317 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
318 return -EIO;
319 }
320
321 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
322 dma->tx_desc->callback_param = ourport;
323 dma->tx_bytes_requested = dma->tx_size;
324
325 ourport->tx_in_progress = S3C24XX_TX_DMA;
326 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
327 dma_async_issue_pending(dma->tx_chan);
328 return 0;
329}
330
331static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
332{
333 struct uart_port *port = &ourport->port;
334 struct circ_buf *xmit = &port->state->xmit;
335 unsigned long count;
336
337 /* Get data size up to the end of buffer */
338 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
339
340 if (!count) {
341 s3c24xx_serial_stop_tx(port);
342 return;
343 }
344
345 if (!ourport->dma || !ourport->dma->tx_chan || count < port->fifosize)
346 s3c24xx_serial_start_tx_pio(ourport);
347 else
348 s3c24xx_serial_start_tx_dma(ourport, count);
349}
350
351void s3c24xx_serial_start_tx(struct uart_port *port)
b497549a 352{
b73c289c 353 struct s3c24xx_uart_port *ourport = to_ourport(port);
29bef799 354 struct circ_buf *xmit = &port->state->xmit;
b73c289c 355
b497549a
BD		 356 if (!tx_enabled(port)) {
357 if (port->flags & UPF_CONS_FLOW)
358 s3c24xx_serial_rx_disable(port);
359
b497549a 360 tx_enabled(port) = 1;
ba019a3e 361 if (!ourport->dma || !ourport->dma->tx_chan)
29bef799 362 s3c24xx_serial_start_tx_pio(ourport);
29bef799
RB		 363 }
364
365 if (ourport->dma && ourport->dma->tx_chan) {
366 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
367 s3c24xx_serial_start_next_tx(ourport);
b497549a
BD		 368 }
369}
370
b543c301
RB		 371static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
372 struct tty_port *tty, int count)
373{
374 struct s3c24xx_uart_dma *dma = ourport->dma;
375 int copied;
376
377 if (!count)
378 return;
379
380 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
381 dma->rx_size, DMA_FROM_DEVICE);
382
383 ourport->port.icount.rx += count;
384 if (!tty) {
385 dev_err(ourport->port.dev, "No tty port\n");
386 return;
387 }
388 copied = tty_insert_flip_string(tty,
389 ((unsigned char *)(ourport->dma->rx_buf)), count);
390 if (copied != count) {
391 WARN_ON(1);
392 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
393 }
394}
395
396static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
397 unsigned long ufstat);
398
399static void uart_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
400{
401 struct uart_port *port = &ourport->port;
402 struct tty_port *tty = &port->state->port;
403 unsigned int ch, ufstat;
404 unsigned int count;
405
406 ufstat = rd_regl(port, S3C2410_UFSTAT);
407 count = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
408
409 if (!count)
410 return;
411
412 while (count-- > 0) {
413 ch = rd_regb(port, S3C2410_URXH);
414
415 ourport->port.icount.rx++;
416 tty_insert_flip_char(tty, ch, TTY_NORMAL);
417 }
418
419 tty_flip_buffer_push(tty);
420}
421
b497549a
BD		 422static void s3c24xx_serial_stop_rx(struct uart_port *port)
423{
b73c289c 424 struct s3c24xx_uart_port *ourport = to_ourport(port);
b543c301
RB		 425 struct s3c24xx_uart_dma *dma = ourport->dma;
426 struct tty_port *t = &port->state->port;
427 struct dma_tx_state state;
428 enum dma_status dma_status;
429 unsigned int received;
b73c289c 430
b497549a
BD		 431 if (rx_enabled(port)) {
432 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
88bb4ea1
TA		 433 if (s3c24xx_serial_has_interrupt_mask(port))
434 __set_bit(S3C64XX_UINTM_RXD,
435 portaddrl(port, S3C64XX_UINTM));
436 else
437 disable_irq_nosync(ourport->rx_irq);
b497549a
BD		 438 rx_enabled(port) = 0;
439 }
b543c301
RB		 440 if (dma && dma->rx_chan) {
441 dmaengine_pause(dma->tx_chan);
442 dma_status = dmaengine_tx_status(dma->rx_chan,
443 dma->rx_cookie, &state);
444 if (dma_status == DMA_IN_PROGRESS ||
445 dma_status == DMA_PAUSED) {
446 received = dma->rx_bytes_requested - state.residue;
447 dmaengine_terminate_all(dma->rx_chan);
448 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
449 }
450 }
b497549a
BD		 451}
452
ef4aca70
RB		 453static inline struct s3c24xx_uart_info
454 *s3c24xx_port_to_info(struct uart_port *port)
b497549a
BD		 455{
456 return to_ourport(port)->info;
457}
458
ef4aca70
RB		 459static inline struct s3c2410_uartcfg
460 *s3c24xx_port_to_cfg(struct uart_port *port)
b497549a 461{
4d84e970
TA		 462 struct s3c24xx_uart_port *ourport;
463
b497549a
BD		 464 if (port->dev == NULL)
465 return NULL;
466
4d84e970
TA		 467 ourport = container_of(port, struct s3c24xx_uart_port, port);
468 return ourport->cfg;
b497549a
BD		 469}
470
471static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
472 unsigned long ufstat)
473{
474 struct s3c24xx_uart_info *info = ourport->info;
475
476 if (ufstat & info->rx_fifofull)
da121506 477 return ourport->port.fifosize;
b497549a
BD		 478
479 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
480}
481
b543c301
RB		 482static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
483static void s3c24xx_serial_rx_dma_complete(void *args)
484{
485 struct s3c24xx_uart_port *ourport = args;
486 struct uart_port *port = &ourport->port;
487
488 struct s3c24xx_uart_dma *dma = ourport->dma;
489 struct tty_port *t = &port->state->port;
490 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
491
492 struct dma_tx_state state;
493 unsigned long flags;
494 int received;
495
496 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
497 received = dma->rx_bytes_requested - state.residue;
498 async_tx_ack(dma->rx_desc);
499
500 spin_lock_irqsave(&port->lock, flags);
501
502 if (received)
503 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
504
505 if (tty) {
506 tty_flip_buffer_push(t);
507 tty_kref_put(tty);
508 }
509
510 s3c64xx_start_rx_dma(ourport);
511
512 spin_unlock_irqrestore(&port->lock, flags);
513}
514
515static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
516{
517 struct s3c24xx_uart_dma *dma = ourport->dma;
518
519 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
520 dma->rx_size, DMA_FROM_DEVICE);
521
522 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
523 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
524 DMA_PREP_INTERRUPT);
525 if (!dma->rx_desc) {
526 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
527 return;
528 }
529
530 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
531 dma->rx_desc->callback_param = ourport;
532 dma->rx_bytes_requested = dma->rx_size;
533
534 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
535 dma_async_issue_pending(dma->rx_chan);
536}
b497549a
BD		 537
538/* ? - where has parity gone?? */
539#define S3C2410_UERSTAT_PARITY (0x1000)
540
b543c301
RB		 541static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
542{
543 struct uart_port *port = &ourport->port;
544 unsigned int ucon;
545
546 /* set Rx mode to DMA mode */
547 ucon = rd_regl(port, S3C2410_UCON);
548 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
549 S3C64XX_UCON_TIMEOUT_MASK |
550 S3C64XX_UCON_EMPTYINT_EN |
551 S3C64XX_UCON_DMASUS_EN |
552 S3C64XX_UCON_TIMEOUT_EN |
553 S3C64XX_UCON_RXMODE_MASK);
554 ucon |= S3C64XX_UCON_RXBURST_16 |
555 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
556 S3C64XX_UCON_EMPTYINT_EN |
557 S3C64XX_UCON_TIMEOUT_EN |
558 S3C64XX_UCON_RXMODE_DMA;
559 wr_regl(port, S3C2410_UCON, ucon);
560
561 ourport->rx_mode = S3C24XX_RX_DMA;
562}
563
564static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
565{
566 struct uart_port *port = &ourport->port;
567 unsigned int ucon;
568
569 /* set Rx mode to DMA mode */
570 ucon = rd_regl(port, S3C2410_UCON);
571 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
572 S3C64XX_UCON_EMPTYINT_EN |
573 S3C64XX_UCON_DMASUS_EN |
574 S3C64XX_UCON_TIMEOUT_EN |
575 S3C64XX_UCON_RXMODE_MASK);
576 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
577 S3C64XX_UCON_TIMEOUT_EN |
578 S3C64XX_UCON_RXMODE_CPU;
579 wr_regl(port, S3C2410_UCON, ucon);
580
581 ourport->rx_mode = S3C24XX_RX_PIO;
582}
583
584static irqreturn_t s3c24xx_serial_rx_chars_dma(int irq, void *dev_id)
585{
586 unsigned int utrstat, ufstat, received;
587 struct s3c24xx_uart_port *ourport = dev_id;
588 struct uart_port *port = &ourport->port;
589 struct s3c24xx_uart_dma *dma = ourport->dma;
590 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
591 struct tty_port *t = &port->state->port;
592 unsigned long flags;
593 struct dma_tx_state state;
594
595 utrstat = rd_regl(port, S3C2410_UTRSTAT);
596 ufstat = rd_regl(port, S3C2410_UFSTAT);
597
598 spin_lock_irqsave(&port->lock, flags);
599
600 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
601 s3c64xx_start_rx_dma(ourport);
602 if (ourport->rx_mode == S3C24XX_RX_PIO)
603 enable_rx_dma(ourport);
604 goto finish;
605 }
606
607 if (ourport->rx_mode == S3C24XX_RX_DMA) {
608 dmaengine_pause(dma->rx_chan);
609 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
610 dmaengine_terminate_all(dma->rx_chan);
611 received = dma->rx_bytes_requested - state.residue;
612 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
613
614 enable_rx_pio(ourport);
615 }
616
617 uart_rx_drain_fifo(ourport);
618
619 if (tty) {
620 tty_flip_buffer_push(t);
621 tty_kref_put(tty);
622 }
623
624 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
625
626finish:
627 spin_unlock_irqrestore(&port->lock, flags);
628
629 return IRQ_HANDLED;
630}
631
632static irqreturn_t s3c24xx_serial_rx_chars_pio(int irq, void *dev_id)
b497549a
BD		 633{
634 struct s3c24xx_uart_port *ourport = dev_id;
635 struct uart_port *port = &ourport->port;
b497549a 636 unsigned int ufcon, ch, flag, ufstat, uerstat;
c15c3747 637 unsigned long flags;
57850a50 638 int max_count = port->fifosize;
b497549a 639
c15c3747
TA		 640 spin_lock_irqsave(&port->lock, flags);
641
b497549a
BD		 642 while (max_count-- > 0) {
643 ufcon = rd_regl(port, S3C2410_UFCON);
644 ufstat = rd_regl(port, S3C2410_UFSTAT);
645
646 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
647 break;
648
649 uerstat = rd_regl(port, S3C2410_UERSTAT);
650 ch = rd_regb(port, S3C2410_URXH);
651
652 if (port->flags & UPF_CONS_FLOW) {
653 int txe = s3c24xx_serial_txempty_nofifo(port);
654
655 if (rx_enabled(port)) {
656 if (!txe) {
657 rx_enabled(port) = 0;
658 continue;
659 }
660 } else {
661 if (txe) {
662 ufcon |= S3C2410_UFCON_RESETRX;
663 wr_regl(port, S3C2410_UFCON, ufcon);
664 rx_enabled(port) = 1;
f5693ea2
VK		 665 spin_unlock_irqrestore(&port->lock,
666 flags);
b497549a
BD		 667 goto out;
668 }
669 continue;
670 }
671 }
672
673 /* insert the character into the buffer */
674
675 flag = TTY_NORMAL;
676 port->icount.rx++;
677
678 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
679 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
680 ch, uerstat);
681
682 /* check for break */
683 if (uerstat & S3C2410_UERSTAT_BREAK) {
684 dbg("break!\n");
685 port->icount.brk++;
686 if (uart_handle_break(port))
9303ac15 687 goto ignore_char;
b497549a
BD		 688 }
689
690 if (uerstat & S3C2410_UERSTAT_FRAME)
691 port->icount.frame++;
692 if (uerstat & S3C2410_UERSTAT_OVERRUN)
693 port->icount.overrun++;
694
695 uerstat &= port->read_status_mask;
696
697 if (uerstat & S3C2410_UERSTAT_BREAK)
698 flag = TTY_BREAK;
699 else if (uerstat & S3C2410_UERSTAT_PARITY)
700 flag = TTY_PARITY;
701 else if (uerstat & (S3C2410_UERSTAT_FRAME |
702 S3C2410_UERSTAT_OVERRUN))
703 flag = TTY_FRAME;
704 }
705
706 if (uart_handle_sysrq_char(port, ch))
707 goto ignore_char;
708
709 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
710 ch, flag);
711
ef4aca70 712ignore_char:
b497549a
BD		 713 continue;
714 }
f5693ea2
VK		 715
716 spin_unlock_irqrestore(&port->lock, flags);
2e124b4a 717 tty_flip_buffer_push(&port->state->port);
b497549a 718
ef4aca70 719out:
b497549a
BD		 720 return IRQ_HANDLED;
721}
722
b543c301
RB		 723
724static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
725{
726 struct s3c24xx_uart_port *ourport = dev_id;
727
728 if (ourport->dma && ourport->dma->rx_chan)
729 return s3c24xx_serial_rx_chars_dma(irq, dev_id);
730 return s3c24xx_serial_rx_chars_pio(irq, dev_id);
731}
732
b497549a
BD		 733static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
734{
735 struct s3c24xx_uart_port *ourport = id;
736 struct uart_port *port = &ourport->port;
ebd2c8f6 737 struct circ_buf *xmit = &port->state->xmit;
c15c3747 738 unsigned long flags;
29bef799 739 int count;
b497549a 740
c15c3747
TA		 741 spin_lock_irqsave(&port->lock, flags);
742
29bef799
RB		 743 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
744
745 if (ourport->dma && ourport->dma->tx_chan && count >= port->fifosize) {
746 s3c24xx_serial_start_tx_dma(ourport, count);
747 goto out;
748 }
749
b497549a
BD		 750 if (port->x_char) {
751 wr_regb(port, S3C2410_UTXH, port->x_char);
752 port->icount.tx++;
753 port->x_char = 0;
754 goto out;
755 }
756
25985edc 757 /* if there isn't anything more to transmit, or the uart is now
b497549a
BD		 758 * stopped, disable the uart and exit
759 */
760
761 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
762 s3c24xx_serial_stop_tx(port);
763 goto out;
764 }
765
766 /* try and drain the buffer... */
767
29bef799 768 count = port->fifosize;
b497549a
BD		 769 while (!uart_circ_empty(xmit) && count-- > 0) {
770 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
771 break;
772
773 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
774 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
775 port->icount.tx++;
776 }
777
c15c3747
TA		 778 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
779 spin_unlock(&port->lock);
b497549a 780 uart_write_wakeup(port);
c15c3747
TA		 781 spin_lock(&port->lock);
782 }
b497549a
BD		 783
784 if (uart_circ_empty(xmit))
785 s3c24xx_serial_stop_tx(port);
786
ef4aca70 787out:
c15c3747 788 spin_unlock_irqrestore(&port->lock, flags);
b497549a
BD		 789 return IRQ_HANDLED;
790}
791
88bb4ea1
TA		 792/* interrupt handler for s3c64xx and later SoC's.*/
793static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
794{
795 struct s3c24xx_uart_port *ourport = id;
796 struct uart_port *port = &ourport->port;
797 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
88bb4ea1
TA		 798 irqreturn_t ret = IRQ_HANDLED;
799
88bb4ea1
TA		 800 if (pend & S3C64XX_UINTM_RXD_MSK) {
801 ret = s3c24xx_serial_rx_chars(irq, id);
802 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
803 }
804 if (pend & S3C64XX_UINTM_TXD_MSK) {
805 ret = s3c24xx_serial_tx_chars(irq, id);
806 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
807 }
88bb4ea1
TA		 808 return ret;
809}
810
b497549a
BD		 811static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
812{
813 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
814 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
815 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
816
817 if (ufcon & S3C2410_UFCON_FIFOMODE) {
818 if ((ufstat & info->tx_fifomask) != 0 ||
819 (ufstat & info->tx_fifofull))
820 return 0;
821
822 return 1;
823 }
824
825 return s3c24xx_serial_txempty_nofifo(port);
826}
827
828/* no modem control lines */
829static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
830{
831 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
832
833 if (umstat & S3C2410_UMSTAT_CTS)
834 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
835 else
836 return TIOCM_CAR | TIOCM_DSR;
837}
838
839static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
840{
2d1e5a48
JMG		 841 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
842
843 if (mctrl & TIOCM_RTS)
844 umcon |= S3C2410_UMCOM_RTS_LOW;
845 else
846 umcon &= ~S3C2410_UMCOM_RTS_LOW;
847
848 wr_regl(port, S3C2410_UMCON, umcon);
b497549a
BD		 849}
850
851static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
852{
853 unsigned long flags;
854 unsigned int ucon;
855
856 spin_lock_irqsave(&port->lock, flags);
857
858 ucon = rd_regl(port, S3C2410_UCON);
859
860 if (break_state)
861 ucon |= S3C2410_UCON_SBREAK;
862 else
863 ucon &= ~S3C2410_UCON_SBREAK;
864
865 wr_regl(port, S3C2410_UCON, ucon);
866
867 spin_unlock_irqrestore(&port->lock, flags);
868}
869
62c37eed
RB		 870static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
871{
872 struct s3c24xx_uart_dma *dma = p->dma;
873 dma_cap_mask_t mask;
874 unsigned long flags;
875
876 /* Default slave configuration parameters */
877 dma->rx_conf.direction = DMA_DEV_TO_MEM;
878 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
879 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
880 dma->rx_conf.src_maxburst = 16;
881
882 dma->tx_conf.direction = DMA_MEM_TO_DEV;
883 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
884 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
885 if (dma_get_cache_alignment() >= 16)
886 dma->tx_conf.dst_maxburst = 16;
887 else
888 dma->tx_conf.dst_maxburst = 1;
889
890 dma_cap_zero(mask);
891 dma_cap_set(DMA_SLAVE, mask);
892
893 dma->rx_chan = dma_request_slave_channel_compat(mask, dma->fn,
894 dma->rx_param, p->port.dev, "rx");
895 if (!dma->rx_chan)
896 return -ENODEV;
897
898 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
899
900 dma->tx_chan = dma_request_slave_channel_compat(mask, dma->fn,
901 dma->tx_param, p->port.dev, "tx");
902 if (!dma->tx_chan) {
903 dma_release_channel(dma->rx_chan);
904 return -ENODEV;
905 }
906
907 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
908
909 /* RX buffer */
910 dma->rx_size = PAGE_SIZE;
911
912 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
913
914 if (!dma->rx_buf) {
915 dma_release_channel(dma->rx_chan);
916 dma_release_channel(dma->tx_chan);
917 return -ENOMEM;
918 }
919
920 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
921 dma->rx_size, DMA_FROM_DEVICE);
922
923 spin_lock_irqsave(&p->port.lock, flags);
924
925 /* TX buffer */
926 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
927 p->port.state->xmit.buf,
928 UART_XMIT_SIZE, DMA_TO_DEVICE);
929
930 spin_unlock_irqrestore(&p->port.lock, flags);
931
932 return 0;
933}
934
935static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
936{
937 struct s3c24xx_uart_dma *dma = p->dma;
938
939 if (dma->rx_chan) {
940 dmaengine_terminate_all(dma->rx_chan);
941 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
942 dma->rx_size, DMA_FROM_DEVICE);
943 kfree(dma->rx_buf);
944 dma_release_channel(dma->rx_chan);
945 dma->rx_chan = NULL;
946 }
947
948 if (dma->tx_chan) {
949 dmaengine_terminate_all(dma->tx_chan);
950 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
951 UART_XMIT_SIZE, DMA_TO_DEVICE);
952 dma_release_channel(dma->tx_chan);
953 dma->tx_chan = NULL;
954 }
955}
956
b497549a
BD		 957static void s3c24xx_serial_shutdown(struct uart_port *port)
958{
959 struct s3c24xx_uart_port *ourport = to_ourport(port);
960
961 if (ourport->tx_claimed) {
88bb4ea1
TA		 962 if (!s3c24xx_serial_has_interrupt_mask(port))
963 free_irq(ourport->tx_irq, ourport);
b497549a
BD		 964 tx_enabled(port) = 0;
965 ourport->tx_claimed = 0;
e91d863d 966 ourport->tx_mode = 0;
b497549a
BD		 967 }
968
969 if (ourport->rx_claimed) {
88bb4ea1
TA		 970 if (!s3c24xx_serial_has_interrupt_mask(port))
971 free_irq(ourport->rx_irq, ourport);
b497549a
BD		 972 ourport->rx_claimed = 0;
973 rx_enabled(port) = 0;
974 }
b497549a 975
88bb4ea1
TA		 976 /* Clear pending interrupts and mask all interrupts */
977 if (s3c24xx_serial_has_interrupt_mask(port)) {
b6ad2935
TF		 978 free_irq(port->irq, ourport);
979
88bb4ea1
TA		 980 wr_regl(port, S3C64XX_UINTP, 0xf);
981 wr_regl(port, S3C64XX_UINTM, 0xf);
982 }
62c37eed
RB		 983
984 if (ourport->dma)
985 s3c24xx_serial_release_dma(ourport);
986
29bef799 987 ourport->tx_in_progress = 0;
88bb4ea1 988}
b497549a
BD		 989
990static int s3c24xx_serial_startup(struct uart_port *port)
991{
992 struct s3c24xx_uart_port *ourport = to_ourport(port);
993 int ret;
994
e4ac92df
JP		 995 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
996 port, (unsigned long long)port->mapbase, port->membase);
b497549a
BD		 997
998 rx_enabled(port) = 1;
999
b73c289c 1000 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
b497549a
BD		 1001 s3c24xx_serial_portname(port), ourport);
1002
1003 if (ret != 0) {
d20925e1 1004 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
b497549a
BD		 1005 return ret;
1006 }
1007
1008 ourport->rx_claimed = 1;
1009
1010 dbg("requesting tx irq...\n");
1011
1012 tx_enabled(port) = 1;
1013
b73c289c 1014 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
b497549a
BD		 1015 s3c24xx_serial_portname(port), ourport);
1016
1017 if (ret) {
d20925e1 1018 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
b497549a
BD		 1019 goto err;
1020 }
1021
1022 ourport->tx_claimed = 1;
1023
1024 dbg("s3c24xx_serial_startup ok\n");
1025
1026 /* the port reset code should have done the correct
1027 * register setup for the port controls */
1028
1029 return ret;
1030
ef4aca70 1031err:
b497549a
BD		 1032 s3c24xx_serial_shutdown(port);
1033 return ret;
1034}
1035
88bb4ea1
TA		 1036static int s3c64xx_serial_startup(struct uart_port *port)
1037{
1038 struct s3c24xx_uart_port *ourport = to_ourport(port);
b543c301
RB		 1039 unsigned long flags;
1040 unsigned int ufcon;
88bb4ea1
TA		 1041 int ret;
1042
e4ac92df
JP		 1043 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1044 port, (unsigned long long)port->mapbase, port->membase);
88bb4ea1 1045
b6ad2935 1046 wr_regl(port, S3C64XX_UINTM, 0xf);
62c37eed
RB		 1047 if (ourport->dma) {
1048 ret = s3c24xx_serial_request_dma(ourport);
1049 if (ret < 0) {
1050 dev_warn(port->dev, "DMA request failed\n");
1051 return ret;
1052 }
1053 }
b6ad2935 1054
88bb4ea1
TA		 1055 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1056 s3c24xx_serial_portname(port), ourport);
1057 if (ret) {
d20925e1 1058 dev_err(port->dev, "cannot get irq %d\n", port->irq);
88bb4ea1
TA		 1059 return ret;
1060 }
1061
1062 /* For compatibility with s3c24xx Soc's */
1063 rx_enabled(port) = 1;
1064 ourport->rx_claimed = 1;
1065 tx_enabled(port) = 0;
1066 ourport->tx_claimed = 1;
1067
29bef799
RB		 1068 spin_lock_irqsave(&port->lock, flags);
1069
1070 ufcon = rd_regl(port, S3C2410_UFCON);
b543c301
RB		 1071 ufcon |= S3C2410_UFCON_RESETRX | S3C2410_UFCON_RESETTX |
1072 S5PV210_UFCON_RXTRIG8;
29bef799
RB		 1073 wr_regl(port, S3C2410_UFCON, ufcon);
1074
1075 enable_rx_pio(ourport);
1076
1077 spin_unlock_irqrestore(&port->lock, flags);
1078
88bb4ea1
TA		 1079 /* Enable Rx Interrupt */
1080 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
29bef799 1081
88bb4ea1
TA		 1082 dbg("s3c64xx_serial_startup ok\n");
1083 return ret;
1084}
1085
b497549a
BD		 1086/* power power management control */
1087
1088static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1089 unsigned int old)
1090{
1091 struct s3c24xx_uart_port *ourport = to_ourport(port);
1ff383a4 1092 int timeout = 10000;
b497549a 1093
30555476
BD		 1094 ourport->pm_level = level;
1095
b497549a
BD		 1096 switch (level) {
1097 case 3:
1ff383a4
RB		 1098 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1099 udelay(100);
1100
7cd88831 1101 if (!IS_ERR(ourport->baudclk))
9484b009 1102 clk_disable_unprepare(ourport->baudclk);
b497549a 1103
9484b009 1104 clk_disable_unprepare(ourport->clk);
b497549a
BD		 1105 break;
1106
1107 case 0:
9484b009 1108 clk_prepare_enable(ourport->clk);
b497549a 1109
7cd88831 1110 if (!IS_ERR(ourport->baudclk))
9484b009 1111 clk_prepare_enable(ourport->baudclk);
b497549a
BD		 1112
1113 break;
1114 default:
d20925e1 1115 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
b497549a
BD		 1116 }
1117}
1118
1119/* baud rate calculation
1120 *
1121 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1122 * of different sources, including the peripheral clock ("pclk") and an
1123 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1124 * with a programmable extra divisor.
1125 *
1126 * The following code goes through the clock sources, and calculates the
1127 * baud clocks (and the resultant actual baud rates) and then tries to
1128 * pick the closest one and select that.
1129 *
1130*/
1131
5f5a7a55 1132#define MAX_CLK_NAME_LENGTH 15
b497549a 1133
5f5a7a55 1134static inline int s3c24xx_serial_getsource(struct uart_port *port)
b497549a
BD		 1135{
1136 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
5f5a7a55 1137 unsigned int ucon;
b497549a 1138
5f5a7a55
TA		 1139 if (info->num_clks == 1)
1140 return 0;
b497549a 1141
5f5a7a55
TA		 1142 ucon = rd_regl(port, S3C2410_UCON);
1143 ucon &= info->clksel_mask;
1144 return ucon >> info->clksel_shift;
b497549a
BD		 1145}
1146
5f5a7a55
TA		 1147static void s3c24xx_serial_setsource(struct uart_port *port,
1148 unsigned int clk_sel)
b497549a 1149{
5f5a7a55
TA		 1150 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1151 unsigned int ucon;
b497549a 1152
5f5a7a55
TA		 1153 if (info->num_clks == 1)
1154 return;
090f848d 1155
5f5a7a55
TA		 1156 ucon = rd_regl(port, S3C2410_UCON);
1157 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1158 return;
b497549a 1159
5f5a7a55
TA		 1160 ucon &= ~info->clksel_mask;
1161 ucon |= clk_sel << info->clksel_shift;
1162 wr_regl(port, S3C2410_UCON, ucon);
b497549a
BD		 1163}
1164
5f5a7a55
TA		 1165static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1166 unsigned int req_baud, struct clk **best_clk,
1167 unsigned int *clk_num)
b497549a 1168{
5f5a7a55
TA		 1169 struct s3c24xx_uart_info *info = ourport->info;
1170 struct clk *clk;
1171 unsigned long rate;
1172 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1173 char clkname[MAX_CLK_NAME_LENGTH];
1174 int calc_deviation, deviation = (1 << 30) - 1;
1175
5f5a7a55
TA		 1176 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1177 ourport->info->def_clk_sel;
1178 for (cnt = 0; cnt < info->num_clks; cnt++) {
1179 if (!(clk_sel & (1 << cnt)))
1180 continue;
1181
1182 sprintf(clkname, "clk_uart_baud%d", cnt);
1183 clk = clk_get(ourport->port.dev, clkname);
7cd88831 1184 if (IS_ERR(clk))
5f5a7a55
TA		 1185 continue;
1186
1187 rate = clk_get_rate(clk);
1188 if (!rate)
1189 continue;
1190
1191 if (ourport->info->has_divslot) {
1192 unsigned long div = rate / req_baud;
1193
1194 /* The UDIVSLOT register on the newer UARTs allows us to
1195 * get a divisor adjustment of 1/16th on the baud clock.
1196 *
1197 * We don't keep the UDIVSLOT value (the 16ths we
1198 * calculated by not multiplying the baud by 16) as it
1199 * is easy enough to recalculate.
1200 */
1201
1202 quot = div / 16;
1203 baud = rate / div;
1204 } else {
1205 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1206 baud = rate / (quot * 16);
b497549a 1207 }
5f5a7a55 1208 quot--;
b497549a 1209
5f5a7a55
TA		 1210 calc_deviation = req_baud - baud;
1211 if (calc_deviation < 0)
1212 calc_deviation = -calc_deviation;
b497549a 1213
5f5a7a55
TA		 1214 if (calc_deviation < deviation) {
1215 *best_clk = clk;
1216 best_quot = quot;
1217 *clk_num = cnt;
1218 deviation = calc_deviation;
b497549a
BD		 1219 }
1220 }
1221
5f5a7a55 1222 return best_quot;
b497549a
BD		 1223}
1224
090f848d
BD		 1225/* udivslot_table[]
1226 *
1227 * This table takes the fractional value of the baud divisor and gives
1228 * the recommended setting for the UDIVSLOT register.
1229 */
1230static u16 udivslot_table[16] = {
1231 [0] = 0x0000,
1232 [1] = 0x0080,
1233 [2] = 0x0808,
1234 [3] = 0x0888,
1235 [4] = 0x2222,
1236 [5] = 0x4924,
1237 [6] = 0x4A52,
1238 [7] = 0x54AA,
1239 [8] = 0x5555,
1240 [9] = 0xD555,
1241 [10] = 0xD5D5,
1242 [11] = 0xDDD5,
1243 [12] = 0xDDDD,
1244 [13] = 0xDFDD,
1245 [14] = 0xDFDF,
1246 [15] = 0xFFDF,
1247};
1248
b497549a
BD		 1249static void s3c24xx_serial_set_termios(struct uart_port *port,
1250 struct ktermios *termios,
1251 struct ktermios *old)
1252{
1253 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1254 struct s3c24xx_uart_port *ourport = to_ourport(port);
7cd88831 1255 struct clk *clk = ERR_PTR(-EINVAL);
b497549a 1256 unsigned long flags;
5f5a7a55 1257 unsigned int baud, quot, clk_sel = 0;
b497549a
BD		 1258 unsigned int ulcon;
1259 unsigned int umcon;
090f848d 1260 unsigned int udivslot = 0;
b497549a
BD		 1261
1262 /*
1263 * We don't support modem control lines.
1264 */
1265 termios->c_cflag &= ~(HUPCL | CMSPAR);
1266 termios->c_cflag |= CLOCAL;
1267
1268 /*
1269 * Ask the core to calculate the divisor for us.
1270 */
1271
1272 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
5f5a7a55 1273 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
b497549a
BD		 1274 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1275 quot = port->custom_divisor;
7cd88831 1276 if (IS_ERR(clk))
5f5a7a55 1277 return;
b497549a
BD		 1278
1279 /* check to see if we need to change clock source */
1280
5f5a7a55
TA		 1281 if (ourport->baudclk != clk) {
1282 s3c24xx_serial_setsource(port, clk_sel);
b497549a 1283
7cd88831 1284 if (!IS_ERR(ourport->baudclk)) {
9484b009 1285 clk_disable_unprepare(ourport->baudclk);
7cd88831 1286 ourport->baudclk = ERR_PTR(-EINVAL);
b497549a
BD		 1287 }
1288
9484b009 1289 clk_prepare_enable(clk);
b497549a 1290
b497549a 1291 ourport->baudclk = clk;
30555476 1292 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
b497549a
BD		 1293 }
1294
090f848d
BD		 1295 if (ourport->info->has_divslot) {
1296 unsigned int div = ourport->baudclk_rate / baud;
1297
8b526ae4
JL		 1298 if (cfg->has_fracval) {
1299 udivslot = (div & 15);
1300 dbg("fracval = %04x\n", udivslot);
1301 } else {
1302 udivslot = udivslot_table[div & 15];
1303 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1304 }
090f848d
BD		 1305 }
1306
b497549a
BD		 1307 switch (termios->c_cflag & CSIZE) {
1308 case CS5:
1309 dbg("config: 5bits/char\n");
1310 ulcon = S3C2410_LCON_CS5;
1311 break;
1312 case CS6:
1313 dbg("config: 6bits/char\n");
1314 ulcon = S3C2410_LCON_CS6;
1315 break;
1316 case CS7:
1317 dbg("config: 7bits/char\n");
1318 ulcon = S3C2410_LCON_CS7;
1319 break;
1320 case CS8:
1321 default:
1322 dbg("config: 8bits/char\n");
1323 ulcon = S3C2410_LCON_CS8;
1324 break;
1325 }
1326
1327 /* preserve original lcon IR settings */
1328 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1329
1330 if (termios->c_cflag & CSTOPB)
1331 ulcon |= S3C2410_LCON_STOPB;
1332
b497549a
BD		 1333 if (termios->c_cflag & PARENB) {
1334 if (termios->c_cflag & PARODD)
1335 ulcon |= S3C2410_LCON_PODD;
1336 else
1337 ulcon |= S3C2410_LCON_PEVEN;
1338 } else {
1339 ulcon |= S3C2410_LCON_PNONE;
1340 }
1341
1342 spin_lock_irqsave(&port->lock, flags);
1343
090f848d
BD		 1344 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1345 ulcon, quot, udivslot);
b497549a
BD		 1346
1347 wr_regl(port, S3C2410_ULCON, ulcon);
1348 wr_regl(port, S3C2410_UBRDIV, quot);
2d1e5a48
JMG		 1349
1350 umcon = rd_regl(port, S3C2410_UMCON);
1351 if (termios->c_cflag & CRTSCTS) {
1352 umcon |= S3C2410_UMCOM_AFC;
1353 /* Disable RTS when RX FIFO contains 63 bytes */
1354 umcon &= ~S3C2412_UMCON_AFC_8;
1355 } else {
1356 umcon &= ~S3C2410_UMCOM_AFC;
1357 }
b497549a
BD		 1358 wr_regl(port, S3C2410_UMCON, umcon);
1359
090f848d
BD		 1360 if (ourport->info->has_divslot)
1361 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1362
b497549a
BD		 1363 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1364 rd_regl(port, S3C2410_ULCON),
1365 rd_regl(port, S3C2410_UCON),
1366 rd_regl(port, S3C2410_UFCON));
1367
1368 /*
1369 * Update the per-port timeout.
1370 */
1371 uart_update_timeout(port, termios->c_cflag, baud);
1372
1373 /*
1374 * Which character status flags are we interested in?
1375 */
1376 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1377 if (termios->c_iflag & INPCK)
ef4aca70
RB		 1378 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1379 S3C2410_UERSTAT_PARITY;
b497549a
BD		 1380 /*
1381 * Which character status flags should we ignore?
1382 */
1383 port->ignore_status_mask = 0;
1384 if (termios->c_iflag & IGNPAR)
1385 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1386 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1387 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1388
1389 /*
1390 * Ignore all characters if CREAD is not set.
1391 */
1392 if ((termios->c_cflag & CREAD) == 0)
1393 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1394
1395 spin_unlock_irqrestore(&port->lock, flags);
1396}
1397
1398static const char *s3c24xx_serial_type(struct uart_port *port)
1399{
1400 switch (port->type) {
1401 case PORT_S3C2410:
1402 return "S3C2410";
1403 case PORT_S3C2440:
1404 return "S3C2440";
1405 case PORT_S3C2412:
1406 return "S3C2412";
b690ace5
BD		 1407 case PORT_S3C6400:
1408 return "S3C6400/10";
b497549a
BD		 1409 default:
1410 return NULL;
1411 }
1412}
1413
1414#define MAP_SIZE (0x100)
1415
1416static void s3c24xx_serial_release_port(struct uart_port *port)
1417{
1418 release_mem_region(port->mapbase, MAP_SIZE);
1419}
1420
1421static int s3c24xx_serial_request_port(struct uart_port *port)
1422{
1423 const char *name = s3c24xx_serial_portname(port);
1424 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1425}
1426
1427static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1428{
1429 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1430
1431 if (flags & UART_CONFIG_TYPE &&
1432 s3c24xx_serial_request_port(port) == 0)
1433 port->type = info->type;
1434}
1435
1436/*
1437 * verify the new serial_struct (for TIOCSSERIAL).
1438 */
1439static int
1440s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1441{
1442 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1443
1444 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1445 return -EINVAL;
1446
1447 return 0;
1448}
1449
1450
1451#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1452
1453static struct console s3c24xx_serial_console;
1454
93b5c032
JP		 1455static int __init s3c24xx_serial_console_init(void)
1456{
1457 register_console(&s3c24xx_serial_console);
1458 return 0;
1459}
1460console_initcall(s3c24xx_serial_console_init);
1461
b497549a
BD		 1462#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1463#else
1464#define S3C24XX_SERIAL_CONSOLE NULL
1465#endif
1466
84f57d9e 1467#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 1468static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1469static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1470 unsigned char c);
1471#endif
1472
b497549a
BD		 1473static struct uart_ops s3c24xx_serial_ops = {
1474 .pm = s3c24xx_serial_pm,
1475 .tx_empty = s3c24xx_serial_tx_empty,
1476 .get_mctrl = s3c24xx_serial_get_mctrl,
1477 .set_mctrl = s3c24xx_serial_set_mctrl,
1478 .stop_tx = s3c24xx_serial_stop_tx,
1479 .start_tx = s3c24xx_serial_start_tx,
1480 .stop_rx = s3c24xx_serial_stop_rx,
b497549a
BD		 1481 .break_ctl = s3c24xx_serial_break_ctl,
1482 .startup = s3c24xx_serial_startup,
1483 .shutdown = s3c24xx_serial_shutdown,
1484 .set_termios = s3c24xx_serial_set_termios,
1485 .type = s3c24xx_serial_type,
1486 .release_port = s3c24xx_serial_release_port,
1487 .request_port = s3c24xx_serial_request_port,
1488 .config_port = s3c24xx_serial_config_port,
1489 .verify_port = s3c24xx_serial_verify_port,
84f57d9e 1490#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 1491 .poll_get_char = s3c24xx_serial_get_poll_char,
1492 .poll_put_char = s3c24xx_serial_put_poll_char,
1493#endif
b497549a
BD		 1494};
1495
b497549a
BD		 1496static struct uart_driver s3c24xx_uart_drv = {
1497 .owner = THIS_MODULE,
2cf0c58e 1498 .driver_name = "s3c2410_serial",
bdd4915a 1499 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
b497549a 1500 .cons = S3C24XX_SERIAL_CONSOLE,
2cf0c58e 1501 .dev_name = S3C24XX_SERIAL_NAME,
b497549a
BD		 1502 .major = S3C24XX_SERIAL_MAJOR,
1503 .minor = S3C24XX_SERIAL_MINOR,
1504};
1505
ef4aca70
RB		 1506#define __PORT_LOCK_UNLOCKED(i) \
1507 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1508static struct s3c24xx_uart_port
1509s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
b497549a
BD		 1510 [0] = {
1511 .port = {
ef4aca70 1512 .lock = __PORT_LOCK_UNLOCKED(0),
b497549a 1513 .iotype = UPIO_MEM,
b497549a
BD		 1514 .uartclk = 0,
1515 .fifosize = 16,
1516 .ops = &s3c24xx_serial_ops,
1517 .flags = UPF_BOOT_AUTOCONF,
1518 .line = 0,
1519 }
1520 },
1521 [1] = {
1522 .port = {
ef4aca70 1523 .lock = __PORT_LOCK_UNLOCKED(1),
b497549a 1524 .iotype = UPIO_MEM,
b497549a
BD		 1525 .uartclk = 0,
1526 .fifosize = 16,
1527 .ops = &s3c24xx_serial_ops,
1528 .flags = UPF_BOOT_AUTOCONF,
1529 .line = 1,
1530 }
1531 },
03d5e77b 1532#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
b497549a
BD		 1533
1534 [2] = {
1535 .port = {
ef4aca70 1536 .lock = __PORT_LOCK_UNLOCKED(2),
b497549a 1537 .iotype = UPIO_MEM,
b497549a
BD		 1538 .uartclk = 0,
1539 .fifosize = 16,
1540 .ops = &s3c24xx_serial_ops,
1541 .flags = UPF_BOOT_AUTOCONF,
1542 .line = 2,
1543 }
03d5e77b
BD		 1544 },
1545#endif
1546#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1547 [3] = {
1548 .port = {
ef4aca70 1549 .lock = __PORT_LOCK_UNLOCKED(3),
03d5e77b 1550 .iotype = UPIO_MEM,
03d5e77b
BD		 1551 .uartclk = 0,
1552 .fifosize = 16,
1553 .ops = &s3c24xx_serial_ops,
1554 .flags = UPF_BOOT_AUTOCONF,
1555 .line = 3,
1556 }
b497549a
BD		 1557 }
1558#endif
1559};
ef4aca70 1560#undef __PORT_LOCK_UNLOCKED
b497549a
BD		 1561
1562/* s3c24xx_serial_resetport
1563 *
0dfb3b41 1564 * reset the fifos and other the settings.
b497549a
BD		 1565*/
1566
0dfb3b41
TA		 1567static void s3c24xx_serial_resetport(struct uart_port *port,
1568 struct s3c2410_uartcfg *cfg)
b497549a
BD		 1569{
1570 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
0dfb3b41
TA		 1571 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1572 unsigned int ucon_mask;
b497549a 1573
0dfb3b41
TA		 1574 ucon_mask = info->clksel_mask;
1575 if (info->type == PORT_S3C2440)
1576 ucon_mask |= S3C2440_UCON0_DIVMASK;
1577
1578 ucon &= ucon_mask;
1579 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1580
1581 /* reset both fifos */
1582 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1583 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1584
1585 /* some delay is required after fifo reset */
1586 udelay(1);
b497549a
BD		 1587}
1588
30555476
BD		 1589
1590#ifdef CONFIG_CPU_FREQ
1591
1592static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1593 unsigned long val, void *data)
1594{
1595 struct s3c24xx_uart_port *port;
1596 struct uart_port *uport;
1597
1598 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1599 uport = &port->port;
1600
1601 /* check to see if port is enabled */
1602
1603 if (port->pm_level != 0)
1604 return 0;
1605
1606 /* try and work out if the baudrate is changing, we can detect
1607 * a change in rate, but we do not have support for detecting
1608 * a disturbance in the clock-rate over the change.
1609 */
1610
25f04ad4 1611 if (IS_ERR(port->baudclk))
30555476
BD		 1612 goto exit;
1613
25f04ad4 1614 if (port->baudclk_rate == clk_get_rate(port->baudclk))
30555476
BD		 1615 goto exit;
1616
1617 if (val == CPUFREQ_PRECHANGE) {
1618 /* we should really shut the port down whilst the
1619 * frequency change is in progress. */
1620
1621 } else if (val == CPUFREQ_POSTCHANGE) {
1622 struct ktermios *termios;
1623 struct tty_struct *tty;
1624
ebd2c8f6 1625 if (uport->state == NULL)
30555476 1626 goto exit;
30555476 1627
ebd2c8f6 1628 tty = uport->state->port.tty;
30555476 1629
7de40c21 1630 if (tty == NULL)
30555476 1631 goto exit;
30555476 1632
adc8d746 1633 termios = &tty->termios;
30555476
BD		 1634
1635 if (termios == NULL) {
d20925e1 1636 dev_warn(uport->dev, "%s: no termios?\n", __func__);
30555476
BD		 1637 goto exit;
1638 }
1639
1640 s3c24xx_serial_set_termios(uport, termios, NULL);
1641 }
1642
ef4aca70 1643exit:
30555476
BD		 1644 return 0;
1645}
1646
ef4aca70
RB		 1647static inline int
1648s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
30555476
BD		 1649{
1650 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1651
1652 return cpufreq_register_notifier(&port->freq_transition,
1653 CPUFREQ_TRANSITION_NOTIFIER);
1654}
1655
ef4aca70
RB		 1656static inline void
1657s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
30555476
BD		 1658{
1659 cpufreq_unregister_notifier(&port->freq_transition,
1660 CPUFREQ_TRANSITION_NOTIFIER);
1661}
1662
1663#else
ef4aca70
RB		 1664static inline int
1665s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
30555476
BD		 1666{
1667 return 0;
1668}
1669
ef4aca70
RB		 1670static inline void
1671s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
30555476
BD		 1672{
1673}
1674#endif
1675
b497549a
BD		 1676/* s3c24xx_serial_init_port
1677 *
1678 * initialise a single serial port from the platform device given
1679 */
1680
1681static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
b497549a
BD		 1682 struct platform_device *platdev)
1683{
1684 struct uart_port *port = &ourport->port;
da121506 1685 struct s3c2410_uartcfg *cfg = ourport->cfg;
b497549a
BD		 1686 struct resource *res;
1687 int ret;
1688
1689 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1690
1691 if (platdev == NULL)
1692 return -ENODEV;
1693
b497549a
BD		 1694 if (port->mapbase != 0)
1695 return 0;
1696
b497549a
BD		 1697 /* setup info for port */
1698 port->dev = &platdev->dev;
b497549a 1699
88bb4ea1
TA		 1700 /* Startup sequence is different for s3c64xx and higher SoC's */
1701 if (s3c24xx_serial_has_interrupt_mask(port))
1702 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1703
b497549a
BD		 1704 port->uartclk = 1;
1705
1706 if (cfg->uart_flags & UPF_CONS_FLOW) {
1707 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1708 port->flags |= UPF_CONS_FLOW;
1709 }
1710
1711 /* sort our the physical and virtual addresses for each UART */
1712
1713 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1714 if (res == NULL) {
d20925e1 1715 dev_err(port->dev, "failed to find memory resource for uart\n");
b497549a
BD		 1716 return -EINVAL;
1717 }
1718
e4ac92df 1719 dbg("resource %pR)\n", res);
b497549a 1720
41147bfd
TA		 1721 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1722 if (!port->membase) {
1723 dev_err(port->dev, "failed to remap controller address\n");
1724 return -EBUSY;
1725 }
1726
b690ace5 1727 port->mapbase = res->start;
b497549a
BD		 1728 ret = platform_get_irq(platdev, 0);
1729 if (ret < 0)
1730 port->irq = 0;
b73c289c 1731 else {
b497549a 1732 port->irq = ret;
b73c289c
BD		 1733 ourport->rx_irq = ret;
1734 ourport->tx_irq = ret + 1;
1735 }
9303ac15 1736
b73c289c
BD		 1737 ret = platform_get_irq(platdev, 1);
1738 if (ret > 0)
1739 ourport->tx_irq = ret;
658c9d2b
RB		 1740 /*
1741 * DMA is currently supported only on DT platforms, if DMA properties
1742 * are specified.
1743 */
1744 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1745 "dmas", NULL)) {
1746 ourport->dma = devm_kzalloc(port->dev,
1747 sizeof(*ourport->dma),
1748 GFP_KERNEL);
1749 if (!ourport->dma)
1750 return -ENOMEM;
1751 }
b497549a
BD		 1752
1753 ourport->clk = clk_get(&platdev->dev, "uart");
60e93575
CK		 1754 if (IS_ERR(ourport->clk)) {
1755 pr_err("%s: Controller clock not found\n",
1756 dev_name(&platdev->dev));
1757 return PTR_ERR(ourport->clk);
1758 }
1759
1760 ret = clk_prepare_enable(ourport->clk);
1761 if (ret) {
1762 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1763 clk_put(ourport->clk);
1764 return ret;
1765 }
b497549a 1766
88bb4ea1
TA		 1767 /* Keep all interrupts masked and cleared */
1768 if (s3c24xx_serial_has_interrupt_mask(port)) {
1769 wr_regl(port, S3C64XX_UINTM, 0xf);
1770 wr_regl(port, S3C64XX_UINTP, 0xf);
1771 wr_regl(port, S3C64XX_UINTSP, 0xf);
1772 }
1773
1ff5b64d
FE		 1774 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1775 &port->mapbase, port->membase, port->irq,
b73c289c 1776 ourport->rx_irq, ourport->tx_irq, port->uartclk);
b497549a
BD		 1777
1778 /* reset the fifos (and setup the uart) */
1779 s3c24xx_serial_resetport(port, cfg);
1780 return 0;
1781}
1782
b497549a
BD		 1783/* Device driver serial port probe */
1784
26c919e1 1785static const struct of_device_id s3c24xx_uart_dt_match[];
b497549a
BD		 1786static int probe_index;
1787
26c919e1
TA		 1788static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1789 struct platform_device *pdev)
1790{
1791#ifdef CONFIG_OF
1792 if (pdev->dev.of_node) {
1793 const struct of_device_id *match;
1794 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1795 return (struct s3c24xx_serial_drv_data *)match->data;
1796 }
1797#endif
1798 return (struct s3c24xx_serial_drv_data *)
1799 platform_get_device_id(pdev)->driver_data;
1800}
1801
da121506 1802static int s3c24xx_serial_probe(struct platform_device *pdev)
b497549a 1803{
4622eb68 1804 struct device_node *np = pdev->dev.of_node;
b497549a 1805 struct s3c24xx_uart_port *ourport;
13a9f6c6 1806 int index = probe_index;
b497549a
BD		 1807 int ret;
1808
4622eb68
NKC		 1809 if (np) {
1810 ret = of_alias_get_id(np, "serial");
13a9f6c6
TF		 1811 if (ret >= 0)
1812 index = ret;
1813 }
1814
1815 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
b497549a 1816
13a9f6c6 1817 ourport = &s3c24xx_serial_ports[index];
da121506 1818
26c919e1
TA		 1819 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1820 if (!ourport->drv_data) {
1821 dev_err(&pdev->dev, "could not find driver data\n");
1822 return -ENODEV;
1823 }
da121506 1824
7cd88831 1825 ourport->baudclk = ERR_PTR(-EINVAL);
da121506 1826 ourport->info = ourport->drv_data->info;
574de559 1827 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
d4aab206 1828 dev_get_platdata(&pdev->dev) :
da121506
TA		 1829 ourport->drv_data->def_cfg;
1830
4622eb68
NKC		 1831 if (np)
1832 of_property_read_u32(np,
135f07c3
NKC		 1833 "samsung,uart-fifosize", &ourport->port.fifosize);
1834
2f1ba72d
RB		 1835 if (ourport->drv_data->fifosize[index])
1836 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1837 else if (ourport->info->fifosize)
1838 ourport->port.fifosize = ourport->info->fifosize;
da121506 1839
b497549a
BD		 1840 probe_index++;
1841
1842 dbg("%s: initialising port %p...\n", __func__, ourport);
1843
da121506 1844 ret = s3c24xx_serial_init_port(ourport, pdev);
b497549a 1845 if (ret < 0)
8ad711a9 1846 return ret;
b497549a 1847
6f134c3c
TB		 1848 if (!s3c24xx_uart_drv.state) {
1849 ret = uart_register_driver(&s3c24xx_uart_drv);
1850 if (ret < 0) {
1851 pr_err("Failed to register Samsung UART driver\n");
1852 return ret;
1853 }
1854 }
1855
b497549a
BD		 1856 dbg("%s: adding port\n", __func__);
1857 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
da121506 1858 platform_set_drvdata(pdev, &ourport->port);
b497549a 1859
0da3336f
HS		 1860 /*
1861 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1862 * so that a potential re-enablement through the pm-callback overlaps
1863 * and keeps the clock enabled in this case.
1864 */
1865 clk_disable_unprepare(ourport->clk);
1866
30555476
BD		 1867 ret = s3c24xx_serial_cpufreq_register(ourport);
1868 if (ret < 0)
da121506 1869 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
30555476 1870
b497549a 1871 return 0;
b497549a
BD		 1872}
1873
ae8d8a14 1874static int s3c24xx_serial_remove(struct platform_device *dev)
b497549a
BD		 1875{
1876 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1877
1878 if (port) {
30555476 1879 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
b497549a
BD		 1880 uart_remove_one_port(&s3c24xx_uart_drv, port);
1881 }
1882
6f134c3c
TB		 1883 uart_unregister_driver(&s3c24xx_uart_drv);
1884
b497549a
BD		 1885 return 0;
1886}
1887
b497549a 1888/* UART power management code */
aef7fe52
MH		 1889#ifdef CONFIG_PM_SLEEP
1890static int s3c24xx_serial_suspend(struct device *dev)
b497549a 1891{
aef7fe52 1892 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1893
1894 if (port)
1895 uart_suspend_port(&s3c24xx_uart_drv, port);
1896
1897 return 0;
1898}
1899
aef7fe52 1900static int s3c24xx_serial_resume(struct device *dev)
b497549a 1901{
aef7fe52 1902 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1903 struct s3c24xx_uart_port *ourport = to_ourport(port);
1904
1905 if (port) {
9484b009 1906 clk_prepare_enable(ourport->clk);
b497549a 1907 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
9484b009 1908 clk_disable_unprepare(ourport->clk);
b497549a
BD		 1909
1910 uart_resume_port(&s3c24xx_uart_drv, port);
1911 }
1912
1913 return 0;
1914}
aef7fe52 1915
d09a7308
MS		 1916static int s3c24xx_serial_resume_noirq(struct device *dev)
1917{
1918 struct uart_port *port = s3c24xx_dev_to_port(dev);
1919
1920 if (port) {
1921 /* restore IRQ mask */
1922 if (s3c24xx_serial_has_interrupt_mask(port)) {
1923 unsigned int uintm = 0xf;
1924 if (tx_enabled(port))
1925 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1926 if (rx_enabled(port))
1927 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1928 wr_regl(port, S3C64XX_UINTM, uintm);
1929 }
1930 }
1931
1932 return 0;
1933}
1934
aef7fe52
MH		 1935static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1936 .suspend = s3c24xx_serial_suspend,
1937 .resume = s3c24xx_serial_resume,
d09a7308 1938 .resume_noirq = s3c24xx_serial_resume_noirq,
aef7fe52 1939};
b882fc1b
KK		 1940#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1941
aef7fe52 1942#else /* !CONFIG_PM_SLEEP */
b882fc1b
KK		 1943
1944#define SERIAL_SAMSUNG_PM_OPS NULL
aef7fe52 1945#endif /* CONFIG_PM_SLEEP */
b497549a 1946
b497549a
BD		 1947/* Console code */
1948
1949#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1950
1951static struct uart_port *cons_uart;
1952
1953static int
1954s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1955{
1956 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1957 unsigned long ufstat, utrstat;
1958
1959 if (ufcon & S3C2410_UFCON_FIFOMODE) {
9ddc5b6f 1960 /* fifo mode - check amount of data in fifo registers... */
b497549a
BD		 1961
1962 ufstat = rd_regl(port, S3C2410_UFSTAT);
1963 return (ufstat & info->tx_fifofull) ? 0 : 1;
1964 }
1965
1966 /* in non-fifo mode, we go and use the tx buffer empty */
1967
1968 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1969 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1970}
1971
38adbc54
MS		 1972static bool
1973s3c24xx_port_configured(unsigned int ucon)
1974{
1975 /* consider the serial port configured if the tx/rx mode set */
1976 return (ucon & 0xf) != 0;
1977}
1978
93b5c032
JP		 1979#ifdef CONFIG_CONSOLE_POLL
1980/*
1981 * Console polling routines for writing and reading from the uart while
1982 * in an interrupt or debug context.
1983 */
1984
1985static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1986{
1987 struct s3c24xx_uart_port *ourport = to_ourport(port);
1988 unsigned int ufstat;
1989
1990 ufstat = rd_regl(port, S3C2410_UFSTAT);
1991 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1992 return NO_POLL_CHAR;
1993
1994 return rd_regb(port, S3C2410_URXH);
1995}
1996
1997static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1998 unsigned char c)
1999{
bb7f09ba
DA		 2000 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2001 unsigned int ucon = rd_regl(port, S3C2410_UCON);
38adbc54
MS		 2002
2003 /* not possible to xmit on unconfigured port */
2004 if (!s3c24xx_port_configured(ucon))
2005 return;
93b5c032
JP		 2006
2007 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2008 cpu_relax();
bb7f09ba 2009 wr_regb(port, S3C2410_UTXH, c);
93b5c032
JP		 2010}
2011
2012#endif /* CONFIG_CONSOLE_POLL */
2013
b497549a
BD		 2014static void
2015s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2016{
bb7f09ba 2017 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
38adbc54 2018
b497549a 2019 while (!s3c24xx_serial_console_txrdy(port, ufcon))
f94b0572 2020 cpu_relax();
bb7f09ba 2021 wr_regb(port, S3C2410_UTXH, ch);
b497549a
BD		 2022}
2023
2024static void
2025s3c24xx_serial_console_write(struct console *co, const char *s,
2026 unsigned int count)
2027{
ab88c8dc
DA		 2028 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2029
2030 /* not possible to xmit on unconfigured port */
2031 if (!s3c24xx_port_configured(ucon))
2032 return;
2033
b497549a
BD		 2034 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2035}
2036
2037static void __init
2038s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2039 int *parity, int *bits)
2040{
b497549a
BD		 2041 struct clk *clk;
2042 unsigned int ulcon;
2043 unsigned int ucon;
2044 unsigned int ubrdiv;
2045 unsigned long rate;
5f5a7a55
TA		 2046 unsigned int clk_sel;
2047 char clk_name[MAX_CLK_NAME_LENGTH];
b497549a
BD		 2048
2049 ulcon = rd_regl(port, S3C2410_ULCON);
2050 ucon = rd_regl(port, S3C2410_UCON);
2051 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2052
2053 dbg("s3c24xx_serial_get_options: port=%p\n"
2054 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2055 port, ulcon, ucon, ubrdiv);
2056
38adbc54 2057 if (s3c24xx_port_configured(ucon)) {
b497549a
BD		 2058 switch (ulcon & S3C2410_LCON_CSMASK) {
2059 case S3C2410_LCON_CS5:
2060 *bits = 5;
2061 break;
2062 case S3C2410_LCON_CS6:
2063 *bits = 6;
2064 break;
2065 case S3C2410_LCON_CS7:
2066 *bits = 7;
2067 break;
b497549a 2068 case S3C2410_LCON_CS8:
3bcce591 2069 default:
b497549a
BD		 2070 *bits = 8;
2071 break;
2072 }
2073
2074 switch (ulcon & S3C2410_LCON_PMASK) {
2075 case S3C2410_LCON_PEVEN:
2076 *parity = 'e';
2077 break;
2078
2079 case S3C2410_LCON_PODD:
2080 *parity = 'o';
2081 break;
2082
2083 case S3C2410_LCON_PNONE:
2084 default:
2085 *parity = 'n';
2086 }
2087
2088 /* now calculate the baud rate */
2089
5f5a7a55
TA		 2090 clk_sel = s3c24xx_serial_getsource(port);
2091 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
b497549a 2092
5f5a7a55 2093 clk = clk_get(port->dev, clk_name);
7cd88831 2094 if (!IS_ERR(clk))
5f5a7a55 2095 rate = clk_get_rate(clk);
b497549a
BD		 2096 else
2097 rate = 1;
2098
b497549a
BD		 2099 *baud = rate / (16 * (ubrdiv + 1));
2100 dbg("calculated baud %d\n", *baud);
2101 }
2102
2103}
2104
b497549a
BD		 2105static int __init
2106s3c24xx_serial_console_setup(struct console *co, char *options)
2107{
2108 struct uart_port *port;
2109 int baud = 9600;
2110 int bits = 8;
2111 int parity = 'n';
2112 int flow = 'n';
2113
2114 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2115 co, co->index, options);
2116
2117 /* is this a valid port */
2118
03d5e77b 2119 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
b497549a
BD		 2120 co->index = 0;
2121
2122 port = &s3c24xx_serial_ports[co->index].port;
2123
2124 /* is the port configured? */
2125
ee430f16
TA		 2126 if (port->mapbase == 0x0)
2127 return -ENODEV;
b497549a
BD		 2128
2129 cons_uart = port;
2130
2131 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2132
2133 /*
2134 * Check whether an invalid uart number has been specified, and
2135 * if so, search for the first available port that does have
2136 * console support.
2137 */
2138 if (options)
2139 uart_parse_options(options, &baud, &parity, &bits, &flow);
2140 else
2141 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2142
2143 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2144
2145 return uart_set_options(port, co, baud, parity, bits, flow);
2146}
2147
b497549a
BD		 2148static struct console s3c24xx_serial_console = {
2149 .name = S3C24XX_SERIAL_NAME,
2150 .device = uart_console_device,
2151 .flags = CON_PRINTBUFFER,
2152 .index = -1,
2153 .write = s3c24xx_serial_console_write,
5822a5df
TA		 2154 .setup = s3c24xx_serial_console_setup,
2155 .data = &s3c24xx_uart_drv,
b497549a 2156};
da121506
TA		 2157#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2158
2159#ifdef CONFIG_CPU_S3C2410
2160static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2161 .info = &(struct s3c24xx_uart_info) {
2162 .name = "Samsung S3C2410 UART",
2163 .type = PORT_S3C2410,
2164 .fifosize = 16,
2165 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2166 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2167 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2168 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2169 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2170 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2171 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2172 .num_clks = 2,
2173 .clksel_mask = S3C2410_UCON_CLKMASK,
2174 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2175 },
2176 .def_cfg = &(struct s3c2410_uartcfg) {
2177 .ucon = S3C2410_UCON_DEFAULT,
2178 .ufcon = S3C2410_UFCON_DEFAULT,
2179 },
2180};
2181#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2182#else
2183#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2184#endif
b497549a 2185
da121506
TA		 2186#ifdef CONFIG_CPU_S3C2412
2187static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2188 .info = &(struct s3c24xx_uart_info) {
2189 .name = "Samsung S3C2412 UART",
2190 .type = PORT_S3C2412,
2191 .fifosize = 64,
2192 .has_divslot = 1,
2193 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2194 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2195 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2196 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2197 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2198 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2199 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2200 .num_clks = 4,
2201 .clksel_mask = S3C2412_UCON_CLKMASK,
2202 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2203 },
2204 .def_cfg = &(struct s3c2410_uartcfg) {
2205 .ucon = S3C2410_UCON_DEFAULT,
2206 .ufcon = S3C2410_UFCON_DEFAULT,
2207 },
2208};
2209#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2210#else
2211#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2212#endif
b497549a 2213
da121506 2214#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
b26469a8 2215 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
da121506
TA		 2216static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2217 .info = &(struct s3c24xx_uart_info) {
2218 .name = "Samsung S3C2440 UART",
2219 .type = PORT_S3C2440,
2220 .fifosize = 64,
2221 .has_divslot = 1,
2222 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2223 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2224 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2225 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2226 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2227 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2228 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2229 .num_clks = 4,
2230 .clksel_mask = S3C2412_UCON_CLKMASK,
2231 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2232 },
2233 .def_cfg = &(struct s3c2410_uartcfg) {
2234 .ucon = S3C2410_UCON_DEFAULT,
2235 .ufcon = S3C2410_UFCON_DEFAULT,
2236 },
2237};
2238#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2239#else
2240#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2241#endif
b497549a 2242
953b53a7 2243#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
da121506
TA		 2244static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2245 .info = &(struct s3c24xx_uart_info) {
2246 .name = "Samsung S3C6400 UART",
2247 .type = PORT_S3C6400,
2248 .fifosize = 64,
2249 .has_divslot = 1,
2250 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2251 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2252 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2253 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2254 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2255 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2256 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2257 .num_clks = 4,
2258 .clksel_mask = S3C6400_UCON_CLKMASK,
2259 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2260 },
2261 .def_cfg = &(struct s3c2410_uartcfg) {
2262 .ucon = S3C2410_UCON_DEFAULT,
2263 .ufcon = S3C2410_UFCON_DEFAULT,
2264 },
2265};
2266#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2267#else
2268#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2269#endif
b497549a 2270
da121506
TA		 2271#ifdef CONFIG_CPU_S5PV210
2272static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2273 .info = &(struct s3c24xx_uart_info) {
2274 .name = "Samsung S5PV210 UART",
2275 .type = PORT_S3C6400,
2276 .has_divslot = 1,
2277 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2278 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2279 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2280 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2281 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2282 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2283 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2284 .num_clks = 2,
2285 .clksel_mask = S5PV210_UCON_CLKMASK,
2286 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2287 },
2288 .def_cfg = &(struct s3c2410_uartcfg) {
2289 .ucon = S5PV210_UCON_DEFAULT,
2290 .ufcon = S5PV210_UFCON_DEFAULT,
2291 },
2292 .fifosize = { 256, 64, 16, 16 },
2293};
2294#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2295#else
2296#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2297#endif
b497549a 2298
33f88136 2299#if defined(CONFIG_ARCH_EXYNOS)
31ec77ac
CC		 2300#define EXYNOS_COMMON_SERIAL_DRV_DATA \
2301 .info = &(struct s3c24xx_uart_info) { \
2302 .name = "Samsung Exynos UART", \
2303 .type = PORT_S3C6400, \
2304 .has_divslot = 1, \
2305 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2306 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2307 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2308 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2309 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2310 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2311 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2312 .num_clks = 1, \
2313 .clksel_mask = 0, \
2314 .clksel_shift = 0, \
2315 }, \
2316 .def_cfg = &(struct s3c2410_uartcfg) { \
2317 .ucon = S5PV210_UCON_DEFAULT, \
2318 .ufcon = S5PV210_UFCON_DEFAULT, \
2319 .has_fracval = 1, \
2320 } \
2321
da121506 2322static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
31ec77ac 2323 EXYNOS_COMMON_SERIAL_DRV_DATA,
da121506
TA		 2324 .fifosize = { 256, 64, 16, 16 },
2325};
31ec77ac
CC		 2326
2327static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2328 EXYNOS_COMMON_SERIAL_DRV_DATA,
2329 .fifosize = { 64, 256, 16, 256 },
2330};
2331
da121506 2332#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
31ec77ac 2333#define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
da121506
TA		 2334#else
2335#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
31ec77ac 2336#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
da121506 2337#endif
b497549a 2338
da121506
TA		 2339static struct platform_device_id s3c24xx_serial_driver_ids[] = {
2340 {
2341 .name = "s3c2410-uart",
2342 .driver_data = S3C2410_SERIAL_DRV_DATA,
2343 }, {
2344 .name = "s3c2412-uart",
2345 .driver_data = S3C2412_SERIAL_DRV_DATA,
2346 }, {
2347 .name = "s3c2440-uart",
2348 .driver_data = S3C2440_SERIAL_DRV_DATA,
2349 }, {
2350 .name = "s3c6400-uart",
2351 .driver_data = S3C6400_SERIAL_DRV_DATA,
2352 }, {
2353 .name = "s5pv210-uart",
2354 .driver_data = S5PV210_SERIAL_DRV_DATA,
2355 }, {
2356 .name = "exynos4210-uart",
2357 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
31ec77ac
CC		 2358 }, {
2359 .name = "exynos5433-uart",
2360 .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
da121506
TA		 2361 },
2362 { },
2363};
2364MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2365
26c919e1
TA		 2366#ifdef CONFIG_OF
2367static const struct of_device_id s3c24xx_uart_dt_match[] = {
666ca0b9
HS		 2368 { .compatible = "samsung,s3c2410-uart",
2369 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2370 { .compatible = "samsung,s3c2412-uart",
2371 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2372 { .compatible = "samsung,s3c2440-uart",
2373 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2374 { .compatible = "samsung,s3c6400-uart",
2375 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2376 { .compatible = "samsung,s5pv210-uart",
2377 .data = (void *)S5PV210_SERIAL_DRV_DATA },
26c919e1 2378 { .compatible = "samsung,exynos4210-uart",
a169a888 2379 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
31ec77ac
CC		 2380 { .compatible = "samsung,exynos5433-uart",
2381 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
26c919e1
TA		 2382 {},
2383};
2384MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
26c919e1
TA		 2385#endif
2386
da121506
TA		 2387static struct platform_driver samsung_serial_driver = {
2388 .probe = s3c24xx_serial_probe,
2d47b716 2389 .remove = s3c24xx_serial_remove,
da121506
TA		 2390 .id_table = s3c24xx_serial_driver_ids,
2391 .driver = {
2392 .name = "samsung-uart",
da121506 2393 .pm = SERIAL_SAMSUNG_PM_OPS,
905f4ba2 2394 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
da121506
TA		 2395 },
2396};
b497549a 2397
6f134c3c 2398module_platform_driver(samsung_serial_driver);
b497549a 2399
c3bda295 2400#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
b94ba032
TF		 2401/*
2402 * Early console.
2403 */
2404
2405struct samsung_early_console_data {
2406 u32 txfull_mask;
2407};
2408
2409static void samsung_early_busyuart(struct uart_port *port)
2410{
2411 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2412 ;
2413}
2414
2415static void samsung_early_busyuart_fifo(struct uart_port *port)
2416{
2417 struct samsung_early_console_data *data = port->private_data;
2418
2419 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2420 ;
2421}
2422
2423static void samsung_early_putc(struct uart_port *port, int c)
2424{
2425 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2426 samsung_early_busyuart_fifo(port);
2427 else
2428 samsung_early_busyuart(port);
2429
2430 writeb(c, port->membase + S3C2410_UTXH);
2431}
2432
2433static void samsung_early_write(struct console *con, const char *s, unsigned n)
2434{
2435 struct earlycon_device *dev = con->data;
2436
2437 uart_console_write(&dev->port, s, n, samsung_early_putc);
2438}
2439
2440static int __init samsung_early_console_setup(struct earlycon_device *device,
2441 const char *opt)
2442{
2443 if (!device->port.membase)
2444 return -ENODEV;
2445
2446 device->con->write = samsung_early_write;
2447 return 0;
2448}
2449
2450/* S3C2410 */
2451static struct samsung_early_console_data s3c2410_early_console_data = {
2452 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2453};
2454
2455static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2456 const char *opt)
2457{
2458 device->port.private_data = &s3c2410_early_console_data;
2459 return samsung_early_console_setup(device, opt);
2460}
2461OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2462 s3c2410_early_console_setup);
2463EARLYCON_DECLARE(s3c2410, s3c2410_early_console_setup);
2464
2465/* S3C2412, S3C2440, S3C64xx */
2466static struct samsung_early_console_data s3c2440_early_console_data = {
2467 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2468};
2469
2470static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2471 const char *opt)
2472{
2473 device->port.private_data = &s3c2440_early_console_data;
2474 return samsung_early_console_setup(device, opt);
2475}
2476OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2477 s3c2440_early_console_setup);
2478OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2479 s3c2440_early_console_setup);
2480OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2481 s3c2440_early_console_setup);
2482EARLYCON_DECLARE(s3c2412, s3c2440_early_console_setup);
2483EARLYCON_DECLARE(s3c2440, s3c2440_early_console_setup);
2484EARLYCON_DECLARE(s3c6400, s3c2440_early_console_setup);
2485
2486/* S5PV210, EXYNOS */
2487static struct samsung_early_console_data s5pv210_early_console_data = {
2488 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2489};
2490
2491static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2492 const char *opt)
2493{
2494 device->port.private_data = &s5pv210_early_console_data;
2495 return samsung_early_console_setup(device, opt);
2496}
2497OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2498 s5pv210_early_console_setup);
2499OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2500 s5pv210_early_console_setup);
2501EARLYCON_DECLARE(s5pv210, s5pv210_early_console_setup);
2502EARLYCON_DECLARE(exynos4210, s5pv210_early_console_setup);
c3bda295 2503#endif
b94ba032 2504
da121506 2505MODULE_ALIAS("platform:samsung-uart");
b497549a
BD		 2506MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2507MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2508MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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