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Merge tag 's5pv210-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux...
[deliverable/linux.git] / drivers / tty / serial / samsung.c
CommitLineData
99edb3d1 1/*
b497549a
BD		 2 * Driver core for Samsung SoC onboard UARTs.
3 *
ccae941e 4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
b497549a
BD		 5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25*/
26
27#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28#define SUPPORT_SYSRQ
29#endif
30
31#include <linux/module.h>
32#include <linux/ioport.h>
33#include <linux/io.h>
34#include <linux/platform_device.h>
35#include <linux/init.h>
36#include <linux/sysrq.h>
37#include <linux/console.h>
38#include <linux/tty.h>
39#include <linux/tty_flip.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
9ee51f01 42#include <linux/serial_s3c.h>
b497549a
BD		 43#include <linux/delay.h>
44#include <linux/clk.h>
30555476 45#include <linux/cpufreq.h>
26c919e1 46#include <linux/of.h>
b497549a
BD		 47
48#include <asm/irq.h>
49
b497549a
BD		 50#include "samsung.h"
51
e4ac92df
JP		 52#if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
53 defined(CONFIG_DEBUG_LL) && \
54 !defined(MODULE)
55
56extern void printascii(const char *);
57
58__printf(1, 2)
59static void dbg(const char *fmt, ...)
60{
61 va_list va;
62 char buff[256];
63
64 va_start(va, fmt);
a859c8b2 65 vscnprintf(buff, sizeof(buff), fmt, va);
e4ac92df
JP		 66 va_end(va);
67
68 printascii(buff);
69}
70
71#else
72#define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
73#endif
74
b497549a
BD		 75/* UART name and device definitions */
76
77#define S3C24XX_SERIAL_NAME "ttySAC"
78#define S3C24XX_SERIAL_MAJOR 204
79#define S3C24XX_SERIAL_MINOR 64
80
b497549a
BD		 81/* macros to change one thing to another */
82
83#define tx_enabled(port) ((port)->unused[0])
84#define rx_enabled(port) ((port)->unused[1])
85
25985edc 86/* flag to ignore all characters coming in */
b497549a
BD		 87#define RXSTAT_DUMMY_READ (0x10000000)
88
89static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
90{
91 return container_of(port, struct s3c24xx_uart_port, port);
92}
93
94/* translate a port to the device name */
95
96static inline const char *s3c24xx_serial_portname(struct uart_port *port)
97{
98 return to_platform_device(port->dev)->name;
99}
100
101static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
102{
9303ac15 103 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
b497549a
BD		 104}
105
88bb4ea1
TA		 106/*
107 * s3c64xx and later SoC's include the interrupt mask and status registers in
108 * the controller itself, unlike the s3c24xx SoC's which have these registers
109 * in the interrupt controller. Check if the port type is s3c64xx or higher.
110 */
111static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
112{
113 return to_ourport(port)->info->type == PORT_S3C6400;
114}
115
b497549a
BD		 116static void s3c24xx_serial_rx_enable(struct uart_port *port)
117{
118 unsigned long flags;
119 unsigned int ucon, ufcon;
120 int count = 10000;
121
122 spin_lock_irqsave(&port->lock, flags);
123
124 while (--count && !s3c24xx_serial_txempty_nofifo(port))
125 udelay(100);
126
127 ufcon = rd_regl(port, S3C2410_UFCON);
128 ufcon |= S3C2410_UFCON_RESETRX;
129 wr_regl(port, S3C2410_UFCON, ufcon);
130
131 ucon = rd_regl(port, S3C2410_UCON);
132 ucon |= S3C2410_UCON_RXIRQMODE;
133 wr_regl(port, S3C2410_UCON, ucon);
134
135 rx_enabled(port) = 1;
136 spin_unlock_irqrestore(&port->lock, flags);
137}
138
139static void s3c24xx_serial_rx_disable(struct uart_port *port)
140{
141 unsigned long flags;
142 unsigned int ucon;
143
144 spin_lock_irqsave(&port->lock, flags);
145
146 ucon = rd_regl(port, S3C2410_UCON);
147 ucon &= ~S3C2410_UCON_RXIRQMODE;
148 wr_regl(port, S3C2410_UCON, ucon);
149
150 rx_enabled(port) = 0;
151 spin_unlock_irqrestore(&port->lock, flags);
152}
153
154static void s3c24xx_serial_stop_tx(struct uart_port *port)
155{
b73c289c
BD		 156 struct s3c24xx_uart_port *ourport = to_ourport(port);
157
b497549a 158 if (tx_enabled(port)) {
88bb4ea1
TA		 159 if (s3c24xx_serial_has_interrupt_mask(port))
160 __set_bit(S3C64XX_UINTM_TXD,
161 portaddrl(port, S3C64XX_UINTM));
162 else
163 disable_irq_nosync(ourport->tx_irq);
b497549a
BD		 164 tx_enabled(port) = 0;
165 if (port->flags & UPF_CONS_FLOW)
166 s3c24xx_serial_rx_enable(port);
167 }
168}
169
170static void s3c24xx_serial_start_tx(struct uart_port *port)
171{
b73c289c
BD		 172 struct s3c24xx_uart_port *ourport = to_ourport(port);
173
b497549a
BD		 174 if (!tx_enabled(port)) {
175 if (port->flags & UPF_CONS_FLOW)
176 s3c24xx_serial_rx_disable(port);
177
88bb4ea1
TA		 178 if (s3c24xx_serial_has_interrupt_mask(port))
179 __clear_bit(S3C64XX_UINTM_TXD,
180 portaddrl(port, S3C64XX_UINTM));
181 else
182 enable_irq(ourport->tx_irq);
b497549a
BD		 183 tx_enabled(port) = 1;
184 }
185}
186
b497549a
BD		 187static void s3c24xx_serial_stop_rx(struct uart_port *port)
188{
b73c289c
BD		 189 struct s3c24xx_uart_port *ourport = to_ourport(port);
190
b497549a
BD		 191 if (rx_enabled(port)) {
192 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
88bb4ea1
TA		 193 if (s3c24xx_serial_has_interrupt_mask(port))
194 __set_bit(S3C64XX_UINTM_RXD,
195 portaddrl(port, S3C64XX_UINTM));
196 else
197 disable_irq_nosync(ourport->rx_irq);
b497549a
BD		 198 rx_enabled(port) = 0;
199 }
200}
201
202static void s3c24xx_serial_enable_ms(struct uart_port *port)
203{
204}
205
206static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
207{
208 return to_ourport(port)->info;
209}
210
211static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
212{
4d84e970
TA		 213 struct s3c24xx_uart_port *ourport;
214
b497549a
BD		 215 if (port->dev == NULL)
216 return NULL;
217
4d84e970
TA		 218 ourport = container_of(port, struct s3c24xx_uart_port, port);
219 return ourport->cfg;
b497549a
BD		 220}
221
222static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
223 unsigned long ufstat)
224{
225 struct s3c24xx_uart_info *info = ourport->info;
226
227 if (ufstat & info->rx_fifofull)
da121506 228 return ourport->port.fifosize;
b497549a
BD		 229
230 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
231}
232
233
234/* ? - where has parity gone?? */
235#define S3C2410_UERSTAT_PARITY (0x1000)
236
237static irqreturn_t
238s3c24xx_serial_rx_chars(int irq, void *dev_id)
239{
240 struct s3c24xx_uart_port *ourport = dev_id;
241 struct uart_port *port = &ourport->port;
b497549a 242 unsigned int ufcon, ch, flag, ufstat, uerstat;
c15c3747 243 unsigned long flags;
b497549a
BD		 244 int max_count = 64;
245
c15c3747
TA		 246 spin_lock_irqsave(&port->lock, flags);
247
b497549a
BD		 248 while (max_count-- > 0) {
249 ufcon = rd_regl(port, S3C2410_UFCON);
250 ufstat = rd_regl(port, S3C2410_UFSTAT);
251
252 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
253 break;
254
255 uerstat = rd_regl(port, S3C2410_UERSTAT);
256 ch = rd_regb(port, S3C2410_URXH);
257
258 if (port->flags & UPF_CONS_FLOW) {
259 int txe = s3c24xx_serial_txempty_nofifo(port);
260
261 if (rx_enabled(port)) {
262 if (!txe) {
263 rx_enabled(port) = 0;
264 continue;
265 }
266 } else {
267 if (txe) {
268 ufcon |= S3C2410_UFCON_RESETRX;
269 wr_regl(port, S3C2410_UFCON, ufcon);
270 rx_enabled(port) = 1;
f5693ea2
VK		 271 spin_unlock_irqrestore(&port->lock,
272 flags);
b497549a
BD		 273 goto out;
274 }
275 continue;
276 }
277 }
278
279 /* insert the character into the buffer */
280
281 flag = TTY_NORMAL;
282 port->icount.rx++;
283
284 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
285 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
286 ch, uerstat);
287
288 /* check for break */
289 if (uerstat & S3C2410_UERSTAT_BREAK) {
290 dbg("break!\n");
291 port->icount.brk++;
292 if (uart_handle_break(port))
9303ac15 293 goto ignore_char;
b497549a
BD		 294 }
295
296 if (uerstat & S3C2410_UERSTAT_FRAME)
297 port->icount.frame++;
298 if (uerstat & S3C2410_UERSTAT_OVERRUN)
299 port->icount.overrun++;
300
301 uerstat &= port->read_status_mask;
302
303 if (uerstat & S3C2410_UERSTAT_BREAK)
304 flag = TTY_BREAK;
305 else if (uerstat & S3C2410_UERSTAT_PARITY)
306 flag = TTY_PARITY;
307 else if (uerstat & (S3C2410_UERSTAT_FRAME |
308 S3C2410_UERSTAT_OVERRUN))
309 flag = TTY_FRAME;
310 }
311
312 if (uart_handle_sysrq_char(port, ch))
313 goto ignore_char;
314
315 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
316 ch, flag);
317
318 ignore_char:
319 continue;
320 }
f5693ea2
VK		 321
322 spin_unlock_irqrestore(&port->lock, flags);
2e124b4a 323 tty_flip_buffer_push(&port->state->port);
b497549a
BD		 324
325 out:
326 return IRQ_HANDLED;
327}
328
329static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
330{
331 struct s3c24xx_uart_port *ourport = id;
332 struct uart_port *port = &ourport->port;
ebd2c8f6 333 struct circ_buf *xmit = &port->state->xmit;
c15c3747 334 unsigned long flags;
b497549a
BD		 335 int count = 256;
336
c15c3747
TA		 337 spin_lock_irqsave(&port->lock, flags);
338
b497549a
BD		 339 if (port->x_char) {
340 wr_regb(port, S3C2410_UTXH, port->x_char);
341 port->icount.tx++;
342 port->x_char = 0;
343 goto out;
344 }
345
25985edc 346 /* if there isn't anything more to transmit, or the uart is now
b497549a
BD		 347 * stopped, disable the uart and exit
348 */
349
350 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
351 s3c24xx_serial_stop_tx(port);
352 goto out;
353 }
354
355 /* try and drain the buffer... */
356
357 while (!uart_circ_empty(xmit) && count-- > 0) {
358 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
359 break;
360
361 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
362 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
363 port->icount.tx++;
364 }
365
c15c3747
TA		 366 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
367 spin_unlock(&port->lock);
b497549a 368 uart_write_wakeup(port);
c15c3747
TA		 369 spin_lock(&port->lock);
370 }
b497549a
BD		 371
372 if (uart_circ_empty(xmit))
373 s3c24xx_serial_stop_tx(port);
374
375 out:
c15c3747 376 spin_unlock_irqrestore(&port->lock, flags);
b497549a
BD		 377 return IRQ_HANDLED;
378}
379
88bb4ea1
TA		 380/* interrupt handler for s3c64xx and later SoC's.*/
381static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
382{
383 struct s3c24xx_uart_port *ourport = id;
384 struct uart_port *port = &ourport->port;
385 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
88bb4ea1
TA		 386 irqreturn_t ret = IRQ_HANDLED;
387
88bb4ea1
TA		 388 if (pend & S3C64XX_UINTM_RXD_MSK) {
389 ret = s3c24xx_serial_rx_chars(irq, id);
390 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
391 }
392 if (pend & S3C64XX_UINTM_TXD_MSK) {
393 ret = s3c24xx_serial_tx_chars(irq, id);
394 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
395 }
88bb4ea1
TA		 396 return ret;
397}
398
b497549a
BD		 399static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
400{
401 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
402 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
403 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
404
405 if (ufcon & S3C2410_UFCON_FIFOMODE) {
406 if ((ufstat & info->tx_fifomask) != 0 ||
407 (ufstat & info->tx_fifofull))
408 return 0;
409
410 return 1;
411 }
412
413 return s3c24xx_serial_txempty_nofifo(port);
414}
415
416/* no modem control lines */
417static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
418{
419 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
420
421 if (umstat & S3C2410_UMSTAT_CTS)
422 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
423 else
424 return TIOCM_CAR | TIOCM_DSR;
425}
426
427static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
428{
2d1e5a48
JMG		 429 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
430
431 if (mctrl & TIOCM_RTS)
432 umcon |= S3C2410_UMCOM_RTS_LOW;
433 else
434 umcon &= ~S3C2410_UMCOM_RTS_LOW;
435
436 wr_regl(port, S3C2410_UMCON, umcon);
b497549a
BD		 437}
438
439static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
440{
441 unsigned long flags;
442 unsigned int ucon;
443
444 spin_lock_irqsave(&port->lock, flags);
445
446 ucon = rd_regl(port, S3C2410_UCON);
447
448 if (break_state)
449 ucon |= S3C2410_UCON_SBREAK;
450 else
451 ucon &= ~S3C2410_UCON_SBREAK;
452
453 wr_regl(port, S3C2410_UCON, ucon);
454
455 spin_unlock_irqrestore(&port->lock, flags);
456}
457
458static void s3c24xx_serial_shutdown(struct uart_port *port)
459{
460 struct s3c24xx_uart_port *ourport = to_ourport(port);
461
462 if (ourport->tx_claimed) {
88bb4ea1
TA		 463 if (!s3c24xx_serial_has_interrupt_mask(port))
464 free_irq(ourport->tx_irq, ourport);
b497549a
BD		 465 tx_enabled(port) = 0;
466 ourport->tx_claimed = 0;
467 }
468
469 if (ourport->rx_claimed) {
88bb4ea1
TA		 470 if (!s3c24xx_serial_has_interrupt_mask(port))
471 free_irq(ourport->rx_irq, ourport);
b497549a
BD		 472 ourport->rx_claimed = 0;
473 rx_enabled(port) = 0;
474 }
b497549a 475
88bb4ea1
TA		 476 /* Clear pending interrupts and mask all interrupts */
477 if (s3c24xx_serial_has_interrupt_mask(port)) {
b6ad2935
TF		 478 free_irq(port->irq, ourport);
479
88bb4ea1
TA		 480 wr_regl(port, S3C64XX_UINTP, 0xf);
481 wr_regl(port, S3C64XX_UINTM, 0xf);
482 }
483}
b497549a
BD		 484
485static int s3c24xx_serial_startup(struct uart_port *port)
486{
487 struct s3c24xx_uart_port *ourport = to_ourport(port);
488 int ret;
489
e4ac92df
JP		 490 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
491 port, (unsigned long long)port->mapbase, port->membase);
b497549a
BD		 492
493 rx_enabled(port) = 1;
494
b73c289c 495 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
b497549a
BD		 496 s3c24xx_serial_portname(port), ourport);
497
498 if (ret != 0) {
d20925e1 499 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
b497549a
BD		 500 return ret;
501 }
502
503 ourport->rx_claimed = 1;
504
505 dbg("requesting tx irq...\n");
506
507 tx_enabled(port) = 1;
508
b73c289c 509 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
b497549a
BD		 510 s3c24xx_serial_portname(port), ourport);
511
512 if (ret) {
d20925e1 513 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
b497549a
BD		 514 goto err;
515 }
516
517 ourport->tx_claimed = 1;
518
519 dbg("s3c24xx_serial_startup ok\n");
520
521 /* the port reset code should have done the correct
522 * register setup for the port controls */
523
524 return ret;
525
526 err:
527 s3c24xx_serial_shutdown(port);
528 return ret;
529}
530
88bb4ea1
TA		 531static int s3c64xx_serial_startup(struct uart_port *port)
532{
533 struct s3c24xx_uart_port *ourport = to_ourport(port);
534 int ret;
535
e4ac92df
JP		 536 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
537 port, (unsigned long long)port->mapbase, port->membase);
88bb4ea1 538
b6ad2935
TF		 539 wr_regl(port, S3C64XX_UINTM, 0xf);
540
88bb4ea1
TA		 541 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
542 s3c24xx_serial_portname(port), ourport);
543 if (ret) {
d20925e1 544 dev_err(port->dev, "cannot get irq %d\n", port->irq);
88bb4ea1
TA		 545 return ret;
546 }
547
548 /* For compatibility with s3c24xx Soc's */
549 rx_enabled(port) = 1;
550 ourport->rx_claimed = 1;
551 tx_enabled(port) = 0;
552 ourport->tx_claimed = 1;
553
554 /* Enable Rx Interrupt */
555 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
556 dbg("s3c64xx_serial_startup ok\n");
557 return ret;
558}
559
b497549a
BD		 560/* power power management control */
561
562static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
563 unsigned int old)
564{
565 struct s3c24xx_uart_port *ourport = to_ourport(port);
566
30555476
BD		 567 ourport->pm_level = level;
568
b497549a
BD		 569 switch (level) {
570 case 3:
7cd88831 571 if (!IS_ERR(ourport->baudclk))
9484b009 572 clk_disable_unprepare(ourport->baudclk);
b497549a 573
9484b009 574 clk_disable_unprepare(ourport->clk);
b497549a
BD		 575 break;
576
577 case 0:
9484b009 578 clk_prepare_enable(ourport->clk);
b497549a 579
7cd88831 580 if (!IS_ERR(ourport->baudclk))
9484b009 581 clk_prepare_enable(ourport->baudclk);
b497549a
BD		 582
583 break;
584 default:
d20925e1 585 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
b497549a
BD		 586 }
587}
588
589/* baud rate calculation
590 *
591 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
592 * of different sources, including the peripheral clock ("pclk") and an
593 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
594 * with a programmable extra divisor.
595 *
596 * The following code goes through the clock sources, and calculates the
597 * baud clocks (and the resultant actual baud rates) and then tries to
598 * pick the closest one and select that.
599 *
600*/
601
5f5a7a55 602#define MAX_CLK_NAME_LENGTH 15
b497549a 603
5f5a7a55 604static inline int s3c24xx_serial_getsource(struct uart_port *port)
b497549a
BD		 605{
606 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
5f5a7a55 607 unsigned int ucon;
b497549a 608
5f5a7a55
TA		 609 if (info->num_clks == 1)
610 return 0;
b497549a 611
5f5a7a55
TA		 612 ucon = rd_regl(port, S3C2410_UCON);
613 ucon &= info->clksel_mask;
614 return ucon >> info->clksel_shift;
b497549a
BD		 615}
616
5f5a7a55
TA		 617static void s3c24xx_serial_setsource(struct uart_port *port,
618 unsigned int clk_sel)
b497549a 619{
5f5a7a55
TA		 620 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
621 unsigned int ucon;
b497549a 622
5f5a7a55
TA		 623 if (info->num_clks == 1)
624 return;
090f848d 625
5f5a7a55
TA		 626 ucon = rd_regl(port, S3C2410_UCON);
627 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
628 return;
b497549a 629
5f5a7a55
TA		 630 ucon &= ~info->clksel_mask;
631 ucon |= clk_sel << info->clksel_shift;
632 wr_regl(port, S3C2410_UCON, ucon);
b497549a
BD		 633}
634
5f5a7a55
TA		 635static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
636 unsigned int req_baud, struct clk **best_clk,
637 unsigned int *clk_num)
b497549a 638{
5f5a7a55
TA		 639 struct s3c24xx_uart_info *info = ourport->info;
640 struct clk *clk;
641 unsigned long rate;
642 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
643 char clkname[MAX_CLK_NAME_LENGTH];
644 int calc_deviation, deviation = (1 << 30) - 1;
645
5f5a7a55
TA		 646 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
647 ourport->info->def_clk_sel;
648 for (cnt = 0; cnt < info->num_clks; cnt++) {
649 if (!(clk_sel & (1 << cnt)))
650 continue;
651
652 sprintf(clkname, "clk_uart_baud%d", cnt);
653 clk = clk_get(ourport->port.dev, clkname);
7cd88831 654 if (IS_ERR(clk))
5f5a7a55
TA		 655 continue;
656
657 rate = clk_get_rate(clk);
658 if (!rate)
659 continue;
660
661 if (ourport->info->has_divslot) {
662 unsigned long div = rate / req_baud;
663
664 /* The UDIVSLOT register on the newer UARTs allows us to
665 * get a divisor adjustment of 1/16th on the baud clock.
666 *
667 * We don't keep the UDIVSLOT value (the 16ths we
668 * calculated by not multiplying the baud by 16) as it
669 * is easy enough to recalculate.
670 */
671
672 quot = div / 16;
673 baud = rate / div;
674 } else {
675 quot = (rate + (8 * req_baud)) / (16 * req_baud);
676 baud = rate / (quot * 16);
b497549a 677 }
5f5a7a55 678 quot--;
b497549a 679
5f5a7a55
TA		 680 calc_deviation = req_baud - baud;
681 if (calc_deviation < 0)
682 calc_deviation = -calc_deviation;
b497549a 683
5f5a7a55
TA		 684 if (calc_deviation < deviation) {
685 *best_clk = clk;
686 best_quot = quot;
687 *clk_num = cnt;
688 deviation = calc_deviation;
b497549a
BD		 689 }
690 }
691
5f5a7a55 692 return best_quot;
b497549a
BD		 693}
694
090f848d
BD		 695/* udivslot_table[]
696 *
697 * This table takes the fractional value of the baud divisor and gives
698 * the recommended setting for the UDIVSLOT register.
699 */
700static u16 udivslot_table[16] = {
701 [0] = 0x0000,
702 [1] = 0x0080,
703 [2] = 0x0808,
704 [3] = 0x0888,
705 [4] = 0x2222,
706 [5] = 0x4924,
707 [6] = 0x4A52,
708 [7] = 0x54AA,
709 [8] = 0x5555,
710 [9] = 0xD555,
711 [10] = 0xD5D5,
712 [11] = 0xDDD5,
713 [12] = 0xDDDD,
714 [13] = 0xDFDD,
715 [14] = 0xDFDF,
716 [15] = 0xFFDF,
717};
718
b497549a
BD		 719static void s3c24xx_serial_set_termios(struct uart_port *port,
720 struct ktermios *termios,
721 struct ktermios *old)
722{
723 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
724 struct s3c24xx_uart_port *ourport = to_ourport(port);
7cd88831 725 struct clk *clk = ERR_PTR(-EINVAL);
b497549a 726 unsigned long flags;
5f5a7a55 727 unsigned int baud, quot, clk_sel = 0;
b497549a
BD		 728 unsigned int ulcon;
729 unsigned int umcon;
090f848d 730 unsigned int udivslot = 0;
b497549a
BD		 731
732 /*
733 * We don't support modem control lines.
734 */
735 termios->c_cflag &= ~(HUPCL | CMSPAR);
736 termios->c_cflag |= CLOCAL;
737
738 /*
739 * Ask the core to calculate the divisor for us.
740 */
741
742 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
5f5a7a55 743 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
b497549a
BD		 744 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
745 quot = port->custom_divisor;
7cd88831 746 if (IS_ERR(clk))
5f5a7a55 747 return;
b497549a
BD		 748
749 /* check to see if we need to change clock source */
750
5f5a7a55
TA		 751 if (ourport->baudclk != clk) {
752 s3c24xx_serial_setsource(port, clk_sel);
b497549a 753
7cd88831 754 if (!IS_ERR(ourport->baudclk)) {
9484b009 755 clk_disable_unprepare(ourport->baudclk);
7cd88831 756 ourport->baudclk = ERR_PTR(-EINVAL);
b497549a
BD		 757 }
758
9484b009 759 clk_prepare_enable(clk);
b497549a 760
b497549a 761 ourport->baudclk = clk;
30555476 762 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
b497549a
BD		 763 }
764
090f848d
BD		 765 if (ourport->info->has_divslot) {
766 unsigned int div = ourport->baudclk_rate / baud;
767
8b526ae4
JL		 768 if (cfg->has_fracval) {
769 udivslot = (div & 15);
770 dbg("fracval = %04x\n", udivslot);
771 } else {
772 udivslot = udivslot_table[div & 15];
773 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
774 }
090f848d
BD		 775 }
776
b497549a
BD		 777 switch (termios->c_cflag & CSIZE) {
778 case CS5:
779 dbg("config: 5bits/char\n");
780 ulcon = S3C2410_LCON_CS5;
781 break;
782 case CS6:
783 dbg("config: 6bits/char\n");
784 ulcon = S3C2410_LCON_CS6;
785 break;
786 case CS7:
787 dbg("config: 7bits/char\n");
788 ulcon = S3C2410_LCON_CS7;
789 break;
790 case CS8:
791 default:
792 dbg("config: 8bits/char\n");
793 ulcon = S3C2410_LCON_CS8;
794 break;
795 }
796
797 /* preserve original lcon IR settings */
798 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
799
800 if (termios->c_cflag & CSTOPB)
801 ulcon |= S3C2410_LCON_STOPB;
802
b497549a
BD		 803 if (termios->c_cflag & PARENB) {
804 if (termios->c_cflag & PARODD)
805 ulcon |= S3C2410_LCON_PODD;
806 else
807 ulcon |= S3C2410_LCON_PEVEN;
808 } else {
809 ulcon |= S3C2410_LCON_PNONE;
810 }
811
812 spin_lock_irqsave(&port->lock, flags);
813
090f848d
BD		 814 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
815 ulcon, quot, udivslot);
b497549a
BD		 816
817 wr_regl(port, S3C2410_ULCON, ulcon);
818 wr_regl(port, S3C2410_UBRDIV, quot);
2d1e5a48
JMG		 819
820 umcon = rd_regl(port, S3C2410_UMCON);
821 if (termios->c_cflag & CRTSCTS) {
822 umcon |= S3C2410_UMCOM_AFC;
823 /* Disable RTS when RX FIFO contains 63 bytes */
824 umcon &= ~S3C2412_UMCON_AFC_8;
825 } else {
826 umcon &= ~S3C2410_UMCOM_AFC;
827 }
b497549a
BD		 828 wr_regl(port, S3C2410_UMCON, umcon);
829
090f848d
BD		 830 if (ourport->info->has_divslot)
831 wr_regl(port, S3C2443_DIVSLOT, udivslot);
832
b497549a
BD		 833 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
834 rd_regl(port, S3C2410_ULCON),
835 rd_regl(port, S3C2410_UCON),
836 rd_regl(port, S3C2410_UFCON));
837
838 /*
839 * Update the per-port timeout.
840 */
841 uart_update_timeout(port, termios->c_cflag, baud);
842
843 /*
844 * Which character status flags are we interested in?
845 */
846 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
847 if (termios->c_iflag & INPCK)
848 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
849
850 /*
851 * Which character status flags should we ignore?
852 */
853 port->ignore_status_mask = 0;
854 if (termios->c_iflag & IGNPAR)
855 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
856 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
857 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
858
859 /*
860 * Ignore all characters if CREAD is not set.
861 */
862 if ((termios->c_cflag & CREAD) == 0)
863 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
864
865 spin_unlock_irqrestore(&port->lock, flags);
866}
867
868static const char *s3c24xx_serial_type(struct uart_port *port)
869{
870 switch (port->type) {
871 case PORT_S3C2410:
872 return "S3C2410";
873 case PORT_S3C2440:
874 return "S3C2440";
875 case PORT_S3C2412:
876 return "S3C2412";
b690ace5
BD		 877 case PORT_S3C6400:
878 return "S3C6400/10";
b497549a
BD		 879 default:
880 return NULL;
881 }
882}
883
884#define MAP_SIZE (0x100)
885
886static void s3c24xx_serial_release_port(struct uart_port *port)
887{
888 release_mem_region(port->mapbase, MAP_SIZE);
889}
890
891static int s3c24xx_serial_request_port(struct uart_port *port)
892{
893 const char *name = s3c24xx_serial_portname(port);
894 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
895}
896
897static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
898{
899 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
900
901 if (flags & UART_CONFIG_TYPE &&
902 s3c24xx_serial_request_port(port) == 0)
903 port->type = info->type;
904}
905
906/*
907 * verify the new serial_struct (for TIOCSSERIAL).
908 */
909static int
910s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
911{
912 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
913
914 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
915 return -EINVAL;
916
917 return 0;
918}
919
920
921#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
922
923static struct console s3c24xx_serial_console;
924
93b5c032
JP		 925static int __init s3c24xx_serial_console_init(void)
926{
927 register_console(&s3c24xx_serial_console);
928 return 0;
929}
930console_initcall(s3c24xx_serial_console_init);
931
b497549a
BD		 932#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
933#else
934#define S3C24XX_SERIAL_CONSOLE NULL
935#endif
936
84f57d9e 937#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 938static int s3c24xx_serial_get_poll_char(struct uart_port *port);
939static void s3c24xx_serial_put_poll_char(struct uart_port *port,
940 unsigned char c);
941#endif
942
b497549a
BD		 943static struct uart_ops s3c24xx_serial_ops = {
944 .pm = s3c24xx_serial_pm,
945 .tx_empty = s3c24xx_serial_tx_empty,
946 .get_mctrl = s3c24xx_serial_get_mctrl,
947 .set_mctrl = s3c24xx_serial_set_mctrl,
948 .stop_tx = s3c24xx_serial_stop_tx,
949 .start_tx = s3c24xx_serial_start_tx,
950 .stop_rx = s3c24xx_serial_stop_rx,
951 .enable_ms = s3c24xx_serial_enable_ms,
952 .break_ctl = s3c24xx_serial_break_ctl,
953 .startup = s3c24xx_serial_startup,
954 .shutdown = s3c24xx_serial_shutdown,
955 .set_termios = s3c24xx_serial_set_termios,
956 .type = s3c24xx_serial_type,
957 .release_port = s3c24xx_serial_release_port,
958 .request_port = s3c24xx_serial_request_port,
959 .config_port = s3c24xx_serial_config_port,
960 .verify_port = s3c24xx_serial_verify_port,
84f57d9e 961#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 962 .poll_get_char = s3c24xx_serial_get_poll_char,
963 .poll_put_char = s3c24xx_serial_put_poll_char,
964#endif
b497549a
BD		 965};
966
b497549a
BD		 967static struct uart_driver s3c24xx_uart_drv = {
968 .owner = THIS_MODULE,
2cf0c58e 969 .driver_name = "s3c2410_serial",
bdd4915a 970 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
b497549a 971 .cons = S3C24XX_SERIAL_CONSOLE,
2cf0c58e 972 .dev_name = S3C24XX_SERIAL_NAME,
b497549a
BD		 973 .major = S3C24XX_SERIAL_MAJOR,
974 .minor = S3C24XX_SERIAL_MINOR,
975};
976
03d5e77b 977static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
b497549a
BD		 978 [0] = {
979 .port = {
980 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
981 .iotype = UPIO_MEM,
b497549a
BD		 982 .uartclk = 0,
983 .fifosize = 16,
984 .ops = &s3c24xx_serial_ops,
985 .flags = UPF_BOOT_AUTOCONF,
986 .line = 0,
987 }
988 },
989 [1] = {
990 .port = {
991 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
992 .iotype = UPIO_MEM,
b497549a
BD		 993 .uartclk = 0,
994 .fifosize = 16,
995 .ops = &s3c24xx_serial_ops,
996 .flags = UPF_BOOT_AUTOCONF,
997 .line = 1,
998 }
999 },
03d5e77b 1000#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
b497549a
BD		 1001
1002 [2] = {
1003 .port = {
1004 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
1005 .iotype = UPIO_MEM,
b497549a
BD		 1006 .uartclk = 0,
1007 .fifosize = 16,
1008 .ops = &s3c24xx_serial_ops,
1009 .flags = UPF_BOOT_AUTOCONF,
1010 .line = 2,
1011 }
03d5e77b
BD		 1012 },
1013#endif
1014#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1015 [3] = {
1016 .port = {
1017 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
1018 .iotype = UPIO_MEM,
03d5e77b
BD		 1019 .uartclk = 0,
1020 .fifosize = 16,
1021 .ops = &s3c24xx_serial_ops,
1022 .flags = UPF_BOOT_AUTOCONF,
1023 .line = 3,
1024 }
b497549a
BD		 1025 }
1026#endif
1027};
1028
1029/* s3c24xx_serial_resetport
1030 *
0dfb3b41 1031 * reset the fifos and other the settings.
b497549a
BD		 1032*/
1033
0dfb3b41
TA		 1034static void s3c24xx_serial_resetport(struct uart_port *port,
1035 struct s3c2410_uartcfg *cfg)
b497549a
BD		 1036{
1037 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
0dfb3b41
TA		 1038 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1039 unsigned int ucon_mask;
b497549a 1040
0dfb3b41
TA		 1041 ucon_mask = info->clksel_mask;
1042 if (info->type == PORT_S3C2440)
1043 ucon_mask |= S3C2440_UCON0_DIVMASK;
1044
1045 ucon &= ucon_mask;
1046 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1047
1048 /* reset both fifos */
1049 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1050 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1051
1052 /* some delay is required after fifo reset */
1053 udelay(1);
b497549a
BD		 1054}
1055
30555476
BD		 1056
1057#ifdef CONFIG_CPU_FREQ
1058
1059static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1060 unsigned long val, void *data)
1061{
1062 struct s3c24xx_uart_port *port;
1063 struct uart_port *uport;
1064
1065 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1066 uport = &port->port;
1067
1068 /* check to see if port is enabled */
1069
1070 if (port->pm_level != 0)
1071 return 0;
1072
1073 /* try and work out if the baudrate is changing, we can detect
1074 * a change in rate, but we do not have support for detecting
1075 * a disturbance in the clock-rate over the change.
1076 */
1077
25f04ad4 1078 if (IS_ERR(port->baudclk))
30555476
BD		 1079 goto exit;
1080
25f04ad4 1081 if (port->baudclk_rate == clk_get_rate(port->baudclk))
30555476
BD		 1082 goto exit;
1083
1084 if (val == CPUFREQ_PRECHANGE) {
1085 /* we should really shut the port down whilst the
1086 * frequency change is in progress. */
1087
1088 } else if (val == CPUFREQ_POSTCHANGE) {
1089 struct ktermios *termios;
1090 struct tty_struct *tty;
1091
ebd2c8f6 1092 if (uport->state == NULL)
30555476 1093 goto exit;
30555476 1094
ebd2c8f6 1095 tty = uport->state->port.tty;
30555476 1096
7de40c21 1097 if (tty == NULL)
30555476 1098 goto exit;
30555476 1099
adc8d746 1100 termios = &tty->termios;
30555476
BD		 1101
1102 if (termios == NULL) {
d20925e1 1103 dev_warn(uport->dev, "%s: no termios?\n", __func__);
30555476
BD		 1104 goto exit;
1105 }
1106
1107 s3c24xx_serial_set_termios(uport, termios, NULL);
1108 }
1109
1110 exit:
1111 return 0;
1112}
1113
1114static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1115{
1116 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1117
1118 return cpufreq_register_notifier(&port->freq_transition,
1119 CPUFREQ_TRANSITION_NOTIFIER);
1120}
1121
1122static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1123{
1124 cpufreq_unregister_notifier(&port->freq_transition,
1125 CPUFREQ_TRANSITION_NOTIFIER);
1126}
1127
1128#else
1129static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1130{
1131 return 0;
1132}
1133
1134static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1135{
1136}
1137#endif
1138
b497549a
BD		 1139/* s3c24xx_serial_init_port
1140 *
1141 * initialise a single serial port from the platform device given
1142 */
1143
1144static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
b497549a
BD		 1145 struct platform_device *platdev)
1146{
1147 struct uart_port *port = &ourport->port;
da121506 1148 struct s3c2410_uartcfg *cfg = ourport->cfg;
b497549a
BD		 1149 struct resource *res;
1150 int ret;
1151
1152 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1153
1154 if (platdev == NULL)
1155 return -ENODEV;
1156
b497549a
BD		 1157 if (port->mapbase != 0)
1158 return 0;
1159
b497549a
BD		 1160 /* setup info for port */
1161 port->dev = &platdev->dev;
b497549a 1162
88bb4ea1
TA		 1163 /* Startup sequence is different for s3c64xx and higher SoC's */
1164 if (s3c24xx_serial_has_interrupt_mask(port))
1165 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1166
b497549a
BD		 1167 port->uartclk = 1;
1168
1169 if (cfg->uart_flags & UPF_CONS_FLOW) {
1170 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1171 port->flags |= UPF_CONS_FLOW;
1172 }
1173
1174 /* sort our the physical and virtual addresses for each UART */
1175
1176 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1177 if (res == NULL) {
d20925e1 1178 dev_err(port->dev, "failed to find memory resource for uart\n");
b497549a
BD		 1179 return -EINVAL;
1180 }
1181
e4ac92df 1182 dbg("resource %pR)\n", res);
b497549a 1183
41147bfd
TA		 1184 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1185 if (!port->membase) {
1186 dev_err(port->dev, "failed to remap controller address\n");
1187 return -EBUSY;
1188 }
1189
b690ace5 1190 port->mapbase = res->start;
b497549a
BD		 1191 ret = platform_get_irq(platdev, 0);
1192 if (ret < 0)
1193 port->irq = 0;
b73c289c 1194 else {
b497549a 1195 port->irq = ret;
b73c289c
BD		 1196 ourport->rx_irq = ret;
1197 ourport->tx_irq = ret + 1;
1198 }
9303ac15 1199
b73c289c
BD		 1200 ret = platform_get_irq(platdev, 1);
1201 if (ret > 0)
1202 ourport->tx_irq = ret;
b497549a
BD		 1203
1204 ourport->clk = clk_get(&platdev->dev, "uart");
60e93575
CK		 1205 if (IS_ERR(ourport->clk)) {
1206 pr_err("%s: Controller clock not found\n",
1207 dev_name(&platdev->dev));
1208 return PTR_ERR(ourport->clk);
1209 }
1210
1211 ret = clk_prepare_enable(ourport->clk);
1212 if (ret) {
1213 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1214 clk_put(ourport->clk);
1215 return ret;
1216 }
b497549a 1217
88bb4ea1
TA		 1218 /* Keep all interrupts masked and cleared */
1219 if (s3c24xx_serial_has_interrupt_mask(port)) {
1220 wr_regl(port, S3C64XX_UINTM, 0xf);
1221 wr_regl(port, S3C64XX_UINTP, 0xf);
1222 wr_regl(port, S3C64XX_UINTSP, 0xf);
1223 }
1224
e4ac92df 1225 dbg("port: map=%08x, mem=%p, irq=%d (%d,%d), clock=%u\n",
b73c289c
BD		 1226 port->mapbase, port->membase, port->irq,
1227 ourport->rx_irq, ourport->tx_irq, port->uartclk);
b497549a
BD		 1228
1229 /* reset the fifos (and setup the uart) */
1230 s3c24xx_serial_resetport(port, cfg);
1231 return 0;
1232}
1233
17efd2b7 1234#ifdef CONFIG_SAMSUNG_CLOCK
b497549a
BD		 1235static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1236 struct device_attribute *attr,
1237 char *buf)
1238{
1239 struct uart_port *port = s3c24xx_dev_to_port(dev);
1240 struct s3c24xx_uart_port *ourport = to_ourport(port);
1241
7cd88831
KK		 1242 if (IS_ERR(ourport->baudclk))
1243 return -EINVAL;
1244
7b15e1d9
KP		 1245 return snprintf(buf, PAGE_SIZE, "* %s\n",
1246 ourport->baudclk->name ?: "(null)");
b497549a
BD		 1247}
1248
1249static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
17efd2b7 1250#endif
26c919e1 1251
b497549a
BD		 1252/* Device driver serial port probe */
1253
26c919e1 1254static const struct of_device_id s3c24xx_uart_dt_match[];
b497549a
BD		 1255static int probe_index;
1256
26c919e1
TA		 1257static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1258 struct platform_device *pdev)
1259{
1260#ifdef CONFIG_OF
1261 if (pdev->dev.of_node) {
1262 const struct of_device_id *match;
1263 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1264 return (struct s3c24xx_serial_drv_data *)match->data;
1265 }
1266#endif
1267 return (struct s3c24xx_serial_drv_data *)
1268 platform_get_device_id(pdev)->driver_data;
1269}
1270
da121506 1271static int s3c24xx_serial_probe(struct platform_device *pdev)
b497549a
BD		 1272{
1273 struct s3c24xx_uart_port *ourport;
1274 int ret;
1275
da121506 1276 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, probe_index);
b497549a
BD		 1277
1278 ourport = &s3c24xx_serial_ports[probe_index];
da121506 1279
26c919e1
TA		 1280 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1281 if (!ourport->drv_data) {
1282 dev_err(&pdev->dev, "could not find driver data\n");
1283 return -ENODEV;
1284 }
da121506 1285
7cd88831 1286 ourport->baudclk = ERR_PTR(-EINVAL);
da121506 1287 ourport->info = ourport->drv_data->info;
574de559 1288 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
d4aab206 1289 dev_get_platdata(&pdev->dev) :
da121506
TA		 1290 ourport->drv_data->def_cfg;
1291
1292 ourport->port.fifosize = (ourport->info->fifosize) ?
1293 ourport->info->fifosize :
1294 ourport->drv_data->fifosize[probe_index];
1295
b497549a
BD		 1296 probe_index++;
1297
1298 dbg("%s: initialising port %p...\n", __func__, ourport);
1299
da121506 1300 ret = s3c24xx_serial_init_port(ourport, pdev);
b497549a
BD		 1301 if (ret < 0)
1302 goto probe_err;
1303
6f134c3c
TB		 1304 if (!s3c24xx_uart_drv.state) {
1305 ret = uart_register_driver(&s3c24xx_uart_drv);
1306 if (ret < 0) {
1307 pr_err("Failed to register Samsung UART driver\n");
1308 return ret;
1309 }
1310 }
1311
b497549a
BD		 1312 dbg("%s: adding port\n", __func__);
1313 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
da121506 1314 platform_set_drvdata(pdev, &ourport->port);
b497549a 1315
0da3336f
HS		 1316 /*
1317 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1318 * so that a potential re-enablement through the pm-callback overlaps
1319 * and keeps the clock enabled in this case.
1320 */
1321 clk_disable_unprepare(ourport->clk);
1322
17efd2b7 1323#ifdef CONFIG_SAMSUNG_CLOCK
da121506 1324 ret = device_create_file(&pdev->dev, &dev_attr_clock_source);
b497549a 1325 if (ret < 0)
da121506 1326 dev_err(&pdev->dev, "failed to add clock source attr.\n");
17efd2b7 1327#endif
b497549a 1328
30555476
BD		 1329 ret = s3c24xx_serial_cpufreq_register(ourport);
1330 if (ret < 0)
da121506 1331 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
30555476 1332
b497549a
BD		 1333 return 0;
1334
1335 probe_err:
1336 return ret;
1337}
1338
ae8d8a14 1339static int s3c24xx_serial_remove(struct platform_device *dev)
b497549a
BD		 1340{
1341 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1342
1343 if (port) {
30555476 1344 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
17efd2b7 1345#ifdef CONFIG_SAMSUNG_CLOCK
b497549a 1346 device_remove_file(&dev->dev, &dev_attr_clock_source);
17efd2b7 1347#endif
b497549a
BD		 1348 uart_remove_one_port(&s3c24xx_uart_drv, port);
1349 }
1350
6f134c3c
TB		 1351 uart_unregister_driver(&s3c24xx_uart_drv);
1352
b497549a
BD		 1353 return 0;
1354}
1355
b497549a 1356/* UART power management code */
aef7fe52
MH		 1357#ifdef CONFIG_PM_SLEEP
1358static int s3c24xx_serial_suspend(struct device *dev)
b497549a 1359{
aef7fe52 1360 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1361
1362 if (port)
1363 uart_suspend_port(&s3c24xx_uart_drv, port);
1364
1365 return 0;
1366}
1367
aef7fe52 1368static int s3c24xx_serial_resume(struct device *dev)
b497549a 1369{
aef7fe52 1370 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1371 struct s3c24xx_uart_port *ourport = to_ourport(port);
1372
1373 if (port) {
9484b009 1374 clk_prepare_enable(ourport->clk);
b497549a 1375 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
9484b009 1376 clk_disable_unprepare(ourport->clk);
b497549a
BD		 1377
1378 uart_resume_port(&s3c24xx_uart_drv, port);
1379 }
1380
1381 return 0;
1382}
aef7fe52 1383
d09a7308
MS		 1384static int s3c24xx_serial_resume_noirq(struct device *dev)
1385{
1386 struct uart_port *port = s3c24xx_dev_to_port(dev);
1387
1388 if (port) {
1389 /* restore IRQ mask */
1390 if (s3c24xx_serial_has_interrupt_mask(port)) {
1391 unsigned int uintm = 0xf;
1392 if (tx_enabled(port))
1393 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1394 if (rx_enabled(port))
1395 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1396 wr_regl(port, S3C64XX_UINTM, uintm);
1397 }
1398 }
1399
1400 return 0;
1401}
1402
aef7fe52
MH		 1403static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1404 .suspend = s3c24xx_serial_suspend,
1405 .resume = s3c24xx_serial_resume,
d09a7308 1406 .resume_noirq = s3c24xx_serial_resume_noirq,
aef7fe52 1407};
b882fc1b
KK		 1408#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1409
aef7fe52 1410#else /* !CONFIG_PM_SLEEP */
b882fc1b
KK		 1411
1412#define SERIAL_SAMSUNG_PM_OPS NULL
aef7fe52 1413#endif /* CONFIG_PM_SLEEP */
b497549a 1414
b497549a
BD		 1415/* Console code */
1416
1417#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1418
1419static struct uart_port *cons_uart;
1420
1421static int
1422s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1423{
1424 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1425 unsigned long ufstat, utrstat;
1426
1427 if (ufcon & S3C2410_UFCON_FIFOMODE) {
9ddc5b6f 1428 /* fifo mode - check amount of data in fifo registers... */
b497549a
BD		 1429
1430 ufstat = rd_regl(port, S3C2410_UFSTAT);
1431 return (ufstat & info->tx_fifofull) ? 0 : 1;
1432 }
1433
1434 /* in non-fifo mode, we go and use the tx buffer empty */
1435
1436 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1437 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1438}
1439
38adbc54
MS		 1440static bool
1441s3c24xx_port_configured(unsigned int ucon)
1442{
1443 /* consider the serial port configured if the tx/rx mode set */
1444 return (ucon & 0xf) != 0;
1445}
1446
93b5c032
JP		 1447#ifdef CONFIG_CONSOLE_POLL
1448/*
1449 * Console polling routines for writing and reading from the uart while
1450 * in an interrupt or debug context.
1451 */
1452
1453static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1454{
1455 struct s3c24xx_uart_port *ourport = to_ourport(port);
1456 unsigned int ufstat;
1457
1458 ufstat = rd_regl(port, S3C2410_UFSTAT);
1459 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1460 return NO_POLL_CHAR;
1461
1462 return rd_regb(port, S3C2410_URXH);
1463}
1464
1465static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1466 unsigned char c)
1467{
bb7f09ba
DA		 1468 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
1469 unsigned int ucon = rd_regl(port, S3C2410_UCON);
38adbc54
MS		 1470
1471 /* not possible to xmit on unconfigured port */
1472 if (!s3c24xx_port_configured(ucon))
1473 return;
93b5c032
JP		 1474
1475 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1476 cpu_relax();
bb7f09ba 1477 wr_regb(port, S3C2410_UTXH, c);
93b5c032
JP		 1478}
1479
1480#endif /* CONFIG_CONSOLE_POLL */
1481
b497549a
BD		 1482static void
1483s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1484{
bb7f09ba 1485 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
38adbc54 1486
b497549a 1487 while (!s3c24xx_serial_console_txrdy(port, ufcon))
f94b0572 1488 cpu_relax();
bb7f09ba 1489 wr_regb(port, S3C2410_UTXH, ch);
b497549a
BD		 1490}
1491
1492static void
1493s3c24xx_serial_console_write(struct console *co, const char *s,
1494 unsigned int count)
1495{
ab88c8dc
DA		 1496 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1497
1498 /* not possible to xmit on unconfigured port */
1499 if (!s3c24xx_port_configured(ucon))
1500 return;
1501
b497549a
BD		 1502 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1503}
1504
1505static void __init
1506s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1507 int *parity, int *bits)
1508{
b497549a
BD		 1509 struct clk *clk;
1510 unsigned int ulcon;
1511 unsigned int ucon;
1512 unsigned int ubrdiv;
1513 unsigned long rate;
5f5a7a55
TA		 1514 unsigned int clk_sel;
1515 char clk_name[MAX_CLK_NAME_LENGTH];
b497549a
BD		 1516
1517 ulcon = rd_regl(port, S3C2410_ULCON);
1518 ucon = rd_regl(port, S3C2410_UCON);
1519 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1520
1521 dbg("s3c24xx_serial_get_options: port=%p\n"
1522 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1523 port, ulcon, ucon, ubrdiv);
1524
38adbc54 1525 if (s3c24xx_port_configured(ucon)) {
b497549a
BD		 1526 switch (ulcon & S3C2410_LCON_CSMASK) {
1527 case S3C2410_LCON_CS5:
1528 *bits = 5;
1529 break;
1530 case S3C2410_LCON_CS6:
1531 *bits = 6;
1532 break;
1533 case S3C2410_LCON_CS7:
1534 *bits = 7;
1535 break;
1536 default:
1537 case S3C2410_LCON_CS8:
1538 *bits = 8;
1539 break;
1540 }
1541
1542 switch (ulcon & S3C2410_LCON_PMASK) {
1543 case S3C2410_LCON_PEVEN:
1544 *parity = 'e';
1545 break;
1546
1547 case S3C2410_LCON_PODD:
1548 *parity = 'o';
1549 break;
1550
1551 case S3C2410_LCON_PNONE:
1552 default:
1553 *parity = 'n';
1554 }
1555
1556 /* now calculate the baud rate */
1557
5f5a7a55
TA		 1558 clk_sel = s3c24xx_serial_getsource(port);
1559 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
b497549a 1560
5f5a7a55 1561 clk = clk_get(port->dev, clk_name);
7cd88831 1562 if (!IS_ERR(clk))
5f5a7a55 1563 rate = clk_get_rate(clk);
b497549a
BD		 1564 else
1565 rate = 1;
1566
b497549a
BD		 1567 *baud = rate / (16 * (ubrdiv + 1));
1568 dbg("calculated baud %d\n", *baud);
1569 }
1570
1571}
1572
b497549a
BD		 1573static int __init
1574s3c24xx_serial_console_setup(struct console *co, char *options)
1575{
1576 struct uart_port *port;
1577 int baud = 9600;
1578 int bits = 8;
1579 int parity = 'n';
1580 int flow = 'n';
1581
1582 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1583 co, co->index, options);
1584
1585 /* is this a valid port */
1586
03d5e77b 1587 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
b497549a
BD		 1588 co->index = 0;
1589
1590 port = &s3c24xx_serial_ports[co->index].port;
1591
1592 /* is the port configured? */
1593
ee430f16
TA		 1594 if (port->mapbase == 0x0)
1595 return -ENODEV;
b497549a
BD		 1596
1597 cons_uart = port;
1598
1599 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1600
1601 /*
1602 * Check whether an invalid uart number has been specified, and
1603 * if so, search for the first available port that does have
1604 * console support.
1605 */
1606 if (options)
1607 uart_parse_options(options, &baud, &parity, &bits, &flow);
1608 else
1609 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1610
1611 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1612
1613 return uart_set_options(port, co, baud, parity, bits, flow);
1614}
1615
b497549a
BD		 1616static struct console s3c24xx_serial_console = {
1617 .name = S3C24XX_SERIAL_NAME,
1618 .device = uart_console_device,
1619 .flags = CON_PRINTBUFFER,
1620 .index = -1,
1621 .write = s3c24xx_serial_console_write,
5822a5df
TA		 1622 .setup = s3c24xx_serial_console_setup,
1623 .data = &s3c24xx_uart_drv,
b497549a 1624};
da121506
TA		 1625#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1626
1627#ifdef CONFIG_CPU_S3C2410
1628static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1629 .info = &(struct s3c24xx_uart_info) {
1630 .name = "Samsung S3C2410 UART",
1631 .type = PORT_S3C2410,
1632 .fifosize = 16,
1633 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1634 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1635 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1636 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1637 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1638 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1639 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1640 .num_clks = 2,
1641 .clksel_mask = S3C2410_UCON_CLKMASK,
1642 .clksel_shift = S3C2410_UCON_CLKSHIFT,
1643 },
1644 .def_cfg = &(struct s3c2410_uartcfg) {
1645 .ucon = S3C2410_UCON_DEFAULT,
1646 .ufcon = S3C2410_UFCON_DEFAULT,
1647 },
1648};
1649#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1650#else
1651#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1652#endif
b497549a 1653
da121506
TA		 1654#ifdef CONFIG_CPU_S3C2412
1655static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1656 .info = &(struct s3c24xx_uart_info) {
1657 .name = "Samsung S3C2412 UART",
1658 .type = PORT_S3C2412,
1659 .fifosize = 64,
1660 .has_divslot = 1,
1661 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1662 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1663 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1664 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1665 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1666 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1667 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1668 .num_clks = 4,
1669 .clksel_mask = S3C2412_UCON_CLKMASK,
1670 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1671 },
1672 .def_cfg = &(struct s3c2410_uartcfg) {
1673 .ucon = S3C2410_UCON_DEFAULT,
1674 .ufcon = S3C2410_UFCON_DEFAULT,
1675 },
1676};
1677#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1678#else
1679#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1680#endif
b497549a 1681
da121506 1682#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
b26469a8 1683 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
da121506
TA		 1684static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1685 .info = &(struct s3c24xx_uart_info) {
1686 .name = "Samsung S3C2440 UART",
1687 .type = PORT_S3C2440,
1688 .fifosize = 64,
1689 .has_divslot = 1,
1690 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1691 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1692 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1693 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1694 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1695 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1696 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1697 .num_clks = 4,
1698 .clksel_mask = S3C2412_UCON_CLKMASK,
1699 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1700 },
1701 .def_cfg = &(struct s3c2410_uartcfg) {
1702 .ucon = S3C2410_UCON_DEFAULT,
1703 .ufcon = S3C2410_UFCON_DEFAULT,
1704 },
1705};
1706#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1707#else
1708#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1709#endif
b497549a 1710
da121506
TA		 1711#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
1712 defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \
1713 defined(CONFIG_CPU_S5PC100)
1714static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1715 .info = &(struct s3c24xx_uart_info) {
1716 .name = "Samsung S3C6400 UART",
1717 .type = PORT_S3C6400,
1718 .fifosize = 64,
1719 .has_divslot = 1,
1720 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1721 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1722 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1723 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1724 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1725 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1726 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1727 .num_clks = 4,
1728 .clksel_mask = S3C6400_UCON_CLKMASK,
1729 .clksel_shift = S3C6400_UCON_CLKSHIFT,
1730 },
1731 .def_cfg = &(struct s3c2410_uartcfg) {
1732 .ucon = S3C2410_UCON_DEFAULT,
1733 .ufcon = S3C2410_UFCON_DEFAULT,
1734 },
1735};
1736#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1737#else
1738#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1739#endif
b497549a 1740
da121506
TA		 1741#ifdef CONFIG_CPU_S5PV210
1742static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1743 .info = &(struct s3c24xx_uart_info) {
1744 .name = "Samsung S5PV210 UART",
1745 .type = PORT_S3C6400,
1746 .has_divslot = 1,
1747 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1748 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1749 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1750 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1751 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1752 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1753 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1754 .num_clks = 2,
1755 .clksel_mask = S5PV210_UCON_CLKMASK,
1756 .clksel_shift = S5PV210_UCON_CLKSHIFT,
1757 },
1758 .def_cfg = &(struct s3c2410_uartcfg) {
1759 .ucon = S5PV210_UCON_DEFAULT,
1760 .ufcon = S5PV210_UFCON_DEFAULT,
1761 },
1762 .fifosize = { 256, 64, 16, 16 },
1763};
1764#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1765#else
1766#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1767#endif
b497549a 1768
33f88136 1769#if defined(CONFIG_ARCH_EXYNOS)
da121506
TA		 1770static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1771 .info = &(struct s3c24xx_uart_info) {
1772 .name = "Samsung Exynos4 UART",
1773 .type = PORT_S3C6400,
1774 .has_divslot = 1,
1775 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1776 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1777 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1778 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1779 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1780 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1781 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1782 .num_clks = 1,
1783 .clksel_mask = 0,
1784 .clksel_shift = 0,
1785 },
1786 .def_cfg = &(struct s3c2410_uartcfg) {
1787 .ucon = S5PV210_UCON_DEFAULT,
1788 .ufcon = S5PV210_UFCON_DEFAULT,
1789 .has_fracval = 1,
1790 },
1791 .fifosize = { 256, 64, 16, 16 },
1792};
1793#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1794#else
1795#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1796#endif
b497549a 1797
da121506
TA		 1798static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1799 {
1800 .name = "s3c2410-uart",
1801 .driver_data = S3C2410_SERIAL_DRV_DATA,
1802 }, {
1803 .name = "s3c2412-uart",
1804 .driver_data = S3C2412_SERIAL_DRV_DATA,
1805 }, {
1806 .name = "s3c2440-uart",
1807 .driver_data = S3C2440_SERIAL_DRV_DATA,
1808 }, {
1809 .name = "s3c6400-uart",
1810 .driver_data = S3C6400_SERIAL_DRV_DATA,
1811 }, {
1812 .name = "s5pv210-uart",
1813 .driver_data = S5PV210_SERIAL_DRV_DATA,
1814 }, {
1815 .name = "exynos4210-uart",
1816 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1817 },
1818 { },
1819};
1820MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1821
26c919e1
TA		 1822#ifdef CONFIG_OF
1823static const struct of_device_id s3c24xx_uart_dt_match[] = {
666ca0b9
HS		 1824 { .compatible = "samsung,s3c2410-uart",
1825 .data = (void *)S3C2410_SERIAL_DRV_DATA },
1826 { .compatible = "samsung,s3c2412-uart",
1827 .data = (void *)S3C2412_SERIAL_DRV_DATA },
1828 { .compatible = "samsung,s3c2440-uart",
1829 .data = (void *)S3C2440_SERIAL_DRV_DATA },
1830 { .compatible = "samsung,s3c6400-uart",
1831 .data = (void *)S3C6400_SERIAL_DRV_DATA },
1832 { .compatible = "samsung,s5pv210-uart",
1833 .data = (void *)S5PV210_SERIAL_DRV_DATA },
26c919e1 1834 { .compatible = "samsung,exynos4210-uart",
a169a888 1835 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
26c919e1
TA		 1836 {},
1837};
1838MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
26c919e1
TA		 1839#endif
1840
da121506
TA		 1841static struct platform_driver samsung_serial_driver = {
1842 .probe = s3c24xx_serial_probe,
2d47b716 1843 .remove = s3c24xx_serial_remove,
da121506
TA		 1844 .id_table = s3c24xx_serial_driver_ids,
1845 .driver = {
1846 .name = "samsung-uart",
1847 .owner = THIS_MODULE,
1848 .pm = SERIAL_SAMSUNG_PM_OPS,
905f4ba2 1849 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
da121506
TA		 1850 },
1851};
b497549a 1852
6f134c3c 1853module_platform_driver(samsung_serial_driver);
b497549a 1854
da121506 1855MODULE_ALIAS("platform:samsung-uart");
b497549a
BD		 1856MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1857MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1858MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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