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serial: samsung: Add support for early console
[deliverable/linux.git] / drivers / tty / serial / samsung.c
CommitLineData
99edb3d1 1/*
b497549a
BD		 2 * Driver core for Samsung SoC onboard UARTs.
3 *
ccae941e 4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
b497549a
BD		 5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25*/
26
27#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28#define SUPPORT_SYSRQ
29#endif
30
62c37eed
RB		 31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/slab.h>
b497549a
BD		 34#include <linux/module.h>
35#include <linux/ioport.h>
36#include <linux/io.h>
37#include <linux/platform_device.h>
38#include <linux/init.h>
39#include <linux/sysrq.h>
40#include <linux/console.h>
41#include <linux/tty.h>
42#include <linux/tty_flip.h>
43#include <linux/serial_core.h>
44#include <linux/serial.h>
9ee51f01 45#include <linux/serial_s3c.h>
b497549a
BD		 46#include <linux/delay.h>
47#include <linux/clk.h>
30555476 48#include <linux/cpufreq.h>
26c919e1 49#include <linux/of.h>
b497549a
BD		 50
51#include <asm/irq.h>
52
b497549a
BD		 53#include "samsung.h"
54
e4ac92df
JP		 55#if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
56 defined(CONFIG_DEBUG_LL) && \
57 !defined(MODULE)
58
59extern void printascii(const char *);
60
61__printf(1, 2)
62static void dbg(const char *fmt, ...)
63{
64 va_list va;
65 char buff[256];
66
67 va_start(va, fmt);
a859c8b2 68 vscnprintf(buff, sizeof(buff), fmt, va);
e4ac92df
JP		 69 va_end(va);
70
71 printascii(buff);
72}
73
74#else
75#define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
76#endif
77
b497549a
BD		 78/* UART name and device definitions */
79
80#define S3C24XX_SERIAL_NAME "ttySAC"
81#define S3C24XX_SERIAL_MAJOR 204
82#define S3C24XX_SERIAL_MINOR 64
83
29bef799
RB		 84#define S3C24XX_TX_PIO 1
85#define S3C24XX_TX_DMA 2
b543c301
RB		 86#define S3C24XX_RX_PIO 1
87#define S3C24XX_RX_DMA 2
b497549a
BD		 88/* macros to change one thing to another */
89
90#define tx_enabled(port) ((port)->unused[0])
91#define rx_enabled(port) ((port)->unused[1])
92
25985edc 93/* flag to ignore all characters coming in */
b497549a
BD		 94#define RXSTAT_DUMMY_READ (0x10000000)
95
96static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
97{
98 return container_of(port, struct s3c24xx_uart_port, port);
99}
100
101/* translate a port to the device name */
102
103static inline const char *s3c24xx_serial_portname(struct uart_port *port)
104{
105 return to_platform_device(port->dev)->name;
106}
107
108static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
109{
9303ac15 110 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
b497549a
BD		 111}
112
88bb4ea1
TA		 113/*
114 * s3c64xx and later SoC's include the interrupt mask and status registers in
115 * the controller itself, unlike the s3c24xx SoC's which have these registers
116 * in the interrupt controller. Check if the port type is s3c64xx or higher.
117 */
118static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
119{
120 return to_ourport(port)->info->type == PORT_S3C6400;
121}
122
b497549a
BD		 123static void s3c24xx_serial_rx_enable(struct uart_port *port)
124{
125 unsigned long flags;
126 unsigned int ucon, ufcon;
127 int count = 10000;
128
129 spin_lock_irqsave(&port->lock, flags);
130
131 while (--count && !s3c24xx_serial_txempty_nofifo(port))
132 udelay(100);
133
134 ufcon = rd_regl(port, S3C2410_UFCON);
135 ufcon |= S3C2410_UFCON_RESETRX;
136 wr_regl(port, S3C2410_UFCON, ufcon);
137
138 ucon = rd_regl(port, S3C2410_UCON);
139 ucon |= S3C2410_UCON_RXIRQMODE;
140 wr_regl(port, S3C2410_UCON, ucon);
141
142 rx_enabled(port) = 1;
143 spin_unlock_irqrestore(&port->lock, flags);
144}
145
146static void s3c24xx_serial_rx_disable(struct uart_port *port)
147{
148 unsigned long flags;
149 unsigned int ucon;
150
151 spin_lock_irqsave(&port->lock, flags);
152
153 ucon = rd_regl(port, S3C2410_UCON);
154 ucon &= ~S3C2410_UCON_RXIRQMODE;
155 wr_regl(port, S3C2410_UCON, ucon);
156
157 rx_enabled(port) = 0;
158 spin_unlock_irqrestore(&port->lock, flags);
159}
160
161static void s3c24xx_serial_stop_tx(struct uart_port *port)
162{
b73c289c 163 struct s3c24xx_uart_port *ourport = to_ourport(port);
29bef799
RB		 164 struct s3c24xx_uart_dma *dma = ourport->dma;
165 struct circ_buf *xmit = &port->state->xmit;
166 struct dma_tx_state state;
167 int count;
b73c289c 168
29bef799
RB		 169 if (!tx_enabled(port))
170 return;
171
172 if (s3c24xx_serial_has_interrupt_mask(port))
173 __set_bit(S3C64XX_UINTM_TXD,
174 portaddrl(port, S3C64XX_UINTM));
175 else
176 disable_irq_nosync(ourport->tx_irq);
177
178 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
179 dmaengine_pause(dma->tx_chan);
180 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
181 dmaengine_terminate_all(dma->tx_chan);
182 dma_sync_single_for_cpu(ourport->port.dev,
183 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
184 async_tx_ack(dma->tx_desc);
185 count = dma->tx_bytes_requested - state.residue;
186 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
187 port->icount.tx += count;
b497549a 188 }
29bef799
RB		 189
190 tx_enabled(port) = 0;
191 ourport->tx_in_progress = 0;
192
193 if (port->flags & UPF_CONS_FLOW)
194 s3c24xx_serial_rx_enable(port);
195
196 ourport->tx_mode = 0;
197}
198
199static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
200
201static void s3c24xx_serial_tx_dma_complete(void *args)
202{
203 struct s3c24xx_uart_port *ourport = args;
204 struct uart_port *port = &ourport->port;
205 struct circ_buf *xmit = &port->state->xmit;
206 struct s3c24xx_uart_dma *dma = ourport->dma;
207 struct dma_tx_state state;
208 unsigned long flags;
209 int count;
210
211
212 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
213 count = dma->tx_bytes_requested - state.residue;
214 async_tx_ack(dma->tx_desc);
215
216 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
217 dma->tx_size, DMA_TO_DEVICE);
218
219 spin_lock_irqsave(&port->lock, flags);
220
221 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
222 port->icount.tx += count;
223 ourport->tx_in_progress = 0;
224
225 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
226 uart_write_wakeup(port);
227
228 s3c24xx_serial_start_next_tx(ourport);
229 spin_unlock_irqrestore(&port->lock, flags);
230}
231
232static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
233{
234 struct uart_port *port = &ourport->port;
235 u32 ucon;
236
237 /* Mask Tx interrupt */
238 if (s3c24xx_serial_has_interrupt_mask(port))
239 __set_bit(S3C64XX_UINTM_TXD,
240 portaddrl(port, S3C64XX_UINTM));
241 else
242 disable_irq_nosync(ourport->tx_irq);
243
244 /* Enable tx dma mode */
245 ucon = rd_regl(port, S3C2410_UCON);
246 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
247 ucon |= (dma_get_cache_alignment() >= 16) ?
248 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
249 ucon |= S3C64XX_UCON_TXMODE_DMA;
250 wr_regl(port, S3C2410_UCON, ucon);
251
252 ourport->tx_mode = S3C24XX_TX_DMA;
253}
254
255static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
256{
257 struct uart_port *port = &ourport->port;
258 u32 ucon, ufcon;
259
260 /* Set ufcon txtrig */
261 ourport->tx_in_progress = S3C24XX_TX_PIO;
262 ufcon = rd_regl(port, S3C2410_UFCON);
263 wr_regl(port, S3C2410_UFCON, ufcon);
264
265 /* Enable tx pio mode */
266 ucon = rd_regl(port, S3C2410_UCON);
267 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
268 ucon |= S3C64XX_UCON_TXMODE_CPU;
269 wr_regl(port, S3C2410_UCON, ucon);
270
271 /* Unmask Tx interrupt */
272 if (s3c24xx_serial_has_interrupt_mask(port))
273 __clear_bit(S3C64XX_UINTM_TXD,
274 portaddrl(port, S3C64XX_UINTM));
275 else
276 enable_irq(ourport->tx_irq);
277
278 ourport->tx_mode = S3C24XX_TX_PIO;
279}
280
281static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
282{
283 if (ourport->tx_mode != S3C24XX_TX_PIO)
284 enable_tx_pio(ourport);
b497549a
BD		 285}
286
29bef799
RB		 287static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
288 unsigned int count)
289{
290 struct uart_port *port = &ourport->port;
291 struct circ_buf *xmit = &port->state->xmit;
292 struct s3c24xx_uart_dma *dma = ourport->dma;
293
294
295 if (ourport->tx_mode != S3C24XX_TX_DMA)
296 enable_tx_dma(ourport);
297
298 while (xmit->tail & (dma_get_cache_alignment() - 1)) {
299 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
300 return 0;
301 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
302 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
303 port->icount.tx++;
304 count--;
305 }
306
307 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
308 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
309
310 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
311 dma->tx_size, DMA_TO_DEVICE);
312
313 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
314 dma->tx_transfer_addr, dma->tx_size,
315 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
316 if (!dma->tx_desc) {
317 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
318 return -EIO;
319 }
320
321 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
322 dma->tx_desc->callback_param = ourport;
323 dma->tx_bytes_requested = dma->tx_size;
324
325 ourport->tx_in_progress = S3C24XX_TX_DMA;
326 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
327 dma_async_issue_pending(dma->tx_chan);
328 return 0;
329}
330
331static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
332{
333 struct uart_port *port = &ourport->port;
334 struct circ_buf *xmit = &port->state->xmit;
335 unsigned long count;
336
337 /* Get data size up to the end of buffer */
338 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
339
340 if (!count) {
341 s3c24xx_serial_stop_tx(port);
342 return;
343 }
344
345 if (!ourport->dma || !ourport->dma->tx_chan || count < port->fifosize)
346 s3c24xx_serial_start_tx_pio(ourport);
347 else
348 s3c24xx_serial_start_tx_dma(ourport, count);
349}
350
351void s3c24xx_serial_start_tx(struct uart_port *port)
b497549a 352{
b73c289c 353 struct s3c24xx_uart_port *ourport = to_ourport(port);
29bef799 354 struct circ_buf *xmit = &port->state->xmit;
b73c289c 355
b497549a
BD		 356 if (!tx_enabled(port)) {
357 if (port->flags & UPF_CONS_FLOW)
358 s3c24xx_serial_rx_disable(port);
359
b497549a 360 tx_enabled(port) = 1;
29bef799
RB		 361 if (!ourport->dma || !ourport->dma->tx_chan) {
362 if (s3c24xx_serial_has_interrupt_mask(port))
363 __clear_bit(S3C64XX_UINTM_TXD,
364 portaddrl(port, S3C64XX_UINTM));
365 else
366 enable_irq(ourport->tx_irq);
367
368 s3c24xx_serial_start_tx_pio(ourport);
369 }
370 }
371
372 if (ourport->dma && ourport->dma->tx_chan) {
373 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
374 s3c24xx_serial_start_next_tx(ourport);
b497549a
BD		 375 }
376}
377
b543c301
RB		 378static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
379 struct tty_port *tty, int count)
380{
381 struct s3c24xx_uart_dma *dma = ourport->dma;
382 int copied;
383
384 if (!count)
385 return;
386
387 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
388 dma->rx_size, DMA_FROM_DEVICE);
389
390 ourport->port.icount.rx += count;
391 if (!tty) {
392 dev_err(ourport->port.dev, "No tty port\n");
393 return;
394 }
395 copied = tty_insert_flip_string(tty,
396 ((unsigned char *)(ourport->dma->rx_buf)), count);
397 if (copied != count) {
398 WARN_ON(1);
399 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
400 }
401}
402
403static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
404 unsigned long ufstat);
405
406static void uart_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
407{
408 struct uart_port *port = &ourport->port;
409 struct tty_port *tty = &port->state->port;
410 unsigned int ch, ufstat;
411 unsigned int count;
412
413 ufstat = rd_regl(port, S3C2410_UFSTAT);
414 count = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
415
416 if (!count)
417 return;
418
419 while (count-- > 0) {
420 ch = rd_regb(port, S3C2410_URXH);
421
422 ourport->port.icount.rx++;
423 tty_insert_flip_char(tty, ch, TTY_NORMAL);
424 }
425
426 tty_flip_buffer_push(tty);
427}
428
b497549a
BD		 429static void s3c24xx_serial_stop_rx(struct uart_port *port)
430{
b73c289c 431 struct s3c24xx_uart_port *ourport = to_ourport(port);
b543c301
RB		 432 struct s3c24xx_uart_dma *dma = ourport->dma;
433 struct tty_port *t = &port->state->port;
434 struct dma_tx_state state;
435 enum dma_status dma_status;
436 unsigned int received;
b73c289c 437
b497549a
BD		 438 if (rx_enabled(port)) {
439 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
88bb4ea1
TA		 440 if (s3c24xx_serial_has_interrupt_mask(port))
441 __set_bit(S3C64XX_UINTM_RXD,
442 portaddrl(port, S3C64XX_UINTM));
443 else
444 disable_irq_nosync(ourport->rx_irq);
b497549a
BD		 445 rx_enabled(port) = 0;
446 }
b543c301
RB		 447 if (dma && dma->rx_chan) {
448 dmaengine_pause(dma->tx_chan);
449 dma_status = dmaengine_tx_status(dma->rx_chan,
450 dma->rx_cookie, &state);
451 if (dma_status == DMA_IN_PROGRESS ||
452 dma_status == DMA_PAUSED) {
453 received = dma->rx_bytes_requested - state.residue;
454 dmaengine_terminate_all(dma->rx_chan);
455 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
456 }
457 }
b497549a
BD		 458}
459
ef4aca70
RB		 460static inline struct s3c24xx_uart_info
461 *s3c24xx_port_to_info(struct uart_port *port)
b497549a
BD		 462{
463 return to_ourport(port)->info;
464}
465
ef4aca70
RB		 466static inline struct s3c2410_uartcfg
467 *s3c24xx_port_to_cfg(struct uart_port *port)
b497549a 468{
4d84e970
TA		 469 struct s3c24xx_uart_port *ourport;
470
b497549a
BD		 471 if (port->dev == NULL)
472 return NULL;
473
4d84e970
TA		 474 ourport = container_of(port, struct s3c24xx_uart_port, port);
475 return ourport->cfg;
b497549a
BD		 476}
477
478static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
479 unsigned long ufstat)
480{
481 struct s3c24xx_uart_info *info = ourport->info;
482
483 if (ufstat & info->rx_fifofull)
da121506 484 return ourport->port.fifosize;
b497549a
BD		 485
486 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
487}
488
b543c301
RB		 489static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
490static void s3c24xx_serial_rx_dma_complete(void *args)
491{
492 struct s3c24xx_uart_port *ourport = args;
493 struct uart_port *port = &ourport->port;
494
495 struct s3c24xx_uart_dma *dma = ourport->dma;
496 struct tty_port *t = &port->state->port;
497 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
498
499 struct dma_tx_state state;
500 unsigned long flags;
501 int received;
502
503 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
504 received = dma->rx_bytes_requested - state.residue;
505 async_tx_ack(dma->rx_desc);
506
507 spin_lock_irqsave(&port->lock, flags);
508
509 if (received)
510 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
511
512 if (tty) {
513 tty_flip_buffer_push(t);
514 tty_kref_put(tty);
515 }
516
517 s3c64xx_start_rx_dma(ourport);
518
519 spin_unlock_irqrestore(&port->lock, flags);
520}
521
522static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
523{
524 struct s3c24xx_uart_dma *dma = ourport->dma;
525
526 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
527 dma->rx_size, DMA_FROM_DEVICE);
528
529 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
530 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
531 DMA_PREP_INTERRUPT);
532 if (!dma->rx_desc) {
533 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
534 return;
535 }
536
537 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
538 dma->rx_desc->callback_param = ourport;
539 dma->rx_bytes_requested = dma->rx_size;
540
541 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
542 dma_async_issue_pending(dma->rx_chan);
543}
b497549a
BD		 544
545/* ? - where has parity gone?? */
546#define S3C2410_UERSTAT_PARITY (0x1000)
547
b543c301
RB		 548static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
549{
550 struct uart_port *port = &ourport->port;
551 unsigned int ucon;
552
553 /* set Rx mode to DMA mode */
554 ucon = rd_regl(port, S3C2410_UCON);
555 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
556 S3C64XX_UCON_TIMEOUT_MASK |
557 S3C64XX_UCON_EMPTYINT_EN |
558 S3C64XX_UCON_DMASUS_EN |
559 S3C64XX_UCON_TIMEOUT_EN |
560 S3C64XX_UCON_RXMODE_MASK);
561 ucon |= S3C64XX_UCON_RXBURST_16 |
562 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
563 S3C64XX_UCON_EMPTYINT_EN |
564 S3C64XX_UCON_TIMEOUT_EN |
565 S3C64XX_UCON_RXMODE_DMA;
566 wr_regl(port, S3C2410_UCON, ucon);
567
568 ourport->rx_mode = S3C24XX_RX_DMA;
569}
570
571static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
572{
573 struct uart_port *port = &ourport->port;
574 unsigned int ucon;
575
576 /* set Rx mode to DMA mode */
577 ucon = rd_regl(port, S3C2410_UCON);
578 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
579 S3C64XX_UCON_EMPTYINT_EN |
580 S3C64XX_UCON_DMASUS_EN |
581 S3C64XX_UCON_TIMEOUT_EN |
582 S3C64XX_UCON_RXMODE_MASK);
583 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
584 S3C64XX_UCON_TIMEOUT_EN |
585 S3C64XX_UCON_RXMODE_CPU;
586 wr_regl(port, S3C2410_UCON, ucon);
587
588 ourport->rx_mode = S3C24XX_RX_PIO;
589}
590
591static irqreturn_t s3c24xx_serial_rx_chars_dma(int irq, void *dev_id)
592{
593 unsigned int utrstat, ufstat, received;
594 struct s3c24xx_uart_port *ourport = dev_id;
595 struct uart_port *port = &ourport->port;
596 struct s3c24xx_uart_dma *dma = ourport->dma;
597 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
598 struct tty_port *t = &port->state->port;
599 unsigned long flags;
600 struct dma_tx_state state;
601
602 utrstat = rd_regl(port, S3C2410_UTRSTAT);
603 ufstat = rd_regl(port, S3C2410_UFSTAT);
604
605 spin_lock_irqsave(&port->lock, flags);
606
607 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
608 s3c64xx_start_rx_dma(ourport);
609 if (ourport->rx_mode == S3C24XX_RX_PIO)
610 enable_rx_dma(ourport);
611 goto finish;
612 }
613
614 if (ourport->rx_mode == S3C24XX_RX_DMA) {
615 dmaengine_pause(dma->rx_chan);
616 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
617 dmaengine_terminate_all(dma->rx_chan);
618 received = dma->rx_bytes_requested - state.residue;
619 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
620
621 enable_rx_pio(ourport);
622 }
623
624 uart_rx_drain_fifo(ourport);
625
626 if (tty) {
627 tty_flip_buffer_push(t);
628 tty_kref_put(tty);
629 }
630
631 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
632
633finish:
634 spin_unlock_irqrestore(&port->lock, flags);
635
636 return IRQ_HANDLED;
637}
638
639static irqreturn_t s3c24xx_serial_rx_chars_pio(int irq, void *dev_id)
b497549a
BD		 640{
641 struct s3c24xx_uart_port *ourport = dev_id;
642 struct uart_port *port = &ourport->port;
b497549a 643 unsigned int ufcon, ch, flag, ufstat, uerstat;
c15c3747 644 unsigned long flags;
57850a50 645 int max_count = port->fifosize;
b497549a 646
c15c3747
TA		 647 spin_lock_irqsave(&port->lock, flags);
648
b497549a
BD		 649 while (max_count-- > 0) {
650 ufcon = rd_regl(port, S3C2410_UFCON);
651 ufstat = rd_regl(port, S3C2410_UFSTAT);
652
653 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
654 break;
655
656 uerstat = rd_regl(port, S3C2410_UERSTAT);
657 ch = rd_regb(port, S3C2410_URXH);
658
659 if (port->flags & UPF_CONS_FLOW) {
660 int txe = s3c24xx_serial_txempty_nofifo(port);
661
662 if (rx_enabled(port)) {
663 if (!txe) {
664 rx_enabled(port) = 0;
665 continue;
666 }
667 } else {
668 if (txe) {
669 ufcon |= S3C2410_UFCON_RESETRX;
670 wr_regl(port, S3C2410_UFCON, ufcon);
671 rx_enabled(port) = 1;
f5693ea2
VK		 672 spin_unlock_irqrestore(&port->lock,
673 flags);
b497549a
BD		 674 goto out;
675 }
676 continue;
677 }
678 }
679
680 /* insert the character into the buffer */
681
682 flag = TTY_NORMAL;
683 port->icount.rx++;
684
685 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
686 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
687 ch, uerstat);
688
689 /* check for break */
690 if (uerstat & S3C2410_UERSTAT_BREAK) {
691 dbg("break!\n");
692 port->icount.brk++;
693 if (uart_handle_break(port))
9303ac15 694 goto ignore_char;
b497549a
BD		 695 }
696
697 if (uerstat & S3C2410_UERSTAT_FRAME)
698 port->icount.frame++;
699 if (uerstat & S3C2410_UERSTAT_OVERRUN)
700 port->icount.overrun++;
701
702 uerstat &= port->read_status_mask;
703
704 if (uerstat & S3C2410_UERSTAT_BREAK)
705 flag = TTY_BREAK;
706 else if (uerstat & S3C2410_UERSTAT_PARITY)
707 flag = TTY_PARITY;
708 else if (uerstat & (S3C2410_UERSTAT_FRAME |
709 S3C2410_UERSTAT_OVERRUN))
710 flag = TTY_FRAME;
711 }
712
713 if (uart_handle_sysrq_char(port, ch))
714 goto ignore_char;
715
716 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
717 ch, flag);
718
ef4aca70 719ignore_char:
b497549a
BD		 720 continue;
721 }
f5693ea2
VK		 722
723 spin_unlock_irqrestore(&port->lock, flags);
2e124b4a 724 tty_flip_buffer_push(&port->state->port);
b497549a 725
ef4aca70 726out:
b497549a
BD		 727 return IRQ_HANDLED;
728}
729
b543c301
RB		 730
731static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
732{
733 struct s3c24xx_uart_port *ourport = dev_id;
734
735 if (ourport->dma && ourport->dma->rx_chan)
736 return s3c24xx_serial_rx_chars_dma(irq, dev_id);
737 return s3c24xx_serial_rx_chars_pio(irq, dev_id);
738}
739
b497549a
BD		 740static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
741{
742 struct s3c24xx_uart_port *ourport = id;
743 struct uart_port *port = &ourport->port;
ebd2c8f6 744 struct circ_buf *xmit = &port->state->xmit;
c15c3747 745 unsigned long flags;
29bef799 746 int count;
b497549a 747
c15c3747
TA		 748 spin_lock_irqsave(&port->lock, flags);
749
29bef799
RB		 750 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
751
752 if (ourport->dma && ourport->dma->tx_chan && count >= port->fifosize) {
753 s3c24xx_serial_start_tx_dma(ourport, count);
754 goto out;
755 }
756
b497549a
BD		 757 if (port->x_char) {
758 wr_regb(port, S3C2410_UTXH, port->x_char);
759 port->icount.tx++;
760 port->x_char = 0;
761 goto out;
762 }
763
25985edc 764 /* if there isn't anything more to transmit, or the uart is now
b497549a
BD		 765 * stopped, disable the uart and exit
766 */
767
768 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
769 s3c24xx_serial_stop_tx(port);
770 goto out;
771 }
772
773 /* try and drain the buffer... */
774
29bef799 775 count = port->fifosize;
b497549a
BD		 776 while (!uart_circ_empty(xmit) && count-- > 0) {
777 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
778 break;
779
780 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
781 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
782 port->icount.tx++;
783 }
784
c15c3747
TA		 785 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
786 spin_unlock(&port->lock);
b497549a 787 uart_write_wakeup(port);
c15c3747
TA		 788 spin_lock(&port->lock);
789 }
b497549a
BD		 790
791 if (uart_circ_empty(xmit))
792 s3c24xx_serial_stop_tx(port);
793
ef4aca70 794out:
c15c3747 795 spin_unlock_irqrestore(&port->lock, flags);
b497549a
BD		 796 return IRQ_HANDLED;
797}
798
88bb4ea1
TA		 799/* interrupt handler for s3c64xx and later SoC's.*/
800static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
801{
802 struct s3c24xx_uart_port *ourport = id;
803 struct uart_port *port = &ourport->port;
804 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
88bb4ea1
TA		 805 irqreturn_t ret = IRQ_HANDLED;
806
88bb4ea1
TA		 807 if (pend & S3C64XX_UINTM_RXD_MSK) {
808 ret = s3c24xx_serial_rx_chars(irq, id);
809 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
810 }
811 if (pend & S3C64XX_UINTM_TXD_MSK) {
812 ret = s3c24xx_serial_tx_chars(irq, id);
813 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
814 }
88bb4ea1
TA		 815 return ret;
816}
817
b497549a
BD		 818static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
819{
820 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
821 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
822 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
823
824 if (ufcon & S3C2410_UFCON_FIFOMODE) {
825 if ((ufstat & info->tx_fifomask) != 0 ||
826 (ufstat & info->tx_fifofull))
827 return 0;
828
829 return 1;
830 }
831
832 return s3c24xx_serial_txempty_nofifo(port);
833}
834
835/* no modem control lines */
836static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
837{
838 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
839
840 if (umstat & S3C2410_UMSTAT_CTS)
841 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
842 else
843 return TIOCM_CAR | TIOCM_DSR;
844}
845
846static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
847{
2d1e5a48
JMG		 848 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
849
850 if (mctrl & TIOCM_RTS)
851 umcon |= S3C2410_UMCOM_RTS_LOW;
852 else
853 umcon &= ~S3C2410_UMCOM_RTS_LOW;
854
855 wr_regl(port, S3C2410_UMCON, umcon);
b497549a
BD		 856}
857
858static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
859{
860 unsigned long flags;
861 unsigned int ucon;
862
863 spin_lock_irqsave(&port->lock, flags);
864
865 ucon = rd_regl(port, S3C2410_UCON);
866
867 if (break_state)
868 ucon |= S3C2410_UCON_SBREAK;
869 else
870 ucon &= ~S3C2410_UCON_SBREAK;
871
872 wr_regl(port, S3C2410_UCON, ucon);
873
874 spin_unlock_irqrestore(&port->lock, flags);
875}
876
62c37eed
RB		 877static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
878{
879 struct s3c24xx_uart_dma *dma = p->dma;
880 dma_cap_mask_t mask;
881 unsigned long flags;
882
883 /* Default slave configuration parameters */
884 dma->rx_conf.direction = DMA_DEV_TO_MEM;
885 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
886 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
887 dma->rx_conf.src_maxburst = 16;
888
889 dma->tx_conf.direction = DMA_MEM_TO_DEV;
890 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
891 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
892 if (dma_get_cache_alignment() >= 16)
893 dma->tx_conf.dst_maxburst = 16;
894 else
895 dma->tx_conf.dst_maxburst = 1;
896
897 dma_cap_zero(mask);
898 dma_cap_set(DMA_SLAVE, mask);
899
900 dma->rx_chan = dma_request_slave_channel_compat(mask, dma->fn,
901 dma->rx_param, p->port.dev, "rx");
902 if (!dma->rx_chan)
903 return -ENODEV;
904
905 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
906
907 dma->tx_chan = dma_request_slave_channel_compat(mask, dma->fn,
908 dma->tx_param, p->port.dev, "tx");
909 if (!dma->tx_chan) {
910 dma_release_channel(dma->rx_chan);
911 return -ENODEV;
912 }
913
914 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
915
916 /* RX buffer */
917 dma->rx_size = PAGE_SIZE;
918
919 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
920
921 if (!dma->rx_buf) {
922 dma_release_channel(dma->rx_chan);
923 dma_release_channel(dma->tx_chan);
924 return -ENOMEM;
925 }
926
927 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
928 dma->rx_size, DMA_FROM_DEVICE);
929
930 spin_lock_irqsave(&p->port.lock, flags);
931
932 /* TX buffer */
933 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
934 p->port.state->xmit.buf,
935 UART_XMIT_SIZE, DMA_TO_DEVICE);
936
937 spin_unlock_irqrestore(&p->port.lock, flags);
938
939 return 0;
940}
941
942static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
943{
944 struct s3c24xx_uart_dma *dma = p->dma;
945
946 if (dma->rx_chan) {
947 dmaengine_terminate_all(dma->rx_chan);
948 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
949 dma->rx_size, DMA_FROM_DEVICE);
950 kfree(dma->rx_buf);
951 dma_release_channel(dma->rx_chan);
952 dma->rx_chan = NULL;
953 }
954
955 if (dma->tx_chan) {
956 dmaengine_terminate_all(dma->tx_chan);
957 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
958 UART_XMIT_SIZE, DMA_TO_DEVICE);
959 dma_release_channel(dma->tx_chan);
960 dma->tx_chan = NULL;
961 }
962}
963
b497549a
BD		 964static void s3c24xx_serial_shutdown(struct uart_port *port)
965{
966 struct s3c24xx_uart_port *ourport = to_ourport(port);
967
968 if (ourport->tx_claimed) {
88bb4ea1
TA		 969 if (!s3c24xx_serial_has_interrupt_mask(port))
970 free_irq(ourport->tx_irq, ourport);
b497549a
BD		 971 tx_enabled(port) = 0;
972 ourport->tx_claimed = 0;
973 }
974
975 if (ourport->rx_claimed) {
88bb4ea1
TA		 976 if (!s3c24xx_serial_has_interrupt_mask(port))
977 free_irq(ourport->rx_irq, ourport);
b497549a
BD		 978 ourport->rx_claimed = 0;
979 rx_enabled(port) = 0;
980 }
b497549a 981
88bb4ea1
TA		 982 /* Clear pending interrupts and mask all interrupts */
983 if (s3c24xx_serial_has_interrupt_mask(port)) {
b6ad2935
TF		 984 free_irq(port->irq, ourport);
985
88bb4ea1
TA		 986 wr_regl(port, S3C64XX_UINTP, 0xf);
987 wr_regl(port, S3C64XX_UINTM, 0xf);
988 }
62c37eed
RB		 989
990 if (ourport->dma)
991 s3c24xx_serial_release_dma(ourport);
992
29bef799 993 ourport->tx_in_progress = 0;
88bb4ea1 994}
b497549a
BD		 995
996static int s3c24xx_serial_startup(struct uart_port *port)
997{
998 struct s3c24xx_uart_port *ourport = to_ourport(port);
999 int ret;
1000
e4ac92df
JP		 1001 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
1002 port, (unsigned long long)port->mapbase, port->membase);
b497549a
BD		 1003
1004 rx_enabled(port) = 1;
1005
b73c289c 1006 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
b497549a
BD		 1007 s3c24xx_serial_portname(port), ourport);
1008
1009 if (ret != 0) {
d20925e1 1010 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
b497549a
BD		 1011 return ret;
1012 }
1013
1014 ourport->rx_claimed = 1;
1015
1016 dbg("requesting tx irq...\n");
1017
1018 tx_enabled(port) = 1;
1019
b73c289c 1020 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
b497549a
BD		 1021 s3c24xx_serial_portname(port), ourport);
1022
1023 if (ret) {
d20925e1 1024 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
b497549a
BD		 1025 goto err;
1026 }
1027
1028 ourport->tx_claimed = 1;
1029
1030 dbg("s3c24xx_serial_startup ok\n");
1031
1032 /* the port reset code should have done the correct
1033 * register setup for the port controls */
1034
1035 return ret;
1036
ef4aca70 1037err:
b497549a
BD		 1038 s3c24xx_serial_shutdown(port);
1039 return ret;
1040}
1041
88bb4ea1
TA		 1042static int s3c64xx_serial_startup(struct uart_port *port)
1043{
1044 struct s3c24xx_uart_port *ourport = to_ourport(port);
b543c301
RB		 1045 unsigned long flags;
1046 unsigned int ufcon;
88bb4ea1
TA		 1047 int ret;
1048
e4ac92df
JP		 1049 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1050 port, (unsigned long long)port->mapbase, port->membase);
88bb4ea1 1051
b6ad2935 1052 wr_regl(port, S3C64XX_UINTM, 0xf);
62c37eed
RB		 1053 if (ourport->dma) {
1054 ret = s3c24xx_serial_request_dma(ourport);
1055 if (ret < 0) {
1056 dev_warn(port->dev, "DMA request failed\n");
1057 return ret;
1058 }
1059 }
b6ad2935 1060
88bb4ea1
TA		 1061 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1062 s3c24xx_serial_portname(port), ourport);
1063 if (ret) {
d20925e1 1064 dev_err(port->dev, "cannot get irq %d\n", port->irq);
88bb4ea1
TA		 1065 return ret;
1066 }
1067
1068 /* For compatibility with s3c24xx Soc's */
1069 rx_enabled(port) = 1;
1070 ourport->rx_claimed = 1;
1071 tx_enabled(port) = 0;
1072 ourport->tx_claimed = 1;
1073
29bef799
RB		 1074 spin_lock_irqsave(&port->lock, flags);
1075
1076 ufcon = rd_regl(port, S3C2410_UFCON);
b543c301
RB		 1077 ufcon |= S3C2410_UFCON_RESETRX | S3C2410_UFCON_RESETTX |
1078 S5PV210_UFCON_RXTRIG8;
29bef799
RB		 1079 wr_regl(port, S3C2410_UFCON, ufcon);
1080
1081 enable_rx_pio(ourport);
1082
1083 spin_unlock_irqrestore(&port->lock, flags);
1084
88bb4ea1
TA		 1085 /* Enable Rx Interrupt */
1086 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
29bef799 1087
88bb4ea1
TA		 1088 dbg("s3c64xx_serial_startup ok\n");
1089 return ret;
1090}
1091
b497549a
BD		 1092/* power power management control */
1093
1094static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1095 unsigned int old)
1096{
1097 struct s3c24xx_uart_port *ourport = to_ourport(port);
1ff383a4 1098 int timeout = 10000;
b497549a 1099
30555476
BD		 1100 ourport->pm_level = level;
1101
b497549a
BD		 1102 switch (level) {
1103 case 3:
1ff383a4
RB		 1104 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1105 udelay(100);
1106
7cd88831 1107 if (!IS_ERR(ourport->baudclk))
9484b009 1108 clk_disable_unprepare(ourport->baudclk);
b497549a 1109
9484b009 1110 clk_disable_unprepare(ourport->clk);
b497549a
BD		 1111 break;
1112
1113 case 0:
9484b009 1114 clk_prepare_enable(ourport->clk);
b497549a 1115
7cd88831 1116 if (!IS_ERR(ourport->baudclk))
9484b009 1117 clk_prepare_enable(ourport->baudclk);
b497549a
BD		 1118
1119 break;
1120 default:
d20925e1 1121 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
b497549a
BD		 1122 }
1123}
1124
1125/* baud rate calculation
1126 *
1127 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1128 * of different sources, including the peripheral clock ("pclk") and an
1129 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1130 * with a programmable extra divisor.
1131 *
1132 * The following code goes through the clock sources, and calculates the
1133 * baud clocks (and the resultant actual baud rates) and then tries to
1134 * pick the closest one and select that.
1135 *
1136*/
1137
5f5a7a55 1138#define MAX_CLK_NAME_LENGTH 15
b497549a 1139
5f5a7a55 1140static inline int s3c24xx_serial_getsource(struct uart_port *port)
b497549a
BD		 1141{
1142 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
5f5a7a55 1143 unsigned int ucon;
b497549a 1144
5f5a7a55
TA		 1145 if (info->num_clks == 1)
1146 return 0;
b497549a 1147
5f5a7a55
TA		 1148 ucon = rd_regl(port, S3C2410_UCON);
1149 ucon &= info->clksel_mask;
1150 return ucon >> info->clksel_shift;
b497549a
BD		 1151}
1152
5f5a7a55
TA		 1153static void s3c24xx_serial_setsource(struct uart_port *port,
1154 unsigned int clk_sel)
b497549a 1155{
5f5a7a55
TA		 1156 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1157 unsigned int ucon;
b497549a 1158
5f5a7a55
TA		 1159 if (info->num_clks == 1)
1160 return;
090f848d 1161
5f5a7a55
TA		 1162 ucon = rd_regl(port, S3C2410_UCON);
1163 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1164 return;
b497549a 1165
5f5a7a55
TA		 1166 ucon &= ~info->clksel_mask;
1167 ucon |= clk_sel << info->clksel_shift;
1168 wr_regl(port, S3C2410_UCON, ucon);
b497549a
BD		 1169}
1170
5f5a7a55
TA		 1171static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1172 unsigned int req_baud, struct clk **best_clk,
1173 unsigned int *clk_num)
b497549a 1174{
5f5a7a55
TA		 1175 struct s3c24xx_uart_info *info = ourport->info;
1176 struct clk *clk;
1177 unsigned long rate;
1178 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1179 char clkname[MAX_CLK_NAME_LENGTH];
1180 int calc_deviation, deviation = (1 << 30) - 1;
1181
5f5a7a55
TA		 1182 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1183 ourport->info->def_clk_sel;
1184 for (cnt = 0; cnt < info->num_clks; cnt++) {
1185 if (!(clk_sel & (1 << cnt)))
1186 continue;
1187
1188 sprintf(clkname, "clk_uart_baud%d", cnt);
1189 clk = clk_get(ourport->port.dev, clkname);
7cd88831 1190 if (IS_ERR(clk))
5f5a7a55
TA		 1191 continue;
1192
1193 rate = clk_get_rate(clk);
1194 if (!rate)
1195 continue;
1196
1197 if (ourport->info->has_divslot) {
1198 unsigned long div = rate / req_baud;
1199
1200 /* The UDIVSLOT register on the newer UARTs allows us to
1201 * get a divisor adjustment of 1/16th on the baud clock.
1202 *
1203 * We don't keep the UDIVSLOT value (the 16ths we
1204 * calculated by not multiplying the baud by 16) as it
1205 * is easy enough to recalculate.
1206 */
1207
1208 quot = div / 16;
1209 baud = rate / div;
1210 } else {
1211 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1212 baud = rate / (quot * 16);
b497549a 1213 }
5f5a7a55 1214 quot--;
b497549a 1215
5f5a7a55
TA		 1216 calc_deviation = req_baud - baud;
1217 if (calc_deviation < 0)
1218 calc_deviation = -calc_deviation;
b497549a 1219
5f5a7a55
TA		 1220 if (calc_deviation < deviation) {
1221 *best_clk = clk;
1222 best_quot = quot;
1223 *clk_num = cnt;
1224 deviation = calc_deviation;
b497549a
BD		 1225 }
1226 }
1227
5f5a7a55 1228 return best_quot;
b497549a
BD		 1229}
1230
090f848d
BD		 1231/* udivslot_table[]
1232 *
1233 * This table takes the fractional value of the baud divisor and gives
1234 * the recommended setting for the UDIVSLOT register.
1235 */
1236static u16 udivslot_table[16] = {
1237 [0] = 0x0000,
1238 [1] = 0x0080,
1239 [2] = 0x0808,
1240 [3] = 0x0888,
1241 [4] = 0x2222,
1242 [5] = 0x4924,
1243 [6] = 0x4A52,
1244 [7] = 0x54AA,
1245 [8] = 0x5555,
1246 [9] = 0xD555,
1247 [10] = 0xD5D5,
1248 [11] = 0xDDD5,
1249 [12] = 0xDDDD,
1250 [13] = 0xDFDD,
1251 [14] = 0xDFDF,
1252 [15] = 0xFFDF,
1253};
1254
b497549a
BD		 1255static void s3c24xx_serial_set_termios(struct uart_port *port,
1256 struct ktermios *termios,
1257 struct ktermios *old)
1258{
1259 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1260 struct s3c24xx_uart_port *ourport = to_ourport(port);
7cd88831 1261 struct clk *clk = ERR_PTR(-EINVAL);
b497549a 1262 unsigned long flags;
5f5a7a55 1263 unsigned int baud, quot, clk_sel = 0;
b497549a
BD		 1264 unsigned int ulcon;
1265 unsigned int umcon;
090f848d 1266 unsigned int udivslot = 0;
b497549a
BD		 1267
1268 /*
1269 * We don't support modem control lines.
1270 */
1271 termios->c_cflag &= ~(HUPCL | CMSPAR);
1272 termios->c_cflag |= CLOCAL;
1273
1274 /*
1275 * Ask the core to calculate the divisor for us.
1276 */
1277
1278 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
5f5a7a55 1279 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
b497549a
BD		 1280 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1281 quot = port->custom_divisor;
7cd88831 1282 if (IS_ERR(clk))
5f5a7a55 1283 return;
b497549a
BD		 1284
1285 /* check to see if we need to change clock source */
1286
5f5a7a55
TA		 1287 if (ourport->baudclk != clk) {
1288 s3c24xx_serial_setsource(port, clk_sel);
b497549a 1289
7cd88831 1290 if (!IS_ERR(ourport->baudclk)) {
9484b009 1291 clk_disable_unprepare(ourport->baudclk);
7cd88831 1292 ourport->baudclk = ERR_PTR(-EINVAL);
b497549a
BD		 1293 }
1294
9484b009 1295 clk_prepare_enable(clk);
b497549a 1296
b497549a 1297 ourport->baudclk = clk;
30555476 1298 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
b497549a
BD		 1299 }
1300
090f848d
BD		 1301 if (ourport->info->has_divslot) {
1302 unsigned int div = ourport->baudclk_rate / baud;
1303
8b526ae4
JL		 1304 if (cfg->has_fracval) {
1305 udivslot = (div & 15);
1306 dbg("fracval = %04x\n", udivslot);
1307 } else {
1308 udivslot = udivslot_table[div & 15];
1309 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1310 }
090f848d
BD		 1311 }
1312
b497549a
BD		 1313 switch (termios->c_cflag & CSIZE) {
1314 case CS5:
1315 dbg("config: 5bits/char\n");
1316 ulcon = S3C2410_LCON_CS5;
1317 break;
1318 case CS6:
1319 dbg("config: 6bits/char\n");
1320 ulcon = S3C2410_LCON_CS6;
1321 break;
1322 case CS7:
1323 dbg("config: 7bits/char\n");
1324 ulcon = S3C2410_LCON_CS7;
1325 break;
1326 case CS8:
1327 default:
1328 dbg("config: 8bits/char\n");
1329 ulcon = S3C2410_LCON_CS8;
1330 break;
1331 }
1332
1333 /* preserve original lcon IR settings */
1334 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1335
1336 if (termios->c_cflag & CSTOPB)
1337 ulcon |= S3C2410_LCON_STOPB;
1338
b497549a
BD		 1339 if (termios->c_cflag & PARENB) {
1340 if (termios->c_cflag & PARODD)
1341 ulcon |= S3C2410_LCON_PODD;
1342 else
1343 ulcon |= S3C2410_LCON_PEVEN;
1344 } else {
1345 ulcon |= S3C2410_LCON_PNONE;
1346 }
1347
1348 spin_lock_irqsave(&port->lock, flags);
1349
090f848d
BD		 1350 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1351 ulcon, quot, udivslot);
b497549a
BD		 1352
1353 wr_regl(port, S3C2410_ULCON, ulcon);
1354 wr_regl(port, S3C2410_UBRDIV, quot);
2d1e5a48
JMG		 1355
1356 umcon = rd_regl(port, S3C2410_UMCON);
1357 if (termios->c_cflag & CRTSCTS) {
1358 umcon |= S3C2410_UMCOM_AFC;
1359 /* Disable RTS when RX FIFO contains 63 bytes */
1360 umcon &= ~S3C2412_UMCON_AFC_8;
1361 } else {
1362 umcon &= ~S3C2410_UMCOM_AFC;
1363 }
b497549a
BD		 1364 wr_regl(port, S3C2410_UMCON, umcon);
1365
090f848d
BD		 1366 if (ourport->info->has_divslot)
1367 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1368
b497549a
BD		 1369 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1370 rd_regl(port, S3C2410_ULCON),
1371 rd_regl(port, S3C2410_UCON),
1372 rd_regl(port, S3C2410_UFCON));
1373
1374 /*
1375 * Update the per-port timeout.
1376 */
1377 uart_update_timeout(port, termios->c_cflag, baud);
1378
1379 /*
1380 * Which character status flags are we interested in?
1381 */
1382 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1383 if (termios->c_iflag & INPCK)
ef4aca70
RB		 1384 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1385 S3C2410_UERSTAT_PARITY;
b497549a
BD		 1386 /*
1387 * Which character status flags should we ignore?
1388 */
1389 port->ignore_status_mask = 0;
1390 if (termios->c_iflag & IGNPAR)
1391 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1392 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1393 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1394
1395 /*
1396 * Ignore all characters if CREAD is not set.
1397 */
1398 if ((termios->c_cflag & CREAD) == 0)
1399 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1400
1401 spin_unlock_irqrestore(&port->lock, flags);
1402}
1403
1404static const char *s3c24xx_serial_type(struct uart_port *port)
1405{
1406 switch (port->type) {
1407 case PORT_S3C2410:
1408 return "S3C2410";
1409 case PORT_S3C2440:
1410 return "S3C2440";
1411 case PORT_S3C2412:
1412 return "S3C2412";
b690ace5
BD		 1413 case PORT_S3C6400:
1414 return "S3C6400/10";
b497549a
BD		 1415 default:
1416 return NULL;
1417 }
1418}
1419
1420#define MAP_SIZE (0x100)
1421
1422static void s3c24xx_serial_release_port(struct uart_port *port)
1423{
1424 release_mem_region(port->mapbase, MAP_SIZE);
1425}
1426
1427static int s3c24xx_serial_request_port(struct uart_port *port)
1428{
1429 const char *name = s3c24xx_serial_portname(port);
1430 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1431}
1432
1433static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1434{
1435 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1436
1437 if (flags & UART_CONFIG_TYPE &&
1438 s3c24xx_serial_request_port(port) == 0)
1439 port->type = info->type;
1440}
1441
1442/*
1443 * verify the new serial_struct (for TIOCSSERIAL).
1444 */
1445static int
1446s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1447{
1448 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1449
1450 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1451 return -EINVAL;
1452
1453 return 0;
1454}
1455
1456
1457#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1458
1459static struct console s3c24xx_serial_console;
1460
93b5c032
JP		 1461static int __init s3c24xx_serial_console_init(void)
1462{
1463 register_console(&s3c24xx_serial_console);
1464 return 0;
1465}
1466console_initcall(s3c24xx_serial_console_init);
1467
b497549a
BD		 1468#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1469#else
1470#define S3C24XX_SERIAL_CONSOLE NULL
1471#endif
1472
84f57d9e 1473#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 1474static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1475static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1476 unsigned char c);
1477#endif
1478
b497549a
BD		 1479static struct uart_ops s3c24xx_serial_ops = {
1480 .pm = s3c24xx_serial_pm,
1481 .tx_empty = s3c24xx_serial_tx_empty,
1482 .get_mctrl = s3c24xx_serial_get_mctrl,
1483 .set_mctrl = s3c24xx_serial_set_mctrl,
1484 .stop_tx = s3c24xx_serial_stop_tx,
1485 .start_tx = s3c24xx_serial_start_tx,
1486 .stop_rx = s3c24xx_serial_stop_rx,
b497549a
BD		 1487 .break_ctl = s3c24xx_serial_break_ctl,
1488 .startup = s3c24xx_serial_startup,
1489 .shutdown = s3c24xx_serial_shutdown,
1490 .set_termios = s3c24xx_serial_set_termios,
1491 .type = s3c24xx_serial_type,
1492 .release_port = s3c24xx_serial_release_port,
1493 .request_port = s3c24xx_serial_request_port,
1494 .config_port = s3c24xx_serial_config_port,
1495 .verify_port = s3c24xx_serial_verify_port,
84f57d9e 1496#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 1497 .poll_get_char = s3c24xx_serial_get_poll_char,
1498 .poll_put_char = s3c24xx_serial_put_poll_char,
1499#endif
b497549a
BD		 1500};
1501
b497549a
BD		 1502static struct uart_driver s3c24xx_uart_drv = {
1503 .owner = THIS_MODULE,
2cf0c58e 1504 .driver_name = "s3c2410_serial",
bdd4915a 1505 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
b497549a 1506 .cons = S3C24XX_SERIAL_CONSOLE,
2cf0c58e 1507 .dev_name = S3C24XX_SERIAL_NAME,
b497549a
BD		 1508 .major = S3C24XX_SERIAL_MAJOR,
1509 .minor = S3C24XX_SERIAL_MINOR,
1510};
1511
ef4aca70
RB		 1512#define __PORT_LOCK_UNLOCKED(i) \
1513 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1514static struct s3c24xx_uart_port
1515s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
b497549a
BD		 1516 [0] = {
1517 .port = {
ef4aca70 1518 .lock = __PORT_LOCK_UNLOCKED(0),
b497549a 1519 .iotype = UPIO_MEM,
b497549a
BD		 1520 .uartclk = 0,
1521 .fifosize = 16,
1522 .ops = &s3c24xx_serial_ops,
1523 .flags = UPF_BOOT_AUTOCONF,
1524 .line = 0,
1525 }
1526 },
1527 [1] = {
1528 .port = {
ef4aca70 1529 .lock = __PORT_LOCK_UNLOCKED(1),
b497549a 1530 .iotype = UPIO_MEM,
b497549a
BD		 1531 .uartclk = 0,
1532 .fifosize = 16,
1533 .ops = &s3c24xx_serial_ops,
1534 .flags = UPF_BOOT_AUTOCONF,
1535 .line = 1,
1536 }
1537 },
03d5e77b 1538#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
b497549a
BD		 1539
1540 [2] = {
1541 .port = {
ef4aca70 1542 .lock = __PORT_LOCK_UNLOCKED(2),
b497549a 1543 .iotype = UPIO_MEM,
b497549a
BD		 1544 .uartclk = 0,
1545 .fifosize = 16,
1546 .ops = &s3c24xx_serial_ops,
1547 .flags = UPF_BOOT_AUTOCONF,
1548 .line = 2,
1549 }
03d5e77b
BD		 1550 },
1551#endif
1552#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1553 [3] = {
1554 .port = {
ef4aca70 1555 .lock = __PORT_LOCK_UNLOCKED(3),
03d5e77b 1556 .iotype = UPIO_MEM,
03d5e77b
BD		 1557 .uartclk = 0,
1558 .fifosize = 16,
1559 .ops = &s3c24xx_serial_ops,
1560 .flags = UPF_BOOT_AUTOCONF,
1561 .line = 3,
1562 }
b497549a
BD		 1563 }
1564#endif
1565};
ef4aca70 1566#undef __PORT_LOCK_UNLOCKED
b497549a
BD		 1567
1568/* s3c24xx_serial_resetport
1569 *
0dfb3b41 1570 * reset the fifos and other the settings.
b497549a
BD		 1571*/
1572
0dfb3b41
TA		 1573static void s3c24xx_serial_resetport(struct uart_port *port,
1574 struct s3c2410_uartcfg *cfg)
b497549a
BD		 1575{
1576 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
0dfb3b41
TA		 1577 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1578 unsigned int ucon_mask;
b497549a 1579
0dfb3b41
TA		 1580 ucon_mask = info->clksel_mask;
1581 if (info->type == PORT_S3C2440)
1582 ucon_mask |= S3C2440_UCON0_DIVMASK;
1583
1584 ucon &= ucon_mask;
1585 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1586
1587 /* reset both fifos */
1588 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1589 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1590
1591 /* some delay is required after fifo reset */
1592 udelay(1);
b497549a
BD		 1593}
1594
30555476
BD		 1595
1596#ifdef CONFIG_CPU_FREQ
1597
1598static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1599 unsigned long val, void *data)
1600{
1601 struct s3c24xx_uart_port *port;
1602 struct uart_port *uport;
1603
1604 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1605 uport = &port->port;
1606
1607 /* check to see if port is enabled */
1608
1609 if (port->pm_level != 0)
1610 return 0;
1611
1612 /* try and work out if the baudrate is changing, we can detect
1613 * a change in rate, but we do not have support for detecting
1614 * a disturbance in the clock-rate over the change.
1615 */
1616
25f04ad4 1617 if (IS_ERR(port->baudclk))
30555476
BD		 1618 goto exit;
1619
25f04ad4 1620 if (port->baudclk_rate == clk_get_rate(port->baudclk))
30555476
BD		 1621 goto exit;
1622
1623 if (val == CPUFREQ_PRECHANGE) {
1624 /* we should really shut the port down whilst the
1625 * frequency change is in progress. */
1626
1627 } else if (val == CPUFREQ_POSTCHANGE) {
1628 struct ktermios *termios;
1629 struct tty_struct *tty;
1630
ebd2c8f6 1631 if (uport->state == NULL)
30555476 1632 goto exit;
30555476 1633
ebd2c8f6 1634 tty = uport->state->port.tty;
30555476 1635
7de40c21 1636 if (tty == NULL)
30555476 1637 goto exit;
30555476 1638
adc8d746 1639 termios = &tty->termios;
30555476
BD		 1640
1641 if (termios == NULL) {
d20925e1 1642 dev_warn(uport->dev, "%s: no termios?\n", __func__);
30555476
BD		 1643 goto exit;
1644 }
1645
1646 s3c24xx_serial_set_termios(uport, termios, NULL);
1647 }
1648
ef4aca70 1649exit:
30555476
BD		 1650 return 0;
1651}
1652
ef4aca70
RB		 1653static inline int
1654s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
30555476
BD		 1655{
1656 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1657
1658 return cpufreq_register_notifier(&port->freq_transition,
1659 CPUFREQ_TRANSITION_NOTIFIER);
1660}
1661
ef4aca70
RB		 1662static inline void
1663s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
30555476
BD		 1664{
1665 cpufreq_unregister_notifier(&port->freq_transition,
1666 CPUFREQ_TRANSITION_NOTIFIER);
1667}
1668
1669#else
ef4aca70
RB		 1670static inline int
1671s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
30555476
BD		 1672{
1673 return 0;
1674}
1675
ef4aca70
RB		 1676static inline void
1677s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
30555476
BD		 1678{
1679}
1680#endif
1681
b497549a
BD		 1682/* s3c24xx_serial_init_port
1683 *
1684 * initialise a single serial port from the platform device given
1685 */
1686
1687static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
b497549a
BD		 1688 struct platform_device *platdev)
1689{
1690 struct uart_port *port = &ourport->port;
da121506 1691 struct s3c2410_uartcfg *cfg = ourport->cfg;
b497549a
BD		 1692 struct resource *res;
1693 int ret;
1694
1695 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1696
1697 if (platdev == NULL)
1698 return -ENODEV;
1699
b497549a
BD		 1700 if (port->mapbase != 0)
1701 return 0;
1702
b497549a
BD		 1703 /* setup info for port */
1704 port->dev = &platdev->dev;
b497549a 1705
88bb4ea1
TA		 1706 /* Startup sequence is different for s3c64xx and higher SoC's */
1707 if (s3c24xx_serial_has_interrupt_mask(port))
1708 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1709
b497549a
BD		 1710 port->uartclk = 1;
1711
1712 if (cfg->uart_flags & UPF_CONS_FLOW) {
1713 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1714 port->flags |= UPF_CONS_FLOW;
1715 }
1716
1717 /* sort our the physical and virtual addresses for each UART */
1718
1719 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1720 if (res == NULL) {
d20925e1 1721 dev_err(port->dev, "failed to find memory resource for uart\n");
b497549a
BD		 1722 return -EINVAL;
1723 }
1724
e4ac92df 1725 dbg("resource %pR)\n", res);
b497549a 1726
41147bfd
TA		 1727 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1728 if (!port->membase) {
1729 dev_err(port->dev, "failed to remap controller address\n");
1730 return -EBUSY;
1731 }
1732
b690ace5 1733 port->mapbase = res->start;
b497549a
BD		 1734 ret = platform_get_irq(platdev, 0);
1735 if (ret < 0)
1736 port->irq = 0;
b73c289c 1737 else {
b497549a 1738 port->irq = ret;
b73c289c
BD		 1739 ourport->rx_irq = ret;
1740 ourport->tx_irq = ret + 1;
1741 }
9303ac15 1742
b73c289c
BD		 1743 ret = platform_get_irq(platdev, 1);
1744 if (ret > 0)
1745 ourport->tx_irq = ret;
658c9d2b
RB		 1746 /*
1747 * DMA is currently supported only on DT platforms, if DMA properties
1748 * are specified.
1749 */
1750 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1751 "dmas", NULL)) {
1752 ourport->dma = devm_kzalloc(port->dev,
1753 sizeof(*ourport->dma),
1754 GFP_KERNEL);
1755 if (!ourport->dma)
1756 return -ENOMEM;
1757 }
b497549a
BD		 1758
1759 ourport->clk = clk_get(&platdev->dev, "uart");
60e93575
CK		 1760 if (IS_ERR(ourport->clk)) {
1761 pr_err("%s: Controller clock not found\n",
1762 dev_name(&platdev->dev));
1763 return PTR_ERR(ourport->clk);
1764 }
1765
1766 ret = clk_prepare_enable(ourport->clk);
1767 if (ret) {
1768 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1769 clk_put(ourport->clk);
1770 return ret;
1771 }
b497549a 1772
88bb4ea1
TA		 1773 /* Keep all interrupts masked and cleared */
1774 if (s3c24xx_serial_has_interrupt_mask(port)) {
1775 wr_regl(port, S3C64XX_UINTM, 0xf);
1776 wr_regl(port, S3C64XX_UINTP, 0xf);
1777 wr_regl(port, S3C64XX_UINTSP, 0xf);
1778 }
1779
1ff5b64d
FE		 1780 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1781 &port->mapbase, port->membase, port->irq,
b73c289c 1782 ourport->rx_irq, ourport->tx_irq, port->uartclk);
b497549a
BD		 1783
1784 /* reset the fifos (and setup the uart) */
1785 s3c24xx_serial_resetport(port, cfg);
1786 return 0;
1787}
1788
b497549a
BD		 1789/* Device driver serial port probe */
1790
26c919e1 1791static const struct of_device_id s3c24xx_uart_dt_match[];
b497549a
BD		 1792static int probe_index;
1793
26c919e1
TA		 1794static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1795 struct platform_device *pdev)
1796{
1797#ifdef CONFIG_OF
1798 if (pdev->dev.of_node) {
1799 const struct of_device_id *match;
1800 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1801 return (struct s3c24xx_serial_drv_data *)match->data;
1802 }
1803#endif
1804 return (struct s3c24xx_serial_drv_data *)
1805 platform_get_device_id(pdev)->driver_data;
1806}
1807
da121506 1808static int s3c24xx_serial_probe(struct platform_device *pdev)
b497549a 1809{
4622eb68 1810 struct device_node *np = pdev->dev.of_node;
b497549a 1811 struct s3c24xx_uart_port *ourport;
13a9f6c6 1812 int index = probe_index;
b497549a
BD		 1813 int ret;
1814
4622eb68
NKC		 1815 if (np) {
1816 ret = of_alias_get_id(np, "serial");
13a9f6c6
TF		 1817 if (ret >= 0)
1818 index = ret;
1819 }
1820
1821 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
b497549a 1822
13a9f6c6 1823 ourport = &s3c24xx_serial_ports[index];
da121506 1824
26c919e1
TA		 1825 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1826 if (!ourport->drv_data) {
1827 dev_err(&pdev->dev, "could not find driver data\n");
1828 return -ENODEV;
1829 }
da121506 1830
7cd88831 1831 ourport->baudclk = ERR_PTR(-EINVAL);
da121506 1832 ourport->info = ourport->drv_data->info;
574de559 1833 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
d4aab206 1834 dev_get_platdata(&pdev->dev) :
da121506
TA		 1835 ourport->drv_data->def_cfg;
1836
4622eb68
NKC		 1837 if (np)
1838 of_property_read_u32(np,
135f07c3
NKC		 1839 "samsung,uart-fifosize", &ourport->port.fifosize);
1840
2f1ba72d
RB		 1841 if (ourport->drv_data->fifosize[index])
1842 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1843 else if (ourport->info->fifosize)
1844 ourport->port.fifosize = ourport->info->fifosize;
da121506 1845
b497549a
BD		 1846 probe_index++;
1847
1848 dbg("%s: initialising port %p...\n", __func__, ourport);
1849
da121506 1850 ret = s3c24xx_serial_init_port(ourport, pdev);
b497549a 1851 if (ret < 0)
8ad711a9 1852 return ret;
b497549a 1853
6f134c3c
TB		 1854 if (!s3c24xx_uart_drv.state) {
1855 ret = uart_register_driver(&s3c24xx_uart_drv);
1856 if (ret < 0) {
1857 pr_err("Failed to register Samsung UART driver\n");
1858 return ret;
1859 }
1860 }
1861
b497549a
BD		 1862 dbg("%s: adding port\n", __func__);
1863 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
da121506 1864 platform_set_drvdata(pdev, &ourport->port);
b497549a 1865
0da3336f
HS		 1866 /*
1867 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1868 * so that a potential re-enablement through the pm-callback overlaps
1869 * and keeps the clock enabled in this case.
1870 */
1871 clk_disable_unprepare(ourport->clk);
1872
30555476
BD		 1873 ret = s3c24xx_serial_cpufreq_register(ourport);
1874 if (ret < 0)
da121506 1875 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
30555476 1876
b497549a 1877 return 0;
b497549a
BD		 1878}
1879
ae8d8a14 1880static int s3c24xx_serial_remove(struct platform_device *dev)
b497549a
BD		 1881{
1882 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1883
1884 if (port) {
30555476 1885 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
b497549a
BD		 1886 uart_remove_one_port(&s3c24xx_uart_drv, port);
1887 }
1888
6f134c3c
TB		 1889 uart_unregister_driver(&s3c24xx_uart_drv);
1890
b497549a
BD		 1891 return 0;
1892}
1893
b497549a 1894/* UART power management code */
aef7fe52
MH		 1895#ifdef CONFIG_PM_SLEEP
1896static int s3c24xx_serial_suspend(struct device *dev)
b497549a 1897{
aef7fe52 1898 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1899
1900 if (port)
1901 uart_suspend_port(&s3c24xx_uart_drv, port);
1902
1903 return 0;
1904}
1905
aef7fe52 1906static int s3c24xx_serial_resume(struct device *dev)
b497549a 1907{
aef7fe52 1908 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1909 struct s3c24xx_uart_port *ourport = to_ourport(port);
1910
1911 if (port) {
9484b009 1912 clk_prepare_enable(ourport->clk);
b497549a 1913 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
9484b009 1914 clk_disable_unprepare(ourport->clk);
b497549a
BD		 1915
1916 uart_resume_port(&s3c24xx_uart_drv, port);
1917 }
1918
1919 return 0;
1920}
aef7fe52 1921
d09a7308
MS		 1922static int s3c24xx_serial_resume_noirq(struct device *dev)
1923{
1924 struct uart_port *port = s3c24xx_dev_to_port(dev);
1925
1926 if (port) {
1927 /* restore IRQ mask */
1928 if (s3c24xx_serial_has_interrupt_mask(port)) {
1929 unsigned int uintm = 0xf;
1930 if (tx_enabled(port))
1931 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1932 if (rx_enabled(port))
1933 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1934 wr_regl(port, S3C64XX_UINTM, uintm);
1935 }
1936 }
1937
1938 return 0;
1939}
1940
aef7fe52
MH		 1941static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1942 .suspend = s3c24xx_serial_suspend,
1943 .resume = s3c24xx_serial_resume,
d09a7308 1944 .resume_noirq = s3c24xx_serial_resume_noirq,
aef7fe52 1945};
b882fc1b
KK		 1946#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1947
aef7fe52 1948#else /* !CONFIG_PM_SLEEP */
b882fc1b
KK		 1949
1950#define SERIAL_SAMSUNG_PM_OPS NULL
aef7fe52 1951#endif /* CONFIG_PM_SLEEP */
b497549a 1952
b497549a
BD		 1953/* Console code */
1954
1955#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1956
1957static struct uart_port *cons_uart;
1958
1959static int
1960s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1961{
1962 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1963 unsigned long ufstat, utrstat;
1964
1965 if (ufcon & S3C2410_UFCON_FIFOMODE) {
9ddc5b6f 1966 /* fifo mode - check amount of data in fifo registers... */
b497549a
BD		 1967
1968 ufstat = rd_regl(port, S3C2410_UFSTAT);
1969 return (ufstat & info->tx_fifofull) ? 0 : 1;
1970 }
1971
1972 /* in non-fifo mode, we go and use the tx buffer empty */
1973
1974 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1975 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1976}
1977
38adbc54
MS		 1978static bool
1979s3c24xx_port_configured(unsigned int ucon)
1980{
1981 /* consider the serial port configured if the tx/rx mode set */
1982 return (ucon & 0xf) != 0;
1983}
1984
93b5c032
JP		 1985#ifdef CONFIG_CONSOLE_POLL
1986/*
1987 * Console polling routines for writing and reading from the uart while
1988 * in an interrupt or debug context.
1989 */
1990
1991static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1992{
1993 struct s3c24xx_uart_port *ourport = to_ourport(port);
1994 unsigned int ufstat;
1995
1996 ufstat = rd_regl(port, S3C2410_UFSTAT);
1997 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1998 return NO_POLL_CHAR;
1999
2000 return rd_regb(port, S3C2410_URXH);
2001}
2002
2003static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2004 unsigned char c)
2005{
bb7f09ba
DA		 2006 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2007 unsigned int ucon = rd_regl(port, S3C2410_UCON);
38adbc54
MS		 2008
2009 /* not possible to xmit on unconfigured port */
2010 if (!s3c24xx_port_configured(ucon))
2011 return;
93b5c032
JP		 2012
2013 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2014 cpu_relax();
bb7f09ba 2015 wr_regb(port, S3C2410_UTXH, c);
93b5c032
JP		 2016}
2017
2018#endif /* CONFIG_CONSOLE_POLL */
2019
b497549a
BD		 2020static void
2021s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2022{
bb7f09ba 2023 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
38adbc54 2024
b497549a 2025 while (!s3c24xx_serial_console_txrdy(port, ufcon))
f94b0572 2026 cpu_relax();
bb7f09ba 2027 wr_regb(port, S3C2410_UTXH, ch);
b497549a
BD		 2028}
2029
2030static void
2031s3c24xx_serial_console_write(struct console *co, const char *s,
2032 unsigned int count)
2033{
ab88c8dc
DA		 2034 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2035
2036 /* not possible to xmit on unconfigured port */
2037 if (!s3c24xx_port_configured(ucon))
2038 return;
2039
b497549a
BD		 2040 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2041}
2042
2043static void __init
2044s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2045 int *parity, int *bits)
2046{
b497549a
BD		 2047 struct clk *clk;
2048 unsigned int ulcon;
2049 unsigned int ucon;
2050 unsigned int ubrdiv;
2051 unsigned long rate;
5f5a7a55
TA		 2052 unsigned int clk_sel;
2053 char clk_name[MAX_CLK_NAME_LENGTH];
b497549a
BD		 2054
2055 ulcon = rd_regl(port, S3C2410_ULCON);
2056 ucon = rd_regl(port, S3C2410_UCON);
2057 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2058
2059 dbg("s3c24xx_serial_get_options: port=%p\n"
2060 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2061 port, ulcon, ucon, ubrdiv);
2062
38adbc54 2063 if (s3c24xx_port_configured(ucon)) {
b497549a
BD		 2064 switch (ulcon & S3C2410_LCON_CSMASK) {
2065 case S3C2410_LCON_CS5:
2066 *bits = 5;
2067 break;
2068 case S3C2410_LCON_CS6:
2069 *bits = 6;
2070 break;
2071 case S3C2410_LCON_CS7:
2072 *bits = 7;
2073 break;
b497549a 2074 case S3C2410_LCON_CS8:
3bcce591 2075 default:
b497549a
BD		 2076 *bits = 8;
2077 break;
2078 }
2079
2080 switch (ulcon & S3C2410_LCON_PMASK) {
2081 case S3C2410_LCON_PEVEN:
2082 *parity = 'e';
2083 break;
2084
2085 case S3C2410_LCON_PODD:
2086 *parity = 'o';
2087 break;
2088
2089 case S3C2410_LCON_PNONE:
2090 default:
2091 *parity = 'n';
2092 }
2093
2094 /* now calculate the baud rate */
2095
5f5a7a55
TA		 2096 clk_sel = s3c24xx_serial_getsource(port);
2097 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
b497549a 2098
5f5a7a55 2099 clk = clk_get(port->dev, clk_name);
7cd88831 2100 if (!IS_ERR(clk))
5f5a7a55 2101 rate = clk_get_rate(clk);
b497549a
BD		 2102 else
2103 rate = 1;
2104
b497549a
BD		 2105 *baud = rate / (16 * (ubrdiv + 1));
2106 dbg("calculated baud %d\n", *baud);
2107 }
2108
2109}
2110
b497549a
BD		 2111static int __init
2112s3c24xx_serial_console_setup(struct console *co, char *options)
2113{
2114 struct uart_port *port;
2115 int baud = 9600;
2116 int bits = 8;
2117 int parity = 'n';
2118 int flow = 'n';
2119
2120 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2121 co, co->index, options);
2122
2123 /* is this a valid port */
2124
03d5e77b 2125 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
b497549a
BD		 2126 co->index = 0;
2127
2128 port = &s3c24xx_serial_ports[co->index].port;
2129
2130 /* is the port configured? */
2131
ee430f16
TA		 2132 if (port->mapbase == 0x0)
2133 return -ENODEV;
b497549a
BD		 2134
2135 cons_uart = port;
2136
2137 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2138
2139 /*
2140 * Check whether an invalid uart number has been specified, and
2141 * if so, search for the first available port that does have
2142 * console support.
2143 */
2144 if (options)
2145 uart_parse_options(options, &baud, &parity, &bits, &flow);
2146 else
2147 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2148
2149 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2150
2151 return uart_set_options(port, co, baud, parity, bits, flow);
2152}
2153
b497549a
BD		 2154static struct console s3c24xx_serial_console = {
2155 .name = S3C24XX_SERIAL_NAME,
2156 .device = uart_console_device,
2157 .flags = CON_PRINTBUFFER,
2158 .index = -1,
2159 .write = s3c24xx_serial_console_write,
5822a5df
TA		 2160 .setup = s3c24xx_serial_console_setup,
2161 .data = &s3c24xx_uart_drv,
b497549a 2162};
da121506
TA		 2163#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2164
2165#ifdef CONFIG_CPU_S3C2410
2166static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2167 .info = &(struct s3c24xx_uart_info) {
2168 .name = "Samsung S3C2410 UART",
2169 .type = PORT_S3C2410,
2170 .fifosize = 16,
2171 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2172 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2173 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2174 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2175 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2176 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2177 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2178 .num_clks = 2,
2179 .clksel_mask = S3C2410_UCON_CLKMASK,
2180 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2181 },
2182 .def_cfg = &(struct s3c2410_uartcfg) {
2183 .ucon = S3C2410_UCON_DEFAULT,
2184 .ufcon = S3C2410_UFCON_DEFAULT,
2185 },
2186};
2187#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2188#else
2189#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2190#endif
b497549a 2191
da121506
TA		 2192#ifdef CONFIG_CPU_S3C2412
2193static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2194 .info = &(struct s3c24xx_uart_info) {
2195 .name = "Samsung S3C2412 UART",
2196 .type = PORT_S3C2412,
2197 .fifosize = 64,
2198 .has_divslot = 1,
2199 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2200 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2201 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2202 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2203 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2204 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2205 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2206 .num_clks = 4,
2207 .clksel_mask = S3C2412_UCON_CLKMASK,
2208 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2209 },
2210 .def_cfg = &(struct s3c2410_uartcfg) {
2211 .ucon = S3C2410_UCON_DEFAULT,
2212 .ufcon = S3C2410_UFCON_DEFAULT,
2213 },
2214};
2215#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2216#else
2217#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2218#endif
b497549a 2219
da121506 2220#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
b26469a8 2221 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
da121506
TA		 2222static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2223 .info = &(struct s3c24xx_uart_info) {
2224 .name = "Samsung S3C2440 UART",
2225 .type = PORT_S3C2440,
2226 .fifosize = 64,
2227 .has_divslot = 1,
2228 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2229 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2230 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2231 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2232 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2233 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2234 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2235 .num_clks = 4,
2236 .clksel_mask = S3C2412_UCON_CLKMASK,
2237 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2238 },
2239 .def_cfg = &(struct s3c2410_uartcfg) {
2240 .ucon = S3C2410_UCON_DEFAULT,
2241 .ufcon = S3C2410_UFCON_DEFAULT,
2242 },
2243};
2244#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2245#else
2246#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2247#endif
b497549a 2248
953b53a7 2249#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
da121506
TA		 2250static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2251 .info = &(struct s3c24xx_uart_info) {
2252 .name = "Samsung S3C6400 UART",
2253 .type = PORT_S3C6400,
2254 .fifosize = 64,
2255 .has_divslot = 1,
2256 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2257 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2258 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2259 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2260 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2261 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2262 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2263 .num_clks = 4,
2264 .clksel_mask = S3C6400_UCON_CLKMASK,
2265 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2266 },
2267 .def_cfg = &(struct s3c2410_uartcfg) {
2268 .ucon = S3C2410_UCON_DEFAULT,
2269 .ufcon = S3C2410_UFCON_DEFAULT,
2270 },
2271};
2272#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2273#else
2274#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2275#endif
b497549a 2276
da121506
TA		 2277#ifdef CONFIG_CPU_S5PV210
2278static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2279 .info = &(struct s3c24xx_uart_info) {
2280 .name = "Samsung S5PV210 UART",
2281 .type = PORT_S3C6400,
2282 .has_divslot = 1,
2283 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2284 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2285 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2286 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2287 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2288 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2289 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2290 .num_clks = 2,
2291 .clksel_mask = S5PV210_UCON_CLKMASK,
2292 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2293 },
2294 .def_cfg = &(struct s3c2410_uartcfg) {
2295 .ucon = S5PV210_UCON_DEFAULT,
2296 .ufcon = S5PV210_UFCON_DEFAULT,
2297 },
2298 .fifosize = { 256, 64, 16, 16 },
2299};
2300#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2301#else
2302#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2303#endif
b497549a 2304
33f88136 2305#if defined(CONFIG_ARCH_EXYNOS)
31ec77ac
CC		 2306#define EXYNOS_COMMON_SERIAL_DRV_DATA \
2307 .info = &(struct s3c24xx_uart_info) { \
2308 .name = "Samsung Exynos UART", \
2309 .type = PORT_S3C6400, \
2310 .has_divslot = 1, \
2311 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2312 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2313 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2314 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2315 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2316 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2317 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2318 .num_clks = 1, \
2319 .clksel_mask = 0, \
2320 .clksel_shift = 0, \
2321 }, \
2322 .def_cfg = &(struct s3c2410_uartcfg) { \
2323 .ucon = S5PV210_UCON_DEFAULT, \
2324 .ufcon = S5PV210_UFCON_DEFAULT, \
2325 .has_fracval = 1, \
2326 } \
2327
da121506 2328static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
31ec77ac 2329 EXYNOS_COMMON_SERIAL_DRV_DATA,
da121506
TA		 2330 .fifosize = { 256, 64, 16, 16 },
2331};
31ec77ac
CC		 2332
2333static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2334 EXYNOS_COMMON_SERIAL_DRV_DATA,
2335 .fifosize = { 64, 256, 16, 256 },
2336};
2337
da121506 2338#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
31ec77ac 2339#define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
da121506
TA		 2340#else
2341#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
31ec77ac 2342#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
da121506 2343#endif
b497549a 2344
da121506
TA		 2345static struct platform_device_id s3c24xx_serial_driver_ids[] = {
2346 {
2347 .name = "s3c2410-uart",
2348 .driver_data = S3C2410_SERIAL_DRV_DATA,
2349 }, {
2350 .name = "s3c2412-uart",
2351 .driver_data = S3C2412_SERIAL_DRV_DATA,
2352 }, {
2353 .name = "s3c2440-uart",
2354 .driver_data = S3C2440_SERIAL_DRV_DATA,
2355 }, {
2356 .name = "s3c6400-uart",
2357 .driver_data = S3C6400_SERIAL_DRV_DATA,
2358 }, {
2359 .name = "s5pv210-uart",
2360 .driver_data = S5PV210_SERIAL_DRV_DATA,
2361 }, {
2362 .name = "exynos4210-uart",
2363 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
31ec77ac
CC		 2364 }, {
2365 .name = "exynos5433-uart",
2366 .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
da121506
TA		 2367 },
2368 { },
2369};
2370MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2371
26c919e1
TA		 2372#ifdef CONFIG_OF
2373static const struct of_device_id s3c24xx_uart_dt_match[] = {
666ca0b9
HS		 2374 { .compatible = "samsung,s3c2410-uart",
2375 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2376 { .compatible = "samsung,s3c2412-uart",
2377 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2378 { .compatible = "samsung,s3c2440-uart",
2379 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2380 { .compatible = "samsung,s3c6400-uart",
2381 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2382 { .compatible = "samsung,s5pv210-uart",
2383 .data = (void *)S5PV210_SERIAL_DRV_DATA },
26c919e1 2384 { .compatible = "samsung,exynos4210-uart",
a169a888 2385 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
31ec77ac
CC		 2386 { .compatible = "samsung,exynos5433-uart",
2387 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
26c919e1
TA		 2388 {},
2389};
2390MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
26c919e1
TA		 2391#endif
2392
da121506
TA		 2393static struct platform_driver samsung_serial_driver = {
2394 .probe = s3c24xx_serial_probe,
2d47b716 2395 .remove = s3c24xx_serial_remove,
da121506
TA		 2396 .id_table = s3c24xx_serial_driver_ids,
2397 .driver = {
2398 .name = "samsung-uart",
da121506 2399 .pm = SERIAL_SAMSUNG_PM_OPS,
905f4ba2 2400 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
da121506
TA		 2401 },
2402};
b497549a 2403
6f134c3c 2404module_platform_driver(samsung_serial_driver);
b497549a 2405
b94ba032
TF		 2406/*
2407 * Early console.
2408 */
2409
2410struct samsung_early_console_data {
2411 u32 txfull_mask;
2412};
2413
2414static void samsung_early_busyuart(struct uart_port *port)
2415{
2416 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2417 ;
2418}
2419
2420static void samsung_early_busyuart_fifo(struct uart_port *port)
2421{
2422 struct samsung_early_console_data *data = port->private_data;
2423
2424 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2425 ;
2426}
2427
2428static void samsung_early_putc(struct uart_port *port, int c)
2429{
2430 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2431 samsung_early_busyuart_fifo(port);
2432 else
2433 samsung_early_busyuart(port);
2434
2435 writeb(c, port->membase + S3C2410_UTXH);
2436}
2437
2438static void samsung_early_write(struct console *con, const char *s, unsigned n)
2439{
2440 struct earlycon_device *dev = con->data;
2441
2442 uart_console_write(&dev->port, s, n, samsung_early_putc);
2443}
2444
2445static int __init samsung_early_console_setup(struct earlycon_device *device,
2446 const char *opt)
2447{
2448 if (!device->port.membase)
2449 return -ENODEV;
2450
2451 device->con->write = samsung_early_write;
2452 return 0;
2453}
2454
2455/* S3C2410 */
2456static struct samsung_early_console_data s3c2410_early_console_data = {
2457 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2458};
2459
2460static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2461 const char *opt)
2462{
2463 device->port.private_data = &s3c2410_early_console_data;
2464 return samsung_early_console_setup(device, opt);
2465}
2466OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2467 s3c2410_early_console_setup);
2468EARLYCON_DECLARE(s3c2410, s3c2410_early_console_setup);
2469
2470/* S3C2412, S3C2440, S3C64xx */
2471static struct samsung_early_console_data s3c2440_early_console_data = {
2472 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2473};
2474
2475static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2476 const char *opt)
2477{
2478 device->port.private_data = &s3c2440_early_console_data;
2479 return samsung_early_console_setup(device, opt);
2480}
2481OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2482 s3c2440_early_console_setup);
2483OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2484 s3c2440_early_console_setup);
2485OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2486 s3c2440_early_console_setup);
2487EARLYCON_DECLARE(s3c2412, s3c2440_early_console_setup);
2488EARLYCON_DECLARE(s3c2440, s3c2440_early_console_setup);
2489EARLYCON_DECLARE(s3c6400, s3c2440_early_console_setup);
2490
2491/* S5PV210, EXYNOS */
2492static struct samsung_early_console_data s5pv210_early_console_data = {
2493 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2494};
2495
2496static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2497 const char *opt)
2498{
2499 device->port.private_data = &s5pv210_early_console_data;
2500 return samsung_early_console_setup(device, opt);
2501}
2502OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2503 s5pv210_early_console_setup);
2504OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2505 s5pv210_early_console_setup);
2506EARLYCON_DECLARE(s5pv210, s5pv210_early_console_setup);
2507EARLYCON_DECLARE(exynos4210, s5pv210_early_console_setup);
2508
da121506 2509MODULE_ALIAS("platform:samsung-uart");
b497549a
BD		 2510MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2511MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2512MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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