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serial: 8250: include <linux/serial_reg.h> from serial_8250.h
[deliverable/linux.git] / drivers / tty / serial / sc16is7xx.c
CommitLineData
dfeae619
JR		 1/*
2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
3 * Author: Jon Ringle <jringle@gridpoint.com>
4 *
5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/gpio.h>
19#include <linux/i2c.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/regmap.h>
24#include <linux/serial_core.h>
25#include <linux/serial.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
d952795d 28#include <linux/uaccess.h>
dfeae619
JR		 29
30#define SC16IS7XX_NAME "sc16is7xx"
31
32/* SC16IS7XX register definitions */
33#define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
34#define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
35#define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
36#define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
37#define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
38#define SC16IS7XX_LCR_REG (0x03) /* Line Control */
39#define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
40#define SC16IS7XX_LSR_REG (0x05) /* Line Status */
41#define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
42#define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
43#define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
44#define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
45#define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
46 * - only on 75x/76x
47 */
48#define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
49 * - only on 75x/76x
50 */
51#define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
52 * - only on 75x/76x
53 */
54#define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
55 * - only on 75x/76x
56 */
57#define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
58
59/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
60#define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
61#define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
62
63/* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
64#define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
65#define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
66
67/* Enhanced Register set: Only if (LCR == 0xBF) */
68#define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
69#define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
70#define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
71#define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
72#define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
73
74/* IER register bits */
75#define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
76#define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
77 * interrupt */
78#define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
79 * interrupt */
80#define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
81 * interrupt */
82
83/* IER register bits - write only if (EFR[4] == 1) */
84#define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
85#define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
86#define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
87#define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
88
89/* FCR register bits */
90#define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
91#define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
92#define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
93#define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
94#define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
95
96/* FCR register bits - write only if (EFR[4] == 1) */
97#define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
98#define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
99
100/* IIR register bits */
101#define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
102#define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
103#define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
104#define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
105#define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
106#define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
107#define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
108 * - only on 75x/76x
109 */
110#define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
111 * - only on 75x/76x
112 */
113#define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
114#define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
115 * from active (LOW)
116 * to inactive (HIGH)
117 */
118/* LCR register bits */
119#define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
120#define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
121 *
122 * Word length bits table:
123 * 00 -> 5 bit words
124 * 01 -> 6 bit words
125 * 10 -> 7 bit words
126 * 11 -> 8 bit words
127 */
128#define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
129 *
130 * STOP length bit table:
131 * 0 -> 1 stop bit
132 * 1 -> 1-1.5 stop bits if
133 * word length is 5,
134 * 2 stop bits otherwise
135 */
136#define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
137#define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
138#define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
139#define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
140#define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
141#define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
142#define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
143#define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
144#define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
145#define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
146 * reg set */
147#define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
148 * reg set */
149
150/* MCR register bits */
151#define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
152 * - only on 75x/76x
153 */
154#define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
155#define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
156#define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
157#define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
158 * - write enabled
159 * if (EFR[4] == 1)
160 */
161#define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
162 * - write enabled
163 * if (EFR[4] == 1)
164 */
165#define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
166 * - write enabled
167 * if (EFR[4] == 1)
168 */
169
170/* LSR register bits */
171#define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
172#define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
173#define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
174#define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
175#define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
176#define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
177#define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
178#define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
179#define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
180
181/* MSR register bits */
182#define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
183#define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
184 * or (IO4)
185 * - only on 75x/76x
186 */
187#define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
188 * or (IO7)
189 * - only on 75x/76x
190 */
191#define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
192 * or (IO6)
193 * - only on 75x/76x
194 */
195#define SC16IS7XX_MSR_CTS_BIT (1 << 0) /* CTS */
196#define SC16IS7XX_MSR_DSR_BIT (1 << 1) /* DSR (IO4)
197 * - only on 75x/76x
198 */
199#define SC16IS7XX_MSR_RI_BIT (1 << 2) /* RI (IO7)
200 * - only on 75x/76x
201 */
202#define SC16IS7XX_MSR_CD_BIT (1 << 3) /* CD (IO6)
203 * - only on 75x/76x
204 */
205#define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
206
207/*
208 * TCR register bits
209 * TCR trigger levels are available from 0 to 60 characters with a granularity
210 * of four.
211 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
212 * no built-in hardware check to make sure this condition is met. Also, the TCR
213 * must be programmed with this condition before auto RTS or software flow
214 * control is enabled to avoid spurious operation of the device.
215 */
216#define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
217#define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
218
219/*
220 * TLR register bits
221 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
222 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
223 * trigger levels. Trigger levels from 4 characters to 60 characters are
224 * available with a granularity of four.
225 *
226 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
227 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
228 * the trigger level defined in FCR is discarded. This applies to both transmit
229 * FIFO and receive FIFO trigger level setting.
230 *
231 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
232 * default state, that is, '00'.
233 */
234#define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
235#define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
236
237/* IOControl register bits (Only 750/760) */
238#define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
239#define SC16IS7XX_IOCONTROL_GPIO_BIT (1 << 1) /* Enable GPIO[7:4] */
240#define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
241
242/* EFCR register bits */
243#define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
244 * mode (RS485) */
245#define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
246#define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
247#define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
248#define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
249#define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
250 * 0 = rate upto 115.2 kbit/s
251 * - Only 750/760
252 * 1 = rate upto 1.152 Mbit/s
253 * - Only 760
254 */
255
256/* EFR register bits */
257#define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
258#define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
259#define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
260#define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
261 * and writing to IER[7:4],
262 * FCR[5:4], MCR[7:5]
263 */
264#define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
265#define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
266 *
267 * SWFLOW bits 3 & 2 table:
268 * 00 -> no transmitter flow
269 * control
270 * 01 -> transmitter generates
271 * XON2 and XOFF2
272 * 10 -> transmitter generates
273 * XON1 and XOFF1
274 * 11 -> transmitter generates
275 * XON1, XON2, XOFF1 and
276 * XOFF2
277 */
278#define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
279#define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
280 *
281 * SWFLOW bits 3 & 2 table:
282 * 00 -> no received flow
283 * control
284 * 01 -> receiver compares
285 * XON2 and XOFF2
286 * 10 -> receiver compares
287 * XON1 and XOFF1
288 * 11 -> receiver compares
289 * XON1, XON2, XOFF1 and
290 * XOFF2
291 */
292
293/* Misc definitions */
294#define SC16IS7XX_FIFO_SIZE (64)
295#define SC16IS7XX_REG_SHIFT 2
296
297struct sc16is7xx_devtype {
298 char name[10];
299 int nr_gpio;
300 int nr_uart;
301};
302
303struct sc16is7xx_one {
304 struct uart_port port;
305 struct work_struct tx_work;
306 struct work_struct md_work;
dfeae619
JR		 307};
308
309struct sc16is7xx_port {
310 struct uart_driver uart;
311 struct sc16is7xx_devtype *devtype;
312 struct regmap *regmap;
313 struct mutex mutex;
314 struct clk *clk;
315#ifdef CONFIG_GPIOLIB
316 struct gpio_chip gpio;
317#endif
beb04a9f 318 unsigned char buf[SC16IS7XX_FIFO_SIZE];
dfeae619
JR		 319 struct sc16is7xx_one p[0];
320};
321
322#define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
323
324static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
325{
326 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
327 unsigned int val = 0;
328
329 regmap_read(s->regmap,
330 (reg << SC16IS7XX_REG_SHIFT) | port->line, &val);
331
332 return val;
333}
334
335static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
336{
337 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
338
339 regmap_write(s->regmap,
340 (reg << SC16IS7XX_REG_SHIFT) | port->line, val);
341}
342
343static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
344 u8 mask, u8 val)
345{
346 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
347
348 regmap_update_bits(s->regmap,
349 (reg << SC16IS7XX_REG_SHIFT) | port->line,
350 mask, val);
351}
352
353
354static void sc16is7xx_power(struct uart_port *port, int on)
355{
356 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
357 SC16IS7XX_IER_SLEEP_BIT,
358 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
359}
360
361static const struct sc16is7xx_devtype sc16is74x_devtype = {
362 .name = "SC16IS74X",
363 .nr_gpio = 0,
364 .nr_uart = 1,
365};
366
367static const struct sc16is7xx_devtype sc16is750_devtype = {
368 .name = "SC16IS750",
369 .nr_gpio = 8,
370 .nr_uart = 1,
371};
372
373static const struct sc16is7xx_devtype sc16is752_devtype = {
374 .name = "SC16IS752",
375 .nr_gpio = 8,
376 .nr_uart = 2,
377};
378
379static const struct sc16is7xx_devtype sc16is760_devtype = {
380 .name = "SC16IS760",
381 .nr_gpio = 8,
382 .nr_uart = 1,
383};
384
385static const struct sc16is7xx_devtype sc16is762_devtype = {
386 .name = "SC16IS762",
387 .nr_gpio = 8,
388 .nr_uart = 2,
389};
390
391static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
392{
393 switch (reg >> SC16IS7XX_REG_SHIFT) {
394 case SC16IS7XX_RHR_REG:
395 case SC16IS7XX_IIR_REG:
396 case SC16IS7XX_LSR_REG:
397 case SC16IS7XX_MSR_REG:
398 case SC16IS7XX_TXLVL_REG:
399 case SC16IS7XX_RXLVL_REG:
400 case SC16IS7XX_IOSTATE_REG:
401 return true;
402 default:
403 break;
404 }
405
406 return false;
407}
408
409static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
410{
411 switch (reg >> SC16IS7XX_REG_SHIFT) {
412 case SC16IS7XX_RHR_REG:
413 return true;
414 default:
415 break;
416 }
417
418 return false;
419}
420
421static int sc16is7xx_set_baud(struct uart_port *port, int baud)
422{
423 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
424 u8 lcr;
425 u8 prescaler = 0;
426 unsigned long clk = port->uartclk, div = clk / 16 / baud;
427
428 if (div > 0xffff) {
429 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
430 div /= 4;
431 }
432
433 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
434
435 /* Open the LCR divisors for configuration */
436 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
437 SC16IS7XX_LCR_CONF_MODE_B);
438
439 /* Enable enhanced features */
440 regcache_cache_bypass(s->regmap, true);
441 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
442 SC16IS7XX_EFR_ENABLE_BIT);
443 regcache_cache_bypass(s->regmap, false);
444
445 /* Put LCR back to the normal mode */
446 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
447
448 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
449 SC16IS7XX_MCR_CLKSEL_BIT,
450 prescaler);
451
452 /* Open the LCR divisors for configuration */
453 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
454 SC16IS7XX_LCR_CONF_MODE_A);
455
456 /* Write the new divisor */
457 regcache_cache_bypass(s->regmap, true);
458 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
459 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
460 regcache_cache_bypass(s->regmap, false);
461
462 /* Put LCR back to the normal mode */
463 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
464
465 return DIV_ROUND_CLOSEST(clk / 16, div);
466}
467
468static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
469 unsigned int iir)
470{
471 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
472 unsigned int lsr = 0, ch, flag, bytes_read, i;
dfeae619
JR		 473 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
474
beb04a9f 475 if (unlikely(rxlen >= sizeof(s->buf))) {
dfeae619
JR		 476 dev_warn_ratelimited(port->dev,
477 "Port %i: Possible RX FIFO overrun: %d\n",
478 port->line, rxlen);
479 port->icount.buf_overrun++;
480 /* Ensure sanity of RX level */
beb04a9f 481 rxlen = sizeof(s->buf);
dfeae619
JR		 482 }
483
484 while (rxlen) {
485 /* Only read lsr if there are possible errors in FIFO */
486 if (read_lsr) {
487 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
488 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
489 read_lsr = false; /* No errors left in FIFO */
490 } else
491 lsr = 0;
492
493 if (read_lsr) {
beb04a9f 494 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
dfeae619
JR		 495 bytes_read = 1;
496 } else {
497 regcache_cache_bypass(s->regmap, true);
498 regmap_raw_read(s->regmap, SC16IS7XX_RHR_REG,
beb04a9f 499 s->buf, rxlen);
dfeae619
JR		 500 regcache_cache_bypass(s->regmap, false);
501 bytes_read = rxlen;
502 }
503
504 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
505
506 port->icount.rx++;
507 flag = TTY_NORMAL;
508
509 if (unlikely(lsr)) {
510 if (lsr & SC16IS7XX_LSR_BI_BIT) {
511 port->icount.brk++;
512 if (uart_handle_break(port))
513 continue;
514 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
515 port->icount.parity++;
516 else if (lsr & SC16IS7XX_LSR_FE_BIT)
517 port->icount.frame++;
518 else if (lsr & SC16IS7XX_LSR_OE_BIT)
519 port->icount.overrun++;
520
521 lsr &= port->read_status_mask;
522 if (lsr & SC16IS7XX_LSR_BI_BIT)
523 flag = TTY_BREAK;
524 else if (lsr & SC16IS7XX_LSR_PE_BIT)
525 flag = TTY_PARITY;
526 else if (lsr & SC16IS7XX_LSR_FE_BIT)
527 flag = TTY_FRAME;
528 else if (lsr & SC16IS7XX_LSR_OE_BIT)
529 flag = TTY_OVERRUN;
530 }
531
532 for (i = 0; i < bytes_read; ++i) {
beb04a9f 533 ch = s->buf[i];
dfeae619
JR		 534 if (uart_handle_sysrq_char(port, ch))
535 continue;
536
537 if (lsr & port->ignore_status_mask)
538 continue;
539
540 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
541 flag);
542 }
543 rxlen -= bytes_read;
544 }
545
546 tty_flip_buffer_push(&port->state->port);
547}
548
549static void sc16is7xx_handle_tx(struct uart_port *port)
550{
551 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
552 struct circ_buf *xmit = &port->state->xmit;
553 unsigned int txlen, to_send, i;
dfeae619
JR		 554
555 if (unlikely(port->x_char)) {
556 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
557 port->icount.tx++;
558 port->x_char = 0;
559 return;
560 }
561
562 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
563 return;
564
565 /* Get length of data pending in circular buffer */
566 to_send = uart_circ_chars_pending(xmit);
567 if (likely(to_send)) {
568 /* Limit to size of TX FIFO */
569 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
570 to_send = (to_send > txlen) ? txlen : to_send;
571
572 /* Add data to send */
573 port->icount.tx += to_send;
574
575 /* Convert to linear buffer */
576 for (i = 0; i < to_send; ++i) {
beb04a9f 577 s->buf[i] = xmit->buf[xmit->tail];
dfeae619
JR		 578 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
579 }
580 regcache_cache_bypass(s->regmap, true);
beb04a9f 581 regmap_raw_write(s->regmap, SC16IS7XX_THR_REG, s->buf, to_send);
dfeae619
JR		 582 regcache_cache_bypass(s->regmap, false);
583 }
584
585 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
586 uart_write_wakeup(port);
587}
588
589static void sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
590{
591 struct uart_port *port = &s->p[portno].port;
592
593 do {
594 unsigned int iir, msr, rxlen;
595
596 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
597 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
598 break;
599
600 iir &= SC16IS7XX_IIR_ID_MASK;
601
602 switch (iir) {
603 case SC16IS7XX_IIR_RDI_SRC:
604 case SC16IS7XX_IIR_RLSE_SRC:
605 case SC16IS7XX_IIR_RTOI_SRC:
606 case SC16IS7XX_IIR_XOFFI_SRC:
607 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
608 if (rxlen)
609 sc16is7xx_handle_rx(port, rxlen, iir);
610 break;
611
612 case SC16IS7XX_IIR_CTSRTS_SRC:
613 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
614 uart_handle_cts_change(port,
615 !!(msr & SC16IS7XX_MSR_CTS_BIT));
616 break;
617 case SC16IS7XX_IIR_THRI_SRC:
618 mutex_lock(&s->mutex);
619 sc16is7xx_handle_tx(port);
620 mutex_unlock(&s->mutex);
621 break;
622 default:
623 dev_err_ratelimited(port->dev,
624 "Port %i: Unexpected interrupt: %x",
625 port->line, iir);
626 break;
627 }
628 } while (1);
629}
630
631static irqreturn_t sc16is7xx_ist(int irq, void *dev_id)
632{
633 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
634 int i;
635
636 for (i = 0; i < s->uart.nr; ++i)
637 sc16is7xx_port_irq(s, i);
638
639 return IRQ_HANDLED;
640}
641
642static void sc16is7xx_wq_proc(struct work_struct *ws)
643{
644 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, tx_work);
645 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev);
646
647 mutex_lock(&s->mutex);
648 sc16is7xx_handle_tx(&one->port);
649 mutex_unlock(&s->mutex);
650}
651
652static void sc16is7xx_stop_tx(struct uart_port* port)
653{
654 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
655 struct circ_buf *xmit = &one->port.state->xmit;
656
657 /* handle rs485 */
b57d15fe 658 if (port->rs485.flags & SER_RS485_ENABLED) {
dfeae619
JR		 659 /* do nothing if current tx not yet completed */
660 int lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
661 if (!(lsr & SC16IS7XX_LSR_TEMT_BIT))
662 return;
663
664 if (uart_circ_empty(xmit) &&
b57d15fe
RRD		 665 (port->rs485.delay_rts_after_send > 0))
666 mdelay(port->rs485.delay_rts_after_send);
dfeae619
JR		 667 }
668
669 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
670 SC16IS7XX_IER_THRI_BIT,
671 0);
672}
673
674static void sc16is7xx_stop_rx(struct uart_port* port)
675{
676 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
677
678 one->port.read_status_mask &= ~SC16IS7XX_LSR_DR_BIT;
679 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
680 SC16IS7XX_LSR_DR_BIT,
681 0);
682}
683
684static void sc16is7xx_start_tx(struct uart_port *port)
685{
686 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
687
688 /* handle rs485 */
b57d15fe
RRD		 689 if ((port->rs485.flags & SER_RS485_ENABLED) &&
690 (port->rs485.delay_rts_before_send > 0)) {
691 mdelay(port->rs485.delay_rts_before_send);
dfeae619
JR		 692 }
693
694 if (!work_pending(&one->tx_work))
695 schedule_work(&one->tx_work);
696}
697
698static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
699{
700 unsigned int lvl, lsr;
701
702 lvl = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
703 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
704
705 return ((lsr & SC16IS7XX_LSR_THRE_BIT) && !lvl) ? TIOCSER_TEMT : 0;
706}
707
708static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
709{
710 /* DCD and DSR are not wired and CTS/RTS is handled automatically
711 * so just indicate DSR and CAR asserted
712 */
713 return TIOCM_DSR | TIOCM_CAR;
714}
715
716static void sc16is7xx_md_proc(struct work_struct *ws)
717{
718 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, md_work);
719
720 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
721 SC16IS7XX_MCR_LOOP_BIT,
722 (one->port.mctrl & TIOCM_LOOP) ?
723 SC16IS7XX_MCR_LOOP_BIT : 0);
724}
725
726static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
727{
728 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
729
730 schedule_work(&one->md_work);
731}
732
733static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
734{
735 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
736 SC16IS7XX_LCR_TXBREAK_BIT,
737 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
738}
739
740static void sc16is7xx_set_termios(struct uart_port *port,
741 struct ktermios *termios,
742 struct ktermios *old)
743{
744 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
745 unsigned int lcr, flow = 0;
746 int baud;
747
748 /* Mask termios capabilities we don't support */
749 termios->c_cflag &= ~CMSPAR;
750
751 /* Word size */
752 switch (termios->c_cflag & CSIZE) {
753 case CS5:
754 lcr = SC16IS7XX_LCR_WORD_LEN_5;
755 break;
756 case CS6:
757 lcr = SC16IS7XX_LCR_WORD_LEN_6;
758 break;
759 case CS7:
760 lcr = SC16IS7XX_LCR_WORD_LEN_7;
761 break;
762 case CS8:
763 lcr = SC16IS7XX_LCR_WORD_LEN_8;
764 break;
765 default:
766 lcr = SC16IS7XX_LCR_WORD_LEN_8;
767 termios->c_cflag &= ~CSIZE;
768 termios->c_cflag |= CS8;
769 break;
770 }
771
772 /* Parity */
773 if (termios->c_cflag & PARENB) {
774 lcr |= SC16IS7XX_LCR_PARITY_BIT;
775 if (!(termios->c_cflag & PARODD))
776 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
777 }
778
779 /* Stop bits */
780 if (termios->c_cflag & CSTOPB)
781 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
782
783 /* Set read status mask */
784 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
785 if (termios->c_iflag & INPCK)
786 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
787 SC16IS7XX_LSR_FE_BIT;
788 if (termios->c_iflag & (BRKINT | PARMRK))
789 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
790
791 /* Set status ignore mask */
792 port->ignore_status_mask = 0;
793 if (termios->c_iflag & IGNBRK)
794 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
795 if (!(termios->c_cflag & CREAD))
796 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
797
798 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
799 SC16IS7XX_LCR_CONF_MODE_B);
800
801 /* Configure flow control */
802 regcache_cache_bypass(s->regmap, true);
803 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
804 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
805 if (termios->c_cflag & CRTSCTS)
806 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
807 SC16IS7XX_EFR_AUTORTS_BIT;
808 if (termios->c_iflag & IXON)
809 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
810 if (termios->c_iflag & IXOFF)
811 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
812
813 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
814 regcache_cache_bypass(s->regmap, false);
815
816 /* Update LCR register */
817 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
818
819 /* Get baud rate generator configuration */
820 baud = uart_get_baud_rate(port, termios, old,
821 port->uartclk / 16 / 4 / 0xffff,
822 port->uartclk / 16);
823
824 /* Setup baudrate generator */
825 baud = sc16is7xx_set_baud(port, baud);
826
827 /* Update timeout according to new baud rate */
828 uart_update_timeout(port, termios->c_cflag, baud);
829}
830
b57d15fe 831static int sc16is7xx_config_rs485(struct uart_port *port,
f0e38115 832 struct serial_rs485 *rs485)
dfeae619 833{
f0e38115
JK		 834 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
835 SC16IS7XX_EFCR_RTS_INVERT_BIT;
836 u32 efcr = 0;
837
838 if (rs485->flags & SER_RS485_ENABLED) {
839 bool rts_during_rx, rts_during_tx;
840
841 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
842 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
843
844 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
845
846 if (!rts_during_rx && rts_during_tx)
847 /* default */;
848 else if (rts_during_rx && !rts_during_tx)
849 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
850 else
851 dev_err(port->dev,
852 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
853 rts_during_tx, rts_during_rx);
854 }
855
856 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
857
b57d15fe 858 port->rs485 = *rs485;
dfeae619 859
b57d15fe 860 return 0;
dfeae619
JR		 861}
862
863static int sc16is7xx_startup(struct uart_port *port)
864{
865 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
866 unsigned int val;
867
868 sc16is7xx_power(port, 1);
869
870 /* Reset FIFOs*/
871 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
872 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
873 udelay(5);
874 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
875 SC16IS7XX_FCR_FIFO_BIT);
876
877 /* Enable EFR */
878 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
879 SC16IS7XX_LCR_CONF_MODE_B);
880
881 regcache_cache_bypass(s->regmap, true);
882
883 /* Enable write access to enhanced features and internal clock div */
884 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
885 SC16IS7XX_EFR_ENABLE_BIT);
886
887 /* Enable TCR/TLR */
888 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
889 SC16IS7XX_MCR_TCRTLR_BIT,
890 SC16IS7XX_MCR_TCRTLR_BIT);
891
892 /* Configure flow control levels */
893 /* Flow control halt level 48, resume level 24 */
894 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
895 SC16IS7XX_TCR_RX_RESUME(24) |
896 SC16IS7XX_TCR_RX_HALT(48));
897
898 regcache_cache_bypass(s->regmap, false);
899
900 /* Now, initialize the UART */
901 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
902
903 /* Enable the Rx and Tx FIFO */
904 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
905 SC16IS7XX_EFCR_RXDISABLE_BIT |
906 SC16IS7XX_EFCR_TXDISABLE_BIT,
907 0);
908
909 /* Enable RX, TX, CTS change interrupts */
910 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT |
911 SC16IS7XX_IER_CTSI_BIT;
912 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
913
914 return 0;
915}
916
917static void sc16is7xx_shutdown(struct uart_port *port)
918{
919 /* Disable all interrupts */
920 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
921 /* Disable TX/RX */
9764e7a0
JK		 922 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
923 SC16IS7XX_EFCR_RXDISABLE_BIT |
924 SC16IS7XX_EFCR_TXDISABLE_BIT,
925 SC16IS7XX_EFCR_RXDISABLE_BIT |
926 SC16IS7XX_EFCR_TXDISABLE_BIT);
dfeae619
JR		 927
928 sc16is7xx_power(port, 0);
929}
930
931static const char *sc16is7xx_type(struct uart_port *port)
932{
933 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
934
935 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
936}
937
938static int sc16is7xx_request_port(struct uart_port *port)
939{
940 /* Do nothing */
941 return 0;
942}
943
944static void sc16is7xx_config_port(struct uart_port *port, int flags)
945{
946 if (flags & UART_CONFIG_TYPE)
947 port->type = PORT_SC16IS7XX;
948}
949
950static int sc16is7xx_verify_port(struct uart_port *port,
951 struct serial_struct *s)
952{
953 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
954 return -EINVAL;
955 if (s->irq != port->irq)
956 return -EINVAL;
957
958 return 0;
959}
960
961static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
962 unsigned int oldstate)
963{
964 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
965}
966
967static void sc16is7xx_null_void(struct uart_port *port)
968{
969 /* Do nothing */
970}
971
972static const struct uart_ops sc16is7xx_ops = {
973 .tx_empty = sc16is7xx_tx_empty,
974 .set_mctrl = sc16is7xx_set_mctrl,
975 .get_mctrl = sc16is7xx_get_mctrl,
976 .stop_tx = sc16is7xx_stop_tx,
977 .start_tx = sc16is7xx_start_tx,
978 .stop_rx = sc16is7xx_stop_rx,
dfeae619
JR		 979 .break_ctl = sc16is7xx_break_ctl,
980 .startup = sc16is7xx_startup,
981 .shutdown = sc16is7xx_shutdown,
982 .set_termios = sc16is7xx_set_termios,
983 .type = sc16is7xx_type,
984 .request_port = sc16is7xx_request_port,
985 .release_port = sc16is7xx_null_void,
986 .config_port = sc16is7xx_config_port,
987 .verify_port = sc16is7xx_verify_port,
dfeae619
JR		 988 .pm = sc16is7xx_pm,
989};
990
991#ifdef CONFIG_GPIOLIB
992static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
993{
994 unsigned int val;
995 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
996 gpio);
997 struct uart_port *port = &s->p[0].port;
998
999 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1000
1001 return !!(val & BIT(offset));
1002}
1003
1004static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1005{
1006 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1007 gpio);
1008 struct uart_port *port = &s->p[0].port;
1009
1010 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1011 val ? BIT(offset) : 0);
1012}
1013
1014static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1015 unsigned offset)
1016{
1017 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1018 gpio);
1019 struct uart_port *port = &s->p[0].port;
1020
1021 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1022
1023 return 0;
1024}
1025
1026static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1027 unsigned offset, int val)
1028{
1029 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1030 gpio);
1031 struct uart_port *port = &s->p[0].port;
1032
1033 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1034 val ? BIT(offset) : 0);
1035 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1036 BIT(offset));
1037
1038 return 0;
1039}
1040#endif
1041
1042static int sc16is7xx_probe(struct device *dev,
1043 struct sc16is7xx_devtype *devtype,
1044 struct regmap *regmap, int irq, unsigned long flags)
1045{
1046 unsigned long freq, *pfreq = dev_get_platdata(dev);
dfeae619
JR		 1047 int i, ret;
1048 struct sc16is7xx_port *s;
1049
1050 if (IS_ERR(regmap))
1051 return PTR_ERR(regmap);
1052
1053 /* Alloc port structure */
1054 s = devm_kzalloc(dev, sizeof(*s) +
1055 sizeof(struct sc16is7xx_one) * devtype->nr_uart,
1056 GFP_KERNEL);
1057 if (!s) {
1058 dev_err(dev, "Error allocating port structure\n");
1059 return -ENOMEM;
1060 }
1061
dc824ebe
JR		 1062 s->clk = devm_clk_get(dev, NULL);
1063 if (IS_ERR(s->clk)) {
dfeae619
JR		 1064 if (pfreq)
1065 freq = *pfreq;
1066 else
dc824ebe 1067 return PTR_ERR(s->clk);
dfeae619 1068 } else {
0814e8d5 1069 clk_prepare_enable(s->clk);
dc824ebe 1070 freq = clk_get_rate(s->clk);
dfeae619
JR		 1071 }
1072
1073 s->regmap = regmap;
1074 s->devtype = devtype;
1075 dev_set_drvdata(dev, s);
1076
1077 /* Register UART driver */
1078 s->uart.owner = THIS_MODULE;
1079 s->uart.dev_name = "ttySC";
1080 s->uart.nr = devtype->nr_uart;
1081 ret = uart_register_driver(&s->uart);
1082 if (ret) {
1083 dev_err(dev, "Registering UART driver failed\n");
1084 goto out_clk;
1085 }
1086
1087#ifdef CONFIG_GPIOLIB
1088 if (devtype->nr_gpio) {
1089 /* Setup GPIO cotroller */
1090 s->gpio.owner = THIS_MODULE;
1091 s->gpio.dev = dev;
1092 s->gpio.label = dev_name(dev);
1093 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1094 s->gpio.get = sc16is7xx_gpio_get;
1095 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1096 s->gpio.set = sc16is7xx_gpio_set;
1097 s->gpio.base = -1;
1098 s->gpio.ngpio = devtype->nr_gpio;
1099 s->gpio.can_sleep = 1;
1100 ret = gpiochip_add(&s->gpio);
1101 if (ret)
1102 goto out_uart;
1103 }
1104#endif
1105
1106 mutex_init(&s->mutex);
1107
1108 for (i = 0; i < devtype->nr_uart; ++i) {
1109 /* Initialize port data */
1110 s->p[i].port.line = i;
1111 s->p[i].port.dev = dev;
1112 s->p[i].port.irq = irq;
1113 s->p[i].port.type = PORT_SC16IS7XX;
1114 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1115 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1116 s->p[i].port.iotype = UPIO_PORT;
1117 s->p[i].port.uartclk = freq;
b57d15fe 1118 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
dfeae619
JR		 1119 s->p[i].port.ops = &sc16is7xx_ops;
1120 /* Disable all interrupts */
1121 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1122 /* Disable TX/RX */
1123 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1124 SC16IS7XX_EFCR_RXDISABLE_BIT |
1125 SC16IS7XX_EFCR_TXDISABLE_BIT);
1126 /* Initialize queue for start TX */
1127 INIT_WORK(&s->p[i].tx_work, sc16is7xx_wq_proc);
1128 /* Initialize queue for changing mode */
1129 INIT_WORK(&s->p[i].md_work, sc16is7xx_md_proc);
1130 /* Register port */
1131 uart_add_one_port(&s->uart, &s->p[i].port);
1132 /* Go to suspend mode */
1133 sc16is7xx_power(&s->p[i].port, 0);
1134 }
1135
1136 /* Setup interrupt */
1137 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_ist,
1138 IRQF_ONESHOT | flags, dev_name(dev), s);
1139 if (!ret)
1140 return 0;
1141
11b03ea0
JK		 1142 for (i = 0; i < s->uart.nr; i++)
1143 uart_remove_one_port(&s->uart, &s->p[i].port);
1144
dfeae619
JR		 1145 mutex_destroy(&s->mutex);
1146
1147#ifdef CONFIG_GPIOLIB
1148 if (devtype->nr_gpio)
e27e2786 1149 gpiochip_remove(&s->gpio);
dfeae619
JR		 1150
1151out_uart:
1152#endif
1153 uart_unregister_driver(&s->uart);
1154
1155out_clk:
1156 if (!IS_ERR(s->clk))
1157 clk_disable_unprepare(s->clk);
1158
1159 return ret;
1160}
1161
1162static int sc16is7xx_remove(struct device *dev)
1163{
1164 struct sc16is7xx_port *s = dev_get_drvdata(dev);
e27e2786 1165 int i;
dfeae619
JR		 1166
1167#ifdef CONFIG_GPIOLIB
e27e2786
LW		 1168 if (s->devtype->nr_gpio)
1169 gpiochip_remove(&s->gpio);
dfeae619
JR		 1170#endif
1171
1172 for (i = 0; i < s->uart.nr; i++) {
1173 cancel_work_sync(&s->p[i].tx_work);
1174 cancel_work_sync(&s->p[i].md_work);
1175 uart_remove_one_port(&s->uart, &s->p[i].port);
1176 sc16is7xx_power(&s->p[i].port, 0);
1177 }
1178
1179 mutex_destroy(&s->mutex);
1180 uart_unregister_driver(&s->uart);
1181 if (!IS_ERR(s->clk))
1182 clk_disable_unprepare(s->clk);
1183
e27e2786 1184 return 0;
dfeae619
JR		 1185}
1186
1187static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1188 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1189 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1190 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1191 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1192 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1193 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1194 { }
1195};
1196MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1197
1198static struct regmap_config regcfg = {
1199 .reg_bits = 7,
1200 .pad_bits = 1,
1201 .val_bits = 8,
1202 .cache_type = REGCACHE_RBTREE,
1203 .volatile_reg = sc16is7xx_regmap_volatile,
1204 .precious_reg = sc16is7xx_regmap_precious,
1205};
1206
dfeae619
JR		 1207static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1208 const struct i2c_device_id *id)
1209{
1210 struct sc16is7xx_devtype *devtype;
1211 unsigned long flags = 0;
1212 struct regmap *regmap;
1213
1214 if (i2c->dev.of_node) {
1215 const struct of_device_id *of_id =
1216 of_match_device(sc16is7xx_dt_ids, &i2c->dev);
1217
1218 devtype = (struct sc16is7xx_devtype *)of_id->data;
1219 } else {
1220 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1221 flags = IRQF_TRIGGER_FALLING;
1222 }
1223
1224 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1225 (devtype->nr_uart - 1);
1226 regmap = devm_regmap_init_i2c(i2c, &regcfg);
1227
1228 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags);
1229}
1230
1231static int sc16is7xx_i2c_remove(struct i2c_client *client)
1232{
1233 return sc16is7xx_remove(&client->dev);
1234}
1235
1236static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1237 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1238 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1239 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1240 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1241 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1242 { }
1243};
1244MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1245
1246static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1247 .driver = {
1248 .name = SC16IS7XX_NAME,
1249 .owner = THIS_MODULE,
1250 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1251 },
1252 .probe = sc16is7xx_i2c_probe,
1253 .remove = sc16is7xx_i2c_remove,
1254 .id_table = sc16is7xx_i2c_id_table,
1255};
1256module_i2c_driver(sc16is7xx_i2c_uart_driver);
1257MODULE_ALIAS("i2c:sc16is7xx");
dfeae619
JR		 1258
1259MODULE_LICENSE("GPL");
1260MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1261MODULE_DESCRIPTION("SC16IS7XX serial driver");
Linux kernel - Deliverables
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