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sc16is7xx: add missing compatible strings
[deliverable/linux.git] / drivers / tty / serial / sc16is7xx.c
CommitLineData
dfeae619
JR		 1/*
2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
3 * Author: Jon Ringle <jringle@gridpoint.com>
4 *
5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/gpio.h>
19#include <linux/i2c.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/regmap.h>
24#include <linux/serial_core.h>
25#include <linux/serial.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
2c837a8a 28#include <linux/spi/spi.h>
d952795d 29#include <linux/uaccess.h>
dfeae619
JR		 30
31#define SC16IS7XX_NAME "sc16is7xx"
32
33/* SC16IS7XX register definitions */
34#define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
35#define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
36#define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
37#define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
38#define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
39#define SC16IS7XX_LCR_REG (0x03) /* Line Control */
40#define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
41#define SC16IS7XX_LSR_REG (0x05) /* Line Status */
42#define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
43#define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
44#define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
45#define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
46#define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
47 * - only on 75x/76x
48 */
49#define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
50 * - only on 75x/76x
51 */
52#define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
53 * - only on 75x/76x
54 */
55#define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
56 * - only on 75x/76x
57 */
58#define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
59
60/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
61#define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
62#define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
63
64/* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
65#define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
66#define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
67
68/* Enhanced Register set: Only if (LCR == 0xBF) */
69#define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
70#define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
71#define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
72#define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
73#define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
74
75/* IER register bits */
76#define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
77#define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
78 * interrupt */
79#define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
80 * interrupt */
81#define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
82 * interrupt */
83
84/* IER register bits - write only if (EFR[4] == 1) */
85#define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
86#define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
87#define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
88#define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
89
90/* FCR register bits */
91#define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
92#define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
93#define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
94#define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
95#define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
96
97/* FCR register bits - write only if (EFR[4] == 1) */
98#define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
99#define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
100
101/* IIR register bits */
102#define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
103#define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
104#define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
105#define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
106#define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
107#define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
108#define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
109 * - only on 75x/76x
110 */
111#define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
112 * - only on 75x/76x
113 */
114#define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
115#define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
116 * from active (LOW)
117 * to inactive (HIGH)
118 */
119/* LCR register bits */
120#define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
121#define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
122 *
123 * Word length bits table:
124 * 00 -> 5 bit words
125 * 01 -> 6 bit words
126 * 10 -> 7 bit words
127 * 11 -> 8 bit words
128 */
129#define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
130 *
131 * STOP length bit table:
132 * 0 -> 1 stop bit
133 * 1 -> 1-1.5 stop bits if
134 * word length is 5,
135 * 2 stop bits otherwise
136 */
137#define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
138#define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
139#define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
140#define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
141#define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
142#define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
143#define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
144#define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
145#define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
146#define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
147 * reg set */
148#define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
149 * reg set */
150
151/* MCR register bits */
152#define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
153 * - only on 75x/76x
154 */
155#define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
156#define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
157#define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
158#define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
159 * - write enabled
160 * if (EFR[4] == 1)
161 */
162#define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
163 * - write enabled
164 * if (EFR[4] == 1)
165 */
166#define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
167 * - write enabled
168 * if (EFR[4] == 1)
169 */
170
171/* LSR register bits */
172#define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
173#define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
174#define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
175#define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
176#define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
177#define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
178#define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
179#define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
180#define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
181
182/* MSR register bits */
183#define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
184#define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
185 * or (IO4)
186 * - only on 75x/76x
187 */
188#define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
189 * or (IO7)
190 * - only on 75x/76x
191 */
192#define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
193 * or (IO6)
194 * - only on 75x/76x
195 */
196#define SC16IS7XX_MSR_CTS_BIT (1 << 0) /* CTS */
197#define SC16IS7XX_MSR_DSR_BIT (1 << 1) /* DSR (IO4)
198 * - only on 75x/76x
199 */
200#define SC16IS7XX_MSR_RI_BIT (1 << 2) /* RI (IO7)
201 * - only on 75x/76x
202 */
203#define SC16IS7XX_MSR_CD_BIT (1 << 3) /* CD (IO6)
204 * - only on 75x/76x
205 */
206#define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
207
208/*
209 * TCR register bits
210 * TCR trigger levels are available from 0 to 60 characters with a granularity
211 * of four.
212 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
213 * no built-in hardware check to make sure this condition is met. Also, the TCR
214 * must be programmed with this condition before auto RTS or software flow
215 * control is enabled to avoid spurious operation of the device.
216 */
217#define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
218#define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
219
220/*
221 * TLR register bits
222 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
223 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
224 * trigger levels. Trigger levels from 4 characters to 60 characters are
225 * available with a granularity of four.
226 *
227 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
228 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
229 * the trigger level defined in FCR is discarded. This applies to both transmit
230 * FIFO and receive FIFO trigger level setting.
231 *
232 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
233 * default state, that is, '00'.
234 */
235#define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
236#define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
237
238/* IOControl register bits (Only 750/760) */
239#define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
240#define SC16IS7XX_IOCONTROL_GPIO_BIT (1 << 1) /* Enable GPIO[7:4] */
241#define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
242
243/* EFCR register bits */
244#define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
245 * mode (RS485) */
246#define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
247#define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
248#define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
249#define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
250#define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
251 * 0 = rate upto 115.2 kbit/s
252 * - Only 750/760
253 * 1 = rate upto 1.152 Mbit/s
254 * - Only 760
255 */
256
257/* EFR register bits */
258#define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
259#define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
260#define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
261#define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
262 * and writing to IER[7:4],
263 * FCR[5:4], MCR[7:5]
264 */
265#define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
266#define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
267 *
268 * SWFLOW bits 3 & 2 table:
269 * 00 -> no transmitter flow
270 * control
271 * 01 -> transmitter generates
272 * XON2 and XOFF2
273 * 10 -> transmitter generates
274 * XON1 and XOFF1
275 * 11 -> transmitter generates
276 * XON1, XON2, XOFF1 and
277 * XOFF2
278 */
279#define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
280#define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
281 *
282 * SWFLOW bits 3 & 2 table:
283 * 00 -> no received flow
284 * control
285 * 01 -> receiver compares
286 * XON2 and XOFF2
287 * 10 -> receiver compares
288 * XON1 and XOFF1
289 * 11 -> receiver compares
290 * XON1, XON2, XOFF1 and
291 * XOFF2
292 */
293
294/* Misc definitions */
295#define SC16IS7XX_FIFO_SIZE (64)
296#define SC16IS7XX_REG_SHIFT 2
297
298struct sc16is7xx_devtype {
299 char name[10];
300 int nr_gpio;
301 int nr_uart;
302};
303
304struct sc16is7xx_one {
305 struct uart_port port;
306 struct work_struct tx_work;
307 struct work_struct md_work;
dfeae619
JR		 308};
309
310struct sc16is7xx_port {
311 struct uart_driver uart;
312 struct sc16is7xx_devtype *devtype;
313 struct regmap *regmap;
314 struct mutex mutex;
315 struct clk *clk;
316#ifdef CONFIG_GPIOLIB
317 struct gpio_chip gpio;
318#endif
beb04a9f 319 unsigned char buf[SC16IS7XX_FIFO_SIZE];
dfeae619
JR		 320 struct sc16is7xx_one p[0];
321};
322
323#define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
324
325static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
326{
327 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
328 unsigned int val = 0;
329
330 regmap_read(s->regmap,
331 (reg << SC16IS7XX_REG_SHIFT) | port->line, &val);
332
333 return val;
334}
335
336static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
337{
338 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
339
340 regmap_write(s->regmap,
341 (reg << SC16IS7XX_REG_SHIFT) | port->line, val);
342}
343
344static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
345 u8 mask, u8 val)
346{
347 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
348
349 regmap_update_bits(s->regmap,
350 (reg << SC16IS7XX_REG_SHIFT) | port->line,
351 mask, val);
352}
353
354
355static void sc16is7xx_power(struct uart_port *port, int on)
356{
357 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
358 SC16IS7XX_IER_SLEEP_BIT,
359 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
360}
361
362static const struct sc16is7xx_devtype sc16is74x_devtype = {
363 .name = "SC16IS74X",
364 .nr_gpio = 0,
365 .nr_uart = 1,
366};
367
368static const struct sc16is7xx_devtype sc16is750_devtype = {
369 .name = "SC16IS750",
370 .nr_gpio = 8,
371 .nr_uart = 1,
372};
373
374static const struct sc16is7xx_devtype sc16is752_devtype = {
375 .name = "SC16IS752",
376 .nr_gpio = 8,
377 .nr_uart = 2,
378};
379
380static const struct sc16is7xx_devtype sc16is760_devtype = {
381 .name = "SC16IS760",
382 .nr_gpio = 8,
383 .nr_uart = 1,
384};
385
386static const struct sc16is7xx_devtype sc16is762_devtype = {
387 .name = "SC16IS762",
388 .nr_gpio = 8,
389 .nr_uart = 2,
390};
391
392static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
393{
394 switch (reg >> SC16IS7XX_REG_SHIFT) {
395 case SC16IS7XX_RHR_REG:
396 case SC16IS7XX_IIR_REG:
397 case SC16IS7XX_LSR_REG:
398 case SC16IS7XX_MSR_REG:
399 case SC16IS7XX_TXLVL_REG:
400 case SC16IS7XX_RXLVL_REG:
401 case SC16IS7XX_IOSTATE_REG:
402 return true;
403 default:
404 break;
405 }
406
407 return false;
408}
409
410static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
411{
412 switch (reg >> SC16IS7XX_REG_SHIFT) {
413 case SC16IS7XX_RHR_REG:
414 return true;
415 default:
416 break;
417 }
418
419 return false;
420}
421
422static int sc16is7xx_set_baud(struct uart_port *port, int baud)
423{
424 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
425 u8 lcr;
426 u8 prescaler = 0;
427 unsigned long clk = port->uartclk, div = clk / 16 / baud;
428
429 if (div > 0xffff) {
430 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
431 div /= 4;
432 }
433
434 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
435
436 /* Open the LCR divisors for configuration */
437 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
438 SC16IS7XX_LCR_CONF_MODE_B);
439
440 /* Enable enhanced features */
441 regcache_cache_bypass(s->regmap, true);
442 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
443 SC16IS7XX_EFR_ENABLE_BIT);
444 regcache_cache_bypass(s->regmap, false);
445
446 /* Put LCR back to the normal mode */
447 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
448
449 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
450 SC16IS7XX_MCR_CLKSEL_BIT,
451 prescaler);
452
453 /* Open the LCR divisors for configuration */
454 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
455 SC16IS7XX_LCR_CONF_MODE_A);
456
457 /* Write the new divisor */
458 regcache_cache_bypass(s->regmap, true);
459 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
460 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
461 regcache_cache_bypass(s->regmap, false);
462
463 /* Put LCR back to the normal mode */
464 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
465
466 return DIV_ROUND_CLOSEST(clk / 16, div);
467}
468
469static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
470 unsigned int iir)
471{
472 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
473 unsigned int lsr = 0, ch, flag, bytes_read, i;
dfeae619
JR		 474 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
475
beb04a9f 476 if (unlikely(rxlen >= sizeof(s->buf))) {
dfeae619
JR		 477 dev_warn_ratelimited(port->dev,
478 "Port %i: Possible RX FIFO overrun: %d\n",
479 port->line, rxlen);
480 port->icount.buf_overrun++;
481 /* Ensure sanity of RX level */
beb04a9f 482 rxlen = sizeof(s->buf);
dfeae619
JR		 483 }
484
485 while (rxlen) {
486 /* Only read lsr if there are possible errors in FIFO */
487 if (read_lsr) {
488 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
489 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
490 read_lsr = false; /* No errors left in FIFO */
491 } else
492 lsr = 0;
493
494 if (read_lsr) {
beb04a9f 495 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
dfeae619
JR		 496 bytes_read = 1;
497 } else {
498 regcache_cache_bypass(s->regmap, true);
499 regmap_raw_read(s->regmap, SC16IS7XX_RHR_REG,
beb04a9f 500 s->buf, rxlen);
dfeae619
JR		 501 regcache_cache_bypass(s->regmap, false);
502 bytes_read = rxlen;
503 }
504
505 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
506
507 port->icount.rx++;
508 flag = TTY_NORMAL;
509
510 if (unlikely(lsr)) {
511 if (lsr & SC16IS7XX_LSR_BI_BIT) {
512 port->icount.brk++;
513 if (uart_handle_break(port))
514 continue;
515 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
516 port->icount.parity++;
517 else if (lsr & SC16IS7XX_LSR_FE_BIT)
518 port->icount.frame++;
519 else if (lsr & SC16IS7XX_LSR_OE_BIT)
520 port->icount.overrun++;
521
522 lsr &= port->read_status_mask;
523 if (lsr & SC16IS7XX_LSR_BI_BIT)
524 flag = TTY_BREAK;
525 else if (lsr & SC16IS7XX_LSR_PE_BIT)
526 flag = TTY_PARITY;
527 else if (lsr & SC16IS7XX_LSR_FE_BIT)
528 flag = TTY_FRAME;
529 else if (lsr & SC16IS7XX_LSR_OE_BIT)
530 flag = TTY_OVERRUN;
531 }
532
533 for (i = 0; i < bytes_read; ++i) {
beb04a9f 534 ch = s->buf[i];
dfeae619
JR		 535 if (uart_handle_sysrq_char(port, ch))
536 continue;
537
538 if (lsr & port->ignore_status_mask)
539 continue;
540
541 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
542 flag);
543 }
544 rxlen -= bytes_read;
545 }
546
547 tty_flip_buffer_push(&port->state->port);
548}
549
550static void sc16is7xx_handle_tx(struct uart_port *port)
551{
552 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
553 struct circ_buf *xmit = &port->state->xmit;
554 unsigned int txlen, to_send, i;
dfeae619
JR		 555
556 if (unlikely(port->x_char)) {
557 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
558 port->icount.tx++;
559 port->x_char = 0;
560 return;
561 }
562
563 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
564 return;
565
566 /* Get length of data pending in circular buffer */
567 to_send = uart_circ_chars_pending(xmit);
568 if (likely(to_send)) {
569 /* Limit to size of TX FIFO */
570 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
571 to_send = (to_send > txlen) ? txlen : to_send;
572
573 /* Add data to send */
574 port->icount.tx += to_send;
575
576 /* Convert to linear buffer */
577 for (i = 0; i < to_send; ++i) {
beb04a9f 578 s->buf[i] = xmit->buf[xmit->tail];
dfeae619
JR		 579 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
580 }
581 regcache_cache_bypass(s->regmap, true);
beb04a9f 582 regmap_raw_write(s->regmap, SC16IS7XX_THR_REG, s->buf, to_send);
dfeae619
JR		 583 regcache_cache_bypass(s->regmap, false);
584 }
585
586 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
587 uart_write_wakeup(port);
588}
589
590static void sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
591{
592 struct uart_port *port = &s->p[portno].port;
593
594 do {
595 unsigned int iir, msr, rxlen;
596
597 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
598 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
599 break;
600
601 iir &= SC16IS7XX_IIR_ID_MASK;
602
603 switch (iir) {
604 case SC16IS7XX_IIR_RDI_SRC:
605 case SC16IS7XX_IIR_RLSE_SRC:
606 case SC16IS7XX_IIR_RTOI_SRC:
607 case SC16IS7XX_IIR_XOFFI_SRC:
608 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
609 if (rxlen)
610 sc16is7xx_handle_rx(port, rxlen, iir);
611 break;
612
613 case SC16IS7XX_IIR_CTSRTS_SRC:
614 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
615 uart_handle_cts_change(port,
616 !!(msr & SC16IS7XX_MSR_CTS_BIT));
617 break;
618 case SC16IS7XX_IIR_THRI_SRC:
619 mutex_lock(&s->mutex);
620 sc16is7xx_handle_tx(port);
621 mutex_unlock(&s->mutex);
622 break;
623 default:
624 dev_err_ratelimited(port->dev,
625 "Port %i: Unexpected interrupt: %x",
626 port->line, iir);
627 break;
628 }
629 } while (1);
630}
631
632static irqreturn_t sc16is7xx_ist(int irq, void *dev_id)
633{
634 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
635 int i;
636
637 for (i = 0; i < s->uart.nr; ++i)
638 sc16is7xx_port_irq(s, i);
639
640 return IRQ_HANDLED;
641}
642
643static void sc16is7xx_wq_proc(struct work_struct *ws)
644{
645 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, tx_work);
646 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev);
647
648 mutex_lock(&s->mutex);
649 sc16is7xx_handle_tx(&one->port);
650 mutex_unlock(&s->mutex);
651}
652
653static void sc16is7xx_stop_tx(struct uart_port* port)
654{
dfeae619
JR		 655 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
656 SC16IS7XX_IER_THRI_BIT,
657 0);
658}
659
660static void sc16is7xx_stop_rx(struct uart_port* port)
661{
662 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
663
664 one->port.read_status_mask &= ~SC16IS7XX_LSR_DR_BIT;
665 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
666 SC16IS7XX_LSR_DR_BIT,
667 0);
668}
669
670static void sc16is7xx_start_tx(struct uart_port *port)
671{
672 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
673
674 /* handle rs485 */
b57d15fe
RRD		 675 if ((port->rs485.flags & SER_RS485_ENABLED) &&
676 (port->rs485.delay_rts_before_send > 0)) {
677 mdelay(port->rs485.delay_rts_before_send);
dfeae619
JR		 678 }
679
680 if (!work_pending(&one->tx_work))
681 schedule_work(&one->tx_work);
682}
683
684static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
685{
686 unsigned int lvl, lsr;
687
688 lvl = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
689 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
690
691 return ((lsr & SC16IS7XX_LSR_THRE_BIT) && !lvl) ? TIOCSER_TEMT : 0;
692}
693
694static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
695{
696 /* DCD and DSR are not wired and CTS/RTS is handled automatically
697 * so just indicate DSR and CAR asserted
698 */
699 return TIOCM_DSR | TIOCM_CAR;
700}
701
702static void sc16is7xx_md_proc(struct work_struct *ws)
703{
704 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, md_work);
705
706 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
707 SC16IS7XX_MCR_LOOP_BIT,
708 (one->port.mctrl & TIOCM_LOOP) ?
709 SC16IS7XX_MCR_LOOP_BIT : 0);
710}
711
712static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
713{
714 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
715
716 schedule_work(&one->md_work);
717}
718
719static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
720{
721 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
722 SC16IS7XX_LCR_TXBREAK_BIT,
723 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
724}
725
726static void sc16is7xx_set_termios(struct uart_port *port,
727 struct ktermios *termios,
728 struct ktermios *old)
729{
730 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
731 unsigned int lcr, flow = 0;
732 int baud;
733
734 /* Mask termios capabilities we don't support */
735 termios->c_cflag &= ~CMSPAR;
736
737 /* Word size */
738 switch (termios->c_cflag & CSIZE) {
739 case CS5:
740 lcr = SC16IS7XX_LCR_WORD_LEN_5;
741 break;
742 case CS6:
743 lcr = SC16IS7XX_LCR_WORD_LEN_6;
744 break;
745 case CS7:
746 lcr = SC16IS7XX_LCR_WORD_LEN_7;
747 break;
748 case CS8:
749 lcr = SC16IS7XX_LCR_WORD_LEN_8;
750 break;
751 default:
752 lcr = SC16IS7XX_LCR_WORD_LEN_8;
753 termios->c_cflag &= ~CSIZE;
754 termios->c_cflag |= CS8;
755 break;
756 }
757
758 /* Parity */
759 if (termios->c_cflag & PARENB) {
760 lcr |= SC16IS7XX_LCR_PARITY_BIT;
761 if (!(termios->c_cflag & PARODD))
762 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
763 }
764
765 /* Stop bits */
766 if (termios->c_cflag & CSTOPB)
767 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
768
769 /* Set read status mask */
770 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
771 if (termios->c_iflag & INPCK)
772 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
773 SC16IS7XX_LSR_FE_BIT;
774 if (termios->c_iflag & (BRKINT | PARMRK))
775 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
776
777 /* Set status ignore mask */
778 port->ignore_status_mask = 0;
779 if (termios->c_iflag & IGNBRK)
780 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
781 if (!(termios->c_cflag & CREAD))
782 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
783
784 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
785 SC16IS7XX_LCR_CONF_MODE_B);
786
787 /* Configure flow control */
788 regcache_cache_bypass(s->regmap, true);
789 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
790 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
791 if (termios->c_cflag & CRTSCTS)
792 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
793 SC16IS7XX_EFR_AUTORTS_BIT;
794 if (termios->c_iflag & IXON)
795 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
796 if (termios->c_iflag & IXOFF)
797 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
798
799 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
800 regcache_cache_bypass(s->regmap, false);
801
802 /* Update LCR register */
803 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
804
805 /* Get baud rate generator configuration */
806 baud = uart_get_baud_rate(port, termios, old,
807 port->uartclk / 16 / 4 / 0xffff,
808 port->uartclk / 16);
809
810 /* Setup baudrate generator */
811 baud = sc16is7xx_set_baud(port, baud);
812
813 /* Update timeout according to new baud rate */
814 uart_update_timeout(port, termios->c_cflag, baud);
815}
816
b57d15fe 817static int sc16is7xx_config_rs485(struct uart_port *port,
f0e38115 818 struct serial_rs485 *rs485)
dfeae619 819{
f0e38115
JK		 820 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
821 SC16IS7XX_EFCR_RTS_INVERT_BIT;
822 u32 efcr = 0;
823
824 if (rs485->flags & SER_RS485_ENABLED) {
825 bool rts_during_rx, rts_during_tx;
826
827 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
828 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
829
830 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
831
832 if (!rts_during_rx && rts_during_tx)
833 /* default */;
834 else if (rts_during_rx && !rts_during_tx)
835 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
836 else
837 dev_err(port->dev,
838 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
839 rts_during_tx, rts_during_rx);
5451bb29
JK		 840
841 /*
842 * RTS signal is handled by HW, it's timing can't be influenced.
843 * However, it's sometimes useful to delay TX even without RTS
844 * control therefore we try to handle .delay_rts_before_send.
845 */
846 if (rs485->delay_rts_after_send)
847 return -EINVAL;
f0e38115
JK		 848 }
849
850 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
851
b57d15fe 852 port->rs485 = *rs485;
dfeae619 853
b57d15fe 854 return 0;
dfeae619
JR		 855}
856
857static int sc16is7xx_startup(struct uart_port *port)
858{
859 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
860 unsigned int val;
861
862 sc16is7xx_power(port, 1);
863
864 /* Reset FIFOs*/
865 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
866 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
867 udelay(5);
868 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
869 SC16IS7XX_FCR_FIFO_BIT);
870
871 /* Enable EFR */
872 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
873 SC16IS7XX_LCR_CONF_MODE_B);
874
875 regcache_cache_bypass(s->regmap, true);
876
877 /* Enable write access to enhanced features and internal clock div */
878 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
879 SC16IS7XX_EFR_ENABLE_BIT);
880
881 /* Enable TCR/TLR */
882 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
883 SC16IS7XX_MCR_TCRTLR_BIT,
884 SC16IS7XX_MCR_TCRTLR_BIT);
885
886 /* Configure flow control levels */
887 /* Flow control halt level 48, resume level 24 */
888 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
889 SC16IS7XX_TCR_RX_RESUME(24) |
890 SC16IS7XX_TCR_RX_HALT(48));
891
892 regcache_cache_bypass(s->regmap, false);
893
894 /* Now, initialize the UART */
895 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
896
897 /* Enable the Rx and Tx FIFO */
898 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
899 SC16IS7XX_EFCR_RXDISABLE_BIT |
900 SC16IS7XX_EFCR_TXDISABLE_BIT,
901 0);
902
903 /* Enable RX, TX, CTS change interrupts */
904 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT |
905 SC16IS7XX_IER_CTSI_BIT;
906 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
907
908 return 0;
909}
910
911static void sc16is7xx_shutdown(struct uart_port *port)
912{
913 /* Disable all interrupts */
914 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
915 /* Disable TX/RX */
9764e7a0
JK		 916 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
917 SC16IS7XX_EFCR_RXDISABLE_BIT |
918 SC16IS7XX_EFCR_TXDISABLE_BIT,
919 SC16IS7XX_EFCR_RXDISABLE_BIT |
920 SC16IS7XX_EFCR_TXDISABLE_BIT);
dfeae619
JR		 921
922 sc16is7xx_power(port, 0);
923}
924
925static const char *sc16is7xx_type(struct uart_port *port)
926{
927 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
928
929 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
930}
931
932static int sc16is7xx_request_port(struct uart_port *port)
933{
934 /* Do nothing */
935 return 0;
936}
937
938static void sc16is7xx_config_port(struct uart_port *port, int flags)
939{
940 if (flags & UART_CONFIG_TYPE)
941 port->type = PORT_SC16IS7XX;
942}
943
944static int sc16is7xx_verify_port(struct uart_port *port,
945 struct serial_struct *s)
946{
947 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
948 return -EINVAL;
949 if (s->irq != port->irq)
950 return -EINVAL;
951
952 return 0;
953}
954
955static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
956 unsigned int oldstate)
957{
958 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
959}
960
961static void sc16is7xx_null_void(struct uart_port *port)
962{
963 /* Do nothing */
964}
965
966static const struct uart_ops sc16is7xx_ops = {
967 .tx_empty = sc16is7xx_tx_empty,
968 .set_mctrl = sc16is7xx_set_mctrl,
969 .get_mctrl = sc16is7xx_get_mctrl,
970 .stop_tx = sc16is7xx_stop_tx,
971 .start_tx = sc16is7xx_start_tx,
972 .stop_rx = sc16is7xx_stop_rx,
dfeae619
JR		 973 .break_ctl = sc16is7xx_break_ctl,
974 .startup = sc16is7xx_startup,
975 .shutdown = sc16is7xx_shutdown,
976 .set_termios = sc16is7xx_set_termios,
977 .type = sc16is7xx_type,
978 .request_port = sc16is7xx_request_port,
979 .release_port = sc16is7xx_null_void,
980 .config_port = sc16is7xx_config_port,
981 .verify_port = sc16is7xx_verify_port,
dfeae619
JR		 982 .pm = sc16is7xx_pm,
983};
984
985#ifdef CONFIG_GPIOLIB
986static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
987{
988 unsigned int val;
989 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
990 gpio);
991 struct uart_port *port = &s->p[0].port;
992
993 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
994
995 return !!(val & BIT(offset));
996}
997
998static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
999{
1000 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1001 gpio);
1002 struct uart_port *port = &s->p[0].port;
1003
1004 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1005 val ? BIT(offset) : 0);
1006}
1007
1008static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1009 unsigned offset)
1010{
1011 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1012 gpio);
1013 struct uart_port *port = &s->p[0].port;
1014
1015 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1016
1017 return 0;
1018}
1019
1020static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1021 unsigned offset, int val)
1022{
1023 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1024 gpio);
1025 struct uart_port *port = &s->p[0].port;
1026
1027 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1028 val ? BIT(offset) : 0);
1029 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1030 BIT(offset));
1031
1032 return 0;
1033}
1034#endif
1035
1036static int sc16is7xx_probe(struct device *dev,
1037 struct sc16is7xx_devtype *devtype,
1038 struct regmap *regmap, int irq, unsigned long flags)
1039{
1040 unsigned long freq, *pfreq = dev_get_platdata(dev);
dfeae619
JR		 1041 int i, ret;
1042 struct sc16is7xx_port *s;
1043
1044 if (IS_ERR(regmap))
1045 return PTR_ERR(regmap);
1046
1047 /* Alloc port structure */
1048 s = devm_kzalloc(dev, sizeof(*s) +
1049 sizeof(struct sc16is7xx_one) * devtype->nr_uart,
1050 GFP_KERNEL);
1051 if (!s) {
1052 dev_err(dev, "Error allocating port structure\n");
1053 return -ENOMEM;
1054 }
1055
dc824ebe
JR		 1056 s->clk = devm_clk_get(dev, NULL);
1057 if (IS_ERR(s->clk)) {
dfeae619
JR		 1058 if (pfreq)
1059 freq = *pfreq;
1060 else
dc824ebe 1061 return PTR_ERR(s->clk);
dfeae619 1062 } else {
0814e8d5 1063 clk_prepare_enable(s->clk);
dc824ebe 1064 freq = clk_get_rate(s->clk);
dfeae619
JR		 1065 }
1066
1067 s->regmap = regmap;
1068 s->devtype = devtype;
1069 dev_set_drvdata(dev, s);
1070
1071 /* Register UART driver */
1072 s->uart.owner = THIS_MODULE;
1073 s->uart.dev_name = "ttySC";
1074 s->uart.nr = devtype->nr_uart;
1075 ret = uart_register_driver(&s->uart);
1076 if (ret) {
1077 dev_err(dev, "Registering UART driver failed\n");
1078 goto out_clk;
1079 }
1080
1081#ifdef CONFIG_GPIOLIB
1082 if (devtype->nr_gpio) {
1083 /* Setup GPIO cotroller */
1084 s->gpio.owner = THIS_MODULE;
1085 s->gpio.dev = dev;
1086 s->gpio.label = dev_name(dev);
1087 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1088 s->gpio.get = sc16is7xx_gpio_get;
1089 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1090 s->gpio.set = sc16is7xx_gpio_set;
1091 s->gpio.base = -1;
1092 s->gpio.ngpio = devtype->nr_gpio;
1093 s->gpio.can_sleep = 1;
1094 ret = gpiochip_add(&s->gpio);
1095 if (ret)
1096 goto out_uart;
1097 }
1098#endif
1099
1100 mutex_init(&s->mutex);
1101
1102 for (i = 0; i < devtype->nr_uart; ++i) {
1103 /* Initialize port data */
1104 s->p[i].port.line = i;
1105 s->p[i].port.dev = dev;
1106 s->p[i].port.irq = irq;
1107 s->p[i].port.type = PORT_SC16IS7XX;
1108 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1109 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1110 s->p[i].port.iotype = UPIO_PORT;
1111 s->p[i].port.uartclk = freq;
b57d15fe 1112 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
dfeae619
JR		 1113 s->p[i].port.ops = &sc16is7xx_ops;
1114 /* Disable all interrupts */
1115 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1116 /* Disable TX/RX */
1117 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1118 SC16IS7XX_EFCR_RXDISABLE_BIT |
1119 SC16IS7XX_EFCR_TXDISABLE_BIT);
1120 /* Initialize queue for start TX */
1121 INIT_WORK(&s->p[i].tx_work, sc16is7xx_wq_proc);
1122 /* Initialize queue for changing mode */
1123 INIT_WORK(&s->p[i].md_work, sc16is7xx_md_proc);
1124 /* Register port */
1125 uart_add_one_port(&s->uart, &s->p[i].port);
1126 /* Go to suspend mode */
1127 sc16is7xx_power(&s->p[i].port, 0);
1128 }
1129
1130 /* Setup interrupt */
1131 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_ist,
1132 IRQF_ONESHOT | flags, dev_name(dev), s);
1133 if (!ret)
1134 return 0;
1135
11b03ea0
JK		 1136 for (i = 0; i < s->uart.nr; i++)
1137 uart_remove_one_port(&s->uart, &s->p[i].port);
1138
dfeae619
JR		 1139 mutex_destroy(&s->mutex);
1140
1141#ifdef CONFIG_GPIOLIB
1142 if (devtype->nr_gpio)
e27e2786 1143 gpiochip_remove(&s->gpio);
dfeae619
JR		 1144
1145out_uart:
1146#endif
1147 uart_unregister_driver(&s->uart);
1148
1149out_clk:
1150 if (!IS_ERR(s->clk))
1151 clk_disable_unprepare(s->clk);
1152
1153 return ret;
1154}
1155
1156static int sc16is7xx_remove(struct device *dev)
1157{
1158 struct sc16is7xx_port *s = dev_get_drvdata(dev);
e27e2786 1159 int i;
dfeae619
JR		 1160
1161#ifdef CONFIG_GPIOLIB
e27e2786
LW		 1162 if (s->devtype->nr_gpio)
1163 gpiochip_remove(&s->gpio);
dfeae619
JR		 1164#endif
1165
1166 for (i = 0; i < s->uart.nr; i++) {
1167 cancel_work_sync(&s->p[i].tx_work);
1168 cancel_work_sync(&s->p[i].md_work);
1169 uart_remove_one_port(&s->uart, &s->p[i].port);
1170 sc16is7xx_power(&s->p[i].port, 0);
1171 }
1172
1173 mutex_destroy(&s->mutex);
1174 uart_unregister_driver(&s->uart);
1175 if (!IS_ERR(s->clk))
1176 clk_disable_unprepare(s->clk);
1177
e27e2786 1178 return 0;
dfeae619
JR		 1179}
1180
1181static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1182 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1183 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1184 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1185 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1186 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1187 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1188 { }
1189};
1190MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1191
1192static struct regmap_config regcfg = {
1193 .reg_bits = 7,
1194 .pad_bits = 1,
1195 .val_bits = 8,
1196 .cache_type = REGCACHE_RBTREE,
1197 .volatile_reg = sc16is7xx_regmap_volatile,
1198 .precious_reg = sc16is7xx_regmap_precious,
1199};
1200
2c837a8a
RKKI		 1201#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1202static int sc16is7xx_spi_probe(struct spi_device *spi)
1203{
1204 struct sc16is7xx_devtype *devtype;
1205 unsigned long flags = 0;
1206 struct regmap *regmap;
1207 int ret;
1208
1209 /* Setup SPI bus */
1210 spi->bits_per_word = 8;
1211 /* only supports mode 0 on SC16IS762 */
1212 spi->mode = spi->mode ? : SPI_MODE_0;
1213 spi->max_speed_hz = spi->max_speed_hz ? : 15000000;
1214 ret = spi_setup(spi);
1215 if (ret)
1216 return ret;
1217
1218 if (spi->dev.of_node) {
1219 const struct of_device_id *of_id =
1220 of_match_device(sc16is7xx_dt_ids, &spi->dev);
1221
1222 devtype = (struct sc16is7xx_devtype *)of_id->data;
1223 } else {
1224 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1225
1226 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1227 flags = IRQF_TRIGGER_FALLING;
1228 }
1229
1230 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1231 (devtype->nr_uart - 1);
1232 regmap = devm_regmap_init_spi(spi, &regcfg);
1233
1234 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq, flags);
1235}
1236
1237static int sc16is7xx_spi_remove(struct spi_device *spi)
1238{
1239 return sc16is7xx_remove(&spi->dev);
1240}
1241
1242static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1243 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
4117a60c
JK		 1244 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1245 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
2c837a8a
RKKI		 1246 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1247 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1248 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1249 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1250 { }
1251};
1252
1253MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1254
1255static struct spi_driver sc16is7xx_spi_uart_driver = {
1256 .driver = {
1257 .name = SC16IS7XX_NAME,
1258 .owner = THIS_MODULE,
1259 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1260 },
1261 .probe = sc16is7xx_spi_probe,
1262 .remove = sc16is7xx_spi_remove,
1263 .id_table = sc16is7xx_spi_id_table,
1264};
1265
1266MODULE_ALIAS("spi:sc16is7xx");
1267#endif
1268
1269#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
dfeae619
JR		 1270static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1271 const struct i2c_device_id *id)
1272{
1273 struct sc16is7xx_devtype *devtype;
1274 unsigned long flags = 0;
1275 struct regmap *regmap;
1276
1277 if (i2c->dev.of_node) {
1278 const struct of_device_id *of_id =
1279 of_match_device(sc16is7xx_dt_ids, &i2c->dev);
1280
1281 devtype = (struct sc16is7xx_devtype *)of_id->data;
1282 } else {
1283 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1284 flags = IRQF_TRIGGER_FALLING;
1285 }
1286
1287 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1288 (devtype->nr_uart - 1);
1289 regmap = devm_regmap_init_i2c(i2c, &regcfg);
1290
1291 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags);
1292}
1293
1294static int sc16is7xx_i2c_remove(struct i2c_client *client)
1295{
1296 return sc16is7xx_remove(&client->dev);
1297}
1298
1299static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1300 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
4117a60c
JK		 1301 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1302 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
dfeae619
JR		 1303 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1304 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1305 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1306 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1307 { }
1308};
1309MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1310
1311static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1312 .driver = {
1313 .name = SC16IS7XX_NAME,
1314 .owner = THIS_MODULE,
1315 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1316 },
1317 .probe = sc16is7xx_i2c_probe,
1318 .remove = sc16is7xx_i2c_remove,
1319 .id_table = sc16is7xx_i2c_id_table,
1320};
2c837a8a 1321
dfeae619 1322MODULE_ALIAS("i2c:sc16is7xx");
2c837a8a
RKKI		 1323#endif
1324
1325static int __init sc16is7xx_init(void)
1326{
1327 int ret = 0;
1328#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1329 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1330 if (ret < 0) {
1331 pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1332 return ret;
1333 }
1334#endif
1335
1336#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1337 ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1338 if (ret < 0) {
1339 pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1340 return ret;
1341 }
1342#endif
1343 return ret;
1344}
1345module_init(sc16is7xx_init);
1346
1347static void __exit sc16is7xx_exit(void)
1348{
1349#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1350 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1351#endif
1352
1353#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1354 spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1355#endif
1356}
1357module_exit(sc16is7xx_exit);
dfeae619
JR		 1358
1359MODULE_LICENSE("GPL");
1360MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1361MODULE_DESCRIPTION("SC16IS7XX serial driver");
Linux kernel - Deliverables
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