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serial: sc16is7xx: depend on I2C
[deliverable/linux.git] / drivers / tty / serial / sc16is7xx.c
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dfeae619
JR		 1/*
2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
3 * Author: Jon Ringle <jringle@gridpoint.com>
4 *
5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/gpio.h>
19#include <linux/i2c.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/regmap.h>
24#include <linux/serial_core.h>
25#include <linux/serial.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
28
29#define SC16IS7XX_NAME "sc16is7xx"
30
31/* SC16IS7XX register definitions */
32#define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
33#define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
34#define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
35#define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
36#define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
37#define SC16IS7XX_LCR_REG (0x03) /* Line Control */
38#define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
39#define SC16IS7XX_LSR_REG (0x05) /* Line Status */
40#define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
41#define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
42#define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
43#define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
44#define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
45 * - only on 75x/76x
46 */
47#define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
48 * - only on 75x/76x
49 */
50#define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
51 * - only on 75x/76x
52 */
53#define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
54 * - only on 75x/76x
55 */
56#define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
57
58/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
59#define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
60#define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
61
62/* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
63#define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
64#define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
65
66/* Enhanced Register set: Only if (LCR == 0xBF) */
67#define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
68#define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
69#define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
70#define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
71#define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
72
73/* IER register bits */
74#define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
75#define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
76 * interrupt */
77#define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
78 * interrupt */
79#define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
80 * interrupt */
81
82/* IER register bits - write only if (EFR[4] == 1) */
83#define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
84#define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
85#define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
86#define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
87
88/* FCR register bits */
89#define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
90#define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
91#define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
92#define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
93#define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
94
95/* FCR register bits - write only if (EFR[4] == 1) */
96#define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
97#define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
98
99/* IIR register bits */
100#define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
101#define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
102#define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
103#define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
104#define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
105#define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
106#define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
107 * - only on 75x/76x
108 */
109#define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
110 * - only on 75x/76x
111 */
112#define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
113#define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
114 * from active (LOW)
115 * to inactive (HIGH)
116 */
117/* LCR register bits */
118#define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
119#define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
120 *
121 * Word length bits table:
122 * 00 -> 5 bit words
123 * 01 -> 6 bit words
124 * 10 -> 7 bit words
125 * 11 -> 8 bit words
126 */
127#define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
128 *
129 * STOP length bit table:
130 * 0 -> 1 stop bit
131 * 1 -> 1-1.5 stop bits if
132 * word length is 5,
133 * 2 stop bits otherwise
134 */
135#define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
136#define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
137#define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
138#define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
139#define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
140#define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
141#define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
142#define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
143#define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
144#define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
145 * reg set */
146#define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
147 * reg set */
148
149/* MCR register bits */
150#define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
151 * - only on 75x/76x
152 */
153#define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
154#define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
155#define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
156#define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
157 * - write enabled
158 * if (EFR[4] == 1)
159 */
160#define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
161 * - write enabled
162 * if (EFR[4] == 1)
163 */
164#define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
165 * - write enabled
166 * if (EFR[4] == 1)
167 */
168
169/* LSR register bits */
170#define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
171#define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
172#define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
173#define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
174#define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
175#define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
176#define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
177#define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
178#define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
179
180/* MSR register bits */
181#define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
182#define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
183 * or (IO4)
184 * - only on 75x/76x
185 */
186#define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
187 * or (IO7)
188 * - only on 75x/76x
189 */
190#define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
191 * or (IO6)
192 * - only on 75x/76x
193 */
194#define SC16IS7XX_MSR_CTS_BIT (1 << 0) /* CTS */
195#define SC16IS7XX_MSR_DSR_BIT (1 << 1) /* DSR (IO4)
196 * - only on 75x/76x
197 */
198#define SC16IS7XX_MSR_RI_BIT (1 << 2) /* RI (IO7)
199 * - only on 75x/76x
200 */
201#define SC16IS7XX_MSR_CD_BIT (1 << 3) /* CD (IO6)
202 * - only on 75x/76x
203 */
204#define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
205
206/*
207 * TCR register bits
208 * TCR trigger levels are available from 0 to 60 characters with a granularity
209 * of four.
210 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
211 * no built-in hardware check to make sure this condition is met. Also, the TCR
212 * must be programmed with this condition before auto RTS or software flow
213 * control is enabled to avoid spurious operation of the device.
214 */
215#define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
216#define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
217
218/*
219 * TLR register bits
220 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
221 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
222 * trigger levels. Trigger levels from 4 characters to 60 characters are
223 * available with a granularity of four.
224 *
225 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
226 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
227 * the trigger level defined in FCR is discarded. This applies to both transmit
228 * FIFO and receive FIFO trigger level setting.
229 *
230 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
231 * default state, that is, '00'.
232 */
233#define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
234#define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
235
236/* IOControl register bits (Only 750/760) */
237#define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
238#define SC16IS7XX_IOCONTROL_GPIO_BIT (1 << 1) /* Enable GPIO[7:4] */
239#define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
240
241/* EFCR register bits */
242#define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
243 * mode (RS485) */
244#define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
245#define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
246#define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
247#define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
248#define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
249 * 0 = rate upto 115.2 kbit/s
250 * - Only 750/760
251 * 1 = rate upto 1.152 Mbit/s
252 * - Only 760
253 */
254
255/* EFR register bits */
256#define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
257#define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
258#define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
259#define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
260 * and writing to IER[7:4],
261 * FCR[5:4], MCR[7:5]
262 */
263#define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
264#define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
265 *
266 * SWFLOW bits 3 & 2 table:
267 * 00 -> no transmitter flow
268 * control
269 * 01 -> transmitter generates
270 * XON2 and XOFF2
271 * 10 -> transmitter generates
272 * XON1 and XOFF1
273 * 11 -> transmitter generates
274 * XON1, XON2, XOFF1 and
275 * XOFF2
276 */
277#define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
278#define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
279 *
280 * SWFLOW bits 3 & 2 table:
281 * 00 -> no received flow
282 * control
283 * 01 -> receiver compares
284 * XON2 and XOFF2
285 * 10 -> receiver compares
286 * XON1 and XOFF1
287 * 11 -> receiver compares
288 * XON1, XON2, XOFF1 and
289 * XOFF2
290 */
291
292/* Misc definitions */
293#define SC16IS7XX_FIFO_SIZE (64)
294#define SC16IS7XX_REG_SHIFT 2
295
296struct sc16is7xx_devtype {
297 char name[10];
298 int nr_gpio;
299 int nr_uart;
300};
301
302struct sc16is7xx_one {
303 struct uart_port port;
304 struct work_struct tx_work;
305 struct work_struct md_work;
306
307 struct serial_rs485 rs485;
308};
309
310struct sc16is7xx_port {
311 struct uart_driver uart;
312 struct sc16is7xx_devtype *devtype;
313 struct regmap *regmap;
314 struct mutex mutex;
315 struct clk *clk;
316#ifdef CONFIG_GPIOLIB
317 struct gpio_chip gpio;
318#endif
319 struct sc16is7xx_one p[0];
320};
321
322#define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
323
324static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
325{
326 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
327 unsigned int val = 0;
328
329 regmap_read(s->regmap,
330 (reg << SC16IS7XX_REG_SHIFT) | port->line, &val);
331
332 return val;
333}
334
335static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
336{
337 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
338
339 regmap_write(s->regmap,
340 (reg << SC16IS7XX_REG_SHIFT) | port->line, val);
341}
342
343static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
344 u8 mask, u8 val)
345{
346 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
347
348 regmap_update_bits(s->regmap,
349 (reg << SC16IS7XX_REG_SHIFT) | port->line,
350 mask, val);
351}
352
353
354static void sc16is7xx_power(struct uart_port *port, int on)
355{
356 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
357 SC16IS7XX_IER_SLEEP_BIT,
358 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
359}
360
361static const struct sc16is7xx_devtype sc16is74x_devtype = {
362 .name = "SC16IS74X",
363 .nr_gpio = 0,
364 .nr_uart = 1,
365};
366
367static const struct sc16is7xx_devtype sc16is750_devtype = {
368 .name = "SC16IS750",
369 .nr_gpio = 8,
370 .nr_uart = 1,
371};
372
373static const struct sc16is7xx_devtype sc16is752_devtype = {
374 .name = "SC16IS752",
375 .nr_gpio = 8,
376 .nr_uart = 2,
377};
378
379static const struct sc16is7xx_devtype sc16is760_devtype = {
380 .name = "SC16IS760",
381 .nr_gpio = 8,
382 .nr_uart = 1,
383};
384
385static const struct sc16is7xx_devtype sc16is762_devtype = {
386 .name = "SC16IS762",
387 .nr_gpio = 8,
388 .nr_uart = 2,
389};
390
391static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
392{
393 switch (reg >> SC16IS7XX_REG_SHIFT) {
394 case SC16IS7XX_RHR_REG:
395 case SC16IS7XX_IIR_REG:
396 case SC16IS7XX_LSR_REG:
397 case SC16IS7XX_MSR_REG:
398 case SC16IS7XX_TXLVL_REG:
399 case SC16IS7XX_RXLVL_REG:
400 case SC16IS7XX_IOSTATE_REG:
401 return true;
402 default:
403 break;
404 }
405
406 return false;
407}
408
409static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
410{
411 switch (reg >> SC16IS7XX_REG_SHIFT) {
412 case SC16IS7XX_RHR_REG:
413 return true;
414 default:
415 break;
416 }
417
418 return false;
419}
420
421static int sc16is7xx_set_baud(struct uart_port *port, int baud)
422{
423 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
424 u8 lcr;
425 u8 prescaler = 0;
426 unsigned long clk = port->uartclk, div = clk / 16 / baud;
427
428 if (div > 0xffff) {
429 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
430 div /= 4;
431 }
432
433 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
434
435 /* Open the LCR divisors for configuration */
436 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
437 SC16IS7XX_LCR_CONF_MODE_B);
438
439 /* Enable enhanced features */
440 regcache_cache_bypass(s->regmap, true);
441 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
442 SC16IS7XX_EFR_ENABLE_BIT);
443 regcache_cache_bypass(s->regmap, false);
444
445 /* Put LCR back to the normal mode */
446 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
447
448 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
449 SC16IS7XX_MCR_CLKSEL_BIT,
450 prescaler);
451
452 /* Open the LCR divisors for configuration */
453 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
454 SC16IS7XX_LCR_CONF_MODE_A);
455
456 /* Write the new divisor */
457 regcache_cache_bypass(s->regmap, true);
458 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
459 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
460 regcache_cache_bypass(s->regmap, false);
461
462 /* Put LCR back to the normal mode */
463 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
464
465 return DIV_ROUND_CLOSEST(clk / 16, div);
466}
467
468static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
469 unsigned int iir)
470{
471 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
472 unsigned int lsr = 0, ch, flag, bytes_read, i;
473 u8 buf[port->fifosize];
474 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
475
476 if (unlikely(rxlen >= port->fifosize)) {
477 dev_warn_ratelimited(port->dev,
478 "Port %i: Possible RX FIFO overrun: %d\n",
479 port->line, rxlen);
480 port->icount.buf_overrun++;
481 /* Ensure sanity of RX level */
482 rxlen = port->fifosize;
483 }
484
485 while (rxlen) {
486 /* Only read lsr if there are possible errors in FIFO */
487 if (read_lsr) {
488 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
489 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
490 read_lsr = false; /* No errors left in FIFO */
491 } else
492 lsr = 0;
493
494 if (read_lsr) {
495 buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
496 bytes_read = 1;
497 } else {
498 regcache_cache_bypass(s->regmap, true);
499 regmap_raw_read(s->regmap, SC16IS7XX_RHR_REG,
500 buf, rxlen);
501 regcache_cache_bypass(s->regmap, false);
502 bytes_read = rxlen;
503 }
504
505 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
506
507 port->icount.rx++;
508 flag = TTY_NORMAL;
509
510 if (unlikely(lsr)) {
511 if (lsr & SC16IS7XX_LSR_BI_BIT) {
512 port->icount.brk++;
513 if (uart_handle_break(port))
514 continue;
515 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
516 port->icount.parity++;
517 else if (lsr & SC16IS7XX_LSR_FE_BIT)
518 port->icount.frame++;
519 else if (lsr & SC16IS7XX_LSR_OE_BIT)
520 port->icount.overrun++;
521
522 lsr &= port->read_status_mask;
523 if (lsr & SC16IS7XX_LSR_BI_BIT)
524 flag = TTY_BREAK;
525 else if (lsr & SC16IS7XX_LSR_PE_BIT)
526 flag = TTY_PARITY;
527 else if (lsr & SC16IS7XX_LSR_FE_BIT)
528 flag = TTY_FRAME;
529 else if (lsr & SC16IS7XX_LSR_OE_BIT)
530 flag = TTY_OVERRUN;
531 }
532
533 for (i = 0; i < bytes_read; ++i) {
534 ch = buf[i];
535 if (uart_handle_sysrq_char(port, ch))
536 continue;
537
538 if (lsr & port->ignore_status_mask)
539 continue;
540
541 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
542 flag);
543 }
544 rxlen -= bytes_read;
545 }
546
547 tty_flip_buffer_push(&port->state->port);
548}
549
550static void sc16is7xx_handle_tx(struct uart_port *port)
551{
552 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
553 struct circ_buf *xmit = &port->state->xmit;
554 unsigned int txlen, to_send, i;
555 u8 buf[port->fifosize];
556
557 if (unlikely(port->x_char)) {
558 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
559 port->icount.tx++;
560 port->x_char = 0;
561 return;
562 }
563
564 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
565 return;
566
567 /* Get length of data pending in circular buffer */
568 to_send = uart_circ_chars_pending(xmit);
569 if (likely(to_send)) {
570 /* Limit to size of TX FIFO */
571 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
572 to_send = (to_send > txlen) ? txlen : to_send;
573
574 /* Add data to send */
575 port->icount.tx += to_send;
576
577 /* Convert to linear buffer */
578 for (i = 0; i < to_send; ++i) {
579 buf[i] = xmit->buf[xmit->tail];
580 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
581 }
582 regcache_cache_bypass(s->regmap, true);
583 regmap_raw_write(s->regmap, SC16IS7XX_THR_REG, buf, to_send);
584 regcache_cache_bypass(s->regmap, false);
585 }
586
587 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
588 uart_write_wakeup(port);
589}
590
591static void sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
592{
593 struct uart_port *port = &s->p[portno].port;
594
595 do {
596 unsigned int iir, msr, rxlen;
597
598 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
599 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
600 break;
601
602 iir &= SC16IS7XX_IIR_ID_MASK;
603
604 switch (iir) {
605 case SC16IS7XX_IIR_RDI_SRC:
606 case SC16IS7XX_IIR_RLSE_SRC:
607 case SC16IS7XX_IIR_RTOI_SRC:
608 case SC16IS7XX_IIR_XOFFI_SRC:
609 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
610 if (rxlen)
611 sc16is7xx_handle_rx(port, rxlen, iir);
612 break;
613
614 case SC16IS7XX_IIR_CTSRTS_SRC:
615 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
616 uart_handle_cts_change(port,
617 !!(msr & SC16IS7XX_MSR_CTS_BIT));
618 break;
619 case SC16IS7XX_IIR_THRI_SRC:
620 mutex_lock(&s->mutex);
621 sc16is7xx_handle_tx(port);
622 mutex_unlock(&s->mutex);
623 break;
624 default:
625 dev_err_ratelimited(port->dev,
626 "Port %i: Unexpected interrupt: %x",
627 port->line, iir);
628 break;
629 }
630 } while (1);
631}
632
633static irqreturn_t sc16is7xx_ist(int irq, void *dev_id)
634{
635 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
636 int i;
637
638 for (i = 0; i < s->uart.nr; ++i)
639 sc16is7xx_port_irq(s, i);
640
641 return IRQ_HANDLED;
642}
643
644static void sc16is7xx_wq_proc(struct work_struct *ws)
645{
646 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, tx_work);
647 struct sc16is7xx_port *s = dev_get_drvdata(one->port.dev);
648
649 mutex_lock(&s->mutex);
650 sc16is7xx_handle_tx(&one->port);
651 mutex_unlock(&s->mutex);
652}
653
654static void sc16is7xx_stop_tx(struct uart_port* port)
655{
656 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
657 struct circ_buf *xmit = &one->port.state->xmit;
658
659 /* handle rs485 */
660 if (one->rs485.flags & SER_RS485_ENABLED) {
661 /* do nothing if current tx not yet completed */
662 int lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
663 if (!(lsr & SC16IS7XX_LSR_TEMT_BIT))
664 return;
665
666 if (uart_circ_empty(xmit) &&
667 (one->rs485.delay_rts_after_send > 0))
668 mdelay(one->rs485.delay_rts_after_send);
669 }
670
671 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
672 SC16IS7XX_IER_THRI_BIT,
673 0);
674}
675
676static void sc16is7xx_stop_rx(struct uart_port* port)
677{
678 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
679
680 one->port.read_status_mask &= ~SC16IS7XX_LSR_DR_BIT;
681 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
682 SC16IS7XX_LSR_DR_BIT,
683 0);
684}
685
686static void sc16is7xx_start_tx(struct uart_port *port)
687{
688 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
689
690 /* handle rs485 */
691 if ((one->rs485.flags & SER_RS485_ENABLED) &&
692 (one->rs485.delay_rts_before_send > 0)) {
693 mdelay(one->rs485.delay_rts_before_send);
694 }
695
696 if (!work_pending(&one->tx_work))
697 schedule_work(&one->tx_work);
698}
699
700static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
701{
702 unsigned int lvl, lsr;
703
704 lvl = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
705 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
706
707 return ((lsr & SC16IS7XX_LSR_THRE_BIT) && !lvl) ? TIOCSER_TEMT : 0;
708}
709
710static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
711{
712 /* DCD and DSR are not wired and CTS/RTS is handled automatically
713 * so just indicate DSR and CAR asserted
714 */
715 return TIOCM_DSR | TIOCM_CAR;
716}
717
718static void sc16is7xx_md_proc(struct work_struct *ws)
719{
720 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, md_work);
721
722 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
723 SC16IS7XX_MCR_LOOP_BIT,
724 (one->port.mctrl & TIOCM_LOOP) ?
725 SC16IS7XX_MCR_LOOP_BIT : 0);
726}
727
728static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
729{
730 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
731
732 schedule_work(&one->md_work);
733}
734
735static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
736{
737 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
738 SC16IS7XX_LCR_TXBREAK_BIT,
739 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
740}
741
742static void sc16is7xx_set_termios(struct uart_port *port,
743 struct ktermios *termios,
744 struct ktermios *old)
745{
746 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
747 unsigned int lcr, flow = 0;
748 int baud;
749
750 /* Mask termios capabilities we don't support */
751 termios->c_cflag &= ~CMSPAR;
752
753 /* Word size */
754 switch (termios->c_cflag & CSIZE) {
755 case CS5:
756 lcr = SC16IS7XX_LCR_WORD_LEN_5;
757 break;
758 case CS6:
759 lcr = SC16IS7XX_LCR_WORD_LEN_6;
760 break;
761 case CS7:
762 lcr = SC16IS7XX_LCR_WORD_LEN_7;
763 break;
764 case CS8:
765 lcr = SC16IS7XX_LCR_WORD_LEN_8;
766 break;
767 default:
768 lcr = SC16IS7XX_LCR_WORD_LEN_8;
769 termios->c_cflag &= ~CSIZE;
770 termios->c_cflag |= CS8;
771 break;
772 }
773
774 /* Parity */
775 if (termios->c_cflag & PARENB) {
776 lcr |= SC16IS7XX_LCR_PARITY_BIT;
777 if (!(termios->c_cflag & PARODD))
778 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
779 }
780
781 /* Stop bits */
782 if (termios->c_cflag & CSTOPB)
783 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
784
785 /* Set read status mask */
786 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
787 if (termios->c_iflag & INPCK)
788 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
789 SC16IS7XX_LSR_FE_BIT;
790 if (termios->c_iflag & (BRKINT | PARMRK))
791 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
792
793 /* Set status ignore mask */
794 port->ignore_status_mask = 0;
795 if (termios->c_iflag & IGNBRK)
796 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
797 if (!(termios->c_cflag & CREAD))
798 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
799
800 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
801 SC16IS7XX_LCR_CONF_MODE_B);
802
803 /* Configure flow control */
804 regcache_cache_bypass(s->regmap, true);
805 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
806 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
807 if (termios->c_cflag & CRTSCTS)
808 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
809 SC16IS7XX_EFR_AUTORTS_BIT;
810 if (termios->c_iflag & IXON)
811 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
812 if (termios->c_iflag & IXOFF)
813 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
814
815 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
816 regcache_cache_bypass(s->regmap, false);
817
818 /* Update LCR register */
819 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
820
821 /* Get baud rate generator configuration */
822 baud = uart_get_baud_rate(port, termios, old,
823 port->uartclk / 16 / 4 / 0xffff,
824 port->uartclk / 16);
825
826 /* Setup baudrate generator */
827 baud = sc16is7xx_set_baud(port, baud);
828
829 /* Update timeout according to new baud rate */
830 uart_update_timeout(port, termios->c_cflag, baud);
831}
832
833#if defined(TIOCSRS485) && defined(TIOCGRS485)
834static void sc16is7xx_config_rs485(struct uart_port *port,
835 struct serial_rs485 *rs485)
836{
837 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
838
839 one->rs485 = *rs485;
840
841 if (one->rs485.flags & SER_RS485_ENABLED) {
842 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
843 SC16IS7XX_EFCR_AUTO_RS485_BIT,
844 SC16IS7XX_EFCR_AUTO_RS485_BIT);
845 } else {
846 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
847 SC16IS7XX_EFCR_AUTO_RS485_BIT,
848 0);
849 }
850}
851#endif
852
853static int sc16is7xx_ioctl(struct uart_port *port, unsigned int cmd,
854 unsigned long arg)
855{
856#if defined(TIOCSRS485) && defined(TIOCGRS485)
857 struct serial_rs485 rs485;
858
859 switch (cmd) {
860 case TIOCSRS485:
861 if (copy_from_user(&rs485, (void __user *)arg, sizeof(rs485)))
862 return -EFAULT;
863
864 sc16is7xx_config_rs485(port, &rs485);
865 return 0;
866 case TIOCGRS485:
867 if (copy_to_user((void __user *)arg,
868 &(to_sc16is7xx_one(port, port)->rs485),
869 sizeof(rs485)))
870 return -EFAULT;
871 return 0;
872 default:
873 break;
874 }
875#endif
876
877 return -ENOIOCTLCMD;
878}
879
880static int sc16is7xx_startup(struct uart_port *port)
881{
882 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
883 unsigned int val;
884
885 sc16is7xx_power(port, 1);
886
887 /* Reset FIFOs*/
888 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
889 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
890 udelay(5);
891 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
892 SC16IS7XX_FCR_FIFO_BIT);
893
894 /* Enable EFR */
895 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
896 SC16IS7XX_LCR_CONF_MODE_B);
897
898 regcache_cache_bypass(s->regmap, true);
899
900 /* Enable write access to enhanced features and internal clock div */
901 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
902 SC16IS7XX_EFR_ENABLE_BIT);
903
904 /* Enable TCR/TLR */
905 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
906 SC16IS7XX_MCR_TCRTLR_BIT,
907 SC16IS7XX_MCR_TCRTLR_BIT);
908
909 /* Configure flow control levels */
910 /* Flow control halt level 48, resume level 24 */
911 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
912 SC16IS7XX_TCR_RX_RESUME(24) |
913 SC16IS7XX_TCR_RX_HALT(48));
914
915 regcache_cache_bypass(s->regmap, false);
916
917 /* Now, initialize the UART */
918 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
919
920 /* Enable the Rx and Tx FIFO */
921 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
922 SC16IS7XX_EFCR_RXDISABLE_BIT |
923 SC16IS7XX_EFCR_TXDISABLE_BIT,
924 0);
925
926 /* Enable RX, TX, CTS change interrupts */
927 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT |
928 SC16IS7XX_IER_CTSI_BIT;
929 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
930
931 return 0;
932}
933
934static void sc16is7xx_shutdown(struct uart_port *port)
935{
936 /* Disable all interrupts */
937 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
938 /* Disable TX/RX */
939 sc16is7xx_port_write(port, SC16IS7XX_EFCR_REG,
940 SC16IS7XX_EFCR_RXDISABLE_BIT |
941 SC16IS7XX_EFCR_TXDISABLE_BIT);
942
943 sc16is7xx_power(port, 0);
944}
945
946static const char *sc16is7xx_type(struct uart_port *port)
947{
948 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
949
950 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
951}
952
953static int sc16is7xx_request_port(struct uart_port *port)
954{
955 /* Do nothing */
956 return 0;
957}
958
959static void sc16is7xx_config_port(struct uart_port *port, int flags)
960{
961 if (flags & UART_CONFIG_TYPE)
962 port->type = PORT_SC16IS7XX;
963}
964
965static int sc16is7xx_verify_port(struct uart_port *port,
966 struct serial_struct *s)
967{
968 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
969 return -EINVAL;
970 if (s->irq != port->irq)
971 return -EINVAL;
972
973 return 0;
974}
975
976static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
977 unsigned int oldstate)
978{
979 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
980}
981
982static void sc16is7xx_null_void(struct uart_port *port)
983{
984 /* Do nothing */
985}
986
987static const struct uart_ops sc16is7xx_ops = {
988 .tx_empty = sc16is7xx_tx_empty,
989 .set_mctrl = sc16is7xx_set_mctrl,
990 .get_mctrl = sc16is7xx_get_mctrl,
991 .stop_tx = sc16is7xx_stop_tx,
992 .start_tx = sc16is7xx_start_tx,
993 .stop_rx = sc16is7xx_stop_rx,
994 .enable_ms = sc16is7xx_null_void,
995 .break_ctl = sc16is7xx_break_ctl,
996 .startup = sc16is7xx_startup,
997 .shutdown = sc16is7xx_shutdown,
998 .set_termios = sc16is7xx_set_termios,
999 .type = sc16is7xx_type,
1000 .request_port = sc16is7xx_request_port,
1001 .release_port = sc16is7xx_null_void,
1002 .config_port = sc16is7xx_config_port,
1003 .verify_port = sc16is7xx_verify_port,
1004 .ioctl = sc16is7xx_ioctl,
1005 .pm = sc16is7xx_pm,
1006};
1007
1008#ifdef CONFIG_GPIOLIB
1009static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1010{
1011 unsigned int val;
1012 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1013 gpio);
1014 struct uart_port *port = &s->p[0].port;
1015
1016 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1017
1018 return !!(val & BIT(offset));
1019}
1020
1021static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1022{
1023 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1024 gpio);
1025 struct uart_port *port = &s->p[0].port;
1026
1027 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1028 val ? BIT(offset) : 0);
1029}
1030
1031static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1032 unsigned offset)
1033{
1034 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1035 gpio);
1036 struct uart_port *port = &s->p[0].port;
1037
1038 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1039
1040 return 0;
1041}
1042
1043static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1044 unsigned offset, int val)
1045{
1046 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1047 gpio);
1048 struct uart_port *port = &s->p[0].port;
1049
1050 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1051 val ? BIT(offset) : 0);
1052 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1053 BIT(offset));
1054
1055 return 0;
1056}
1057#endif
1058
1059static int sc16is7xx_probe(struct device *dev,
1060 struct sc16is7xx_devtype *devtype,
1061 struct regmap *regmap, int irq, unsigned long flags)
1062{
1063 unsigned long freq, *pfreq = dev_get_platdata(dev);
1064 struct clk *clk;
1065 int i, ret;
1066 struct sc16is7xx_port *s;
1067
1068 if (IS_ERR(regmap))
1069 return PTR_ERR(regmap);
1070
1071 /* Alloc port structure */
1072 s = devm_kzalloc(dev, sizeof(*s) +
1073 sizeof(struct sc16is7xx_one) * devtype->nr_uart,
1074 GFP_KERNEL);
1075 if (!s) {
1076 dev_err(dev, "Error allocating port structure\n");
1077 return -ENOMEM;
1078 }
1079
1080 clk = devm_clk_get(dev, NULL);
1081 if (IS_ERR(clk)) {
1082 if (pfreq)
1083 freq = *pfreq;
1084 else
1085 return PTR_ERR(clk);
1086 } else {
1087 freq = clk_get_rate(clk);
1088 }
1089
1090 s->regmap = regmap;
1091 s->devtype = devtype;
1092 dev_set_drvdata(dev, s);
1093
1094 /* Register UART driver */
1095 s->uart.owner = THIS_MODULE;
1096 s->uart.dev_name = "ttySC";
1097 s->uart.nr = devtype->nr_uart;
1098 ret = uart_register_driver(&s->uart);
1099 if (ret) {
1100 dev_err(dev, "Registering UART driver failed\n");
1101 goto out_clk;
1102 }
1103
1104#ifdef CONFIG_GPIOLIB
1105 if (devtype->nr_gpio) {
1106 /* Setup GPIO cotroller */
1107 s->gpio.owner = THIS_MODULE;
1108 s->gpio.dev = dev;
1109 s->gpio.label = dev_name(dev);
1110 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1111 s->gpio.get = sc16is7xx_gpio_get;
1112 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1113 s->gpio.set = sc16is7xx_gpio_set;
1114 s->gpio.base = -1;
1115 s->gpio.ngpio = devtype->nr_gpio;
1116 s->gpio.can_sleep = 1;
1117 ret = gpiochip_add(&s->gpio);
1118 if (ret)
1119 goto out_uart;
1120 }
1121#endif
1122
1123 mutex_init(&s->mutex);
1124
1125 for (i = 0; i < devtype->nr_uart; ++i) {
1126 /* Initialize port data */
1127 s->p[i].port.line = i;
1128 s->p[i].port.dev = dev;
1129 s->p[i].port.irq = irq;
1130 s->p[i].port.type = PORT_SC16IS7XX;
1131 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1132 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1133 s->p[i].port.iotype = UPIO_PORT;
1134 s->p[i].port.uartclk = freq;
1135 s->p[i].port.ops = &sc16is7xx_ops;
1136 /* Disable all interrupts */
1137 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1138 /* Disable TX/RX */
1139 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1140 SC16IS7XX_EFCR_RXDISABLE_BIT |
1141 SC16IS7XX_EFCR_TXDISABLE_BIT);
1142 /* Initialize queue for start TX */
1143 INIT_WORK(&s->p[i].tx_work, sc16is7xx_wq_proc);
1144 /* Initialize queue for changing mode */
1145 INIT_WORK(&s->p[i].md_work, sc16is7xx_md_proc);
1146 /* Register port */
1147 uart_add_one_port(&s->uart, &s->p[i].port);
1148 /* Go to suspend mode */
1149 sc16is7xx_power(&s->p[i].port, 0);
1150 }
1151
1152 /* Setup interrupt */
1153 ret = devm_request_threaded_irq(dev, irq, NULL, sc16is7xx_ist,
1154 IRQF_ONESHOT | flags, dev_name(dev), s);
1155 if (!ret)
1156 return 0;
1157
1158 mutex_destroy(&s->mutex);
1159
1160#ifdef CONFIG_GPIOLIB
1161 if (devtype->nr_gpio)
1162 WARN_ON(gpiochip_remove(&s->gpio));
1163
1164out_uart:
1165#endif
1166 uart_unregister_driver(&s->uart);
1167
1168out_clk:
1169 if (!IS_ERR(s->clk))
1170 clk_disable_unprepare(s->clk);
1171
1172 return ret;
1173}
1174
1175static int sc16is7xx_remove(struct device *dev)
1176{
1177 struct sc16is7xx_port *s = dev_get_drvdata(dev);
1178 int i, ret = 0;
1179
1180#ifdef CONFIG_GPIOLIB
1181 if (s->devtype->nr_gpio) {
1182 ret = gpiochip_remove(&s->gpio);
1183 if (ret)
1184 return ret;
1185 }
1186#endif
1187
1188 for (i = 0; i < s->uart.nr; i++) {
1189 cancel_work_sync(&s->p[i].tx_work);
1190 cancel_work_sync(&s->p[i].md_work);
1191 uart_remove_one_port(&s->uart, &s->p[i].port);
1192 sc16is7xx_power(&s->p[i].port, 0);
1193 }
1194
1195 mutex_destroy(&s->mutex);
1196 uart_unregister_driver(&s->uart);
1197 if (!IS_ERR(s->clk))
1198 clk_disable_unprepare(s->clk);
1199
1200 return ret;
1201}
1202
1203static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1204 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1205 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1206 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1207 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1208 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1209 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1210 { }
1211};
1212MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1213
1214static struct regmap_config regcfg = {
1215 .reg_bits = 7,
1216 .pad_bits = 1,
1217 .val_bits = 8,
1218 .cache_type = REGCACHE_RBTREE,
1219 .volatile_reg = sc16is7xx_regmap_volatile,
1220 .precious_reg = sc16is7xx_regmap_precious,
1221};
1222
1223#ifdef CONFIG_REGMAP_I2C
1224static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1225 const struct i2c_device_id *id)
1226{
1227 struct sc16is7xx_devtype *devtype;
1228 unsigned long flags = 0;
1229 struct regmap *regmap;
1230
1231 if (i2c->dev.of_node) {
1232 const struct of_device_id *of_id =
1233 of_match_device(sc16is7xx_dt_ids, &i2c->dev);
1234
1235 devtype = (struct sc16is7xx_devtype *)of_id->data;
1236 } else {
1237 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1238 flags = IRQF_TRIGGER_FALLING;
1239 }
1240
1241 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1242 (devtype->nr_uart - 1);
1243 regmap = devm_regmap_init_i2c(i2c, &regcfg);
1244
1245 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags);
1246}
1247
1248static int sc16is7xx_i2c_remove(struct i2c_client *client)
1249{
1250 return sc16is7xx_remove(&client->dev);
1251}
1252
1253static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1254 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
1255 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1256 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1257 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1258 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1259 { }
1260};
1261MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1262
1263static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1264 .driver = {
1265 .name = SC16IS7XX_NAME,
1266 .owner = THIS_MODULE,
1267 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1268 },
1269 .probe = sc16is7xx_i2c_probe,
1270 .remove = sc16is7xx_i2c_remove,
1271 .id_table = sc16is7xx_i2c_id_table,
1272};
1273module_i2c_driver(sc16is7xx_i2c_uart_driver);
1274MODULE_ALIAS("i2c:sc16is7xx");
1275#endif
1276
1277MODULE_LICENSE("GPL");
1278MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1279MODULE_DESCRIPTION("SC16IS7XX serial driver");
Linux kernel - Deliverables
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