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sc16is7xx: save and use per-chip line number
[deliverable/linux.git] / drivers / tty / serial / sc16is7xx.c
CommitLineData
dfeae619
JR		 1/*
2 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
3 * Author: Jon Ringle <jringle@gridpoint.com>
4 *
5 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13
14#include <linux/bitops.h>
15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/gpio.h>
19#include <linux/i2c.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/regmap.h>
24#include <linux/serial_core.h>
25#include <linux/serial.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
2c837a8a 28#include <linux/spi/spi.h>
d952795d 29#include <linux/uaccess.h>
dfeae619
JR		 30
31#define SC16IS7XX_NAME "sc16is7xx"
32
33/* SC16IS7XX register definitions */
34#define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
35#define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
36#define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
37#define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
38#define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
39#define SC16IS7XX_LCR_REG (0x03) /* Line Control */
40#define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
41#define SC16IS7XX_LSR_REG (0x05) /* Line Status */
42#define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
43#define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
44#define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
45#define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
46#define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
47 * - only on 75x/76x
48 */
49#define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
50 * - only on 75x/76x
51 */
52#define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
53 * - only on 75x/76x
54 */
55#define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
56 * - only on 75x/76x
57 */
58#define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
59
60/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
61#define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
62#define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
63
64/* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
65#define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
66#define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
67
68/* Enhanced Register set: Only if (LCR == 0xBF) */
69#define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
70#define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
71#define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
72#define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
73#define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
74
75/* IER register bits */
76#define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
77#define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
78 * interrupt */
79#define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
80 * interrupt */
81#define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
82 * interrupt */
83
84/* IER register bits - write only if (EFR[4] == 1) */
85#define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
86#define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
87#define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
88#define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
89
90/* FCR register bits */
91#define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
92#define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
93#define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
94#define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
95#define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
96
97/* FCR register bits - write only if (EFR[4] == 1) */
98#define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
99#define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
100
101/* IIR register bits */
102#define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
103#define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
104#define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
105#define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
106#define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
107#define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
108#define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
109 * - only on 75x/76x
110 */
111#define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
112 * - only on 75x/76x
113 */
114#define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
115#define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
116 * from active (LOW)
117 * to inactive (HIGH)
118 */
119/* LCR register bits */
120#define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
121#define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
122 *
123 * Word length bits table:
124 * 00 -> 5 bit words
125 * 01 -> 6 bit words
126 * 10 -> 7 bit words
127 * 11 -> 8 bit words
128 */
129#define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
130 *
131 * STOP length bit table:
132 * 0 -> 1 stop bit
133 * 1 -> 1-1.5 stop bits if
134 * word length is 5,
135 * 2 stop bits otherwise
136 */
137#define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
138#define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
139#define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
140#define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
141#define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
142#define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
143#define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
144#define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
145#define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
146#define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
147 * reg set */
148#define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
149 * reg set */
150
151/* MCR register bits */
152#define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
153 * - only on 75x/76x
154 */
155#define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
156#define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
157#define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
158#define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
159 * - write enabled
160 * if (EFR[4] == 1)
161 */
162#define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
163 * - write enabled
164 * if (EFR[4] == 1)
165 */
166#define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
167 * - write enabled
168 * if (EFR[4] == 1)
169 */
170
171/* LSR register bits */
172#define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
173#define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
174#define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
175#define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
176#define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
177#define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
178#define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
179#define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
180#define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
181
182/* MSR register bits */
183#define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
184#define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
185 * or (IO4)
186 * - only on 75x/76x
187 */
188#define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
189 * or (IO7)
190 * - only on 75x/76x
191 */
192#define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
193 * or (IO6)
194 * - only on 75x/76x
195 */
196#define SC16IS7XX_MSR_CTS_BIT (1 << 0) /* CTS */
197#define SC16IS7XX_MSR_DSR_BIT (1 << 1) /* DSR (IO4)
198 * - only on 75x/76x
199 */
200#define SC16IS7XX_MSR_RI_BIT (1 << 2) /* RI (IO7)
201 * - only on 75x/76x
202 */
203#define SC16IS7XX_MSR_CD_BIT (1 << 3) /* CD (IO6)
204 * - only on 75x/76x
205 */
206#define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
207
208/*
209 * TCR register bits
210 * TCR trigger levels are available from 0 to 60 characters with a granularity
211 * of four.
212 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
213 * no built-in hardware check to make sure this condition is met. Also, the TCR
214 * must be programmed with this condition before auto RTS or software flow
215 * control is enabled to avoid spurious operation of the device.
216 */
217#define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
218#define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
219
220/*
221 * TLR register bits
222 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
223 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
224 * trigger levels. Trigger levels from 4 characters to 60 characters are
225 * available with a granularity of four.
226 *
227 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
228 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
229 * the trigger level defined in FCR is discarded. This applies to both transmit
230 * FIFO and receive FIFO trigger level setting.
231 *
232 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
233 * default state, that is, '00'.
234 */
235#define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
236#define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
237
238/* IOControl register bits (Only 750/760) */
239#define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
240#define SC16IS7XX_IOCONTROL_GPIO_BIT (1 << 1) /* Enable GPIO[7:4] */
241#define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
242
243/* EFCR register bits */
244#define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
245 * mode (RS485) */
246#define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
247#define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
248#define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
249#define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
250#define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
251 * 0 = rate upto 115.2 kbit/s
252 * - Only 750/760
253 * 1 = rate upto 1.152 Mbit/s
254 * - Only 760
255 */
256
257/* EFR register bits */
258#define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
259#define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
260#define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
261#define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
262 * and writing to IER[7:4],
263 * FCR[5:4], MCR[7:5]
264 */
265#define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
266#define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
267 *
268 * SWFLOW bits 3 & 2 table:
269 * 00 -> no transmitter flow
270 * control
271 * 01 -> transmitter generates
272 * XON2 and XOFF2
273 * 10 -> transmitter generates
274 * XON1 and XOFF1
275 * 11 -> transmitter generates
276 * XON1, XON2, XOFF1 and
277 * XOFF2
278 */
279#define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
280#define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
281 *
282 * SWFLOW bits 3 & 2 table:
283 * 00 -> no received flow
284 * control
285 * 01 -> receiver compares
286 * XON2 and XOFF2
287 * 10 -> receiver compares
288 * XON1 and XOFF1
289 * 11 -> receiver compares
290 * XON1, XON2, XOFF1 and
291 * XOFF2
292 */
293
294/* Misc definitions */
295#define SC16IS7XX_FIFO_SIZE (64)
296#define SC16IS7XX_REG_SHIFT 2
297
298struct sc16is7xx_devtype {
299 char name[10];
300 int nr_gpio;
301 int nr_uart;
302};
303
a0104085 304#define SC16IS7XX_RECONF_MD (1 << 0)
059d5815 305#define SC16IS7XX_RECONF_IER (1 << 1)
478d1051 306#define SC16IS7XX_RECONF_RS485 (1 << 2)
a0104085
JK		 307
308struct sc16is7xx_one_config {
309 unsigned int flags;
059d5815 310 u8 ier_clear;
a0104085
JK		 311};
312
dfeae619
JR		 313struct sc16is7xx_one {
314 struct uart_port port;
e92a886b 315 u8 line;
9e6f4ca3 316 struct kthread_work tx_work;
a0104085
JK		 317 struct kthread_work reg_work;
318 struct sc16is7xx_one_config config;
dfeae619
JR		 319};
320
321struct sc16is7xx_port {
322 struct uart_driver uart;
323 struct sc16is7xx_devtype *devtype;
324 struct regmap *regmap;
dfeae619
JR		 325 struct clk *clk;
326#ifdef CONFIG_GPIOLIB
327 struct gpio_chip gpio;
328#endif
beb04a9f 329 unsigned char buf[SC16IS7XX_FIFO_SIZE];
9e6f4ca3
JK		 330 struct kthread_worker kworker;
331 struct task_struct *kworker_task;
332 struct kthread_work irq_work;
dfeae619
JR		 333 struct sc16is7xx_one p[0];
334};
335
9e6f4ca3 336#define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e)))
dfeae619
JR		 337#define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
338
e92a886b
JK		 339static int sc16is7xx_line(struct uart_port *port)
340{
341 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
342
343 return one->line;
344}
345
dfeae619
JR		 346static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
347{
348 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
349 unsigned int val = 0;
e92a886b 350 const u8 line = sc16is7xx_line(port);
dfeae619 351
e92a886b 352 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val);
dfeae619
JR		 353
354 return val;
355}
356
357static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
358{
359 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
e92a886b 360 const u8 line = sc16is7xx_line(port);
dfeae619 361
e92a886b 362 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val);
dfeae619
JR		 363}
364
dec273ec
BS		 365static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen)
366{
367 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
e92a886b
JK		 368 const u8 line = sc16is7xx_line(port);
369 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line;
dec273ec
BS		 370
371 regcache_cache_bypass(s->regmap, true);
372 regmap_raw_read(s->regmap, addr, s->buf, rxlen);
373 regcache_cache_bypass(s->regmap, false);
374}
375
376static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send)
377{
378 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
e92a886b
JK		 379 const u8 line = sc16is7xx_line(port);
380 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line;
dec273ec
BS		 381
382 regcache_cache_bypass(s->regmap, true);
383 regmap_raw_write(s->regmap, addr, s->buf, to_send);
384 regcache_cache_bypass(s->regmap, false);
385}
386
dfeae619
JR		 387static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
388 u8 mask, u8 val)
389{
390 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
e92a886b 391 const u8 line = sc16is7xx_line(port);
dfeae619 392
e92a886b 393 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line,
dfeae619
JR		 394 mask, val);
395}
396
397
398static void sc16is7xx_power(struct uart_port *port, int on)
399{
400 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
401 SC16IS7XX_IER_SLEEP_BIT,
402 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
403}
404
405static const struct sc16is7xx_devtype sc16is74x_devtype = {
406 .name = "SC16IS74X",
407 .nr_gpio = 0,
408 .nr_uart = 1,
409};
410
411static const struct sc16is7xx_devtype sc16is750_devtype = {
412 .name = "SC16IS750",
413 .nr_gpio = 8,
414 .nr_uart = 1,
415};
416
417static const struct sc16is7xx_devtype sc16is752_devtype = {
418 .name = "SC16IS752",
419 .nr_gpio = 8,
420 .nr_uart = 2,
421};
422
423static const struct sc16is7xx_devtype sc16is760_devtype = {
424 .name = "SC16IS760",
425 .nr_gpio = 8,
426 .nr_uart = 1,
427};
428
429static const struct sc16is7xx_devtype sc16is762_devtype = {
430 .name = "SC16IS762",
431 .nr_gpio = 8,
432 .nr_uart = 2,
433};
434
435static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
436{
437 switch (reg >> SC16IS7XX_REG_SHIFT) {
438 case SC16IS7XX_RHR_REG:
439 case SC16IS7XX_IIR_REG:
440 case SC16IS7XX_LSR_REG:
441 case SC16IS7XX_MSR_REG:
442 case SC16IS7XX_TXLVL_REG:
443 case SC16IS7XX_RXLVL_REG:
444 case SC16IS7XX_IOSTATE_REG:
445 return true;
446 default:
447 break;
448 }
449
450 return false;
451}
452
453static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
454{
455 switch (reg >> SC16IS7XX_REG_SHIFT) {
456 case SC16IS7XX_RHR_REG:
457 return true;
458 default:
459 break;
460 }
461
462 return false;
463}
464
465static int sc16is7xx_set_baud(struct uart_port *port, int baud)
466{
467 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
468 u8 lcr;
469 u8 prescaler = 0;
470 unsigned long clk = port->uartclk, div = clk / 16 / baud;
471
472 if (div > 0xffff) {
473 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
474 div /= 4;
475 }
476
477 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
478
479 /* Open the LCR divisors for configuration */
480 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
481 SC16IS7XX_LCR_CONF_MODE_B);
482
483 /* Enable enhanced features */
484 regcache_cache_bypass(s->regmap, true);
485 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
486 SC16IS7XX_EFR_ENABLE_BIT);
487 regcache_cache_bypass(s->regmap, false);
488
489 /* Put LCR back to the normal mode */
490 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
491
492 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
493 SC16IS7XX_MCR_CLKSEL_BIT,
494 prescaler);
495
496 /* Open the LCR divisors for configuration */
497 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
498 SC16IS7XX_LCR_CONF_MODE_A);
499
500 /* Write the new divisor */
501 regcache_cache_bypass(s->regmap, true);
502 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
503 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
504 regcache_cache_bypass(s->regmap, false);
505
506 /* Put LCR back to the normal mode */
507 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
508
509 return DIV_ROUND_CLOSEST(clk / 16, div);
510}
511
512static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
513 unsigned int iir)
514{
515 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
516 unsigned int lsr = 0, ch, flag, bytes_read, i;
dfeae619
JR		 517 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
518
beb04a9f 519 if (unlikely(rxlen >= sizeof(s->buf))) {
dfeae619 520 dev_warn_ratelimited(port->dev,
e92a886b 521 "ttySC%i: Possible RX FIFO overrun: %d\n",
dfeae619
JR		 522 port->line, rxlen);
523 port->icount.buf_overrun++;
524 /* Ensure sanity of RX level */
beb04a9f 525 rxlen = sizeof(s->buf);
dfeae619
JR		 526 }
527
528 while (rxlen) {
529 /* Only read lsr if there are possible errors in FIFO */
530 if (read_lsr) {
531 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
532 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
533 read_lsr = false; /* No errors left in FIFO */
534 } else
535 lsr = 0;
536
537 if (read_lsr) {
beb04a9f 538 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
dfeae619
JR		 539 bytes_read = 1;
540 } else {
dec273ec 541 sc16is7xx_fifo_read(port, rxlen);
dfeae619
JR		 542 bytes_read = rxlen;
543 }
544
545 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
546
547 port->icount.rx++;
548 flag = TTY_NORMAL;
549
550 if (unlikely(lsr)) {
551 if (lsr & SC16IS7XX_LSR_BI_BIT) {
552 port->icount.brk++;
553 if (uart_handle_break(port))
554 continue;
555 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
556 port->icount.parity++;
557 else if (lsr & SC16IS7XX_LSR_FE_BIT)
558 port->icount.frame++;
559 else if (lsr & SC16IS7XX_LSR_OE_BIT)
560 port->icount.overrun++;
561
562 lsr &= port->read_status_mask;
563 if (lsr & SC16IS7XX_LSR_BI_BIT)
564 flag = TTY_BREAK;
565 else if (lsr & SC16IS7XX_LSR_PE_BIT)
566 flag = TTY_PARITY;
567 else if (lsr & SC16IS7XX_LSR_FE_BIT)
568 flag = TTY_FRAME;
569 else if (lsr & SC16IS7XX_LSR_OE_BIT)
570 flag = TTY_OVERRUN;
571 }
572
573 for (i = 0; i < bytes_read; ++i) {
beb04a9f 574 ch = s->buf[i];
dfeae619
JR		 575 if (uart_handle_sysrq_char(port, ch))
576 continue;
577
578 if (lsr & port->ignore_status_mask)
579 continue;
580
581 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
582 flag);
583 }
584 rxlen -= bytes_read;
585 }
586
587 tty_flip_buffer_push(&port->state->port);
588}
589
590static void sc16is7xx_handle_tx(struct uart_port *port)
591{
592 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
593 struct circ_buf *xmit = &port->state->xmit;
594 unsigned int txlen, to_send, i;
dfeae619
JR		 595
596 if (unlikely(port->x_char)) {
597 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
598 port->icount.tx++;
599 port->x_char = 0;
600 return;
601 }
602
603 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
604 return;
605
606 /* Get length of data pending in circular buffer */
607 to_send = uart_circ_chars_pending(xmit);
608 if (likely(to_send)) {
609 /* Limit to size of TX FIFO */
610 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
611 to_send = (to_send > txlen) ? txlen : to_send;
612
613 /* Add data to send */
614 port->icount.tx += to_send;
615
616 /* Convert to linear buffer */
617 for (i = 0; i < to_send; ++i) {
beb04a9f 618 s->buf[i] = xmit->buf[xmit->tail];
dfeae619
JR		 619 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
620 }
dec273ec
BS		 621
622 sc16is7xx_fifo_write(port, to_send);
dfeae619
JR		 623 }
624
625 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
626 uart_write_wakeup(port);
627}
628
629static void sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
630{
631 struct uart_port *port = &s->p[portno].port;
632
633 do {
634 unsigned int iir, msr, rxlen;
635
636 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
637 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
638 break;
639
640 iir &= SC16IS7XX_IIR_ID_MASK;
641
642 switch (iir) {
643 case SC16IS7XX_IIR_RDI_SRC:
644 case SC16IS7XX_IIR_RLSE_SRC:
645 case SC16IS7XX_IIR_RTOI_SRC:
646 case SC16IS7XX_IIR_XOFFI_SRC:
647 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
648 if (rxlen)
649 sc16is7xx_handle_rx(port, rxlen, iir);
650 break;
651
652 case SC16IS7XX_IIR_CTSRTS_SRC:
653 msr = sc16is7xx_port_read(port, SC16IS7XX_MSR_REG);
654 uart_handle_cts_change(port,
655 !!(msr & SC16IS7XX_MSR_CTS_BIT));
656 break;
657 case SC16IS7XX_IIR_THRI_SRC:
dfeae619 658 sc16is7xx_handle_tx(port);
dfeae619
JR		 659 break;
660 default:
661 dev_err_ratelimited(port->dev,
e92a886b 662 "ttySC%i: Unexpected interrupt: %x",
dfeae619
JR		 663 port->line, iir);
664 break;
665 }
666 } while (1);
667}
668
9e6f4ca3 669static void sc16is7xx_ist(struct kthread_work *ws)
dfeae619 670{
9e6f4ca3 671 struct sc16is7xx_port *s = to_sc16is7xx_port(ws, irq_work);
dfeae619
JR		 672 int i;
673
674 for (i = 0; i < s->uart.nr; ++i)
675 sc16is7xx_port_irq(s, i);
9e6f4ca3
JK		 676}
677
678static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
679{
680 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
681
682 queue_kthread_work(&s->kworker, &s->irq_work);
dfeae619
JR		 683
684 return IRQ_HANDLED;
685}
686
9e6f4ca3 687static void sc16is7xx_tx_proc(struct kthread_work *ws)
dfeae619 688{
dbe5a40c 689 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
dfeae619 690
dbe5a40c
JK		 691 if ((port->rs485.flags & SER_RS485_ENABLED) &&
692 (port->rs485.delay_rts_before_send > 0))
693 msleep(port->rs485.delay_rts_before_send);
694
695 sc16is7xx_handle_tx(port);
dfeae619
JR		 696}
697
478d1051
JK		 698static void sc16is7xx_reconf_rs485(struct uart_port *port)
699{
700 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
701 SC16IS7XX_EFCR_RTS_INVERT_BIT;
702 u32 efcr = 0;
703 struct serial_rs485 *rs485 = &port->rs485;
704 unsigned long irqflags;
705
706 spin_lock_irqsave(&port->lock, irqflags);
707 if (rs485->flags & SER_RS485_ENABLED) {
708 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
709
710 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
711 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
712 }
713 spin_unlock_irqrestore(&port->lock, irqflags);
714
715 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
716}
717
a0104085
JK		 718static void sc16is7xx_reg_proc(struct kthread_work *ws)
719{
720 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
721 struct sc16is7xx_one_config config;
722 unsigned long irqflags;
723
724 spin_lock_irqsave(&one->port.lock, irqflags);
725 config = one->config;
726 memset(&one->config, 0, sizeof(one->config));
727 spin_unlock_irqrestore(&one->port.lock, irqflags);
728
729 if (config.flags & SC16IS7XX_RECONF_MD)
730 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
731 SC16IS7XX_MCR_LOOP_BIT,
732 (one->port.mctrl & TIOCM_LOOP) ?
733 SC16IS7XX_MCR_LOOP_BIT : 0);
059d5815
JK		 734
735 if (config.flags & SC16IS7XX_RECONF_IER)
736 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
737 config.ier_clear, 0);
478d1051
JK		 738
739 if (config.flags & SC16IS7XX_RECONF_RS485)
740 sc16is7xx_reconf_rs485(&one->port);
a0104085
JK		 741}
742
059d5815 743static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
dfeae619 744{
059d5815
JK		 745 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
746 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
747
748 one->config.flags |= SC16IS7XX_RECONF_IER;
749 one->config.ier_clear |= bit;
750 queue_kthread_work(&s->kworker, &one->reg_work);
dfeae619
JR		 751}
752
059d5815 753static void sc16is7xx_stop_tx(struct uart_port *port)
dfeae619 754{
059d5815
JK		 755 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
756}
dfeae619 757
059d5815
JK		 758static void sc16is7xx_stop_rx(struct uart_port *port)
759{
760 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
dfeae619
JR		 761}
762
763static void sc16is7xx_start_tx(struct uart_port *port)
764{
9e6f4ca3 765 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
dfeae619
JR		 766 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
767
9e6f4ca3 768 queue_kthread_work(&s->kworker, &one->tx_work);
dfeae619
JR		 769}
770
771static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
772{
4ae82e5d 773 unsigned int lsr;
dfeae619 774
dfeae619
JR		 775 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
776
4ae82e5d 777 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
dfeae619
JR		 778}
779
780static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
781{
782 /* DCD and DSR are not wired and CTS/RTS is handled automatically
783 * so just indicate DSR and CAR asserted
784 */
785 return TIOCM_DSR | TIOCM_CAR;
786}
787
dfeae619
JR		 788static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
789{
a0104085 790 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
dfeae619
JR		 791 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
792
a0104085
JK		 793 one->config.flags |= SC16IS7XX_RECONF_MD;
794 queue_kthread_work(&s->kworker, &one->reg_work);
dfeae619
JR		 795}
796
797static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
798{
799 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
800 SC16IS7XX_LCR_TXBREAK_BIT,
801 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
802}
803
804static void sc16is7xx_set_termios(struct uart_port *port,
805 struct ktermios *termios,
806 struct ktermios *old)
807{
808 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
809 unsigned int lcr, flow = 0;
810 int baud;
811
812 /* Mask termios capabilities we don't support */
813 termios->c_cflag &= ~CMSPAR;
814
815 /* Word size */
816 switch (termios->c_cflag & CSIZE) {
817 case CS5:
818 lcr = SC16IS7XX_LCR_WORD_LEN_5;
819 break;
820 case CS6:
821 lcr = SC16IS7XX_LCR_WORD_LEN_6;
822 break;
823 case CS7:
824 lcr = SC16IS7XX_LCR_WORD_LEN_7;
825 break;
826 case CS8:
827 lcr = SC16IS7XX_LCR_WORD_LEN_8;
828 break;
829 default:
830 lcr = SC16IS7XX_LCR_WORD_LEN_8;
831 termios->c_cflag &= ~CSIZE;
832 termios->c_cflag |= CS8;
833 break;
834 }
835
836 /* Parity */
837 if (termios->c_cflag & PARENB) {
838 lcr |= SC16IS7XX_LCR_PARITY_BIT;
839 if (!(termios->c_cflag & PARODD))
840 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
841 }
842
843 /* Stop bits */
844 if (termios->c_cflag & CSTOPB)
845 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
846
847 /* Set read status mask */
848 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
849 if (termios->c_iflag & INPCK)
850 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
851 SC16IS7XX_LSR_FE_BIT;
852 if (termios->c_iflag & (BRKINT | PARMRK))
853 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
854
855 /* Set status ignore mask */
856 port->ignore_status_mask = 0;
857 if (termios->c_iflag & IGNBRK)
858 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
859 if (!(termios->c_cflag & CREAD))
860 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
861
862 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
863 SC16IS7XX_LCR_CONF_MODE_B);
864
865 /* Configure flow control */
866 regcache_cache_bypass(s->regmap, true);
867 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
868 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
869 if (termios->c_cflag & CRTSCTS)
870 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
871 SC16IS7XX_EFR_AUTORTS_BIT;
872 if (termios->c_iflag & IXON)
873 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
874 if (termios->c_iflag & IXOFF)
875 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
876
877 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
878 regcache_cache_bypass(s->regmap, false);
879
880 /* Update LCR register */
881 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
882
883 /* Get baud rate generator configuration */
884 baud = uart_get_baud_rate(port, termios, old,
885 port->uartclk / 16 / 4 / 0xffff,
886 port->uartclk / 16);
887
888 /* Setup baudrate generator */
889 baud = sc16is7xx_set_baud(port, baud);
890
891 /* Update timeout according to new baud rate */
892 uart_update_timeout(port, termios->c_cflag, baud);
893}
894
b57d15fe 895static int sc16is7xx_config_rs485(struct uart_port *port,
f0e38115 896 struct serial_rs485 *rs485)
dfeae619 897{
478d1051
JK		 898 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
899 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
f0e38115
JK		 900
901 if (rs485->flags & SER_RS485_ENABLED) {
902 bool rts_during_rx, rts_during_tx;
903
904 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
905 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
906
478d1051 907 if (rts_during_rx == rts_during_tx)
f0e38115
JK		 908 dev_err(port->dev,
909 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
910 rts_during_tx, rts_during_rx);
5451bb29
JK		 911
912 /*
913 * RTS signal is handled by HW, it's timing can't be influenced.
914 * However, it's sometimes useful to delay TX even without RTS
915 * control therefore we try to handle .delay_rts_before_send.
916 */
917 if (rs485->delay_rts_after_send)
918 return -EINVAL;
f0e38115
JK		 919 }
920
b57d15fe 921 port->rs485 = *rs485;
478d1051
JK		 922 one->config.flags |= SC16IS7XX_RECONF_RS485;
923 queue_kthread_work(&s->kworker, &one->reg_work);
dfeae619 924
b57d15fe 925 return 0;
dfeae619
JR		 926}
927
928static int sc16is7xx_startup(struct uart_port *port)
929{
930 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
931 unsigned int val;
932
933 sc16is7xx_power(port, 1);
934
935 /* Reset FIFOs*/
936 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
937 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
938 udelay(5);
939 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
940 SC16IS7XX_FCR_FIFO_BIT);
941
942 /* Enable EFR */
943 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
944 SC16IS7XX_LCR_CONF_MODE_B);
945
946 regcache_cache_bypass(s->regmap, true);
947
948 /* Enable write access to enhanced features and internal clock div */
949 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
950 SC16IS7XX_EFR_ENABLE_BIT);
951
952 /* Enable TCR/TLR */
953 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
954 SC16IS7XX_MCR_TCRTLR_BIT,
955 SC16IS7XX_MCR_TCRTLR_BIT);
956
957 /* Configure flow control levels */
958 /* Flow control halt level 48, resume level 24 */
959 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
960 SC16IS7XX_TCR_RX_RESUME(24) |
961 SC16IS7XX_TCR_RX_HALT(48));
962
963 regcache_cache_bypass(s->regmap, false);
964
965 /* Now, initialize the UART */
966 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
967
968 /* Enable the Rx and Tx FIFO */
969 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
970 SC16IS7XX_EFCR_RXDISABLE_BIT |
971 SC16IS7XX_EFCR_TXDISABLE_BIT,
972 0);
973
974 /* Enable RX, TX, CTS change interrupts */
975 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT |
976 SC16IS7XX_IER_CTSI_BIT;
977 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
978
979 return 0;
980}
981
982static void sc16is7xx_shutdown(struct uart_port *port)
983{
9e6f4ca3
JK		 984 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
985
dfeae619
JR		 986 /* Disable all interrupts */
987 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
988 /* Disable TX/RX */
9764e7a0
JK		 989 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
990 SC16IS7XX_EFCR_RXDISABLE_BIT |
991 SC16IS7XX_EFCR_TXDISABLE_BIT,
992 SC16IS7XX_EFCR_RXDISABLE_BIT |
993 SC16IS7XX_EFCR_TXDISABLE_BIT);
dfeae619
JR		 994
995 sc16is7xx_power(port, 0);
9e6f4ca3
JK		 996
997 flush_kthread_worker(&s->kworker);
dfeae619
JR		 998}
999
1000static const char *sc16is7xx_type(struct uart_port *port)
1001{
1002 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1003
1004 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1005}
1006
1007static int sc16is7xx_request_port(struct uart_port *port)
1008{
1009 /* Do nothing */
1010 return 0;
1011}
1012
1013static void sc16is7xx_config_port(struct uart_port *port, int flags)
1014{
1015 if (flags & UART_CONFIG_TYPE)
1016 port->type = PORT_SC16IS7XX;
1017}
1018
1019static int sc16is7xx_verify_port(struct uart_port *port,
1020 struct serial_struct *s)
1021{
1022 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1023 return -EINVAL;
1024 if (s->irq != port->irq)
1025 return -EINVAL;
1026
1027 return 0;
1028}
1029
1030static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1031 unsigned int oldstate)
1032{
1033 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1034}
1035
1036static void sc16is7xx_null_void(struct uart_port *port)
1037{
1038 /* Do nothing */
1039}
1040
1041static const struct uart_ops sc16is7xx_ops = {
1042 .tx_empty = sc16is7xx_tx_empty,
1043 .set_mctrl = sc16is7xx_set_mctrl,
1044 .get_mctrl = sc16is7xx_get_mctrl,
1045 .stop_tx = sc16is7xx_stop_tx,
1046 .start_tx = sc16is7xx_start_tx,
1047 .stop_rx = sc16is7xx_stop_rx,
dfeae619
JR		 1048 .break_ctl = sc16is7xx_break_ctl,
1049 .startup = sc16is7xx_startup,
1050 .shutdown = sc16is7xx_shutdown,
1051 .set_termios = sc16is7xx_set_termios,
1052 .type = sc16is7xx_type,
1053 .request_port = sc16is7xx_request_port,
1054 .release_port = sc16is7xx_null_void,
1055 .config_port = sc16is7xx_config_port,
1056 .verify_port = sc16is7xx_verify_port,
dfeae619
JR		 1057 .pm = sc16is7xx_pm,
1058};
1059
1060#ifdef CONFIG_GPIOLIB
1061static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1062{
1063 unsigned int val;
1064 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1065 gpio);
1066 struct uart_port *port = &s->p[0].port;
1067
1068 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1069
1070 return !!(val & BIT(offset));
1071}
1072
1073static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1074{
1075 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1076 gpio);
1077 struct uart_port *port = &s->p[0].port;
1078
1079 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1080 val ? BIT(offset) : 0);
1081}
1082
1083static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1084 unsigned offset)
1085{
1086 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1087 gpio);
1088 struct uart_port *port = &s->p[0].port;
1089
1090 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1091
1092 return 0;
1093}
1094
1095static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1096 unsigned offset, int val)
1097{
1098 struct sc16is7xx_port *s = container_of(chip, struct sc16is7xx_port,
1099 gpio);
1100 struct uart_port *port = &s->p[0].port;
1101
1102 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1103 val ? BIT(offset) : 0);
1104 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1105 BIT(offset));
1106
1107 return 0;
1108}
1109#endif
1110
1111static int sc16is7xx_probe(struct device *dev,
1112 struct sc16is7xx_devtype *devtype,
1113 struct regmap *regmap, int irq, unsigned long flags)
1114{
9e6f4ca3 1115 struct sched_param sched_param = { .sched_priority = MAX_RT_PRIO / 2 };
dfeae619 1116 unsigned long freq, *pfreq = dev_get_platdata(dev);
dfeae619
JR		 1117 int i, ret;
1118 struct sc16is7xx_port *s;
1119
1120 if (IS_ERR(regmap))
1121 return PTR_ERR(regmap);
1122
1123 /* Alloc port structure */
1124 s = devm_kzalloc(dev, sizeof(*s) +
1125 sizeof(struct sc16is7xx_one) * devtype->nr_uart,
1126 GFP_KERNEL);
1127 if (!s) {
1128 dev_err(dev, "Error allocating port structure\n");
1129 return -ENOMEM;
1130 }
1131
dc824ebe
JR		 1132 s->clk = devm_clk_get(dev, NULL);
1133 if (IS_ERR(s->clk)) {
dfeae619
JR		 1134 if (pfreq)
1135 freq = *pfreq;
1136 else
dc824ebe 1137 return PTR_ERR(s->clk);
dfeae619 1138 } else {
0814e8d5 1139 clk_prepare_enable(s->clk);
dc824ebe 1140 freq = clk_get_rate(s->clk);
dfeae619
JR		 1141 }
1142
1143 s->regmap = regmap;
1144 s->devtype = devtype;
1145 dev_set_drvdata(dev, s);
1146
1147 /* Register UART driver */
1148 s->uart.owner = THIS_MODULE;
1149 s->uart.dev_name = "ttySC";
1150 s->uart.nr = devtype->nr_uart;
1151 ret = uart_register_driver(&s->uart);
1152 if (ret) {
1153 dev_err(dev, "Registering UART driver failed\n");
1154 goto out_clk;
1155 }
1156
9e6f4ca3
JK		 1157 init_kthread_worker(&s->kworker);
1158 init_kthread_work(&s->irq_work, sc16is7xx_ist);
1159 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1160 "sc16is7xx");
1161 if (IS_ERR(s->kworker_task)) {
1162 ret = PTR_ERR(s->kworker_task);
1163 goto out_uart;
1164 }
1165 sched_setscheduler(s->kworker_task, SCHED_FIFO, &sched_param);
1166
dfeae619
JR		 1167#ifdef CONFIG_GPIOLIB
1168 if (devtype->nr_gpio) {
1169 /* Setup GPIO cotroller */
1170 s->gpio.owner = THIS_MODULE;
1171 s->gpio.dev = dev;
1172 s->gpio.label = dev_name(dev);
1173 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1174 s->gpio.get = sc16is7xx_gpio_get;
1175 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1176 s->gpio.set = sc16is7xx_gpio_set;
1177 s->gpio.base = -1;
1178 s->gpio.ngpio = devtype->nr_gpio;
1179 s->gpio.can_sleep = 1;
1180 ret = gpiochip_add(&s->gpio);
1181 if (ret)
9e6f4ca3 1182 goto out_thread;
dfeae619
JR		 1183 }
1184#endif
1185
dfeae619 1186 for (i = 0; i < devtype->nr_uart; ++i) {
e92a886b 1187 s->p[i].line = i;
dfeae619
JR		 1188 /* Initialize port data */
1189 s->p[i].port.line = i;
1190 s->p[i].port.dev = dev;
1191 s->p[i].port.irq = irq;
1192 s->p[i].port.type = PORT_SC16IS7XX;
1193 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1194 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1195 s->p[i].port.iotype = UPIO_PORT;
1196 s->p[i].port.uartclk = freq;
b57d15fe 1197 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
dfeae619
JR		 1198 s->p[i].port.ops = &sc16is7xx_ops;
1199 /* Disable all interrupts */
1200 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1201 /* Disable TX/RX */
1202 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1203 SC16IS7XX_EFCR_RXDISABLE_BIT |
1204 SC16IS7XX_EFCR_TXDISABLE_BIT);
a0104085 1205 /* Initialize kthread work structs */
9e6f4ca3 1206 init_kthread_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
a0104085 1207 init_kthread_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
dfeae619
JR		 1208 /* Register port */
1209 uart_add_one_port(&s->uart, &s->p[i].port);
1210 /* Go to suspend mode */
1211 sc16is7xx_power(&s->p[i].port, 0);
1212 }
1213
1214 /* Setup interrupt */
9e6f4ca3
JK		 1215 ret = devm_request_irq(dev, irq, sc16is7xx_irq,
1216 IRQF_ONESHOT | flags, dev_name(dev), s);
dfeae619
JR		 1217 if (!ret)
1218 return 0;
1219
11b03ea0
JK		 1220 for (i = 0; i < s->uart.nr; i++)
1221 uart_remove_one_port(&s->uart, &s->p[i].port);
1222
dfeae619
JR		 1223#ifdef CONFIG_GPIOLIB
1224 if (devtype->nr_gpio)
e27e2786 1225 gpiochip_remove(&s->gpio);
dfeae619 1226
9e6f4ca3 1227out_thread:
dfeae619 1228#endif
9e6f4ca3
JK		 1229 kthread_stop(s->kworker_task);
1230
1231out_uart:
dfeae619
JR		 1232 uart_unregister_driver(&s->uart);
1233
1234out_clk:
1235 if (!IS_ERR(s->clk))
1236 clk_disable_unprepare(s->clk);
1237
1238 return ret;
1239}
1240
1241static int sc16is7xx_remove(struct device *dev)
1242{
1243 struct sc16is7xx_port *s = dev_get_drvdata(dev);
e27e2786 1244 int i;
dfeae619
JR		 1245
1246#ifdef CONFIG_GPIOLIB
e27e2786
LW		 1247 if (s->devtype->nr_gpio)
1248 gpiochip_remove(&s->gpio);
dfeae619
JR		 1249#endif
1250
1251 for (i = 0; i < s->uart.nr; i++) {
dfeae619
JR		 1252 uart_remove_one_port(&s->uart, &s->p[i].port);
1253 sc16is7xx_power(&s->p[i].port, 0);
1254 }
1255
9e6f4ca3
JK		 1256 flush_kthread_worker(&s->kworker);
1257 kthread_stop(s->kworker_task);
1258
dfeae619
JR		 1259 uart_unregister_driver(&s->uart);
1260 if (!IS_ERR(s->clk))
1261 clk_disable_unprepare(s->clk);
1262
e27e2786 1263 return 0;
dfeae619
JR		 1264}
1265
1266static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1267 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1268 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1269 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1270 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1271 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1272 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1273 { }
1274};
1275MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1276
1277static struct regmap_config regcfg = {
1278 .reg_bits = 7,
1279 .pad_bits = 1,
1280 .val_bits = 8,
1281 .cache_type = REGCACHE_RBTREE,
1282 .volatile_reg = sc16is7xx_regmap_volatile,
1283 .precious_reg = sc16is7xx_regmap_precious,
1284};
1285
2c837a8a
RKKI		 1286#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1287static int sc16is7xx_spi_probe(struct spi_device *spi)
1288{
1289 struct sc16is7xx_devtype *devtype;
1290 unsigned long flags = 0;
1291 struct regmap *regmap;
1292 int ret;
1293
1294 /* Setup SPI bus */
1295 spi->bits_per_word = 8;
1296 /* only supports mode 0 on SC16IS762 */
1297 spi->mode = spi->mode ? : SPI_MODE_0;
1298 spi->max_speed_hz = spi->max_speed_hz ? : 15000000;
1299 ret = spi_setup(spi);
1300 if (ret)
1301 return ret;
1302
1303 if (spi->dev.of_node) {
1304 const struct of_device_id *of_id =
1305 of_match_device(sc16is7xx_dt_ids, &spi->dev);
1306
1307 devtype = (struct sc16is7xx_devtype *)of_id->data;
1308 } else {
1309 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1310
1311 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1312 flags = IRQF_TRIGGER_FALLING;
1313 }
1314
1315 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1316 (devtype->nr_uart - 1);
1317 regmap = devm_regmap_init_spi(spi, &regcfg);
1318
1319 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq, flags);
1320}
1321
1322static int sc16is7xx_spi_remove(struct spi_device *spi)
1323{
1324 return sc16is7xx_remove(&spi->dev);
1325}
1326
1327static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1328 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
4117a60c
JK		 1329 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1330 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
2c837a8a
RKKI		 1331 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1332 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1333 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1334 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1335 { }
1336};
1337
1338MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1339
1340static struct spi_driver sc16is7xx_spi_uart_driver = {
1341 .driver = {
1342 .name = SC16IS7XX_NAME,
1343 .owner = THIS_MODULE,
1344 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1345 },
1346 .probe = sc16is7xx_spi_probe,
1347 .remove = sc16is7xx_spi_remove,
1348 .id_table = sc16is7xx_spi_id_table,
1349};
1350
1351MODULE_ALIAS("spi:sc16is7xx");
1352#endif
1353
1354#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
dfeae619
JR		 1355static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1356 const struct i2c_device_id *id)
1357{
1358 struct sc16is7xx_devtype *devtype;
1359 unsigned long flags = 0;
1360 struct regmap *regmap;
1361
1362 if (i2c->dev.of_node) {
1363 const struct of_device_id *of_id =
1364 of_match_device(sc16is7xx_dt_ids, &i2c->dev);
1365
1366 devtype = (struct sc16is7xx_devtype *)of_id->data;
1367 } else {
1368 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1369 flags = IRQF_TRIGGER_FALLING;
1370 }
1371
1372 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1373 (devtype->nr_uart - 1);
1374 regmap = devm_regmap_init_i2c(i2c, &regcfg);
1375
1376 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags);
1377}
1378
1379static int sc16is7xx_i2c_remove(struct i2c_client *client)
1380{
1381 return sc16is7xx_remove(&client->dev);
1382}
1383
1384static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1385 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
4117a60c
JK		 1386 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1387 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
dfeae619
JR		 1388 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1389 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1390 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1391 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1392 { }
1393};
1394MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1395
1396static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1397 .driver = {
1398 .name = SC16IS7XX_NAME,
dfeae619
JR		 1399 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1400 },
1401 .probe = sc16is7xx_i2c_probe,
1402 .remove = sc16is7xx_i2c_remove,
1403 .id_table = sc16is7xx_i2c_id_table,
1404};
2c837a8a 1405
dfeae619 1406MODULE_ALIAS("i2c:sc16is7xx");
2c837a8a
RKKI		 1407#endif
1408
1409static int __init sc16is7xx_init(void)
1410{
1411 int ret = 0;
1412#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1413 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1414 if (ret < 0) {
1415 pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1416 return ret;
1417 }
1418#endif
1419
1420#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1421 ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1422 if (ret < 0) {
1423 pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1424 return ret;
1425 }
1426#endif
1427 return ret;
1428}
1429module_init(sc16is7xx_init);
1430
1431static void __exit sc16is7xx_exit(void)
1432{
1433#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1434 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1435#endif
1436
1437#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1438 spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1439#endif
1440}
1441module_exit(sc16is7xx_exit);
dfeae619
JR		 1442
1443MODULE_LICENSE("GPL");
1444MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1445MODULE_DESCRIPTION("SC16IS7XX serial driver");
Linux kernel - Deliverables
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